diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 76ffdee..3c1846a 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -89,7 +89,7 @@
           virtualenv -p /usr/bin/python3 /tmp/venvhtml
           . /tmp/venvhtml/bin/activate
           pip install -r doc/sphinx/requirements.txt
-          make htmldocs
+          make htmldocs KDOC_WERROR=1
           make infodocs
 
   - job: todo
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index b193fee..e6c6ab3 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -171,7 +171,7 @@
     - virtualenv -p /usr/bin/python3 /tmp/venvhtml
     - . /tmp/venvhtml/bin/activate
     - pip install -r doc/sphinx/requirements.txt
-    - make htmldocs
+    - make htmldocs KDOC_WERROR=1
     - make infodocs
 
 # some statistics about the code base
diff --git a/Kconfig b/Kconfig
index f24e4f0..a372378 100644
--- a/Kconfig
+++ b/Kconfig
@@ -175,6 +175,8 @@
 
 config XEN
 	bool "Select U-Boot be run as a bootloader for XEN Virtual Machine"
+	depends on ARM64
+	select SSCANF
 	help
 	  Enabling this option will make U-Boot be run as a bootloader
 	  for XEN [1] Virtual Machine.
@@ -435,7 +437,7 @@
 	default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
 	default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
 	default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
-				ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
+				RISCV || ARCH_ZYNQMP)
 	default "u-boot.kwb" if (ARCH_KIRKWOOD || ARMADA_32BIT) && !SPL
 	help
 	  Some SoCs need special image types (e.g. U-Boot binary
diff --git a/MAINTAINERS b/MAINTAINERS
index 02a5a86..e9ed6ac 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -291,6 +291,7 @@
 F:	arch/arm/cpu/armv8/hisilicon
 F:	arch/arm/include/asm/arch-hi6220/
 F:	arch/arm/include/asm/arch-hi3660/
+F:	arch/arm/mach-histb
 
 ARM HPE GXP ARCHITECTURE
 M:	Jean-Marie Verdun <verdun@hpe.com>
@@ -1204,6 +1205,14 @@
 F:	include/nvme.h
 F:	doc/develop/driver-model/nvme.rst
 
+NVMXIP
+M:	Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+S:	Maintained
+F:	doc/develop/driver-model/nvmxip.rst
+F:	doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt
+F:	drivers/mtd/nvmxip/
+F:	test/dm/nvmxip.c
+
 NVMEM
 M:	Sean Anderson <seanga2@gmail.com>
 S:	Maintained
@@ -1353,6 +1362,7 @@
 F:	doc/arch/sandbox.rst
 F:	drivers/*/*sandbox*.c
 F:	include/dt-bindings/*/sandbox*.h
+F:	include/os.h
 
 SEAMA
 M:	Linus Walleij <linus.walleij@linaro.org>
@@ -1484,18 +1494,16 @@
 F:	configs/k2l_hs_evm_defconfig
 F:	configs/am65x_hs_evm_r5_defconfig
 F:	configs/am65x_hs_evm_a53_defconfig
-F:	configs/j7200_hs_evm_a72_defconfig
-F:	configs/j7200_hs_evm_r5_defconfig
 F:	configs/j721e_hs_evm_a72_defconfig
 F:	configs/j721e_hs_evm_r5_defconfig
-F:	configs/j721s2_hs_evm_a72_defconfig
-F:	configs/j721s2_hs_evm_r5_defconfig
 
 TPM DRIVERS
 M:	Ilias Apalodimas <ilias.apalodimas@linaro.org>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-tpm.git
+F:	cmd/tpm*
 F:	drivers/tpm/
+F:	include/tpm*
 
 TQ GROUP
 #M:	Martin Krause <martin.krause@tq-systems.de>
diff --git a/Makefile b/Makefile
index eaaf7d2..4f4f014 100644
--- a/Makefile
+++ b/Makefile
@@ -1,9 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 VERSION = 2023
-PATCHLEVEL = 04
+PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
 NAME =
 
 # *DOCUMENTATION*
@@ -437,6 +437,7 @@
 ifeq ($(cc-name),clang)
 ifneq ($(CROSS_COMPILE),)
 CLANG_TARGET	:= --target=$(notdir $(CROSS_COMPILE:%-=%))
+LDPPFLAGS	+= $(CLANG_TARGET)
 GCC_TOOLCHAIN_DIR := $(dir $(shell which $(LD)))
 CLANG_PREFIX	:= --prefix=$(GCC_TOOLCHAIN_DIR)
 GCC_TOOLCHAIN	:= $(realpath $(GCC_TOOLCHAIN_DIR)/..)
@@ -893,8 +894,10 @@
 ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y)
 PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a
 else
+ifndef CONFIG_CC_IS_CLANG
 PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`) -lgcc
 endif
+endif
 PLATFORM_LIBS += $(PLATFORM_LIBGCC)
 
 ifdef CONFIG_CC_COVERAGE
diff --git a/api/Kconfig b/api/Kconfig
index 6072288..b5a7399 100644
--- a/api/Kconfig
+++ b/api/Kconfig
@@ -1,13 +1,14 @@
-menu "API"
-
 config API
 	bool "Enable U-Boot API"
+	depends on CC_IS_GCC
 	help
 	  This option enables the U-Boot API. See api/README for more information.
 
+menu "API"
+	depends on API
+
 config SYS_MMC_MAX_DEVICE
 	int  "Maximum number of MMC devices exposed via the API"
-	depends on API
 	default 1
 
 config EXAMPLES
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f0118e2..99264a6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -12,7 +12,7 @@
 
 config ARM64_CRC32
 	bool "Enable support for CRC32 instruction"
-	depends on ARM64
+	depends on ARM64 && CC_IS_GCC
 	default y
 	help
 	  ARMv8 implements dedicated crc32 instruction for crc32 calculation.
@@ -357,7 +357,7 @@
 
 choice
 	prompt "Select the ARM data write cache policy"
-	default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1
+	default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || TARGET_BCMNS || RZA1
 	default SYS_ARM_CACHE_WRITEBACK
 
 config SYS_ARM_CACHE_WRITEBACK
@@ -578,6 +578,16 @@
 	help
 	  Support for TI's DaVinci platform.
 
+config ARCH_HISTB
+	bool "Hisilicon HiSTB SoCs"
+	select DM
+	select DM_SERIAL
+	select OF_CONTROL
+	select PL01X_SERIAL
+	imply CMD_DM
+	help
+	  Support for HiSTB SoCs.
+
 config ARCH_KIRKWOOD
 	bool "Marvell Kirkwood"
 	select ARCH_MISC_INIT
@@ -671,6 +681,25 @@
 	imply HASH_VERIFY
 	imply NETDEVICES
 
+config TARGET_BCMNS
+	bool "Support Broadcom Northstar"
+	select CPU_V7A
+	select DM
+	select DM_GPIO
+	select DM_SERIAL
+	select OF_CONTROL
+	select TIMER
+	select SYS_NS16550
+	select ARM_GLOBAL_TIMER
+	imply SYS_THUMB_BUILD
+	imply MTD_RAW_NAND
+	imply NAND_BRCMNAND
+	imply NAND_BRCMNAND_IPROC
+	help
+	  Support for Broadcom Northstar SoCs. NS is a dual-core 32-bit
+	  ARMv7 Cortex-A9 SoC family including BCM4708, BCM47094,
+	  BCM5301x etc.
+
 config TARGET_BCMNS2
 	bool "Support Broadcom Northstar2"
 	select ARM64
@@ -1956,8 +1985,7 @@
 	imply ADC
 	imply CMD_DM
 	imply DEBUG_UART_BOARD_INIT
-	imply DISTRO_DEFAULTS if !ROCKCHIP_RK3399
-	imply BOOTSTD_DEFAULTS if !DISTRO_DEFAULTS
+	imply BOOTSTD_DEFAULTS
 	imply FAT_WRITE
 	imply SARADC_ROCKCHIP
 	imply SPL_SYSRESET
@@ -2044,7 +2072,6 @@
 	select OF_CONTROL
 	select LINUX_KERNEL_IMAGE_HEADER
 	select XEN_SERIAL
-	select SSCANF
 	imply OF_HAS_PRIOR_STAGE
 
 config ARCH_GXP
@@ -2157,6 +2184,8 @@
 
 source "arch/arm/mach-highbank/Kconfig"
 
+source "arch/arm/mach-histb/Kconfig"
+
 source "arch/arm/mach-integrator/Kconfig"
 
 source "arch/arm/mach-ipq40xx/Kconfig"
@@ -2268,6 +2297,7 @@
 source "board/armltd/vexpress/Kconfig"
 source "board/armltd/vexpress64/Kconfig"
 source "board/cortina/presidio-asic/Kconfig"
+source "board/broadcom/bcmns/Kconfig"
 source "board/broadcom/bcmns3/Kconfig"
 source "board/cavium/thunderx/Kconfig"
 source "board/eets/pdu001/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ac602ae..5ebe061 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -61,6 +61,7 @@
 machine-$(CONFIG_ARCH_EXYNOS)		+= exynos
 machine-$(CONFIG_ARCH_GXP)		+= hpe
 machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
+machine-$(CONFIG_ARCH_HISTB)		+= histb
 machine-$(CONFIG_ARCH_IPQ40XX)		+= ipq40xx
 machine-$(CONFIG_ARCH_K3)		+= k3
 machine-$(CONFIG_ARCH_KEYSTONE)		+= keystone
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index bf781f1..5530d02 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -3,7 +3,13 @@
 # (C) Copyright 2000-2002
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
-CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \
+ifeq ($(CONFIG_ARM64),y)
+FIXED_REG := -ffixed-x18
+else
+FIXED_REG := -ffixed-r9
+endif
+
+CFLAGS_NON_EFI := -fno-pic $(FIXED_REG) -ffunction-sections -fdata-sections \
 		  -fstack-protector-strong
 CFLAGS_EFI := -fpic -fshort-wchar
 
@@ -15,7 +21,7 @@
 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
 endif
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r9
+PLATFORM_RELFLAGS += -fno-common $(FIXED_REG)
 PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
 		     $(call cc-option,-mgeneral-regs-only) \
       $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 7d7aac0..69e281b 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -134,8 +134,8 @@
  */
 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
-	mcr     p15, 0, r0, c7, c10, 4	@ DSB
-	mcr     p15, 0, r0, c7, c5, 4	@ ISB
+	dsb
+	isb
 #endif
 
 	bx	lr
@@ -188,8 +188,8 @@
 	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
 	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
 	mcr	p15, 0, r0, c7, c5, 6	@ invalidate BP array
-	mcr     p15, 0, r0, c7, c10, 4	@ DSB
-	mcr     p15, 0, r0, c7, c5, 4	@ ISB
+	dsb
+	isb
 
 	/*
 	 * disable MMU stuff and caches
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 6973340..cb1131a 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -93,10 +93,16 @@
 
 	if (el == 1) {
 		tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
+		if (gd->arch.has_hafdbs)
+			tcr |= TCR_EL1_HA | TCR_EL1_HD;
 	} else if (el == 2) {
 		tcr = TCR_EL2_RSVD | (ips << 16);
+		if (gd->arch.has_hafdbs)
+			tcr |= TCR_EL2_HA | TCR_EL2_HD;
 	} else {
 		tcr = TCR_EL3_RSVD | (ips << 16);
+		if (gd->arch.has_hafdbs)
+			tcr |= TCR_EL3_HA | TCR_EL3_HD;
 	}
 
 	/* PTWs cacheable, inner/outer WBWA and inner shareable */
@@ -200,6 +206,9 @@
 		    attrs != PTE_BLOCK_MEMTYPE(MT_NORMAL_NC))
 			continue;
 
+		if (gd->arch.has_hafdbs && (pte & (PTE_RDONLY | PTE_DBM)) != PTE_DBM)
+			continue;
+
 		end = va + BIT(level2shift(level)) - 1;
 
 		/* No intersection with RAM? */
@@ -309,7 +318,7 @@
 	for (i = idx; size; i++) {
 		u64 next_size, *next_table;
 
-		if (level >= 1 &&
+		if (level >= gd->arch.first_block_level &&
 		    size >= map_size && !(virt & (map_size - 1))) {
 			if (level == 3)
 				table[i] = phys | attrs | PTE_TYPE_PAGE;
@@ -348,6 +357,12 @@
 	if (va_bits < 39)
 		level = 1;
 
+	if (!gd->arch.first_block_level)
+		gd->arch.first_block_level = 1;
+
+	if (gd->arch.has_hafdbs)
+		attrs |= PTE_DBM | PTE_RDONLY;
+
 	map_range(map->virt, map->phys, map->size, level,
 		  (u64 *)gd->arch.tlb_addr, attrs);
 }
@@ -361,7 +376,7 @@
 	for (i = idx; size; i++) {
 		u64 next_size;
 
-		if (level >= 1 &&
+		if (level >= gd->arch.first_block_level &&
 		    size >= map_size && !(virt & (map_size - 1))) {
 			virt += map_size;
 			size -= map_size;
@@ -399,7 +414,16 @@
 __weak u64 get_page_table_size(void)
 {
 	u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
-	u64 size;
+	u64 size, mmfr1;
+
+	asm volatile("mrs %0, id_aa64mmfr1_el1" : "=r" (mmfr1));
+	if ((mmfr1 & 0xf) == 2) {
+		gd->arch.has_hafdbs = true;
+		gd->arch.first_block_level = 2;
+	} else {
+		gd->arch.has_hafdbs = false;
+		gd->arch.first_block_level = 1;
+	}
 
 	/* Account for all page tables we would need to cover our memory map */
 	size = one_pt * count_ranges();
diff --git a/arch/arm/cpu/armv8/config.mk b/arch/arm/cpu/armv8/config.mk
index ca06ed3..4d74b2a 100644
--- a/arch/arm/cpu/armv8/config.mk
+++ b/arch/arm/cpu/armv8/config.mk
@@ -2,7 +2,6 @@
 #
 # (C) Copyright 2002
 # Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-PLATFORM_RELFLAGS += -fno-common -ffixed-x18
 PLATFORM_RELFLAGS += $(call cc-option,-mbranch-protection=none)
 
 PF_NO_UNALIGNED := $(call cc-option, -mstrict-align)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 4f91db4..22ce699 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -387,6 +387,10 @@
 	u64 jr_offset, used_jr;
 	fdt32_t *reg;
 
+	/* Return if crypto node not found */
+	if (crypto_node < 0)
+		return;
+
 	used_jr = sec_firmware_used_jobring_offset();
 	fdt_support_default_count_cells(blob, crypto_node, &addr_cells, NULL);
 
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3385948..935b2f1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -961,6 +961,7 @@
 	fsl-imx8qm-apalis.dtb \
 	fsl-imx8qm-mek.dtb \
 	imx8qm-cgtqmx8.dtb \
+	imx8qm-dmsse20-a1.dtb \
 	imx8qm-rom7720-a1.dtb \
 	fsl-imx8qxp-ai_ml.dtb \
 	fsl-imx8qxp-colibri.dtb \
@@ -1142,9 +1143,6 @@
 	omap4-sdp.dtb \
 	omap4-sdp-es23plus.dtb
 
-dtb-$(CONFIG_TARGET_OMAP5_UEVM) += \
-	omap5-uevm.dtb
-
 dtb-$(CONFIG_TARGET_SAMA7G5EK) += \
 	at91-sama7g5ek.dtb
 
@@ -1200,6 +1198,8 @@
 	bcm2837-rpi-cm3-io3.dtb \
 	bcm2711-rpi-4-b.dtb
 
+dtb-$(CONFIG_TARGET_BCMNS) += ns-board.dtb
+
 dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
 
 dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
@@ -1308,6 +1308,8 @@
 	mt7981-rfb.dtb \
 	mt7981-emmc-rfb.dtb \
 	mt7981-sd-rfb.dtb \
+	mt7986a-bpi-r3-sd.dtb \
+	mt7986a-bpi-r3-emmc.dtb \
 	mt7986a-rfb.dtb \
 	mt7986b-rfb.dtb \
 	mt7986a-sd-rfb.dtb \
diff --git a/arch/arm/dts/am335x-base0033.dts b/arch/arm/dts/am335x-base0033.dts
index 29782be..89c00ce 100644
--- a/arch/arm/dts/am335x-base0033.dts
+++ b/arch/arm/dts/am335x-base0033.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION
  *
  * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include "am335x-igep0033.dtsi"
@@ -46,39 +43,39 @@
 &am33xx_pinmux {
 	nxp_hdmi_pins: pinmux_nxp_hdmi_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3)	/* xdma_event_intr0.clkout1 */
-			AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)	/* lcd_data0 */
-			AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)	/* lcd_data1 */
-			AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)	/* lcd_data2 */
-			AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)	/* lcd_data3 */
-			AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)	/* lcd_data4 */
-			AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)	/* lcd_data5 */
-			AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)	/* lcd_data6 */
-			AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)	/* lcd_data7 */
-			AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)	/* lcd_data8 */
-			AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)	/* lcd_data9 */
-			AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)	/* lcd_data10 */
-			AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)	/* lcd_data11 */
-			AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)	/* lcd_data12 */
-			AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)	/* lcd_data13 */
-			AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)	/* lcd_data14 */
-			AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)	/* lcd_data15 */
-			AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)	/* lcd_vsync */
-			AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)	/* lcd_hsync */
-			AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)	/* lcd_pclk */
-			AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)	/* lcd_ac_bias_en */
+			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3)	/* xdma_event_intr0.clkout1 */
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
 		>;
 	};
 	nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3)	/* xdma_event_intr0.clkout1 */
+			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3)	/* xdma_event_intr0.clkout1 */
 		>;
 	};
 
 	leds_base_pins: pinmux_leds_base_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a5.gpio1_21 */
-			AM33XX_IOPAD(0x888, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_csn3.gpio2_0 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_a5.gpio1_21 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_csn3.gpio2_0 */
 		>;
 	};
 };
diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi
index 43fe03d..67dfcd8 100644
--- a/arch/arm/dts/am335x-bone-common.dtsi
+++ b/arch/arm/dts/am335x-bone-common.dtsi
@@ -371,7 +371,6 @@
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&davinci_mdio_default>;
 	pinctrl-1 = <&davinci_mdio_sleep>;
-	status = "okay";
 
 	ethphy0: ethernet-phy@0 {
 		reg = <0>;
diff --git a/arch/arm/dts/am335x-boneblack-hdmi.dtsi b/arch/arm/dts/am335x-boneblack-hdmi.dtsi
index 7cfddad..486f24d 100644
--- a/arch/arm/dts/am335x-boneblack-hdmi.dtsi
+++ b/arch/arm/dts/am335x-boneblack-hdmi.dtsi
@@ -85,8 +85,13 @@
 		audio-ports = <	TDA998x_I2S	0x03>;
 
 		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
 			port@0 {
-				hdmi_0: endpoint@0 {
+				reg = <0>;
+
+				hdmi_0: endpoint {
 					remote-endpoint = <&lcdc_0>;
 				};
 			};
diff --git a/arch/arm/dts/am335x-boneblack-wireless.dts b/arch/arm/dts/am335x-boneblack-wireless.dts
index 8b2b24c..afa4fdc 100644
--- a/arch/arm/dts/am335x-boneblack-wireless.dts
+++ b/arch/arm/dts/am335x-boneblack-wireless.dts
@@ -19,7 +19,7 @@
 		regulator-name = "wlan-en-regulator";
 		regulator-min-microvolt = <1800000>;
 		regulator-max-microvolt = <1800000>;
-		startup-delay-us= <70000>;
+		startup-delay-us = <70000>;
 
 		/* WL_EN */
 		gpio = <&gpio3 9 0>;
diff --git a/arch/arm/dts/am335x-boneblack.dts b/arch/arm/dts/am335x-boneblack.dts
index 9312197..b956e2f 100644
--- a/arch/arm/dts/am335x-boneblack.dts
+++ b/arch/arm/dts/am335x-boneblack.dts
@@ -168,3 +168,7 @@
 		"NC",
 		"NC";
 };
+
+&baseboard_eeprom {
+	vcc-supply = <&ldo4_reg>;
+};
diff --git a/arch/arm/dts/am335x-boneblue.dts b/arch/arm/dts/am335x-boneblue.dts
index 856fdf5..f04f46d 100644
--- a/arch/arm/dts/am335x-boneblue.dts
+++ b/arch/arm/dts/am335x-boneblue.dts
@@ -107,7 +107,7 @@
 		regulator-name = "wlan-en-regulator";
 		regulator-min-microvolt = <1800000>;
 		regulator-max-microvolt = <1800000>;
-		startup-delay-us= <70000>;
+		startup-delay-us = <70000>;
 
 		/* WL_EN */
 		gpio = <&gpio3 9 0>;
diff --git a/arch/arm/dts/am335x-bonegreen-wireless.dts b/arch/arm/dts/am335x-bonegreen-wireless.dts
index 74db0fc..b363d03 100644
--- a/arch/arm/dts/am335x-bonegreen-wireless.dts
+++ b/arch/arm/dts/am335x-bonegreen-wireless.dts
@@ -18,7 +18,7 @@
 		regulator-name = "wlan-en-regulator";
 		regulator-min-microvolt = <1800000>;
 		regulator-max-microvolt = <1800000>;
-		startup-delay-us= <70000>;
+		startup-delay-us = <70000>;
 
 		/* WL_EN */
 		gpio = <&gpio0 26 0>;
diff --git a/arch/arm/dts/am335x-chiliboard.dts b/arch/arm/dts/am335x-chiliboard.dts
index 9c2a947..129a02b 100644
--- a/arch/arm/dts/am335x-chiliboard.dts
+++ b/arch/arm/dts/am335x-chiliboard.dts
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
+ * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/
  * Author: Rostislav Lisovy <lisovy@jablotron.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 /dts-v1/;
 #include "am335x-chilisom.dtsi"
@@ -37,79 +34,79 @@
 &am33xx_pinmux {
 	uart0_pins: pinmux_uart0_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
-			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
+			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 		>;
 	};
 
 	cpsw_default: cpsw_default {
 		pinctrl-single,pins = <
 			/* Slave 1 */
-			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs */
-			AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1)	/* mii1_rxerr.rmii1_rxerr */
-			AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txen.rmii1_txen */
-			AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd1.rmii1_txd1 */
-			AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd0.rmii1_txd0 */
-			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1)	/* mii1_rxd1.rmii1_rxd1 */
-			AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1)	/* mii1_rxd0.rmii1_rxd0 */
-			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* rmii1_ref_clk.rmii_ref_clk */
+			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
 		>;
 	};
 
 	cpsw_sleep: cpsw_sleep {
 		pinctrl-single,pins = <
 			/* Slave 1 reset value */
-			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
 		>;
 	};
 
 	davinci_mdio_default: davinci_mdio_default {
 		pinctrl-single,pins = <
 			/* mdio_data.mdio_data */
-			AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
 			/* mdio_clk.mdio_clk */
-			AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 
 	davinci_mdio_sleep: davinci_mdio_sleep {
 		pinctrl-single,pins = <
 			/* MDIO reset value */
-			AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
 		>;
 	};
 
 	usb1_drvvbus: usb1_drvvbus {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */
+			AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 		>;
 	};
 
 	sd_pins: pinmux_sd_card {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
-			AM33XX_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
-			AM33XX_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
-			AM33XX_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
-			AM33XX_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
-			AM33XX_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
-			AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */
 		>;
 	};
 
 	led_gpio_pins: led_gpio_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x9e4, PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */
-			AM33XX_IOPAD(0x9e8, PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */
+			AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_OUTPUT, MUX_MODE7) /* emu0.gpio3_7 */
+			AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT, MUX_MODE7) /* emu1.gpio3_8 */
 		>;
 	};
 };
diff --git a/arch/arm/dts/am335x-chilisom.dtsi b/arch/arm/dts/am335x-chilisom.dtsi
index 1b43ebd..43b61e4 100644
--- a/arch/arm/dts/am335x-chilisom.dtsi
+++ b/arch/arm/dts/am335x-chilisom.dtsi
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
+ * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/
  * Author: Rostislav Lisovy <lisovy@jablotron.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 #include "am33xx.dtsi"
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -30,28 +27,28 @@
 
 	i2c0_pins: pinmux_i2c0_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
-			AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 
 	nandflash_pins: nandflash_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
-			AM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
-			AM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
-			AM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
-			AM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
-			AM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
-			AM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
-			AM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE0)
 
-			AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
-			AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_csn0.gpmc_csn0 */
-			AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_advn_ale.gpmc_advn_ale */
-			AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_oen_ren.gpmc_oen_ren */
-			AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_wen.gpmc_wen */
-			AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_be0n_cle.gpmc_be0n_cle */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 };
diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts
index 2a2972f..6e79962 100644
--- a/arch/arm/dts/am335x-evm.dts
+++ b/arch/arm/dts/am335x-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -25,12 +22,16 @@
 		};
 	};
 
-	memory {
+	memory@80000000 {
 		device_type = "memory";
 		reg = <0x80000000 0x10000000>; /* 256 MB */
 	};
 
-	vbat: fixedregulator@0 {
+	chosen {
+		stdout-path = &uart0;
+	};
+
+	vbat: fixedregulator0 {
 		compatible = "regulator-fixed";
 		regulator-name = "vbat";
 		regulator-min-microvolt = <5000000>;
@@ -38,13 +39,13 @@
 		regulator-boot-on;
 	};
 
-	lis3_reg: fixedregulator@1 {
+	lis3_reg: fixedregulator1 {
 		compatible = "regulator-fixed";
 		regulator-name = "lis3_reg";
 		regulator-boot-on;
 	};
 
-	wlan_en_reg: fixedregulator@2 {
+	wlan_en_reg: fixedregulator2 {
 		compatible = "regulator-fixed";
 		regulator-name = "wlan-en-regulator";
 		regulator-min-microvolt = <1800000>;
@@ -78,18 +79,18 @@
 				0x0201006c>;	/* DOWN */
 	};
 
-	gpio_keys: volume_keys@0 {
+	gpio_keys: volume-keys {
 		compatible = "gpio-keys";
 		autorepeat;
 
-		switch@9 {
+		switch-9 {
 			label = "volume-up";
 			linux,code = <115>;
 			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
 			gpio-key,wakeup;
 		};
 
-		switch@10 {
+		switch-10 {
 			label = "volume-down";
 			linux,code = <114>;
 			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
@@ -158,206 +159,206 @@
 
 	matrix_keypad_s0: matrix_keypad_s0 {
 		pinctrl-single,pins = <
-			0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a5.gpio1_21 */
-			0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a6.gpio1_22 */
-			0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a9.gpio1_25 */
-			0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a10.gpio1_26 */
-			0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a11.gpio1_27 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_a5.gpio1_21 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_a6.gpio1_22 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_a9.gpio1_25 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_a10.gpio1_26 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_a11.gpio1_27 */
 		>;
 	};
 
 	volume_keys_s0: volume_keys_s0 {
 		pinctrl-single,pins = <
-			0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* spi0_sclk.gpio0_2 */
-			0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* spi0_d0.gpio0_3 */
+			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* spi0_sclk.gpio0_2 */
+			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* spi0_d0.gpio0_3 */
 		>;
 	};
 
 	i2c0_pins: pinmux_i2c0_pins {
 		pinctrl-single,pins = <
-			0x188 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
-			0x18c (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)	/* i2c0_sda.i2c0_sda */
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)	/* i2c0_scl.i2c0_scl */
 		>;
 	};
 
 	i2c1_pins: pinmux_i2c1_pins {
 		pinctrl-single,pins = <
-			0x158 (PIN_INPUT_PULLUP | MUX_MODE2)	/* spi0_d1.i2c1_sda */
-			0x15c (PIN_INPUT_PULLUP | MUX_MODE2)	/* spi0_cs0.i2c1_scl */
+			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2)	/* spi0_d1.i2c1_sda */
+			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2)	/* spi0_cs0.i2c1_scl */
 		>;
 	};
 
 	uart0_pins: pinmux_uart0_pins {
 		pinctrl-single,pins = <
-			0x170 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
-			0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
+			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 		>;
 	};
 
 	uart1_pins: pinmux_uart1_pins {
 		pinctrl-single,pins = <
-			0x178 (PIN_INPUT | MUX_MODE0)		/* uart1_ctsn.uart1_ctsn */
-			0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart1_rtsn.uart1_rtsn */
-			0x180 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart1_rxd.uart1_rxd */
-			0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart1_txd.uart1_txd */
+			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 		>;
 	};
 
 	clkout2_pin: pinmux_clkout2_pin {
 		pinctrl-single,pins = <
-			0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	/* xdma_event_intr1.clkout2 */
+			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* xdma_event_intr1.clkout2 */
 		>;
 	};
 
 	nandflash_pins_s0: nandflash_pins_s0 {
 		pinctrl-single,pins = <
-			0x0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
-			0x4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
-			0x8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
-			0xc (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
-			0x10 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
-			0x14 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
-			0x18 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
-			0x1c (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
-			0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
-			0x74 (PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpio0_30 */
-			0x7c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
-			0x90 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
-			0x94 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
-			0x98 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
-			0x9c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)	/* gpmc_wpn.gpio0_31 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
 		>;
 	};
 
 	ecap0_pins: backlight_pins {
 		pinctrl-single,pins = <
-			0x164 0x0	/* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+			AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0)
 		>;
 	};
 
 	cpsw_default: cpsw_default {
 		pinctrl-single,pins = <
 			/* Slave 1 */
-			0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
-			0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
-			0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd3.rgmii1_td3 */
-			0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd2.rgmii1_td2 */
-			0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
-			0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
-			0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txclk.rgmii1_tclk */
-			0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxclk.rgmii1_rclk */
-			0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd3.rgmii1_rd3 */
-			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd2.rgmii1_rd2 */
-			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
-			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd3.rgmii1_td3 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd2.rgmii1_td2 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txclk.rgmii1_tclk */
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxclk.rgmii1_rclk */
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd3.rgmii1_rd3 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd2.rgmii1_rd2 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
 		>;
 	};
 
 	cpsw_sleep: cpsw_sleep {
 		pinctrl-single,pins = <
 			/* Slave 1 reset value */
-			0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 		>;
 	};
 
 	davinci_mdio_default: davinci_mdio_default {
 		pinctrl-single,pins = <
 			/* MDIO */
-			0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
-			0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 
 	davinci_mdio_sleep: davinci_mdio_sleep {
 		pinctrl-single,pins = <
 			/* MDIO reset value */
-			0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
 		>;
 	};
 
 	mmc1_pins: pinmux_mmc1_pins {
 		pinctrl-single,pins = <
-			0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)		/* spi0_cs1.gpio0_6 */
 		>;
 	};
 
 	mmc3_pins: pinmux_mmc3_pins {
 		pinctrl-single,pins = <
-			0x44 (PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
-			0x48 (PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
-			0x4C (PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
-			0x78 (PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
-			0x88 (PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
-			0x8C (PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
 		>;
 	};
 
 	wlan_pins: pinmux_wlan_pins {
 		pinctrl-single,pins = <
-			0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a0.gpio1_16 */
-			0x19C (PIN_INPUT | MUX_MODE7)		/* mcasp0_ahclkr.gpio3_17 */
-			0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* mcasp0_ahclkx.gpio3_21 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_a0.gpio1_16 */
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7)		/* mcasp0_ahclkr.gpio3_17 */
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* mcasp0_ahclkx.gpio3_21 */
 		>;
 	};
 
 	lcd_pins_s0: lcd_pins_s0 {
 		pinctrl-single,pins = <
-			0x20 (PIN_OUTPUT | MUX_MODE1)		/* gpmc_ad8.lcd_data23 */
-			0x24 (PIN_OUTPUT | MUX_MODE1)		/* gpmc_ad9.lcd_data22 */
-			0x28 (PIN_OUTPUT | MUX_MODE1)		/* gpmc_ad10.lcd_data21 */
-			0x2c (PIN_OUTPUT | MUX_MODE1)		/* gpmc_ad11.lcd_data20 */
-			0x30 (PIN_OUTPUT | MUX_MODE1)		/* gpmc_ad12.lcd_data19 */
-			0x34 (PIN_OUTPUT | MUX_MODE1)		/* gpmc_ad13.lcd_data18 */
-			0x38 (PIN_OUTPUT | MUX_MODE1)		/* gpmc_ad14.lcd_data17 */
-			0x3c (PIN_OUTPUT | MUX_MODE1)		/* gpmc_ad15.lcd_data16 */
-			0xa0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data0.lcd_data0 */
-			0xa4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data1.lcd_data1 */
-			0xa8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data2.lcd_data2 */
-			0xac (PIN_OUTPUT | MUX_MODE0)		/* lcd_data3.lcd_data3 */
-			0xb0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data4.lcd_data4 */
-			0xb4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data5.lcd_data5 */
-			0xb8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data6.lcd_data6 */
-			0xbc (PIN_OUTPUT | MUX_MODE0)		/* lcd_data7.lcd_data7 */
-			0xc0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data8.lcd_data8 */
-			0xc4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data9.lcd_data9 */
-			0xc8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data10.lcd_data10 */
-			0xcc (PIN_OUTPUT | MUX_MODE0)		/* lcd_data11.lcd_data11 */
-			0xd0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data12.lcd_data12 */
-			0xd4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data13.lcd_data13 */
-			0xd8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data14.lcd_data14 */
-			0xdc (PIN_OUTPUT | MUX_MODE0)		/* lcd_data15.lcd_data15 */
-			0xe0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_vsync.lcd_vsync */
-			0xe4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_hsync.lcd_hsync */
-			0xe8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_pclk.lcd_pclk */
-			0xec (PIN_OUTPUT | MUX_MODE0)		/* lcd_ac_bias_en.lcd_ac_bias_en */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)		/* gpmc_ad8.lcd_data23 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)		/* gpmc_ad9.lcd_data22 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)		/* gpmc_ad10.lcd_data21 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)		/* gpmc_ad11.lcd_data20 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)		/* gpmc_ad12.lcd_data19 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)		/* gpmc_ad13.lcd_data18 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)		/* gpmc_ad14.lcd_data17 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)		/* gpmc_ad15.lcd_data16 */
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
 		>;
 	};
 
-	am335x_evm_audio_pins: am335x_evm_audio_pins {
+	mcasp1_pins: mcasp1_pins {
 		pinctrl-single,pins = <
-			0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
-			0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
-			0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
-			0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
+			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */
+			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
 		>;
 	};
 
 	dcan1_pins_default: dcan1_pins_default {
 		pinctrl-single,pins = <
-			0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
-			0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
+			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
+			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
 		>;
 	};
 };
@@ -486,7 +487,7 @@
 &epwmss0 {
 	status = "okay";
 
-	ecap0: ecap@100 {
+	ecap0: pwm@100 {
 		status = "okay";
 		pinctrl-names = "default";
 		pinctrl-0 = <&ecap0_pins>;
@@ -534,7 +535,7 @@
 		#size-cells = <1>;
 		partition@0 {
 			label = "NAND.SPL";
-			reg = <0x00000000 0x000020000>;
+			reg = <0x00000000 0x00020000>;
 		};
 		partition@1 {
 			label = "NAND.SPL.backup1";
@@ -578,19 +579,19 @@
 #include "tps65910.dtsi"
 
 &mcasp1 {
-		pinctrl-names = "default";
-		pinctrl-0 = <&am335x_evm_audio_pins>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcasp1_pins>;
 
-		status = "okay";
+	status = "okay";
 
-		op-mode = <0>;          /* MCASP_IIS_MODE */
-		tdm-slots = <2>;
-		/* 4 serializers */
-		serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
-			0 0 1 2
-		>;
-		tx-num-evt = <32>;
-		rx-num-evt = <32>;
+	op-mode = <0>;          /* MCASP_IIS_MODE */
+	tdm-slots = <2>;
+	/* 4 serializers */
+	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
+		0 0 1 2
+	>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
 };
 
 &tps {
diff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts
index b14bf2f..5d96225 100644
--- a/arch/arm/dts/am335x-evmsk.dts
+++ b/arch/arm/dts/am335x-evmsk.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /*
@@ -32,12 +29,12 @@
 		};
 	};
 
-	memory {
+	memory@80000000 {
 		device_type = "memory";
 		reg = <0x80000000 0x10000000>; /* 256 MB */
 	};
 
-	vbat: fixedregulator@0 {
+	vbat: fixedregulator0 {
 		compatible = "regulator-fixed";
 		regulator-name = "vbat";
 		regulator-min-microvolt = <5000000>;
@@ -45,13 +42,13 @@
 		regulator-boot-on;
 	};
 
-	lis3_reg: fixedregulator@1 {
+	lis3_reg: fixedregulator1 {
 		compatible = "regulator-fixed";
 		regulator-name = "lis3_reg";
 		regulator-boot-on;
 	};
 
-	wl12xx_vmmc: fixedregulator@2 {
+	wl12xx_vmmc: fixedregulator2 {
 		pinctrl-names = "default";
 		pinctrl-0 = <&wl12xx_gpio>;
 		compatible = "regulator-fixed";
@@ -63,7 +60,7 @@
 		enable-active-high;
 	};
 
-	vtt_fixed: fixedregulator@3 {
+	vtt_fixed: fixedregulator3 {
 		compatible = "regulator-fixed";
 		regulator-name = "vtt";
 		regulator-min-microvolt = <1500000>;
@@ -80,26 +77,26 @@
 
 		compatible = "gpio-leds";
 
-		led@1 {
+		led1 {
 			label = "evmsk:green:usr0";
 			gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
-		led@2 {
+		led2 {
 			label = "evmsk:green:usr1";
 			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
-		led@3 {
+		led3 {
 			label = "evmsk:green:mmc0";
 			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "mmc0";
 			default-state = "off";
 		};
 
-		led@4 {
+		led4 {
 			label = "evmsk:green:heartbeat";
 			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
@@ -107,36 +104,38 @@
 		};
 	};
 
-	gpio_buttons: gpio_buttons@0 {
+	gpio_buttons: gpio_buttons0 {
 		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
 
-		switch@1 {
+		switch1 {
 			label = "button0";
 			linux,code = <0x100>;
 			gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
 		};
 
-		switch@2 {
+		switch2 {
 			label = "button1";
 			linux,code = <0x101>;
 			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
 		};
 
-		switch@3 {
+		switch3 {
 			label = "button2";
 			linux,code = <0x102>;
 			gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
 			wakeup-source;
 		};
 
-		switch@4 {
+		switch4 {
 			label = "button3";
 			linux,code = <0x103>;
 			gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
 		};
 	};
 
-	backlight {
+	lcd_bl: backlight {
 		compatible = "pwm-backlight";
 		pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>;
 		brightness-levels = <0 58 61 66 75 90 125 170 255>;
@@ -207,234 +206,234 @@
 
 	lcd_pins_default: lcd_pins_default {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad8.lcd_data23 */
-			AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad9.lcd_data22 */
-			AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad10.lcd_data21 */
-			AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad11.lcd_data20 */
-			AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad12.lcd_data19 */
-			AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad13.lcd_data18 */
-			AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad14.lcd_data17 */
-			AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad15.lcd_data16 */
-			AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)	/* lcd_data0.lcd_data0 */
-			AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)	/* lcd_data1.lcd_data1 */
-			AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)	/* lcd_data2.lcd_data2 */
-			AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)	/* lcd_data3.lcd_data3 */
-			AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)	/* lcd_data4.lcd_data4 */
-			AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)	/* lcd_data5.lcd_data5 */
-			AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)	/* lcd_data6.lcd_data6 */
-			AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)	/* lcd_data7.lcd_data7 */
-			AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)	/* lcd_data8.lcd_data8 */
-			AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)	/* lcd_data9.lcd_data9 */
-			AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)	/* lcd_data10.lcd_data10 */
-			AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)	/* lcd_data11.lcd_data11 */
-			AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)	/* lcd_data12.lcd_data12 */
-			AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)	/* lcd_data13.lcd_data13 */
-			AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)	/* lcd_data14.lcd_data14 */
-			AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)	/* lcd_data15.lcd_data15 */
-			AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)	/* lcd_vsync.lcd_vsync */
-			AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)	/* lcd_hsync.lcd_hsync */
-			AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)	/* lcd_pclk.lcd_pclk */
-			AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)	/* lcd_ac_bias_en.lcd_ac_bias_en */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad8.lcd_data23 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad9.lcd_data22 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad10.lcd_data21 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad11.lcd_data20 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad12.lcd_data19 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad13.lcd_data18 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad14.lcd_data17 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad15.lcd_data16 */
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
 		>;
 	};
 
 	lcd_pins_sleep: lcd_pins_sleep {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad8.lcd_data23 */
-			AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad9.lcd_data22 */
-			AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad10.lcd_data21 */
-			AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad11.lcd_data20 */
-			AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad12.lcd_data19 */
-			AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad13.lcd_data18 */
-			AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad14.lcd_data17 */
-			AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad15.lcd_data16 */
-			AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7)	/* lcd_data0.lcd_data0 */
-			AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7)	/* lcd_data1.lcd_data1 */
-			AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7)	/* lcd_data2.lcd_data2 */
-			AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7)	/* lcd_data3.lcd_data3 */
-			AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7)	/* lcd_data4.lcd_data4 */
-			AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7)	/* lcd_data5.lcd_data5 */
-			AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7)	/* lcd_data6.lcd_data6 */
-			AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7)	/* lcd_data7.lcd_data7 */
-			AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7)	/* lcd_data8.lcd_data8 */
-			AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7)	/* lcd_data9.lcd_data9 */
-			AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7)	/* lcd_data10.lcd_data10 */
-			AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7)	/* lcd_data11.lcd_data11 */
-			AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7)	/* lcd_data12.lcd_data12 */
-			AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7)	/* lcd_data13.lcd_data13 */
-			AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7)	/* lcd_data14.lcd_data14 */
-			AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7)	/* lcd_data15.lcd_data15 */
-			AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_vsync.lcd_vsync */
-			AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_hsync.lcd_hsync */
-			AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_pclk.lcd_pclk */
-			AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_ac_bias_en.lcd_ac_bias_en */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad8.lcd_data23 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad9.lcd_data22 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad10.lcd_data21 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad11.lcd_data20 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad12.lcd_data19 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad13.lcd_data18 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad14.lcd_data17 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad15.lcd_data16 */
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
 		>;
 	};
 
 
 	user_leds_s0: user_leds_s0 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x810, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad4.gpio1_4 */
-			AM33XX_IOPAD(0x814, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad5.gpio1_5 */
-			AM33XX_IOPAD(0x818, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad6.gpio1_6 */
-			AM33XX_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad7.gpio1_7 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad4.gpio1_4 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad5.gpio1_5 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad6.gpio1_6 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad7.gpio1_7 */
 		>;
 	};
 
 	gpio_keys_s0: gpio_keys_s0 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_oen_ren.gpio2_3 */
-			AM33XX_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_advn_ale.gpio2_2 */
-			AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_wait0.gpio0_30 */
-			AM33XX_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ben0_cle.gpio2_5 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_oen_ren.gpio2_3 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_advn_ale.gpio2_2 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_wait0.gpio0_30 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ben0_cle.gpio2_5 */
 		>;
 	};
 
 	i2c0_pins: pinmux_i2c0_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
-			AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 
 	uart0_pins: pinmux_uart0_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
-			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
+			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 		>;
 	};
 
 	clkout2_pin: pinmux_clkout2_pin {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)	/* xdma_event_intr1.clkout2 */
+			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* xdma_event_intr1.clkout2 */
 		>;
 	};
 
 	ecap2_pins: backlight_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x99c, MUX_MODE4)	/* mcasp0_ahclkr.ecap2_in_pwm2_out */
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4)	/* mcasp0_ahclkr.ecap2_in_pwm2_out */
 		>;
 	};
 
 	cpsw_default: cpsw_default {
 		pinctrl-single,pins = <
 			/* Slave 1 */
-			AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
-			AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
-			AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd3.rgmii1_td3 */
-			AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd2.rgmii1_td2 */
-			AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
-			AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
-			AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txclk.rgmii1_tclk */
-			AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxclk.rgmii1_rclk */
-			AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd3.rgmii1_rd3 */
-			AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd2.rgmii1_rd2 */
-			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
-			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd3.rgmii1_td3 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd2.rgmii1_td2 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txclk.rgmii1_tclk */
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxclk.rgmii1_rclk */
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd3.rgmii1_rd3 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd2.rgmii1_rd2 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
 
 			/* Slave 2 */
-			AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a0.rgmii2_tctl */
-			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a1.rgmii2_rctl */
-			AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a2.rgmii2_td3 */
-			AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a3.rgmii2_td2 */
-			AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a4.rgmii2_td1 */
-			AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a5.rgmii2_td0 */
-			AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a6.rgmii2_tclk */
-			AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a7.rgmii2_rclk */
-			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a8.rgmii2_rd3 */
-			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a9.rgmii2_rd2 */
-			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a10.rgmii2_rd1 */
-			AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a11.rgmii2_rd0 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a0.rgmii2_tctl */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a1.rgmii2_rctl */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a2.rgmii2_td3 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a3.rgmii2_td2 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a4.rgmii2_td1 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a5.rgmii2_td0 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a6.rgmii2_tclk */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a7.rgmii2_rclk */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a8.rgmii2_rd3 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a9.rgmii2_rd2 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a10.rgmii2_rd1 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a11.rgmii2_rd0 */
 		>;
 	};
 
 	cpsw_sleep: cpsw_sleep {
 		pinctrl-single,pins = <
 			/* Slave 1 reset value */
-			AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 
 			/* Slave 2 reset value*/
-			AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
 		>;
 	};
 
 	davinci_mdio_default: davinci_mdio_default {
 		pinctrl-single,pins = <
 			/* MDIO */
-			AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
-			AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 
 	davinci_mdio_sleep: davinci_mdio_sleep {
 		pinctrl-single,pins = <
 			/* MDIO reset value */
-			AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
 		>;
 	};
 
 	mmc1_pins: pinmux_mmc1_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) 		/* spi0_cs1.gpio0_6 */
 		>;
 	};
 
 	mcasp1_pins: mcasp1_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
-			AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
-			AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
-			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
+			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */
+			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
 		>;
 	};
 
 	mcasp1_pins_sleep: mcasp1_pins_sleep {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
 		>;
 	};
 
 	mmc2_pins: pinmux_mmc2_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
-			AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
-			AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
-			AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
-			AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
-			AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
-			AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
 		>;
 	};
 
 	wl12xx_gpio: pinmux_wl12xx_gpio {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */
 		>;
 	};
 };
@@ -531,7 +530,7 @@
 &epwmss2 {
 	status = "okay";
 
-	ecap2: ecap@100 {
+	ecap2: pwm@100 {
 		status = "okay";
 		pinctrl-names = "default";
 		pinctrl-0 = <&ecap2_pins>;
@@ -722,7 +721,7 @@
 };
 
 &lcdc {
-      status = "okay";
+	status = "okay";
 };
 
 &rtc {
diff --git a/arch/arm/dts/am335x-guardian.dts b/arch/arm/dts/am335x-guardian.dts
index 067c402..c2fd610 100644
--- a/arch/arm/dts/am335x-guardian.dts
+++ b/arch/arm/dts/am335x-guardian.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  * Copyright (C) 2018 Robert Bosch Power Tools GmbH
  */
 /dts-v1/;
@@ -29,10 +29,10 @@
 		reg = <0x80000000 0x10000000>; /* 256 MB */
 	};
 
-	gpio_keys {
-		compatible = "gpio-keys";
+	guardian_buttons: gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&guardian_button_pins>;
+		compatible = "gpio-keys";
 
 		select-button {
 			label = "guardian-select-button";
@@ -49,10 +49,10 @@
 		};
 	};
 
-	leds {
-		compatible = "gpio-leds";
+	guardian_leds: gpio-leds {
 		pinctrl-names = "default";
 		pinctrl-0 = <&guardian_led_pins>;
+		compatible = "gpio-leds";
 
 		life-led {
 			label = "guardian:life-led";
@@ -98,7 +98,7 @@
 
 	};
 
-	pwm7: dmtimer-pwm {
+	pwm7: pwm-7 {
 		compatible = "ti,omap-dmtimer-pwm";
 		ti,timers = <&timer7>;
 		pinctrl-names = "default";
diff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts
index 2a1b3a5..a542724 100644
--- a/arch/arm/dts/am335x-icev2.dts
+++ b/arch/arm/dts/am335x-icev2.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /*
@@ -24,12 +21,12 @@
 		tick-timer = &timer2;
 	};
 
-	memory {
+	memory@80000000 {
 		device_type = "memory";
 		reg = <0x80000000 0x10000000>; /* 256 MB */
 	};
 
-	vbat: fixedregulator@0 {
+	vbat: fixedregulator0 {
 		compatible = "regulator-fixed";
 		regulator-name = "vbat";
 		regulator-min-microvolt = <5000000>;
@@ -37,7 +34,7 @@
 		regulator-boot-on;
 	};
 
-	vtt_fixed: fixedregulator@1 {
+	vtt_fixed: fixedregulator1 {
 		compatible = "regulator-fixed";
 		regulator-name = "vtt";
 		regulator-min-microvolt = <1500000>;
@@ -48,52 +45,51 @@
 		enable-active-high;
 	};
 
-	leds@0 {
+	leds-iio {
 		compatible = "gpio-leds";
-
-		led@0 {
+		led-out0 {
 			label = "out0";
 			gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
-		led@1 {
+		led-out1 {
 			label = "out1";
 			gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
-		led@2 {
+		led-out2 {
 			label = "out2";
 			gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
-		led@3 {
+		led-out3 {
 			label = "out3";
 			gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
-		led@4 {
+		led-out4 {
 			label = "out4";
 			gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
-		led@5 {
+		led-out5 {
 			label = "out5";
 			gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
-		led@6 {
+		led-out6 {
 			label = "out6";
 			gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
-		led@7 {
+		led-out7 {
 			label = "out7";
 			gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
@@ -101,44 +97,44 @@
 	};
 
 	/* Tricolor status LEDs */
-	leds@1 {
+	leds1 {
 		compatible = "gpio-leds";
 		pinctrl-names = "default";
 		pinctrl-0 = <&user_leds>;
 
-		led@0 {
+		led0 {
 			label = "status0:red:cpu0";
 			gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 			linux,default-trigger = "cpu0";
 		};
 
-		led@1 {
+		led1 {
 			label = "status0:green:usr";
 			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
-		led@2 {
+		led2 {
 			label = "status0:yellow:usr";
 			gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
-		led@3 {
+		led3 {
 			label = "status1:red:mmc0";
 			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 			linux,default-trigger = "mmc0";
 		};
 
-		led@4 {
+		led4 {
 			label = "status1:green:usr";
 			gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
-		led@5 {
+		led5 {
 			label = "status1:yellow:usr";
 			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
@@ -149,31 +145,31 @@
 &am33xx_pinmux {
 	user_leds: user_leds {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
-			AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
-			AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
-			AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
-			AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
-			AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
+			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
+			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
 		>;
 	};
 
 	mmc0_pins_default: mmc0_pins_default {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */
-			AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */
-			AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */
-			AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
-			AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
-			AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
 			AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */
 		>;
 	};
 
 	i2c0_pins_default: i2c0_pins_default {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
-			AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
 		>;
 	};
 
@@ -188,71 +184,71 @@
 
 	uart3_pins_default: uart3_pins_default {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
-			AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
 		>;
 	};
 
 	cpsw_default: cpsw_default {
 		pinctrl-single,pins = <
 			/* Slave 1, RMII mode */
-			AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_crs.rmii1_crs_dv */
-			AM33XX_IOPAD(0x944, (PIN_INPUT_PULLUP | MUX_MODE0))	/* rmii1_refclk.rmii1_refclk */
-			AM33XX_IOPAD(0x940, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_rxd0.rmii1_rxd0 */
-			AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_rxd1.rmii1_rxd1 */
-			AM33XX_IOPAD(0x910, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_rxerr.rmii1_rxerr */
-			AM33XX_IOPAD(0x928, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))	/* mii1_txd0.rmii1_txd0 */
-			AM33XX_IOPAD(0x924, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))	/* mii1_txd1.rmii1_txd1 */
-			AM33XX_IOPAD(0x914, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))	/* mii1_txen.rmii1_txen */
+			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1)	/* mii1_crs.rmii1_crs_dv */
+			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)	/* mii1_rxerr.rmii1_rxerr */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* mii1_txd0.rmii1_txd0 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* mii1_txd1.rmii1_txd1 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* mii1_txen.rmii1_txen */
 			/* Slave 2, RMII mode */
-			AM33XX_IOPAD(0x870, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_wait0.rmii2_crs_dv */
-			AM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_col.rmii2_refclk */
-			AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_a11.rmii2_rxd0 */
-			AM33XX_IOPAD(0x868, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_a10.rmii2_rxd1 */
-			AM33XX_IOPAD(0x874, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_wpn.rmii2_rxerr */
-			AM33XX_IOPAD(0x854, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))	/* gpmc_a5.rmii2_txd0 */
-			AM33XX_IOPAD(0x850, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))	/* gpmc_a4.rmii2_txd1 */
-			AM33XX_IOPAD(0x840, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))	/* gpmc_a0.rmii2_txen */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_wait0.rmii2_crs_dv */
+			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE1)	/* mii1_col.rmii2_refclk */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_a11.rmii2_rxd0 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_a10.rmii2_rxd1 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_wpn.rmii2_rxerr */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* gpmc_a5.rmii2_txd0 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* gpmc_a4.rmii2_txd1 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* gpmc_a0.rmii2_txen */
 		>;
 	};
 
 	cpsw_sleep: cpsw_sleep {
 		pinctrl-single,pins = <
 			/* Slave 1 reset value */
-			AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-			AM33XX_IOPAD(0x944, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-			AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-			AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-			AM33XX_IOPAD(0x910, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-			AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-			AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-			AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
 
 			/* Slave 2 reset value */
-			AM33XX_IOPAD(0x870, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-			AM33XX_IOPAD(0x908, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-			AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-			AM33XX_IOPAD(0x868, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-			AM33XX_IOPAD(0x874, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-			AM33XX_IOPAD(0x854, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-			AM33XX_IOPAD(0x850, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-			AM33XX_IOPAD(0x840, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 		>;
 	};
 
 	davinci_mdio_default: davinci_mdio_default {
 		pinctrl-single,pins = <
 			/* MDIO */
-			AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0))	/* mdio_data.mdio_data */
-			AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0))			/* mdio_clk.mdio_clk */
+			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 
 	davinci_mdio_sleep: davinci_mdio_sleep {
 		pinctrl-single,pins = <
 			/* MDIO reset value */
-			AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-			AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
 		>;
 	};
 };
@@ -273,6 +269,56 @@
 		reg = <0x60>;
 		gpio-controller;
 		#gpio-cells = <2>;
+	};
+};
+
+&spi0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins_default>;
+
+	sn65hvs882@1 {
+		compatible = "pisosr-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+
+		reg = <1>;
+		spi-max-frequency = <1000000>;
+		spi-cpol;
+	};
+
+	spi_nor: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q64", "jedec,spi-nor";
+		spi-max-frequency = <80000000>;
+		m25p,fast-read;
+		reg = <0>;
+
+		partition@0 {
+			label = "u-boot-spl";
+			reg = <0x0 0x80000>;
+			read-only;
+		};
+
+		partition@1 {
+			label = "u-boot";
+			reg = <0x80000 0x100000>;
+			read-only;
+		};
+
+		partition@2 {
+			label = "u-boot-env";
+			reg = <0x180000 0x20000>;
+			read-only;
+		};
+
+		partition@3 {
+			label = "misc";
+			reg = <0x1A0000 0x660000>;
+		};
 	};
 };
 
@@ -381,16 +427,17 @@
 };
 
 &gpio3 {
-	p4 {
+	pr1-mii-ctl-hog {
 		gpio-hog;
 		gpios = <4 GPIO_ACTIVE_HIGH>;
 		output-high;
 		line-name = "PR1_MII_CTRL";
 	};
 
-	p10 {
+	mux-mii-hog {
 		gpio-hog;
 		gpios = <10 GPIO_ACTIVE_HIGH>;
+		/* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */
 		output-high;
 		line-name = "MUX_MII_CTRL";
 	};
@@ -437,52 +484,3 @@
 	};
 };
 
-&spi0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi0_pins_default>;
-
-	sn65hvs882@1 {
-		compatible = "pisosr-gpio";
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
-
-		reg = <1>;
-		spi-max-frequency = <1000000>;
-		spi-cpol;
-	};
-
-	spi_nor: flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "winbond,w25q64", "jedec,spi-nor";
-		spi-max-frequency = <80000000>;
-		m25p,fast-read;
-		reg = <0>;
-
-		partition@0 {
-			label = "u-boot-spl";
-			reg = <0x0 0x80000>;
-			read-only;
-		};
-
-		partition@1 {
-			label = "u-boot";
-			reg = <0x80000 0x100000>;
-			read-only;
-		};
-
-		partition@2 {
-			label = "u-boot-env";
-			reg = <0x180000 0x20000>;
-			read-only;
-		};
-
-		partition@3 {
-			label = "misc";
-			reg = <0x1A0000 0x660000>;
-		};
-	};
-};
diff --git a/arch/arm/dts/am335x-igep0033.dtsi b/arch/arm/dts/am335x-igep0033.dtsi
index f102f6a..ad57c74 100644
--- a/arch/arm/dts/am335x-igep0033.dtsi
+++ b/arch/arm/dts/am335x-igep0033.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x
  *
  * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 /dts-v1/;
@@ -57,41 +54,41 @@
 &am33xx_pinmux {
 	i2c0_pins: pinmux_i2c0_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
-			AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 
 	nandflash_pins: pinmux_nandflash_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
-			AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
-			AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
-			AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
-			AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
-			AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
-			AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
-			AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
-			AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
-			AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpio0_30 */
-			AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0 */
-			AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
-			AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
-			AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
-			AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)	/* gpmc_wpn.gpio0_31 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
 		>;
 	};
 
 	uart0_pins: pinmux_uart0_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
-			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
+			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 		>;
 	};
 
 	leds_pins: pinmux_leds_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a7.gpio1_23 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_a7.gpio1_23 */
 		>;
 	};
 };
@@ -174,7 +171,7 @@
 		/* MTD partition table */
 		partition@0 {
 			label = "SPL";
-			reg = <0x00000000 0x000080000>;
+			reg = <0x00000000 0x00080000>;
 		};
 
 		partition@1 {
@@ -194,7 +191,7 @@
 
 		partition@4 {
 			label = "File System";
-			reg = <0x00780000 0x007880000>;
+			reg = <0x00780000 0x07880000>;
 		};
 	};
 };
diff --git a/arch/arm/dts/am335x-osd335x-common.dtsi b/arch/arm/dts/am335x-osd335x-common.dtsi
index 2b55b7d..7cf4e9f 100644
--- a/arch/arm/dts/am335x-osd335x-common.dtsi
+++ b/arch/arm/dts/am335x-osd335x-common.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  *
  * Author: Robert Nelson <robertcnelson@gmail.com>
  */
@@ -36,8 +36,8 @@
 &am33xx_pinmux {
 	i2c0_pins: pinmux-i2c0-pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)	/* (C17) I2C0_SDA.I2C0_SDA */
-			AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)	/* (C16) I2C0_SCL.I2C0_SCL */
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 };
diff --git a/arch/arm/dts/am335x-pdu001.dts b/arch/arm/dts/am335x-pdu001.dts
index ae43d61..5820324 100644
--- a/arch/arm/dts/am335x-pdu001.dts
+++ b/arch/arm/dts/am335x-pdu001.dts
@@ -5,7 +5,7 @@
  *
  * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
  *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
  *
  * SPDX-License-Identifier:  GPL-2.0+
  */
@@ -92,162 +92,162 @@
 
 	i2c0_pins: pinmux_i2c0_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
-			AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 
 	i2c1_pins: pinmux_i2c1_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2)	/* spi0_d1.i2c1_sda */
-			AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2)	/* spi0_cs0.i2c1_scl */
+			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2)	/* spi0_d1.i2c1_sda */
+			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2)	/* spi0_cs0.i2c1_scl */
 		>;
 	};
 
 	i2c2_pins: pinmux_i2c2_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE2)	/* spi0_clk.i2c2_sda */
-			AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE2)	/* spi0_d0.i2c2_scl */
+			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE2)	/* spi0_clk.i2c2_sda */
+			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE2)	/* spi0_d0.i2c2_scl */
 		>;
 	};
 
 	spi1_pins: pinmux_spi1_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE3)		/* mcasp0_aclkx.spi1_sclk */
-			AM33XX_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3)		/* mcasp0_fsx.spi1_d0 */
-			AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcasp0_axr0.spi1_d1 */
-			AM33XX_IOPAD(0x99C, PIN_OUTPUT | MUX_MODE3)		/* mcasp0_ahclkr.spi1_cs0 */
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT, MUX_MODE3)		/* mcasp0_aclkx.spi1_sclk */
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT, MUX_MODE3)		/* mcasp0_fsx.spi1_d0 */
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE3)	/* mcasp0_axr0.spi1_d1 */
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE3)		/* mcasp0_ahclkr.spi1_cs0 */
 		>;
 	};
 
 	uart0_pins: pinmux_uart0_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x96C, PIN_OUTPUT | MUX_MODE7)		/* uart0_rtsn.gpio1_9 */
-			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
-			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
+			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 		>;
 	};
 
 	uart1_pins: pinmux_uart1_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart1_rxd.uart1_rxd */
-			AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart1_txd.uart1_txd */
+			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 		>;
 	};
 
 	uart3_pins: pinmux_uart3_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE1)	/* spi0_cs1.uart3_rxd */
-			AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* ecap0_in_pwm0_out.uart3_txd */
+			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1)	/* spi0_cs1.uart3_rxd */
+			AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* ecap0_in_pwm0_out.uart3_txd */
 		>;
 	};
 
 	clkout2_pin: pinmux_clkout2_pin {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)	/* xdma_event_intr1.clkout2 */
+			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* xdma_event_intr1.clkout2 */
 		>;
 	};
 
 	cpsw_default: cpsw_default {
 		pinctrl-single,pins = <
 			/* Port 1 (emac0) */
-			AM33XX_IOPAD(0x908, PIN_INPUT | MUX_MODE0)		/* mii1_col.mii1_col */
-			AM33XX_IOPAD(0x90C, PIN_INPUT | MUX_MODE0)		/* mii1_crs.mii1_crs */
-			AM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE0)		/* mii1_rxer.mii1_rxer */
-			AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE0)		/* mii1_txen.mii1_txen */
-			AM33XX_IOPAD(0x918, PIN_INPUT | MUX_MODE0)		/* mii1_rxdv.mii1_rxdv */
-			AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE0)		/* mii1_txd3.mii1_txd3 */
-			AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE0)		/* mii1_txd2.mii1_txd2 */
-			AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE0)		/* mii1_txd1.mii1_txd1 */
-			AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE0)		/* mii1_txd0.mii1_txd0 */
-			AM33XX_IOPAD(0x92c, PIN_INPUT | MUX_MODE0)		/* mii1_txclk.mii1_txclk */
-			AM33XX_IOPAD(0x930, PIN_INPUT | MUX_MODE0)		/* mii1_rxclk.mii1_rxclk */
-			AM33XX_IOPAD(0x934, PIN_INPUT | MUX_MODE0)		/* mii1_rxd3.mii1_rxd3 */
-			AM33XX_IOPAD(0x938, PIN_INPUT | MUX_MODE0)		/* mii1_rxd2.mii1_rxd2 */
-			AM33XX_IOPAD(0x93c, PIN_INPUT | MUX_MODE0)		/* mii1_rxd1.mii1_rxd1 */
-			AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE0)		/* mii1_rxd0.mii1_rxd0 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE0)
 
 			/* Port 2 (emac1) */
-			AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1)		/* mii2_txen.gpmc_a0 */
-			AM33XX_IOPAD(0x844, PIN_INPUT | MUX_MODE1)		/* mii2_rxdv.gpmc_a1 */
-			AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1)		/* mii2_txd3.gpmc_a2 */
-			AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1)		/* mii2_txd2.gpmc_a3 */
-			AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1)		/* mii2_txd1.gpmc_a4 */
-			AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1)		/* mii2_txd0.gpmc_a5 */
-			AM33XX_IOPAD(0x858, PIN_INPUT | MUX_MODE1)		/* mii2_txclk.gpmc_a6 */
-			AM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE1)		/* mii2_rxclk.gpmc_a7 */
-			AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE1)		/* mii2_rxd3.gpmc_a8 */
-			AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE1)		/* mii2_rxd2.gpmc_a9 */
-			AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE1)		/* mii2_rxd1.gpmc_a10 */
-			AM33XX_IOPAD(0x86C, PIN_INPUT | MUX_MODE1)		/* mii2_rxd0.gpmc_a11 */
-			AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE1)		/* mii2_crs.gpmc_wait0 */
-			AM33XX_IOPAD(0x874, PIN_INPUT | MUX_MODE1)		/* mii2_rxer.gpmc_wpn */
-			AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE1)		/* mii2_col.gpmc_ben1 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1)		/* mii2_txen.gpmc_a0 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT, MUX_MODE1)		/* mii2_rxdv.gpmc_a1 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1)		/* mii2_txd3.gpmc_a2 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1)		/* mii2_txd2.gpmc_a3 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1)		/* mii2_txd1.gpmc_a4 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1)		/* mii2_txd0.gpmc_a5 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT, MUX_MODE1)		/* mii2_txclk.gpmc_a6 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT, MUX_MODE1)		/* mii2_rxclk.gpmc_a7 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE1)		/* mii2_rxd3.gpmc_a8 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE1)		/* mii2_rxd2.gpmc_a9 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE1)		/* mii2_rxd1.gpmc_a10 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE1)		/* mii2_rxd0.gpmc_a11 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE1)		/* mii2_crs.gpmc_wait0 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT, MUX_MODE1)		/* mii2_rxer.gpmc_wpn */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT, MUX_MODE1)		/* mii2_col.gpmc_ben1 */
 		>;
 	};
 
 	davinci_mdio_default: davinci_mdio_default {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
-			AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 
 	mmc1_pins: pinmux_mmc1_pins {
 		/* eMMC */
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat3 */
-			AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat2 */
-			AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat1 */
-			AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat0 */
-			AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_clk */
-			AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_cmd */
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 
 	mmc2_pins: pinmux_mmc2_pins {
 		/* SD cardcage */
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_ad3.mmc1_dat3 */
-			AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_ad2.mmc1_dat2 */
-			AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_ad1.mmc1_dat1 */
-			AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_ad0.mmc1_dat0 */
-			AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2)	/* gpmc_csn1.mmc1_clk */
-			AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)	/* gpmc_csn2.mmc1_cmd */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad3.mmc1_dat3 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad2.mmc1_dat2 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad1.mmc1_dat1 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad0.mmc1_dat0 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)	/* gpmc_csn1.mmc1_clk */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)	/* gpmc_csn2.mmc1_cmd */
 			/* card change signal for frontpanel SD cardcage */
-			AM33XX_IOPAD(0x890, PIN_INPUT | MUX_MODE7)		/* gpmc_advn_ale.gpio2_2 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT, MUX_MODE7)		/* gpmc_advn_ale.gpio2_2 */
 		>;
 	};
 
 	lcd_pins_s0: lcd_pins_s0 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)		/* lcd_data0.lcd_data0 */
-			AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)		/* lcd_data1.lcd_data1 */
-			AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)		/* lcd_data2.lcd_data2 */
-			AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)		/* lcd_data3.lcd_data3 */
-			AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)		/* lcd_data4.lcd_data4 */
-			AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)		/* lcd_data5.lcd_data5 */
-			AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)		/* lcd_data6.lcd_data6 */
-			AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)		/* lcd_data7.lcd_data7 */
-			AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)		/* lcd_data8.lcd_data8 */
-			AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)		/* lcd_data9.lcd_data9 */
-			AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)		/* lcd_data10.lcd_data10 */
-			AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)		/* lcd_data11.lcd_data11 */
-			AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)		/* lcd_data12.lcd_data12 */
-			AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)		/* lcd_data13.lcd_data13 */
-			AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)		/* lcd_data14.lcd_data14 */
-			AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)		/* lcd_data15.lcd_data15 */
-			AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)		/* lcd_vsync.lcd_vsync */
-			AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)		/* lcd_hsync.lcd_hsync */
-			AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)		/* lcd_pclk.lcd_pclk */
-			AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)		/* lcd_ac_bias_en.lcd_ac_bias_en */
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
 		>;
 	};
 
 	dcan0_pins: pinmux_dcan0_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2)		/* uart1_ctsn.d_can0_tx */
-			AM33XX_IOPAD(0x97c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* uart1_rtsn.d_can0_rx */
+			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2)		/* uart1_ctsn.d_can0_tx */
+			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* uart1_rtsn.d_can0_rx */
 		>;
 	};
 };
@@ -353,7 +353,7 @@
 		};
 	};
 
-	mcp79400: mcp79400@6f {
+	mcp79400: rtc@6f {
 		compatible = "microchip,mcp7940x";
 		reg = <0x6f>;
 	};
diff --git a/arch/arm/dts/am335x-phycore-som.dtsi b/arch/arm/dts/am335x-phycore-som.dtsi
index 8d7c19e..3f9a4ea 100644
--- a/arch/arm/dts/am335x-phycore-som.dtsi
+++ b/arch/arm/dts/am335x-phycore-som.dtsi
@@ -1,11 +1,7 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2015 Phytec Messtechnik GmbH
  * Author: Teresa Remmet <t.remmet@phytec.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include "am33xx.dtsi"
@@ -31,17 +27,13 @@
 		reg = <0x80000000 0x10000000>; /* 256 MB */
 	};
 
-	regulators {
-		compatible = "simple-bus";
-
-		vcc5v: fixedregulator0 {
-			compatible = "regulator-fixed";
-			regulator-name = "vcc5v";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			regulator-boot-on;
-			regulator-always-on;
-		};
+	vcc5v: fixedregulator0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		regulator-always-on;
 	};
 };
 
@@ -58,22 +50,22 @@
 &am33xx_pinmux {
 	ethernet0_pins: pinmux_ethernet0 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_crs.rmii1_crs_dv */
-			AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxerr.rmii1_rxerr */
-			AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1)		/* mii1_txen.rmii1_txen */
-			AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1)		/* mii1_txd1.rmii1_txd1 */
-			AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1)		/* mii1_txd0.rmii1_txd0 */
-			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd1.rmii1_rxd1 */
-			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd0.rmii1_rxd0 */
-			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* rmii1_refclk.rmii1_refclk */
+			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
 		>;
 	};
 
 	mdio_pins: pinmux_mdio {
 		pinctrl-single,pins = <
 			/* MDIO */
-			AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
-			AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 };
@@ -105,8 +97,8 @@
 &am33xx_pinmux {
 	i2c0_pins: pinmux_i2c0 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
-			AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
 		>;
 	};
 };
@@ -145,20 +137,20 @@
 &am33xx_pinmux {
 		nandflash_pins: pinmux_nandflash {
 			pinctrl-single,pins = <
-			AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
-			AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
-			AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
-			AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
-			AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
-			AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
-			AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
-			AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
-			AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
-			AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0 */
-			AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
-			AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
-			AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
-			AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
 		>;
 	};
 };
@@ -297,10 +289,10 @@
 &am33xx_pinmux {
 	spi0_pins: pinmux_spi0 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* spi0_clk.spi0_clk */
-			AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* spi0_d0.spi0_d0 */
-			AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)	/* spi0_d1.spi0_d1 */
-			AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0)	/* spi0_cs0.spi0_cs0 */
+			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 };
@@ -310,7 +302,7 @@
 	pinctrl-0 = <&spi0_pins>;
 	status = "okay";
 
-	serial_flash: m25p80@0 {
+	serial_flash: flash@0 {
 		compatible = "jedec,spi-nor";
 		spi-max-frequency = <48000000>;
 		reg = <0x0>;
diff --git a/arch/arm/dts/am335x-pocketbeagle.dts b/arch/arm/dts/am335x-pocketbeagle.dts
index 62fe5ca..b379e3a 100644
--- a/arch/arm/dts/am335x-pocketbeagle.dts
+++ b/arch/arm/dts/am335x-pocketbeagle.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  *
  * Author: Robert Nelson <robertcnelson@gmail.com>
  */
@@ -23,28 +23,28 @@
 
 		compatible = "gpio-leds";
 
-		usr0 {
+		led-usr0 {
 			label = "beaglebone:green:usr0";
 			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 			default-state = "off";
 		};
 
-		usr1 {
+		led-usr1 {
 			label = "beaglebone:green:usr1";
 			gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "mmc0";
 			default-state = "off";
 		};
 
-		usr2 {
+		led-usr2 {
 			label = "beaglebone:green:usr2";
 			gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "cpu0";
 			default-state = "off";
 		};
 
-		usr3 {
+		led-usr3 {
 			label = "beaglebone:green:usr3";
 			gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
@@ -62,74 +62,74 @@
 &am33xx_pinmux {
 	i2c2_pins: pinmux-i2c2-pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3)	/* (D17) uart1_rtsn.I2C2_SCL */
-			AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3)	/* (D18) uart1_ctsn.I2C2_SDA */
+			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)	/* (D17) uart1_rtsn.I2C2_SCL */
+			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)	/* (D18) uart1_ctsn.I2C2_SDA */
 		>;
 	};
 
 	ehrpwm0_pins: pinmux-ehrpwm0-pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* (A13) mcasp0_aclkx.ehrpwm0A */
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* (A13) mcasp0_aclkx.ehrpwm0A */
 		>;
 	};
 
 	ehrpwm1_pins: pinmux-ehrpwm1-pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE6)	/* (U14) gpmc_a2.ehrpwm1A */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE6)	/* (U14) gpmc_a2.ehrpwm1A */
 		>;
 	};
 
 	mmc0_pins: pinmux-mmc0-pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)		/* (C15) spi0_cs1.gpio0[6] */
-			AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)	/* (G16) mmc0_dat0.mmc0_dat0 */
-			AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)	/* (G15) mmc0_dat1.mmc0_dat1 */
-			AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)	/* (F18) mmc0_dat2.mmc0_dat2 */
-			AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)	/* (F17) mmc0_dat3.mmc0_dat3 */
-			AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)	/* (G18) mmc0_cmd.mmc0_cmd */
-			AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)	/* (G17) mmc0_clk.mmc0_clk */
+			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)		/* (C15) spi0_cs1.gpio0[6] */
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
 			AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4)		/* (B12) mcasp0_aclkr.mmc0_sdwp */
 		>;
 	};
 
 	spi0_pins: pinmux-spi0-pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0)	/* (A17) spi0_sclk.spi0_sclk */
-			AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0)	/* (B17) spi0_d0.spi0_d0 */
-			AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)	/* (B16) spi0_d1.spi0_d1 */
-			AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0)	/* (A16) spi0_cs0.spi0_cs0 */
+			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 
 	spi1_pins: pinmux-spi1-pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x964, PIN_INPUT_PULLUP | MUX_MODE4)	/* (C18) eCAP0_in_PWM0_out.spi1_sclk */
-			AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE4)	/* (E18) uart0_ctsn.spi1_d0 */
-			AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE4)	/* (E17) uart0_rtsn.spi1_d1 */
-			AM33XX_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE4)	/* (A15) xdma_event_intr0.spi1_cs1 */
+			AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4)	/* (C18) eCAP0_in_PWM0_out.spi1_sclk */
+			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4)	/* (E18) uart0_ctsn.spi1_d0 */
+			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4)	/* (E17) uart0_rtsn.spi1_d1 */
+			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE4)	/* (A15) xdma_event_intr0.spi1_cs1 */
 		>;
 	};
 
 	usr_leds_pins: pinmux-usr-leds-pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7)		/* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */
-			AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7)		/* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */
-			AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7)		/* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */
-			AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7)		/* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)		/* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)		/* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7)		/* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7)		/* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */
 		>;
 	};
 
 	uart0_pins: pinmux-uart0-pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)	/* (E15) uart0_rxd.uart0_rxd */
-			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* (E16) uart0_txd.uart0_txd */
+			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 		>;
 	};
 
 	uart4_pins: pinmux-uart4-pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6)	/* (T17) gpmc_wait0.uart4_rxd */
-			AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6)	/* (U17) gpmc_wpn.uart4_txd */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)	/* (T17) gpmc_wait0.uart4_rxd */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6)	/* (U17) gpmc_wpn.uart4_txd */
 		>;
 	};
 };
diff --git a/arch/arm/dts/am335x-pxm2.dtsi b/arch/arm/dts/am335x-pxm2.dtsi
index 645d221..a51d6ac 100644
--- a/arch/arm/dts/am335x-pxm2.dtsi
+++ b/arch/arm/dts/am335x-pxm2.dtsi
@@ -148,7 +148,7 @@
 &epwmss0 {
 	status = "okay";
 
-	ecap0: ecap@100 {
+	ecap0: pwm@100 {
 		status = "okay";
 		pinctrl-names = "default";
 		pinctrl-0 = <&ecap0_pins>;
diff --git a/arch/arm/dts/am335x-regor.dtsi b/arch/arm/dts/am335x-regor.dtsi
index 86b3f07..6fbf4ac 100644
--- a/arch/arm/dts/am335x-regor.dtsi
+++ b/arch/arm/dts/am335x-regor.dtsi
@@ -41,8 +41,8 @@
 &am33xx_pinmux {
 	user_leds_pins: pinmux_user_leds {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x8E0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* lcd_hsync.gpio2_22 */
-			AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* mcasp0_fsx.gpio3_15 */
+			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* lcd_hsync.gpio2_22 */
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* mcasp0_fsx.gpio3_15 */
 		>;
 	};
 };
@@ -51,8 +51,8 @@
 &am33xx_pinmux {
 	dcan1_pins: pinmux_dcan1 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2)	/* uart0_ctsn.d_can1_tx */
-			AM33XX_IOPAD(0x96C, PIN_INPUT_PULLUP | MUX_MODE2)	/* uart0_rtsn.d_can1_rx */
+			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2)	/* uart0_ctsn.d_can1_tx */
+			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2)	/* uart0_rtsn.d_can1_rx */
 		>;
 	};
 };
@@ -67,20 +67,20 @@
 &am33xx_pinmux {
 	ethernet1_pins: pinmux_ethernet1 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a0.mii2_txen */
-			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a1.mii2_rxdv */
-			AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a2.mii2_txd3 */
-			AM33XX_IOPAD(0x84C, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a3.mii2_txd2 */
-			AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a4.mii2_txd1 */
-			AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a5.mii2_txd0 */
-			AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a6.mii2_txclk */
-			AM33XX_IOPAD(0x85C, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a7.mii2_rxclk */
-			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a8.mii2_rxd3 */
-			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1)	 /* gpmc_a9.mii2_rxd2 */
-			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a10.mii2_rxd1 */
-			AM33XX_IOPAD(0x86C, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a11.mii2_rxd0 */
-			AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_wpn.mii2_rxerr */
-			AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ben1.mii2_col */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a0.mii2_txen */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a1.mii2_rxdv */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a2.mii2_txd3 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a3.mii2_txd2 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a4.mii2_txd1 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a5.mii2_txd0 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a6.mii2_txclk */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a7.mii2_rxclk */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a8.mii2_rxd3 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1)	 /* gpmc_a9.mii2_rxd2 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a10.mii2_rxd1 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a11.mii2_rxd0 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_wpn.mii2_rxerr */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_ben1.mii2_col */
 		>;
 	};
 };
@@ -112,15 +112,15 @@
 	user_gpios_pins: pinmux_user_gpios {
 		pinctrl-single,pins = <
 			/* DIGIN 1-4 */
-			AM33XX_IOPAD(0x82C, PIN_INPUT | MUX_MODE7)		/* gpmc_ad11.gpio0_27 */
-			AM33XX_IOPAD(0x828, PIN_INPUT | MUX_MODE7)		/* gpmc_ad10.gpio0_26 */
-			AM33XX_IOPAD(0x824, PIN_INPUT | MUX_MODE7)		/* gpmc_ad9.gpio0_23 */
-			AM33XX_IOPAD(0x820, PIN_INPUT | MUX_MODE7)		/* gpmc_ad8.gpio0_22 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7)		/* gpmc_ad11.gpio0_27 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT, MUX_MODE7)		/* gpmc_ad10.gpio0_26 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT, MUX_MODE7)		/* gpmc_ad9.gpio0_23 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT, MUX_MODE7)		/* gpmc_ad8.gpio0_22 */
 			/* DIGOUT 1-4 */
-			AM33XX_IOPAD(0x83C, PIN_OUTPUT | MUX_MODE7)		/* gpmc_ad15.gpio1_15 */
-			AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE7)		/* gpmc_ad14.gpio1_14 */
-			AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE7)		/* gpmc_ad13.gpio1_13 */
-			AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE7)		/* gpmc_ad12.gpio1_12 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE7)		/* gpmc_ad15.gpio1_15 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE7)		/* gpmc_ad14.gpio1_14 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE7)		/* gpmc_ad13.gpio1_13 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE7)		/* gpmc_ad12.gpio1_12 */
 		>;
 	};
 };
@@ -129,13 +129,13 @@
 &am33xx_pinmux {
 	mmc1_pins: pinmux_mmc1 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x8F0, PIN_INPUT_PULLUP | MUX_MODE0)
-			AM33XX_IOPAD(0x8F4, PIN_INPUT_PULLUP | MUX_MODE0)
-			AM33XX_IOPAD(0x8F8, PIN_INPUT_PULLUP | MUX_MODE0)
-			AM33XX_IOPAD(0x8FC, PIN_INPUT_PULLUP | MUX_MODE0)
-			AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)
-			AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)
-			AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7)	/* spi0_cs1.mmc0_sdcd */
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7)	/* spi0_cs1.mmc0_sdcd */
 		>;
 	};
 };
@@ -158,15 +158,15 @@
 &am33xx_pinmux {
 	uart0_pins: pinmux_uart0 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)
-			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 		>;
 	};
 
 	uart2_pins: pinmux_uart2 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x92C, PIN_INPUT_PULLUP | MUX_MODE1)	/* mii1_tx_clk.uart2_rxd */
-			AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_rx_clk.uart2_txd */
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1)	/* mii1_tx_clk.uart2_rxd */
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* mii1_rx_clk.uart2_txd */
 		>;
 	};
 };
@@ -187,9 +187,9 @@
 &am33xx_pinmux {
 	uart1_rs485_pins: pinmux_uart1_rs485_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)
-			AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
-			AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 };
diff --git a/arch/arm/dts/am335x-rut.dts b/arch/arm/dts/am335x-rut.dts
index cc06f5d..7760b97 100644
--- a/arch/arm/dts/am335x-rut.dts
+++ b/arch/arm/dts/am335x-rut.dts
@@ -174,7 +174,7 @@
 &epwmss0 {
 	status = "okay";
 
-	ecap0: ecap@100 {
+	ecap0: pwm@100 {
 		status = "okay";
 		pinctrl-names = "default";
 		pinctrl-0 = <&ecap0_pins>;
diff --git a/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts
index 246a1a9..a2676d1 100644
--- a/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts
+++ b/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts
@@ -23,7 +23,7 @@
 		regulator-name = "wlan-en-regulator";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
-		startup-delay-us= <100000>;
+		startup-delay-us = <100000>;
 	};
 };
 
diff --git a/arch/arm/dts/am335x-shc.dts b/arch/arm/dts/am335x-shc.dts
index a41a060..b44b159 100644
--- a/arch/arm/dts/am335x-shc.dts
+++ b/arch/arm/dts/am335x-shc.dts
@@ -36,10 +36,10 @@
 		};
 	};
 
-	gpio_keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 
-		back_button {
+		back-button {
 			label = "Back Button";
 			gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
 			linux,code = <KEY_BACK>;
@@ -47,7 +47,7 @@
 			wakeup-source;
 		};
 
-		front_button {
+		front-button {
 			label = "Front Button";
 			gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
 			linux,code = <KEY_FRONT>;
@@ -144,14 +144,14 @@
 };
 
 &gpio1 {
-	hmtc_rst {
+	hmtc-rst-hog {
 		gpio-hog;
 		gpios = <24 GPIO_ACTIVE_LOW>;
 		output-high;
 		line-name = "homematic_reset";
 	};
 
-	hmtc_prog {
+	hmtc-prog-hog {
 		gpio-hog;
 		gpios = <27 GPIO_ACTIVE_LOW>;
 		output-high;
@@ -160,14 +160,14 @@
 };
 
 &gpio3 {
-	zgb_rst {
+	zgb-rst-hog {
 		gpio-hog;
 		gpios = <18 GPIO_ACTIVE_LOW>;
 		output-low;
 		line-name = "zigbee_reset";
 	};
 
-	zgb_boot {
+	zgb-boot-hog {
 		gpio-hog;
 		gpios = <19 GPIO_ACTIVE_HIGH>;
 		output-high;
@@ -383,193 +383,191 @@
 	clkout2_pin: pinmux_clkout2_pin {
 		pinctrl-single,pins = <
 			/* xdma_event_intr1.clkout2 */
-			AM33XX_IOPAD(0x9b4, PIN_INPUT | MUX_MODE6)
+			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT, MUX_MODE6)
 		>;
 	};
 
 	cpsw_default: cpsw_default {
 		pinctrl-single,pins = <
 			/* Slave 1 */
-			AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE0)
-			AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
-			AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE0)
-			AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
-			AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
-			AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE0)
-			AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE0)
-			AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0)
-			AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE0)
-			AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE0)
-			AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE0)
-			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE0)
-			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
 		>;
 	};
 
 	cpsw_sleep: cpsw_sleep {
 		pinctrl-single,pins = <
 			/* Slave 1 reset value */
-			AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 		>;
 	};
 
 	davinci_mdio_default: davinci_mdio_default {
 		pinctrl-single,pins = <
-			/* mdio_data.mdio_data */
-			AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
-			/* mdio_clk.mdio_clk */
-			AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 
 	davinci_mdio_sleep: davinci_mdio_sleep {
 		pinctrl-single,pins = <
 			/* MDIO reset value */
-			AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
 		>;
 	};
 
 	ehrpwm1_pins: pinmux_ehrpwm1 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.gpio1_19 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.gpio1_19 */
 		>;
 	};
 
 	emmc_pins: pinmux_emmc_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x880, PIN_INPUT | MUX_MODE2)
-			AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)
-			AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)
-			AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)
-			AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)
-			AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)
-			AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1)
-			AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1)
-			AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1)
-			AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT, MUX_MODE2)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)
 		>;
 	};
 
 	i2c0_pins: pinmux_i2c0_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0)
-			AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
 		>;
 	};
 
 	mmc1_pins: pinmux_mmc1_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE5)
+			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE5)
 		>;
 	};
 
 	mmc3_pins: pinmux_mmc3_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x830, PIN_INPUT | MUX_MODE3)
-			AM33XX_IOPAD(0x834, PIN_INPUT | MUX_MODE3)
-			AM33XX_IOPAD(0x838, PIN_INPUT | MUX_MODE3)
-			AM33XX_IOPAD(0x83c, PIN_INPUT | MUX_MODE3)
-			AM33XX_IOPAD(0x888, PIN_INPUT | MUX_MODE3)
-			AM33XX_IOPAD(0x88c, PIN_INPUT | MUX_MODE3)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE3)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE3)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT, MUX_MODE3)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE3)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT, MUX_MODE3)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT, MUX_MODE3)
 		>;
 	};
 
 	uart0_pins: pinmux_uart0_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x968, PIN_INPUT_PULLDOWN | MUX_MODE0)
-			AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE0)
-			AM33XX_IOPAD(0x970, PIN_INPUT_PULLDOWN | MUX_MODE0)
-			AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0)
 		>;
 	};
 
 	uart1_pins: pinmux_uart1 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0)
-			AM33XX_IOPAD(0x97C, PIN_OUTPUT | MUX_MODE0)
-			AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0)
-			AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0)
 		>;
 	};
 
 	uart2_pins: pinmux_uart2_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1)
-			AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1)
+			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1)
 		>;
 	};
 
 	uart4_pins: pinmux_uart4_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6)
-			AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE6)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE6)
 		>;
 	};
 
 	user_leds_s0: user_leds_s0 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x844, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLUP | MUX_MODE7)
-			AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x86c, PIN_INPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x878, PIN_OUTPUT_PULLUP | MUX_MODE7)
-			AM33XX_IOPAD(0x87c, PIN_INPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x894, PIN_INPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x958, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE7)
-			AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLUP | MUX_MODE7)
-			AM33XX_IOPAD(0x9a0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLUP, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLUP, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7)
 		>;
 	};
 };
diff --git a/arch/arm/dts/am335x-sl50.dts b/arch/arm/dts/am335x-sl50.dts
index ebb56bd..56c0943 100644
--- a/arch/arm/dts/am335x-sl50.dts
+++ b/arch/arm/dts/am335x-sl50.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 /dts-v1/;
 
@@ -34,25 +31,25 @@
 		pinctrl-0 = <&led_pins>;
 
 		led0 {
-			label = "sl50:green:usr0";
+			label = "sl50:red:usr0";
 			gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
 			default-state = "off";
 		};
 
 		led1 {
-			label = "sl50:red:usr1";
+			label = "sl50:green:usr1";
 			gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
 			default-state = "off";
 		};
 
 		led2 {
-			label = "sl50:green:usr2";
+			label = "sl50:red:usr2";
 			gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
 			default-state = "off";
 		};
 
 		led3 {
-			label = "sl50:red:usr3";
+			label = "sl50:green:usr3";
 			gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
 			default-state = "off";
 		};
@@ -78,7 +75,7 @@
 		#size-cells = <0>;
 
 		/* audio external oscillator */
-		tlv320aic3x_mclk: oscillator@0 {
+		audio_mclk_fixed: oscillator@0 {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency  = <24576000>;	/* 24.576MHz */
@@ -91,7 +88,7 @@
 		ti,audio-codec = <&audio_codec>;
 		ti,mcasp-controller = <&mcasp0>;
 
-		clocks = <&tlv320aic3x_mclk>;
+		clocks = <&audio_mclk_fixed>;
 		clock-names = "mclk";
 
 		ti,audio-routing =
@@ -122,126 +119,126 @@
 
 	led_pins: pinmux_led_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7)	/* gpmc_a5.gpio1_21 */
-			AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7)	/* gpmc_a6.gpio1_22 */
-			AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7)	/* gpmc_a7.gpio1_23 */
-			AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7)	/* gpmc_a8.gpio1_24 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)	/* gpmc_a5.gpio1_21 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)	/* gpmc_a6.gpio1_22 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7)	/* gpmc_a7.gpio1_23 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7)	/* gpmc_a8.gpio1_24 */
 		>;
 	};
 
 	uart0_pins: pinmux_uart0_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
-			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
+			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 		>;
 	};
 
 	uart1_pins: pinmux_uart1_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart1_rxd.uart1_rxd */
-			AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart1_txd.uart1_txd */
+			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 		>;
 	};
 
 	uart4_pins: pinmux_uart4_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6)	/* gpmc_wait0.uart4_rxd */
-			AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6)	/* gpmc_wpn.uart4_txd */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)	/* gpmc_wait0.uart4_rxd */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6)	/* gpmc_wpn.uart4_txd */
 		>;
 	};
 
 	i2c0_pins: pinmux_i2c0_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
-			AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 
 	i2c2_pins: pinmux_i2c2_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3)	/* uart1_ctsn.i2c2_sda */
-			AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3)	/* uart1_rtsn.i2c2_scl */
+			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)	/* uart1_ctsn.i2c2_sda */
+			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)	/* uart1_rtsn.i2c2_scl */
 		>;
 	};
 
 	cpsw_default: cpsw_default {
 		pinctrl-single,pins = <
 			/* Slave 1 */
-			AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxerr.mii1_rxerr */
-			AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txen.mii1_txen */
-			AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxdv.mii1_rxdv */
-			AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd3.mii1_txd3 */
-			AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd2.mii1_txd2 */
-			AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd1.mii1_txd1 */
-			AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd0.mii1_txd0 */
-			AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_txclk.mii1_txclk */
-			AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxclk.mii1_rxclk */
-			AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd3.mii1_rxd3 */
-			AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd2.mii1_rxd2 */
-			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd1.mii1_rxd1 */
-			AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd0.mii1_rxd0 */
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 
 	cpsw_sleep: cpsw_sleep {
 		pinctrl-single,pins = <
 			/* Slave 1 reset value */
-			AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 		>;
 	};
 
 	davinci_mdio_default: davinci_mdio_default {
 		pinctrl-single,pins = <
 			/* MDIO */
-			AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
-			AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
 		>;
 	};
 
 	davinci_mdio_sleep: davinci_mdio_sleep {
 		pinctrl-single,pins = <
 			/* MDIO reset value */
-			AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
 		>;
 	};
 
 	mmc1_pins: pinmux_mmc1_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE7)		/* uart0_rtsn.gpio1_9 */
+			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE7)		/* uart0_rtsn.gpio1_9 */
 		>;
 	};
 
 	emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_a4.gpio1_20 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLUP, MUX_MODE7)	/* gpmc_a4.gpio1_20 */
 		>;
 	};
 
 	emmc_pins: pinmux_emmc_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2)	/* gpmc_csn1.mmc1_clk */
-			AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)	/* gpmc_csn2.mmc1_cmd */
-			AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_ad0.mmc1_dat0 */
-			AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_ad1.mmc1_dat1 */
-			AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_ad2.mmc1_dat2 */
-			AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_ad3.mmc1_dat3 */
-			AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_ad4.mmc1_dat4 */
-			AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_ad5.mmc1_dat5 */
-			AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_ad6.mmc1_dat6 */
-			AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_ad7.mmc1_dat7 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)	/* gpmc_csn1.mmc1_clk */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)	/* gpmc_csn2.mmc1_cmd */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad0.mmc1_dat0 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad1.mmc1_dat1 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad2.mmc1_dat2 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad3.mmc1_dat3 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad4.mmc1_dat4 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) 	/* gpmc_ad5.mmc1_dat5 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad6.mmc1_dat6 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad7.mmc1_dat7 */
 		>;
 	};
 
@@ -264,11 +261,11 @@
 
 	spi0_pins: pinmux_spi0_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0)	/* SPI0_MOSI - spi0_d0.spi0_d0 */
-			AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)	/* SPI0_MISO - spi0_d1.spi0_d1 */
-			AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0)	/* SPI0_CLK  - spi0_clk.spi0_clk */
-			AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0)	/* SPI0_CS0 (NBATTSS) - spi0_cs0.spi0_cs0 */
-			AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0)	/* SPI0_CS1 (FPGA_FLASH_NCS) - spi0_cs1.spi0_cs1 */
+			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)	/* SPI0_MOSI */
+			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)	/* SPI0_MISO */
+			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)	/* SPI0_CS0 (NBATTSS) */
+			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0)	/* SPI0_CS1 (FPGA_FLASH_NCS) */
 		>;
 	};
 
@@ -276,13 +273,13 @@
 		pinctrl-single,pins = <
 			AM33XX_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7)	/* SoundPA_en - mcasp0_fsr.gpio3_19 */
 			AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7)	/* nKbdOnC - gpmc_ad10.gpio0_26 */
-			AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE7)	/* nKbdInt - gpmc_ad12.gpio1_12 */
-			AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7)	/* nKbdReset - gpmc_ad13.gpio1_13 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7)	/* nKbdInt - gpmc_ad12.gpio1_12 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7)	/* nKbdReset - gpmc_ad13.gpio1_13 */
 			AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7)	/* nDispReset - gpmc_ad14.gpio1_14 */
-			AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7)	/* USB1_enPower - gpmc_a1.gpio1_17 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE7)	/* USB1_enPower - gpmc_a1.gpio1_17 */
 			/* PDI Bus - Battery system */
-			AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7)	/* nBattReset  gpmc_a0.gpio1_16 */
-			AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE7)	/* BattPDIData gpmc_ad15.gpio1_15 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7)	/* nBattReset  gpmc_a0.gpio1_16 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7)	/* BattPDIData gpmc_ad15.gpio1_15 */
 		>;
 	};
 };
@@ -433,7 +430,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi0_pins>;
 
-	flash: n25q032@1 {
+	flash: flash@1 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "micron,n25q032";
diff --git a/arch/arm/dts/am335x-wega-rdk.dts b/arch/arm/dts/am335x-wega-rdk.dts
index fe50f30..2e04f6d 100644
--- a/arch/arm/dts/am335x-wega-rdk.dts
+++ b/arch/arm/dts/am335x-wega-rdk.dts
@@ -1,11 +1,7 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2015 Phytec Messtechnik GmbH
  * Author: Teresa Remmet <t.remmet@phytec.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/am335x-wega.dtsi b/arch/arm/dts/am335x-wega.dtsi
index f3e045d..408034d 100644
--- a/arch/arm/dts/am335x-wega.dtsi
+++ b/arch/arm/dts/am335x-wega.dtsi
@@ -1,11 +1,7 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2015 Phytec Messtechnik GmbH
  * Author: Teresa Remmet <t.remmet@phytec.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 / {
@@ -16,16 +12,12 @@
 		compatible = "ti,da830-evm-audio";
 	};
 
-	regulators {
-		compatible = "simple-bus";
-
-		vcc3v3: fixedregulator1 {
-			compatible = "regulator-fixed";
-			regulator-name = "vcc3v3";
-			regulator-min-microvolt = <3300000>;
-			regulator-max-microvolt = <3300000>;
-			regulator-boot-on;
-		};
+	vcc3v3: fixedregulator1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
 	};
 };
 
@@ -33,11 +25,11 @@
 &am33xx_pinmux {
 	mcasp0_pins: pinmux_mcasp0 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x9AC, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahclkx.mcasp0_ahclkx */
-			AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp0_aclkx.mcasp0_aclkx */
-			AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp0_fsx.mcasp0_fsx */
-			AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp0_axr0.mcasp0_axr0 */
-			AM33XX_IOPAD(0x9A8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 		>;
 	};
 };
@@ -85,8 +77,8 @@
 &am33xx_pinmux {
 	dcan1_pins: pinmux_dcan1 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
-			AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
+			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
+			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
 		>;
 	};
 };
@@ -101,20 +93,20 @@
 &am33xx_pinmux {
 	ethernet1_pins: pinmux_ethernet1 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a0.mii2_txen */
-			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a1.mii2_rxdv */
-			AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a2.mii2_txd3 */
-			AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a3.mii2_txd2 */
-			AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a4.mii2_txd1 */
-			AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a5.mii2_txd0 */
-			AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a6.mii2_txclk */
-			AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a7.mii2_rxclk */
-			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a8.mii2_rxd3 */
-			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a9.mii2_rxd2 */
-			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a10.mii2_rxd1 */
-			AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a11.mii2_rxd0 */
-			AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_wpn.mii2_rxerr */
-			AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ben1.mii2_col */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a0.mii2_txen */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a1.mii2_rxdv */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a2.mii2_txd3 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a3.mii2_txd2 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a4.mii2_txd1 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a5.mii2_txd0 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a6.mii2_txclk */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a7.mii2_rxclk */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a8.mii2_rxd3 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a9.mii2_rxd2 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a10.mii2_rxd1 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a11.mii2_rxd0 */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_wpn.mii2_rxerr */
+			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_ben1.mii2_col */
 		>;
 	};
 };
@@ -142,13 +134,13 @@
 &am33xx_pinmux {
 	mmc1_pins: pinmux_mmc1 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat3.mmc0_dat3 */
-			AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat2.mmc0_dat2 */
-			AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat1.mmc0_dat1 */
-			AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat0.mmc0_dat0 */
-			AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_clk.mmc0_clk */
-			AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_cmd.mmc0_cmd */
-			AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7)	/* spi0_cs1.mmc0_sdcd */
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7)	/* spi0_cs1.mmc0_sdcd */
 		>;
 	};
 };
@@ -172,17 +164,17 @@
 &am33xx_pinmux {
 	uart0_pins: pinmux_uart0 {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
-			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 		>;
 	};
 
 	uart1_pins: pinmux_uart1_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart1_rxd.uart1_rxd */
-			AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart1_txd.uart1_txd */
-			AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0)		/* uart1_ctsn.uart1_ctsn */
-			AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart1_rtsn.uart1_rtsn */
+			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 		>;
 	};
 };
diff --git a/arch/arm/dts/am33xx-clocks.dtsi b/arch/arm/dts/am33xx-clocks.dtsi
index 44b6268..2984b2f 100644
--- a/arch/arm/dts/am33xx-clocks.dtsi
+++ b/arch/arm/dts/am33xx-clocks.dtsi
@@ -1,14 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for AM33xx clock data
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 &scm_clocks {
-	sys_clkin_ck: sys_clkin_ck@40 {
+	sys_clkin_ck: clock-sys-clkin-22@40 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
@@ -16,7 +13,7 @@
 		reg = <0x0040>;
 	};
 
-	adc_tsc_fck: adc_tsc_fck {
+	adc_tsc_fck: clock-adc-tsc-fck {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&sys_clkin_ck>;
@@ -24,7 +21,7 @@
 		clock-div = <1>;
 	};
 
-	dcan0_fck: dcan0_fck {
+	dcan0_fck: clock-dcan0-fck {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&sys_clkin_ck>;
@@ -32,7 +29,7 @@
 		clock-div = <1>;
 	};
 
-	dcan1_fck: dcan1_fck {
+	dcan1_fck: clock-dcan1-fck {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&sys_clkin_ck>;
@@ -40,7 +37,7 @@
 		clock-div = <1>;
 	};
 
-	mcasp0_fck: mcasp0_fck {
+	mcasp0_fck: clock-mcasp0-fck {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&sys_clkin_ck>;
@@ -48,7 +45,7 @@
 		clock-div = <1>;
 	};
 
-	mcasp1_fck: mcasp1_fck {
+	mcasp1_fck: clock-mcasp1-fck {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&sys_clkin_ck>;
@@ -56,7 +53,7 @@
 		clock-div = <1>;
 	};
 
-	smartreflex0_fck: smartreflex0_fck {
+	smartreflex0_fck: clock-smartreflex0-fck {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&sys_clkin_ck>;
@@ -64,7 +61,7 @@
 		clock-div = <1>;
 	};
 
-	smartreflex1_fck: smartreflex1_fck {
+	smartreflex1_fck: clock-smartreflex1-fck {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&sys_clkin_ck>;
@@ -72,7 +69,7 @@
 		clock-div = <1>;
 	};
 
-	sha0_fck: sha0_fck {
+	sha0_fck: clock-sha0-fck {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&sys_clkin_ck>;
@@ -80,7 +77,7 @@
 		clock-div = <1>;
 	};
 
-	aes0_fck: aes0_fck {
+	aes0_fck: clock-aes0-fck {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&sys_clkin_ck>;
@@ -88,7 +85,7 @@
 		clock-div = <1>;
 	};
 
-	rng_fck: rng_fck {
+	rng_fck: clock-rng-fck {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&sys_clkin_ck>;
@@ -121,62 +118,62 @@
 	};
 };
 &prcm_clocks {
-	clk_32768_ck: clk_32768_ck {
+	clk_32768_ck: clock-clk-32768 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <32768>;
 	};
 
-	clk_rc32k_ck: clk_rc32k_ck {
+	clk_rc32k_ck: clock-clk-rc32k {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <32000>;
 	};
 
-	virt_19200000_ck: virt_19200000_ck {
+	virt_19200000_ck: clock-virt-19200000 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <19200000>;
 	};
 
-	virt_24000000_ck: virt_24000000_ck {
+	virt_24000000_ck: clock-virt-24000000 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <24000000>;
 	};
 
-	virt_25000000_ck: virt_25000000_ck {
+	virt_25000000_ck: clock-virt-25000000 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <25000000>;
 	};
 
-	virt_26000000_ck: virt_26000000_ck {
+	virt_26000000_ck: clock-virt-26000000 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <26000000>;
 	};
 
-	tclkin_ck: tclkin_ck {
+	tclkin_ck: clock-tclkin {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <12000000>;
 	};
 
-	dpll_core_ck: dpll_core_ck@490 {
+	dpll_core_ck: clock@490 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-core-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 		reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
 	};
 
-	dpll_core_x2_ck: dpll_core_x2_ck {
+	dpll_core_x2_ck: clock-dpll-core-x2 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-x2-clock";
 		clocks = <&dpll_core_ck>;
 	};
 
-	dpll_core_m4_ck: dpll_core_m4_ck@480 {
+	dpll_core_m4_ck: clock-dpll-core-m4@480 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -185,7 +182,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_core_m5_ck: dpll_core_m5_ck@484 {
+	dpll_core_m5_ck: clock-dpll-core-m5@484 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -194,7 +191,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
+	dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -203,14 +200,14 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_mpu_ck: dpll_mpu_ck@488 {
+	dpll_mpu_ck: clock@488 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 		reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
 	};
 
-	dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
+	dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_mpu_ck>;
@@ -219,14 +216,14 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_ddr_ck: dpll_ddr_ck@494 {
+	dpll_ddr_ck: clock@494 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-no-gate-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 		reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
 	};
 
-	dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
+	dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_ddr_ck>;
@@ -235,7 +232,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
+	dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_ddr_m2_ck>;
@@ -243,14 +240,14 @@
 		clock-div = <2>;
 	};
 
-	dpll_disp_ck: dpll_disp_ck@498 {
+	dpll_disp_ck: clock@498 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-no-gate-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 		reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
 	};
 
-	dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
+	dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_disp_ck>;
@@ -260,14 +257,14 @@
 		ti,set-rate-parent;
 	};
 
-	dpll_per_ck: dpll_per_ck@48c {
+	dpll_per_ck: clock@48c {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-no-gate-j-type-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 		reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
 	};
 
-	dpll_per_m2_ck: dpll_per_m2_ck@4ac {
+	dpll_per_m2_ck: clock-dpll-per-m2@4ac {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_ck>;
@@ -276,7 +273,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+	dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_per_m2_ck>;
@@ -284,7 +281,7 @@
 		clock-div = <4>;
 	};
 
-	dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+	dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_per_m2_ck>;
@@ -292,7 +289,7 @@
 		clock-div = <4>;
 	};
 
-	clk_24mhz: clk_24mhz {
+	clk_24mhz: clock-clk-24mhz {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_per_m2_ck>;
@@ -300,7 +297,7 @@
 		clock-div = <8>;
 	};
 
-	clkdiv32k_ck: clkdiv32k_ck {
+	clkdiv32k_ck: clock-clkdiv32k {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&clk_24mhz>;
@@ -308,7 +305,7 @@
 		clock-div = <732>;
 	};
 
-	l3_gclk: l3_gclk {
+	l3_gclk: clock-l3-gclk {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_core_m4_ck>;
@@ -316,14 +313,14 @@
 		clock-div = <1>;
 	};
 
-	pruss_ocp_gclk: pruss_ocp_gclk@530 {
+	pruss_ocp_gclk: clock-pruss-ocp-gclk@530 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
 		reg = <0x0530>;
 	};
 
-	mmu_fck: mmu_fck@914 {
+	mmu_fck: clock-mmu-fck-1@914 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_core_m4_ck>;
@@ -331,56 +328,56 @@
 		reg = <0x0914>;
 	};
 
-	timer1_fck: timer1_fck@528 {
+	timer1_fck: clock-timer1-fck@528 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
 		reg = <0x0528>;
 	};
 
-	timer2_fck: timer2_fck@508 {
+	timer2_fck: clock-timer2-fck@508 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 		reg = <0x0508>;
 	};
 
-	timer3_fck: timer3_fck@50c {
+	timer3_fck: clock-timer3-fck@50c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 		reg = <0x050c>;
 	};
 
-	timer4_fck: timer4_fck@510 {
+	timer4_fck: clock-timer4-fck@510 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 		reg = <0x0510>;
 	};
 
-	timer5_fck: timer5_fck@518 {
+	timer5_fck: clock-timer5-fck@518 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 		reg = <0x0518>;
 	};
 
-	timer6_fck: timer6_fck@51c {
+	timer6_fck: clock-timer6-fck@51c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 		reg = <0x051c>;
 	};
 
-	timer7_fck: timer7_fck@504 {
+	timer7_fck: clock-timer7-fck@504 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 		reg = <0x0504>;
 	};
 
-	usbotg_fck: usbotg_fck@47c {
+	usbotg_fck: clock-usbotg-fck-8@47c {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_per_ck>;
@@ -388,7 +385,7 @@
 		reg = <0x047c>;
 	};
 
-	dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+	dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_core_m4_ck>;
@@ -396,7 +393,7 @@
 		clock-div = <2>;
 	};
 
-	ieee5000_fck: ieee5000_fck@e4 {
+	ieee5000_fck: clock-ieee5000-fck-1@e4 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_core_m4_div2_ck>;
@@ -404,14 +401,14 @@
 		reg = <0x00e4>;
 	};
 
-	wdt1_fck: wdt1_fck@538 {
+	wdt1_fck: clock-wdt1-fck@538 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 		reg = <0x0538>;
 	};
 
-	l4_rtc_gclk: l4_rtc_gclk {
+	l4_rtc_gclk: clock-l4-rtc-gclk {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_core_m4_ck>;
@@ -419,7 +416,7 @@
 		clock-div = <2>;
 	};
 
-	l4hs_gclk: l4hs_gclk {
+	l4hs_gclk: clock-l4hs-gclk {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_core_m4_ck>;
@@ -427,7 +424,7 @@
 		clock-div = <1>;
 	};
 
-	l3s_gclk: l3s_gclk {
+	l3s_gclk: clock-l3s-gclk {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_core_m4_div2_ck>;
@@ -435,7 +432,7 @@
 		clock-div = <1>;
 	};
 
-	l4fw_gclk: l4fw_gclk {
+	l4fw_gclk: clock-l4fw-gclk {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_core_m4_div2_ck>;
@@ -443,7 +440,7 @@
 		clock-div = <1>;
 	};
 
-	l4ls_gclk: l4ls_gclk {
+	l4ls_gclk: clock-l4ls-gclk {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_core_m4_div2_ck>;
@@ -451,7 +448,7 @@
 		clock-div = <1>;
 	};
 
-	sysclk_div_ck: sysclk_div_ck {
+	sysclk_div_ck: clock-sysclk-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_core_m4_ck>;
@@ -459,7 +456,7 @@
 		clock-div = <1>;
 	};
 
-	cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+	cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_core_m5_ck>;
@@ -467,21 +464,21 @@
 		clock-div = <2>;
 	};
 
-	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
+	cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
 		reg = <0x0520>;
 	};
 
-	gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
+	gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 		reg = <0x053c>;
 	};
 
-	lcd_gclk: lcd_gclk@534 {
+	lcd_gclk: clock-lcd-gclk@534 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
@@ -489,7 +486,7 @@
 		ti,set-rate-parent;
 	};
 
-	mmc_clk: mmc_clk {
+	mmc_clk: clock-mmc {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_per_m2_ck>;
@@ -539,138 +536,138 @@
 };
 
 &prcm {
-	per_cm: per-cm@0 {
+	per_cm: clock@0 {
 		compatible = "ti,omap4-cm";
 		reg = <0x0 0x400>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0 0x0 0x400>;
 
-		l4ls_clkctrl: l4ls-clkctrl@38 {
+		l4ls_clkctrl: clock@38 {
 			compatible = "ti,clkctrl";
 			reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
 			#clock-cells = <2>;
 		};
 
-		l3s_clkctrl: l3s-clkctrl@1c {
+		l3s_clkctrl: clock@1c {
 			compatible = "ti,clkctrl";
 			reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
 			#clock-cells = <2>;
 		};
 
-		l3_clkctrl: l3-clkctrl@24 {
+		l3_clkctrl: clock@24 {
 			compatible = "ti,clkctrl";
 			reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
 			#clock-cells = <2>;
 		};
 
-		l4hs_clkctrl: l4hs-clkctrl@120 {
+		l4hs_clkctrl: clock@120 {
 			compatible = "ti,clkctrl";
 			reg = <0x120 0x4>;
 			#clock-cells = <2>;
 		};
 
-		pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 {
+		pruss_ocp_clkctrl: clock@e8 {
 			compatible = "ti,clkctrl";
 			reg = <0xe8 0x4>;
 			#clock-cells = <2>;
 		};
 
-		cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 {
+		cpsw_125mhz_clkctrl: clock@0 {
 			compatible = "ti,clkctrl";
 			reg = <0x0 0x18>;
 			#clock-cells = <2>;
 		};
 
-		lcdc_clkctrl: lcdc-clkctrl@18 {
+		lcdc_clkctrl: clock@18 {
 			compatible = "ti,clkctrl";
 			reg = <0x18 0x4>;
 			#clock-cells = <2>;
 		};
 
-		clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c {
+		clk_24mhz_clkctrl: clock@14c {
 			compatible = "ti,clkctrl";
 			reg = <0x14c 0x4>;
 			#clock-cells = <2>;
 		};
 	};
 
-	wkup_cm: wkup-cm@400 {
+	wkup_cm: clock@400 {
 		compatible = "ti,omap4-cm";
 		reg = <0x400 0x100>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0 0x400 0x100>;
 
-		l4_wkup_clkctrl: l4-wkup-clkctrl@0 {
+		l4_wkup_clkctrl: clock@0 {
 			compatible = "ti,clkctrl";
 			reg = <0x0 0x10>, <0xb4 0x24>;
 			#clock-cells = <2>;
 		};
 
-		l3_aon_clkctrl: l3-aon-clkctrl@14 {
+		l3_aon_clkctrl: clock@14 {
 			compatible = "ti,clkctrl";
 			reg = <0x14 0x4>;
 			#clock-cells = <2>;
 		};
 
-		l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 {
+		l4_wkup_aon_clkctrl: clock@b0 {
 			compatible = "ti,clkctrl";
 			reg = <0xb0 0x4>;
 			#clock-cells = <2>;
 		};
 	};
 
-	mpu_cm: mpu-cm@600 {
+	mpu_cm: clock@600 {
 		compatible = "ti,omap4-cm";
 		reg = <0x600 0x100>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0 0x600 0x100>;
 
-		mpu_clkctrl: mpu-clkctrl@0 {
+		mpu_clkctrl: clock@0 {
 			compatible = "ti,clkctrl";
 			reg = <0x0 0x8>;
 			#clock-cells = <2>;
 		};
 	};
 
-	l4_rtc_cm: l4-rtc-cm@800 {
+	l4_rtc_cm: clock@800 {
 		compatible = "ti,omap4-cm";
 		reg = <0x800 0x100>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0 0x800 0x100>;
 
-		l4_rtc_clkctrl: l4-rtc-clkctrl@0 {
+		l4_rtc_clkctrl: clock@0 {
 			compatible = "ti,clkctrl";
 			reg = <0x0 0x4>;
 			#clock-cells = <2>;
 		};
 	};
 
-	gfx_l3_cm: gfx-l3-cm@900 {
+	gfx_l3_cm: clock@900 {
 		compatible = "ti,omap4-cm";
 		reg = <0x900 0x100>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0 0x900 0x100>;
 
-		gfx_l3_clkctrl: gfx-l3-clkctrl@0 {
+		gfx_l3_clkctrl: clock@0 {
 			compatible = "ti,clkctrl";
 			reg = <0x0 0x8>;
 			#clock-cells = <2>;
 		};
 	};
 
-	l4_cefuse_cm: l4-cefuse-cm@a00 {
+	l4_cefuse_cm: clock@a00 {
 		compatible = "ti,omap4-cm";
 		reg = <0xa00 0x100>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0 0xa00 0x100>;
 
-		l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 {
+		l4_cefuse_clkctrl: clock@0 {
 			compatible = "ti,clkctrl";
 			reg = <0x0 0x24>;
 			#clock-cells = <2>;
diff --git a/arch/arm/dts/am33xx-l4.dtsi b/arch/arm/dts/am33xx-l4.dtsi
index 5892612..2264a1a 100644
--- a/arch/arm/dts/am33xx-l4.dtsi
+++ b/arch/arm/dts/am33xx-l4.dtsi
@@ -1327,7 +1327,7 @@
 				#mbox-cells = <1>;
 				ti,mbox-num-users = <4>;
 				ti,mbox-num-fifos = <8>;
-				mbox_wkupm3: wkup_m3 {
+				mbox_wkupm3: mbox-wkup-m3 {
 					ti,mbox-send-noirq;
 					ti,mbox-tx = <0 0 0>;
 					ti,mbox-rx = <0 0 3>;
@@ -1621,7 +1621,7 @@
 			};
 		};
 
-		target-module@ae000 {			/* 0x481ae000, ap 56 3a.0 */
+		target-module@ae000 {		/* 0x481ae000, ap 56 3a.0 */
 			compatible = "ti,sysc-omap2", "ti,sysc";
 			reg = <0xae000 0x4>,
 			      <0xae010 0x4>,
@@ -1798,7 +1798,7 @@
 				status = "disabled";
 				ranges = <0 0 0x1000>;
 
-				ecap0: ecap@100 {
+				ecap0: pwm@100 {
 					compatible = "ti,am3352-ecap",
 						     "ti,am33xx-ecap";
 					#pwm-cells = <3>;
@@ -1859,7 +1859,7 @@
 				status = "disabled";
 				ranges = <0 0 0x1000>;
 
-				ecap1: ecap@100 {
+				ecap1: pwm@100 {
 					compatible = "ti,am3352-ecap",
 						     "ti,am33xx-ecap";
 					#pwm-cells = <3>;
@@ -1920,7 +1920,7 @@
 				status = "disabled";
 				ranges = <0 0 0x1000>;
 
-				ecap2: ecap@100 {
+				ecap2: pwm@100 {
 					compatible = "ti,am3352-ecap",
 						     "ti,am33xx-ecap";
 					#pwm-cells = <3>;
diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi
index 5871344..3c7e038 100644
--- a/arch/arm/dts/am33xx.dtsi
+++ b/arch/arm/dts/am33xx.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for AM33XX SoC
  *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/bus/ti-sysc.h>
@@ -175,7 +172,7 @@
 	 * for the moment, just use a fake OCP bus entry to represent
 	 * the whole bus hierarchy.
 	 */
-	ocp {
+	ocp: ocp {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -325,11 +322,11 @@
 			ranges = <0x0 0x47810000 0x1000>;
 
 			mmc3: mmc@0 {
-			      compatible = "ti,am335-sdhci";
-			      ti,needs-special-reset;
-			      interrupts = <29>;
-			      reg = <0x0 0x1000>;
-			      status = "disabled";
+				compatible = "ti,am335-sdhci";
+				ti,needs-special-reset;
+				interrupts = <29>;
+				reg = <0x0 0x1000>;
+				status = "disabled";
 			};
 		};
 
diff --git a/arch/arm/dts/am3517-evm-ui.dtsi b/arch/arm/dts/am3517-evm-ui.dtsi
index 340e681..75ad421 100644
--- a/arch/arm/dts/am3517-evm-ui.dtsi
+++ b/arch/arm/dts/am3517-evm-ui.dtsi
@@ -70,61 +70,61 @@
 		compatible = "gpio-keys-polled";
 		poll-interval = <100>;
 
-		record {
+		key-record {
 			label = "Record";
-			linux,code = <KEY_RECORD>;
+			/* linux,code = <BTN_0>; */
 			gpios = <&tca6416_2 15 GPIO_ACTIVE_LOW>;
 		};
 
-		play {
+		key-play {
 			label = "Play";
 			linux,code = <KEY_PLAY>;
 			gpios = <&tca6416_2 14 GPIO_ACTIVE_LOW>;
 		};
 
-		Stop {
+		key-stop {
 			label = "Stop";
 			linux,code = <KEY_STOP>;
 			gpios = <&tca6416_2 13 GPIO_ACTIVE_LOW>;
 		};
 
-		fwd {
+		key-fwd {
 			label = "FWD";
 			linux,code = <KEY_FASTFORWARD>;
 			gpios = <&tca6416_2 12 GPIO_ACTIVE_LOW>;
 		};
 
-		rwd {
+		key-rwd {
 			label = "RWD";
 			linux,code = <KEY_REWIND>;
 			gpios = <&tca6416_2 11 GPIO_ACTIVE_LOW>;
 		};
 
-		shift {
+		key-shift {
 			label = "Shift";
 			linux,code = <KEY_LEFTSHIFT>;
 			gpios = <&tca6416_2 10 GPIO_ACTIVE_LOW>;
 		};
 
-		Mode {
+		key-mode {
 			label = "Mode";
 			linux,code = <BTN_MODE>;
 			gpios = <&tca6416_2 9 GPIO_ACTIVE_LOW>;
 		};
 
-		Menu {
+		key-menu {
 			label = "Menu";
 			linux,code = <KEY_MENU>;
 			gpios = <&tca6416_2 8 GPIO_ACTIVE_LOW>;
 		};
 
-		Up {
+		key-up {
 			label = "Up";
 			linux,code = <KEY_UP>;
 			gpios = <&tca6416_2 7 GPIO_ACTIVE_LOW>;
 		};
 
-		Down {
+		key-down {
 			label = "Down";
 			linux,code = <KEY_DOWN>;
 			gpios = <&tca6416_2 6 GPIO_ACTIVE_LOW>;
@@ -137,14 +137,14 @@
 	tlv320aic23_1: codec@1a {
 		compatible = "ti,tlv320aic23";
 		reg = <0x1a>;
-		#sound-dai-cells= <0>;
+		#sound-dai-cells = <0>;
 		status = "okay";
 	};
 
 	tlv320aic23_2: codec@1b {
 		compatible = "ti,tlv320aic23";
 		reg = <0x1b>;
-		#sound-dai-cells= <0>;
+		#sound-dai-cells = <0>;
 		status = "okay";
 	};
 };
@@ -154,7 +154,7 @@
 	tlv320aic23_3: codec@1a {
 		compatible = "ti,tlv320aic23";
 		reg = <0x1a>;
-		#sound-dai-cells= <0>;
+		#sound-dai-cells = <0>;
 		status = "okay";
 	};
 
diff --git a/arch/arm/dts/am3517-evm.dts b/arch/arm/dts/am3517-evm.dts
index a01f9cf..d21bb2c 100644
--- a/arch/arm/dts/am3517-evm.dts
+++ b/arch/arm/dts/am3517-evm.dts
@@ -26,66 +26,66 @@
 		reg = <0x80000000 0x10000000>; /* 256 MB */
 	};
 
-        vmmc_fixed: vmmc {
-                compatible = "regulator-fixed";
-                regulator-name = "vmmc_fixed";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-        };
+	vmmc_fixed: vmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "vmmc_fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
 
 	gpio-keys {
 		compatible = "gpio-keys-polled";
 		poll-interval = <100>;
 
-		user_pb {
+		button-user {
 			label = "User Push Button";
 			linux,code = <BTN_0>;
 			gpios = <&tca6416 5 GPIO_ACTIVE_LOW>;
 		};
 
-		user_sw_1 {
+		switch-1 {
 			label = "User Switch 1";
 			linux,code = <BTN_1>;
 			gpios = <&tca6416 8 GPIO_ACTIVE_LOW>;
 		};
 
-		user_sw_2 {
+		switch-2 {
 			label = "User Switch 2";
 			linux,code = <BTN_2>;
 			gpios = <&tca6416 9 GPIO_ACTIVE_LOW>;
 		};
 
-		user_sw_3 {
+		switch-3 {
 			label = "User Switch 3";
 			linux,code = <BTN_3>;
 			gpios = <&tca6416 10 GPIO_ACTIVE_LOW>;
 		};
 
-		user_sw_4 {
+		switch-4 {
 			label = "User Switch 4";
 			linux,code = <BTN_4>;
 			gpios = <&tca6416 11 GPIO_ACTIVE_LOW>;
 		};
 
-		user_sw_5 {
+		switch-5 {
 			label = "User Switch 5";
 			linux,code = <BTN_5>;
 			gpios = <&tca6416 12 GPIO_ACTIVE_LOW>;
 		};
 
-		user_sw_6 {
+		switch-6 {
 			label = "User Switch 6";
 			linux,code = <BTN_6>;
 			gpios = <&tca6416 13 GPIO_ACTIVE_LOW>;
 		};
 
-		user_sw_7 {
+		switch-7 {
 			label = "User Switch 7";
 			linux,code = <BTN_7>;
 			gpios = <&tca6416 14 GPIO_ACTIVE_LOW>;
 		};
 
-		user_sw_8 {
+		switch-8 {
 			label = "User Switch 8";
 			linux,code = <BTN_8>;
 			gpios = <&tca6416 15 GPIO_ACTIVE_LOW>;
@@ -150,7 +150,7 @@
 		enable-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* gpio_182 */
 	};
 
-	pwm11: dmtimer-pwm@11 {
+	pwm11: pwm-11 {
 		compatible = "ti,omap-dmtimer-pwm";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwm_pins>;
@@ -176,7 +176,7 @@
 };
 
 &davinci_mdio {
-	     status = "okay";
+	status = "okay";
 };
 
 &dss {
@@ -223,7 +223,7 @@
 };
 
 &mmc3 {
-      status = "disabled";
+	status = "disabled";
 };
 
 &usbhshost {
diff --git a/arch/arm/dts/am3517.dtsi b/arch/arm/dts/am3517.dtsi
index 23ea381..2633fae 100644
--- a/arch/arm/dts/am3517.dtsi
+++ b/arch/arm/dts/am3517.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for am3517 SoC
  *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "omap3.dtsi"
@@ -43,7 +40,7 @@
 			clock-names = "ick";
 		};
 
-		davinci_mdio: ethernet@5c030000 {
+		davinci_mdio: mdio@5c030000 {
 			compatible = "ti,davinci_mdio";
 			ti,hwmods = "davinci_mdio";
 			status = "disabled";
diff --git a/arch/arm/dts/am35xx-clocks.dtsi b/arch/arm/dts/am35xx-clocks.dtsi
index 00dd1f0..220d0a5 100644
--- a/arch/arm/dts/am35xx-clocks.dtsi
+++ b/arch/arm/dts/am35xx-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP3 clock data
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 &scm_clocks {
 	emac_ick: emac_ick@32c {
diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi
index 6f60a32..42a0307 100644
--- a/arch/arm/dts/am4372.dtsi
+++ b/arch/arm/dts/am4372.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for AM4372 SoC
  *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/gpio/gpio.h>
diff --git a/arch/arm/dts/am437x-gp-evm.dts b/arch/arm/dts/am437x-gp-evm.dts
index 21f7691..bbd61f8 100644
--- a/arch/arm/dts/am437x-gp-evm.dts
+++ b/arch/arm/dts/am437x-gp-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /* AM437x GP EVM */
@@ -138,139 +135,138 @@
 
 	i2c0_pins: i2c0_pins {
 		pinctrl-single,pins = <
-			0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
-			0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
+			AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
+			AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
 		>;
 	};
 
 	i2c1_pins: i2c1_pins {
 		pinctrl-single,pins = <
-			0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
-			0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
+			AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
+			AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
 		>;
 	};
 
 	mmc1_pins: pinmux_mmc1_pins {
 		pinctrl-single,pins = <
-			0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+			AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
 		>;
 	};
 
 	ecap0_pins: backlight_pins {
 		pinctrl-single,pins = <
-			0x164 MUX_MODE0       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+			AM4372_IOPAD(0x964, MUX_MODE0)       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
 		>;
 	};
 
 	pixcir_ts_pins: pixcir_ts_pins {
 		pinctrl-single,pins = <
-			0x264 (PIN_INPUT_PULLUP | MUX_MODE7)  /* spi2_d0.gpio3_22 */
+			AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7)  /* spi2_d0.gpio3_22 */
 		>;
 	};
 
 	cpsw_default: cpsw_default {
 		pinctrl-single,pins = <
 			/* Slave 1 */
-			0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txen.rgmii1_txen */
-			0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxdv.rgmii1_rxctl */
-			0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_txd3 */
-			0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_txd2 */
-			0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_txd1 */
-			0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_txd0 */
-			0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txclk.rmii1_tclk */
-			0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxclk.rmii1_rclk */
-			0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rxd3 */
-			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rxd2 */
-			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rxd1 */
-			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rxd0 */
+			AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txen.rgmii1_txen */
+			AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxdv.rgmii1_rxctl */
+			AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_txd3 */
+			AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_txd2 */
+			AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_txd1 */
+			AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_txd0 */
+			AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txclk.rmii1_tclk */
+			AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxclk.rmii1_rclk */
+			AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rxd3 */
+			AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rxd2 */
+			AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rxd1 */
+			AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rxd0 */
 		>;
 	};
 
 	cpsw_sleep: cpsw_sleep {
 		pinctrl-single,pins = <
 			/* Slave 1 reset value */
-			0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
 		>;
 	};
 
 	davinci_mdio_default: davinci_mdio_default {
 		pinctrl-single,pins = <
 			/* MDIO */
-			0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
-			0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+			AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
+			AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
 		>;
 	};
 
 	davinci_mdio_sleep: davinci_mdio_sleep {
 		pinctrl-single,pins = <
 			/* MDIO reset value */
-			0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 		>;
 	};
 
 	nand_flash_x8: nand_flash_x8 {
 		pinctrl-single,pins = <
-			0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* spi2_cs0.gpio/eMMCorNANDsel */
-			0x0  (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
-			0x4  (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
-			0x8  (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
-			0xc  (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
-			0x10 (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
-			0x14 (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
-			0x18 (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
-			0x1c (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
-			0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
-			0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpmc_wpn */
-			0x7c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
-			0x90 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
-			0x94 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
-			0x98 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
-			0x9c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
+			AM4372_IOPAD(0x800, PIN_INPUT  | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
+			AM4372_IOPAD(0x804, PIN_INPUT  | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
+			AM4372_IOPAD(0x808, PIN_INPUT  | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
+			AM4372_IOPAD(0x80c, PIN_INPUT  | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
+			AM4372_IOPAD(0x810, PIN_INPUT  | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
+			AM4372_IOPAD(0x814, PIN_INPUT  | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
+			AM4372_IOPAD(0x818, PIN_INPUT  | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
+			AM4372_IOPAD(0x81c, PIN_INPUT  | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
+			AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
+			AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpmc_wpn */
+			AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
+			AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
+			AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
+			AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
+			AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
 		>;
 	};
 
 	dss_pins: dss_pins {
 		pinctrl-single,pins = <
-			0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
-			0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
-			0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
-			0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
-			0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
-			0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
-			0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
-			0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
-			0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
-			0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-			0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-			0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
-			0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-			0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-			0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-			0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
-			0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-			0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-			0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-			0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
-			0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-			0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-			0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-			0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
-			0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
-			0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
-			0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
-			0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
+			AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
+			AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
+			AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
+			AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
+			AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
+			AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
+			AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
+			AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
+			AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
+			AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
+			AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
+			AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
+			AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
+			AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
 
 		>;
 	};
@@ -278,140 +274,140 @@
 	lcd_pins: lcd_pins {
 		pinctrl-single,pins = <
 			/* GPIO 5_8 to select LCD / HDMI */
-			0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
+			AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7)
 		>;
 	};
 
 	dcan0_default: dcan0_default_pins {
 		pinctrl-single,pins = <
-			0x178 (PIN_OUTPUT | MUX_MODE2)		/* uart1_ctsn.d_can0_tx */
-			0x17c (PIN_INPUT_PULLUP | MUX_MODE2)	/* uart1_rtsn.d_can0_rx */
+			AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2)		/* uart1_ctsn.d_can0_tx */
+			AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2)	/* uart1_rtsn.d_can0_rx */
 		>;
 	};
 
 	dcan1_default: dcan1_default_pins {
 		pinctrl-single,pins = <
-			0x180 (PIN_OUTPUT | MUX_MODE2)		/* uart1_rxd.d_can1_tx */
-			0x184 (PIN_INPUT_PULLUP | MUX_MODE2)	/* uart1_txd.d_can1_rx */
+			AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2)		/* uart1_rxd.d_can1_tx */
+			AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2)	/* uart1_txd.d_can1_rx */
 		>;
 	};
 
 	vpfe0_pins_default: vpfe0_pins_default {
 		pinctrl-single,pins = <
-			0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_hd mode 0*/
-			0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_vd mode 0*/
-			0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_pclk mode 0*/
-			0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data8 mode 0*/
-			0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data9 mode 0*/
-			0x208 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data0 mode 0*/
-			0x20C (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data1 mode 0*/
-			0x210 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data2 mode 0*/
-			0x214 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data3 mode 0*/
-			0x218 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data4 mode 0*/
-			0x21C (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data5 mode 0*/
-			0x220 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data6 mode 0*/
-			0x224 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data7 mode 0*/
+			AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_hd mode 0*/
+			AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_vd mode 0*/
+			AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_pclk mode 0*/
+			AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data8 mode 0*/
+			AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data9 mode 0*/
+			AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data0 mode 0*/
+			AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data1 mode 0*/
+			AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data2 mode 0*/
+			AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data3 mode 0*/
+			AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data4 mode 0*/
+			AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data5 mode 0*/
+			AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data6 mode 0*/
+			AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data7 mode 0*/
 		>;
 	};
 
 	vpfe0_pins_sleep: vpfe0_pins_sleep {
 		pinctrl-single,pins = <
-			0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_hd mode 0*/
-			0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_vd mode 0*/
-			0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_pclk mode 0*/
-			0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data8 mode 0*/
-			0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data9 mode 0*/
-			0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data0 mode 0*/
-			0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data1 mode 0*/
-			0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data2 mode 0*/
-			0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data3 mode 0*/
-			0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data4 mode 0*/
-			0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data5 mode 0*/
-			0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data6 mode 0*/
-			0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data7 mode 0*/
+			AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_hd mode 0*/
+			AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_vd mode 0*/
+			AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_pclk mode 0*/
+			AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data8 mode 0*/
+			AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data9 mode 0*/
+			AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data0 mode 0*/
+			AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data1 mode 0*/
+			AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data2 mode 0*/
+			AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data3 mode 0*/
+			AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data4 mode 0*/
+			AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data5 mode 0*/
+			AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data6 mode 0*/
+			AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data7 mode 0*/
 		>;
 	};
 
 	vpfe1_pins_default: vpfe1_pins_default {
 		pinctrl-single,pins = <
-			0x1CC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0*/
-			0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0*/
-			0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0*/
-			0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0*/
-			0x1DC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0*/
-			0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0*/
-			0x1EC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0*/
-			0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0*/
-			0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0*/
-			0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0*/
-			0x1FC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0*/
-			0x200 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0*/
-			0x204 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0*/
+			AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0*/
+			AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0*/
+			AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0*/
+			AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0*/
+			AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0*/
+			AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0*/
+			AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0*/
+			AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0*/
+			AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0*/
+			AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0*/
+			AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0*/
+			AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0*/
+			AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0*/
 		>;
 	};
 
 	vpfe1_pins_sleep: vpfe1_pins_sleep {
 		pinctrl-single,pins = <
-			0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data9 mode 0*/
-			0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data8 mode 0*/
-			0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_hd mode 0*/
-			0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_vd mode 0*/
-			0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_pclk mode 0*/
-			0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data0 mode 0*/
-			0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data1 mode 0*/
-			0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data2 mode 0*/
-			0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data3 mode 0*/
-			0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data4 mode 0*/
-			0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data5 mode 0*/
-			0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data6 mode 0*/
-			0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data7 mode 0*/
+			AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data9 mode 0*/
+			AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data8 mode 0*/
+			AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_hd mode 0*/
+			AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_vd mode 0*/
+			AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_pclk mode 0*/
+			AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data0 mode 0*/
+			AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data1 mode 0*/
+			AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data2 mode 0*/
+			AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data3 mode 0*/
+			AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data4 mode 0*/
+			AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data5 mode 0*/
+			AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data6 mode 0*/
+			AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data7 mode 0*/
 		>;
 	};
 
 	mmc3_pins_default: pinmux_mmc3_pins_default {
 		pinctrl-single,pins = <
-			0x8c (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_clk.mmc2_clk */
-			0x88 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_csn3.mmc2_cmd */
-			0x44 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a1.mmc2_dat0 */
-			0x48 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a2.mmc2_dat1 */
-			0x4c (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a3.mmc2_dat2 */
-			0x78 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_be1n.mmc2_dat3 */
+			AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_clk.mmc2_clk */
+			AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_csn3.mmc2_cmd */
+			AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a1.mmc2_dat0 */
+			AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a2.mmc2_dat1 */
+			AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a3.mmc2_dat2 */
+			AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_be1n.mmc2_dat3 */
 		>;
 	};
 
 	mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
 		pinctrl-single,pins = <
-			0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_clk.mmc2_clk */
-			0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_csn3.mmc2_cmd */
-			0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a1.mmc2_dat0 */
-			0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a2.mmc2_dat1 */
-			0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a3.mmc2_dat2 */
-			0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_be1n.mmc2_dat3 */
+			AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_clk.mmc2_clk */
+			AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_csn3.mmc2_cmd */
+			AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a1.mmc2_dat0 */
+			AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a2.mmc2_dat1 */
+			AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a3.mmc2_dat2 */
+			AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_be1n.mmc2_dat3 */
 		>;
 	};
 
 	wlan_pins_default: pinmux_wlan_pins_default {
 		pinctrl-single,pins = <
-			0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)		/* gpmc_a4.gpio1_20 WL_EN */
-			0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)	/* gpmc_a7.gpio1_23 WL_IRQ*/
-			0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)		/* gpmc_a0.gpio1_16 BT_EN*/
+			AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)		/* gpmc_a4.gpio1_20 WL_EN */
+			AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)	/* gpmc_a7.gpio1_23 WL_IRQ*/
+			AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7)		/* gpmc_a0.gpio1_16 BT_EN*/
 		>;
 	};
 
 	wlan_pins_sleep: pinmux_wlan_pins_sleep {
 		pinctrl-single,pins = <
-			0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)		/* gpmc_a4.gpio1_20 WL_EN */
-			0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)	/* gpmc_a7.gpio1_23 WL_IRQ*/
-			0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7)		/* gpmc_a0.gpio1_16 BT_EN*/
+			AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)		/* gpmc_a4.gpio1_20 WL_EN */
+			AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)	/* gpmc_a7.gpio1_23 WL_IRQ*/
+			AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7)		/* gpmc_a0.gpio1_16 BT_EN*/
 		>;
 	};
 
 	uart3_pins: uart3_pins {
 		pinctrl-single,pins = <
-			0x228 (PIN_INPUT | MUX_MODE0)		/* uart3_rxd.uart3_rxd */
-			0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
-			0x230 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart3_ctsn.uart3_ctsn */
-			0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
+			AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0)		/* uart3_rxd.uart3_rxd */
+			AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
+			AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart3_ctsn.uart3_ctsn */
+			AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
 		>;
 	};
 };
diff --git a/arch/arm/dts/am437x-idk-evm.dts b/arch/arm/dts/am437x-idk-evm.dts
index 8f6824c..2c94c87 100644
--- a/arch/arm/dts/am437x-idk-evm.dts
+++ b/arch/arm/dts/am437x-idk-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/am437x-sk-evm.dts b/arch/arm/dts/am437x-sk-evm.dts
index 66a3bd1..f1bb009 100644
--- a/arch/arm/dts/am437x-sk-evm.dts
+++ b/arch/arm/dts/am437x-sk-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /* AM437x SK EVM */
@@ -140,250 +137,250 @@
 &am43xx_pinmux {
 	matrix_keypad_pins: matrix_keypad_pins {
 		pinctrl-single,pins = <
-			0x24c (PIN_OUTPUT | MUX_MODE7)	/* gpio5_13.gpio5_13 */
-			0x250 (PIN_OUTPUT | MUX_MODE7)	/* spi4_sclk.gpio5_4 */
-			0x254 (PIN_INPUT | MUX_MODE7)	/* spi4_d0.gpio5_5 */
-			0x258 (PIN_INPUT | MUX_MODE7)	/* spi4_d1.gpio5_5 */
+			AM4372_IOPAD(0xa4c, PIN_OUTPUT | MUX_MODE7)	/* gpio5_13.gpio5_13 */
+			AM4372_IOPAD(0xa50, PIN_OUTPUT | MUX_MODE7)	/* spi4_sclk.gpio5_4 */
+			AM4372_IOPAD(0xa54, PIN_INPUT | MUX_MODE7)	/* spi4_d0.gpio5_5 */
+			AM4372_IOPAD(0xa58, PIN_INPUT | MUX_MODE7)	/* spi4_d1.gpio5_5 */
 		>;
 	};
 
 	leds_pins: leds_pins {
 		pinctrl-single,pins = <
-			0x228 (PIN_OUTPUT | MUX_MODE7)	/* uart3_rxd.gpio5_2 */
-			0x22c (PIN_OUTPUT | MUX_MODE7)	/* uart3_txd.gpio5_3 */
-			0x230 (PIN_OUTPUT | MUX_MODE7)	/* uart3_ctsn.gpio5_0 */
-			0x234 (PIN_OUTPUT | MUX_MODE7)	/* uart3_rtsn.gpio5_1 */
+			AM4372_IOPAD(0xa28, PIN_OUTPUT | MUX_MODE7)	/* uart3_rxd.gpio5_2 */
+			AM4372_IOPAD(0xa2c, PIN_OUTPUT | MUX_MODE7)	/* uart3_txd.gpio5_3 */
+			AM4372_IOPAD(0xa30, PIN_OUTPUT | MUX_MODE7)	/* uart3_ctsn.gpio5_0 */
+			AM4372_IOPAD(0xa34, PIN_OUTPUT | MUX_MODE7)	/* uart3_rtsn.gpio5_1 */
 		>;
 	};
 
 	i2c0_pins: i2c0_pins {
 		pinctrl-single,pins = <
-			0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
-			0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
+			AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
+			AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
 		>;
 	};
 
 	i2c1_pins: i2c1_pins {
 		pinctrl-single,pins = <
-			0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
-			0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
+			AM4372_IOPAD(0x95c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
+			AM4372_IOPAD(0x958, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
 		>;
 	};
 
 	mmc1_pins: pinmux_mmc1_pins {
 		pinctrl-single,pins = <
-			0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
-			0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
-			0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
-			0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
-			0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
-			0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
-			0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+			AM4372_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
+			AM4372_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
+			AM4372_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
+			AM4372_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
+			AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
+			AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
+			AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
 		>;
 	};
 
 	ecap0_pins: backlight_pins {
 		pinctrl-single,pins = <
-			0x164 (PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
+			AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
 		>;
 	};
 
 	edt_ft5306_ts_pins: edt_ft5306_ts_pins {
 		pinctrl-single,pins = <
-			0x74 (PIN_INPUT | MUX_MODE7)	/* gpmc_wpn.gpio0_31 */
-			0x78 (PIN_OUTPUT | MUX_MODE7)	/* gpmc_be1n.gpio1_28 */
+			AM4372_IOPAD(0x874, PIN_INPUT | MUX_MODE7)	/* gpmc_wpn.gpio0_31 */
+			AM4372_IOPAD(0x878, PIN_OUTPUT | MUX_MODE7)	/* gpmc_be1n.gpio1_28 */
 		>;
 	};
 
 	vpfe0_pins_default: vpfe0_pins_default {
 		pinctrl-single,pins = <
-			0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_hd mode 0*/
-			0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_vd mode 0*/
-			0x1b8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_field mode 0*/
-			0x1bc (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_wen mode 0*/
-			0x1c0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_pclk mode 0*/
-			0x1c4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data8 mode 0*/
-			0x1c8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data9 mode 0*/
-			0x208 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data0 mode 0*/
-			0x20c (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data1 mode 0*/
-			0x210 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data2 mode 0*/
-			0x214 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data3 mode 0*/
-			0x218 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data4 mode 0*/
-			0x21c (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data5 mode 0*/
-			0x220 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data6 mode 0*/
-			0x224 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data7 mode 0*/
+			AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_hd mode 0*/
+			AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_vd mode 0*/
+			AM4372_IOPAD(0x9b8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_field mode 0*/
+			AM4372_IOPAD(0x9bc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_wen mode 0*/
+			AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_pclk mode 0*/
+			AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data8 mode 0*/
+			AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data9 mode 0*/
+			AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data0 mode 0*/
+			AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data1 mode 0*/
+			AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data2 mode 0*/
+			AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data3 mode 0*/
+			AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data4 mode 0*/
+			AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data5 mode 0*/
+			AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data6 mode 0*/
+			AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data7 mode 0*/
 		>;
 	};
 
 	vpfe0_pins_sleep: vpfe0_pins_sleep {
 		pinctrl-single,pins = <
-			0x1b0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-			0x1b4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-			0x1b8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-			0x1bc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-			0x1c0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-			0x1c4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-			0x1c8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-			0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-			0x20c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-			0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-			0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-			0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-			0x21c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-			0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-			0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+			AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+			AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+			AM4372_IOPAD(0x9b8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+			AM4372_IOPAD(0x9bc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+			AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+			AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+			AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+			AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+			AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+			AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+			AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+			AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+			AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+			AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+			AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 		>;
 	};
 
 	cpsw_default: cpsw_default {
 		pinctrl-single,pins = <
 			/* Slave 1 */
-			0x12c (PIN_OUTPUT | MUX_MODE2)	/* mii1_txclk.rmii1_tclk */
-			0x114 (PIN_OUTPUT | MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
-			0x128 (PIN_OUTPUT | MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
-			0x124 (PIN_OUTPUT | MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
-			0x120 (PIN_OUTPUT | MUX_MODE2)	/* mii1_txd0.rgmii1_td2 */
-			0x11c (PIN_OUTPUT | MUX_MODE2)	/* mii1_txd1.rgmii1_td3 */
-			0x130 (PIN_INPUT | MUX_MODE2)	/* mii1_rxclk.rmii1_rclk */
-			0x118 (PIN_INPUT | MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
-			0x140 (PIN_INPUT | MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
-			0x13c (PIN_INPUT | MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
-			0x138 (PIN_INPUT | MUX_MODE2)	/* mii1_rxd0.rgmii1_rd2 */
-			0x134 (PIN_INPUT | MUX_MODE2)	/* mii1_rxd1.rgmii1_rd3 */
+			AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE2)	/* mii1_txclk.rmii1_tclk */
+			AM4372_IOPAD(0x914, PIN_OUTPUT | MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
+			AM4372_IOPAD(0x928, PIN_OUTPUT | MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
+			AM4372_IOPAD(0x924, PIN_OUTPUT | MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
+			AM4372_IOPAD(0x920, PIN_OUTPUT | MUX_MODE2)	/* mii1_txd0.rgmii1_td2 */
+			AM4372_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE2)	/* mii1_txd1.rgmii1_td3 */
+			AM4372_IOPAD(0x930, PIN_INPUT | MUX_MODE2)	/* mii1_rxclk.rmii1_rclk */
+			AM4372_IOPAD(0x918, PIN_INPUT | MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
+			AM4372_IOPAD(0x940, PIN_INPUT | MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
+			AM4372_IOPAD(0x93c, PIN_INPUT | MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
+			AM4372_IOPAD(0x938, PIN_INPUT | MUX_MODE2)	/* mii1_rxd0.rgmii1_rd2 */
+			AM4372_IOPAD(0x934, PIN_INPUT | MUX_MODE2)	/* mii1_rxd1.rgmii1_rd3 */
 
 			/* Slave 2 */
-			0x58 (PIN_OUTPUT | MUX_MODE2)	/* gpmc_a6.rgmii2_tclk */
-			0x40 (PIN_OUTPUT | MUX_MODE2)	/* gpmc_a0.rgmii2_tctl */
-			0x54 (PIN_OUTPUT | MUX_MODE2)	/* gpmc_a5.rgmii2_td0 */
-			0x50 (PIN_OUTPUT | MUX_MODE2)	/* gpmc_a4.rgmii2_td1 */
-			0x4c (PIN_OUTPUT | MUX_MODE2)	/* gpmc_a3.rgmii2_td2 */
-			0x48 (PIN_OUTPUT | MUX_MODE2)	/* gpmc_a2.rgmii2_td3 */
-			0x5c (PIN_INPUT | MUX_MODE2)	/* gpmc_a7.rgmii2_rclk */
-			0x44 (PIN_INPUT | MUX_MODE2)	/* gpmc_a1.rgmii2_rtcl */
-			0x6c (PIN_INPUT | MUX_MODE2)	/* gpmc_a11.rgmii2_rd0 */
-			0x68 (PIN_INPUT | MUX_MODE2)	/* gpmc_a10.rgmii2_rd1 */
-			0x64 (PIN_INPUT | MUX_MODE2)	/* gpmc_a9.rgmii2_rd2 */
-			0x60 (PIN_INPUT | MUX_MODE2)	/* gpmc_a8.rgmii2_rd3 */
+			AM4372_IOPAD(0x858, PIN_OUTPUT | MUX_MODE2)	/* gpmc_a6.rgmii2_tclk */
+			AM4372_IOPAD(0x840, PIN_OUTPUT | MUX_MODE2)	/* gpmc_a0.rgmii2_tctl */
+			AM4372_IOPAD(0x854, PIN_OUTPUT | MUX_MODE2)	/* gpmc_a5.rgmii2_td0 */
+			AM4372_IOPAD(0x850, PIN_OUTPUT | MUX_MODE2)	/* gpmc_a4.rgmii2_td1 */
+			AM4372_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE2)	/* gpmc_a3.rgmii2_td2 */
+			AM4372_IOPAD(0x848, PIN_OUTPUT | MUX_MODE2)	/* gpmc_a2.rgmii2_td3 */
+			AM4372_IOPAD(0x85c, PIN_INPUT | MUX_MODE2)	/* gpmc_a7.rgmii2_rclk */
+			AM4372_IOPAD(0x844, PIN_INPUT | MUX_MODE2)	/* gpmc_a1.rgmii2_rtcl */
+			AM4372_IOPAD(0x86c, PIN_INPUT | MUX_MODE2)	/* gpmc_a11.rgmii2_rd0 */
+			AM4372_IOPAD(0x868, PIN_INPUT | MUX_MODE2)	/* gpmc_a10.rgmii2_rd1 */
+			AM4372_IOPAD(0x864, PIN_INPUT | MUX_MODE2)	/* gpmc_a9.rgmii2_rd2 */
+			AM4372_IOPAD(0x860, PIN_INPUT | MUX_MODE2)	/* gpmc_a8.rgmii2_rd3 */
 		>;
 	};
 
 	cpsw_sleep: cpsw_sleep {
 		pinctrl-single,pins = <
 			/* Slave 1 reset value */
-			0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
 
 			/* Slave 2 reset value */
-			0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
 		>;
 	};
 
 	davinci_mdio_default: davinci_mdio_default {
 		pinctrl-single,pins = <
 			/* MDIO */
-			0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
-			0x14c (PIN_OUTPUT | MUX_MODE0)			/* mdio_clk.mdio_clk */
+			AM4372_IOPAD(0x948, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
+			AM4372_IOPAD(0x94c, PIN_OUTPUT | MUX_MODE0)			/* mdio_clk.mdio_clk */
 		>;
 	};
 
 	davinci_mdio_sleep: davinci_mdio_sleep {
 		pinctrl-single,pins = <
 			/* MDIO reset value */
-			0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-			0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 		>;
 	};
 
 	dss_pins: dss_pins {
 		pinctrl-single,pins = <
-			0x020 (PIN_OUTPUT | MUX_MODE1)	/* gpmc ad 8 -> DSS DATA 23 */
-			0x024 (PIN_OUTPUT | MUX_MODE1)
-			0x028 (PIN_OUTPUT | MUX_MODE1)
-			0x02c (PIN_OUTPUT | MUX_MODE1)
-			0x030 (PIN_OUTPUT | MUX_MODE1)
-			0x034 (PIN_OUTPUT | MUX_MODE1)
-			0x038 (PIN_OUTPUT | MUX_MODE1)
-			0x03c (PIN_OUTPUT | MUX_MODE1)	/* gpmc ad 15 -> DSS DATA 16 */
-			0x0a0 (PIN_OUTPUT | MUX_MODE0)	/* DSS DATA 0 */
-			0x0a4 (PIN_OUTPUT | MUX_MODE0)
-			0x0a8 (PIN_OUTPUT | MUX_MODE0)
-			0x0ac (PIN_OUTPUT | MUX_MODE0)
-			0x0b0 (PIN_OUTPUT | MUX_MODE0)
-			0x0b4 (PIN_OUTPUT | MUX_MODE0)
-			0x0b8 (PIN_OUTPUT | MUX_MODE0)
-			0x0bc (PIN_OUTPUT | MUX_MODE0)
-			0x0c0 (PIN_OUTPUT | MUX_MODE0)
-			0x0c4 (PIN_OUTPUT | MUX_MODE0)
-			0x0c8 (PIN_OUTPUT | MUX_MODE0)
-			0x0cc (PIN_OUTPUT | MUX_MODE0)
-			0x0d0 (PIN_OUTPUT | MUX_MODE0)
-			0x0d4 (PIN_OUTPUT | MUX_MODE0)
-			0x0d8 (PIN_OUTPUT | MUX_MODE0)
-			0x0dc (PIN_OUTPUT | MUX_MODE0)	/* DSS DATA 15 */
-			0x0e0 (PIN_OUTPUT | MUX_MODE0)	/* DSS VSYNC */
-			0x0e4 (PIN_OUTPUT | MUX_MODE0)	/* DSS HSYNC */
-			0x0e8 (PIN_OUTPUT | MUX_MODE0)	/* DSS PCLK */
-			0x0ec (PIN_OUTPUT | MUX_MODE0)	/* DSS AC BIAS EN */
+			AM4372_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1)	/* gpmc ad 8 -> DSS DATA 23 */
+			AM4372_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1)
+			AM4372_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1)
+			AM4372_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1)
+			AM4372_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1)
+			AM4372_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1)
+			AM4372_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1)
+			AM4372_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1)	/* gpmc ad 15 -> DSS DATA 16 */
+			AM4372_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)	/* DSS DATA 0 */
+			AM4372_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)
+			AM4372_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)
+			AM4372_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)
+			AM4372_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)
+			AM4372_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)
+			AM4372_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)
+			AM4372_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)
+			AM4372_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)
+			AM4372_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)
+			AM4372_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)
+			AM4372_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)
+			AM4372_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)
+			AM4372_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)
+			AM4372_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)
+			AM4372_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)	/* DSS DATA 15 */
+			AM4372_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)	/* DSS VSYNC */
+			AM4372_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)	/* DSS HSYNC */
+			AM4372_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)	/* DSS PCLK */
+			AM4372_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)	/* DSS AC BIAS EN */
 
 		>;
 	};
 
 	qspi_pins: qspi_pins {
 		pinctrl-single,pins = <
-			0x7c (PIN_OUTPUT | MUX_MODE3)	/* gpmc_csn0.qspi_csn */
-			0x88 (PIN_OUTPUT | MUX_MODE2)	/* gpmc_csn3.qspi_clk */
-			0x90 (PIN_INPUT | MUX_MODE3)	/* gpmc_advn_ale.qspi_d0 */
-			0x94 (PIN_INPUT | MUX_MODE3)	/* gpmc_oen_ren.qspi_d1 */
-			0x98 (PIN_INPUT | MUX_MODE3)	/* gpmc_wen.qspi_d2 */
-			0x9c (PIN_INPUT | MUX_MODE3)	/* gpmc_be0n_cle.qspi_d3 */
+			AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE3)	/* gpmc_csn0.qspi_csn */
+			AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2)	/* gpmc_csn3.qspi_clk */
+			AM4372_IOPAD(0x890, PIN_INPUT | MUX_MODE3)	/* gpmc_advn_ale.qspi_d0 */
+			AM4372_IOPAD(0x894, PIN_INPUT | MUX_MODE3)	/* gpmc_oen_ren.qspi_d1 */
+			AM4372_IOPAD(0x898, PIN_INPUT | MUX_MODE3)	/* gpmc_wen.qspi_d2 */
+			AM4372_IOPAD(0x89c, PIN_INPUT | MUX_MODE3)	/* gpmc_be0n_cle.qspi_d3 */
 		>;
 	};
 
 	mcasp1_pins: mcasp1_pins {
 		pinctrl-single,pins = <
-			0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4)	/* mii1_crs.mcasp1_aclkx */
-			0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4)	/* mii1_rxerr.mcasp1_fsx */
-			0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4)	/* mii1_col.mcasp1_axr2 */
-			0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4)	/* rmii1_ref_clk.mcasp1_axr3 */
+			AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4)	/* mii1_crs.mcasp1_aclkx */
+			AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4)	/* mii1_rxerr.mcasp1_fsx */
+			AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4)	/* mii1_col.mcasp1_axr2 */
+			AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4)	/* rmii1_ref_clk.mcasp1_axr3 */
 		>;
 	};
 
 	lcd_pins: lcd_pins {
 		pinctrl-single,pins = <
-			0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */
+			AM4372_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */
 		>;
 	};
 
 	usb1_pins: usb1_pins {
 		pinctrl-single,pins = <
-			0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
+			AM4372_IOPAD(0xac0, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
 		>;
 	};
 
 	usb2_pins: usb2_pins {
 		pinctrl-single,pins = <
-			0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
+			AM4372_IOPAD(0xac4, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
 		>;
 	};
 };
diff --git a/arch/arm/dts/am43x-epos-evm.dts b/arch/arm/dts/am43x-epos-evm.dts
index b940bc6..90455a6 100644
--- a/arch/arm/dts/am43x-epos-evm.dts
+++ b/arch/arm/dts/am43x-epos-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /* AM43x EPOS EVM */
diff --git a/arch/arm/dts/am43xx-clocks.dtsi b/arch/arm/dts/am43xx-clocks.dtsi
index b1127b5..07ed769 100644
--- a/arch/arm/dts/am43xx-clocks.dtsi
+++ b/arch/arm/dts/am43xx-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for AM43xx clock data
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 &scm_clocks {
 	sys_clkin_ck: sys_clkin_ck {
diff --git a/arch/arm/dts/am571x-idk.dts b/arch/arm/dts/am571x-idk.dts
index 798fbfe..b3592b2 100644
--- a/arch/arm/dts/am571x-idk.dts
+++ b/arch/arm/dts/am571x-idk.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -77,17 +74,17 @@
 
 &mailbox5 {
 	status = "okay";
-	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+	mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
 		status = "okay";
 	};
-	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+	mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
 		status = "okay";
 	};
 };
 
 &mailbox6 {
 	status = "okay";
-	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+	mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
 		status = "okay";
 	};
 };
diff --git a/arch/arm/dts/am5729-beagleboneai.dts b/arch/arm/dts/am5729-beagleboneai.dts
index 3429303..f772aef 100644
--- a/arch/arm/dts/am5729-beagleboneai.dts
+++ b/arch/arm/dts/am5729-beagleboneai.dts
@@ -4,6 +4,7 @@
  */
 
 /dts-v1/;
+
 #include "dra74x.dtsi"
 #include "dra74x-mmc-iodelay.dtsi"
 #include <dt-bindings/gpio/gpio.h>
diff --git a/arch/arm/dts/am572x-idk-common.dtsi b/arch/arm/dts/am572x-idk-common.dtsi
index c6d858b..c7dc844 100644
--- a/arch/arm/dts/am572x-idk-common.dtsi
+++ b/arch/arm/dts/am572x-idk-common.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -81,20 +81,20 @@
 
 &mailbox5 {
 	status = "okay";
-	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+	mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
 		status = "okay";
 	};
-	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+	mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
 		status = "okay";
 	};
 };
 
 &mailbox6 {
 	status = "okay";
-	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+	mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
 		status = "okay";
 	};
-	mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+	mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
 		status = "okay";
 	};
 };
diff --git a/arch/arm/dts/am572x-idk.dts b/arch/arm/dts/am572x-idk.dts
index 42e88c1..ed9b912 100644
--- a/arch/arm/dts/am572x-idk.dts
+++ b/arch/arm/dts/am572x-idk.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/am574x-idk.dts b/arch/arm/dts/am574x-idk.dts
index 0de7361..dd3f2ac 100644
--- a/arch/arm/dts/am574x-idk.dts
+++ b/arch/arm/dts/am574x-idk.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 
diff --git a/arch/arm/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/dts/am57xx-beagle-x15-common.dtsi
index 1912ea9..22d8d3d 100644
--- a/arch/arm/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/dts/am57xx-beagle-x15-common.dtsi
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -571,20 +568,20 @@
 
 &mailbox5 {
 	status = "okay";
-	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+	mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
 		status = "okay";
 	};
-	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+	mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
 		status = "okay";
 	};
 };
 
 &mailbox6 {
 	status = "okay";
-	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+	mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
 		status = "okay";
 	};
-	mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+	mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
 		status = "okay";
 	};
 };
diff --git a/arch/arm/dts/am57xx-beagle-x15-revb1.dts b/arch/arm/dts/am57xx-beagle-x15-revb1.dts
index 34c6996..9f65d36 100644
--- a/arch/arm/dts/am57xx-beagle-x15-revb1.dts
+++ b/arch/arm/dts/am57xx-beagle-x15-revb1.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "am57xx-beagle-x15-common.dtsi"
diff --git a/arch/arm/dts/am57xx-beagle-x15-revc.dts b/arch/arm/dts/am57xx-beagle-x15-revc.dts
index ccd9916..803c7f4 100644
--- a/arch/arm/dts/am57xx-beagle-x15-revc.dts
+++ b/arch/arm/dts/am57xx-beagle-x15-revc.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "am57xx-beagle-x15-common.dtsi"
diff --git a/arch/arm/dts/am57xx-beagle-x15.dts b/arch/arm/dts/am57xx-beagle-x15.dts
index 8d9bdf1..6373697 100644
--- a/arch/arm/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/dts/am57xx-beagle-x15.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "am57xx-beagle-x15-common.dtsi"
diff --git a/arch/arm/dts/am57xx-idk-common-u-boot.dtsi b/arch/arm/dts/am57xx-idk-common-u-boot.dtsi
index d0ce469..b07aea0 100644
--- a/arch/arm/dts/am57xx-idk-common-u-boot.dtsi
+++ b/arch/arm/dts/am57xx-idk-common-u-boot.dtsi
@@ -3,7 +3,6 @@
  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
  */
 #include "omap5-u-boot.dtsi"
-#include "dra7-ipu-common-early-boot.dtsi"
 
 / {
 	xtal25mhz: xtal25mhz {
diff --git a/arch/arm/dts/am57xx-idk-common.dtsi b/arch/arm/dts/am57xx-idk-common.dtsi
index 590fb14..b83c9e9 100644
--- a/arch/arm/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/dts/am57xx-idk-common.dtsi
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "am57xx-industrial-grade.dtsi"
@@ -440,7 +437,7 @@
 	status = "okay";
 
 	spi-max-frequency = <76800000>;
-	m25p80@0 {
+	flash@0 {
 		compatible = "s25fl256s1", "jedec,spi-nor";
 		spi-max-frequency = <76800000>;
 		reg = <0>;
@@ -456,7 +453,7 @@
 		 */
 		partition@0 {
 			label = "QSPI.SPL";
-			reg = <0x00000000 0x000040000>;
+			reg = <0x00000000 0x00040000>;
 		};
 		partition@1 {
 			label = "QSPI.u-boot";
diff --git a/arch/arm/dts/bcm5301x.dtsi b/arch/arm/dts/bcm5301x.dtsi
new file mode 100644
index 0000000..5fc1b84
--- /dev/null
+++ b/arch/arm/dts/bcm5301x.dtsi
@@ -0,0 +1,581 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
+ * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
+ *
+ * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+#include <dt-bindings/clock/bcm-nsp.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&gic>;
+
+	chipcommon-a-bus@18000000 {
+		compatible = "simple-bus";
+		ranges = <0x00000000 0x18000000 0x00001000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: serial@300 {
+			compatible = "ns16550";
+			reg = <0x0300 0x100>;
+			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&iprocslow>;
+			status = "disabled";
+		};
+
+		uart1: serial@400 {
+			compatible = "ns16550";
+			reg = <0x0400 0x100>;
+			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&iprocslow>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinmux_uart1>;
+			status = "disabled";
+		};
+	};
+
+	mpcore-bus@19000000 {
+		compatible = "simple-bus";
+		ranges = <0x00000000 0x19000000 0x00023000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		a9pll: arm_clk@0 {
+			#clock-cells = <0>;
+			compatible = "brcm,nsp-armpll";
+			clocks = <&osc>;
+			reg = <0x00000 0x1000>;
+		};
+
+		scu@20000 {
+			compatible = "arm,cortex-a9-scu";
+			reg = <0x20000 0x100>;
+		};
+
+		timer@20200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x20200 0x100>;
+			interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&periph_clk>;
+		};
+
+		timer@20600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x20600 0x20>;
+			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+						  IRQ_TYPE_EDGE_RISING)>;
+			clocks = <&periph_clk>;
+		};
+
+		watchdog@20620 {
+			compatible = "arm,cortex-a9-twd-wdt";
+			reg = <0x20620 0x20>;
+			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+						  IRQ_TYPE_EDGE_RISING)>;
+			clocks = <&periph_clk>;
+		};
+
+		gic: interrupt-controller@21000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x21000 0x1000>,
+			      <0x20100 0x100>;
+		};
+
+		L2: cache-controller@22000 {
+			compatible = "arm,pl310-cache";
+			reg = <0x22000 0x1000>;
+			cache-unified;
+			arm,shared-override;
+			prefetch-data = <1>;
+			prefetch-instr = <1>;
+			cache-level = <2>;
+		};
+	};
+
+	pmu {
+		compatible = "arm,cortex-a9-pmu";
+		interrupts =
+			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		osc: oscillator {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <25000000>;
+		};
+
+		iprocmed: iprocmed {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+			clock-div = <2>;
+			clock-mult = <1>;
+		};
+
+		iprocslow: iprocslow {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+			clock-div = <4>;
+			clock-mult = <1>;
+		};
+
+		periph_clk: periph_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&a9pll>;
+			clock-div = <2>;
+			clock-mult = <1>;
+		};
+	};
+
+	axi@18000000 {
+		compatible = "brcm,bus-axi";
+		reg = <0x18000000 0x1000>;
+		ranges = <0x00000000 0x18000000 0x00100000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0x000fffff 0xffff>;
+		interrupt-map = 
+			/* ChipCommon */
+			<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+
+			/* Switch Register Access Block */
+			<0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+
+			/* PCIe Controller 0 */
+			<0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+
+			/* PCIe Controller 1 */
+			<0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+
+			/* PCIe Controller 2 */
+			<0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+
+			/* USB 2.0 Controller */
+			<0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+
+			/* USB 3.0 Controller */
+			<0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+
+			/* Ethernet Controller 0 */
+			<0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+
+			/* Ethernet Controller 1 */
+			<0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+
+			/* Ethernet Controller 2 */
+			<0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+
+			/* Ethernet Controller 3 */
+			<0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+
+			/* NAND Controller */
+			<0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+
+		chipcommon: chipcommon@0 {
+			reg = <0x00000000 0x1000>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pcie0: pcie@12000 {
+			reg = <0x00012000 0x1000>;
+		};
+
+		pcie1: pcie@13000 {
+			reg = <0x00013000 0x1000>;
+		};
+
+		pcie2: pcie@14000 {
+			reg = <0x00014000 0x1000>;
+		};
+
+		usb2: usb2@21000 {
+			reg = <0x00021000 0x1000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			interrupt-parent = <&gic>;
+
+			ehci: usb@21000 {
+				#usb-cells = <0>;
+
+				compatible = "generic-ehci";
+				reg = <0x00021000 0x1000>;
+				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb2_phy>;
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ehci_port1: port@1 {
+					reg = <1>;
+					#trigger-source-cells = <0>;
+				};
+
+				ehci_port2: port@2 {
+					reg = <2>;
+					#trigger-source-cells = <0>;
+				};
+			};
+
+			ohci: usb@22000 {
+				#usb-cells = <0>;
+
+				compatible = "generic-ohci";
+				reg = <0x00022000 0x1000>;
+				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ohci_port1: port@1 {
+					reg = <1>;
+					#trigger-source-cells = <0>;
+				};
+
+				ohci_port2: port@2 {
+					reg = <2>;
+					#trigger-source-cells = <0>;
+				};
+			};
+		};
+
+		usb3: usb3@23000 {
+			reg = <0x00023000 0x1000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			interrupt-parent = <&gic>;
+
+			xhci: usb@23000 {
+				#usb-cells = <0>;
+
+				compatible = "generic-xhci";
+				reg = <0x00023000 0x1000>;
+				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb3_phy>;
+				phy-names = "usb";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				xhci_port1: port@1 {
+					reg = <1>;
+					#trigger-source-cells = <0>;
+				};
+			};
+		};
+
+		gmac0: ethernet@24000 {
+			reg = <0x24000 0x800>;
+		};
+
+		gmac1: ethernet@25000 {
+			reg = <0x25000 0x800>;
+		};
+
+		gmac2: ethernet@26000 {
+			reg = <0x26000 0x800>;
+		};
+
+		gmac3: ethernet@27000 {
+			reg = <0x27000 0x800>;
+		};
+	};
+
+	pwm: pwm@18002000 {
+		compatible = "brcm,iproc-pwm";
+		reg = <0x18002000 0x28>;
+		clocks = <&osc>;
+		#pwm-cells = <3>;
+		status = "disabled";
+	};
+
+	mdio: mdio@18003000 {
+		compatible = "brcm,iproc-mdio";
+		reg = <0x18003000 0x8>;
+		#size-cells = <0>;
+		#address-cells = <1>;
+	};
+
+	mdio-mux@18003000 {
+		compatible = "mdio-mux-mmioreg", "mdio-mux";
+		mdio-parent-bus = <&mdio>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x18003000 0x4>;
+		mux-mask = <0x200>;
+
+		mdio@0 {
+			reg = <0x0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			usb3_phy: usb3-phy@10 {
+				compatible = "brcm,ns-ax-usb3-phy";
+				reg = <0x10>;
+				usb3-dmp-syscon = <&usb3_dmp>;
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+		};
+	};
+
+	usb3_dmp: syscon@18105000 {
+		reg = <0x18105000 0x1000>;
+	};
+
+	uart2: serial@18008000 {
+		compatible = "ns16550a";
+		reg = <0x18008000 0x20>;
+		clocks = <&iprocslow>;
+		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	i2c0: i2c@18009000 {
+		compatible = "brcm,iproc-i2c";
+		reg = <0x18009000 0x50>;
+		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-frequency = <100000>;
+		status = "disabled";
+	};
+
+	dmu-bus@1800c000 {
+		compatible = "simple-bus";
+		ranges = <0 0x1800c000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cru-bus@100 {
+			compatible = "brcm,ns-cru", "simple-mfd";
+			reg = <0x100 0x1a4>;
+			ranges;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			lcpll0: clock-controller@100 {
+				#clock-cells = <1>;
+				compatible = "brcm,nsp-lcpll0";
+				reg = <0x100 0x14>;
+				clocks = <&osc>;
+				clock-output-names = "lcpll0", "pcie_phy",
+						     "sdio", "ddr_phy";
+			};
+
+			genpll: clock-controller@140 {
+				#clock-cells = <1>;
+				compatible = "brcm,nsp-genpll";
+				reg = <0x140 0x24>;
+				clocks = <&osc>;
+				clock-output-names = "genpll", "phy",
+						     "ethernetclk",
+						     "usbclk", "iprocfast",
+						     "sata1", "sata2";
+			};
+
+			usb2_phy: phy@164 {
+				compatible = "brcm,ns-usb2-phy";
+				reg = <0x164 0x4>;
+				brcm,syscon-clkset = <&cru_clkset>;
+				clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
+				clock-names = "phy-ref-clk";
+				#phy-cells = <0>;
+			};
+
+			cru_clkset: syscon@180 {
+				compatible = "brcm,cru-clkset", "syscon";
+				reg = <0x180 0x4>;
+			};
+
+			pinctrl: pinctrl@1c0 {
+				compatible = "brcm,bcm4708-pinmux";
+				reg = <0x1c0 0x24>;
+				reg-names = "cru_gpio_control";
+
+				spi-pins {
+					groups = "spi_grp";
+					function = "spi";
+				};
+
+				pinmux_i2c: i2c-pins {
+					groups = "i2c_grp";
+					function = "i2c";
+				};
+
+				pinmux_pwm: pwm-pins {
+					groups = "pwm0_grp", "pwm1_grp",
+						 "pwm2_grp", "pwm3_grp";
+					function = "pwm";
+				};
+
+				pinmux_uart1: uart1-pins {
+					groups = "uart1_grp";
+					function = "uart1";
+				};
+			};
+
+			thermal: thermal@2c0 {
+				compatible = "brcm,ns-thermal";
+				reg = <0x2c0 0x10>;
+				#thermal-sensor-cells = <0>;
+			};
+		};
+	};
+
+	srab: ethernet-switch@18007000 {
+		compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab";
+		reg = <0x18007000 0x1000>;
+
+		status = "disabled";
+
+		/* ports are defined in board DTS */
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+
+	rng: rng@18004000 {
+		compatible = "brcm,bcm5301x-rng";
+		reg = <0x18004000 0x14>;
+	};
+
+	nand_controller: nand-controller@18028000 {
+		compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
+		reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
+		reg-names = "nand", "iproc-idm", "iproc-ext";
+		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		brcm,nand-has-wp;
+	};
+
+	spi@18029200 {
+		compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
+		reg = <0x18029200 0x184>,
+		      <0x18029000 0x124>,
+		      <0x1811b408 0x004>,
+		      <0x180293a0 0x01c>;
+		reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
+		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "mspi_done",
+				  "mspi_halted",
+				  "spi_lr_fullness_reached",
+				  "spi_lr_session_aborted",
+				  "spi_lr_impatient",
+				  "spi_lr_session_done",
+				  "spi_lr_overread";
+		clocks = <&iprocmed>;
+		clock-names = "iprocmed";
+		num-cs = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		spi_nor: flash@0 {
+			compatible = "jedec,spi-nor";
+			reg = <0>;
+			spi-max-frequency = <20000000>;
+			status = "disabled";
+
+			partitions {
+				compatible = "brcm,bcm947xx-cfe-partitions";
+			};
+		};
+	};
+
+	thermal-zones {
+		cpu_thermal: cpu-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <1000>;
+			coefficients = <(-556) 418000>;
+			thermal-sensors = <&thermal>;
+
+			trips {
+				cpu-crit {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi
index 4e46826..533dfdf 100644
--- a/arch/arm/dts/corstone1000.dtsi
+++ b/arch/arm/dts/corstone1000.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0 or MIT
 /*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
  * Copyright (c) 2022, Linaro Limited. All rights reserved.
  *
  */
@@ -38,6 +38,13 @@
 		reg = <0x88200000 0x77e00000>;
 	};
 
+	nvmxip-qspi@08000000 {
+		compatible = "nvmxip,qspi";
+		reg = <0x08000000 0x2000000>;
+		lba_shift = <9>;
+		lba = <65536>;
+	};
+
 	gic: interrupt-controller@1c000000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
diff --git a/arch/arm/dts/da850-evm.dts b/arch/arm/dts/da850-evm.dts
index b331cef..378af9f 100644
--- a/arch/arm/dts/da850-evm.dts
+++ b/arch/arm/dts/da850-evm.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree for DA850 EVM board
  *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation, version 2.
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 #include "da850.dtsi"
@@ -55,15 +52,15 @@
 		enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */
 
 		panel-info {
-			ac-bias		= <255>;
-			ac-bias-intrpt	= <0>;
-			dma-burst-sz	= <16>;
-			bpp		= <16>;
-			fdd		= <0x80>;
-			sync-edge	= <0>;
-			sync-ctrl	= <1>;
-			raster-order	= <0>;
-			fifo-th		= <0>;
+			ac-bias = <255>;
+			ac-bias-intrpt = <0>;
+			dma-burst-sz = <16>;
+			bpp = <16>;
+			fdd = <0x80>;
+			sync-edge = <0>;
+			sync-ctrl = <1>;
+			raster-order = <0>;
+			fifo-th = <0>;
 		};
 
 		display-timings {
@@ -268,7 +265,7 @@
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi1_pins &spi1_cs0_pin>;
-	flash: m25p80@0 {
+	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "m25p64";
diff --git a/arch/arm/dts/da850-lcdk.dts b/arch/arm/dts/da850-lcdk.dts
index db8ae56..9c8e9f0 100644
--- a/arch/arm/dts/da850-lcdk.dts
+++ b/arch/arm/dts/da850-lcdk.dts
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2016 BayLibre, Inc.
- *
- * Licensed under GPLv2.
  */
 /dts-v1/;
 #include "da850.dtsi"
diff --git a/arch/arm/dts/da850-lego-ev3.dts b/arch/arm/dts/da850-lego-ev3.dts
index e281d03..7207d12 100644
--- a/arch/arm/dts/da850-lego-ev3.dts
+++ b/arch/arm/dts/da850-lego-ev3.dts
@@ -1,12 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device tree for LEGO MINDSTORMS EV3
  *
  * Copyright (C) 2017 David Lechner <david@lechnology.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * This is an absolute minimum device tree instead of using the one from Linux
- * because the bootloader on the EV3 is limited to 256k. This saves us >10k.
  */
 
 /dts-v1/;
@@ -26,7 +22,7 @@
 		stdout-path = &serial1;
 	};
 
-	memory {
+	memory@c0000000 {
 		device_type = "memory";
 		reg = <0xc0000000 0x04000000>;
 	};
diff --git a/arch/arm/dts/da850.dtsi b/arch/arm/dts/da850.dtsi
index 559659b..c96f64b 100644
--- a/arch/arm/dts/da850.dtsi
+++ b/arch/arm/dts/da850.dtsi
@@ -1,11 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
 /*
  * Copyright 2012 DENX Software Engineering GmbH
  * Heiko Schocher <hs@denx.de>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
  */
 #include <dt-bindings/interrupt-controller/irq.h>
 
@@ -373,7 +369,7 @@
 		edma0: edma@0 {
 			compatible = "ti,edma3-tpcc";
 			/* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
-			reg =	<0x0 0x8000>;
+			reg = <0x0 0x8000>;
 			reg-names = "edma3_cc";
 			interrupts = <11 12>;
 			interrupt-names = "edma3_ccint", "edma3_ccerrint";
@@ -384,14 +380,14 @@
 		};
 		edma0_tptc0: tptc@8000 {
 			compatible = "ti,edma3-tptc";
-			reg =	<0x8000 0x400>;
+			reg = <0x8000 0x400>;
 			interrupts = <13>;
 			interrupt-names = "edm3_tcerrint";
 			power-domains = <&psc0 1>;
 		};
 		edma0_tptc1: tptc@8400 {
 			compatible = "ti,edma3-tptc";
-			reg =	<0x8400 0x400>;
+			reg = <0x8400 0x400>;
 			interrupts = <32>;
 			interrupt-names = "edm3_tcerrint";
 			power-domains = <&psc0 2>;
@@ -399,7 +395,7 @@
 		edma1: edma@230000 {
 			compatible = "ti,edma3-tpcc";
 			/* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
-			reg =	<0x230000 0x8000>;
+			reg = <0x230000 0x8000>;
 			reg-names = "edma3_cc";
 			interrupts = <93 94>;
 			interrupt-names = "edma3_ccint", "edma3_ccerrint";
@@ -410,7 +406,7 @@
 		};
 		edma1_tptc0: tptc@238000 {
 			compatible = "ti,edma3-tptc";
-			reg =	<0x238000 0x400>;
+			reg = <0x238000 0x400>;
 			interrupts = <95>;
 			interrupt-names = "edm3_tcerrint";
 			power-domains = <&psc1 21>;
@@ -547,7 +543,7 @@
 			power-domains = <&psc1 17>;
 			status = "disabled";
 		};
-		ecap0: ecap@306000 {
+		ecap0: pwm@306000 {
 			compatible = "ti,da850-ecap", "ti,am3352-ecap",
 				     "ti,am33xx-ecap";
 			#pwm-cells = <3>;
@@ -557,7 +553,7 @@
 			power-domains = <&psc1 20>;
 			status = "disabled";
 		};
-		ecap1: ecap@307000 {
+		ecap1: pwm@307000 {
 			compatible = "ti,da850-ecap", "ti,am3352-ecap",
 				     "ti,am33xx-ecap";
 			#pwm-cells = <3>;
@@ -567,7 +563,7 @@
 			power-domains = <&psc1 20>;
 			status = "disabled";
 		};
-		ecap2: ecap@308000 {
+		ecap2: pwm@308000 {
 			compatible = "ti,da850-ecap", "ti,am3352-ecap",
 				     "ti,am33xx-ecap";
 			#pwm-cells = <3>;
@@ -631,7 +627,7 @@
 
 			cppi41dma: dma-controller@201000 {
 				compatible = "ti,da830-cppi41";
-				reg =  <0x201000 0x1000
+				reg = <0x201000 0x1000
 					0x202000 0x1000
 					0x204000 0x4000>;
 				reg-names = "controller",
diff --git a/arch/arm/dts/dm8168-evm.dts b/arch/arm/dts/dm8168-evm.dts
index 0bf55fa..70255ab 100644
--- a/arch/arm/dts/dm8168-evm.dts
+++ b/arch/arm/dts/dm8168-evm.dts
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
 /dts-v1/;
 
 #include "dm816x.dtsi"
@@ -120,19 +116,19 @@
 			label = "X-Loader";
 			reg = <0 0x80000>;
 		};
-		partition@0x80000 {
+		partition@80000 {
 			label = "U-Boot";
 			reg = <0x80000 0x1c0000>;
 		};
-		partition@0x1c0000 {
+		partition@1c0000 {
 			label = "Environment";
 			reg = <0x240000 0x40000>;
 		};
-		partition@0x280000 {
+		partition@280000 {
 			label = "Kernel";
 			reg = <0x280000 0x500000>;
 		};
-		partition@0x780000 {
+		partition@780000 {
 			label = "Filesystem";
 			reg = <0x780000 0xf880000>;
 		};
@@ -143,7 +139,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&mcspi1_pins>;
 
-	m25p80@0 {
+	flash@0 {
 		compatible = "w25x32";
 		spi-max-frequency = <48000000>;
 		reg = <0>;
diff --git a/arch/arm/dts/dm816x-clocks.dtsi b/arch/arm/dts/dm816x-clocks.dtsi
index 51865eb..f7a839d 100644
--- a/arch/arm/dts/dm816x-clocks.dtsi
+++ b/arch/arm/dts/dm816x-clocks.dtsi
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
 
 &scrm {
 	main_fapll: main_fapll {
diff --git a/arch/arm/dts/dm816x.dtsi b/arch/arm/dts/dm816x.dtsi
index fe58faf..c4a8653 100644
--- a/arch/arm/dts/dm816x.dtsi
+++ b/arch/arm/dts/dm816x.dtsi
@@ -1,8 +1,4 @@
-/*
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/omap.h>
@@ -67,8 +63,11 @@
 		ranges;
 
 		prcm: prcm@48180000 {
-			compatible = "ti,dm816-prcm";
+			compatible = "ti,dm816-prcm", "simple-bus";
 			reg = <0x48180000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x48180000 0x4000>;
 
 			prcm_clocks: clocks {
 				#address-cells = <1>;
@@ -90,6 +89,8 @@
 			dm816x_pinmux: pinmux@800 {
 				compatible = "pinctrl-single";
 				reg = <0x800 0x50a>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				#pinctrl-cells = <1>;
 				pinctrl-single,register-width = <16>;
 				pinctrl-single,function-mask = <0xf>;
@@ -125,6 +126,8 @@
 			};
 
 			scrm_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
 			};
 
 			scrm_clockdomains: clockdomains {
@@ -232,7 +235,7 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <4>;
 			ti,mbox-num-fifos = <12>;
-			mbox_dsp: mbox_dsp {
+			mbox_dsp: mbox-dsp {
 				ti,mbox-tx = <3 0 0>;
 				ti,mbox-rx = <0 0 0>;
 			};
@@ -368,7 +371,7 @@
 			ti,timer-pwm;
 		};
 
-		uart1: uart@48020000 {
+		uart1: serial@48020000 {
 			compatible = "ti,am3352-uart", "ti,omap3-uart";
 			ti,hwmods = "uart1";
 			reg = <0x48020000 0x2000>;
@@ -378,7 +381,7 @@
 			dma-names = "tx", "rx";
 		};
 
-		uart2: uart@48022000 {
+		uart2: serial@48022000 {
 			compatible = "ti,am3352-uart", "ti,omap3-uart";
 			ti,hwmods = "uart2";
 			reg = <0x48022000 0x2000>;
@@ -388,7 +391,7 @@
 			dma-names = "tx", "rx";
 		};
 
-		uart3: uart@48024000 {
+		uart3: serial@48024000 {
 			compatible = "ti,am3352-uart", "ti,omap3-uart";
 			ti,hwmods = "uart3";
 			reg = <0x48024000 0x2000>;
diff --git a/arch/arm/dts/dra7-dspeve-thermal.dtsi b/arch/arm/dts/dra7-dspeve-thermal.dtsi
index 1c39a84..747ff0d 100644
--- a/arch/arm/dts/dra7-dspeve-thermal.dtsi
+++ b/arch/arm/dts/dra7-dspeve-thermal.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for DRA7x SoC DSPEVE thermal
  *
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/thermal/thermal.h>
diff --git a/arch/arm/dts/dra7-evm-common.dtsi b/arch/arm/dts/dra7-evm-common.dtsi
index 343e95f..8f3a005 100644
--- a/arch/arm/dts/dra7-evm-common.dtsi
+++ b/arch/arm/dts/dra7-evm-common.dtsi
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -132,7 +129,7 @@
 	status = "okay";
 
 	spi-max-frequency = <76800000>;
-	m25p80@0 {
+	flash@0 {
 		compatible = "s25fl256s1";
 		spi-max-frequency = <76800000>;
 		reg = <0>;
@@ -148,7 +145,7 @@
 		 */
 		partition@0 {
 			label = "QSPI.SPL";
-			reg = <0x00000000 0x000010000>;
+			reg = <0x00000000 0x00010000>;
 		};
 		partition@1 {
 			label = "QSPI.SPL.backup1";
@@ -239,20 +236,20 @@
 
 &mailbox5 {
 	status = "okay";
-	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+	mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
 		status = "okay";
 	};
-	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+	mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
 		status = "okay";
 	};
 };
 
 &mailbox6 {
 	status = "okay";
-	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+	mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
 		status = "okay";
 	};
-	mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+	mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
 		status = "okay";
 	};
 };
diff --git a/arch/arm/dts/dra7-evm-u-boot.dtsi b/arch/arm/dts/dra7-evm-u-boot.dtsi
index f1ff5f6..87b2451 100644
--- a/arch/arm/dts/dra7-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra7-evm-u-boot.dtsi
@@ -4,7 +4,6 @@
  */
 
 #include "omap5-u-boot.dtsi"
-#include "dra7-ipu-common-early-boot.dtsi"
 
 &pcf_gpio_21{
 	u-boot,i2c-offset-len = <0>;
diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts
index 8e9a1a8..5333f17 100644
--- a/arch/arm/dts/dra7-evm.dts
+++ b/arch/arm/dts/dra7-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -315,7 +312,7 @@
 		reg = <0x26>;
 		gpio-controller;
 		#gpio-cells = <2>;
-		p1 {
+		hdmi-audio-hog {
 			/* vin6_sel_s0: high: VIN6, low: audio */
 			gpio-hog;
 			gpios = <1 GPIO_ACTIVE_HIGH>;
@@ -419,7 +416,7 @@
 		#size-cells = <1>;
 		partition@0 {
 			label = "NAND.SPL";
-			reg = <0x00000000 0x000020000>;
+			reg = <0x00000000 0x00020000>;
 		};
 		partition@1 {
 			label = "NAND.SPL.backup1";
diff --git a/arch/arm/dts/dra7-iva-thermal.dtsi b/arch/arm/dts/dra7-iva-thermal.dtsi
index dd74a53..0a31313 100644
--- a/arch/arm/dts/dra7-iva-thermal.dtsi
+++ b/arch/arm/dts/dra7-iva-thermal.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for DRA7x SoC IVA thermal
  *
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/thermal/thermal.h>
diff --git a/arch/arm/dts/dra7-mmc-iodelay.dtsi b/arch/arm/dts/dra7-mmc-iodelay.dtsi
index 4acc215..d46a1c0 100644
--- a/arch/arm/dts/dra7-mmc-iodelay.dtsi
+++ b/arch/arm/dts/dra7-mmc-iodelay.dtsi
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * MMC IOdelay values for TI's DRA7xx SoCs.
- * Copyright (C) 2019 Texas Instruments
+ * Copyright (C) 2018 Texas Instruments
  * Author: Faiz Abbas <faiz_abbas@ti.com>
  */
 
diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index e2e958b..b1aef63 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -1,9 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  * Based on "omap4.dtsi"
  */
 
@@ -134,7 +132,7 @@
 	 * the moment, just use a fake OCP bus entry to represent the whole bus
 	 * hierarchy.
 	 */
-	ocp {
+	ocp: ocp {
 		compatible = "ti,dra7-l3-noc", "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -357,7 +355,13 @@
 			};
 		};
 
-		axi@1 {
+		/*
+		 * Register access seems to have complex dependencies and also
+		 * seems to need an enabled phy. See the TRM chapter for "Table
+		 * 26-678. Main Sequence PCIe Controller Global Initialization"
+		 * and also dra7xx_pcie_probe().
+		 */
+		axi1: target-module@51800000 {
 			compatible = "simple-bus";
 			#size-cells = <1>;
 			#address-cells = <1>;
@@ -372,8 +376,8 @@
 				#address-cells = <3>;
 				#size-cells = <2>;
 				device_type = "pci";
-				ranges = <0x81000000 0 0          0x03000 0 0x00010000
-					  0x82000000 0 0x30013000 0x13000 0 0xffed000>;
+				ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>,
+					 <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>;
 				bus-range = <0x00 0xff>;
 				#interrupt-cells = <1>;
 				num-lanes = <1>;
@@ -2112,4 +2116,4 @@
 	temperature = <120000>; /* milli Celsius */
 };
 
-/include/ "dra7xx-clocks.dtsi"
+#include "dra7xx-clocks.dtsi"
diff --git a/arch/arm/dts/dra71-evm-u-boot.dtsi b/arch/arm/dts/dra71-evm-u-boot.dtsi
index f13eadf..8e7dc71 100644
--- a/arch/arm/dts/dra71-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra71-evm-u-boot.dtsi
@@ -4,7 +4,6 @@
  */
 
 #include "omap5-u-boot.dtsi"
-#include "dra7-ipu-common-early-boot.dtsi"
 
 &pcf_gpio_21{
 	u-boot,i2c-offset-len = <0>;
diff --git a/arch/arm/dts/dra71-evm.dts b/arch/arm/dts/dra71-evm.dts
index 9bf0829..b322598 100644
--- a/arch/arm/dts/dra71-evm.dts
+++ b/arch/arm/dts/dra71-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "dra72-evm-common.dtsi"
@@ -160,7 +157,7 @@
 };
 
 &pcf_hdmi {
-	p0 {
+	hdmi-i2c-disable-hog {
 		/*
 		 * PM_OEn to High: Disable routing I2C3 to PM_I2C
 		 * With this PM_SEL(p3) should not matter
diff --git a/arch/arm/dts/dra72-evm-common.dtsi b/arch/arm/dts/dra72-evm-common.dtsi
index 964e5e9..aa7a1c6 100644
--- a/arch/arm/dts/dra72-evm-common.dtsi
+++ b/arch/arm/dts/dra72-evm-common.dtsi
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -272,7 +269,7 @@
 		 */
 		lines-initial-states = <0x0f2b>;
 
-		p1 {
+		hdmi-audio-hog {
 			/* vin6_sel_s0: high: VIN6, low: audio */
 			gpio-hog;
 			gpios = <1 GPIO_ACTIVE_HIGH>;
@@ -343,7 +340,7 @@
 		#size-cells = <1>;
 		partition@0 {
 			label = "NAND.SPL";
-			reg = <0x00000000 0x000020000>;
+			reg = <0x00000000 0x00020000>;
 		};
 		partition@1 {
 			label = "NAND.SPL.backup1";
@@ -441,7 +438,7 @@
 	status = "okay";
 
 	spi-max-frequency = <76800000>;
-	m25p80@0 {
+	flash@0 {
 		compatible = "s25fl256s1";
 		spi-max-frequency = <76800000>;
 		reg = <0>;
@@ -457,7 +454,7 @@
 		 */
 		partition@0 {
 			label = "QSPI.SPL";
-			reg = <0x00000000 0x000010000>;
+			reg = <0x00000000 0x00010000>;
 		};
 		partition@1 {
 			label = "QSPI.SPL.backup1";
@@ -549,17 +546,17 @@
 
 &mailbox5 {
 	status = "okay";
-	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+	mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
 		status = "okay";
 	};
-	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+	mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
 		status = "okay";
 	};
 };
 
 &mailbox6 {
 	status = "okay";
-	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+	mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
 		status = "okay";
 	};
 };
diff --git a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
index f13eadf..8e7dc71 100644
--- a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
+++ b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
@@ -4,7 +4,6 @@
  */
 
 #include "omap5-u-boot.dtsi"
-#include "dra7-ipu-common-early-boot.dtsi"
 
 &pcf_gpio_21{
 	u-boot,i2c-offset-len = <0>;
diff --git a/arch/arm/dts/dra72-evm-revc.dts b/arch/arm/dts/dra72-evm-revc.dts
index fafc2a4..a6dbdd5 100644
--- a/arch/arm/dts/dra72-evm-revc.dts
+++ b/arch/arm/dts/dra72-evm-revc.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 #include "dra72-evm-common.dtsi"
 #include "dra72x-mmc-iodelay.dtsi"
diff --git a/arch/arm/dts/dra72-evm-tps65917.dtsi b/arch/arm/dts/dra72-evm-tps65917.dtsi
index 57bfe5c..c7b4768 100644
--- a/arch/arm/dts/dra72-evm-tps65917.dtsi
+++ b/arch/arm/dts/dra72-evm-tps65917.dtsi
@@ -1,14 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /*
  * Integrated Power Management Chip
- * http://www.ti.com/lit/ds/symlink/tps65917-q1.pdf
+ * https://www.ti.com/lit/ds/symlink/tps65917-q1.pdf
  */
 
 &tps65917 {
diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts
index 154b0a0..2f24412 100644
--- a/arch/arm/dts/dra72-evm.dts
+++ b/arch/arm/dts/dra72-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 #include "dra72-evm-common.dtsi"
 #include "dra72x-mmc-iodelay.dtsi"
diff --git a/arch/arm/dts/dra72x-mmc-iodelay.dtsi b/arch/arm/dts/dra72x-mmc-iodelay.dtsi
index 088013c..98f2eac 100644
--- a/arch/arm/dts/dra72x-mmc-iodelay.dtsi
+++ b/arch/arm/dts/dra72x-mmc-iodelay.dtsi
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs.
  *
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /*
diff --git a/arch/arm/dts/dra72x.dtsi b/arch/arm/dts/dra72x.dtsi
index 6710760..481189d 100644
--- a/arch/arm/dts/dra72x.dtsi
+++ b/arch/arm/dts/dra72x.dtsi
@@ -1,9 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  * Based on "omap4.dtsi"
  */
 
@@ -31,12 +29,12 @@
 };
 
 &mailbox5 {
-	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+	mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
 		ti,mbox-tx = <6 2 2>;
 		ti,mbox-rx = <4 2 2>;
 		status = "disabled";
 	};
-	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+	mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
 		ti,mbox-tx = <5 2 2>;
 		ti,mbox-rx = <1 2 2>;
 		status = "disabled";
@@ -44,7 +42,7 @@
 };
 
 &mailbox6 {
-	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+	mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
 		ti,mbox-tx = <6 2 2>;
 		ti,mbox-rx = <4 2 2>;
 		status = "disabled";
diff --git a/arch/arm/dts/dra74x-mmc-iodelay.dtsi b/arch/arm/dts/dra74x-mmc-iodelay.dtsi
index 214b9e6..b9d0401 100644
--- a/arch/arm/dts/dra74x-mmc-iodelay.dtsi
+++ b/arch/arm/dts/dra74x-mmc-iodelay.dtsi
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs.
  *
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /*
diff --git a/arch/arm/dts/dra74x.dtsi b/arch/arm/dts/dra74x.dtsi
index 24e6746..9ade216 100644
--- a/arch/arm/dts/dra74x.dtsi
+++ b/arch/arm/dts/dra74x.dtsi
@@ -1,9 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  * Based on "omap4.dtsi"
  */
 
@@ -100,12 +98,12 @@
 };
 
 &mailbox5 {
-	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+	mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
 		ti,mbox-tx = <6 2 2>;
 		ti,mbox-rx = <4 2 2>;
 		status = "disabled";
 	};
-	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+	mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
 		ti,mbox-tx = <5 2 2>;
 		ti,mbox-rx = <1 2 2>;
 		status = "disabled";
@@ -113,12 +111,12 @@
 };
 
 &mailbox6 {
-	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+	mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
 		ti,mbox-tx = <6 2 2>;
 		ti,mbox-rx = <4 2 2>;
 		status = "disabled";
 	};
-	mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+	mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
 		ti,mbox-tx = <5 2 2>;
 		ti,mbox-rx = <1 2 2>;
 		status = "disabled";
diff --git a/arch/arm/dts/dra76-evm-u-boot.dtsi b/arch/arm/dts/dra76-evm-u-boot.dtsi
index db5a466..1216d93 100644
--- a/arch/arm/dts/dra76-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra76-evm-u-boot.dtsi
@@ -4,7 +4,6 @@
  */
 
 #include "omap5-u-boot.dtsi"
-#include "dra7-ipu-common-early-boot.dtsi"
 
 &cpsw_emac0 {
 	phy-handle = <&dp83867_0>;
diff --git a/arch/arm/dts/dra76-evm.dts b/arch/arm/dts/dra76-evm.dts
index e3da17a..c131e7f 100644
--- a/arch/arm/dts/dra76-evm.dts
+++ b/arch/arm/dts/dra76-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -274,7 +271,7 @@
 		reg = <0x26>;
 		gpio-controller;
 		#gpio-cells = <2>;
-		p1 {
+		hdmi-audio-hog {
 			/* vin6_sel_s0: high: VIN6, low: audio */
 			gpio-hog;
 			gpios = <1 GPIO_ACTIVE_HIGH>;
@@ -382,7 +379,7 @@
 
 &qspi {
 	spi-max-frequency = <96000000>;
-	m25p80@0 {
+	flash@0 {
 		spi-max-frequency = <96000000>;
 	};
 };
diff --git a/arch/arm/dts/dra76x.dtsi b/arch/arm/dts/dra76x.dtsi
index 1c88c58..4f0e178 100644
--- a/arch/arm/dts/dra76x.dtsi
+++ b/arch/arm/dts/dra76x.dtsi
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "dra74x.dtsi"
diff --git a/arch/arm/dts/dra7xx-clocks.dtsi b/arch/arm/dts/dra7xx-clocks.dtsi
index cf229df..b0cfe55 100644
--- a/arch/arm/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/dts/dra7xx-clocks.dtsi
@@ -1,110 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for DRA7xx clock data
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 &cm_core_aon_clocks {
-	atl_clkin0_ck: atl_clkin0_ck {
+	atl_clkin0_ck: clock-atl-clkin0 {
 		#clock-cells = <0>;
 		compatible = "ti,dra7-atl-clock";
 		clocks = <&atl_gfclk_mux>;
 	};
 
-	atl_clkin1_ck: atl_clkin1_ck {
+	atl_clkin1_ck: clock-atl-clkin1 {
 		#clock-cells = <0>;
 		compatible = "ti,dra7-atl-clock";
 		clocks = <&atl_gfclk_mux>;
 	};
 
-	atl_clkin2_ck: atl_clkin2_ck {
+	atl_clkin2_ck: clock-atl-clkin2 {
 		#clock-cells = <0>;
 		compatible = "ti,dra7-atl-clock";
 		clocks = <&atl_gfclk_mux>;
 	};
 
-	atl_clkin3_ck: atl_clkin3_ck {
+	atl_clkin3_ck: clock-atl-clkin3 {
 		#clock-cells = <0>;
 		compatible = "ti,dra7-atl-clock";
 		clocks = <&atl_gfclk_mux>;
 	};
 
-	hdmi_clkin_ck: hdmi_clkin_ck {
+	hdmi_clkin_ck: clock-hdmi-clkin {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <0>;
 	};
 
-	mlb_clkin_ck: mlb_clkin_ck {
+	mlb_clkin_ck: clock-mlb-clkin {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <0>;
 	};
 
-	mlbp_clkin_ck: mlbp_clkin_ck {
+	mlbp_clkin_ck: clock-mlbp-clkin {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <0>;
 	};
 
-	pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+	pciesref_acs_clk_ck: clock-pciesref-acs {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <100000000>;
 	};
 
-	ref_clkin0_ck: ref_clkin0_ck {
+	ref_clkin0_ck: clock-ref-clkin0 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <0>;
 	};
 
-	ref_clkin1_ck: ref_clkin1_ck {
+	ref_clkin1_ck: clock-ref-clkin1 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <0>;
 	};
 
-	ref_clkin2_ck: ref_clkin2_ck {
+	ref_clkin2_ck: clock-ref-clkin2 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <0>;
 	};
 
-	ref_clkin3_ck: ref_clkin3_ck {
+	ref_clkin3_ck: clock-ref-clkin3 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <0>;
 	};
 
-	rmii_clk_ck: rmii_clk_ck {
+	rmii_clk_ck: clock-rmii {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <0>;
 	};
 
-	sdvenc_clkin_ck: sdvenc_clkin_ck {
+	sdvenc_clkin_ck: clock-sdvenc-clkin {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <0>;
 	};
 
-	secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+	secure_32k_clk_src_ck: clock-secure-32k-clk-src {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <32768>;
 	};
 
-	sys_clk32_crystal_ck: sys_clk32_crystal_ck {
+	sys_clk32_crystal_ck: clock-sys-clk32-crystal {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <32768>;
 	};
 
-	sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
+	sys_clk32_pseudo_ck: clock-sys-clk32-pseudo {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&sys_clkin1>;
@@ -112,104 +109,104 @@
 		clock-div = <610>;
 	};
 
-	virt_12000000_ck: virt_12000000_ck {
+	virt_12000000_ck: clock-virt-12000000 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <12000000>;
 	};
 
-	virt_13000000_ck: virt_13000000_ck {
+	virt_13000000_ck: clock-virt-13000000 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <13000000>;
 	};
 
-	virt_16800000_ck: virt_16800000_ck {
+	virt_16800000_ck: clock-virt-16800000 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <16800000>;
 	};
 
-	virt_19200000_ck: virt_19200000_ck {
+	virt_19200000_ck: clock-virt-19200000 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <19200000>;
 	};
 
-	virt_20000000_ck: virt_20000000_ck {
+	virt_20000000_ck: clock-virt-20000000 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <20000000>;
 	};
 
-	virt_26000000_ck: virt_26000000_ck {
+	virt_26000000_ck: clock-virt-26000000 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <26000000>;
 	};
 
-	virt_27000000_ck: virt_27000000_ck {
+	virt_27000000_ck: clock-virt-27000000 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <27000000>;
 	};
 
-	virt_38400000_ck: virt_38400000_ck {
+	virt_38400000_ck: clock-virt-38400000 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <38400000>;
 	};
 
-	sys_clkin2: sys_clkin2 {
+	sys_clkin2: clock-sys-clkin2 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <22579200>;
 	};
 
-	usb_otg_clkin_ck: usb_otg_clkin_ck {
+	usb_otg_clkin_ck: clock-usb-otg-clkin {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <0>;
 	};
 
-	video1_clkin_ck: video1_clkin_ck {
+	video1_clkin_ck: clock-video1-clkin {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <0>;
 	};
 
-	video1_m2_clkin_ck: video1_m2_clkin_ck {
+	video1_m2_clkin_ck: clock-video1-m2-clkin {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <0>;
 	};
 
-	video2_clkin_ck: video2_clkin_ck {
+	video2_clkin_ck: clock-video2-clkin {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <0>;
 	};
 
-	video2_m2_clkin_ck: video2_m2_clkin_ck {
+	video2_m2_clkin_ck: clock-video2-m2-clkin {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <0>;
 	};
 
-	dpll_abe_ck: dpll_abe_ck@1e0 {
+	dpll_abe_ck: clock@1e0 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-m4xen-clock";
 		clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
 		reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
 	};
 
-	dpll_abe_x2_ck: dpll_abe_x2_ck {
+	dpll_abe_x2_ck: clock-dpll-abe-x2 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-x2-clock";
 		clocks = <&dpll_abe_ck>;
 	};
 
-	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
+	dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_x2_ck>;
@@ -220,7 +217,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	abe_clk: abe_clk@108 {
+	abe_clk: clock-abe@108 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_m2x2_ck>;
@@ -229,7 +226,7 @@
 		ti,index-power-of-two;
 	};
 
-	dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
+	dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_ck>;
@@ -240,7 +237,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
+	dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_x2_ck>;
@@ -251,7 +248,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_core_byp_mux: dpll_core_byp_mux@12c {
+	dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -259,20 +256,20 @@
 		reg = <0x012c>;
 	};
 
-	dpll_core_ck: dpll_core_ck@120 {
+	dpll_core_ck: clock@120 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-core-clock";
 		clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
 		reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
 	};
 
-	dpll_core_x2_ck: dpll_core_x2_ck {
+	dpll_core_x2_ck: clock-dpll-core-x2 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-x2-clock";
 		clocks = <&dpll_core_ck>;
 	};
 
-	dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
+	dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -283,7 +280,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+	mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_core_h12x2_ck>;
@@ -291,14 +288,14 @@
 		clock-div = <1>;
 	};
 
-	dpll_mpu_ck: dpll_mpu_ck@160 {
+	dpll_mpu_ck: clock@160 {
 		#clock-cells = <0>;
 		compatible = "ti,omap5-mpu-dpll-clock";
 		clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
 		reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
 	};
 
-	dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
+	dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_mpu_ck>;
@@ -309,7 +306,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	mpu_dclk_div: mpu_dclk_div {
+	mpu_dclk_div: clock-mpu-dclk-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_mpu_m2_ck>;
@@ -317,7 +314,7 @@
 		clock-div = <1>;
 	};
 
-	dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
+	dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_core_h12x2_ck>;
@@ -325,7 +322,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
+	dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
@@ -333,7 +330,7 @@
 		reg = <0x0240>;
 	};
 
-	dpll_dsp_ck: dpll_dsp_ck@234 {
+	dpll_dsp_ck: clock@234 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
@@ -342,7 +339,7 @@
 		assigned-clock-rates = <600000000>;
 	};
 
-	dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
+	dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_dsp_ck>;
@@ -355,7 +352,7 @@
 		assigned-clock-rates = <600000000>;
 	};
 
-	iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+	iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_core_h12x2_ck>;
@@ -363,7 +360,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
+	dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
@@ -371,7 +368,7 @@
 		reg = <0x01ac>;
 	};
 
-	dpll_iva_ck: dpll_iva_ck@1a0 {
+	dpll_iva_ck: clock@1a0 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
@@ -380,7 +377,7 @@
 		assigned-clock-rates = <1165000000>;
 	};
 
-	dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
+	dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_iva_ck>;
@@ -393,7 +390,7 @@
 		assigned-clock-rates = <388333334>;
 	};
 
-	iva_dclk: iva_dclk {
+	iva_dclk: clock-iva-dclk {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_iva_m2_ck>;
@@ -401,7 +398,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
+	dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -409,7 +406,7 @@
 		reg = <0x02e4>;
 	};
 
-	dpll_gpu_ck: dpll_gpu_ck@2d8 {
+	dpll_gpu_ck: clock@2d8 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
@@ -418,7 +415,7 @@
 		assigned-clock-rates = <1277000000>;
 	};
 
-	dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
+	dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_gpu_ck>;
@@ -431,7 +428,7 @@
 		assigned-clock-rates = <425666667>;
 	};
 
-	dpll_core_m2_ck: dpll_core_m2_ck@130 {
+	dpll_core_m2_ck: clock-dpll-core-m2-8@130 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_ck>;
@@ -442,7 +439,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	core_dpll_out_dclk_div: core_dpll_out_dclk_div {
+	core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_core_m2_ck>;
@@ -450,7 +447,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
+	dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -458,14 +455,14 @@
 		reg = <0x021c>;
 	};
 
-	dpll_ddr_ck: dpll_ddr_ck@210 {
+	dpll_ddr_ck: clock@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
 		reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
 	};
 
-	dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
+	dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_ddr_ck>;
@@ -476,7 +473,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
+	dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -484,14 +481,14 @@
 		reg = <0x02b4>;
 	};
 
-	dpll_gmac_ck: dpll_gmac_ck@2a8 {
+	dpll_gmac_ck: clock@2a8 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
 		reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
 	};
 
-	dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
+	dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_gmac_ck>;
@@ -502,7 +499,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	video2_dclk_div: video2_dclk_div {
+	video2_dclk_div: clock-video2-dclk-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&video2_m2_clkin_ck>;
@@ -510,7 +507,7 @@
 		clock-div = <1>;
 	};
 
-	video1_dclk_div: video1_dclk_div {
+	video1_dclk_div: clock-video1-dclk-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&video1_m2_clkin_ck>;
@@ -518,7 +515,7 @@
 		clock-div = <1>;
 	};
 
-	hdmi_dclk_div: hdmi_dclk_div {
+	hdmi_dclk_div: clock-hdmi-dclk-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&hdmi_clkin_ck>;
@@ -526,7 +523,7 @@
 		clock-div = <1>;
 	};
 
-	per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+	per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_abe_m3x2_ck>;
@@ -534,7 +531,7 @@
 		clock-div = <2>;
 	};
 
-	usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+	usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_abe_m3x2_ck>;
@@ -542,7 +539,7 @@
 		clock-div = <3>;
 	};
 
-	eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
+	eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_core_h12x2_ck>;
@@ -550,7 +547,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
+	dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
@@ -558,14 +555,14 @@
 		reg = <0x0290>;
 	};
 
-	dpll_eve_ck: dpll_eve_ck@284 {
+	dpll_eve_ck: clock@284 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
 		reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
 	};
 
-	dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
+	dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_eve_ck>;
@@ -576,7 +573,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	eve_dclk_div: eve_dclk_div {
+	eve_dclk_div: clock-eve-dclk-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_eve_m2_ck>;
@@ -584,7 +581,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
+	dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -595,7 +592,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
+	dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -606,7 +603,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
+	dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -617,7 +614,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
+	dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -628,7 +625,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
+	dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -639,13 +636,13 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+	dpll_ddr_x2_ck: clock-dpll-ddr-x2 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-x2-clock";
 		clocks = <&dpll_ddr_ck>;
 	};
 
-	dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
+	dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_ddr_x2_ck>;
@@ -656,13 +653,13 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_dsp_x2_ck: dpll_dsp_x2_ck {
+	dpll_dsp_x2_ck: clock-dpll-dsp-x2 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-x2-clock";
 		clocks = <&dpll_dsp_ck>;
 	};
 
-	dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
+	dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_dsp_x2_ck>;
@@ -675,13 +672,13 @@
 		assigned-clock-rates = <400000000>;
 	};
 
-	dpll_gmac_x2_ck: dpll_gmac_x2_ck {
+	dpll_gmac_x2_ck: clock-dpll-gmac-x2 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-x2-clock";
 		clocks = <&dpll_gmac_ck>;
 	};
 
-	dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
+	dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_gmac_x2_ck>;
@@ -692,7 +689,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
+	dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_gmac_x2_ck>;
@@ -703,7 +700,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
+	dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_gmac_x2_ck>;
@@ -714,7 +711,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
+	dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_gmac_x2_ck>;
@@ -725,7 +722,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	gmii_m_clk_div: gmii_m_clk_div {
+	gmii_m_clk_div: clock-gmii-m-clk-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_gmac_h11x2_ck>;
@@ -733,7 +730,7 @@
 		clock-div = <2>;
 	};
 
-	hdmi_clk2_div: hdmi_clk2_div {
+	hdmi_clk2_div: clock-hdmi-clk2-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&hdmi_clkin_ck>;
@@ -741,7 +738,7 @@
 		clock-div = <1>;
 	};
 
-	hdmi_div_clk: hdmi_div_clk {
+	hdmi_div_clk: clock-hdmi-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&hdmi_clkin_ck>;
@@ -749,7 +746,7 @@
 		clock-div = <1>;
 	};
 
-	l3_iclk_div: l3_iclk_div@100 {
+	l3_iclk_div: clock-l3-iclk-div-4@100 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		ti,max-div = <2>;
@@ -759,7 +756,7 @@
 		ti,index-power-of-two;
 	};
 
-	l4_root_clk_div: l4_root_clk_div {
+	l4_root_clk_div: clock-l4-root-clk-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&l3_iclk_div>;
@@ -767,7 +764,7 @@
 		clock-div = <2>;
 	};
 
-	video1_clk2_div: video1_clk2_div {
+	video1_clk2_div: clock-video1-clk2-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&video1_clkin_ck>;
@@ -775,7 +772,7 @@
 		clock-div = <1>;
 	};
 
-	video1_div_clk: video1_div_clk {
+	video1_div_clk: clock-video1-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&video1_clkin_ck>;
@@ -783,7 +780,7 @@
 		clock-div = <1>;
 	};
 
-	video2_clk2_div: video2_clk2_div {
+	video2_clk2_div: clock-video2-clk2-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&video2_clkin_ck>;
@@ -791,7 +788,7 @@
 		clock-div = <1>;
 	};
 
-	video2_div_clk: video2_div_clk {
+	video2_div_clk: clock-video2-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&video2_clkin_ck>;
@@ -873,14 +870,14 @@
 		reg = <0x0580>;
 	};
 
-	dummy_ck: dummy_ck {
+	dummy_ck: clock-dummy {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <0>;
 	};
 };
 &prm_clocks {
-	sys_clkin1: sys_clkin1@110 {
+	sys_clkin1: clock-sys-clkin1@110 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
@@ -888,28 +885,28 @@
 		ti,index-starts-at-one;
 	};
 
-	abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
+	abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&sys_clkin2>;
 		reg = <0x0118>;
 	};
 
-	abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
+	abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 		reg = <0x0114>;
 	};
 
-	abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
+	abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 		reg = <0x010c>;
 	};
 
-	abe_24m_fclk: abe_24m_fclk@11c {
+	abe_24m_fclk: clock-abe-24m@11c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_m2x2_ck>;
@@ -917,7 +914,7 @@
 		ti,dividers = <8>, <16>;
 	};
 
-	aess_fclk: aess_fclk@178 {
+	aess_fclk: clock-aess@178 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&abe_clk>;
@@ -925,7 +922,7 @@
 		ti,max-div = <2>;
 	};
 
-	abe_giclk_div: abe_giclk_div@174 {
+	abe_giclk_div: clock-abe-giclk-div@174 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&aess_fclk>;
@@ -933,7 +930,7 @@
 		ti,max-div = <2>;
 	};
 
-	abe_lp_clk_div: abe_lp_clk_div@1d8 {
+	abe_lp_clk_div: clock-abe-lp-clk-div@1d8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_m2x2_ck>;
@@ -941,7 +938,7 @@
 		ti,dividers = <16>, <32>;
 	};
 
-	abe_sys_clk_div: abe_sys_clk_div@120 {
+	abe_sys_clk_div: clock-abe-sys-clk-div@120 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sys_clkin1>;
@@ -949,14 +946,14 @@
 		ti,max-div = <2>;
 	};
 
-	adc_gfclk_mux: adc_gfclk_mux@1dc {
+	adc_gfclk_mux: clock-adc-gfclk-mux@1dc {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
 		reg = <0x01dc>;
 	};
 
-	sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
+	sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sys_clkin1>;
@@ -965,7 +962,7 @@
 		ti,index-power-of-two;
 	};
 
-	sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
+	sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sys_clkin2>;
@@ -974,7 +971,7 @@
 		ti,index-power-of-two;
 	};
 
-	per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
+	per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_m2_ck>;
@@ -983,7 +980,7 @@
 		ti,index-power-of-two;
 	};
 
-	dsp_gclk_div: dsp_gclk_div@18c {
+	dsp_gclk_div: clock-dsp-gclk-div@18c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_dsp_m2_ck>;
@@ -992,7 +989,7 @@
 		ti,index-power-of-two;
 	};
 
-	gpu_dclk: gpu_dclk@1a0 {
+	gpu_dclk: clock-gpu-dclk@1a0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_gpu_m2_ck>;
@@ -1001,7 +998,7 @@
 		ti,index-power-of-two;
 	};
 
-	emif_phy_dclk_div: emif_phy_dclk_div@190 {
+	emif_phy_dclk_div: clock-emif-phy-dclk-div@190 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_ddr_m2_ck>;
@@ -1010,7 +1007,7 @@
 		ti,index-power-of-two;
 	};
 
-	gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
+	gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_gmac_m2_ck>;
@@ -1019,7 +1016,7 @@
 		ti,index-power-of-two;
 	};
 
-	gmac_main_clk: gmac_main_clk {
+	gmac_main_clk: clock-gmac-main {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&gmac_250m_dclk_div>;
@@ -1027,7 +1024,7 @@
 		clock-div = <2>;
 	};
 
-	l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
+	l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_usb_m2_ck>;
@@ -1036,7 +1033,7 @@
 		ti,index-power-of-two;
 	};
 
-	usb_otg_dclk_div: usb_otg_dclk_div@184 {
+	usb_otg_dclk_div: clock-usb-otg-dclk-div@184 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&usb_otg_clkin_ck>;
@@ -1045,7 +1042,7 @@
 		ti,index-power-of-two;
 	};
 
-	sata_dclk_div: sata_dclk_div@1c0 {
+	sata_dclk_div: clock-sata-dclk-div@1c0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sys_clkin1>;
@@ -1054,7 +1051,7 @@
 		ti,index-power-of-two;
 	};
 
-	pcie2_dclk_div: pcie2_dclk_div@1b8 {
+	pcie2_dclk_div: clock-pcie2-dclk-div@1b8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_pcie_ref_m2_ck>;
@@ -1063,7 +1060,7 @@
 		ti,index-power-of-two;
 	};
 
-	pcie_dclk_div: pcie_dclk_div@1b4 {
+	pcie_dclk_div: clock-pcie-dclk-div@1b4 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&apll_pcie_m2_ck>;
@@ -1072,7 +1069,7 @@
 		ti,index-power-of-two;
 	};
 
-	emu_dclk_div: emu_dclk_div@194 {
+	emu_dclk_div: clock-emu-dclk-div@194 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sys_clkin1>;
@@ -1081,7 +1078,7 @@
 		ti,index-power-of-two;
 	};
 
-	secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
+	secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&secure_32k_clk_src_ck>;
@@ -1090,28 +1087,28 @@
 		ti,index-power-of-two;
 	};
 
-	clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
+	clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
 		reg = <0x0158>;
 	};
 
-	clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
+	clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
 		reg = <0x015c>;
 	};
 
-	clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
+	clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
 		reg = <0x0160>;
 	};
 
-	custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+	custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&sys_clkin1>;
@@ -1119,21 +1116,21 @@
 		clock-div = <2>;
 	};
 
-	eve_clk: eve_clk@180 {
+	eve_clk: clock-eve@180 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
 		reg = <0x0180>;
 	};
 
-	hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
+	hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&sys_clkin2>;
 		reg = <0x0164>;
 	};
 
-	mlb_clk: mlb_clk@134 {
+	mlb_clk: clock-mlb@134 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&mlb_clkin_ck>;
@@ -1142,7 +1139,7 @@
 		ti,index-power-of-two;
 	};
 
-	mlbp_clk: mlbp_clk@130 {
+	mlbp_clk: clock-mlbp@130 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&mlbp_clkin_ck>;
@@ -1151,7 +1148,7 @@
 		ti,index-power-of-two;
 	};
 
-	per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
+	per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_m2_ck>;
@@ -1160,7 +1157,7 @@
 		ti,index-power-of-two;
 	};
 
-	timer_sys_clk_div: timer_sys_clk_div@144 {
+	timer_sys_clk_div: clock-timer-sys-clk-div@144 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sys_clkin1>;
@@ -1168,21 +1165,21 @@
 		ti,max-div = <2>;
 	};
 
-	video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
+	video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&sys_clkin2>;
 		reg = <0x0168>;
 	};
 
-	video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
+	video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&sys_clkin2>;
 		reg = <0x016c>;
 	};
 
-	wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
+	wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
@@ -1222,14 +1219,14 @@
 	};
 };
 &cm_core_clocks {
-	dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
+	dpll_pcie_ref_ck: clock@200 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&sys_clkin1>;
 		reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
 	};
 
-	dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
+	dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_pcie_ref_ck>;
@@ -1240,7 +1237,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
+	apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 {
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
 		#clock-cells = <0>;
@@ -1248,7 +1245,7 @@
 		ti,bit-shift = <7>;
 	};
 
-	apll_pcie_ck: apll_pcie_ck@21c {
+	apll_pcie_ck: clock@21c {
 		#clock-cells = <0>;
 		compatible = "ti,dra7-apll-clock";
 		clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
@@ -1271,7 +1268,7 @@
 		ti,bit-shift = <8>;
 	};
 
-	optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
+	optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c {
 		compatible = "ti,divider-clock";
 		clocks = <&apll_pcie_ck>;
 		#clock-cells = <0>;
@@ -1313,7 +1310,7 @@
 		ti,bit-shift = <10>;
 	};
 
-	apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
+	apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&apll_pcie_ck>;
@@ -1321,7 +1318,7 @@
 		clock-div = <1>;
 	};
 
-	apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
+	apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&apll_pcie_ck>;
@@ -1329,7 +1326,7 @@
 		clock-div = <1>;
 	};
 
-	apll_pcie_m2_ck: apll_pcie_m2_ck {
+	apll_pcie_m2_ck: clock-apll-pcie-m2 {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&apll_pcie_ck>;
@@ -1337,7 +1334,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_per_byp_mux: dpll_per_byp_mux@14c {
+	dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
@@ -1345,14 +1342,14 @@
 		reg = <0x014c>;
 	};
 
-	dpll_per_ck: dpll_per_ck@140 {
+	dpll_per_ck: clock@140 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
 		reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
 	};
 
-	dpll_per_m2_ck: dpll_per_m2_ck@150 {
+	dpll_per_m2_ck: clock-dpll-per-m2-8@150 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_ck>;
@@ -1363,7 +1360,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	func_96m_aon_dclk_div: func_96m_aon_dclk_div {
+	func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_per_m2_ck>;
@@ -1371,7 +1368,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
+	dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
@@ -1379,14 +1376,14 @@
 		reg = <0x018c>;
 	};
 
-	dpll_usb_ck: dpll_usb_ck@180 {
+	dpll_usb_ck: clock@180 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-j-type-clock";
 		clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
 		reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
 	};
 
-	dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
+	dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_usb_ck>;
@@ -1397,7 +1394,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
+	dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_pcie_ref_ck>;
@@ -1408,13 +1405,13 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_per_x2_ck: dpll_per_x2_ck {
+	dpll_per_x2_ck: clock-dpll-per-x2 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-x2-clock";
 		clocks = <&dpll_per_ck>;
 	};
 
-	dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
+	dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -1425,7 +1422,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
+	dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -1436,7 +1433,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
+	dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -1447,7 +1444,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
+	dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -1458,7 +1455,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
+	dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -1469,7 +1466,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+	dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_usb_ck>;
@@ -1477,7 +1474,7 @@
 		clock-div = <1>;
 	};
 
-	func_128m_clk: func_128m_clk {
+	func_128m_clk: clock-func-128m {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_per_h11x2_ck>;
@@ -1485,7 +1482,7 @@
 		clock-div = <2>;
 	};
 
-	func_12m_fclk: func_12m_fclk {
+	func_12m_fclk: clock-func-12m-fclk {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_per_m2x2_ck>;
@@ -1493,7 +1490,7 @@
 		clock-div = <16>;
 	};
 
-	func_24m_clk: func_24m_clk {
+	func_24m_clk: clock-func-24m {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_per_m2_ck>;
@@ -1501,7 +1498,7 @@
 		clock-div = <4>;
 	};
 
-	func_48m_fclk: func_48m_fclk {
+	func_48m_fclk: clock-func-48m-fclk {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_per_m2x2_ck>;
@@ -1509,7 +1506,7 @@
 		clock-div = <4>;
 	};
 
-	func_96m_fclk: func_96m_fclk {
+	func_96m_fclk: clock-func-96m-fclk {
 		#clock-cells = <0>;
 		compatible = "fixed-factor-clock";
 		clocks = <&dpll_per_m2x2_ck>;
@@ -1517,7 +1514,7 @@
 		clock-div = <2>;
 	};
 
-	l3init_60m_fclk: l3init_60m_fclk@104 {
+	l3init_60m_fclk: clock-l3init-60m@104 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_usb_m2_ck>;
@@ -1525,7 +1522,7 @@
 		ti,dividers = <1>, <8>;
 	};
 
-	clkout2_clk: clkout2_clk@6b0 {
+	clkout2_clk: clock-clkout2-8@6b0 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&clkoutmux2_clk_mux>;
@@ -1533,7 +1530,7 @@
 		reg = <0x06b0>;
 	};
 
-	l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
+	l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_usb_clkdcoldo>;
@@ -1702,7 +1699,7 @@
 		reg = <0x1340>;
 	};
 
-	usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
+	usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1710,7 +1707,7 @@
 		reg = <0x0640>;
 	};
 
-	usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
+	usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1718,7 +1715,7 @@
 		reg = <0x0688>;
 	};
 
-	usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
+	usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1758,7 +1755,7 @@
 		reg = <0x13d0>;
 	};
 
-	gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
+	gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
@@ -1768,7 +1765,7 @@
 		assigned-clock-parents = <&dpll_gpu_m2_ck>;
 	};
 
-	gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
+	gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
@@ -1778,7 +1775,7 @@
 		assigned-clock-parents = <&dpll_gpu_m2_ck>;
 	};
 
-	l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
+	l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&wkupaon_iclk_mux>;
@@ -2141,7 +2138,7 @@
 		reg = <0x18e8>;
 	};
 
-	vip1_gclk_mux: vip1_gclk_mux@1020 {
+	vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
@@ -2149,7 +2146,7 @@
 		reg = <0x1020>;
 	};
 
-	vip2_gclk_mux: vip2_gclk_mux@1028 {
+	vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
diff --git a/arch/arm/dts/dragonboard845c.dts b/arch/arm/dts/dragonboard845c.dts
index 1722dce..b4f057a 100644
--- a/arch/arm/dts/dragonboard845c.dts
+++ b/arch/arm/dts/dragonboard845c.dts
@@ -21,7 +21,7 @@
 	};
 
 	aliases {
-		serial0 = &debug_uart;
+		serial0 = &uart9;
 	};
 
 	memory {
diff --git a/arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi
new file mode 100644
index 0000000..298adb8
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <config.h>
+
+#include "fsl-ls1088a-u-boot.dtsi"
+
diff --git a/arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi
new file mode 100644
index 0000000..298adb8
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <config.h>
+
+#include "fsl-ls1088a-u-boot.dtsi"
+
diff --git a/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi
new file mode 100644
index 0000000..89566bf
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <config.h>
+
+#include "fsl-ls1088a-u-boot.dtsi"
+
+/{
+	aliases {
+		spi0 = &qspi;
+	};
+};
+
+&i2c0 {
+	uc: board-controller@7e {
+		compatible = "traverse,ten64-controller";
+		reg = <0x7e>;
+	};
+};
+
diff --git a/arch/arm/dts/fsl-ls1088a-ten64.dts b/arch/arm/dts/fsl-ls1088a-ten64.dts
index 55a7d41..0d11440 100644
--- a/arch/arm/dts/fsl-ls1088a-ten64.dts
+++ b/arch/arm/dts/fsl-ls1088a-ten64.dts
@@ -1,9 +1,10 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
- * Device Tree file for Travese Ten64 (LS1088) board
+ * Device Tree file for Traverse Technologies Ten64
+ * (LS1088A) board
  * Based on fsl-ls1088a-rdb.dts
  * Copyright 2017-2020 NXP
- * Copyright 2019-2021 Traverse Technologies
+ * Copyright 2019-2023 Traverse Technologies
  *
  * Author: Mathew McBride <matt@traverse.com.au>
  */
@@ -22,7 +23,6 @@
 	aliases {
 		serial0 = &duart0;
 		serial1 = &duart1;
-		spi0 = &qspi;
 	};
 
 	chosen {
@@ -36,18 +36,16 @@
 		 * external power off (e.g ATX Power Button)
 		 * asserted
 		 */
-		powerdn {
+		button-powerdn {
 			label = "External Power Down";
 			gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
-			interrupts = <&gpio1 17 IRQ_TYPE_EDGE_FALLING>;
 			linux,code = <KEY_POWER>;
 		};
 
 		/* Rear Panel 'ADMIN' button (GPIO_H) */
-		admin {
+		button-admin {
 			label = "ADMIN button";
 			gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
-			interrupts = <&gpio3 8 IRQ_TYPE_EDGE_RISING>;
 			linux,code = <KEY_WPS_BUTTON>;
 		};
 	};
@@ -55,17 +53,17 @@
 	leds {
 		compatible = "gpio-leds";
 
-		sfp1down {
+		led-0 {
 			label = "ten64:green:sfp1:down";
 			gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
 		};
 
-		sfp2up {
+		led-1 {
 			label = "ten64:green:sfp2:up";
 			gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
 		};
 
-		admin {
+		led-2 {
 			label = "ten64:admin";
 			gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>;
 		};
@@ -95,17 +93,17 @@
 /* XG1 - Upper SFP */
 &dpmac1 {
 	sfp = <&sfp_xg1>;
+	pcs-handle = <&pcs1>;
 	phy-connection-type = "10gbase-r";
 	managed = "in-band-status";
-	status = "okay";
 };
 
 /* XG0 - Lower SFP */
 &dpmac2 {
 	sfp = <&sfp_xg0>;
+	pcs-handle = <&pcs2>;
 	phy-connection-type = "10gbase-r";
 	managed = "in-band-status";
-	status = "okay";
 };
 
 /* DPMAC3..6 is GE4 to GE8 */
@@ -113,28 +111,28 @@
 	phy-handle = <&mdio1_phy5>;
 	phy-connection-type = "qsgmii";
 	managed = "in-band-status";
-	status = "okay";
+	pcs-handle = <&pcs3_0>;
 };
 
 &dpmac4 {
 	phy-handle = <&mdio1_phy6>;
 	phy-connection-type = "qsgmii";
 	managed = "in-band-status";
-	status = "okay";
+	pcs-handle = <&pcs3_1>;
 };
 
 &dpmac5 {
 	phy-handle = <&mdio1_phy7>;
 	phy-connection-type = "qsgmii";
 	managed = "in-band-status";
-	status = "okay";
+	pcs-handle = <&pcs3_2>;
 };
 
 &dpmac6 {
 	phy-handle = <&mdio1_phy8>;
 	phy-connection-type = "qsgmii";
 	managed = "in-band-status";
-	status = "okay";
+	pcs-handle = <&pcs3_3>;
 };
 
 /* DPMAC7..10 is GE0 to GE3 */
@@ -142,28 +140,28 @@
 	phy-handle = <&mdio1_phy1>;
 	phy-connection-type = "qsgmii";
 	managed = "in-band-status";
-	status = "okay";
+	pcs-handle = <&pcs7_0>;
 };
 
 &dpmac8 {
 	phy-handle = <&mdio1_phy2>;
 	phy-connection-type = "qsgmii";
 	managed = "in-band-status";
-	status = "okay";
+	pcs-handle = <&pcs7_1>;
 };
 
 &dpmac9 {
 	phy-handle = <&mdio1_phy3>;
 	phy-connection-type = "qsgmii";
 	managed = "in-band-status";
-	status = "okay";
+	pcs-handle = <&pcs7_2>;
 };
 
 &dpmac10 {
 	phy-handle = <&mdio1_phy4>;
 	phy-connection-type = "qsgmii";
 	managed = "in-band-status";
-	status = "okay";
+	pcs-handle = <&pcs7_3>;
 };
 
 &duart0 {
@@ -234,11 +232,6 @@
 		compatible = "atmel,at97sc3204t";
 		reg = <0x29>;
 	};
-
-	uc: board-controller@7e {
-		compatible = "traverse,ten64-controller";
-		reg = <0x7e>;
-	};
 };
 
 &i2c2 {
@@ -253,7 +246,7 @@
 &i2c3 {
 	status = "okay";
 
-	i2c-switch@70 {
+	i2c-mux@70 {
 		compatible = "nxp,pca9540";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -273,6 +266,22 @@
 	};
 };
 
+&pcs_mdio1 {
+	status = "okay";
+};
+
+&pcs_mdio2 {
+	status = "okay";
+};
+
+&pcs_mdio3 {
+	status = "okay";
+};
+
+&pcs_mdio7 {
+	status = "okay";
+};
+
 &qspi {
 	status = "okay";
 
diff --git a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi
new file mode 100644
index 0000000..efcfdd9
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <config.h>
+
+/{
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000 0 0x80000000>;
+		      /* DRAM space - 1, size : 2 GB DRAM */
+	};
+};
+
+&duart0 {
+	bootph-all;
+};
+
+&duart1 {
+	bootph-all;
+};
+
+/* MDIO controllers - U-Boot uses a different
+ * driver for the DPAA2 (LS/LX2) family,
+ * so must match fsl,ls-mdio first.
+ */
+&emdio1 {
+	compatible = "fsl,ls-mdio", "fsl,fman-memac-mdio";
+};
+
+&emdio2 {
+	compatible = "fsl,ls-mdio", "fsl,fman-memac-mdio";
+};
+
+/* DPAA2 Management Complex (MC)
+ * "simple-mfd" compatible used by U-Boot only,
+ * to allow driver model functionality.
+ */
+&fsl_mc {
+	compatible = "fsl,qoriq-mc", "simple-mfd";
+
+	dpmacs {
+		compatible = "simple-mfd";
+	};
+};
+
+&pcie1 {
+	status = "okay";
+};
+
+&pcie2 {
+	status = "okay";
+};
+
+&pcie3 {
+	status = "okay";
+};
+
+&usb0 {
+	compatible = "fsl,layerscape-dwc3", "snps,dwc3";
+};
+
+&usb1 {
+	compatible = "fsl,layerscape-dwc3", "snps,dwc3";
+};
+
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index 4782b83..e5fb137 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -1,39 +1,202 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
- * NXP ls1088a SOC common device tree source
+ * Device Tree Include file for NXP Layerscape-1088A family SoC.
  *
- * Copyright 2017, 2020-2021, 2023 NXP
+ * Copyright 2017-2020 NXP
+ *
+ * Harninder Rai <harninder.rai@nxp.com>
+ *
  */
-
 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
+
 / {
 	compatible = "fsl,ls1088a";
 	interrupt-parent = <&gic>;
 	#address-cells = <2>;
 	#size-cells = <2>;
 
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x00000000 0x80000000 0 0x80000000>;
-		      /* DRAM space - 1, size : 2 GB DRAM */
+	aliases {
+		crypto = &crypto;
+		rtc1 = &ftm_alarm0;
 	};
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* We have 2 clusters having 4 Cortex-A53 cores each */
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0>;
+			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
+			cpu-idle-states = <&CPU_PH20>;
+			#cooling-cells = <2>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x1>;
+			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
+			cpu-idle-states = <&CPU_PH20>;
+			#cooling-cells = <2>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x2>;
+			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
+			cpu-idle-states = <&CPU_PH20>;
+			#cooling-cells = <2>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x3>;
+			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
+			cpu-idle-states = <&CPU_PH20>;
+			#cooling-cells = <2>;
+		};
+
+		cpu4: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x100>;
+			clocks = <&clockgen QORIQ_CLK_CMUX 1>;
+			cpu-idle-states = <&CPU_PH20>;
+			#cooling-cells = <2>;
+		};
+
+		cpu5: cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x101>;
+			clocks = <&clockgen QORIQ_CLK_CMUX 1>;
+			cpu-idle-states = <&CPU_PH20>;
+			#cooling-cells = <2>;
+		};
+
+		cpu6: cpu@102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x102>;
+			clocks = <&clockgen QORIQ_CLK_CMUX 1>;
+			cpu-idle-states = <&CPU_PH20>;
+			#cooling-cells = <2>;
+		};
+
+		cpu7: cpu@103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x103>;
+			clocks = <&clockgen QORIQ_CLK_CMUX 1>;
+			cpu-idle-states = <&CPU_PH20>;
+			#cooling-cells = <2>;
+		};
+
+		CPU_PH20: cpu-ph20 {
+			compatible = "arm,idle-state";
+			idle-state-name = "PH20";
+			arm,psci-suspend-param = <0x0>;
+			entry-latency-us = <1000>;
+			exit-latency-us = <1000>;
+			min-residency-us = <3000>;
+		};
+	};
+
 	gic: interrupt-controller@6000000 {
 		compatible = "arm,gic-v3";
-		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
-		      <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
 		#interrupt-cells = <3>;
 		interrupt-controller;
-		interrupts = <1 9 0x4>;
+		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
+		      <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
+		      <0x0 0x0c0c0000 0 0x2000>, /* GICC */
+		      <0x0 0x0c0d0000 0 0x1000>, /* GICH */
+		      <0x0 0x0c0e0000 0 0x20000>; /* GICV */
+		interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		its: gic-its@6020000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0x6020000 0 0x20000>;
+		};
 	};
 
+	thermal-zones {
+		core-cluster {
+			polling-delay-passive = <1000>;
+			polling-delay = <5000>;
+			thermal-sensors = <&tmu 0>;
+
+			trips {
+				core_cluster_alert: core-cluster-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				core-cluster-crit {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&core_cluster_alert>;
+					cooling-device =
+						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		soc {
+			polling-delay-passive = <1000>;
+			polling-delay = <5000>;
+			thermal-sensors = <&tmu 1>;
+
+			trips {
+				soc-crit {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
-			     <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
-			     <1 11 0x8>, /* Virtual PPI, active-low */
-			     <1 10 0x8>; /* Hypervisor PPI, active-low */
+		interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
+			     <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
+			     <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
+			     <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
+	};
+
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
 	};
 
 	sysclk: sysclk {
@@ -43,6 +206,13 @@
 		clock-output-names = "sysclk";
 	};
 
+	reboot {
+		compatible = "syscon-reboot";
+		regmap = <&reset>;
+		offset = <0x0>;
+		mask = <0x02>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
@@ -57,6 +227,121 @@
 			clocks = <&sysclk>;
 		};
 
+		dcfg: dcfg@1e00000 {
+			compatible = "fsl,ls1088a-dcfg", "syscon";
+			reg = <0x0 0x1e00000 0x0 0x10000>;
+			little-endian;
+		};
+
+		reset: syscon@1e60000 {
+			compatible = "fsl,ls1088a-reset", "syscon";
+			reg = <0x0 0x1e60000 0x0 0x10000>;
+		};
+
+		isc: syscon@1f70000 {
+			compatible = "fsl,ls1088a-isc", "syscon";
+			reg = <0x0 0x1f70000 0x0 0x10000>;
+			little-endian;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x0 0x1f70000 0x10000>;
+
+			extirq: interrupt-controller@14 {
+				compatible = "fsl,ls1088a-extirq";
+				#interrupt-cells = <2>;
+				#address-cells = <0>;
+				interrupt-controller;
+				reg = <0x14 4>;
+				interrupt-map =
+					<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+					<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+					<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+					<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+					<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+					<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+					<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+					<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+					<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+					<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+					<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-map-mask = <0xf 0x0>;
+			};
+		};
+
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1028a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
+		tmu: tmu@1f80000 {
+			compatible = "fsl,qoriq-tmu";
+			reg = <0x0 0x1f80000 0x0 0x10000>;
+			interrupts = <0 23 0x4>;
+			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
+			fsl,tmu-calibration =
+				/* Calibration data group 1 */
+				<0x00000000 0x00000023
+				0x00000001 0x0000002a
+				0x00000002 0x00000030
+				0x00000003 0x00000037
+				0x00000004 0x0000003d
+				0x00000005 0x00000044
+				0x00000006 0x0000004a
+				0x00000007 0x00000051
+				0x00000008 0x00000057
+				0x00000009 0x0000005e
+				0x0000000a 0x00000064
+				0x0000000b 0x0000006b
+				/* Calibration data group 2 */
+				0x00010000 0x00000022
+				0x00010001 0x0000002a
+				0x00010002 0x00000032
+				0x00010003 0x0000003a
+				0x00010004 0x00000042
+				0x00010005 0x0000004a
+				0x00010006 0x00000052
+				0x00010007 0x0000005a
+				0x00010008 0x00000062
+				0x00010009 0x0000006a
+				/* Calibration data group 3 */
+				0x00020000 0x00000021
+				0x00020001 0x0000002b
+				0x00020002 0x00000035
+				0x00020003 0x00000040
+				0x00020004 0x0000004a
+				0x00020005 0x00000054
+				0x00020006 0x0000005e
+				/* Calibration data group 4 */
+				0x00030000 0x00000010
+				0x00030001 0x0000001c
+				0x00030002 0x00000027
+				0x00030003 0x00000032
+				0x00030004 0x0000003e
+				0x00030005 0x00000049
+				0x00030006 0x00000054
+				0x00030007 0x00000060>;
+			little-endian;
+			#thermal-sensor-cells = <1>;
+		};
+
+		dspi: spi@2100000 {
+			compatible = "fsl,ls1088a-dspi",
+				     "fsl,ls1021a-v1.0-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2100000 0x0 0x10000>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "dspi";
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(2)>;
+			spi-num-chipselects = <6>;
+			status = "disabled";
+		};
+
 		duart0: serial@21c0500 {
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x0 0x21c0500 0x0 0x100>;
@@ -64,7 +349,6 @@
 					    QORIQ_CLK_PLL_DIV(4)>;
 			interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
-			bootph-all;
 		};
 
 		duart1: serial@21c0600 {
@@ -74,328 +358,694 @@
 					    QORIQ_CLK_PLL_DIV(4)>;
 			interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
-			bootph-all;
 		};
-	};
 
-	i2c0: i2c@2000000 {
-		compatible = "fsl,vf610-i2c";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x0 0x2000000 0x0 0x10000>;
-		interrupts = <0 34 4>;
-	};
+		gpio0: gpio@2300000 {
+			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
+			reg = <0x0 0x2300000 0x0 0x10000>;
+			interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
+			little-endian;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
 
-	i2c1: i2c@2010000 {
-		compatible = "fsl,vf610-i2c";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x0 0x2010000 0x0 0x10000>;
-		interrupts = <0 34 4>;
-	};
+		gpio1: gpio@2310000 {
+			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
+			reg = <0x0 0x2310000 0x0 0x10000>;
+			interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
+			little-endian;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
 
-	i2c2: i2c@2020000 {
-		compatible = "fsl,vf610-i2c";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x0 0x2020000 0x0 0x10000>;
-		interrupts = <0 35 4>;
-	};
+		gpio2: gpio@2320000 {
+			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
+			reg = <0x0 0x2320000 0x0 0x10000>;
+			interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
+			little-endian;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
 
-	i2c3: i2c@2030000 {
-		compatible = "fsl,vf610-i2c";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x0 0x2030000 0x0 0x10000>;
-		interrupts = <0 35 4>;
-	};
+		gpio3: gpio@2330000 {
+			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
+			reg = <0x0 0x2330000 0x0 0x10000>;
+			interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
+			little-endian;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
 
-	dspi: dspi@2100000 {
-		compatible = "fsl,vf610-dspi";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x0 0x2100000 0x0 0x10000>;
-		interrupts = <0 26 0x4>; /* Level high type */
-		spi-num-chipselects = <6>;
-	};
+		ifc: memory-controller@2240000 {
+			compatible = "fsl,ifc";
+			reg = <0x0 0x2240000 0x0 0x20000>;
+			interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
+			little-endian;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			status = "disabled";
+		};
 
-	qspi: quadspi@1550000 {
-		compatible = "fsl,ls1088a-qspi";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x0 0x20c0000 0x0 0x10000>,
-			<0x0 0x20000000 0x0 0x10000000>;
-		reg-names = "QuadSPI", "QuadSPI-memory";
-		status = "disabled";
-	};
+		i2c0: i2c@2000000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2000000 0x0 0x10000>;
+			interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(8)>;
+			status = "disabled";
+		};
 
-	esdhc: esdhc@2140000 {
-		compatible = "fsl,esdhc";
-		reg = <0x0 0x2140000 0x0 0x10000>;
-		interrupts = <0 28 0x4>; /* Level high type */
-		little-endian;
-		bus-width = <4>;
-	};
+		i2c1: i2c@2010000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2010000 0x0 0x10000>;
+			interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(8)>;
+			status = "disabled";
+		};
 
-	gpio0: gpio@2300000 {
-		compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
-		reg = <0x0 0x2300000 0x0 0x10000>;
-		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-		little-endian;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
+		i2c2: i2c@2020000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2020000 0x0 0x10000>;
+			interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(8)>;
+			status = "disabled";
+		};
 
-	gpio1: gpio@2310000 {
-		compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
-		reg = <0x0 0x2310000 0x0 0x10000>;
-		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-		little-endian;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
+		i2c3: i2c@2030000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2030000 0x0 0x10000>;
+			interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(8)>;
+			status = "disabled";
+		};
 
-	gpio2: gpio@2320000 {
-		compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
-		reg = <0x0 0x2320000 0x0 0x10000>;
-		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-		little-endian;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
+		qspi: spi@20c0000 {
+			compatible = "fsl,ls2080a-qspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x20c0000 0x0 0x10000>,
+			      <0x0 0x20000000 0x0 0x10000000>;
+			reg-names = "QuadSPI", "QuadSPI-memory";
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "qspi_en", "qspi";
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>,
+				 <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			status = "disabled";
+		};
 
-	gpio3: gpio@2330000 {
-		compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
-		reg = <0x0 0x2330000 0x0 0x10000>;
-		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-		little-endian;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
+		esdhc: esdhc@2140000 {
+			compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
+			reg = <0x0 0x2140000 0x0 0x10000>;
+			interrupts = <0 28 0x4>; /* Level high type */
+			clock-frequency = <0>;
+			clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
+			voltage-ranges = <1800 1800 3300 3300>;
+			sdhci,auto-cmd12;
+			little-endian;
+			bus-width = <4>;
+			status = "disabled";
+		};
 
-	ifc: ifc@1530000 {
-		compatible = "fsl,ifc", "simple-bus";
-		reg = <0x0 0x2240000 0x0 0x20000>;
-		interrupts = <0 21 0x4>; /* Level high type */
-	};
+		usb0: usb@3100000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0x3100000 0x0 0x10000>;
+			interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "host";
+			snps,quirk-frame-length-adjustment = <0x20>;
+			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+			status = "disabled";
+		};
 
-	usb0: usb3@3100000 {
-		compatible = "fsl,layerscape-dwc3";
-		reg = <0x0 0x3100000 0x0 0x10000>;
-		interrupts = <0 80 0x4>; /* Level high type */
-		dr_mode = "host";
-	};
+		usb1: usb@3110000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0x3110000 0x0 0x10000>;
+			interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "host";
+			snps,quirk-frame-length-adjustment = <0x20>;
+			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+			status = "disabled";
+		};
 
-	usb1: usb3@3110000 {
-		compatible = "fsl,layerscape-dwc3";
-		reg = <0x0 0x3110000 0x0 0x10000>;
-		interrupts = <0 81 0x4>; /* Level high type */
-		dr_mode = "host";
-	};
+		sata: sata@3200000 {
+			compatible = "fsl,ls1088a-ahci";
+			reg = <0x0 0x3200000 0x0 0x10000>,
+				<0x7 0x100520 0x0 0x4>;
+			reg-names = "ahci", "sata-ecc";
+			interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			dma-coherent;
+			status = "disabled";
+		};
 
-	crypto: crypto@8000000 {
-		compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
-		fsl,sec-era = <8>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x00 0x8000000 0x100000>;
-		reg = <0x00 0x8000000 0x0 0x100000>;
-		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
-		dma-coherent;
+		crypto: crypto@8000000 {
+			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+			fsl,sec-era = <8>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x00 0x8000000 0x100000>;
+			reg = <0x00 0x8000000 0x0 0x100000>;
+			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+			dma-coherent;
+
+			sec_jr0: jr@10000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg = <0x10000 0x10000>;
+				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr1: jr@20000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg = <0x20000 0x10000>;
+				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr2: jr@30000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg = <0x30000 0x10000>;
+				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+			};
 
-		sec_jr0: jr@10000 {
-			compatible = "fsl,sec-v5.0-job-ring",
-				     "fsl,sec-v4.0-job-ring";
-			reg	   = <0x10000 0x10000>;
-			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			sec_jr3: jr@40000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg = <0x40000 0x10000>;
+				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			};
 		};
 
-		sec_jr1: jr@20000 {
-			compatible = "fsl,sec-v5.0-job-ring",
-				     "fsl,sec-v4.0-job-ring";
-			reg	   = <0x20000 0x10000>;
-			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+		pcie1: pcie@3400000 {
+			compatible = "fsl,ls1088a-pcie";
+			reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+			      <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
+			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "aer";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			dma-coherent;
+			num-viewport = <256>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			msi-parent = <&its>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
+			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+			status = "disabled";
 		};
 
-		sec_jr2: jr@30000 {
-			compatible = "fsl,sec-v5.0-job-ring",
-				     "fsl,sec-v4.0-job-ring";
-			reg	   = <0x30000 0x10000>;
-			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+		pcie_ep1: pcie-ep@3400000 {
+			compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
+			reg = <0x00 0x03400000 0x0 0x00100000>,
+			      <0x20 0x00000000 0x8 0x00000000>;
+			reg-names = "regs", "addr_space";
+			num-ib-windows = <24>;
+			num-ob-windows = <256>;
+			max-functions = /bits/ 8 <2>;
+			status = "disabled";
 		};
 
-		sec_jr3: jr@40000 {
-			compatible = "fsl,sec-v5.0-job-ring",
-				     "fsl,sec-v4.0-job-ring";
-			reg	   = <0x40000 0x10000>;
-			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+		pcie2: pcie@3500000 {
+			compatible = "fsl,ls1088a-pcie";
+			reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+			      <0x28 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
+			interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "aer";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			dma-coherent;
+			num-viewport = <6>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			msi-parent = <&its>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
+			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+			status = "disabled";
 		};
-	};
 
-	pcie1: pcie@3400000 {
-		compatible = "fsl,ls-pcie", "snps,dw-pcie";
-		reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
-		       0x00 0x03480000 0x0 0x80000   /* lut registers */
-		       0x00 0x034c0000 0x0 0x40000   /* pf controls registers */
-		       0x20 0x00000000 0x0 0x20000>; /* configuration space */
-		reg-names = "dbi", "lut", "ctrl", "config";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		num-lanes = <4>;
-		bus-range = <0x0 0xff>;
-		ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000   /* downstream I/O */
-			  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-	};
+		pcie_ep2: pcie-ep@3500000 {
+			compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
+			reg = <0x00 0x03500000 0x0 0x00100000>,
+			      <0x28 0x00000000 0x8 0x00000000>;
+			reg-names = "regs", "addr_space";
+			num-ib-windows = <6>;
+			num-ob-windows = <6>;
+			status = "disabled";
+		};
 
-	pcie2: pcie@3500000 {
-		compatible = "fsl,ls-pcie", "snps,dw-pcie";
-		reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
-		       0x00 0x03580000 0x0 0x80000   /* lut registers */
-		       0x00 0x035c0000 0x0 0x40000   /* pf controls registers */
-		       0x28 0x00000000 0x0 0x20000>; /* configuration space */
-		reg-names = "dbi", "lut", "ctrl", "config";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		num-lanes = <4>;
-		bus-range = <0x0 0xff>;
-		ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000   /* downstream I/O */
-			  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-	};
+		pcie3: pcie@3600000 {
+			compatible = "fsl,ls1088a-pcie";
+			reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+			      <0x30 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
+			interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "aer";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			dma-coherent;
+			num-viewport = <6>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			msi-parent = <&its>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
+			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+			status = "disabled";
+		};
 
-	pcie3: pcie@3600000 {
-		compatible = "fsl,ls-pcie", "snps,dw-pcie";
-		reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
-		       0x00 0x03680000 0x0 0x80000   /* lut registers */
-		       0x00 0x036c0000 0x0 0x40000   /* pf controls registers */
-		       0x30 0x00000000 0x0 0x20000>; /* configuration space */
-		reg-names = "dbi", "lut", "ctrl", "config";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		num-lanes = <8>;
-		bus-range = <0x0 0xff>;
-		ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000   /* downstream I/O */
-			  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-	};
+		pcie_ep3: pcie-ep@3600000 {
+			compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
+			reg = <0x00 0x03600000 0x0 0x00100000>,
+			      <0x30 0x00000000 0x8 0x00000000>;
+			reg-names = "regs", "addr_space";
+			num-ib-windows = <6>;
+			num-ob-windows = <6>;
+			status = "disabled";
+		};
 
-	sata: sata@3200000 {
-		compatible = "fsl,ls1088a-ahci";
-		reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
-		       0x7 0x100520  0x0 0x4>;	 /* ecc sata addr*/
-		reg-names = "ahci", "sata-ecc";
-		interrupts = <0 133 4>;
-		status = "disabled";
-	};
+		smmu: iommu@5000000 {
+			compatible = "arm,mmu-500";
+			reg = <0 0x5000000 0 0x800000>;
+			#iommu-cells = <1>;
+			stream-match-mask = <0x7C00>;
+			dma-coherent;
+			#global-interrupts = <12>;
+				     // global secure fault
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+				     // combined secure
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+				     // global non-secure fault
+				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+				     // combined non-secure
+				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+				     // performance counter interrupts 0-7
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     // per context interrupt, 64 interrupts
+				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+		};
 
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
+		console@8340020 {
+			compatible = "fsl,dpaa2-console";
+			reg = <0x00000000 0x08340020 0 0x2>;
+		};
+
+		ptp-timer@8b95000 {
+			compatible = "fsl,dpaa2-ptp";
+			reg = <0x0 0x8b95000 0x0 0x100>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(1)>;
+			little-endian;
+			fsl,extts-fifo;
+		};
+
+		emdio1: mdio@8b96000 {
+			compatible = "fsl,fman-memac-mdio";
+			reg = <0x0 0x8b96000 0x0 0x1000>;
+			little-endian;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-frequency = <2500000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(1)>;
+			status = "disabled";
+		};
+
+		emdio2: mdio@8b97000 {
+			compatible = "fsl,fman-memac-mdio";
+			reg = <0x0 0x8b97000 0x0 0x1000>;
+			little-endian;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-frequency = <2500000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(1)>;
+			status = "disabled";
+		};
 
-	fsl_mc: fsl-mc@80c000000 {
-		compatible = "fsl,qoriq-mc", "simple-mfd";
-		reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
-		      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
-		#address-cells = <3>;
-		#size-cells = <1>;
+		pcs_mdio1: mdio@8c07000 {
+			compatible = "fsl,fman-memac-mdio";
+			reg = <0x0 0x8c07000 0x0 0x1000>;
+			little-endian;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
 
-		/*
-		 * Region type 0x0 - MC portals
-		 * Region type 0x1 - QBMAN portals
-		 */
-		ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
-			  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
+			pcs1: ethernet-phy@0 {
+				reg = <0>;
+			};
+		};
 
-		dpmacs {
-			compatible = "simple-mfd";
+		pcs_mdio2: mdio@8c0b000 {
+			compatible = "fsl,fman-memac-mdio";
+			reg = <0x0 0x8c0b000 0x0 0x1000>;
+			little-endian;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			status = "disabled";
 
-			dpmac1: dpmac@1 {
-				compatible = "fsl,qoriq-mc-dpmac";
-				reg = <0x1>;
-				status = "disabled";
+			pcs2: ethernet-phy@0 {
+				reg = <0>;
 			};
+		};
+
+		pcs_mdio3: mdio@8c0f000 {
+			compatible = "fsl,fman-memac-mdio";
+			reg = <0x0 0x8c0f000 0x0 0x1000>;
+			little-endian;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
 
-			dpmac2: dpmac@2 {
-				compatible = "fsl,qoriq-mc-dpmac";
-				reg = <0x2>;
-				status = "disabled";
+			pcs3_0: ethernet-phy@0 {
+				reg = <0>;
 			};
 
-			dpmac3: dpmac@3 {
-				compatible = "fsl,qoriq-mc-dpmac";
-				reg = <0x3>;
-				status = "disabled";
+			pcs3_1: ethernet-phy@1 {
+				reg = <1>;
 			};
 
-			dpmac4: dpmac@4 {
-				compatible = "fsl,qoriq-mc-dpmac";
-				reg = <0x4>;
-				status = "disabled";
+			pcs3_2: ethernet-phy@2 {
+				reg = <2>;
 			};
 
-			dpmac5: dpmac@5 {
-				compatible = "fsl,qoriq-mc-dpmac";
-				reg = <0x5>;
-				status = "disabled";
+			pcs3_3: ethernet-phy@3 {
+				reg = <3>;
 			};
+		};
+
+		pcs_mdio7: mdio@8c1f000 {
+			compatible = "fsl,fman-memac-mdio";
+			reg = <0x0 0x8c1f000 0x0 0x1000>;
+			little-endian;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
 
-			dpmac6: dpmac@6 {
-				compatible = "fsl,qoriq-mc-dpmac";
-				reg = <0x6>;
-				status = "disabled";
+			pcs7_0: ethernet-phy@0 {
+				reg = <0>;
 			};
 
-			dpmac7: dpmac@7 {
-				compatible = "fsl,qoriq-mc-dpmac";
-				reg = <0x7>;
-				status = "disabled";
+			pcs7_1: ethernet-phy@1 {
+				reg = <1>;
 			};
 
-			dpmac8: dpmac@8 {
-				compatible = "fsl,qoriq-mc-dpmac";
-				reg = <0x8>;
-				status = "disabled";
+			pcs7_2: ethernet-phy@2 {
+				reg = <2>;
 			};
 
-			dpmac9: dpmac@9 {
-				compatible = "fsl,qoriq-mc-dpmac";
-				reg = <0x9>;
-				status = "disabled";
+			pcs7_3: ethernet-phy@3 {
+				reg = <3>;
 			};
+		};
+
+		cluster1_core0_watchdog: wdt@c000000 {
+			compatible = "arm,sp805", "arm,primecell";
+			reg = <0x0 0xc000000 0x0 0x1000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(16)>,
+				 <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(16)>;
+			clock-names = "wdog_clk", "apb_pclk";
+		};
+
+		cluster1_core1_watchdog: wdt@c010000 {
+			compatible = "arm,sp805", "arm,primecell";
+			reg = <0x0 0xc010000 0x0 0x1000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(16)>,
+				 <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(16)>;
+			clock-names = "wdog_clk", "apb_pclk";
+		};
+
+		cluster1_core2_watchdog: wdt@c020000 {
+			compatible = "arm,sp805", "arm,primecell";
+			reg = <0x0 0xc020000 0x0 0x1000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(16)>,
+				 <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(16)>;
+			clock-names = "wdog_clk", "apb_pclk";
+		};
+
+		cluster1_core3_watchdog: wdt@c030000 {
+			compatible = "arm,sp805", "arm,primecell";
+			reg = <0x0 0xc030000 0x0 0x1000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(16)>,
+				 <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(16)>;
+			clock-names = "wdog_clk", "apb_pclk";
+		};
+
+		cluster2_core0_watchdog: wdt@c100000 {
+			compatible = "arm,sp805", "arm,primecell";
+			reg = <0x0 0xc100000 0x0 0x1000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(16)>,
+				 <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(16)>;
+			clock-names = "wdog_clk", "apb_pclk";
+		};
+
+		cluster2_core1_watchdog: wdt@c110000 {
+			compatible = "arm,sp805", "arm,primecell";
+			reg = <0x0 0xc110000 0x0 0x1000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(16)>,
+				 <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(16)>;
+			clock-names = "wdog_clk", "apb_pclk";
+		};
+
+		cluster2_core2_watchdog: wdt@c120000 {
+			compatible = "arm,sp805", "arm,primecell";
+			reg = <0x0 0xc120000 0x0 0x1000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(16)>,
+				 <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(16)>;
+			clock-names = "wdog_clk", "apb_pclk";
+		};
+
+		cluster2_core3_watchdog: wdt@c130000 {
+			compatible = "arm,sp805", "arm,primecell";
+			reg = <0x0 0xc130000 0x0 0x1000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(16)>,
+				 <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(16)>;
+			clock-names = "wdog_clk", "apb_pclk";
+		};
+
+		fsl_mc: fsl-mc@80c000000 {
+			compatible = "fsl,qoriq-mc";
+			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
+			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
+			msi-parent = <&its>;
+			iommu-map = <0 &smmu 0 0>;	/* This is fixed-up by u-boot */
+			dma-coherent;
+			#address-cells = <3>;
+			#size-cells = <1>;
+
+			/*
+			 * Region type 0x0 - MC portals
+			 * Region type 0x1 - QBMAN portals
+			 */
+			ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
+				  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
+
+			dpmacs {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				dpmac1: ethernet@1 {
+					compatible = "fsl,qoriq-mc-dpmac";
+					reg = <1>;
+				};
+
+				dpmac2: ethernet@2 {
+					compatible = "fsl,qoriq-mc-dpmac";
+					reg = <2>;
+				};
 
-			dpmac10: dpmac@a {
-				compatible = "fsl,qoriq-mc-dpmac";
-				reg = <0xa>;
-				status = "disabled";
+				dpmac3: ethernet@3 {
+					compatible = "fsl,qoriq-mc-dpmac";
+					reg = <3>;
+				};
+
+				dpmac4: ethernet@4 {
+					compatible = "fsl,qoriq-mc-dpmac";
+					reg = <4>;
+				};
+
+				dpmac5: ethernet@5 {
+					compatible = "fsl,qoriq-mc-dpmac";
+					reg = <5>;
+				};
+
+				dpmac6: ethernet@6 {
+					compatible = "fsl,qoriq-mc-dpmac";
+					reg = <6>;
+				};
+
+				dpmac7: ethernet@7 {
+					compatible = "fsl,qoriq-mc-dpmac";
+					reg = <7>;
+				};
+
+				dpmac8: ethernet@8 {
+					compatible = "fsl,qoriq-mc-dpmac";
+					reg = <8>;
+				};
+
+				dpmac9: ethernet@9 {
+					compatible = "fsl,qoriq-mc-dpmac";
+					reg = <9>;
+				};
+
+				dpmac10: ethernet@a {
+					compatible = "fsl,qoriq-mc-dpmac";
+					reg = <0xa>;
+				};
 			};
 		};
-	};
 
-	emdio1: mdio@8B96000 {
-		compatible = "fsl,ls-mdio";
-		reg = <0x0 0x8B96000 0x0 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
+		rcpm: power-controller@1e34040 {
+			compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
+			reg = <0x0 0x1e34040 0x0 0x18>;
+			#fsl,rcpm-wakeup-cells = <6>;
+			little-endian;
+		};
+
+		ftm_alarm0: timer@2800000 {
+			compatible = "fsl,ls1088a-ftm-alarm";
+			reg = <0x0 0x2800000 0x0 0x10000>;
+			fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+		};
 	};
 
-	emdio2: mdio@8B97000 {
-		compatible = "fsl,ls-mdio";
-		reg = <0x0 0x8B97000 0x0 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
 	};
 };
diff --git a/arch/arm/dts/hi3798mv200-hc2910-2aghd05-u-boot.dtsi b/arch/arm/dts/hi3798mv200-hc2910-2aghd05-u-boot.dtsi
new file mode 100644
index 0000000..eb32076
--- /dev/null
+++ b/arch/arm/dts/hi3798mv200-hc2910-2aghd05-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "hi3798mv200-u-boot.dtsi"
+
+/* The clock driver is missing */
+&sd0 {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/hi3798mv200-hc2910-2aghd05.dts b/arch/arm/dts/hi3798mv200-hc2910-2aghd05.dts
new file mode 100644
index 0000000..c4ca5ed
--- /dev/null
+++ b/arch/arm/dts/hi3798mv200-hc2910-2aghd05.dts
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS File for Skyworth HC2910 with board label 2AGHD05 set-top box.
+ *
+ * Released under the GPLv2 only.
+ */
+
+/dts-v1/;
+
+#include "hi3798mv200.dtsi"
+
+/ {
+	// Usually known as Henan Guangdian HC2910
+	model = "Skyworth HC2910 with board label 2AGHD05";
+	compatible = "skyworth,hc2910-2aghd05", "hisilicon,hi3798mv200";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&emmc {
+	fifo-depth = <256>;
+	clock-frequency = <200000000>;
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	non-removable;
+	bus-width = <8>;
+	status = "okay";
+};
+
+&gmac {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	phy-handle = <&eth_phy1>;
+	phy-mode = "rgmii";
+	hisilicon,phy-reset-delays-us = <10000 10000 30000>;
+
+	eth_phy1: phy@3 {
+		reg = <3>;
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&sd0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/hi3798mv200-u-boot.dtsi b/arch/arm/dts/hi3798mv200-u-boot.dtsi
new file mode 100644
index 0000000..8917bcf
--- /dev/null
+++ b/arch/arm/dts/hi3798mv200-u-boot.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot addition to:
+ *  1) use platform data for the console
+ *
+ */
+
+#include <dt-bindings/reset/ti-syscon.h>
+
+/* The driver in U-Boot does not support "snps,dw-mshc" compatible. */
+&sd0 {
+	compatible = "hisilicon,hi3798mv200-dw-mshc";
+};
+
+&sd1 {
+	compatible = "hisilicon,hi3798mv200-dw-mshc";
+};
+
+/* The clock driver is missing */
+&uart0 {
+	clock = <75000000>;
+};
diff --git a/arch/arm/dts/hi3798mv200.dtsi b/arch/arm/dts/hi3798mv200.dtsi
new file mode 100644
index 0000000..fedf87a
--- /dev/null
+++ b/arch/arm/dts/hi3798mv200.dtsi
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS File for HiSilicon Hi3798mv200 SoC.
+ *
+ * Released under the GPLv2 only.
+ */
+
+#include <dt-bindings/clock/histb-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/reset/ti-syscon.h>
+
+/ {
+	compatible = "hisilicon,hi3798mv200";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+		};
+
+		cpu@1 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+		};
+
+		cpu@2 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+		};
+
+		cpu@3 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+		};
+	};
+
+	gic: interrupt-controller@f1001000 {
+		compatible = "arm,gic-400";
+		reg = <0x0 0xf1001000 0x0 0x1000>,  /* GICD */
+		      <0x0 0xf1002000 0x0 0x100>;   /* GICC */
+		#address-cells = <0>;
+		#interrupt-cells = <3>;
+		interrupt-controller;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+			      IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+			      IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+			      IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+			      IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	/* Initialization is done in boot loader */
+	usb2_phy1: hsusb1_phy {
+		compatible = "usb-nop-xceiv";
+		clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
+		clock-names = "main";
+		#phy-cells = <0>;
+	};
+
+	soc: soc@f0000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0xf0000000 0x10000000>;
+
+		crg: clock-reset-controller@8a22000 {
+			compatible = "hisilicon,hi3798mv200-crg", "syscon", "simple-mfd";
+			reg = <0x8a22000 0x1000>;
+			#clock-cells = <1>;
+			#reset-cells = <2>;
+		};
+
+		sysctrl: system-controller@8000000 {
+			compatible = "hisilicon,hi3798mv200-sysctrl", "syscon";
+			reg = <0x8000000 0x1000>;
+			#clock-cells = <1>;
+			#reset-cells = <2>;
+		};
+
+		perictrl: peripheral-controller@8a20000 {
+			compatible = "hisilicon,hi3798mv200-perictrl", "syscon",
+				     "simple-mfd";
+			reg = <0x8a20000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x8a20000 0x1000>;
+
+			combphy0: phy@850 {
+				compatible = "hisilicon,hi3798mv200-combphy";
+				reg = <0x850 0x8>;
+				#phy-cells = <1>;
+				clocks = <&crg HISTB_COMBPHY0_CLK>;
+				resets = <&crg 0x188 4>;
+				assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
+				assigned-clock-rates = <100000000>;
+				hisilicon,fixed-mode = <PHY_TYPE_USB3>;
+			};
+		};
+
+		pmx0: pinconf@8a21000 {
+			compatible = "pinconf-single";
+			reg = <0x8a21000 0x180>;
+			pinctrl-single,register-width = <32>;
+			pinctrl-single,function-mask = <7>;
+		};
+
+		uart0: serial@8b00000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x8b00000 0x1000>;
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysctrl HISTB_UART0_CLK>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		sd0: mmc@9820000 {
+			compatible = "snps,dw-mshc";
+			reg = <0x9820000 0x10000>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg HISTB_SDIO0_CIU_CLK>,
+				 <&crg HISTB_SDIO0_BIU_CLK>;
+			clock-names = "ciu", "biu";
+			resets = <&crg 0x9c 4>;
+			reset-names = "reset";
+			status = "disabled";
+		};
+
+		emmc: mmc@9830000 {
+			compatible = "hisilicon,hi3798mv200-dw-mshc";
+			reg = <0x9830000 0x10000>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg HISTB_MMC_CIU_CLK>,
+				 <&crg HISTB_MMC_BIU_CLK>,
+				 <&crg HISTB_MMC_SAMPLE_CLK>,
+				 <&crg HISTB_MMC_DRV_CLK>;
+			clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
+			resets = <&crg 0xa0 4>;
+			reset-names = "reset";
+			status = "disabled";
+		};
+
+		gmac: ethernet@9840000 {
+			compatible = "hisilicon,hi3798mv200-gmac", "hisilicon,hisi-gmac-v2";
+			reg = <0x9840000 0x1000>,
+			      <0x984300c 0x4>;
+			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg HISTB_ETH0_MAC_CLK>,
+				 <&crg HISTB_ETH0_MACIF_CLK>;
+			clock-names = "mac_core", "mac_ifc";
+			resets = <&crg 0xcc 0>,
+				 <&crg 0xcc 2>,
+				 <&crg 0xcc 5>;
+			reset-names = "mac_core", "mac_ifc", "phy";
+			status = "disabled";
+		};
+
+		ohci: ohci@9880000 {
+			compatible = "generic-ohci";
+			reg = <0x9880000 0x10000>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg HISTB_USB2_BUS_CLK>,
+				 <&crg HISTB_USB2_12M_CLK>,
+				 <&crg HISTB_USB2_48M_CLK>;
+			clock-names = "bus", "clk12", "clk48";
+			resets = <&crg 0xb8 12>;
+			reset-names = "bus";
+			status = "disabled";
+		};
+
+		ehci: ehci@9890000 {
+			compatible = "generic-ehci";
+			reg = <0x9890000 0x10000>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg HISTB_USB2_BUS_CLK>,
+				 <&crg HISTB_USB2_PHY_CLK>,
+				 <&crg HISTB_USB2_UTMI_CLK>;
+			clock-names = "bus", "phy", "utmi";
+			resets = <&crg 0xb8 12>,
+				 <&crg 0xb8 16>,
+				 <&crg 0xb8 13>;
+			reset-names = "bus", "phy", "utmi";
+			phys = <&usb2_phy1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		sd1: mmc@9c40000 {
+			compatible = "snps,dw-mshc";
+			reg = <0x9c40000 0x10000>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg HISTB_SDIO1_CIU_CLK>,
+				 <&crg HISTB_SDIO1_BIU_CLK>;
+			clock-names = "ciu", "biu";
+			resets = <&crg 0x28c 4>;
+			reset-names = "reset";
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
new file mode 100644
index 0000000..46a4dfe
--- /dev/null
+++ b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "imx8mq-u-boot.dtsi"
+
+&pinctrl_uart1 {
+	bootph-pre-ram;
+};
+
+&uart1 { /* console */
+	bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx8qm-dmsse20-a1.dts b/arch/arm/dts/imx8qm-dmsse20-a1.dts
new file mode 100644
index 0000000..cff150d
--- /dev/null
+++ b/arch/arm/dts/imx8qm-dmsse20-a1.dts
@@ -0,0 +1,397 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2017-2018 NXP
+ * Copyright 2019-2023 Kococonnector GmbH
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x80000000 0x00020000;
+
+#include "fsl-imx8qm.dtsi"
+#include "imx8qm-u-boot.dtsi"
+
+/ {
+	model = "Advantech iMX8QM DMSSE20";
+	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
+
+	aliases {
+		mmc0 = &usdhc1;
+		mmc2 = &usdhc3;
+	};
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon";
+		stdout-path = &lpuart0;
+	};
+
+	reg_usb_otg1_vbus: usb_otg1_vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg1_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_usdhc2_vmmc: usdhc2_vmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "sw-3p3-sd1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx8qm-mek {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000048
+			>;
+		};
+
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD	0x000014a0
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x00000060
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000060
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000060
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x00000060
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x00000060
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x00000060
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000060
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000060
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x00000060
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x00000060
+			>;
+		};
+
+		pinctrl_fec2: fec2grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD	0x000014a0
+				SC_P_ENET1_MDC_CONN_ENET1_MDC			0x06000020
+				SC_P_ENET1_MDIO_CONN_ENET1_MDIO			0x06000020
+				SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x00000060
+				SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC	0x00000060
+				SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0	0x00000060
+				SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1	0x00000060
+				SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2	0x00000060
+				SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3	0x00000060
+				SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC	0x00000060
+				SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x00000060
+				SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0	0x00000060
+				SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1	0x00000060
+				SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2	0x00000060
+				SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3	0x00000060
+			>;
+		};
+
+		pinctrl_lpi2c1: lpi2c1grp {
+			fsl,pins = <
+				SC_P_GPT0_CLK_DMA_I2C1_SCL		0xc600004c
+				SC_P_GPT0_CAPTURE_DMA_I2C1_SDA		0xc600004c
+			>;
+		};
+
+		pinctrl_lpi2c2: lpi2c2grp {
+			fsl,pins = <
+				SC_P_GPT1_CLK_DMA_I2C2_SCL		0xc600004c
+				SC_P_GPT1_CAPTURE_DMA_I2C2_SDA		0xc600004c
+			>;
+		};
+
+		pinctrl_lpuart0: lpuart0grp {
+			fsl,pins = <
+				SC_P_UART0_RX_DMA_UART0_RX		0x06000020
+				SC_P_UART0_TX_DMA_UART0_TX		0x06000020
+			>;
+		};
+
+		pinctrl_rtc_mc_8803: rtc-mc-8803-grp{
+			fsl,pins = <
+				SC_P_SIM0_POWER_EN_DMA_I2C3_SDA		0xc600004c
+				SC_P_SIM0_PD_DMA_I2C3_SCL		0xc600004c
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000041
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07	0x00000020
+				SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc3_gpio: usdhc3grpgpio {
+			fsl,pins = <
+				SC_P_USDHC2_WP_LSIO_GPIO4_IO11          0x00000021
+				SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12        0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000041
+				SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000021
+				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000021
+				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000021
+				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000021
+				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000021
+				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+			fsl,pins = <
+				SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000040
+				SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000020
+				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000020
+				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000020
+				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000020
+				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000020
+				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+			fsl,pins = <
+				SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000040
+				SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000020
+				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000020
+				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000020
+				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000020
+				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000020
+				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000020
+			>;
+		};
+	};
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&usdhc1 {
+	bus-width = <8>;
+	non-removable;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	status = "okay";
+};
+
+&usdhc2 {
+	bus-width = <4>;
+	cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&usdhc3 {
+	bus-width = <4>;
+	cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
+	no-1-8-v;
+	pinctrl-names = "default","state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
+	wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&fec1 {
+	fsl,ar8031-phy-fixup;
+	fsl,magic-packet;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+		};
+	};
+};
+
+&fec2 {
+	fsl,ar8031-phy-fixup;
+	fsl,magic-packet;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec2>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy1>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy1: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+		};
+	};
+};
+
+&i2c1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c1>;
+	status = "okay";
+};
+
+&i2c2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c2>;
+	status = "okay";
+};
+
+&i2c3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rtc_mc_8803>;
+	status = "okay";
+
+	rv8803@32 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "microcrystal,rv8803";
+		reg = <0x32>;
+	};
+
+	24c02@50 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "atmel,24c04";
+		reg = <0x50>;
+	};
+};
+
+&lpuart0 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart0>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts
index dad4670..78df7ce 100644
--- a/arch/arm/dts/k3-am625-r5-sk.dts
+++ b/arch/arm/dts/k3-am625-r5-sk.dts
@@ -47,7 +47,8 @@
 		compatible = "ti,am654-rproc";
 		reg = <0x00 0x00a90000 0x00 0x10>;
 		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
 		resets = <&k3_reset 135 0>;
 		clocks = <&k3_clks 61 0>;
 		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts
index c953a82..cc4b179 100644
--- a/arch/arm/dts/k3-am62a7-r5-sk.dts
+++ b/arch/arm/dts/k3-am62a7-r5-sk.dts
@@ -47,7 +47,8 @@
 		compatible = "ti,am654-rproc";
 		reg = <0x00 0x00a90000 0x00 0x10>;
 		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
 		resets = <&k3_reset 135 0>;
 		clocks = <&k3_clks 61 0>;
 		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts
index ca5ce4a..e870492 100644
--- a/arch/arm/dts/k3-am642-r5-evm.dts
+++ b/arch/arm/dts/k3-am642-r5-evm.dts
@@ -32,7 +32,8 @@
 		compatible = "ti,am654-rproc";
 		reg = <0x00 0x00a90000 0x00 0x10>;
 		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
 		resets = <&k3_reset 135 0>;
 		clocks = <&k3_clks 61 0>;
 		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts
index 9ff4dd3..32d4c31 100644
--- a/arch/arm/dts/k3-am642-r5-sk.dts
+++ b/arch/arm/dts/k3-am642-r5-sk.dts
@@ -34,7 +34,8 @@
 		compatible = "ti,am654-rproc";
 		reg = <0x00 0x00a90000 0x00 0x10>;
 		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
 		resets = <&k3_reset 135 0>;
 		clocks = <&k3_clks 61 0>;
 		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi
index e7e0ca4..e73458c 100644
--- a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi
@@ -49,5 +49,3 @@
 	snps,dis-u1-entry-quirk;
 	snps,dis-u2-entry-quirk;
 };
-
-#include "k3-am65-iot2050-common-pg2-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi b/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi
index 0d215b4..4a9bf7d 100644
--- a/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi
+++ b/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi
@@ -11,9 +11,6 @@
 
 #include "k3-am65-iot2050-common.dtsi"
 
-#include "k3-am65-iot2050-common-u-boot.dtsi"
-#include "k3-am65-iot2050-boot-image.dtsi"
-
 / {
 	memory@80000000 {
 		device_type = "memory";
diff --git a/arch/arm/dts/k3-am6528-iot2050-basic-pg2-u-boot.dtsi b/arch/arm/dts/k3-am6528-iot2050-basic-pg2-u-boot.dtsi
new file mode 100644
index 0000000..1e39304
--- /dev/null
+++ b/arch/arm/dts/k3-am6528-iot2050-basic-pg2-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2023
+ *
+ * Authors:
+ *   Jan Kiszka <jan.kiszka@siemens.com>
+ */
+
+#include "k3-am65-iot2050-common-u-boot.dtsi"
+#include "k3-am65-iot2050-common-pg2-u-boot.dtsi"
+#include "k3-am65-iot2050-boot-image.dtsi"
diff --git a/arch/arm/dts/k3-am6528-iot2050-basic-u-boot.dtsi b/arch/arm/dts/k3-am6528-iot2050-basic-u-boot.dtsi
new file mode 100644
index 0000000..64afe25
--- /dev/null
+++ b/arch/arm/dts/k3-am6528-iot2050-basic-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2023
+ *
+ * Authors:
+ *   Jan Kiszka <jan.kiszka@siemens.com>
+ */
+
+#include "k3-am65-iot2050-common-u-boot.dtsi"
+#include "k3-am65-iot2050-boot-image.dtsi"
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi
index 816a4cb..d25e8b2 100644
--- a/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi
+++ b/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi
@@ -13,9 +13,6 @@
 
 #include "k3-am65-iot2050-common.dtsi"
 
-#include "k3-am65-iot2050-common-u-boot.dtsi"
-#include "k3-am65-iot2050-boot-image.dtsi"
-
 / {
 	memory@80000000 {
 		device_type = "memory";
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-u-boot.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-m2-u-boot.dtsi
new file mode 120000
index 0000000..859776d
--- /dev/null
+++ b/arch/arm/dts/k3-am6548-iot2050-advanced-m2-u-boot.dtsi
@@ -0,0 +1 @@
+k3-am6528-iot2050-basic-pg2-u-boot.dtsi
\ No newline at end of file
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-pg2-u-boot.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-pg2-u-boot.dtsi
new file mode 120000
index 0000000..859776d
--- /dev/null
+++ b/arch/arm/dts/k3-am6548-iot2050-advanced-pg2-u-boot.dtsi
@@ -0,0 +1 @@
+k3-am6528-iot2050-basic-pg2-u-boot.dtsi
\ No newline at end of file
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-u-boot.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-u-boot.dtsi
new file mode 120000
index 0000000..ac30e4e
--- /dev/null
+++ b/arch/arm/dts/k3-am6548-iot2050-advanced-u-boot.dtsi
@@ -0,0 +1 @@
+k3-am6528-iot2050-basic-u-boot.dtsi
\ No newline at end of file
diff --git a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
index 42ac8c5..9ec8dff 100644
--- a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
+++ b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
@@ -1,12 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.5.0
- * This file was generated on 08/07/2020
- * Includes hand-edits
- */
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.0
+ * This file was generated on 06/01/2021
+*/
 
 #define DDRSS_PLL_FHS_CNT 10
+#define DDRSS_PLL_FREQUENCY_0 27500000
 #define DDRSS_PLL_FREQUENCY_1 666500000
 #define DDRSS_PLL_FREQUENCY_2 666500000
 
@@ -17,10 +17,10 @@
 #define DDRSS_CTL_04_DATA 0x00000000
 #define DDRSS_CTL_05_DATA 0x00000000
 #define DDRSS_CTL_06_DATA 0x00000000
-#define DDRSS_CTL_07_DATA 0x00002710
-#define DDRSS_CTL_08_DATA 0x000186A0
+#define DDRSS_CTL_07_DATA 0x00002AF8
+#define DDRSS_CTL_08_DATA 0x0001ADAF
 #define DDRSS_CTL_09_DATA 0x00000005
-#define DDRSS_CTL_10_DATA 0x00000064
+#define DDRSS_CTL_10_DATA 0x0000006E
 #define DDRSS_CTL_11_DATA 0x000411AB
 #define DDRSS_CTL_12_DATA 0x0028B0AB
 #define DDRSS_CTL_13_DATA 0x00000005
@@ -33,11 +33,11 @@
 #define DDRSS_CTL_20_DATA 0x02011001
 #define DDRSS_CTL_21_DATA 0x02010000
 #define DDRSS_CTL_22_DATA 0x00020100
-#define DDRSS_CTL_23_DATA 0x0000000A
-#define DDRSS_CTL_24_DATA 0x00000019
+#define DDRSS_CTL_23_DATA 0x0000000B
+#define DDRSS_CTL_24_DATA 0x0000001C
 #define DDRSS_CTL_25_DATA 0x00000000
 #define DDRSS_CTL_26_DATA 0x00000000
-#define DDRSS_CTL_27_DATA 0x02020200
+#define DDRSS_CTL_27_DATA 0x03020200
 #define DDRSS_CTL_28_DATA 0x00003636
 #define DDRSS_CTL_29_DATA 0x00100000
 #define DDRSS_CTL_30_DATA 0x00000000
@@ -54,7 +54,7 @@
 #define DDRSS_CTL_41_DATA 0x113C0057
 #define DDRSS_CTL_42_DATA 0x2000291B
 #define DDRSS_CTL_43_DATA 0x000A0A09
-#define DDRSS_CTL_44_DATA 0x040006DB
+#define DDRSS_CTL_44_DATA 0x0400078A
 #define DDRSS_CTL_45_DATA 0x130E0B04
 #define DDRSS_CTL_46_DATA 0x0A00B6D0
 #define DDRSS_CTL_47_DATA 0x130E0B0A
@@ -62,7 +62,7 @@
 #define DDRSS_CTL_49_DATA 0x0203040A
 #define DDRSS_CTL_50_DATA 0x1C040500
 #define DDRSS_CTL_51_DATA 0x081D1C1D
-#define DDRSS_CTL_52_DATA 0x14000D0A
+#define DDRSS_CTL_52_DATA 0x14000E0A
 #define DDRSS_CTL_53_DATA 0x02010A0A
 #define DDRSS_CTL_54_DATA 0x01010002
 #define DDRSS_CTL_55_DATA 0x04383808
@@ -70,15 +70,15 @@
 #define DDRSS_CTL_57_DATA 0x00001F1F
 #define DDRSS_CTL_58_DATA 0x00010100
 #define DDRSS_CTL_59_DATA 0x03010000
-#define DDRSS_CTL_60_DATA 0x00000E08
-#define DDRSS_CTL_61_DATA 0x000000BB
+#define DDRSS_CTL_60_DATA 0x00001008
+#define DDRSS_CTL_61_DATA 0x000000CE
 #define DDRSS_CTL_62_DATA 0x00000176
 #define DDRSS_CTL_63_DATA 0x00001448
 #define DDRSS_CTL_64_DATA 0x00000176
 #define DDRSS_CTL_65_DATA 0x00001448
 #define DDRSS_CTL_66_DATA 0x00000005
-#define DDRSS_CTL_67_DATA 0x00030000
-#define DDRSS_CTL_68_DATA 0x005D0010
+#define DDRSS_CTL_67_DATA 0x00040000
+#define DDRSS_CTL_68_DATA 0x005D0012
 #define DDRSS_CTL_69_DATA 0x005D0282
 #define DDRSS_CTL_70_DATA 0x00400282
 #define DDRSS_CTL_71_DATA 0x00120103
@@ -89,7 +89,7 @@
 #define DDRSS_CTL_76_DATA 0x03130A07
 #define DDRSS_CTL_77_DATA 0x0A070301
 #define DDRSS_CTL_78_DATA 0x00010313
-#define DDRSS_CTL_79_DATA 0x000F000F
+#define DDRSS_CTL_79_DATA 0x00100010
 #define DDRSS_CTL_80_DATA 0x01800180
 #define DDRSS_CTL_81_DATA 0x01800180
 #define DDRSS_CTL_82_DATA 0x03050505
@@ -112,13 +112,13 @@
 #define DDRSS_CTL_99_DATA 0x00000000
 #define DDRSS_CTL_100_DATA 0x00040005
 #define DDRSS_CTL_101_DATA 0x00000000
-#define DDRSS_CTL_102_DATA 0x00002EC0
-#define DDRSS_CTL_103_DATA 0x00002EC0
-#define DDRSS_CTL_104_DATA 0x00002EC0
-#define DDRSS_CTL_105_DATA 0x00002EC0
-#define DDRSS_CTL_106_DATA 0x00002EC0
+#define DDRSS_CTL_102_DATA 0x00003380
+#define DDRSS_CTL_103_DATA 0x00003380
+#define DDRSS_CTL_104_DATA 0x00003380
+#define DDRSS_CTL_105_DATA 0x00003380
+#define DDRSS_CTL_106_DATA 0x00003380
 #define DDRSS_CTL_107_DATA 0x00000000
-#define DDRSS_CTL_108_DATA 0x0000051D
+#define DDRSS_CTL_108_DATA 0x000005A2
 #define DDRSS_CTL_109_DATA 0x00051200
 #define DDRSS_CTL_110_DATA 0x00051200
 #define DDRSS_CTL_111_DATA 0x00051200
@@ -174,9 +174,9 @@
 #define DDRSS_CTL_161_DATA 0x00000000
 #define DDRSS_CTL_162_DATA 0x00000000
 #define DDRSS_CTL_163_DATA 0x00000000
-#define DDRSS_CTL_164_DATA 0x000A0000
-#define DDRSS_CTL_165_DATA 0x000D0005
-#define DDRSS_CTL_166_DATA 0x000D0404
+#define DDRSS_CTL_164_DATA 0x000B0000
+#define DDRSS_CTL_165_DATA 0x000E0006
+#define DDRSS_CTL_166_DATA 0x000E0404
 #define DDRSS_CTL_167_DATA 0x0086010B
 #define DDRSS_CTL_168_DATA 0x0A0A014E
 #define DDRSS_CTL_169_DATA 0x010B014E
@@ -191,7 +191,7 @@
 #define DDRSS_CTL_178_DATA 0x36000000
 #define DDRSS_CTL_179_DATA 0x27270036
 #define DDRSS_CTL_180_DATA 0x0F0F0000
-#define DDRSS_CTL_181_DATA 0x00000000
+#define DDRSS_CTL_181_DATA 0x15000000
 #define DDRSS_CTL_182_DATA 0x00841515
 #define DDRSS_CTL_183_DATA 0x24C424C4
 #define DDRSS_CTL_184_DATA 0x2B2B2B00
@@ -199,7 +199,7 @@
 #define DDRSS_CTL_186_DATA 0x00363600
 #define DDRSS_CTL_187_DATA 0x00002727
 #define DDRSS_CTL_188_DATA 0x00000F0F
-#define DDRSS_CTL_189_DATA 0x15150000
+#define DDRSS_CTL_189_DATA 0x15151500
 #define DDRSS_CTL_190_DATA 0x00000020
 #define DDRSS_CTL_191_DATA 0x00000000
 #define DDRSS_CTL_192_DATA 0x00000001
@@ -268,7 +268,7 @@
 #define DDRSS_CTL_255_DATA 0x00000000
 #define DDRSS_CTL_256_DATA 0x00000000
 #define DDRSS_CTL_257_DATA 0x01000200
-#define DDRSS_CTL_258_DATA 0x00320040
+#define DDRSS_CTL_258_DATA 0x00370040
 #define DDRSS_CTL_259_DATA 0x00020008
 #define DDRSS_CTL_260_DATA 0x00400100
 #define DDRSS_CTL_261_DATA 0x00280536
@@ -399,13 +399,13 @@
 #define DDRSS_CTL_386_DATA 0x00000000
 #define DDRSS_CTL_387_DATA 0x2E2E1B00
 #define DDRSS_CTL_388_DATA 0x000A0000
-#define DDRSS_CTL_389_DATA 0x00000176
+#define DDRSS_CTL_389_DATA 0x0000019C
 #define DDRSS_CTL_390_DATA 0x00000200
 #define DDRSS_CTL_391_DATA 0x00000200
 #define DDRSS_CTL_392_DATA 0x00000200
 #define DDRSS_CTL_393_DATA 0x00000200
-#define DDRSS_CTL_394_DATA 0x00000462
-#define DDRSS_CTL_395_DATA 0x00000E9C
+#define DDRSS_CTL_394_DATA 0x000004D4
+#define DDRSS_CTL_395_DATA 0x00001018
 #define DDRSS_CTL_396_DATA 0x00000204
 #define DDRSS_CTL_397_DATA 0x00002890
 #define DDRSS_CTL_398_DATA 0x00000200
@@ -432,7 +432,7 @@
 #define DDRSS_CTL_419_DATA 0x00000000
 #define DDRSS_CTL_420_DATA 0x00000000
 #define DDRSS_CTL_421_DATA 0x00030000
-#define DDRSS_CTL_422_DATA 0x0006001E
+#define DDRSS_CTL_422_DATA 0x0007001F
 #define DDRSS_CTL_423_DATA 0x0013002B
 #define DDRSS_CTL_424_DATA 0x0013002B
 #define DDRSS_CTL_425_DATA 0x00000000
@@ -633,14 +633,14 @@
 #define DDRSS_PI_160_DATA 0x00000000
 #define DDRSS_PI_161_DATA 0x00010000
 #define DDRSS_PI_162_DATA 0x00000000
-#define DDRSS_PI_163_DATA 0x1B1B0100
+#define DDRSS_PI_163_DATA 0x1B1B0200
 #define DDRSS_PI_164_DATA 0x00000034
 #define DDRSS_PI_165_DATA 0x00000051
 #define DDRSS_PI_166_DATA 0x00020051
 #define DDRSS_PI_167_DATA 0x02000200
 #define DDRSS_PI_168_DATA 0x300C0C04
-#define DDRSS_PI_169_DATA 0x000E300C
-#define DDRSS_PI_170_DATA 0x000000BB
+#define DDRSS_PI_169_DATA 0x0010300C
+#define DDRSS_PI_170_DATA 0x000000CE
 #define DDRSS_PI_171_DATA 0x00000176
 #define DDRSS_PI_172_DATA 0x00001448
 #define DDRSS_PI_173_DATA 0x00000176
@@ -658,14 +658,14 @@
 #define DDRSS_PI_185_DATA 0x0E040100
 #define DDRSS_PI_186_DATA 0x0808020E
 #define DDRSS_PI_187_DATA 0x00040402
-#define DDRSS_PI_188_DATA 0x000C8034
+#define DDRSS_PI_188_DATA 0x000D0035
 #define DDRSS_PI_189_DATA 0x00198041
 #define DDRSS_PI_190_DATA 0x00198041
 #define DDRSS_PI_191_DATA 0x01010101
-#define DDRSS_PI_192_DATA 0x0002000D
+#define DDRSS_PI_192_DATA 0x0002000E
 #define DDRSS_PI_193_DATA 0x0002014E
 #define DDRSS_PI_194_DATA 0x0100014E
-#define DDRSS_PI_195_DATA 0x000E000E
+#define DDRSS_PI_195_DATA 0x000F000F
 #define DDRSS_PI_196_DATA 0x014F0100
 #define DDRSS_PI_197_DATA 0x0100014F
 #define DDRSS_PI_198_DATA 0x014F014F
@@ -678,7 +678,7 @@
 #define DDRSS_PI_205_DATA 0x00C01000
 #define DDRSS_PI_206_DATA 0x00C01000
 #define DDRSS_PI_207_DATA 0x00021000
-#define DDRSS_PI_208_DATA 0x001C000D
+#define DDRSS_PI_208_DATA 0x001C000E
 #define DDRSS_PI_209_DATA 0x001C014E
 #define DDRSS_PI_210_DATA 0x0011014E
 #define DDRSS_PI_211_DATA 0x32000056
@@ -689,7 +689,7 @@
 #define DDRSS_PI_216_DATA 0x3212005A
 #define DDRSS_PI_217_DATA 0x09000301
 #define DDRSS_PI_218_DATA 0x04010504
-#define DDRSS_PI_219_DATA 0x0400062B
+#define DDRSS_PI_219_DATA 0x040006C9
 #define DDRSS_PI_220_DATA 0x0A032001
 #define DDRSS_PI_221_DATA 0x1C1F0B0A
 #define DDRSS_PI_222_DATA 0x00001D12
@@ -699,43 +699,43 @@
 #define DDRSS_PI_226_DATA 0x00001D12
 #define DDRSS_PI_227_DATA 0x3C00A488
 #define DDRSS_PI_228_DATA 0x13142005
-#define DDRSS_PI_229_DATA 0x0001760E
-#define DDRSS_PI_230_DATA 0x00000E9C
+#define DDRSS_PI_229_DATA 0x00019C0E
+#define DDRSS_PI_230_DATA 0x00001018
 #define DDRSS_PI_231_DATA 0x00002890
 #define DDRSS_PI_232_DATA 0x000195A0
 #define DDRSS_PI_233_DATA 0x00002890
 #define DDRSS_PI_234_DATA 0x000195A0
-#define DDRSS_PI_235_DATA 0x0180000F
+#define DDRSS_PI_235_DATA 0x01800010
 #define DDRSS_PI_236_DATA 0x03030180
-#define DDRSS_PI_237_DATA 0x00271003
-#define DDRSS_PI_238_DATA 0x000186A0
+#define DDRSS_PI_237_DATA 0x002AF803
+#define DDRSS_PI_238_DATA 0x0001ADAF
 #define DDRSS_PI_239_DATA 0x00000005
-#define DDRSS_PI_240_DATA 0x00000064
-#define DDRSS_PI_241_DATA 0x0000000F
+#define DDRSS_PI_240_DATA 0x0000006E
+#define DDRSS_PI_241_DATA 0x00000010
 #define DDRSS_PI_242_DATA 0x000411AB
-#define DDRSS_PI_243_DATA 0x000186A0
+#define DDRSS_PI_243_DATA 0x0001ADAF
 #define DDRSS_PI_244_DATA 0x00000005
 #define DDRSS_PI_245_DATA 0x00000A6B
 #define DDRSS_PI_246_DATA 0x00000180
 #define DDRSS_PI_247_DATA 0x000411AB
-#define DDRSS_PI_248_DATA 0x000186A0
+#define DDRSS_PI_248_DATA 0x0001ADAF
 #define DDRSS_PI_249_DATA 0x00000005
 #define DDRSS_PI_250_DATA 0x00000A6B
 #define DDRSS_PI_251_DATA 0x01000180
-#define DDRSS_PI_252_DATA 0x00320040
+#define DDRSS_PI_252_DATA 0x00370040
 #define DDRSS_PI_253_DATA 0x00010008
 #define DDRSS_PI_254_DATA 0x05360040
 #define DDRSS_PI_255_DATA 0x00010028
 #define DDRSS_PI_256_DATA 0x05360040
 #define DDRSS_PI_257_DATA 0x00000328
 #define DDRSS_PI_258_DATA 0x00430043
-#define DDRSS_PI_259_DATA 0x00040404
+#define DDRSS_PI_259_DATA 0x08040404
 #define DDRSS_PI_260_DATA 0x00000055
-#define DDRSS_PI_261_DATA 0x55003C5A
+#define DDRSS_PI_261_DATA 0x55083C5A
 #define DDRSS_PI_262_DATA 0x5A000000
-#define DDRSS_PI_263_DATA 0x0055003C
+#define DDRSS_PI_263_DATA 0x0055083C
 #define DDRSS_PI_264_DATA 0x3C5A0000
-#define DDRSS_PI_265_DATA 0x00005500
+#define DDRSS_PI_265_DATA 0x00005508
 #define DDRSS_PI_266_DATA 0x0C3C5A00
 #define DDRSS_PI_267_DATA 0x080F0E0D
 #define DDRSS_PI_268_DATA 0x000B0A09
@@ -879,7 +879,7 @@
 #define DDRSS_PHY_105_DATA 0x0F0C2701
 #define DDRSS_PHY_106_DATA 0x01000140
 #define DDRSS_PHY_107_DATA 0x04000420
-#define DDRSS_PHY_108_DATA 0x00000255
+#define DDRSS_PHY_108_DATA 0x00000198
 #define DDRSS_PHY_109_DATA 0x0A0000D0
 #define DDRSS_PHY_110_DATA 0x00030200
 #define DDRSS_PHY_111_DATA 0x02800000
@@ -1135,7 +1135,7 @@
 #define DDRSS_PHY_361_DATA 0x0F0C2701
 #define DDRSS_PHY_362_DATA 0x01000140
 #define DDRSS_PHY_363_DATA 0x04000420
-#define DDRSS_PHY_364_DATA 0x00000255
+#define DDRSS_PHY_364_DATA 0x00000198
 #define DDRSS_PHY_365_DATA 0x0A0000D0
 #define DDRSS_PHY_366_DATA 0x00030200
 #define DDRSS_PHY_367_DATA 0x02800000
@@ -1391,7 +1391,7 @@
 #define DDRSS_PHY_617_DATA 0x0F0C2701
 #define DDRSS_PHY_618_DATA 0x01000140
 #define DDRSS_PHY_619_DATA 0x04000420
-#define DDRSS_PHY_620_DATA 0x00000255
+#define DDRSS_PHY_620_DATA 0x00000198
 #define DDRSS_PHY_621_DATA 0x0A0000D0
 #define DDRSS_PHY_622_DATA 0x00030200
 #define DDRSS_PHY_623_DATA 0x02800000
@@ -1647,7 +1647,7 @@
 #define DDRSS_PHY_873_DATA 0x0F0C2701
 #define DDRSS_PHY_874_DATA 0x01000140
 #define DDRSS_PHY_875_DATA 0x04000420
-#define DDRSS_PHY_876_DATA 0x00000255
+#define DDRSS_PHY_876_DATA 0x00000198
 #define DDRSS_PHY_877_DATA 0x0A0000D0
 #define DDRSS_PHY_878_DATA 0x00030200
 #define DDRSS_PHY_879_DATA 0x02800000
@@ -2081,7 +2081,7 @@
 #define DDRSS_PHY_1307_DATA 0x01200F02
 #define DDRSS_PHY_1308_DATA 0x00194280
 #define DDRSS_PHY_1309_DATA 0x00000004
-#define DDRSS_PHY_1310_DATA 0x00050000
+#define DDRSS_PHY_1310_DATA 0x00052000
 #define DDRSS_PHY_1311_DATA 0x00000000
 #define DDRSS_PHY_1312_DATA 0x00000000
 #define DDRSS_PHY_1313_DATA 0x00000000
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 55ad615..e62f921 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -30,7 +30,8 @@
 		compatible = "ti,am654-rproc";
 		reg = <0x0 0x00a90000 0x0 0x10>;
 		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
+				<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
 		resets = <&k3_reset 202 0>;
 		clocks = <&k3_clks 61 1>;
 		assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
diff --git a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi
index ca05e06..5a6f9b1 100644
--- a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi
+++ b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi
@@ -1,11 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.5.0
- * This file was generated on 09/25/2020
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.1
+ * This file was generated on 07/17/2022
 */
 
 #define DDRSS_PLL_FHS_CNT 10
+#define DDRSS_PLL_FREQUENCY_0 27500000
 #define DDRSS_PLL_FREQUENCY_1 1066500000
 #define DDRSS_PLL_FREQUENCY_2 1066500000
 
@@ -16,10 +17,10 @@
 #define DDRSS_CTL_04_DATA 0x00000000
 #define DDRSS_CTL_05_DATA 0x00000000
 #define DDRSS_CTL_06_DATA 0x00000000
-#define DDRSS_CTL_07_DATA 0x00002710
-#define DDRSS_CTL_08_DATA 0x000186A0
+#define DDRSS_CTL_07_DATA 0x00002AF8
+#define DDRSS_CTL_08_DATA 0x0001ADAF
 #define DDRSS_CTL_09_DATA 0x00000005
-#define DDRSS_CTL_10_DATA 0x00000064
+#define DDRSS_CTL_10_DATA 0x0000006E
 #define DDRSS_CTL_11_DATA 0x000681C8
 #define DDRSS_CTL_12_DATA 0x004111C9
 #define DDRSS_CTL_13_DATA 0x00000005
@@ -32,11 +33,11 @@
 #define DDRSS_CTL_20_DATA 0x02011001
 #define DDRSS_CTL_21_DATA 0x02010000
 #define DDRSS_CTL_22_DATA 0x00020100
-#define DDRSS_CTL_23_DATA 0x0000000A
-#define DDRSS_CTL_24_DATA 0x00000019
+#define DDRSS_CTL_23_DATA 0x0000000B
+#define DDRSS_CTL_24_DATA 0x0000001C
 #define DDRSS_CTL_25_DATA 0x00000000
 #define DDRSS_CTL_26_DATA 0x00000000
-#define DDRSS_CTL_27_DATA 0x02020200
+#define DDRSS_CTL_27_DATA 0x03020200
 #define DDRSS_CTL_28_DATA 0x00005656
 #define DDRSS_CTL_29_DATA 0x00100000
 #define DDRSS_CTL_30_DATA 0x00000000
@@ -53,7 +54,7 @@
 #define DDRSS_CTL_41_DATA 0x1B60008B
 #define DDRSS_CTL_42_DATA 0x2000422B
 #define DDRSS_CTL_43_DATA 0x000A0A09
-#define DDRSS_CTL_44_DATA 0x040006DB
+#define DDRSS_CTL_44_DATA 0x0400078A
 #define DDRSS_CTL_45_DATA 0x1E161104
 #define DDRSS_CTL_46_DATA 0x10012458
 #define DDRSS_CTL_47_DATA 0x1E161110
@@ -61,7 +62,7 @@
 #define DDRSS_CTL_49_DATA 0x02030410
 #define DDRSS_CTL_50_DATA 0x2C040500
 #define DDRSS_CTL_51_DATA 0x082D2C2D
-#define DDRSS_CTL_52_DATA 0x14000D0A
+#define DDRSS_CTL_52_DATA 0x14000E0A
 #define DDRSS_CTL_53_DATA 0x04010A0A
 #define DDRSS_CTL_54_DATA 0x01010004
 #define DDRSS_CTL_55_DATA 0x04585808
@@ -69,15 +70,15 @@
 #define DDRSS_CTL_57_DATA 0x00003131
 #define DDRSS_CTL_58_DATA 0x00010100
 #define DDRSS_CTL_59_DATA 0x03010000
-#define DDRSS_CTL_60_DATA 0x00000E08
-#define DDRSS_CTL_61_DATA 0x000000BB
+#define DDRSS_CTL_60_DATA 0x00001008
+#define DDRSS_CTL_61_DATA 0x000000CE
 #define DDRSS_CTL_62_DATA 0x00000256
 #define DDRSS_CTL_63_DATA 0x00002073
 #define DDRSS_CTL_64_DATA 0x00000256
 #define DDRSS_CTL_65_DATA 0x00002073
 #define DDRSS_CTL_66_DATA 0x00000005
-#define DDRSS_CTL_67_DATA 0x00030000
-#define DDRSS_CTL_68_DATA 0x00950010
+#define DDRSS_CTL_67_DATA 0x00040000
+#define DDRSS_CTL_68_DATA 0x00950012
 #define DDRSS_CTL_69_DATA 0x00950408
 #define DDRSS_CTL_70_DATA 0x00400408
 #define DDRSS_CTL_71_DATA 0x00120103
@@ -88,7 +89,7 @@
 #define DDRSS_CTL_76_DATA 0x041E100B
 #define DDRSS_CTL_77_DATA 0x100B0401
 #define DDRSS_CTL_78_DATA 0x0001041E
-#define DDRSS_CTL_79_DATA 0x000F000F
+#define DDRSS_CTL_79_DATA 0x00100010
 #define DDRSS_CTL_80_DATA 0x02660266
 #define DDRSS_CTL_81_DATA 0x02660266
 #define DDRSS_CTL_82_DATA 0x03050505
@@ -111,13 +112,13 @@
 #define DDRSS_CTL_99_DATA 0x00000000
 #define DDRSS_CTL_100_DATA 0x00040005
 #define DDRSS_CTL_101_DATA 0x00000000
-#define DDRSS_CTL_102_DATA 0x00002EC0
-#define DDRSS_CTL_103_DATA 0x00002EC0
-#define DDRSS_CTL_104_DATA 0x00002EC0
-#define DDRSS_CTL_105_DATA 0x00002EC0
-#define DDRSS_CTL_106_DATA 0x00002EC0
+#define DDRSS_CTL_102_DATA 0x00003380
+#define DDRSS_CTL_103_DATA 0x00003380
+#define DDRSS_CTL_104_DATA 0x00003380
+#define DDRSS_CTL_105_DATA 0x00003380
+#define DDRSS_CTL_106_DATA 0x00003380
 #define DDRSS_CTL_107_DATA 0x00000000
-#define DDRSS_CTL_108_DATA 0x0000051D
+#define DDRSS_CTL_108_DATA 0x000005A2
 #define DDRSS_CTL_109_DATA 0x00081CC0
 #define DDRSS_CTL_110_DATA 0x00081CC0
 #define DDRSS_CTL_111_DATA 0x00081CC0
@@ -173,9 +174,9 @@
 #define DDRSS_CTL_161_DATA 0x00000000
 #define DDRSS_CTL_162_DATA 0x00000000
 #define DDRSS_CTL_163_DATA 0x00000000
-#define DDRSS_CTL_164_DATA 0x000A0000
-#define DDRSS_CTL_165_DATA 0x000D0005
-#define DDRSS_CTL_166_DATA 0x000D0404
+#define DDRSS_CTL_164_DATA 0x000B0000
+#define DDRSS_CTL_165_DATA 0x000E0006
+#define DDRSS_CTL_166_DATA 0x000E0404
 #define DDRSS_CTL_167_DATA 0x00D601AB
 #define DDRSS_CTL_168_DATA 0x10100216
 #define DDRSS_CTL_169_DATA 0x01AB0216
@@ -190,15 +191,15 @@
 #define DDRSS_CTL_178_DATA 0x56000000
 #define DDRSS_CTL_179_DATA 0x27270056
 #define DDRSS_CTL_180_DATA 0x0F0F0000
-#define DDRSS_CTL_181_DATA 0x00000000
-#define DDRSS_CTL_182_DATA 0x00840606
+#define DDRSS_CTL_181_DATA 0x16000000
+#define DDRSS_CTL_182_DATA 0x00841616
 #define DDRSS_CTL_183_DATA 0x3FF43FF4
 #define DDRSS_CTL_184_DATA 0x33333300
 #define DDRSS_CTL_185_DATA 0x00000000
 #define DDRSS_CTL_186_DATA 0x00565600
 #define DDRSS_CTL_187_DATA 0x00002727
 #define DDRSS_CTL_188_DATA 0x00000F0F
-#define DDRSS_CTL_189_DATA 0x06060000
+#define DDRSS_CTL_189_DATA 0x16161600
 #define DDRSS_CTL_190_DATA 0x00000020
 #define DDRSS_CTL_191_DATA 0x00000000
 #define DDRSS_CTL_192_DATA 0x00000001
@@ -238,17 +239,17 @@
 #define DDRSS_CTL_226_DATA 0x00000000
 #define DDRSS_CTL_227_DATA 0x15110000
 #define DDRSS_CTL_228_DATA 0x00040C18
-#define DDRSS_CTL_229_DATA 0x00000000
-#define DDRSS_CTL_230_DATA 0x00000000
+#define DDRSS_CTL_229_DATA 0xF000C000
+#define DDRSS_CTL_230_DATA 0x0000F000
 #define DDRSS_CTL_231_DATA 0x00000000
 #define DDRSS_CTL_232_DATA 0x00000000
-#define DDRSS_CTL_233_DATA 0x00000000
-#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_233_DATA 0xC0000000
+#define DDRSS_CTL_234_DATA 0xF000F000
 #define DDRSS_CTL_235_DATA 0x00000000
 #define DDRSS_CTL_236_DATA 0x00000000
 #define DDRSS_CTL_237_DATA 0x00000000
-#define DDRSS_CTL_238_DATA 0x00000000
-#define DDRSS_CTL_239_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0xF000C000
+#define DDRSS_CTL_239_DATA 0x0000F000
 #define DDRSS_CTL_240_DATA 0x00000000
 #define DDRSS_CTL_241_DATA 0x00000000
 #define DDRSS_CTL_242_DATA 0x00030000
@@ -267,7 +268,7 @@
 #define DDRSS_CTL_255_DATA 0x00000000
 #define DDRSS_CTL_256_DATA 0x00000000
 #define DDRSS_CTL_257_DATA 0x01000200
-#define DDRSS_CTL_258_DATA 0x00320040
+#define DDRSS_CTL_258_DATA 0x00370040
 #define DDRSS_CTL_259_DATA 0x00020008
 #define DDRSS_CTL_260_DATA 0x00400100
 #define DDRSS_CTL_261_DATA 0x00400855
@@ -276,7 +277,7 @@
 #define DDRSS_CTL_264_DATA 0x00000040
 #define DDRSS_CTL_265_DATA 0x006B0003
 #define DDRSS_CTL_266_DATA 0x0100006B
-#define DDRSS_CTL_267_DATA 0x00000000
+#define DDRSS_CTL_267_DATA 0x03030303
 #define DDRSS_CTL_268_DATA 0x01010000
 #define DDRSS_CTL_269_DATA 0x00000202
 #define DDRSS_CTL_270_DATA 0x00000FFF
@@ -398,13 +399,13 @@
 #define DDRSS_CTL_386_DATA 0x00000000
 #define DDRSS_CTL_387_DATA 0x3A3A1B00
 #define DDRSS_CTL_388_DATA 0x000A0000
-#define DDRSS_CTL_389_DATA 0x00000176
+#define DDRSS_CTL_389_DATA 0x0000019C
 #define DDRSS_CTL_390_DATA 0x00000200
 #define DDRSS_CTL_391_DATA 0x00000200
 #define DDRSS_CTL_392_DATA 0x00000200
 #define DDRSS_CTL_393_DATA 0x00000200
-#define DDRSS_CTL_394_DATA 0x00000462
-#define DDRSS_CTL_395_DATA 0x00000E9C
+#define DDRSS_CTL_394_DATA 0x000004D4
+#define DDRSS_CTL_395_DATA 0x00001018
 #define DDRSS_CTL_396_DATA 0x00000204
 #define DDRSS_CTL_397_DATA 0x000040E6
 #define DDRSS_CTL_398_DATA 0x00000200
@@ -431,7 +432,7 @@
 #define DDRSS_CTL_419_DATA 0x00000000
 #define DDRSS_CTL_420_DATA 0x00000000
 #define DDRSS_CTL_421_DATA 0x00030000
-#define DDRSS_CTL_422_DATA 0x0006001E
+#define DDRSS_CTL_422_DATA 0x0007001F
 #define DDRSS_CTL_423_DATA 0x001B0033
 #define DDRSS_CTL_424_DATA 0x001B0033
 #define DDRSS_CTL_425_DATA 0x00000000
@@ -632,14 +633,14 @@
 #define DDRSS_PI_160_DATA 0x00000000
 #define DDRSS_PI_161_DATA 0x00010000
 #define DDRSS_PI_162_DATA 0x00000000
-#define DDRSS_PI_163_DATA 0x2B2B0100
+#define DDRSS_PI_163_DATA 0x2B2B0200
 #define DDRSS_PI_164_DATA 0x00000034
 #define DDRSS_PI_165_DATA 0x00000064
 #define DDRSS_PI_166_DATA 0x00020064
 #define DDRSS_PI_167_DATA 0x02000200
 #define DDRSS_PI_168_DATA 0x48120C04
-#define DDRSS_PI_169_DATA 0x000E4812
-#define DDRSS_PI_170_DATA 0x000000BB
+#define DDRSS_PI_169_DATA 0x00104812
+#define DDRSS_PI_170_DATA 0x000000CE
 #define DDRSS_PI_171_DATA 0x00000256
 #define DDRSS_PI_172_DATA 0x00002073
 #define DDRSS_PI_173_DATA 0x00000256
@@ -657,14 +658,14 @@
 #define DDRSS_PI_185_DATA 0x15040000
 #define DDRSS_PI_186_DATA 0x0E0E0215
 #define DDRSS_PI_187_DATA 0x00040402
-#define DDRSS_PI_188_DATA 0x000C8034
+#define DDRSS_PI_188_DATA 0x000D0035
 #define DDRSS_PI_189_DATA 0x00218049
 #define DDRSS_PI_190_DATA 0x00218049
 #define DDRSS_PI_191_DATA 0x01010101
-#define DDRSS_PI_192_DATA 0x0004000D
+#define DDRSS_PI_192_DATA 0x0004000E
 #define DDRSS_PI_193_DATA 0x00040216
 #define DDRSS_PI_194_DATA 0x01000216
-#define DDRSS_PI_195_DATA 0x000E000E
+#define DDRSS_PI_195_DATA 0x000F000F
 #define DDRSS_PI_196_DATA 0x02170100
 #define DDRSS_PI_197_DATA 0x01000217
 #define DDRSS_PI_198_DATA 0x02170217
@@ -677,7 +678,7 @@
 #define DDRSS_PI_205_DATA 0x00C01000
 #define DDRSS_PI_206_DATA 0x00C01000
 #define DDRSS_PI_207_DATA 0x00021000
-#define DDRSS_PI_208_DATA 0x0024000D
+#define DDRSS_PI_208_DATA 0x0024000E
 #define DDRSS_PI_209_DATA 0x00240216
 #define DDRSS_PI_210_DATA 0x00110216
 #define DDRSS_PI_211_DATA 0x32000056
@@ -688,7 +689,7 @@
 #define DDRSS_PI_216_DATA 0x3212005B
 #define DDRSS_PI_217_DATA 0x09000301
 #define DDRSS_PI_218_DATA 0x04010504
-#define DDRSS_PI_219_DATA 0x0400062B
+#define DDRSS_PI_219_DATA 0x040006C9
 #define DDRSS_PI_220_DATA 0x0A032001
 #define DDRSS_PI_221_DATA 0x2C31110A
 #define DDRSS_PI_222_DATA 0x00002D1C
@@ -698,43 +699,43 @@
 #define DDRSS_PI_226_DATA 0x00002D1C
 #define DDRSS_PI_227_DATA 0x6001071C
 #define DDRSS_PI_228_DATA 0x1E202008
-#define DDRSS_PI_229_DATA 0x00017616
-#define DDRSS_PI_230_DATA 0x00000E9C
+#define DDRSS_PI_229_DATA 0x00019C16
+#define DDRSS_PI_230_DATA 0x00001018
 #define DDRSS_PI_231_DATA 0x000040E6
 #define DDRSS_PI_232_DATA 0x000288FC
 #define DDRSS_PI_233_DATA 0x000040E6
 #define DDRSS_PI_234_DATA 0x000288FC
-#define DDRSS_PI_235_DATA 0x0266000F
+#define DDRSS_PI_235_DATA 0x02660010
 #define DDRSS_PI_236_DATA 0x03030266
-#define DDRSS_PI_237_DATA 0x00271003
-#define DDRSS_PI_238_DATA 0x000186A0
+#define DDRSS_PI_237_DATA 0x002AF803
+#define DDRSS_PI_238_DATA 0x0001ADAF
 #define DDRSS_PI_239_DATA 0x00000005
-#define DDRSS_PI_240_DATA 0x00000064
-#define DDRSS_PI_241_DATA 0x0000000F
+#define DDRSS_PI_240_DATA 0x0000006E
+#define DDRSS_PI_241_DATA 0x00000010
 #define DDRSS_PI_242_DATA 0x000681C8
-#define DDRSS_PI_243_DATA 0x000186A0
+#define DDRSS_PI_243_DATA 0x0001ADAF
 #define DDRSS_PI_244_DATA 0x00000005
 #define DDRSS_PI_245_DATA 0x000010A9
 #define DDRSS_PI_246_DATA 0x00000266
 #define DDRSS_PI_247_DATA 0x000681C8
-#define DDRSS_PI_248_DATA 0x000186A0
+#define DDRSS_PI_248_DATA 0x0001ADAF
 #define DDRSS_PI_249_DATA 0x00000005
 #define DDRSS_PI_250_DATA 0x000010A9
 #define DDRSS_PI_251_DATA 0x01000266
-#define DDRSS_PI_252_DATA 0x00320040
+#define DDRSS_PI_252_DATA 0x00370040
 #define DDRSS_PI_253_DATA 0x00010008
 #define DDRSS_PI_254_DATA 0x08550040
 #define DDRSS_PI_255_DATA 0x00010040
 #define DDRSS_PI_256_DATA 0x08550040
 #define DDRSS_PI_257_DATA 0x00000340
 #define DDRSS_PI_258_DATA 0x006B006B
-#define DDRSS_PI_259_DATA 0x00040404
+#define DDRSS_PI_259_DATA 0x08040404
 #define DDRSS_PI_260_DATA 0x00000055
-#define DDRSS_PI_261_DATA 0x55003C5A
+#define DDRSS_PI_261_DATA 0x55083C5A
 #define DDRSS_PI_262_DATA 0x5A000000
-#define DDRSS_PI_263_DATA 0x0055003C
+#define DDRSS_PI_263_DATA 0x0055083C
 #define DDRSS_PI_264_DATA 0x3C5A0000
-#define DDRSS_PI_265_DATA 0x00005500
+#define DDRSS_PI_265_DATA 0x00005508
 #define DDRSS_PI_266_DATA 0x0C3C5A00
 #define DDRSS_PI_267_DATA 0x080F0E0D
 #define DDRSS_PI_268_DATA 0x000B0A09
@@ -802,8 +803,8 @@
 #define DDRSS_PHY_29_DATA 0x00000808
 #define DDRSS_PHY_30_DATA 0x0F000000
 #define DDRSS_PHY_31_DATA 0x00000F0F
-#define DDRSS_PHY_32_DATA 0x10200000
-#define DDRSS_PHY_33_DATA 0x0C002007
+#define DDRSS_PHY_32_DATA 0x10400000
+#define DDRSS_PHY_33_DATA 0x0C002006
 #define DDRSS_PHY_34_DATA 0x00000000
 #define DDRSS_PHY_35_DATA 0x00000000
 #define DDRSS_PHY_36_DATA 0x55555555
@@ -878,7 +879,7 @@
 #define DDRSS_PHY_105_DATA 0x0F0C3701
 #define DDRSS_PHY_106_DATA 0x01000140
 #define DDRSS_PHY_107_DATA 0x0C000420
-#define DDRSS_PHY_108_DATA 0x00000322
+#define DDRSS_PHY_108_DATA 0x00000198
 #define DDRSS_PHY_109_DATA 0x0A0000D0
 #define DDRSS_PHY_110_DATA 0x00030200
 #define DDRSS_PHY_111_DATA 0x02800000
@@ -1058,8 +1059,8 @@
 #define DDRSS_PHY_285_DATA 0x00000808
 #define DDRSS_PHY_286_DATA 0x0F000000
 #define DDRSS_PHY_287_DATA 0x00000F0F
-#define DDRSS_PHY_288_DATA 0x10200000
-#define DDRSS_PHY_289_DATA 0x0C002007
+#define DDRSS_PHY_288_DATA 0x10400000
+#define DDRSS_PHY_289_DATA 0x0C002006
 #define DDRSS_PHY_290_DATA 0x00000000
 #define DDRSS_PHY_291_DATA 0x00000000
 #define DDRSS_PHY_292_DATA 0x55555555
@@ -1134,7 +1135,7 @@
 #define DDRSS_PHY_361_DATA 0x0F0C3701
 #define DDRSS_PHY_362_DATA 0x01000140
 #define DDRSS_PHY_363_DATA 0x0C000420
-#define DDRSS_PHY_364_DATA 0x00000322
+#define DDRSS_PHY_364_DATA 0x00000198
 #define DDRSS_PHY_365_DATA 0x0A0000D0
 #define DDRSS_PHY_366_DATA 0x00030200
 #define DDRSS_PHY_367_DATA 0x02800000
@@ -1314,8 +1315,8 @@
 #define DDRSS_PHY_541_DATA 0x00000808
 #define DDRSS_PHY_542_DATA 0x0F000000
 #define DDRSS_PHY_543_DATA 0x00000F0F
-#define DDRSS_PHY_544_DATA 0x10200000
-#define DDRSS_PHY_545_DATA 0x0C002007
+#define DDRSS_PHY_544_DATA 0x10400000
+#define DDRSS_PHY_545_DATA 0x0C002006
 #define DDRSS_PHY_546_DATA 0x00000000
 #define DDRSS_PHY_547_DATA 0x00000000
 #define DDRSS_PHY_548_DATA 0x55555555
@@ -1390,7 +1391,7 @@
 #define DDRSS_PHY_617_DATA 0x0F0C3701
 #define DDRSS_PHY_618_DATA 0x01000140
 #define DDRSS_PHY_619_DATA 0x0C000420
-#define DDRSS_PHY_620_DATA 0x00000322
+#define DDRSS_PHY_620_DATA 0x00000198
 #define DDRSS_PHY_621_DATA 0x0A0000D0
 #define DDRSS_PHY_622_DATA 0x00030200
 #define DDRSS_PHY_623_DATA 0x02800000
@@ -1570,8 +1571,8 @@
 #define DDRSS_PHY_797_DATA 0x00000808
 #define DDRSS_PHY_798_DATA 0x0F000000
 #define DDRSS_PHY_799_DATA 0x00000F0F
-#define DDRSS_PHY_800_DATA 0x10200000
-#define DDRSS_PHY_801_DATA 0x0C002007
+#define DDRSS_PHY_800_DATA 0x10400000
+#define DDRSS_PHY_801_DATA 0x0C002006
 #define DDRSS_PHY_802_DATA 0x00000000
 #define DDRSS_PHY_803_DATA 0x00000000
 #define DDRSS_PHY_804_DATA 0x55555555
@@ -1646,7 +1647,7 @@
 #define DDRSS_PHY_873_DATA 0x0F0C3701
 #define DDRSS_PHY_874_DATA 0x01000140
 #define DDRSS_PHY_875_DATA 0x0C000420
-#define DDRSS_PHY_876_DATA 0x00000322
+#define DDRSS_PHY_876_DATA 0x00000198
 #define DDRSS_PHY_877_DATA 0x0A0000D0
 #define DDRSS_PHY_878_DATA 0x00030200
 #define DDRSS_PHY_879_DATA 0x02800000
@@ -2080,7 +2081,7 @@
 #define DDRSS_PHY_1307_DATA 0x01200F02
 #define DDRSS_PHY_1308_DATA 0x00194280
 #define DDRSS_PHY_1309_DATA 0x00000004
-#define DDRSS_PHY_1310_DATA 0x00050000
+#define DDRSS_PHY_1310_DATA 0x00052000
 #define DDRSS_PHY_1311_DATA 0x00000000
 #define DDRSS_PHY_1312_DATA 0x00000000
 #define DDRSS_PHY_1313_DATA 0x00000000
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index e9e5053..1b40cf2 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -25,7 +25,8 @@
 		compatible = "ti,am654-rproc";
 		reg = <0x0 0x00a90000 0x0 0x10>;
 		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
+				<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
 		resets = <&k3_reset 202 0>;
 		clocks = <&k3_clks 61 1>;
 		assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
diff --git a/arch/arm/dts/k3-j721e-r5-sk.dts b/arch/arm/dts/k3-j721e-r5-sk.dts
index 8d6eaa4..6986292 100644
--- a/arch/arm/dts/k3-j721e-r5-sk.dts
+++ b/arch/arm/dts/k3-j721e-r5-sk.dts
@@ -159,7 +159,8 @@
 		compatible = "ti,am654-rproc";
 		reg = <0x0 0x00a90000 0x0 0x10>;
 		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
+				<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
 		resets = <&k3_reset 202 0>;
 		clocks = <&k3_clks 61 1>;
 		assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
index bc61702..e02b334 100644
--- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
@@ -30,7 +30,8 @@
 		compatible = "ti,am654-rproc";
 		reg = <0x0 0x00a90000 0x0 0x10>;
 		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
+				<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
 		resets = <&k3_reset 202 0>;
 		clocks = <&k3_clks 61 1>;
 		assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;
diff --git a/arch/arm/dts/keystone-clocks.dtsi b/arch/arm/dts/keystone-clocks.dtsi
index 0c334b2..457515b 100644
--- a/arch/arm/dts/keystone-clocks.dtsi
+++ b/arch/arm/dts/keystone-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Device Tree Source for Keystone 2 clock tree
  *
- * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 clocks {
@@ -51,7 +48,7 @@
 		clock-output-names = "gemtraceclk";
 	};
 
-	chipstmxptclk: chipstmxptclk {
+	chipstmxptclk: chipstmxptclk@2310164 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,pll-divider-clock";
 		clocks = <&mainmuxclk>;
@@ -160,7 +157,7 @@
 		clock-output-names = "chipclk1rstiso112";
 	};
 
-	clkmodrst0: clkmodrst0 {
+	clkmodrst0: clkmodrst0@2350000 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk16>;
@@ -171,7 +168,7 @@
 	};
 
 
-	clkusb: clkusb {
+	clkusb: clkusb@2350008 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk16>;
@@ -181,7 +178,7 @@
 		domain-id = <0>;
 	};
 
-	clkaemifspi: clkaemifspi {
+	clkaemifspi: clkaemifspi@235000c {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk16>;
@@ -192,7 +189,7 @@
 	};
 
 
-	clkdebugsstrc: clkdebugsstrc {
+	clkdebugsstrc: clkdebugsstrc@2350014 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -202,7 +199,7 @@
 		domain-id = <1>;
 	};
 
-	clktetbtrc: clktetbtrc {
+	clktetbtrc: clktetbtrc@2350018 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -212,7 +209,7 @@
 		domain-id = <1>;
 	};
 
-	clkpa: clkpa {
+	clkpa: clkpa@235001c {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&paclk13>;
@@ -222,7 +219,7 @@
 		domain-id = <2>;
 	};
 
-	clkcpgmac: clkcpgmac {
+	clkcpgmac: clkcpgmac@2350020 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&clkpa>;
@@ -232,7 +229,7 @@
 		domain-id = <2>;
 	};
 
-	clksa: clksa {
+	clksa: clksa@2350024 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&clkpa>;
@@ -242,7 +239,7 @@
 		domain-id = <2>;
 	};
 
-	clkpcie: clkpcie {
+	clkpcie: clkpcie@2350028 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk12>;
@@ -252,7 +249,7 @@
 		domain-id = <3>;
 	};
 
-	clksr: clksr {
+	clksr: clksr@2350034 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk1rstiso112>;
@@ -262,7 +259,7 @@
 		domain-id = <6>;
 	};
 
-	clkgem0: clkgem0 {
+	clkgem0: clkgem0@235003c {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk1>;
@@ -272,7 +269,7 @@
 		domain-id = <8>;
 	};
 
-	clkddr30: clkddr30 {
+	clkddr30: clkddr30@235005c {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk12>;
@@ -282,7 +279,7 @@
 		domain-id = <16>;
 	};
 
-	clkwdtimer0: clkwdtimer0 {
+	clkwdtimer0: clkwdtimer0@2350000 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&clkmodrst0>;
@@ -292,7 +289,7 @@
 		domain-id = <0>;
 	};
 
-	clkwdtimer1: clkwdtimer1 {
+	clkwdtimer1: clkwdtimer1@2350000 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&clkmodrst0>;
@@ -302,7 +299,7 @@
 		domain-id = <0>;
 	};
 
-	clkwdtimer2: clkwdtimer2 {
+	clkwdtimer2: clkwdtimer2@2350000 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&clkmodrst0>;
@@ -312,7 +309,7 @@
 		domain-id = <0>;
 	};
 
-	clkwdtimer3: clkwdtimer3 {
+	clkwdtimer3: clkwdtimer3@2350000 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&clkmodrst0>;
@@ -322,7 +319,7 @@
 		domain-id = <0>;
 	};
 
-	clktimer15: clktimer15 {
+	clktimer15: clktimer15@2350000 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&clkmodrst0>;
@@ -332,7 +329,7 @@
 		domain-id = <0>;
 	};
 
-	clkuart0: clkuart0 {
+	clkuart0: clkuart0@2350000 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&clkmodrst0>;
@@ -342,7 +339,7 @@
 		domain-id = <0>;
 	};
 
-	clkuart1: clkuart1 {
+	clkuart1: clkuart1@2350000 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&clkmodrst0>;
@@ -352,7 +349,7 @@
 		domain-id = <0>;
 	};
 
-	clkaemif: clkaemif {
+	clkaemif: clkaemif@2350000 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&clkaemifspi>;
@@ -362,7 +359,7 @@
 		domain-id = <0>;
 	};
 
-	clkusim: clkusim {
+	clkusim: clkusim@2350000 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&clkmodrst0>;
@@ -372,7 +369,7 @@
 		domain-id = <0>;
 	};
 
-	clki2c: clki2c {
+	clki2c: clki2c@2350000 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&clkmodrst0>;
@@ -382,7 +379,7 @@
 		domain-id = <0>;
 	};
 
-	clkspi: clkspi {
+	clkspi: clkspi@2350000 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&clkaemifspi>;
@@ -392,7 +389,7 @@
 		domain-id = <0>;
 	};
 
-	clkgpio: clkgpio {
+	clkgpio: clkgpio@2350000 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&clkmodrst0>;
@@ -402,7 +399,7 @@
 		domain-id = <0>;
 	};
 
-	clkkeymgr: clkkeymgr {
+	clkkeymgr: clkkeymgr@2350000 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&clkmodrst0>;
diff --git a/arch/arm/dts/keystone-k2e-clocks.dtsi b/arch/arm/dts/keystone-k2e-clocks.dtsi
index d56d68f..f759215 100644
--- a/arch/arm/dts/keystone-k2e-clocks.dtsi
+++ b/arch/arm/dts/keystone-k2e-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2014 Texas Instruments, Inc.
- *
  * Keystone 2 Edison SoC specific device tree
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 clocks {
@@ -35,7 +32,7 @@
 		reg-names = "control";
 	};
 
-	clkusb1: clkusb1 {
+	clkusb1: clkusb1@2350004 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk16>;
@@ -45,7 +42,7 @@
 		domain-id = <0>;
 	};
 
-	clkhyperlink0: clkhyperlink0 {
+	clkhyperlink0: clkhyperlink0@2350030 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk12>;
@@ -55,7 +52,7 @@
 		domain-id = <5>;
 	};
 
-	clkpcie1: clkpcie1 {
+	clkpcie1: clkpcie1@235006c {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk12>;
@@ -65,7 +62,7 @@
 		domain-id = <18>;
 	};
 
-	clkxge: clkxge {
+	clkxge: clkxge@23500c8 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
diff --git a/arch/arm/dts/keystone-k2e-evm.dts b/arch/arm/dts/keystone-k2e-evm.dts
index bb197e1..ed76e56 100644
--- a/arch/arm/dts/keystone-k2e-evm.dts
+++ b/arch/arm/dts/keystone-k2e-evm.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2013-2014 Texas Instruments, Inc.
- *
  * Keystone 2 Edison EVM device tree
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 /dts-v1/;
 
@@ -13,7 +10,7 @@
 #include "keystone-k2e.dtsi"
 
 / {
-	compatible =  "ti,k2e-evm","ti,keystone";
+	compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone";
 	model = "Texas Instruments Keystone 2 Edison EVM";
 
 	soc {
@@ -120,7 +117,7 @@
 
 &spi0 {
 	status = "okay";
-	nor_flash: n25q128a11@0 {
+	nor_flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "Micron,n25q128a11", "jedec,spi-nor";
diff --git a/arch/arm/dts/keystone-k2e-netcp.dtsi b/arch/arm/dts/keystone-k2e-netcp.dtsi
index b13b3c9..45ebb0a 100644
--- a/arch/arm/dts/keystone-k2e-netcp.dtsi
+++ b/arch/arm/dts/keystone-k2e-netcp.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Device Tree Source for Keystone 2 Edison Netcp driver
  *
- * Copyright 2015 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 qmss: qmss@2a40000 {
@@ -15,9 +12,9 @@
 	#size-cells = <1>;
 	clocks = <&chipclk13>;
 	ranges;
-	queue-range	= <0 0x2000>;
-	linkram0	= <0x100000 0x4000>;
-	linkram1	= <0 0x10000>;
+	queue-range = <0 0x2000>;
+	linkram0 = <0x100000 0x4000>;
+	linkram1 = <0 0x10000>;
 
 	qmgrs {
 		#address-cells = <1>;
@@ -138,40 +135,40 @@
 			interfaces {
 				gbe0: interface-0 {
 					slave-port = <0>;
-					link-interface	= <1>;
-					phy-handle	= <&ethphy0>;
+					link-interface = <1>;
+					phy-handle = <&ethphy0>;
 				};
 				gbe1: interface-1 {
 					slave-port = <1>;
-					link-interface	= <1>;
-					phy-handle	= <&ethphy1>;
+					link-interface = <1>;
+					phy-handle = <&ethphy1>;
 				};
 			};
 
 			secondary-slave-ports {
 				port-2 {
 					slave-port = <2>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 				port-3 {
 					slave-port = <3>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 				port-4 {
 					slave-port = <4>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 				port-5 {
 					slave-port = <5>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 				port-6 {
 					slave-port = <6>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 				port-7 {
 					slave-port = <7>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 			};
 		};
diff --git a/arch/arm/dts/keystone-k2e.dtsi b/arch/arm/dts/keystone-k2e.dtsi
index b5d9061..496bb31 100644
--- a/arch/arm/dts/keystone-k2e.dtsi
+++ b/arch/arm/dts/keystone-k2e.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2013-2014 Texas Instruments, Inc.
- *
  * Keystone 2 Edison soc device tree
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 / {
@@ -45,7 +42,7 @@
 
 		usb: usb@2680000 {
 			interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
-			dwc3@2690000 {
+			usb@2690000 {
 				interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
 			};
 		};
@@ -71,7 +68,7 @@
 			dma-ranges;
 			status = "disabled";
 
-			dwc3@25010000 {
+			usb@25010000 {
 				compatible = "synopsys,dwc3";
 				reg = <0x25010000 0x70000>;
 				interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
@@ -92,7 +89,7 @@
 			clock-names = "pcie";
 			#address-cells = <3>;
 			#size-cells = <2>;
-			reg =  <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
+			reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
 			ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
 				0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
 
@@ -133,14 +130,14 @@
 		};
 
 		mdio: mdio@24200f00 {
-			compatible	= "ti,keystone_mdio", "ti,davinci_mdio";
+			compatible = "ti,keystone_mdio", "ti,davinci_mdio";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x24200f00 0x100>;
 			status = "disabled";
 			clocks = <&clkcpgmac>;
 			clock-names = "fck";
-			bus_freq	= <2500000>;
+			bus_freq = <2500000>;
 		};
 		/include/ "keystone-k2e-netcp.dtsi"
 	};
diff --git a/arch/arm/dts/keystone-k2g-evm.dts b/arch/arm/dts/keystone-k2g-evm.dts
index b5b511c..6376c62 100644
--- a/arch/arm/dts/keystone-k2g-evm.dts
+++ b/arch/arm/dts/keystone-k2g-evm.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2014 Texas Instruments, Inc.
- *
  * Device Tree Source for K2G EVM
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 /dts-v1/;
 
@@ -93,8 +90,8 @@
 &qspi {
 	status = "okay";
 
-	flash0: m25p80@0 {
-		compatible = "s25fl512s","jedec,spi-nor";
+	flash0: flash@0 {
+		compatible = "s25fl512s", "jedec,spi-nor";
 		reg = <0>;
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <4>;
diff --git a/arch/arm/dts/keystone-k2g-ice.dts b/arch/arm/dts/keystone-k2g-ice.dts
index ecca2df..cbdb6bf 100644
--- a/arch/arm/dts/keystone-k2g-ice.dts
+++ b/arch/arm/dts/keystone-k2g-ice.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Device Tree Source for K2G Industrial Communication Engine EVM
  *
@@ -38,7 +38,7 @@
 &qspi {
 	status = "okay";
 
-	flash0: m25p80@0 {
+	flash0: flash@0 {
 		compatible = "s25fl256s1", "jedec,spi-nor";
 		reg = <0>;
 		spi-tx-bus-width = <1>;
diff --git a/arch/arm/dts/keystone-k2g-netcp.dtsi b/arch/arm/dts/keystone-k2g-netcp.dtsi
index d76f2a1..136cd20 100644
--- a/arch/arm/dts/keystone-k2g-netcp.dtsi
+++ b/arch/arm/dts/keystone-k2g-netcp.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Device Tree Source for K2G Netcp driver
  *
- * Copyright 2015 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 qmss: qmss@4020000 {
@@ -17,8 +14,8 @@
 	/* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; */
 	clock-names = "nss_vclk";
 	ranges;
-	queue-range	= <0 0x80>;
-	linkram0	= <0x4020000 0x7ff>;
+	queue-range = <0 0x80>;
+	linkram0 = <0x4020000 0x7ff>;
 
 	qmgrs {
 		#address-cells = <1>;
@@ -80,12 +77,12 @@
 
 	dma_gbe: dma_gbe@0 {
 		reg = <0x4010000 0x100>,
-			  <0x4011000 0x2a0>, /* 21 Tx channels */
-			  <0x4012000 0x400>, /* 32 Rx channels */
-			  <0x4010100 0x80>,
-			  <0x4013000 0x400>; /* 32 Rx flows */
+		      <0x4011000 0x2a0>, /* 21 Tx channels */
+		      <0x4012000 0x400>, /* 32 Rx channels */
+		      <0x4010100 0x80>,
+		      <0x4013000 0x400>; /* 32 Rx flows */
 		reg-names = "global", "txchan", "rxchan",
-				"txsched", "rxflow";
+			    "txsched", "rxflow";
 	};
 
 };
@@ -99,9 +96,9 @@
 	reg = <0x2620110 0x8>;
 	reg-names = "efuse";
 	compatible = "ti,netcp-1.0";
-	status = "disabled";
 	#address-cells = <1>;
 	#size-cells = <1>;
+	status = "disabled";
 	/* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
 	/* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */
 	clock-names = "ethss_clk";
@@ -130,7 +127,7 @@
 			interfaces {
 				gbe0: interface-0 {
 					slave-port = <0>;
-					link-interface	= <5>;
+					link-interface = <5>;
 				};
 			};
 		};
diff --git a/arch/arm/dts/keystone-k2g.dtsi b/arch/arm/dts/keystone-k2g.dtsi
index ede7118..f12af43 100644
--- a/arch/arm/dts/keystone-k2g.dtsi
+++ b/arch/arm/dts/keystone-k2g.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2014 Texas Instruments, Inc.
- *
  * Device Tree Source for K2G SOC
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -43,7 +40,7 @@
 		};
 	};
 
-	gic: interrupt-controller {
+	gic: interrupt-controller@2561000 {
 		compatible = "arm,cortex-a15-gic";
 		#interrupt-cells = <3>;
 		interrupt-controller;
diff --git a/arch/arm/dts/keystone-k2hk-clocks.dtsi b/arch/arm/dts/keystone-k2hk-clocks.dtsi
index af9b719..4ba6912 100644
--- a/arch/arm/dts/keystone-k2hk-clocks.dtsi
+++ b/arch/arm/dts/keystone-k2hk-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2013-2014 Texas Instruments, Inc.
- *
  * Keystone 2 Kepler/Hawking SoC clock nodes
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 clocks {
@@ -53,7 +50,7 @@
 		reg-names = "control";
 	};
 
-	clktsip: clktsip {
+	clktsip: clktsip@2350000 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk16>;
@@ -63,7 +60,7 @@
 		domain-id = <0>;
 	};
 
-	clksrio: clksrio {
+	clksrio: clksrio@235002c {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk1rstiso13>;
@@ -73,7 +70,7 @@
 		domain-id = <4>;
 	};
 
-	clkhyperlink0: clkhyperlink0 {
+	clkhyperlink0: clkhyperlink0@2350030 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk12>;
@@ -83,7 +80,7 @@
 		domain-id = <5>;
 	};
 
-	clkgem1: clkgem1 {
+	clkgem1: clkgem1@2350040 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk1>;
@@ -93,7 +90,7 @@
 		domain-id = <9>;
 	};
 
-	clkgem2: clkgem2 {
+	clkgem2: clkgem2@2350044 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk1>;
@@ -103,7 +100,7 @@
 		domain-id = <10>;
 	};
 
-	clkgem3: clkgem3 {
+	clkgem3: clkgem3@2350048 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk1>;
@@ -113,7 +110,7 @@
 		domain-id = <11>;
 	};
 
-	clkgem4: clkgem4 {
+	clkgem4: clkgem4@235004c {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk1>;
@@ -123,7 +120,7 @@
 		domain-id = <12>;
 	};
 
-	clkgem5: clkgem5 {
+	clkgem5: clkgem5@2350050 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk1>;
@@ -133,7 +130,7 @@
 		domain-id = <13>;
 	};
 
-	clkgem6: clkgem6 {
+	clkgem6: clkgem6@2350054 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk1>;
@@ -143,7 +140,7 @@
 		domain-id = <14>;
 	};
 
-	clkgem7: clkgem7 {
+	clkgem7: clkgem7@2350058 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk1>;
@@ -153,7 +150,7 @@
 		domain-id = <15>;
 	};
 
-	clkddr31: clkddr31 {
+	clkddr31: clkddr31@2350060 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -163,7 +160,7 @@
 		domain-id = <16>;
 	};
 
-	clktac: clktac {
+	clktac: clktac@2350064 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -173,7 +170,7 @@
 		domain-id = <17>;
 	};
 
-	clkrac01: clkrac01 {
+	clkrac01: clkrac01@2350068 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -183,7 +180,7 @@
 		domain-id = <17>;
 	};
 
-	clkrac23: clkrac23 {
+	clkrac23: clkrac23@235006c {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -193,7 +190,7 @@
 		domain-id = <18>;
 	};
 
-	clkfftc0: clkfftc0 {
+	clkfftc0: clkfftc0@2350070 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -203,7 +200,7 @@
 		domain-id = <19>;
 	};
 
-	clkfftc1: clkfftc1 {
+	clkfftc1: clkfftc1@2350074 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -213,7 +210,7 @@
 		domain-id = <19>;
 	};
 
-	clkfftc2: clkfftc2 {
+	clkfftc2: clkfftc2@2350078 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -223,7 +220,7 @@
 		domain-id = <20>;
 	};
 
-	clkfftc3: clkfftc3 {
+	clkfftc3: clkfftc3@235007c {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -233,7 +230,7 @@
 		domain-id = <20>;
 	};
 
-	clkfftc4: clkfftc4 {
+	clkfftc4: clkfftc4@2350080 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -243,7 +240,7 @@
 		domain-id = <20>;
 	};
 
-	clkfftc5: clkfftc5 {
+	clkfftc5: clkfftc5@2350084 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -253,7 +250,7 @@
 		domain-id = <20>;
 	};
 
-	clkaif: clkaif {
+	clkaif: clkaif@2350088 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -263,7 +260,7 @@
 		domain-id = <21>;
 	};
 
-	clktcp3d0: clktcp3d0 {
+	clktcp3d0: clktcp3d0@235008c {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -273,7 +270,7 @@
 		domain-id = <22>;
 	};
 
-	clktcp3d1: clktcp3d1 {
+	clktcp3d1: clktcp3d1@2350090 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -283,7 +280,7 @@
 		domain-id = <22>;
 	};
 
-	clktcp3d2: clktcp3d2 {
+	clktcp3d2: clktcp3d2@2350094 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -293,7 +290,7 @@
 		domain-id = <23>;
 	};
 
-	clktcp3d3: clktcp3d3 {
+	clktcp3d3: clktcp3d3@2350098 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -303,7 +300,7 @@
 		domain-id = <23>;
 	};
 
-	clkvcp0: clkvcp0 {
+	clkvcp0: clkvcp0@235009c {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -313,7 +310,7 @@
 		domain-id = <24>;
 	};
 
-	clkvcp1: clkvcp1 {
+	clkvcp1: clkvcp1@23500a0 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -323,7 +320,7 @@
 		domain-id = <24>;
 	};
 
-	clkvcp2: clkvcp2 {
+	clkvcp2: clkvcp2@23500a4 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -333,7 +330,7 @@
 		domain-id = <24>;
 	};
 
-	clkvcp3: clkvcp3 {
+	clkvcp3: clkvcp3@23500a8 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -343,7 +340,7 @@
 		domain-id = <24>;
 	};
 
-	clkvcp4: clkvcp4 {
+	clkvcp4: clkvcp4@23500ac {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -353,7 +350,7 @@
 		domain-id = <25>;
 	};
 
-	clkvcp5: clkvcp5 {
+	clkvcp5: clkvcp5@23500b0 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -363,7 +360,7 @@
 		domain-id = <25>;
 	};
 
-	clkvcp6: clkvcp6 {
+	clkvcp6: clkvcp6@23500b4 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -373,7 +370,7 @@
 		domain-id = <25>;
 	};
 
-	clkvcp7: clkvcp7 {
+	clkvcp7: clkvcp7@23500b8 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -383,7 +380,7 @@
 		domain-id = <25>;
 	};
 
-	clkbcp: clkbcp {
+	clkbcp: clkbcp@23500bc {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -393,7 +390,7 @@
 		domain-id = <26>;
 	};
 
-	clkdxb: clkdxb {
+	clkdxb: clkdxb@23500c0 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -403,7 +400,7 @@
 		domain-id = <27>;
 	};
 
-	clkhyperlink1: clkhyperlink1 {
+	clkhyperlink1: clkhyperlink1@23500c4 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk12>;
@@ -413,7 +410,7 @@
 		domain-id = <28>;
 	};
 
-	clkxge: clkxge {
+	clkxge: clkxge@23500c8 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
diff --git a/arch/arm/dts/keystone-k2hk-evm.dts b/arch/arm/dts/keystone-k2hk-evm.dts
index acfcaff..ea53f3f 100644
--- a/arch/arm/dts/keystone-k2hk-evm.dts
+++ b/arch/arm/dts/keystone-k2hk-evm.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2013-2014 Texas Instruments, Inc.
- *
  * Keystone 2 Kepler/Hawking EVM device tree
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 /dts-v1/;
 
@@ -57,22 +54,22 @@
 
 	leds {
 		compatible = "gpio-leds";
-		debug1_1 {
+		led-debug-1-1 {
 			label = "keystone:green:debug1";
 			gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */
 		};
 
-		debug1_2 {
+		led-debug-1-2 {
 			label = "keystone:red:debug1";
 			gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */
 		};
 
-		debug2 {
+		led-debug-2 {
 			label = "keystone:blue:debug2";
 			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */
 		};
 
-		debug3 {
+		led-debug-3 {
 			label = "keystone:blue:debug3";
 			gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */
 		};
@@ -148,7 +145,7 @@
 
 &spi0 {
 	status = "okay";
-	nor_flash: n25q128a11@0 {
+	nor_flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "Micron,n25q128a11", "jedec,spi-nor";
diff --git a/arch/arm/dts/keystone-k2hk-netcp.dtsi b/arch/arm/dts/keystone-k2hk-netcp.dtsi
index 77a32c3..580af63 100644
--- a/arch/arm/dts/keystone-k2hk-netcp.dtsi
+++ b/arch/arm/dts/keystone-k2hk-netcp.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Device Tree Source for Keystone 2 Hawking Netcp driver
  *
- * Copyright 2015 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 qmss: qmss@2a40000 {
@@ -15,9 +12,9 @@
 	#size-cells = <1>;
 	clocks = <&chipclk13>;
 	ranges;
-	queue-range	= <0 0x4000>;
-	linkram0	= <0x100000 0x8000>;
-	linkram1	= <0x0 0x10000>;
+	queue-range = <0 0x4000>;
+	linkram0 = <0x100000 0x8000>;
+	linkram1 = <0x0 0x10000>;
 
 	qmgrs {
 		#address-cells = <1>;
@@ -47,6 +44,7 @@
 				    "region", "push", "pop";
 		};
 	};
+
 	queue-pools {
 		qpend {
 			qpend-0 {
@@ -89,6 +87,7 @@
 			};
 		};
 	};
+
 	descriptor-regions {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -129,7 +128,7 @@
 	#size-cells = <1>;
 
 	/* NetCP address range */
-	ranges  = <0 0x2000000 0x100000>;
+	ranges = <0 0x2000000 0x100000>;
 
 	clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
 	dma-coherent;
@@ -169,11 +168,11 @@
 			secondary-slave-ports {
 				port-2 {
 					slave-port = <2>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 				port-3 {
 					slave-port = <3>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 			};
 		};
diff --git a/arch/arm/dts/keystone-k2hk.dtsi b/arch/arm/dts/keystone-k2hk.dtsi
index fc78696..ef02f23 100644
--- a/arch/arm/dts/keystone-k2hk.dtsi
+++ b/arch/arm/dts/keystone-k2hk.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2013-2014 Texas Instruments, Inc.
- *
  * Keystone 2 Kepler/Hawking soc specific device tree
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 / {
diff --git a/arch/arm/dts/keystone-k2l-clocks.dtsi b/arch/arm/dts/keystone-k2l-clocks.dtsi
index ef8464b..6355280 100644
--- a/arch/arm/dts/keystone-k2l-clocks.dtsi
+++ b/arch/arm/dts/keystone-k2l-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2013-2014 Texas Instruments, Inc.
- *
  * Keystone 2 lamarr SoC clock nodes
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 clocks {
@@ -44,7 +41,7 @@
 		reg-names = "control";
 	};
 
-	clkdfeiqnsys: clkdfeiqnsys {
+	clkdfeiqnsys: clkdfeiqnsys@2350004 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk12>;
@@ -54,7 +51,7 @@
 		domain-id = <0>;
 	};
 
-	clkpcie1: clkpcie1 {
+	clkpcie1: clkpcie1@235002c {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk12>;
@@ -64,7 +61,7 @@
 		domain-id = <4>;
 	};
 
-	clkgem1: clkgem1 {
+	clkgem1: clkgem1@2350040 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk1>;
@@ -74,7 +71,7 @@
 		domain-id = <9>;
 	};
 
-	clkgem2: clkgem2 {
+	clkgem2: clkgem2@2350044 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk1>;
@@ -84,7 +81,7 @@
 		domain-id = <10>;
 	};
 
-	clkgem3: clkgem3 {
+	clkgem3: clkgem3@2350048 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk1>;
@@ -94,7 +91,7 @@
 		domain-id = <11>;
 	};
 
-	clktac: clktac {
+	clktac: clktac@2350064 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -104,7 +101,7 @@
 		domain-id = <17>;
 	};
 
-	clkrac: clkrac {
+	clkrac: clkrac@2350068 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -114,7 +111,7 @@
 		domain-id = <17>;
 	};
 
-	clkdfepd0: clkdfepd0 {
+	clkdfepd0: clkdfepd0@235006c {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -124,7 +121,7 @@
 		domain-id = <18>;
 	};
 
-	clkfftc0: clkfftc0 {
+	clkfftc0: clkfftc0@2350070 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -134,7 +131,7 @@
 		domain-id = <19>;
 	};
 
-	clkosr: clkosr {
+	clkosr: clkosr@2350088 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -144,7 +141,7 @@
 		domain-id = <21>;
 	};
 
-	clktcp3d0: clktcp3d0 {
+	clktcp3d0: clktcp3d0@235008c {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -154,7 +151,7 @@
 		domain-id = <22>;
 	};
 
-	clktcp3d1: clktcp3d1 {
+	clktcp3d1: clktcp3d1@2350094 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -164,7 +161,7 @@
 		domain-id = <23>;
 	};
 
-	clkvcp0: clkvcp0 {
+	clkvcp0: clkvcp0@235009c {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -174,7 +171,7 @@
 		domain-id = <24>;
 	};
 
-	clkvcp1: clkvcp1 {
+	clkvcp1: clkvcp1@23500a0 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -184,7 +181,7 @@
 		domain-id = <24>;
 	};
 
-	clkvcp2: clkvcp2 {
+	clkvcp2: clkvcp2@23500a4 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -194,7 +191,7 @@
 		domain-id = <24>;
 	};
 
-	clkvcp3: clkvcp3 {
+	clkvcp3: clkvcp3@23500a8 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -204,7 +201,7 @@
 		domain-id = <24>;
 	};
 
-	clkbcp: clkbcp {
+	clkbcp: clkbcp@23500bc {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -214,7 +211,7 @@
 		domain-id = <26>;
 	};
 
-	clkdfepd1: clkdfepd1 {
+	clkdfepd1: clkdfepd1@23500c0 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -224,7 +221,7 @@
 		domain-id = <27>;
 	};
 
-	clkfftc1: clkfftc1 {
+	clkfftc1: clkfftc1@23500c4 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -234,7 +231,7 @@
 		domain-id = <28>;
 	};
 
-	clkiqnail: clkiqnail {
+	clkiqnail: clkiqnail@23500c8 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
@@ -244,7 +241,7 @@
 		domain-id = <29>;
 	};
 
-	clkuart2: clkuart2 {
+	clkuart2: clkuart2@2350000 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&clkmodrst0>;
@@ -254,7 +251,7 @@
 		domain-id = <0>;
 	};
 
-	clkuart3: clkuart3 {
+	clkuart3: clkuart3@2350000 {
 		#clock-cells = <0>;
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&clkmodrst0>;
diff --git a/arch/arm/dts/keystone-k2l-evm.dts b/arch/arm/dts/keystone-k2l-evm.dts
index ca049ba..187f2ca 100644
--- a/arch/arm/dts/keystone-k2l-evm.dts
+++ b/arch/arm/dts/keystone-k2l-evm.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2014 Texas Instruments, Inc.
- *
  * Keystone 2 Lamarr EVM device tree
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 /dts-v1/;
 
@@ -97,7 +94,7 @@
 
 &spi0 {
 	status ="okay";
-	nor_flash: n25q128a11@0 {
+	nor_flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "Micron,n25q128a11", "jedec,spi-nor";
diff --git a/arch/arm/dts/keystone-k2l-netcp.dtsi b/arch/arm/dts/keystone-k2l-netcp.dtsi
index 6b95284..54c1128 100644
--- a/arch/arm/dts/keystone-k2l-netcp.dtsi
+++ b/arch/arm/dts/keystone-k2l-netcp.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Device Tree Source for Keystone 2 Lamarr Netcp driver
  *
- * Copyright 2015 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 qmss: qmss@2a40000 {
@@ -15,9 +12,9 @@
 	#size-cells = <1>;
 	clocks = <&chipclk13>;
 	ranges;
-	queue-range	= <0 0x2000>;
-	linkram0	= <0x100000 0x4000>;
-	linkram1	= <0x70000000 0x10000>; /* 1MB OSR mem */
+	queue-range = <0 0x2000>;
+	linkram0 = <0x100000 0x4000>;
+	linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
 
 	qmgrs {
 		#address-cells = <1>;
@@ -73,6 +70,7 @@
 			};
 		};
 	};
+
 	descriptor-regions {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -137,24 +135,24 @@
 			interfaces {
 				gbe0: interface-0 {
 					slave-port = <0>;
-					link-interface	= <1>;
-					phy-handle	= <&ethphy0>;
+					link-interface = <1>;
+					phy-handle = <&ethphy0>;
 				};
 				gbe1: interface-1 {
 					slave-port = <1>;
-					link-interface	= <1>;
-					phy-handle	= <&ethphy1>;
+					link-interface = <1>;
+					phy-handle = <&ethphy1>;
 				};
 			};
 
 			secondary-slave-ports {
 				port-2 {
 					slave-port = <2>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 				port-3 {
 					slave-port = <3>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 			};
 		};
diff --git a/arch/arm/dts/keystone-k2l.dtsi b/arch/arm/dts/keystone-k2l.dtsi
index d681cab..dcc83a7 100644
--- a/arch/arm/dts/keystone-k2l.dtsi
+++ b/arch/arm/dts/keystone-k2l.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2014 Texas Instruments, Inc.
- *
  * Keystone 2 Lamarr SoC specific device tree
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 / {
@@ -31,23 +28,23 @@
 	soc {
 		/include/ "keystone-k2l-clocks.dtsi"
 
-		uart2: serial@02348400 {
+		uart2: serial@2348400 {
 			compatible = "ns16550a";
 			current-speed = <115200>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			reg = <0x02348400 0x100>;
-			clocks	= <&clkuart2>;
+			clocks = <&clkuart2>;
 			interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>;
 		};
 
-		uart3:	serial@02348800 {
+		uart3:	serial@2348800 {
 			compatible = "ns16550a";
 			current-speed = <115200>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			reg = <0x02348800 0x100>;
-			clocks	= <&clkuart3>;
+			clocks = <&clkuart3>;
 			interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
 		};
 
@@ -80,14 +77,14 @@
 		};
 
 		mdio: mdio@26200f00 {
-			compatible	= "ti,keystone_mdio", "ti,davinci_mdio";
+			compatible = "ti,keystone_mdio", "ti,davinci_mdio";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x26200f00 0x100>;
 			status = "disabled";
 			clocks = <&clkcpgmac>;
 			clock-names = "fck";
-			bus_freq	= <2500000>;
+			bus_freq = <2500000>;
 		};
 		/include/ "keystone-k2l-netcp.dtsi"
 	};
diff --git a/arch/arm/dts/keystone.dtsi b/arch/arm/dts/keystone.dtsi
index 9a2e1f6..2afcab7 100644
--- a/arch/arm/dts/keystone.dtsi
+++ b/arch/arm/dts/keystone.dtsi
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -94,23 +91,23 @@
 
 		/include/ "keystone-clocks.dtsi"
 
-		uart0: serial@02530c00 {
+		uart0: serial@2530c00 {
 			compatible = "ns16550a";
 			current-speed = <115200>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			reg = <0x02530c00 0x100>;
-			clocks	= <&clkuart0>;
+			clocks = <&clkuart0>;
 			interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
 		};
 
-		uart1:	serial@02531000 {
+		uart1:	serial@2531000 {
 			compatible = "ns16550a";
 			current-speed = <115200>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			reg = <0x02531000 0x100>;
-			clocks	= <&clkuart1>;
+			clocks = <&clkuart1>;
 			interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
 		};
 
@@ -198,7 +195,7 @@
 			dma-ranges;
 			status = "disabled";
 
-			dwc3@2690000 {
+			usb@2690000 {
 				compatible = "synopsys,dwc3";
 				reg = <0x2690000 0x70000>;
 				interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
@@ -206,7 +203,7 @@
 			};
 		};
 
-		wdt: wdt@022f0080 {
+		wdt: wdt@22f0080 {
 			compatible = "ti,keystone-wdt","ti,davinci-wdt";
 			reg = <0x022f0080 0x80>;
 			clocks = <&clkwdtimer0>;
@@ -290,7 +287,7 @@
 			clock-names = "pcie";
 			#address-cells = <3>;
 			#size-cells = <2>;
-			reg =  <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
+			reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
 			ranges = <0x81000000 0 0 0x23250000 0 0x4000
 				0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
 
diff --git a/arch/arm/dts/mt7986a-bpi-r3-emmc.dts b/arch/arm/dts/mt7986a-bpi-r3-emmc.dts
new file mode 100644
index 0000000..4e2e526
--- /dev/null
+++ b/arch/arm/dts/mt7986a-bpi-r3-emmc.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7986a-bpi-r3-sd.dts"
+#include <dt-bindings/gpio/gpio.h>
+/ {
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_default>;
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	non-removable;
+	status = "okay";
+};
diff --git a/arch/arm/dts/mt7986a-bpi-r3-sd.dts b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
new file mode 100644
index 0000000..4d12440
--- /dev/null
+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7986.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	model = "BananaPi BPi-R3";
+	compatible = "mediatek,mt7986", "mediatek,mt7986-sd-rfb";
+
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer0;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		factory {
+			label = "reset";
+			gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_status_green: green {
+			label = "green:status";
+			gpios = <&gpio 69 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_status_blue: blue {
+			label = "blue:status";
+			gpios = <&gpio 86 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	status = "disabled";
+};
+
+&eth {
+	status = "okay";
+	mediatek,gmac-id = <0>;
+	phy-mode = "sgmii";
+	mediatek,switch = "mt7531";
+	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&pinctrl {
+	spic_pins: spi1-pins-func-1 {
+		mux {
+			function = "spi";
+			groups = "spi1_2";
+		};
+	};
+
+	uart1_pins: spi1-pins-func-3 {
+		mux {
+			function = "uart";
+			groups = "uart1_2";
+		};
+	};
+
+	pwm_pins: pwm0-pins-func-1 {
+		mux {
+			function = "pwm";
+			groups = "pwm0";
+		};
+	};
+
+	mmc0_pins_default: mmc0default {
+		mux {
+			function = "flash";
+			groups =  "emmc_51";
+		};
+
+		conf-cmd-dat {
+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+			input-enable;
+			drive-strength = <MTK_DRIVE_4mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+
+		conf-clk {
+			pins = "EMMC_CK";
+			drive-strength = <MTK_DRIVE_6mA>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+
+		conf-dsl {
+			pins = "EMMC_DSL";
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+
+		conf-rst {
+			pins = "EMMC_RSTB";
+			drive-strength = <MTK_DRIVE_4mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+	};
+
+	spi_flash_pins: spi0-pins-func-1 {
+		mux {
+			function = "flash";
+			groups = "spi0", "spi0_wp_hold";
+		};
+
+		conf-pu {
+			pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
+		};
+
+		conf-pd {
+			pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
+		};
+	};
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm_pins>;
+	status = "okay";
+};
+
+&spi0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_flash_pins>;
+	status = "okay";
+	must_tx;
+	enhance_timing;
+	dma_ext;
+	ipm_design;
+	support_quad;
+	tick_dly = <1>;
+	sample_sel = <0>;
+
+	spi_nor@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "bl2";
+				reg = <0x0 0x40000>;
+			};
+
+			partition@40000 {
+				label = "u-boot-env";
+				reg = <0x40000 0x40000>;
+			};
+
+			partition@80000 {
+				label = "reserved";
+				reg = <0x80000 0x80000>;
+			};
+
+			partition@100000 {
+				label = "fip";
+				reg = <0x100000 0x80000>;
+			};
+
+			partition@180000 {
+				label = "recovery";
+				reg = <0x180000 0xa80000>;
+			};
+
+			partition@c00000 {
+				label = "fit";
+				reg = <0xc00000 0x1400000>;
+			};
+		};
+	};
+
+	spi_nand@1 {
+		compatible = "spi-nand";
+		reg = <1>;
+		spi-max-frequency = <52000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "bl2";
+				reg = <0x0 0x80000>;
+			};
+
+			partition@80000 {
+				label = "factory";
+				reg = <0x80000 0x300000>;
+			};
+
+			partition@380000 {
+				label = "fip";
+				reg = <0x380000 0x200000>;
+			};
+
+			partition@580000 {
+				label = "ubi";
+				reg = <0x580000 0x7a80000>;
+			};
+		};
+	};
+};
+
+&watchdog {
+	status = "disabled";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_default>;
+	bus-width = <4>;
+	max-frequency = <52000000>;
+	cap-sd-highspeed;
+	r_smpl = <1>;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/ns-board.dts b/arch/arm/dts/ns-board.dts
new file mode 100644
index 0000000..bc2a0dd
--- /dev/null
+++ b/arch/arm/dts/ns-board.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier:      GPL-2.0+
+
+/dts-v1/;
+
+#include "bcm5301x.dtsi"
+
+/ {
+	/*
+	 * The Northstar does not have a proper fallback compatible, but
+	 * these basic chips will suffice.
+	 */
+	model = "Northstar model";
+	compatible = "brcm,bcm47094", "brcm,bcm4708";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&gic>;
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x08000000>,
+		      <0x88000000 0x08000000>;
+	};
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	nand-controller@18028000 {
+		nandcs: nand@0 {
+			compatible = "brcm,nandcs";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			/*
+			 * Same as using the bcm5301x-nand-cs0-bch1.dtsi
+			 * include from the Linux kernel.
+			 */
+			nand-ecc-algo = "bch";
+			nand-ecc-strength = <1>;
+			nand-ecc-step-size = <512>;
+
+			partitions {
+				compatible = "brcm,bcm947xx-cfe-partitions";
+			};
+		};
+	};
+};
+
+&uart0 {
+	clock-frequency = <125000000>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/dts/omap-gpmc-smsc911x.dtsi
index ded7e8f..9cf5265 100644
--- a/arch/arm/dts/omap-gpmc-smsc911x.dtsi
+++ b/arch/arm/dts/omap-gpmc-smsc911x.dtsi
@@ -8,9 +8,9 @@
 
 / {
 	vddvario: regulator-vddvario {
-		  compatible = "regulator-fixed";
-		  regulator-name = "vddvario";
-		  regulator-always-on;
+		compatible = "regulator-fixed";
+		regulator-name = "vddvario";
+		regulator-always-on;
 	};
 
 	vdd33a: regulator-vdd33a {
diff --git a/arch/arm/dts/omap-gpmc-smsc9221.dtsi b/arch/arm/dts/omap-gpmc-smsc9221.dtsi
index 73e272f..ac81793 100644
--- a/arch/arm/dts/omap-gpmc-smsc9221.dtsi
+++ b/arch/arm/dts/omap-gpmc-smsc9221.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Common file for GPMC connected smsc9221 on omaps
  *
@@ -11,9 +12,9 @@
 
 / {
 	vddvario: regulator-vddvario {
-		  compatible = "regulator-fixed";
-		  regulator-name = "vddvario";
-		  regulator-always-on;
+		compatible = "regulator-fixed";
+		regulator-name = "vddvario";
+		regulator-always-on;
 	};
 
 	vdd33a: regulator-vdd33a {
diff --git a/arch/arm/dts/omap3-beagle-xm-ab.dts b/arch/arm/dts/omap3-beagle-xm-ab.dts
index 7ac3bcf..cb6968a 100644
--- a/arch/arm/dts/omap3-beagle-xm-ab.dts
+++ b/arch/arm/dts/omap3-beagle-xm-ab.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "omap3-beagle-xm.dts"
diff --git a/arch/arm/dts/omap3-beagle-xm.dts b/arch/arm/dts/omap3-beagle-xm.dts
index 8461159..73152f6 100644
--- a/arch/arm/dts/omap3-beagle-xm.dts
+++ b/arch/arm/dts/omap3-beagle-xm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -30,26 +27,26 @@
 		ethernet = &ethernet;
 	};
 
-	leds {
+	led-controller-1 {
 		compatible = "gpio-leds";
 
-		heartbeat {
+		led-1 {
 			label = "beagleboard::usr0";
 			gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
 			linux,default-trigger = "heartbeat";
 		};
 
-		mmc {
+		led-2 {
 			label = "beagleboard::usr1";
 			gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
 			linux,default-trigger = "mmc0";
 		};
 	};
 
-	pwmleds {
+	led-controller-2 {
 		compatible = "pwm-leds";
 
-		pmu_stat {
+		led-3 {
 			label = "beagleboard::pmu_stat";
 			pwms = <&twl_pwmled 1 7812500>;
 			max-brightness = <127>;
@@ -360,7 +357,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		ethernet: usbether@1 {
+		ethernet: ethernet@1 {
 			compatible = "usb424,ec00";
 			reg = <1>;
 		};
diff --git a/arch/arm/dts/omap3-beagle.dts b/arch/arm/dts/omap3-beagle.dts
index 4ceee2b..321b6d7 100644
--- a/arch/arm/dts/omap3-beagle.dts
+++ b/arch/arm/dts/omap3-beagle.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -31,18 +28,18 @@
 
 	leds {
 		compatible = "gpio-leds";
-		pmu_stat {
+		led-pmu-stat {
 			label = "beagleboard::pmu_stat";
 			gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
 		};
 
-		heartbeat {
+		led-heartbeat {
 			label = "beagleboard::usr0";
 			gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
 			linux,default-trigger = "heartbeat";
 		};
 
-		mmc {
+		led-mmc {
 			label = "beagleboard::usr1";
 			gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
 			linux,default-trigger = "mmc0";
diff --git a/arch/arm/dts/omap3-cpu-thermal.dtsi b/arch/arm/dts/omap3-cpu-thermal.dtsi
index 235ecfd..e677d1d 100644
--- a/arch/arm/dts/omap3-cpu-thermal.dtsi
+++ b/arch/arm/dts/omap3-cpu-thermal.dtsi
@@ -1,16 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP3 SoC CPU thermal
  *
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/thermal/thermal.h>
 
-cpu_thermal: cpu_thermal {
+cpu_thermal: cpu-thermal {
 	polling-delay-passive = <250>; /* milliseconds */
 	polling-delay = <1000>; /* milliseconds */
 	coefficients = <0 20000>;
diff --git a/arch/arm/dts/omap3-evm-37xx.dts b/arch/arm/dts/omap3-evm-37xx.dts
index a14303b..abd403c 100644
--- a/arch/arm/dts/omap3-evm-37xx.dts
+++ b/arch/arm/dts/omap3-evm-37xx.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -63,7 +60,7 @@
 		interrupt-parent = <&gpmc>;
 		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 			     <1 IRQ_TYPE_NONE>;	/* termcount */
-		linux,mtd-name= "hynix,h8kds0un0mer-4em";
+		linux,mtd-name = "hynix,h8kds0un0mer-4em";
 		nand-bus-width = <16>;
 		gpmc,device-width = <2>;
 		ti,nand-ecc-opt = "bch8";
diff --git a/arch/arm/dts/omap3-evm-processor-common.dtsi b/arch/arm/dts/omap3-evm-processor-common.dtsi
index b4109f4..e6ba30a 100644
--- a/arch/arm/dts/omap3-evm-processor-common.dtsi
+++ b/arch/arm/dts/omap3-evm-processor-common.dtsi
@@ -195,7 +195,7 @@
  * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V.
  */
 &gpio2 {
-	en_usb2_port {
+	en-usb2-port-hog {
 		gpio-hog;
 		gpios = <29 GPIO_ACTIVE_HIGH>;	/* gpio_61 */
 		output-low;
diff --git a/arch/arm/dts/omap3-evm.dts b/arch/arm/dts/omap3-evm.dts
index 21a3b88..f95eea6 100644
--- a/arch/arm/dts/omap3-evm.dts
+++ b/arch/arm/dts/omap3-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -63,7 +60,7 @@
 		interrupt-parent = <&gpmc>;
 		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 			     <1 IRQ_TYPE_NONE>;	/* termcount */
-		linux,mtd-name= "micron,mt29f2g16abdhc";
+		linux,mtd-name = "micron,mt29f2g16abdhc";
 		nand-bus-width = <16>;
 		gpmc,device-width = <2>;
 		ti,nand-ecc-opt = "bch8";
diff --git a/arch/arm/dts/omap3-igep.dtsi b/arch/arm/dts/omap3-igep.dtsi
index f33cc80..2192026 100644
--- a/arch/arm/dts/omap3-igep.dtsi
+++ b/arch/arm/dts/omap3-igep.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Common device tree for IGEP boards based on AM/DM37x
  *
- * Copyright (C) 2012 Javier Martinez Canillas <javier@osg.samsung.com>
+ * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
  * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 /dts-v1/;
 
@@ -114,7 +111,7 @@
 		interrupt-parent = <&gpmc>;
 		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 			     <1 IRQ_TYPE_NONE>;	/* termcount */
-		linux,mtd-name= "micron,mt29c4g96maz";
+		linux,mtd-name = "micron,mt29c4g96maz";
 		nand-bus-width = <16>;
 		gpmc,device-width = <2>;
 		ti,nand-ecc-opt = "bch8";
diff --git a/arch/arm/dts/omap3-igep0020-common.dtsi b/arch/arm/dts/omap3-igep0020-common.dtsi
index d62481d..73d8f47 100644
--- a/arch/arm/dts/omap3-igep0020-common.dtsi
+++ b/arch/arm/dts/omap3-igep0020-common.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Common Device Tree Source for IGEPv2
  *
- * Copyright (C) 2014 Javier Martinez Canillas <javier@osg.samsung.com>
+ * Copyright (C) 2014 Javier Martinez Canillas <javier@dowhile0.org>
  * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include "omap3-igep.dtsi"
diff --git a/arch/arm/dts/omap3-igep0020.dts b/arch/arm/dts/omap3-igep0020.dts
index 33d6b4e..cf3ac84 100644
--- a/arch/arm/dts/omap3-igep0020.dts
+++ b/arch/arm/dts/omap3-igep0020.dts
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x)
  *
- * Copyright (C) 2012 Javier Martinez Canillas <javier@osg.samsung.com>
+ * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
  * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include "omap3-igep0020-common.dtsi"
diff --git a/arch/arm/dts/omap3.dtsi b/arch/arm/dts/omap3.dtsi
index 4043ecb..622ee45 100644
--- a/arch/arm/dts/omap3.dtsi
+++ b/arch/arm/dts/omap3.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP3 SoC
  *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -356,7 +353,7 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <2>;
 			ti,mbox-num-fifos = <2>;
-			mbox_dsp: dsp {
+			mbox_dsp: mbox-dsp {
 				ti,mbox-tx = <0 0 0>;
 				ti,mbox-rx = <1 0 0>;
 			};
diff --git a/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi
index 858aa07..5e9d1af 100644
--- a/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi
+++ b/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP34XX/OMAP36XX clock data
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 &cm_clocks {
 	security_l4_ick2: security_l4_ick2 {
diff --git a/arch/arm/dts/omap34xx.dtsi b/arch/arm/dts/omap34xx.dtsi
index a703d09..28ca9c3 100644
--- a/arch/arm/dts/omap34xx.dtsi
+++ b/arch/arm/dts/omap34xx.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP34xx/OMAP35xx SoC
  *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/media/omap3-isp.h>
diff --git a/arch/arm/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
index 15d1866..9974d52 100644
--- a/arch/arm/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
+++ b/arch/arm/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 &prm_clocks {
 	corex2_d3_fck: corex2_d3_fck {
diff --git a/arch/arm/dts/omap36xx-clocks.dtsi b/arch/arm/dts/omap36xx-clocks.dtsi
index a21d1f0..e66fc57 100644
--- a/arch/arm/dts/omap36xx-clocks.dtsi
+++ b/arch/arm/dts/omap36xx-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP36xx clock data
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 &cm_clocks {
 	dpll4_ck: dpll4_ck@d00 {
diff --git a/arch/arm/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/dts/omap36xx-omap3430es2plus-clocks.dtsi
index 1a4fbdf..945537a 100644
--- a/arch/arm/dts/omap36xx-omap3430es2plus-clocks.dtsi
+++ b/arch/arm/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP34xx/OMAP36xx clock data
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 &cm_clocks {
 	ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 {
diff --git a/arch/arm/dts/omap36xx.dtsi b/arch/arm/dts/omap36xx.dtsi
index 52e1b8c..e5f0207 100644
--- a/arch/arm/dts/omap36xx.dtsi
+++ b/arch/arm/dts/omap36xx.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP3 SoC
  *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/bus/ti-sysc.h>
diff --git a/arch/arm/dts/omap3xxx-clocks.dtsi b/arch/arm/dts/omap3xxx-clocks.dtsi
index 9bd9164..685c82a 100644
--- a/arch/arm/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/dts/omap3xxx-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP3 clock data
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 &prm_clocks {
 	virt_16_8m_ck: virt_16_8m_ck {
diff --git a/arch/arm/dts/omap4-cpu-thermal.dtsi b/arch/arm/dts/omap4-cpu-thermal.dtsi
index ab7f87a..801b4f1 100644
--- a/arch/arm/dts/omap4-cpu-thermal.dtsi
+++ b/arch/arm/dts/omap4-cpu-thermal.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP4/5 SoC CPU thermal
  *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <dt-bindings/thermal/thermal.h>
@@ -16,20 +13,20 @@
 	polling-delay = <1000>; /* milliseconds */
 
 			/* sensor       ID */
-        thermal-sensors = <&bandgap     0>;
+	thermal-sensors = <&bandgap     0>;
 
 	cpu_trips: trips {
-                cpu_alert0: cpu_alert {
-                        temperature = <100000>; /* millicelsius */
-                        hysteresis = <2000>; /* millicelsius */
-                        type = "passive";
-                };
-                cpu_crit: cpu_crit {
-                        temperature = <125000>; /* millicelsius */
-                        hysteresis = <2000>; /* millicelsius */
-                        type = "critical";
-                };
-        };
+		cpu_alert0: cpu_alert {
+			temperature = <100000>; /* millicelsius */
+			hysteresis = <2000>; /* millicelsius */
+			type = "passive";
+		};
+		cpu_crit: cpu_crit {
+			temperature = <125000>; /* millicelsius */
+			hysteresis = <2000>; /* millicelsius */
+			type = "critical";
+		};
+	};
 
 	cpu_cooling_maps: cooling-maps {
 		map0 {
diff --git a/arch/arm/dts/omap4-l4.dtsi b/arch/arm/dts/omap4-l4.dtsi
index 424a694..84d92b8 100644
--- a/arch/arm/dts/omap4-l4.dtsi
+++ b/arch/arm/dts/omap4-l4.dtsi
@@ -599,11 +599,11 @@
 				#mbox-cells = <1>;
 				ti,mbox-num-users = <3>;
 				ti,mbox-num-fifos = <8>;
-				mbox_ipu: mbox_ipu {
+				mbox_ipu: mbox-ipu {
 					ti,mbox-tx = <0 0 0>;
 					ti,mbox-rx = <1 0 0>;
 				};
-				mbox_dsp: mbox_dsp {
+				mbox_dsp: mbox-dsp {
 					ti,mbox-tx = <3 0 0>;
 					ti,mbox-rx = <2 0 0>;
 				};
diff --git a/arch/arm/dts/omap4-panda-common.dtsi b/arch/arm/dts/omap4-panda-common.dtsi
index c124b20..6174fbe 100644
--- a/arch/arm/dts/omap4-panda-common.dtsi
+++ b/arch/arm/dts/omap4-panda-common.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2011-2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2013 Texas Instruments Incorporated - https://www.ti.com/
  */
 #include <dt-bindings/input/input.h>
 #include "elpida_ecb240abacn.dtsi"
@@ -29,13 +29,13 @@
 			&led_wkgpio_pins
 		>;
 
-		heartbeat {
+		led-heartbeat {
 			label = "pandaboard::status1";
 			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 
-		mmc {
+		led-mmc {
 			label = "pandaboard::status2";
 			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "mmc0";
@@ -538,7 +538,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		ethernet: usbether@1 {
+		ethernet: ethernet@1 {
 			compatible = "usb424,ec00";
 			reg = <1>;
 		};
diff --git a/arch/arm/dts/omap4-panda-es.dts b/arch/arm/dts/omap4-panda-es.dts
index 9dd307b..35e4f34 100644
--- a/arch/arm/dts/omap4-panda-es.dts
+++ b/arch/arm/dts/omap4-panda-es.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -63,10 +63,10 @@
 		&led_wkgpio_pins
 	>;
 
-	heartbeat {
+	led-heartbeat {
 		gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
 	};
-	mmc {
+	led-mmc {
 		gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
 	};
 };
diff --git a/arch/arm/dts/omap4-panda.dts b/arch/arm/dts/omap4-panda.dts
index fb2f477..529d5bc 100644
--- a/arch/arm/dts/omap4-panda.dts
+++ b/arch/arm/dts/omap4-panda.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
diff --git a/arch/arm/dts/omap4-sdp-es23plus.dts b/arch/arm/dts/omap4-sdp-es23plus.dts
index 4215452..869f627 100644
--- a/arch/arm/dts/omap4-sdp-es23plus.dts
+++ b/arch/arm/dts/omap4-sdp-es23plus.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 #include "omap4-sdp.dts"
 
diff --git a/arch/arm/dts/omap4-sdp.dts b/arch/arm/dts/omap4-sdp.dts
index 28b989c..9e97614 100644
--- a/arch/arm/dts/omap4-sdp.dts
+++ b/arch/arm/dts/omap4-sdp.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -45,58 +45,60 @@
 		regulator-boot-on;
 	};
 
-	leds {
+	led-controller-1 {
 		compatible = "gpio-leds";
-		debug0 {
+
+		led-1 {
 			label = "omap4:green:debug0";
 			gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */
 		};
 
-		debug1 {
+		led-2 {
 			label = "omap4:green:debug1";
 			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */
 		};
 
-		debug2 {
+		led-3 {
 			label = "omap4:green:debug2";
 			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */
 		};
 
-		debug3 {
+		led-4 {
 			label = "omap4:green:debug3";
 			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */
 		};
 
-		debug4 {
+		led-5 {
 			label = "omap4:green:debug4";
 			gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */
 		};
 
-		user1 {
+		led-6 {
 			label = "omap4:blue:user";
 			gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */
 		};
 
-		user2 {
+		led-7 {
 			label = "omap4:red:user";
 			gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */
 		};
 
-		user3 {
+		led-8 {
 			label = "omap4:green:user";
 			gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */
 		};
 	};
 
-	pwmleds {
+	led-controller-2 {
 		compatible = "pwm-leds";
-		kpad {
+
+		led-9 {
 			label = "omap4::keypad";
 			pwms = <&twl_pwm 0 7812500>;
 			max-brightness = <127>;
 		};
 
-		charging {
+		led-10 {
 			label = "omap4:green:chrg";
 			pwms = <&twl_pwmled 0 7812500>;
 			max-brightness = <255>;
@@ -428,7 +430,7 @@
 
 	/*
 	 * Temperature Sensor
-	 * http://www.ti.com/lit/ds/symlink/tmp105.pdf
+	 * https://www.ti.com/lit/ds/symlink/tmp105.pdf
 	 */
 	tmp105@48 {
 		compatible = "ti,tmp105";
@@ -453,7 +455,7 @@
 
 	/*
 	 * 3-Axis Digital Compass
-	 * http://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf
+	 * https://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf
 	 */
 	hmc5843@1e {
 		compatible = "honeywell,hmc5843";
@@ -662,8 +664,9 @@
 		};
 	};
 
-	lcd0: display {
+	lcd0: panel@0 {
 		compatible = "tpo,taal", "panel-dsi-cm";
+		reg = <0>;
 		label = "lcd0";
 
 		reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;	/* 102 */
@@ -687,8 +690,9 @@
 		};
 	};
 
-	lcd1: display {
+	lcd1: panel@0 {
 		compatible = "tpo,taal", "panel-dsi-cm";
+		reg = <0>;
 		label = "lcd1";
 
 		reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;	/* 104 */
diff --git a/arch/arm/dts/omap4.dtsi b/arch/arm/dts/omap4.dtsi
index 763bdea..d1ab5f4 100644
--- a/arch/arm/dts/omap4.dtsi
+++ b/arch/arm/dts/omap4.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/bus/ti-sysc.h>
@@ -71,7 +71,7 @@
 		interrupt-parent = <&gic>;
 	};
 
-	L2: l2-cache-controller@48242000 {
+	L2: cache-controller@48242000 {
 		compatible = "arm,pl310-cache";
 		reg = <0x48242000 0x1000>;
 		cache-unified;
@@ -389,7 +389,7 @@
 			status = "disabled";
 		};
 
-		target-module@56000000 {
+		sgx_module: target-module@56000000 {
 			compatible = "ti,sysc-omap4", "ti,sysc";
 			reg = <0x5600fe00 0x4>,
 			      <0x5600fe10 0x4>;
@@ -551,6 +551,9 @@
 						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
 							 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 						clock-names = "fck", "sys_clk";
+
+						#address-cells = <1>;
+						#size-cells = <0>;
 					};
 				};
 
@@ -583,6 +586,9 @@
 						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
 						         <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 						clock-names = "fck", "sys_clk";
+
+						#address-cells = <1>;
+						#size-cells = <0>;
 					};
 				};
 
diff --git a/arch/arm/dts/omap443x-clocks.dtsi b/arch/arm/dts/omap443x-clocks.dtsi
index 3929786..581e088 100644
--- a/arch/arm/dts/omap443x-clocks.dtsi
+++ b/arch/arm/dts/omap443x-clocks.dtsi
@@ -8,6 +8,7 @@
 	bandgap_fclk: bandgap_fclk@1888 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
+		clock-output-names = "bandgap_fclk";
 		clocks = <&sys_32k_ck>;
 		ti,bit-shift = <8>;
 		reg = <0x1888>;
diff --git a/arch/arm/dts/omap443x.dtsi b/arch/arm/dts/omap443x.dtsi
index cbcdcb4..a7ee13b 100644
--- a/arch/arm/dts/omap443x.dtsi
+++ b/arch/arm/dts/omap443x.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP443x SoC
  *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "omap4.dtsi"
diff --git a/arch/arm/dts/omap4460.dtsi b/arch/arm/dts/omap4460.dtsi
index 2223dc0..21ddff9 100644
--- a/arch/arm/dts/omap4460.dtsi
+++ b/arch/arm/dts/omap4460.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP4460 SoC
  *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 #include "omap4.dtsi"
 
diff --git a/arch/arm/dts/omap5-board-common.dtsi b/arch/arm/dts/omap5-board-common.dtsi
deleted file mode 100644
index 1eedd8d..0000000
--- a/arch/arm/dts/omap5-board-common.dtsi
+++ /dev/null
@@ -1,762 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- */
-#include "omap5.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
-	aliases {
-		display0 = &hdmi0;
-	};
-
-	chosen {
-		stdout-path = &uart3;
-	};
-
-	vmain: fixedregulator-vmain {
-		compatible = "regulator-fixed";
-		regulator-name = "vmain";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-
-	vsys_cobra: fixedregulator-vsys_cobra {
-		compatible = "regulator-fixed";
-		regulator-name = "vsys_cobra";
-		vin-supply = <&vmain>;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-
-	vdds_1v8_main: fixedregulator-vdds_1v8_main {
-		compatible = "regulator-fixed";
-		regulator-name = "vdds_1v8_main";
-		vin-supply = <&smps7_reg>;
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-	};
-
-	vmmcsd_fixed: fixedregulator-mmcsd {
-		compatible = "regulator-fixed";
-		regulator-name = "vmmcsd_fixed";
-		regulator-min-microvolt = <3000000>;
-		regulator-max-microvolt = <3000000>;
-	};
-
-	mmc3_pwrseq: sdhci0_pwrseq {
-		compatible = "mmc-pwrseq-simple";
-		clocks = <&clk32kgaudio>;
-		clock-names = "ext_clock";
-	};
-
-	vmmcsdio_fixed: fixedregulator-mmcsdio {
-		compatible = "regulator-fixed";
-		regulator-name = "vmmcsdio_fixed";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		gpio = <&gpio5 12 GPIO_ACTIVE_HIGH>;	/* gpio140 WLAN_EN */
-		enable-active-high;
-		startup-delay-us = <70000>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&wlan_pins>;
-	};
-
-	/* HS USB Host PHY on PORT 2 */
-	hsusb2_phy: hsusb2_phy {
-		compatible = "usb-nop-xceiv";
-		reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */
-		clocks = <&auxclk1_ck>;
-		clock-names = "main_clk";
-		clock-frequency = <19200000>;
-		#phy-cells = <0>;
-	};
-
-	/* HS USB Host PHY on PORT 3 */
-	hsusb3_phy: hsusb3_phy {
-		compatible = "usb-nop-xceiv";
-		reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */
-		#phy-cells = <0>;
-	};
-
-	tpd12s015: encoder {
-		compatible = "ti,tpd12s015";
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&tpd12s015_pins>;
-
-		/* gpios defined in the board specific dts */
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-
-				tpd12s015_in: endpoint {
-					remote-endpoint = <&hdmi_out>;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-
-				tpd12s015_out: endpoint {
-					remote-endpoint = <&hdmi_connector_in>;
-				};
-			};
-		};
-	};
-
-	hdmi0: connector {
-		compatible = "hdmi-connector";
-		label = "hdmi";
-
-		type = "b";
-
-		port {
-			hdmi_connector_in: endpoint {
-				remote-endpoint = <&tpd12s015_out>;
-			};
-		};
-	};
-
-	sound: sound {
-		compatible = "ti,abe-twl6040";
-		ti,model = "omap5-uevm";
-
-		ti,jack-detection;
-		ti,mclk-freq = <19200000>;
-
-		ti,mcpdm = <&mcpdm>;
-
-		ti,twl6040 = <&twl6040>;
-
-		/* Audio routing */
-		ti,audio-routing =
-			"Headset Stereophone", "HSOL",
-			"Headset Stereophone", "HSOR",
-			"Line Out", "AUXL",
-			"Line Out", "AUXR",
-			"HSMIC", "Headset Mic",
-			"Headset Mic", "Headset Mic Bias",
-			"AFML", "Line In",
-			"AFMR", "Line In";
-	};
-};
-
-&gpio8 {
-	/* TI trees use GPIO instead of msecure, see also muxing */
-	p234 {
-		gpio-hog;
-		gpios = <10 GPIO_ACTIVE_HIGH>;
-		output-high;
-		line-name = "gpio8_234/msecure";
-	};
-};
-
-&omap5_pmx_core {
-	pinctrl-names = "default";
-	pinctrl-0 = <
-			&usbhost_pins
-			&led_gpio_pins
-	>;
-
-	twl6040_pins: pinmux_twl6040_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6)	/* mcspi1_somi.gpio5_141 */
-		>;
-	};
-
-	mcpdm_pins: pinmux_mcpdm_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x182, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_clks.abe_clks */
-			OMAP5_IOPAD(0x19c, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abemcpdm_ul_data.abemcpdm_ul_data */
-			OMAP5_IOPAD(0x19e, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abemcpdm_dl_data.abemcpdm_dl_data */
-			OMAP5_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE0)	/* abemcpdm_frame.abemcpdm_frame */
-			OMAP5_IOPAD(0x1a2, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abemcpdm_lb_clk.abemcpdm_lb_clk */
-		>;
-	};
-
-	mcbsp1_pins: pinmux_mcbsp1_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x18c, PIN_INPUT | MUX_MODE1)		/* abedmic_clk2.abemcbsp1_fsx */
-			OMAP5_IOPAD(0x18e, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* abedmic_clk3.abemcbsp1_dx */
-			OMAP5_IOPAD(0x190, PIN_INPUT | MUX_MODE1)		/* abeslimbus1_clock.abemcbsp1_clkx */
-			OMAP5_IOPAD(0x192, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* abeslimbus1_data.abemcbsp1_dr */
-		>;
-	};
-
-	mcbsp2_pins: pinmux_mcbsp2_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x194, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abemcbsp2_dr.abemcbsp2_dr */
-			OMAP5_IOPAD(0x196, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* abemcbsp2_dx.abemcbsp2_dx */
-			OMAP5_IOPAD(0x198, PIN_INPUT | MUX_MODE0)		/* abemcbsp2_fsx.abemcbsp2_fsx */
-			OMAP5_IOPAD(0x19a, PIN_INPUT | MUX_MODE0)		/* abemcbsp2_clkx.abemcbsp2_clkx */
-		>;
-	};
-
-	i2c1_pins: pinmux_i2c1_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x1f2, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_scl */
-			OMAP5_IOPAD(0x1f4, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_sda */
-		>;
-	};
-
-	mcspi2_pins: pinmux_mcspi2_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0)		/*  mcspi2_clk */
-			OMAP5_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0)		/*  mcspi2_simo */
-			OMAP5_IOPAD(0x100, PIN_INPUT_PULLUP | MUX_MODE0)	/*  mcspi2_somi */
-			OMAP5_IOPAD(0x102, PIN_OUTPUT | MUX_MODE0)		/*  mcspi2_cs0 */
-		>;
-	};
-
-	mcspi3_pins: pinmux_mcspi3_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x0b8, PIN_INPUT | MUX_MODE1)		/*  mcspi3_somi */
-			OMAP5_IOPAD(0x0ba, PIN_INPUT | MUX_MODE1)		/*  mcspi3_cs0 */
-			OMAP5_IOPAD(0x0bc, PIN_INPUT | MUX_MODE1)		/*  mcspi3_simo */
-			OMAP5_IOPAD(0x0be, PIN_INPUT | MUX_MODE1)		/*  mcspi3_clk */
-		>;
-	};
-
-	mmc3_pins: pinmux_mmc3_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */
-			OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */
-			OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */
-			OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */
-			OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */
-			OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */
-		>;
-	};
-
-	wlan_pins: pinmux_wlan_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE6) /* mcspi1_clk.gpio5_140 */
-		>;
-	};
-
-	/* TI trees use GPIO mode; msecure mode does not work reliably? */
-	palmas_msecure_pins: palmas_msecure_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE6) /* gpio8_234 */
-		>;
-	};
-
-	usbhost_pins: pinmux_usbhost_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x0c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */
-			OMAP5_IOPAD(0x0c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */
-
-			OMAP5_IOPAD(0x1de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */
-			OMAP5_IOPAD(0x1e0, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */
-
-			OMAP5_IOPAD(0x0b0, PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */
-			OMAP5_IOPAD(0x0ae, PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */
-		>;
-	};
-
-	led_gpio_pins: pinmux_led_gpio_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x1d6, PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */
-		>;
-	};
-
-	uart1_pins: pinmux_uart1_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x0a0, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */
-			OMAP5_IOPAD(0x0a2, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */
-			OMAP5_IOPAD(0x0a4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */
-			OMAP5_IOPAD(0x0a6, PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */
-		>;
-	};
-
-	uart3_pins: pinmux_uart3_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x1da, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */
-			OMAP5_IOPAD(0x1dc, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */
-		>;
-	};
-
-	uart5_pins: pinmux_uart5_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x1b0, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */
-			OMAP5_IOPAD(0x1b2, PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */
-			OMAP5_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */
-			OMAP5_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */
-		>;
-	};
-
-	dss_hdmi_pins: pinmux_dss_hdmi_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x13c, PIN_INPUT | MUX_MODE0)	/* hdmi_cec.hdmi_cec */
-			OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0)	/* hdmi_ddc_scl.hdmi_ddc_scl */
-			OMAP5_IOPAD(0x142, PIN_INPUT | MUX_MODE0)	/* hdmi_ddc_sda.hdmi_ddc_sda */
-		>;
-	};
-
-	tpd12s015_pins: pinmux_tpd12s015_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x13e, PIN_INPUT_PULLDOWN | MUX_MODE6)	/* hdmi_hpd.gpio7_193 */
-		>;
-	};
-};
-
-&omap5_pmx_wkup {
-	pinctrl-names = "default";
-	pinctrl-0 = <
-			&usbhost_wkup_pins
-	>;
-
-	palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {
-		pinctrl-single,pins = <
-			/* sys_nirq1 is pulled down as the SoC is inverting it for GIC */
-			OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0)
-		>;
-	};
-
-	usbhost_wkup_pins: pinmux_usbhost_wkup_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */
-		>;
-	};
-
-	wlcore_irq_pin: pinmux_wlcore_irq_pin {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6)	/* llia_wakereqin.gpio1_wk14 */
-		>;
-	};
-};
-
-&mmc1 {
-	vmmc-supply = <&ldo9_reg>;
-	bus-width = <4>;
-};
-
-&mmc2 {
-	vmmc-supply = <&vmmcsd_fixed>;
-	bus-width = <8>;
-	ti,non-removable;
-};
-
-&mmc3 {
-	vmmc-supply = <&vmmcsdio_fixed>;
-	mmc-pwrseq = <&mmc3_pwrseq>;
-	bus-width = <4>;
-	non-removable;
-	cap-power-off-card;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins>;
-	interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
-			       &omap5_pmx_core 0x16a>;
-
-	#address-cells = <1>;
-	#size-cells = <0>;
-	wlcore: wlcore@2 {
-		compatible = "ti,wl1271";
-		reg = <2>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&wlcore_irq_pin>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;	/* gpio 14 */
-		ref-clock-frequency = <26000000>;
-	};
-};
-
-&mmc4 {
-	status = "disabled";
-};
-
-&mmc5 {
-	status = "disabled";
-};
-
-&i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins>;
-
-	clock-frequency = <400000>;
-
-	palmas: palmas@48 {
-		compatible = "ti,palmas";
-		/* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
-		reg = <0x48>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		ti,system-power-controller;
-		ti,mux-pad1 = <0xa1>;
-		ti,mux-pad2 = <0x1b>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>;
-
-		palmas_gpio: gpio {
-			compatible = "ti,palmas-gpio";
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		extcon_usb3: palmas_usb {
-			compatible = "ti,palmas-usb-vid";
-			ti,enable-vbus-detection;
-			ti,enable-id-detection;
-			ti,wakeup;
-			id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>;
-		};
-
-		clk32kgaudio: palmas_clk32k@1 {
-			compatible = "ti,palmas-clk32kgaudio";
-			#clock-cells = <0>;
-		};
-
-		rtc {
-			compatible = "ti,palmas-rtc";
-			interrupt-parent = <&palmas>;
-			interrupts = <8 IRQ_TYPE_NONE>;
-			ti,backup-battery-chargeable;
-			ti,backup-battery-charge-high-current;
-		};
-
-		gpadc: gpadc {
-			compatible = "ti,palmas-gpadc";
-			interrupts = <18 0
-				      16 0
-				      17 0>;
-			#io-channel-cells = <1>;
-			ti,channel0-current-microamp = <5>;
-			ti,channel3-current-microamp = <10>;
-		};
-
-		palmas_pmic {
-			compatible = "ti,palmas-pmic";
-			interrupt-parent = <&palmas>;
-			interrupts = <14 IRQ_TYPE_NONE>;
-			interrupt-names = "short-irq";
-
-			ti,ldo6-vibrator;
-
-			smps123-in-supply = <&vsys_cobra>;
-			smps45-in-supply = <&vsys_cobra>;
-			smps6-in-supply = <&vsys_cobra>;
-			smps7-in-supply = <&vsys_cobra>;
-			smps8-in-supply = <&vsys_cobra>;
-			smps9-in-supply = <&vsys_cobra>;
-			smps10_out2-in-supply = <&vsys_cobra>;
-			smps10_out1-in-supply = <&vsys_cobra>;
-			ldo1-in-supply = <&vsys_cobra>;
-			ldo2-in-supply = <&vsys_cobra>;
-			ldo3-in-supply = <&vdds_1v8_main>;
-			ldo4-in-supply = <&vdds_1v8_main>;
-			ldo5-in-supply = <&vsys_cobra>;
-			ldo6-in-supply = <&vdds_1v8_main>;
-			ldo7-in-supply = <&vsys_cobra>;
-			ldo8-in-supply = <&vsys_cobra>;
-			ldo9-in-supply = <&vmmcsd_fixed>;
-			ldoln-in-supply = <&vsys_cobra>;
-			ldousb-in-supply = <&vsys_cobra>;
-
-			regulators {
-				smps123_reg: smps123 {
-					/* VDD_OPP_MPU */
-					regulator-name = "smps123";
-					regulator-min-microvolt = < 600000>;
-					regulator-max-microvolt = <1500000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				smps45_reg: smps45 {
-					/* VDD_OPP_MM */
-					regulator-name = "smps45";
-					regulator-min-microvolt = < 600000>;
-					regulator-max-microvolt = <1310000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				smps6_reg: smps6 {
-					/* VDD_DDR3 - over VDD_SMPS6 */
-					regulator-name = "smps6";
-					regulator-min-microvolt = <1350000>;
-					regulator-max-microvolt = <1350000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				smps7_reg: smps7 {
-					/* VDDS_1v8_OMAP over VDDS_1v8_MAIN */
-					regulator-name = "smps7";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				smps8_reg: smps8 {
-					/* VDD_OPP_CORE */
-					regulator-name = "smps8";
-					regulator-min-microvolt = < 600000>;
-					regulator-max-microvolt = <1310000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				smps9_reg: smps9 {
-					/* VDDA_2v1_AUD over VDD_2v1 */
-					regulator-name = "smps9";
-					regulator-min-microvolt = <2100000>;
-					regulator-max-microvolt = <2100000>;
-					ti,smps-range = <0x80>;
-				};
-
-				smps10_out2_reg: smps10_out2 {
-					/* VBUS_5V_OTG */
-					regulator-name = "smps10_out2";
-					regulator-min-microvolt = <5000000>;
-					regulator-max-microvolt = <5000000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				smps10_out1_reg: smps10_out1 {
-					/* VBUS_5V_OTG */
-					regulator-name = "smps10_out1";
-					regulator-min-microvolt = <5000000>;
-					regulator-max-microvolt = <5000000>;
-				};
-
-				ldo1_reg: ldo1 {
-					/* VDDAPHY_CAM: vdda_csiport */
-					regulator-name = "ldo1";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-				};
-
-				ldo2_reg: ldo2 {
-					/* VCC_2V8_DISP: Does not go anywhere */
-					regulator-name = "ldo2";
-					regulator-min-microvolt = <2800000>;
-					regulator-max-microvolt = <2800000>;
-					/* Unused */
-					status = "disabled";
-				};
-
-				ldo3_reg: ldo3 {
-					/* VDDAPHY_MDM: vdda_lli */
-					regulator-name = "ldo3";
-					regulator-min-microvolt = <1500000>;
-					regulator-max-microvolt = <1500000>;
-					regulator-boot-on;
-					/* Only if Modem is used */
-					status = "disabled";
-				};
-
-				ldo4_reg: ldo4 {
-					/* VDDAPHY_DISP: vdda_dsiport/hdmi */
-					regulator-name = "ldo4";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-				};
-
-				ldo5_reg: ldo5 {
-					/* VDDA_1V8_PHY: usb/sata/hdmi.. */
-					regulator-name = "ldo5";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				ldo6_reg: ldo6 {
-					/* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */
-					regulator-name = "ldo6";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				ldo7_reg: ldo7 {
-					/* VDD_VPP: vpp1 */
-					regulator-name = "ldo7";
-					regulator-min-microvolt = <2000000>;
-					regulator-max-microvolt = <2000000>;
-					/* Only for efuse reprograming! */
-					status = "disabled";
-				};
-
-				ldo8_reg: ldo8 {
-					/* VDD_3v0: Does not go anywhere */
-					regulator-name = "ldo8";
-					regulator-min-microvolt = <3000000>;
-					regulator-max-microvolt = <3000000>;
-					regulator-boot-on;
-					/* Unused */
-					status = "disabled";
-				};
-
-				ldo9_reg: ldo9 {
-					/* VCC_DV_SDIO: vdds_sdcard */
-					regulator-name = "ldo9";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <3000000>;
-					regulator-boot-on;
-				};
-
-				ldoln_reg: ldoln {
-					/* VDDA_1v8_REF: vdds_osc/mm_l4per.. */
-					regulator-name = "ldoln";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				ldousb_reg: ldousb {
-					/* VDDA_3V_USB: VDDA_USBHS33 */
-					regulator-name = "ldousb";
-					regulator-min-microvolt = <3250000>;
-					regulator-max-microvolt = <3250000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				regen3_reg: regen3 {
-					/* REGEN3 controls LDO9 supply to card */
-					regulator-name = "regen3";
-					regulator-always-on;
-					regulator-boot-on;
-				};
-			};
-		};
-
-		palmas_power_button: palmas_power_button {
-			compatible = "ti,palmas-pwrbutton";
-			interrupt-parent = <&palmas>;
-			interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
-			wakeup-source;
-		};
-	};
-
-	twl6040: twl@4b {
-		compatible = "ti,twl6040";
-		#clock-cells = <0>;
-		reg = <0x4b>;
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&twl6040_pins>;
-
-		/* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
-		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_LOW>;
-
-		/* audpwron gpio defined in the board specific dts */
-
-		vio-supply = <&smps7_reg>;
-		v2v1-supply = <&smps9_reg>;
-		enable-active-high;
-
-		clocks = <&clk32kgaudio>, <&fref_xtal_ck>;
-		clock-names = "clk32k", "mclk";
-	};
-};
-
-&mcpdm_module {
-	/* Module on the SoC needs external clock from the PMIC */
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcpdm_pins>;
-	status = "okay";
-};
-
-&mcpdm {
-	clocks = <&twl6040>;
-	clock-names = "pdmclk";
-};
-
-&mcbsp1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcbsp1_pins>;
-	status = "okay";
-};
-
-&mcbsp2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcbsp2_pins>;
-	status = "okay";
-};
-
-&usbhshost {
-	port2-mode = "ehci-hsic";
-	port3-mode = "ehci-hsic";
-};
-
-&usbhsehci {
-	phys = <0 &hsusb2_phy &hsusb3_phy>;
-};
-
-&usb3 {
-	extcon = <&extcon_usb3>;
-	vbus-supply = <&smps10_out1_reg>;
-};
-
-&dwc3 {
-	extcon = <&extcon_usb3>;
-	dr_mode = "otg";
-};
-
-&mcspi1 {
-
-};
-
-&mcspi2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcspi2_pins>;
-};
-
-&mcspi3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcspi3_pins>;
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-};
-
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart3_pins>;
-	interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
-			      <&omap5_pmx_core 0x19c>;
-};
-
-&uart5 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart5_pins>;
-};
-
-&cpu0 {
-	cpu0-supply = <&smps123_reg>;
-};
-
-&dss {
-	status = "okay";
-};
-
-&hdmi {
-	status = "okay";
-
-	/* vdda-supply populated in board specific dts file */
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&dss_hdmi_pins>;
-
-	port {
-		hdmi_out: endpoint {
-			remote-endpoint = <&tpd12s015_in>;
-		};
-	};
-};
diff --git a/arch/arm/dts/omap5-core-thermal.dtsi b/arch/arm/dts/omap5-core-thermal.dtsi
index de8a3d4..e0d8e39 100644
--- a/arch/arm/dts/omap5-core-thermal.dtsi
+++ b/arch/arm/dts/omap5-core-thermal.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP543x SoC CORE thermal
  *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <dt-bindings/thermal/thermal.h>
diff --git a/arch/arm/dts/omap5-gpu-thermal.dtsi b/arch/arm/dts/omap5-gpu-thermal.dtsi
index bc3090f..1b4b7d9 100644
--- a/arch/arm/dts/omap5-gpu-thermal.dtsi
+++ b/arch/arm/dts/omap5-gpu-thermal.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP543x SoC GPU thermal
  *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <dt-bindings/thermal/thermal.h>
diff --git a/arch/arm/dts/omap5-l4-abe.dtsi b/arch/arm/dts/omap5-l4-abe.dtsi
deleted file mode 100644
index f73eea0..0000000
--- a/arch/arm/dts/omap5-l4-abe.dtsi
+++ /dev/null
@@ -1,449 +0,0 @@
-&l4_abe {						/* 0x40100000 */
-	compatible = "ti,omap5-l4-abe", "simple-bus";
-	reg = <0x40100000 0x400>,
-	      <0x40100400 0x400>;
-	reg-names = "la", "ap";
-	#address-cells = <1>;
-	#size-cells = <1>;
-	ranges = <0x00000000 0x40100000 0x100000>,	/* segment 0 */
-		 <0x49000000 0x49000000 0x100000>;
-	segment@0 {					/* 0x40100000 */
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges =
-			 /* CPU to L4 ABE mapping */
-			 <0x00000000 0x00000000 0x000400>,	/* ap 0 */
-			 <0x00000400 0x00000400 0x000400>,	/* ap 1 */
-			 <0x00022000 0x00022000 0x001000>,	/* ap 2 */
-			 <0x00023000 0x00023000 0x001000>,	/* ap 3 */
-			 <0x00024000 0x00024000 0x001000>,	/* ap 4 */
-			 <0x00025000 0x00025000 0x001000>,	/* ap 5 */
-			 <0x00026000 0x00026000 0x001000>,	/* ap 6 */
-			 <0x00027000 0x00027000 0x001000>,	/* ap 7 */
-			 <0x00028000 0x00028000 0x001000>,	/* ap 8 */
-			 <0x00029000 0x00029000 0x001000>,	/* ap 9 */
-			 <0x0002a000 0x0002a000 0x001000>,	/* ap 10 */
-			 <0x0002b000 0x0002b000 0x001000>,	/* ap 11 */
-			 <0x0002e000 0x0002e000 0x001000>,	/* ap 12 */
-			 <0x0002f000 0x0002f000 0x001000>,	/* ap 13 */
-			 <0x00030000 0x00030000 0x001000>,	/* ap 14 */
-			 <0x00031000 0x00031000 0x001000>,	/* ap 15 */
-			 <0x00032000 0x00032000 0x001000>,	/* ap 16 */
-			 <0x00033000 0x00033000 0x001000>,	/* ap 17 */
-			 <0x00038000 0x00038000 0x001000>,	/* ap 18 */
-			 <0x00039000 0x00039000 0x001000>,	/* ap 19 */
-			 <0x0003a000 0x0003a000 0x001000>,	/* ap 20 */
-			 <0x0003b000 0x0003b000 0x001000>,	/* ap 21 */
-			 <0x0003c000 0x0003c000 0x001000>,	/* ap 22 */
-			 <0x0003d000 0x0003d000 0x001000>,	/* ap 23 */
-			 <0x0003e000 0x0003e000 0x001000>,	/* ap 24 */
-			 <0x0003f000 0x0003f000 0x001000>,	/* ap 25 */
-			 <0x00080000 0x00080000 0x010000>,	/* ap 26 */
-			 <0x00080000 0x00080000 0x001000>,	/* ap 27 */
-			 <0x000a0000 0x000a0000 0x010000>,	/* ap 28 */
-			 <0x000a0000 0x000a0000 0x001000>,	/* ap 29 */
-			 <0x000c0000 0x000c0000 0x010000>,	/* ap 30 */
-			 <0x000c0000 0x000c0000 0x001000>,	/* ap 31 */
-			 <0x000f1000 0x000f1000 0x001000>,	/* ap 32 */
-			 <0x000f2000 0x000f2000 0x001000>,	/* ap 33 */
-
-			 /* L3 to L4 ABE mapping */
-			 <0x49000000 0x49000000 0x000400>,	/* ap 0 */
-			 <0x49000400 0x49000400 0x000400>,	/* ap 1 */
-			 <0x49022000 0x49022000 0x001000>,	/* ap 2 */
-			 <0x49023000 0x49023000 0x001000>,	/* ap 3 */
-			 <0x49024000 0x49024000 0x001000>,	/* ap 4 */
-			 <0x49025000 0x49025000 0x001000>,	/* ap 5 */
-			 <0x49026000 0x49026000 0x001000>,	/* ap 6 */
-			 <0x49027000 0x49027000 0x001000>,	/* ap 7 */
-			 <0x49028000 0x49028000 0x001000>,	/* ap 8 */
-			 <0x49029000 0x49029000 0x001000>,	/* ap 9 */
-			 <0x4902a000 0x4902a000 0x001000>,	/* ap 10 */
-			 <0x4902b000 0x4902b000 0x001000>,	/* ap 11 */
-			 <0x4902e000 0x4902e000 0x001000>,	/* ap 12 */
-			 <0x4902f000 0x4902f000 0x001000>,	/* ap 13 */
-			 <0x49030000 0x49030000 0x001000>,	/* ap 14 */
-			 <0x49031000 0x49031000 0x001000>,	/* ap 15 */
-			 <0x49032000 0x49032000 0x001000>,	/* ap 16 */
-			 <0x49033000 0x49033000 0x001000>,	/* ap 17 */
-			 <0x49038000 0x49038000 0x001000>,	/* ap 18 */
-			 <0x49039000 0x49039000 0x001000>,	/* ap 19 */
-			 <0x4903a000 0x4903a000 0x001000>,	/* ap 20 */
-			 <0x4903b000 0x4903b000 0x001000>,	/* ap 21 */
-			 <0x4903c000 0x4903c000 0x001000>,	/* ap 22 */
-			 <0x4903d000 0x4903d000 0x001000>,	/* ap 23 */
-			 <0x4903e000 0x4903e000 0x001000>,	/* ap 24 */
-			 <0x4903f000 0x4903f000 0x001000>,	/* ap 25 */
-			 <0x49080000 0x49080000 0x010000>,	/* ap 26 */
-			 <0x49080000 0x49080000 0x001000>,	/* ap 27 */
-			 <0x490a0000 0x490a0000 0x010000>,	/* ap 28 */
-			 <0x490a0000 0x490a0000 0x001000>,	/* ap 29 */
-			 <0x490c0000 0x490c0000 0x010000>,	/* ap 30 */
-			 <0x490c0000 0x490c0000 0x001000>,	/* ap 31 */
-			 <0x490f1000 0x490f1000 0x001000>,	/* ap 32 */
-			 <0x490f2000 0x490f2000 0x001000>;	/* ap 33 */
-
-		target-module@22000 {			/* 0x40122000, ap 2 02.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x2208c 0x4>;
-			reg-names = "sysc";
-			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
-					 SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>;
-			/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
-			clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x22000 0x1000>,
-				 <0x49022000 0x49022000 0x1000>;
-
-			mcbsp1: mcbsp@0 {
-				compatible = "ti,omap4-mcbsp";
-				reg = <0x0 0xff>, /* MPU private access */
-				      <0x49022000 0xff>; /* L3 Interconnect */
-				reg-names = "mpu", "dma";
-				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-names = "common";
-				ti,buffer-size = <128>;
-				dmas = <&sdma 33>,
-				       <&sdma 34>;
-				dma-names = "tx", "rx";
-				status = "disabled";
-			};
-		};
-
-		target-module@24000 {			/* 0x40124000, ap 4 04.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x2408c 0x4>;
-			reg-names = "sysc";
-			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
-					 SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>;
-			/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
-			clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x24000 0x1000>,
-				 <0x49024000 0x49024000 0x1000>;
-
-			mcbsp2: mcbsp@0 {
-				compatible = "ti,omap4-mcbsp";
-				reg = <0x0 0xff>, /* MPU private access */
-				      <0x49024000 0xff>; /* L3 Interconnect */
-				reg-names = "mpu", "dma";
-				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-names = "common";
-				ti,buffer-size = <128>;
-				dmas = <&sdma 17>,
-				       <&sdma 18>;
-				dma-names = "tx", "rx";
-				status = "disabled";
-			};
-		};
-
-		target-module@26000 {			/* 0x40126000, ap 6 06.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x2608c 0x4>;
-			reg-names = "sysc";
-			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
-					 SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>;
-			/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
-			clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x26000 0x1000>,
-				 <0x49026000 0x49026000 0x1000>;
-
-			mcbsp3: mcbsp@0 {
-				compatible = "ti,omap4-mcbsp";
-				reg = <0x0 0xff>, /* MPU private access */
-				      <0x49026000 0xff>; /* L3 Interconnect */
-				reg-names = "mpu", "dma";
-				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-names = "common";
-				ti,buffer-size = <128>;
-				dmas = <&sdma 19>,
-				       <&sdma 20>;
-				dma-names = "tx", "rx";
-				status = "disabled";
-			};
-		};
-
-		target-module@28000 {			/* 0x40128000, ap 8 08.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x28000 0x1000>,
-				 <0x49028000 0x49028000 0x1000>;
-		};
-
-		target-module@2a000 {			/* 0x4012a000, ap 10 0a.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x2a000 0x1000>,
-				 <0x4902a000 0x4902a000 0x1000>;
-		};
-
-		target-module@2e000 {			/* 0x4012e000, ap 12 0c.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0x2e000 0x4>,
-			      <0x2e010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
-			clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x2e000 0x1000>,
-				 <0x4902e000 0x4902e000 0x1000>;
-
-			dmic: dmic@0 {
-				compatible = "ti,omap4-dmic";
-				reg = <0x0 0x7f>, /* MPU private access */
-				      <0x4902e000 0x7f>; /* L3 Interconnect */
-				reg-names = "mpu", "dma";
-				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&sdma 67>;
-				dma-names = "up_link";
-				status = "disabled";
-			};
-		};
-
-		target-module@30000 {			/* 0x40130000, ap 14 0e.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x30000 0x1000>,
-				 <0x49030000 0x49030000 0x1000>;
-		};
-
-		mcpdm_module: target-module@32000 {	/* 0x40132000, ap 16 10.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0x32000 0x4>,
-			      <0x32010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
-			clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x32000 0x1000>,
-				 <0x49032000 0x49032000 0x1000>;
-
-			/* Must be only enabled for boards with pdmclk wired */
-			status = "disabled";
-
-			mcpdm: mcpdm@0 {
-				compatible = "ti,omap4-mcpdm";
-				reg = <0x0 0x7f>, /* MPU private access */
-				      <0x49032000 0x7f>; /* L3 Interconnect */
-				reg-names = "mpu", "dma";
-				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&sdma 65>,
-				       <&sdma 66>;
-				dma-names = "up_link", "dn_link";
-			};
-		};
-
-		target-module@38000 {			/* 0x40138000, ap 18 12.0 */
-			compatible = "ti,sysc-omap4-timer", "ti,sysc";
-			reg = <0x38000 0x4>,
-			      <0x38010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
-			clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x38000 0x1000>,
-				 <0x49038000 0x49038000 0x1000>;
-
-			timer5: timer@0 {
-				compatible = "ti,omap5430-timer";
-				reg = <0x0 0x80>,
-				      <0x49038000 0x80>;
-				clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>;
-				clock-names = "fck";
-				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
-				ti,timer-dsp;
-				ti,timer-pwm;
-			};
-		};
-
-		target-module@3a000 {			/* 0x4013a000, ap 20 14.0 */
-			compatible = "ti,sysc-omap4-timer", "ti,sysc";
-			reg = <0x3a000 0x4>,
-			      <0x3a010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
-			clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x3a000 0x1000>,
-				 <0x4903a000 0x4903a000 0x1000>;
-
-			timer6: timer@0 {
-				compatible = "ti,omap5430-timer";
-				reg = <0x0 0x80>,
-				      <0x4903a000 0x80>;
-				clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>;
-				clock-names = "fck";
-				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
-				ti,timer-dsp;
-				ti,timer-pwm;
-			};
-		};
-
-		target-module@3c000 {			/* 0x4013c000, ap 22 16.0 */
-			compatible = "ti,sysc-omap4-timer", "ti,sysc";
-			reg = <0x3c000 0x4>,
-			      <0x3c010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
-			clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x3c000 0x1000>,
-				 <0x4903c000 0x4903c000 0x1000>;
-
-			timer7: timer@0 {
-				compatible = "ti,omap5430-timer";
-				reg = <0x0 0x80>,
-				      <0x4903c000 0x80>;
-				clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>;
-				clock-names = "fck";
-				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
-				ti,timer-dsp;
-			};
-		};
-
-		target-module@3e000 {			/* 0x4013e000, ap 24 18.0 */
-			compatible = "ti,sysc-omap4-timer", "ti,sysc";
-			reg = <0x3e000 0x4>,
-			      <0x3e010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
-			clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x3e000 0x1000>,
-				 <0x4903e000 0x4903e000 0x1000>;
-
-			timer8: timer@0 {
-				compatible = "ti,omap5430-timer";
-				reg = <0x0 0x80>,
-				      <0x4903e000 0x80>;
-				clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>;
-				clock-names = "fck";
-				interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
-				ti,timer-dsp;
-				ti,timer-pwm;
-			};
-		};
-
-		target-module@80000 {			/* 0x40180000, ap 26 1a.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x80000 0x10000>,
-				 <0x49080000 0x49080000 0x10000>;
-		};
-
-		target-module@a0000 {			/* 0x401a0000, ap 28 1c.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0xa0000 0x10000>,
-				 <0x490a0000 0x490a0000 0x10000>;
-		};
-
-		target-module@c0000 {			/* 0x401c0000, ap 30 1e.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0xc0000 0x10000>,
-				 <0x490c0000 0x490c0000 0x10000>;
-		};
-
-		target-module@f1000 {			/* 0x401f1000, ap 32 20.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0xf1000 0x4>,
-			      <0xf1010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-midle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>;
-			/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
-			clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0xf1000 0x1000>,
-				 <0x490f1000 0x490f1000 0x1000>;
-		};
-	};
-};
diff --git a/arch/arm/dts/omap5-l4.dtsi b/arch/arm/dts/omap5-l4.dtsi
deleted file mode 100644
index 8582016..0000000
--- a/arch/arm/dts/omap5-l4.dtsi
+++ /dev/null
@@ -1,2437 +0,0 @@
-&l4_cfg {						/* 0x4a000000 */
-	compatible = "ti,omap5-l4-cfg", "simple-bus";
-	reg = <0x4a000000 0x800>,
-	      <0x4a000800 0x800>,
-	      <0x4a001000 0x1000>;
-	reg-names = "ap", "la", "ia0";
-	#address-cells = <1>;
-	#size-cells = <1>;
-	ranges = <0x00000000 0x4a000000 0x080000>,	/* segment 0 */
-		 <0x00080000 0x4a080000 0x080000>,	/* segment 1 */
-		 <0x00100000 0x4a100000 0x080000>,	/* segment 2 */
-		 <0x00180000 0x4a180000 0x080000>,	/* segment 3 */
-		 <0x00200000 0x4a200000 0x080000>,	/* segment 4 */
-		 <0x00280000 0x4a280000 0x080000>,	/* segment 5 */
-		 <0x00300000 0x4a300000 0x080000>;	/* segment 6 */
-
-	segment@0 {					/* 0x4a000000 */
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x00000000 0x00000000 0x000800>,	/* ap 0 */
-			 <0x00001000 0x00001000 0x001000>,	/* ap 1 */
-			 <0x00000800 0x00000800 0x000800>,	/* ap 2 */
-			 <0x00002000 0x00002000 0x001000>,	/* ap 3 */
-			 <0x00003000 0x00003000 0x001000>,	/* ap 4 */
-			 <0x00004000 0x00004000 0x001000>,	/* ap 5 */
-			 <0x00005000 0x00005000 0x001000>,	/* ap 6 */
-			 <0x00056000 0x00056000 0x001000>,	/* ap 7 */
-			 <0x00057000 0x00057000 0x001000>,	/* ap 8 */
-			 <0x0005c000 0x0005c000 0x001000>,	/* ap 9 */
-			 <0x00058000 0x00058000 0x001000>,	/* ap 10 */
-			 <0x00062000 0x00062000 0x001000>,	/* ap 11 */
-			 <0x00063000 0x00063000 0x001000>,	/* ap 12 */
-			 <0x00008000 0x00008000 0x002000>,	/* ap 21 */
-			 <0x0000a000 0x0000a000 0x001000>,	/* ap 22 */
-			 <0x00066000 0x00066000 0x001000>,	/* ap 23 */
-			 <0x00067000 0x00067000 0x001000>,	/* ap 24 */
-			 <0x0005e000 0x0005e000 0x002000>,	/* ap 69 */
-			 <0x00060000 0x00060000 0x001000>,	/* ap 70 */
-			 <0x00064000 0x00064000 0x001000>,	/* ap 71 */
-			 <0x00065000 0x00065000 0x001000>,	/* ap 72 */
-			 <0x0005a000 0x0005a000 0x001000>,	/* ap 77 */
-			 <0x0005b000 0x0005b000 0x001000>,	/* ap 78 */
-			 <0x00070000 0x00070000 0x004000>,	/* ap 79 */
-			 <0x00074000 0x00074000 0x001000>,	/* ap 80 */
-			 <0x00075000 0x00075000 0x001000>,	/* ap 81 */
-			 <0x00076000 0x00076000 0x001000>,	/* ap 82 */
-			 <0x00020000 0x00020000 0x020000>,	/* ap 109 */
-			 <0x00040000 0x00040000 0x001000>,	/* ap 110 */
-			 <0x00059000 0x00059000 0x001000>;	/* ap 111 */
-
-		target-module@2000 {			/* 0x4a002000, ap 3 44.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0x2000 0x4>;
-			reg-names = "rev";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x2000 0x1000>;
-
-			scm_core: scm@0 {
-				compatible = "ti,omap5-scm-core", "simple-bus";
-				reg = <0x0 0x1000>;
-				#address-cells = <1>;
-				#size-cells = <1>;
-				ranges = <0 0 0x800>;
-
-				scm_conf: scm_conf@0 {
-					compatible = "syscon";
-					reg = <0x0 0x800>;
-					#address-cells = <1>;
-					#size-cells = <1>;
-				};
-			};
-
-			scm_padconf_core: scm@800 {
-				compatible = "ti,omap5-scm-padconf-core",
-					     "simple-bus";
-				#address-cells = <1>;
-				#size-cells = <1>;
-				ranges = <0 0x800 0x800>;
-
-				omap5_pmx_core: pinmux@40 {
-					compatible = "ti,omap5-padconf",
-						     "pinctrl-single";
-					reg = <0x40 0x01b6>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-					#pinctrl-cells = <1>;
-					#interrupt-cells = <1>;
-					interrupt-controller;
-					pinctrl-single,register-width = <16>;
-					pinctrl-single,function-mask = <0x7fff>;
-				};
-
-				omap5_padconf_global: omap5_padconf_global@5a0 {
-					compatible = "syscon",
-						     "simple-bus";
-					reg = <0x5a0 0xec>;
-					#address-cells = <1>;
-					#size-cells = <1>;
-					ranges = <0 0x5a0 0xec>;
-
-					pbias_regulator: pbias_regulator@60 {
-						compatible = "ti,pbias-omap5", "ti,pbias-omap";
-						reg = <0x60 0x4>;
-						syscon = <&omap5_padconf_global>;
-						pbias_mmc_reg: pbias_mmc_omap5 {
-							regulator-name = "pbias_mmc_omap5";
-							regulator-min-microvolt = <1800000>;
-							regulator-max-microvolt = <3300000>;
-						};
-					};
-				};
-			};
-		};
-
-		target-module@4000 {			/* 0x4a004000, ap 5 5c.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0x4000 0x4>;
-			reg-names = "rev";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x4000 0x1000>;
-
-			cm_core_aon: cm_core_aon@0 {
-				compatible = "ti,omap5-cm-core-aon",
-					     "simple-bus";
-				reg = <0x0 0x2000>;
-				#address-cells = <1>;
-				#size-cells = <1>;
-				ranges = <0 0 0x1000>;
-
-				cm_core_aon_clocks: clocks {
-					#address-cells = <1>;
-					#size-cells = <0>;
-				};
-
-				cm_core_aon_clockdomains: clockdomains {
-				};
-			};
-		};
-
-		target-module@8000 {			/* 0x4a008000, ap 21 4c.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0x8000 0x4>;
-			reg-names = "rev";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x8000 0x2000>;
-
-			cm_core: cm_core@0 {
-				compatible = "ti,omap5-cm-core", "simple-bus";
-				reg = <0x0 0x2000>;
-				#address-cells = <1>;
-				#size-cells = <1>;
-				ranges = <0 0 0x2000>;
-
-				cm_core_clocks: clocks {
-					#address-cells = <1>;
-					#size-cells = <0>;
-				};
-
-				cm_core_clockdomains: clockdomains {
-				};
-			};
-		};
-
-		target-module@20000 {			/* 0x4a020000, ap 109 08.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			ti,hwmods = "usb_otg_ss";
-			reg = <0x20000 0x4>,
-			      <0x20010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
-			ti,sysc-midle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
-			clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x20000 0x20000>;
-
-			usb3: omap_dwc3@0 {
-				compatible = "ti,dwc3";
-				reg = <0x0 0x10000>;
-				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-				#address-cells = <1>;
-				#size-cells = <1>;
-				utmi-mode = <2>;
-				ranges = <0 0 0x20000>;
-				dwc3: dwc3@10000 {
-					compatible = "snps,dwc3";
-					reg = <0x10000 0x10000>;
-					interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
-						     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
-						     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-					interrupt-names = "peripheral",
-							  "host",
-							  "otg";
-					phys = <&usb2_phy>, <&usb3_phy>;
-					phy-names = "usb2-phy", "usb3-phy";
-					dr_mode = "peripheral";
-				};
-			};
-		};
-
-		target-module@56000 {			/* 0x4a056000, ap 7 02.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x56000 0x4>,
-			      <0x5602c 0x4>,
-			      <0x56028 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
-					 SYSC_OMAP2_EMUFREE |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-midle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, dma_clkdm */
-			clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x56000 0x1000>;
-
-			sdma: dma-controller@0 {
-				compatible = "ti,omap4430-sdma", "ti,omap-sdma";
-				reg = <0x0 0x1000>;
-				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-				#dma-cells = <1>;
-				dma-channels = <32>;
-				dma-requests = <127>;
-			};
-		};
-
-		target-module@58000 {			/* 0x4a058000, ap 10 06.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x00000000 0x00058000 0x00001000>,
-				 <0x00001000 0x00059000 0x00001000>,
-				 <0x00002000 0x0005a000 0x00001000>,
-				 <0x00003000 0x0005b000 0x00001000>;
-		};
-
-		target-module@5e000 {			/* 0x4a05e000, ap 69 2a.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x5e000 0x2000>;
-		};
-
-		target-module@62000 {			/* 0x4a062000, ap 11 0e.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			ti,hwmods = "usb_tll_hs";
-			reg = <0x62000 0x4>,
-			      <0x62010 0x4>,
-			      <0x62014 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
-					 SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
-			clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x62000 0x1000>;
-
-			usbhstll: usbhstll@0 {
-				compatible = "ti,usbhs-tll";
-				reg = <0x0 0x1000>;
-				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-			};
-		};
-
-		target-module@64000 {			/* 0x4a064000, ap 71 1e.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			ti,hwmods = "usb_host_hs";
-			reg = <0x64000 0x4>,
-			      <0x64010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
-			ti,sysc-midle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
-			clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x64000 0x1000>;
-
-			usbhshost: usbhshost@0 {
-				compatible = "ti,usbhs-host";
-				reg = <0x0 0x800>;
-				#address-cells = <1>;
-				#size-cells = <1>;
-				ranges = <0 0 0x1000>;
-				clocks = <&l3init_60m_fclk>,
-					 <&xclk60mhsp1_ck>,
-					 <&xclk60mhsp2_ck>;
-				clock-names = "refclk_60m_int",
-					      "refclk_60m_ext_p1",
-					      "refclk_60m_ext_p2";
-
-				usbhsohci: ohci@800 {
-					compatible = "ti,ohci-omap3";
-					reg = <0x800 0x400>;
-					interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-					remote-wakeup-connected;
-				};
-
-				usbhsehci: ehci@c00 {
-					compatible = "ti,ehci-omap";
-					reg = <0xc00 0x400>;
-					interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-				};
-			};
-		};
-
-		target-module@66000 {			/* 0x4a066000, ap 23 0a.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x66000 0x4>,
-			      <0x66010 0x4>,
-			      <0x66014 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */
-			clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
-			clock-names = "fck";
-			resets = <&prm_dsp 1>;
-			reset-names = "rstctrl";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x66000 0x1000>;
-
-			mmu_dsp: mmu@0 {
-				compatible = "ti,omap4-iommu";
-				reg = <0x0 0x100>;
-				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-				#iommu-cells = <0>;
-			};
-		};
-
-		target-module@70000 {			/* 0x4a070000, ap 79 2e.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x70000 0x4000>;
-		};
-
-		target-module@75000 {			/* 0x4a075000, ap 81 32.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x75000 0x1000>;
-		};
-	};
-
-	segment@80000 {					/* 0x4a080000 */
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x00059000 0x000d9000 0x001000>,	/* ap 13 */
-			 <0x0005a000 0x000da000 0x001000>,	/* ap 14 */
-			 <0x0005b000 0x000db000 0x001000>,	/* ap 15 */
-			 <0x0005c000 0x000dc000 0x001000>,	/* ap 16 */
-			 <0x0005d000 0x000dd000 0x001000>,	/* ap 17 */
-			 <0x0005e000 0x000de000 0x001000>,	/* ap 18 */
-			 <0x00060000 0x000e0000 0x001000>,	/* ap 19 */
-			 <0x00061000 0x000e1000 0x001000>,	/* ap 20 */
-			 <0x00074000 0x000f4000 0x001000>,	/* ap 25 */
-			 <0x00075000 0x000f5000 0x001000>,	/* ap 26 */
-			 <0x00076000 0x000f6000 0x001000>,	/* ap 27 */
-			 <0x00077000 0x000f7000 0x001000>,	/* ap 28 */
-			 <0x00036000 0x000b6000 0x001000>,	/* ap 65 */
-			 <0x00037000 0x000b7000 0x001000>,	/* ap 66 */
-			 <0x0004d000 0x000cd000 0x001000>,	/* ap 67 */
-			 <0x0004e000 0x000ce000 0x001000>,	/* ap 68 */
-			 <0x00000000 0x00080000 0x004000>,	/* ap 83 */
-			 <0x00004000 0x00084000 0x001000>,	/* ap 84 */
-			 <0x00005000 0x00085000 0x001000>,	/* ap 85 */
-			 <0x00006000 0x00086000 0x001000>,	/* ap 86 */
-			 <0x00007000 0x00087000 0x001000>,	/* ap 87 */
-			 <0x00008000 0x00088000 0x001000>,	/* ap 88 */
-			 <0x00010000 0x00090000 0x004000>,	/* ap 89 */
-			 <0x00014000 0x00094000 0x001000>,	/* ap 90 */
-			 <0x00015000 0x00095000 0x001000>,	/* ap 91 */
-			 <0x00016000 0x00096000 0x001000>,	/* ap 92 */
-			 <0x00017000 0x00097000 0x001000>,	/* ap 93 */
-			 <0x00018000 0x00098000 0x001000>,	/* ap 94 */
-			 <0x00020000 0x000a0000 0x004000>,	/* ap 95 */
-			 <0x00024000 0x000a4000 0x001000>,	/* ap 96 */
-			 <0x00025000 0x000a5000 0x001000>,	/* ap 97 */
-			 <0x00026000 0x000a6000 0x001000>,	/* ap 98 */
-			 <0x00027000 0x000a7000 0x001000>,	/* ap 99 */
-			 <0x00028000 0x000a8000 0x001000>;	/* ap 100 */
-
-		target-module@0 {			/* 0x4a080000, ap 83 28.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x0 0x4>,
-			      <0x10 0x4>,
-			      <0x14 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
-			clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x00000000 0x00000000 0x00004000>,
-				 <0x00004000 0x00004000 0x00001000>,
-				 <0x00005000 0x00005000 0x00001000>,
-				 <0x00006000 0x00006000 0x00001000>,
-				 <0x00007000 0x00007000 0x00001000>;
-
-			ocp2scp@0 {
-				compatible = "ti,omap-ocp2scp";
-				#address-cells = <1>;
-				#size-cells = <1>;
-				reg = <0 0x20>;
-			};
-
-			usb2_phy: usb2phy@4000 {
-				compatible = "ti,omap-usb2";
-				reg = <0x4000 0x7c>;
-				syscon-phy-power = <&scm_conf 0x300>;
-				clocks = <&usb_phy_cm_clk32k>,
-				<&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
-				clock-names = "wkupclk", "refclk";
-				#phy-cells = <0>;
-			};
-
-			usb3_phy: usb3phy@4400 {
-				compatible = "ti,omap-usb3";
-				reg = <0x4400 0x80>,
-				<0x4800 0x64>,
-				<0x4c00 0x40>;
-				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
-				syscon-phy-power = <&scm_conf 0x370>;
-				clocks = <&usb_phy_cm_clk32k>,
-				<&sys_clkin>,
-				<&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
-				clock-names =	"wkupclk",
-				"sysclk",
-				"refclk";
-				#phy-cells = <0>;
-			};
-		};
-
-		target-module@10000 {			/* 0x4a090000, ap 89 36.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x10000 0x4>,
-			      <0x10010 0x4>,
-			      <0x10014 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
-			clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x00000000 0x00010000 0x00004000>,
-				 <0x00004000 0x00014000 0x00001000>,
-				 <0x00005000 0x00015000 0x00001000>,
-				 <0x00006000 0x00016000 0x00001000>,
-				 <0x00007000 0x00017000 0x00001000>;
-
-				ocp2scp@0 {
-					compatible = "ti,omap-ocp2scp";
-					#address-cells = <1>;
-					#size-cells = <1>;
-					reg = <0x0 0x20>;
-				};
-
-				sata_phy: phy@6000 {
-					compatible = "ti,phy-pipe3-sata";
-					reg = <0x6000 0x80>, /* phy_rx */
-					      <0x6400 0x64>, /* phy_tx */
-					      <0x6800 0x40>; /* pll_ctrl */
-					reg-names = "phy_rx", "phy_tx", "pll_ctrl";
-					syscon-phy-power = <&scm_conf 0x374>;
-					clocks = <&sys_clkin>,
-						 <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
-					clock-names = "sysclk", "refclk";
-					#phy-cells = <0>;
-				};
-		};
-
-		target-module@20000 {			/* 0x4a0a0000, ap 95 50.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x00000000 0x00020000 0x00004000>,
-				 <0x00004000 0x00024000 0x00001000>,
-				 <0x00005000 0x00025000 0x00001000>,
-				 <0x00006000 0x00026000 0x00001000>,
-				 <0x00007000 0x00027000 0x00001000>;
-		};
-
-		target-module@36000 {			/* 0x4a0b6000, ap 65 6c.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x36000 0x1000>;
-		};
-
-		target-module@4d000 {			/* 0x4a0cd000, ap 67 64.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x4d000 0x1000>;
-		};
-
-		target-module@59000 {			/* 0x4a0d9000, ap 13 20.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x59000 0x1000>;
-		};
-
-		target-module@5b000 {			/* 0x4a0db000, ap 15 10.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x5b000 0x1000>;
-		};
-
-		target-module@5d000 {			/* 0x4a0dd000, ap 17 18.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x5d000 0x1000>;
-		};
-
-		target-module@60000 {			/* 0x4a0e0000, ap 19 54.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x60000 0x1000>;
-		};
-
-		target-module@74000 {			/* 0x4a0f4000, ap 25 04.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0x74000 0x4>,
-			      <0x74010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>;
-			/* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */
-			clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x74000 0x1000>;
-
-			mailbox: mailbox@0 {
-				compatible = "ti,omap4-mailbox";
-				reg = <0x0 0x200>;
-				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-				#mbox-cells = <1>;
-				ti,mbox-num-users = <3>;
-				ti,mbox-num-fifos = <8>;
-				mbox_ipu: mbox_ipu {
-					ti,mbox-tx = <0 0 0>;
-					ti,mbox-rx = <1 0 0>;
-				};
-				mbox_dsp: mbox_dsp {
-					ti,mbox-tx = <3 0 0>;
-					ti,mbox-rx = <2 0 0>;
-				};
-			};
-		};
-
-		target-module@76000 {			/* 0x4a0f6000, ap 27 0c.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x76000 0x4>,
-			      <0x76010 0x4>,
-			      <0x76014 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
-					 SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */
-			clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x76000 0x1000>;
-
-			hwspinlock: spinlock@0 {
-				compatible = "ti,omap4-hwspinlock";
-				reg = <0x0 0x1000>;
-				#hwlock-cells = <1>;
-			};
-		};
-	};
-
-	segment@100000 {					/* 0x4a100000 */
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x00002000 0x00102000 0x001000>,	/* ap 59 */
-			 <0x00003000 0x00103000 0x001000>,	/* ap 60 */
-			 <0x00008000 0x00108000 0x001000>,	/* ap 61 */
-			 <0x00009000 0x00109000 0x001000>,	/* ap 62 */
-			 <0x0000a000 0x0010a000 0x001000>,	/* ap 63 */
-			 <0x0000b000 0x0010b000 0x001000>,	/* ap 64 */
-			 <0x00040000 0x00140000 0x010000>,	/* ap 101 */
-			 <0x00050000 0x00150000 0x001000>;	/* ap 102 */
-
-		target-module@2000 {			/* 0x4a102000, ap 59 2c.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x2000 0x1000>;
-		};
-
-		target-module@8000 {			/* 0x4a108000, ap 61 26.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x8000 0x1000>;
-		};
-
-		target-module@a000 {			/* 0x4a10a000, ap 63 22.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0xa000 0x1000>;
-		};
-
-		target-module@40000 {			/* 0x4a140000, ap 101 16.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x40000 0x10000>;
-		};
-	};
-
-	segment@180000 {					/* 0x4a180000 */
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-
-	segment@200000 {					/* 0x4a200000 */
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0001e000 0x0021e000 0x001000>,	/* ap 29 */
-			 <0x0001f000 0x0021f000 0x001000>,	/* ap 30 */
-			 <0x0000a000 0x0020a000 0x001000>,	/* ap 31 */
-			 <0x0000b000 0x0020b000 0x001000>,	/* ap 32 */
-			 <0x00006000 0x00206000 0x001000>,	/* ap 33 */
-			 <0x00007000 0x00207000 0x001000>,	/* ap 34 */
-			 <0x00004000 0x00204000 0x001000>,	/* ap 35 */
-			 <0x00005000 0x00205000 0x001000>,	/* ap 36 */
-			 <0x00012000 0x00212000 0x001000>,	/* ap 37 */
-			 <0x00013000 0x00213000 0x001000>,	/* ap 38 */
-			 <0x0000c000 0x0020c000 0x001000>,	/* ap 39 */
-			 <0x0000d000 0x0020d000 0x001000>,	/* ap 40 */
-			 <0x00010000 0x00210000 0x001000>,	/* ap 41 */
-			 <0x00011000 0x00211000 0x001000>,	/* ap 42 */
-			 <0x00016000 0x00216000 0x001000>,	/* ap 43 */
-			 <0x00017000 0x00217000 0x001000>,	/* ap 44 */
-			 <0x00014000 0x00214000 0x001000>,	/* ap 45 */
-			 <0x00015000 0x00215000 0x001000>,	/* ap 46 */
-			 <0x00018000 0x00218000 0x001000>,	/* ap 47 */
-			 <0x00019000 0x00219000 0x001000>,	/* ap 48 */
-			 <0x00020000 0x00220000 0x001000>,	/* ap 49 */
-			 <0x00021000 0x00221000 0x001000>,	/* ap 50 */
-			 <0x00026000 0x00226000 0x001000>,	/* ap 51 */
-			 <0x00027000 0x00227000 0x001000>,	/* ap 52 */
-			 <0x00028000 0x00228000 0x001000>,	/* ap 53 */
-			 <0x00029000 0x00229000 0x001000>,	/* ap 54 */
-			 <0x0002a000 0x0022a000 0x001000>,	/* ap 55 */
-			 <0x0002b000 0x0022b000 0x001000>,	/* ap 56 */
-			 <0x0001c000 0x0021c000 0x001000>,	/* ap 57 */
-			 <0x0001d000 0x0021d000 0x001000>,	/* ap 58 */
-			 <0x0001a000 0x0021a000 0x001000>,	/* ap 73 */
-			 <0x0001b000 0x0021b000 0x001000>,	/* ap 74 */
-			 <0x00024000 0x00224000 0x001000>,	/* ap 75 */
-			 <0x00025000 0x00225000 0x001000>,	/* ap 76 */
-			 <0x00002000 0x00202000 0x001000>,	/* ap 103 */
-			 <0x00003000 0x00203000 0x001000>,	/* ap 104 */
-			 <0x00008000 0x00208000 0x001000>,	/* ap 105 */
-			 <0x00009000 0x00209000 0x001000>,	/* ap 106 */
-			 <0x00022000 0x00222000 0x001000>,	/* ap 107 */
-			 <0x00023000 0x00223000 0x001000>;	/* ap 108 */
-
-		target-module@2000 {			/* 0x4a202000, ap 103 3c.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x2000 0x1000>;
-		};
-
-		target-module@4000 {			/* 0x4a204000, ap 35 46.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x4000 0x1000>;
-		};
-
-		target-module@6000 {			/* 0x4a206000, ap 33 4e.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x6000 0x1000>;
-		};
-
-		target-module@8000 {			/* 0x4a208000, ap 105 34.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x8000 0x1000>;
-		};
-
-		target-module@a000 {			/* 0x4a20a000, ap 31 30.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0xa000 0x1000>;
-		};
-
-		target-module@c000 {			/* 0x4a20c000, ap 39 14.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0xc000 0x1000>;
-		};
-
-		target-module@10000 {			/* 0x4a210000, ap 41 56.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x10000 0x1000>;
-		};
-
-		target-module@12000 {			/* 0x4a212000, ap 37 52.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x12000 0x1000>;
-		};
-
-		target-module@14000 {			/* 0x4a214000, ap 45 1c.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x14000 0x1000>;
-		};
-
-		target-module@16000 {			/* 0x4a216000, ap 43 42.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x16000 0x1000>;
-		};
-
-		target-module@18000 {			/* 0x4a218000, ap 47 1a.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x18000 0x1000>;
-		};
-
-		target-module@1a000 {			/* 0x4a21a000, ap 73 3e.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x1a000 0x1000>;
-		};
-
-		target-module@1c000 {			/* 0x4a21c000, ap 57 40.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x1c000 0x1000>;
-		};
-
-		target-module@1e000 {			/* 0x4a21e000, ap 29 12.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x1e000 0x1000>;
-		};
-
-		target-module@20000 {			/* 0x4a220000, ap 49 4a.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x20000 0x1000>;
-		};
-
-		target-module@22000 {			/* 0x4a222000, ap 107 3a.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x22000 0x1000>;
-		};
-
-		target-module@24000 {			/* 0x4a224000, ap 75 48.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x24000 0x1000>;
-		};
-
-		target-module@26000 {			/* 0x4a226000, ap 51 24.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x26000 0x1000>;
-		};
-
-		target-module@28000 {			/* 0x4a228000, ap 53 38.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x28000 0x1000>;
-		};
-
-		target-module@2a000 {			/* 0x4a22a000, ap 55 5a.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x2a000 0x1000>;
-		};
-	};
-
-	segment@280000 {					/* 0x4a280000 */
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-
-	segment@300000 {					/* 0x4a300000 */
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-};
-
-&l4_per {						/* 0x48000000 */
-	compatible = "ti,omap5-l4-per", "simple-bus";
-	reg = <0x48000000 0x800>,
-	      <0x48000800 0x800>,
-	      <0x48001000 0x400>,
-	      <0x48001400 0x400>,
-	      <0x48001800 0x400>,
-	      <0x48001c00 0x400>;
-	reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
-	#address-cells = <1>;
-	#size-cells = <1>;
-	ranges = <0x00000000 0x48000000 0x200000>,	/* segment 0 */
-		 <0x00200000 0x48200000 0x200000>;	/* segment 1 */
-
-	segment@0 {					/* 0x48000000 */
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x00000000 0x00000000 0x000800>,	/* ap 0 */
-			 <0x00001000 0x00001000 0x000400>,	/* ap 1 */
-			 <0x00000800 0x00000800 0x000800>,	/* ap 2 */
-			 <0x00020000 0x00020000 0x001000>,	/* ap 3 */
-			 <0x00021000 0x00021000 0x001000>,	/* ap 4 */
-			 <0x00032000 0x00032000 0x001000>,	/* ap 5 */
-			 <0x00033000 0x00033000 0x001000>,	/* ap 6 */
-			 <0x00034000 0x00034000 0x001000>,	/* ap 7 */
-			 <0x00035000 0x00035000 0x001000>,	/* ap 8 */
-			 <0x00036000 0x00036000 0x001000>,	/* ap 9 */
-			 <0x00037000 0x00037000 0x001000>,	/* ap 10 */
-			 <0x0003e000 0x0003e000 0x001000>,	/* ap 11 */
-			 <0x0003f000 0x0003f000 0x001000>,	/* ap 12 */
-			 <0x00055000 0x00055000 0x001000>,	/* ap 13 */
-			 <0x00056000 0x00056000 0x001000>,	/* ap 14 */
-			 <0x00057000 0x00057000 0x001000>,	/* ap 15 */
-			 <0x00058000 0x00058000 0x001000>,	/* ap 16 */
-			 <0x00059000 0x00059000 0x001000>,	/* ap 17 */
-			 <0x0005a000 0x0005a000 0x001000>,	/* ap 18 */
-			 <0x0005b000 0x0005b000 0x001000>,	/* ap 19 */
-			 <0x0005c000 0x0005c000 0x001000>,	/* ap 20 */
-			 <0x0005d000 0x0005d000 0x001000>,	/* ap 21 */
-			 <0x0005e000 0x0005e000 0x001000>,	/* ap 22 */
-			 <0x00060000 0x00060000 0x001000>,	/* ap 23 */
-			 <0x0006a000 0x0006a000 0x001000>,	/* ap 24 */
-			 <0x0006b000 0x0006b000 0x001000>,	/* ap 25 */
-			 <0x0006c000 0x0006c000 0x001000>,	/* ap 26 */
-			 <0x0006d000 0x0006d000 0x001000>,	/* ap 27 */
-			 <0x0006e000 0x0006e000 0x001000>,	/* ap 28 */
-			 <0x0006f000 0x0006f000 0x001000>,	/* ap 29 */
-			 <0x00070000 0x00070000 0x001000>,	/* ap 30 */
-			 <0x00071000 0x00071000 0x001000>,	/* ap 31 */
-			 <0x00072000 0x00072000 0x001000>,	/* ap 32 */
-			 <0x00073000 0x00073000 0x001000>,	/* ap 33 */
-			 <0x00061000 0x00061000 0x001000>,	/* ap 34 */
-			 <0x00053000 0x00053000 0x001000>,	/* ap 35 */
-			 <0x00054000 0x00054000 0x001000>,	/* ap 36 */
-			 <0x000b2000 0x000b2000 0x001000>,	/* ap 37 */
-			 <0x000b3000 0x000b3000 0x001000>,	/* ap 38 */
-			 <0x00078000 0x00078000 0x001000>,	/* ap 39 */
-			 <0x00079000 0x00079000 0x001000>,	/* ap 40 */
-			 <0x00086000 0x00086000 0x001000>,	/* ap 41 */
-			 <0x00087000 0x00087000 0x001000>,	/* ap 42 */
-			 <0x00088000 0x00088000 0x001000>,	/* ap 43 */
-			 <0x00089000 0x00089000 0x001000>,	/* ap 44 */
-			 <0x00051000 0x00051000 0x001000>,	/* ap 45 */
-			 <0x00052000 0x00052000 0x001000>,	/* ap 46 */
-			 <0x00098000 0x00098000 0x001000>,	/* ap 47 */
-			 <0x00099000 0x00099000 0x001000>,	/* ap 48 */
-			 <0x0009a000 0x0009a000 0x001000>,	/* ap 49 */
-			 <0x0009b000 0x0009b000 0x001000>,	/* ap 50 */
-			 <0x0009c000 0x0009c000 0x001000>,	/* ap 51 */
-			 <0x0009d000 0x0009d000 0x001000>,	/* ap 52 */
-			 <0x00068000 0x00068000 0x001000>,	/* ap 53 */
-			 <0x00069000 0x00069000 0x001000>,	/* ap 54 */
-			 <0x00090000 0x00090000 0x002000>,	/* ap 55 */
-			 <0x00092000 0x00092000 0x001000>,	/* ap 56 */
-			 <0x000a4000 0x000a4000 0x001000>,	/* ap 57 */
-			 <0x000a6000 0x000a6000 0x001000>,	/* ap 58 */
-			 <0x000a8000 0x000a8000 0x004000>,	/* ap 59 */
-			 <0x000ac000 0x000ac000 0x001000>,	/* ap 60 */
-			 <0x000ad000 0x000ad000 0x001000>,	/* ap 61 */
-			 <0x000ae000 0x000ae000 0x001000>,	/* ap 62 */
-			 <0x00066000 0x00066000 0x001000>,	/* ap 63 */
-			 <0x00067000 0x00067000 0x001000>,	/* ap 64 */
-			 <0x000b4000 0x000b4000 0x001000>,	/* ap 65 */
-			 <0x000b5000 0x000b5000 0x001000>,	/* ap 66 */
-			 <0x000b8000 0x000b8000 0x001000>,	/* ap 67 */
-			 <0x000b9000 0x000b9000 0x001000>,	/* ap 68 */
-			 <0x000ba000 0x000ba000 0x001000>,	/* ap 69 */
-			 <0x000bb000 0x000bb000 0x001000>,	/* ap 70 */
-			 <0x000d1000 0x000d1000 0x001000>,	/* ap 71 */
-			 <0x000d2000 0x000d2000 0x001000>,	/* ap 72 */
-			 <0x000d5000 0x000d5000 0x001000>,	/* ap 73 */
-			 <0x000d6000 0x000d6000 0x001000>,	/* ap 74 */
-			 <0x000a2000 0x000a2000 0x001000>,	/* ap 75 */
-			 <0x000a3000 0x000a3000 0x001000>,	/* ap 76 */
-			 <0x00001400 0x00001400 0x000400>,	/* ap 77 */
-			 <0x00001800 0x00001800 0x000400>,	/* ap 78 */
-			 <0x00001c00 0x00001c00 0x000400>,	/* ap 79 */
-			 <0x000a5000 0x000a5000 0x001000>,	/* ap 80 */
-			 <0x0007a000 0x0007a000 0x001000>,	/* ap 81 */
-			 <0x0007b000 0x0007b000 0x001000>,	/* ap 82 */
-			 <0x0007c000 0x0007c000 0x001000>,	/* ap 83 */
-			 <0x0007d000 0x0007d000 0x001000>;	/* ap 84 */
-
-		target-module@20000 {			/* 0x48020000, ap 3 04.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x20050 0x4>,
-			      <0x20054 0x4>,
-			      <0x20058 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x20000 0x1000>;
-
-			uart3: serial@0 {
-				compatible = "ti,omap4-uart";
-				reg = <0x0 0x100>;
-				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-				clock-frequency = <48000000>;
-			};
-		};
-
-		target-module@32000 {			/* 0x48032000, ap 5 3e.0 */
-			compatible = "ti,sysc-omap4-timer", "ti,sysc";
-			reg = <0x32000 0x4>,
-			      <0x32010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x32000 0x1000>;
-
-			timer2: timer@0 {
-				compatible = "ti,omap5430-timer";
-				reg = <0x0 0x80>;
-				clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>;
-				clock-names = "fck";
-				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
-			};
-		};
-
-		target-module@34000 {			/* 0x48034000, ap 7 46.0 */
-			compatible = "ti,sysc-omap4-timer", "ti,sysc";
-			reg = <0x34000 0x4>,
-			      <0x34010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x34000 0x1000>;
-
-			timer3: timer@0 {
-				compatible = "ti,omap5430-timer";
-				reg = <0x0 0x80>;
-				clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>;
-				clock-names = "fck";
-				interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-			};
-		};
-
-		target-module@36000 {			/* 0x48036000, ap 9 4e.0 */
-			compatible = "ti,sysc-omap4-timer", "ti,sysc";
-			reg = <0x36000 0x4>,
-			      <0x36010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x36000 0x1000>;
-
-			timer4: timer@0 {
-				compatible = "ti,omap5430-timer";
-				reg = <0x0 0x80>;
-				clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>;
-				clock-names = "fck";
-				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
-			};
-		};
-
-		target-module@3e000 {			/* 0x4803e000, ap 11 56.0 */
-			compatible = "ti,sysc-omap4-timer", "ti,sysc";
-			reg = <0x3e000 0x4>,
-			      <0x3e010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x3e000 0x1000>;
-
-			timer9: timer@0 {
-				compatible = "ti,omap5430-timer";
-				reg = <0x0 0x80>;
-				clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>;
-				clock-names = "fck";
-				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
-				ti,timer-pwm;
-			};
-		};
-
-		target-module@51000 {			/* 0x48051000, ap 45 2e.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x51000 0x4>,
-			      <0x51010 0x4>,
-			      <0x51114 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>,
-				 <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 8>;
-			clock-names = "fck", "dbclk";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x51000 0x1000>;
-
-			gpio7: gpio@0 {
-				compatible = "ti,omap4-gpio";
-				reg = <0x0 0x200>;
-				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-		};
-
-		target-module@53000 {			/* 0x48053000, ap 35 36.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x53000 0x4>,
-			      <0x53010 0x4>,
-			      <0x53114 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>,
-				 <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 8>;
-			clock-names = "fck", "dbclk";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x53000 0x1000>;
-
-			gpio8: gpio@0 {
-				compatible = "ti,omap4-gpio";
-				reg = <0x0 0x200>;
-				interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-		};
-
-		target-module@55000 {			/* 0x48055000, ap 13 0e.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x55000 0x4>,
-			      <0x55010 0x4>,
-			      <0x55114 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>,
-				 <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 8>;
-			clock-names = "fck", "dbclk";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x55000 0x1000>;
-
-			gpio2: gpio@0 {
-				compatible = "ti,omap4-gpio";
-				reg = <0x0 0x200>;
-				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-		};
-
-		target-module@57000 {			/* 0x48057000, ap 15 06.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x57000 0x4>,
-			      <0x57010 0x4>,
-			      <0x57114 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>,
-				 <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 8>;
-			clock-names = "fck", "dbclk";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x57000 0x1000>;
-
-			gpio3: gpio@0 {
-				compatible = "ti,omap4-gpio";
-				reg = <0x0 0x200>;
-				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-		};
-
-		target-module@59000 {			/* 0x48059000, ap 17 16.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x59000 0x4>,
-			      <0x59010 0x4>,
-			      <0x59114 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>,
-				 <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 8>;
-			clock-names = "fck", "dbclk";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x59000 0x1000>;
-
-			gpio4: gpio@0 {
-				compatible = "ti,omap4-gpio";
-				reg = <0x0 0x200>;
-				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-		};
-
-		target-module@5b000 {			/* 0x4805b000, ap 19 1e.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x5b000 0x4>,
-			      <0x5b010 0x4>,
-			      <0x5b114 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>,
-				 <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 8>;
-			clock-names = "fck", "dbclk";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x5b000 0x1000>;
-
-			gpio5: gpio@0 {
-				compatible = "ti,omap4-gpio";
-				reg = <0x0 0x200>;
-				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-		};
-
-		target-module@5d000 {			/* 0x4805d000, ap 21 26.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x5d000 0x4>,
-			      <0x5d010 0x4>,
-			      <0x5d114 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>,
-				 <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 8>;
-			clock-names = "fck", "dbclk";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x5d000 0x1000>;
-
-			gpio6: gpio@0 {
-				compatible = "ti,omap4-gpio";
-				reg = <0x0 0x200>;
-				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-		};
-
-		target-module@60000 {			/* 0x48060000, ap 23 24.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x60000 0x8>,
-			      <0x60010 0x8>,
-			      <0x60090 0x8>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
-					 SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x60000 0x1000>;
-
-			i2c3: i2c@0 {
-				compatible = "ti,omap4-i2c";
-				reg = <0x0 0x100>;
-				interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-			};
-		};
-
-		target-module@66000 {			/* 0x48066000, ap 63 4c.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x66050 0x4>,
-			      <0x66054 0x4>,
-			      <0x66058 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x66000 0x1000>;
-
-			uart5: serial@0 {
-				compatible = "ti,omap4-uart";
-				reg = <0x0 0x100>;
-				interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
-				clock-frequency = <48000000>;
-			};
-		};
-
-		target-module@68000 {			/* 0x48068000, ap 53 54.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x68050 0x4>,
-			      <0x68054 0x4>,
-			      <0x68058 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x68000 0x1000>;
-
-			uart6: serial@0 {
-				compatible = "ti,omap4-uart";
-				reg = <0x0 0x100>;
-				interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-				clock-frequency = <48000000>;
-			};
-		};
-
-		target-module@6a000 {			/* 0x4806a000, ap 24 0a.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x6a050 0x4>,
-			      <0x6a054 0x4>,
-			      <0x6a058 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x6a000 0x1000>;
-
-			uart1: serial@0 {
-				compatible = "ti,omap4-uart";
-				reg = <0x0 0x100>;
-				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-				clock-frequency = <48000000>;
-			};
-		};
-
-		target-module@6c000 {			/* 0x4806c000, ap 26 22.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x6c050 0x4>,
-			      <0x6c054 0x4>,
-			      <0x6c058 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x6c000 0x1000>;
-
-			uart2: serial@0 {
-				compatible = "ti,omap4-uart";
-				reg = <0x0 0x100>;
-				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-				clock-frequency = <48000000>;
-			};
-		};
-
-		target-module@6e000 {			/* 0x4806e000, ap 28 44.1 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x6e050 0x4>,
-			      <0x6e054 0x4>,
-			      <0x6e058 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x6e000 0x1000>;
-
-			uart4: serial@0 {
-				compatible = "ti,omap4-uart";
-				reg = <0x0 0x100>;
-				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-				clock-frequency = <48000000>;
-			};
-		};
-
-		target-module@70000 {			/* 0x48070000, ap 30 14.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x70000 0x8>,
-			      <0x70010 0x8>,
-			      <0x70090 0x8>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
-					 SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x70000 0x1000>;
-
-			i2c1: i2c@0 {
-				compatible = "ti,omap4-i2c";
-				reg = <0x0 0x100>;
-				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-			};
-		};
-
-		target-module@72000 {			/* 0x48072000, ap 32 1c.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x72000 0x8>,
-			      <0x72010 0x8>,
-			      <0x72090 0x8>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
-					 SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x72000 0x1000>;
-
-			i2c2: i2c@0 {
-				compatible = "ti,omap4-i2c";
-				reg = <0x0 0x100>;
-				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-			};
-		};
-
-		target-module@78000 {			/* 0x48078000, ap 39 12.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x78000 0x1000>;
-		};
-
-		target-module@7a000 {			/* 0x4807a000, ap 81 2c.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x7a000 0x8>,
-			      <0x7a010 0x8>,
-			      <0x7a090 0x8>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
-					 SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x7a000 0x1000>;
-
-			i2c4: i2c@0 {
-				compatible = "ti,omap4-i2c";
-				reg = <0x0 0x100>;
-				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-			};
-		};
-
-		target-module@7c000 {			/* 0x4807c000, ap 83 34.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x7c000 0x8>,
-			      <0x7c010 0x8>,
-			      <0x7c090 0x8>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
-					 SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x7c000 0x1000>;
-
-			i2c5: i2c@0 {
-				compatible = "ti,omap4-i2c";
-				reg = <0x0 0x100>;
-				interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-			};
-		};
-
-		target-module@86000 {			/* 0x48086000, ap 41 5e.0 */
-			compatible = "ti,sysc-omap4-timer", "ti,sysc";
-			reg = <0x86000 0x4>,
-			      <0x86010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x86000 0x1000>;
-
-			timer10: timer@0 {
-				compatible = "ti,omap5430-timer";
-				reg = <0x0 0x80>;
-				clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>;
-				clock-names = "fck";
-				interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-				ti,timer-pwm;
-			};
-		};
-
-		target-module@88000 {			/* 0x48088000, ap 43 66.0 */
-			compatible = "ti,sysc-omap4-timer", "ti,sysc";
-			reg = <0x88000 0x4>,
-			      <0x88010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x88000 0x1000>;
-
-			timer11: timer@0 {
-				compatible = "ti,omap5430-timer";
-				reg = <0x0 0x80>;
-				clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>;
-				clock-names = "fck";
-				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
-				ti,timer-pwm;
-			};
-		};
-
-		rng_target: target-module@90000 {	/* 0x48090000, ap 55 1a.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x91fe0 0x4>,
-			      <0x91fe4 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>;
-			/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
-			clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x90000 0x2000>;
-
-			rng: rng@0 {
-				compatible = "ti,omap4-rng";
-				reg = <0x0 0x2000>;
-				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
-			};
-		};
-
-		target-module@98000 {			/* 0x48098000, ap 47 08.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0x98000 0x4>,
-			      <0x98010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x98000 0x1000>;
-
-			mcspi1: spi@0 {
-				compatible = "ti,omap4-mcspi";
-				reg = <0x0 0x200>;
-				interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				ti,spi-num-cs = <4>;
-				dmas = <&sdma 35>,
-				       <&sdma 36>,
-				       <&sdma 37>,
-				       <&sdma 38>,
-				       <&sdma 39>,
-				       <&sdma 40>,
-				       <&sdma 41>,
-				       <&sdma 42>;
-				dma-names = "tx0", "rx0", "tx1", "rx1",
-					    "tx2", "rx2", "tx3", "rx3";
-			};
-		};
-
-		target-module@9a000 {			/* 0x4809a000, ap 49 10.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0x9a000 0x4>,
-			      <0x9a010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x9a000 0x1000>;
-
-			mcspi2: spi@0 {
-				compatible = "ti,omap4-mcspi";
-				reg = <0x0 0x200>;
-				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				ti,spi-num-cs = <2>;
-				dmas = <&sdma 43>,
-				       <&sdma 44>,
-				       <&sdma 45>,
-				       <&sdma 46>;
-				dma-names = "tx0", "rx0", "tx1", "rx1";
-			};
-		};
-
-		target-module@9c000 {			/* 0x4809c000, ap 51 3a.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0x9c000 0x4>,
-			      <0x9c010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-midle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
-			clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x9c000 0x1000>;
-
-			mmc1: mmc@0 {
-				compatible = "ti,omap4-hsmmc";
-				reg = <0x0 0x400>;
-				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-				ti,dual-volt;
-				ti,needs-special-reset;
-				dmas = <&sdma 61>, <&sdma 62>;
-				dma-names = "tx", "rx";
-				pbias-supply = <&pbias_mmc_reg>;
-			};
-		};
-
-		target-module@a2000 {			/* 0x480a2000, ap 75 02.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0xa2000 0x1000>;
-		};
-
-		target-module@a4000 {			/* 0x480a4000, ap 57 3c.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x00000000 0x000a4000 0x00001000>,
-				 <0x00001000 0x000a5000 0x00001000>;
-		};
-
-		target-module@a8000 {			/* 0x480a8000, ap 59 2a.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0xa8000 0x4000>;
-		};
-
-		target-module@ad000 {			/* 0x480ad000, ap 61 20.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0xad000 0x4>,
-			      <0xad010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-midle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0xad000 0x1000>;
-
-			mmc3: mmc@0 {
-				compatible = "ti,omap4-hsmmc";
-				reg = <0x0 0x400>;
-				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-				ti,needs-special-reset;
-				dmas = <&sdma 77>, <&sdma 78>;
-				dma-names = "tx", "rx";
-			};
-		};
-
-		target-module@b2000 {			/* 0x480b2000, ap 37 0c.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0xb2000 0x1000>;
-		};
-
-		target-module@b4000 {			/* 0x480b4000, ap 65 42.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0xb4000 0x4>,
-			      <0xb4010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-midle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
-			clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0xb4000 0x1000>;
-
-			mmc2: mmc@0 {
-				compatible = "ti,omap4-hsmmc";
-				reg = <0x0 0x400>;
-				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-				ti,needs-special-reset;
-				dmas = <&sdma 47>, <&sdma 48>;
-				dma-names = "tx", "rx";
-			};
-		};
-
-		target-module@b8000 {			/* 0x480b8000, ap 67 32.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0xb8000 0x4>,
-			      <0xb8010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0xb8000 0x1000>;
-
-			mcspi3: spi@0 {
-				compatible = "ti,omap4-mcspi";
-				reg = <0x0 0x200>;
-				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				ti,spi-num-cs = <2>;
-				dmas = <&sdma 15>, <&sdma 16>;
-				dma-names = "tx0", "rx0";
-			};
-		};
-
-		target-module@ba000 {			/* 0x480ba000, ap 69 18.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0xba000 0x4>,
-			      <0xba010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0xba000 0x1000>;
-
-			mcspi4: spi@0 {
-				compatible = "ti,omap4-mcspi";
-				reg = <0x0 0x200>;
-				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				ti,spi-num-cs = <1>;
-				dmas = <&sdma 70>, <&sdma 71>;
-				dma-names = "tx0", "rx0";
-			};
-		};
-
-		target-module@d1000 {			/* 0x480d1000, ap 71 28.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0xd1000 0x4>,
-			      <0xd1010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-midle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0xd1000 0x1000>;
-
-			mmc4: mmc@0 {
-				compatible = "ti,omap4-hsmmc";
-				reg = <0x0 0x400>;
-				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-				ti,needs-special-reset;
-				dmas = <&sdma 57>, <&sdma 58>;
-				dma-names = "tx", "rx";
-			};
-		};
-
-		target-module@d5000 {			/* 0x480d5000, ap 73 30.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0xd5000 0x4>,
-			      <0xd5010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-midle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
-			clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0xd5000 0x1000>;
-
-			mmc5: mmc@0 {
-				compatible = "ti,omap4-hsmmc";
-				reg = <0x0 0x400>;
-				interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-				ti,needs-special-reset;
-				dmas = <&sdma 59>, <&sdma 60>;
-				dma-names = "tx", "rx";
-			};
-		};
-	};
-
-	segment@200000 {					/* 0x48200000 */
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-};
-
-&l4_wkup {						/* 0x4ae00000 */
-	compatible = "ti,omap5-l4-wkup", "simple-bus";
-	reg = <0x4ae00000 0x800>,
-	      <0x4ae00800 0x800>,
-	      <0x4ae01000 0x1000>;
-	reg-names = "ap", "la", "ia0";
-	#address-cells = <1>;
-	#size-cells = <1>;
-	ranges = <0x00000000 0x4ae00000 0x010000>,	/* segment 0 */
-		 <0x00010000 0x4ae10000 0x010000>,	/* segment 1 */
-		 <0x00020000 0x4ae20000 0x010000>;	/* segment 2 */
-
-	segment@0 {					/* 0x4ae00000 */
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x00000000 0x00000000 0x000800>,	/* ap 0 */
-			 <0x00001000 0x00001000 0x001000>,	/* ap 1 */
-			 <0x00000800 0x00000800 0x000800>,	/* ap 2 */
-			 <0x00006000 0x00006000 0x002000>,	/* ap 3 */
-			 <0x00008000 0x00008000 0x001000>,	/* ap 4 */
-			 <0x0000a000 0x0000a000 0x001000>,	/* ap 15 */
-			 <0x0000b000 0x0000b000 0x001000>,	/* ap 16 */
-			 <0x00004000 0x00004000 0x001000>,	/* ap 17 */
-			 <0x00005000 0x00005000 0x001000>,	/* ap 18 */
-			 <0x0000c000 0x0000c000 0x001000>,	/* ap 19 */
-			 <0x0000d000 0x0000d000 0x001000>;	/* ap 20 */
-
-		target-module@4000 {			/* 0x4ae04000, ap 17 20.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			ti,hwmods = "counter_32k";
-			reg = <0x4000 0x4>,
-			      <0x4010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>;
-			/* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
-			clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x4000 0x1000>;
-
-			counter32k: counter@0 {
-				compatible = "ti,omap-counter32k";
-				reg = <0x0 0x40>;
-			};
-		};
-
-		target-module@6000 {			/* 0x4ae06000, ap 3 08.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0x6000 0x4>;
-			reg-names = "rev";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x6000 0x2000>;
-
-			prm: prm@0 {
-				compatible = "ti,omap5-prm", "simple-bus";
-				reg = <0x0 0x2000>;
-				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-				#address-cells = <1>;
-				#size-cells = <1>;
-				ranges = <0 0 0x2000>;
-
-				prm_clocks: clocks {
-					#address-cells = <1>;
-					#size-cells = <0>;
-				};
-
-				prm_clockdomains: clockdomains {
-				};
-			};
-		};
-
-		target-module@a000 {			/* 0x4ae0a000, ap 15 2c.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0xa000 0x4>;
-			reg-names = "rev";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0xa000 0x1000>;
-
-			scrm: scrm@0 {
-				compatible = "ti,omap5-scrm";
-				reg = <0x0 0x1000>;
-
-				scrm_clocks: clocks {
-					#address-cells = <1>;
-					#size-cells = <0>;
-				};
-
-				scrm_clockdomains: clockdomains {
-				};
-			};
-		};
-
-		target-module@c000 {			/* 0x4ae0c000, ap 19 28.0 */
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0xc000 0x4>;
-			reg-names = "rev";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0xc000 0x1000>;
-
-			omap5_pmx_wkup: pinmux@840 {
-				compatible = "ti,omap5-padconf",
-					     "pinctrl-single";
-				reg = <0x840 0x003c>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				#pinctrl-cells = <1>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-				pinctrl-single,register-width = <16>;
-				pinctrl-single,function-mask = <0x7fff>;
-			};
-
-			omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@da0 {
-				compatible = "ti,omap5-scm-wkup-pad-conf",
-					     "simple-bus";
-				reg = <0xda0 0x60>;
-				#address-cells = <1>;
-				#size-cells = <1>;
-				ranges = <0 0 0x60>;
-
-				scm_wkup_pad_conf: scm_conf@0 {
-					compatible = "syscon", "simple-bus";
-					reg = <0x0 0x60>;
-					#address-cells = <1>;
-					#size-cells = <1>;
-					ranges = <0 0x0 0x60>;
-
-					scm_wkup_pad_conf_clocks: clocks@0 {
-						#address-cells = <1>;
-						#size-cells = <0>;
-					};
-				};
-			};
-		};
-	};
-
-	segment@10000 {					/* 0x4ae10000 */
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x00000000 0x00010000 0x001000>,	/* ap 5 */
-			 <0x00001000 0x00011000 0x001000>,	/* ap 6 */
-			 <0x00004000 0x00014000 0x001000>,	/* ap 7 */
-			 <0x00005000 0x00015000 0x001000>,	/* ap 8 */
-			 <0x00008000 0x00018000 0x001000>,	/* ap 9 */
-			 <0x00009000 0x00019000 0x001000>,	/* ap 10 */
-			 <0x0000c000 0x0001c000 0x001000>,	/* ap 11 */
-			 <0x0000d000 0x0001d000 0x001000>;	/* ap 12 */
-
-		target-module@0 {			/* 0x4ae10000, ap 5 10.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x0 0x4>,
-			      <0x10 0x4>,
-			      <0x114 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
-			clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>,
-				 <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 8>;
-			clock-names = "fck", "dbclk";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x0 0x1000>;
-
-			gpio1: gpio@0 {
-				compatible = "ti,omap4-gpio";
-				reg = <0x0 0x200>;
-				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-				ti,gpio-always-on;
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-		};
-
-		target-module@4000 {			/* 0x4ae14000, ap 7 14.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x4000 0x4>,
-			      <0x4010 0x4>,
-			      <0x4014 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
-					 SYSC_OMAP2_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			ti,syss-mask = <1>;
-			/* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
-			clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x4000 0x1000>;
-
-			wdt2: wdt@0 {
-				compatible = "ti,omap5-wdt", "ti,omap3-wdt";
-				reg = <0x0 0x80>;
-				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			};
-		};
-
-		target-module@8000 {			/* 0x4ae18000, ap 9 18.0 */
-			compatible = "ti,sysc-omap4-timer", "ti,sysc";
-			ti,hwmods = "timer1";
-			reg = <0x8000 0x4>,
-			      <0x8010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
-					 SYSC_OMAP4_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>,
-					<SYSC_IDLE_SMART_WKUP>;
-			/* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
-			clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x8000 0x1000>;
-
-			timer1: timer@0 {
-				compatible = "ti,omap5430-timer";
-				reg = <0x0 0x80>;
-				clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
-				clock-names = "fck";
-				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-				ti,timer-alwon;
-			};
-		};
-
-		target-module@c000 {			/* 0x4ae1c000, ap 11 1c.0 */
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0xc000 0x4>,
-			      <0xc010 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
-					 SYSC_OMAP2_SOFTRESET)>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>;
-			/* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
-			clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0xc000 0x1000>;
-
-			keypad: keypad@0 {
-				compatible = "ti,omap4-keypad";
-				reg = <0x0 0x400>;
-			};
-		};
-	};
-
-	segment@20000 {					/* 0x4ae20000 */
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x00006000 0x00026000 0x001000>,	/* ap 13 */
-			 <0x0000a000 0x0002a000 0x001000>,	/* ap 14 */
-			 <0x00000000 0x00020000 0x001000>,	/* ap 21 */
-			 <0x00001000 0x00021000 0x001000>,	/* ap 22 */
-			 <0x00002000 0x00022000 0x001000>,	/* ap 23 */
-			 <0x00003000 0x00023000 0x001000>,	/* ap 24 */
-			 <0x00007000 0x00027000 0x000400>,	/* ap 25 */
-			 <0x00008000 0x00028000 0x000800>,	/* ap 26 */
-			 <0x00009000 0x00029000 0x000100>,	/* ap 27 */
-			 <0x00008800 0x00028800 0x000200>,	/* ap 28 */
-			 <0x00008a00 0x00028a00 0x000100>;	/* ap 29 */
-
-		target-module@0 {			/* 0x4ae20000, ap 21 04.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x0 0x1000>;
-		};
-
-		target-module@2000 {			/* 0x4ae22000, ap 23 0c.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x2000 0x1000>;
-		};
-
-		target-module@6000 {			/* 0x4ae26000, ap 13 24.0 */
-			compatible = "ti,sysc";
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x00000000 0x00006000 0x00001000>,
-				 <0x00001000 0x00007000 0x00000400>,
-				 <0x00002000 0x00008000 0x00000800>,
-				 <0x00002800 0x00008800 0x00000200>,
-				 <0x00002a00 0x00008a00 0x00000100>,
-				 <0x00003000 0x00009000 0x00000100>;
-		};
-	};
-};
diff --git a/arch/arm/dts/omap5-uevm.dts b/arch/arm/dts/omap5-uevm.dts
deleted file mode 100644
index 9441e9a..0000000
--- a/arch/arm/dts/omap5-uevm.dts
+++ /dev/null
@@ -1,200 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- */
-/dts-v1/;
-
-#include "omap5-board-common.dtsi"
-
-/ {
-	model = "TI OMAP5 uEVM board";
-	compatible = "ti,omap5-uevm", "ti,omap5";
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */
-	};
-
-	aliases {
-		ethernet = &ethernet;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		led1 {
-			label = "omap5:blue:usr1";
-			gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */
-			linux,default-trigger = "heartbeat";
-			default-state = "off";
-		};
-	};
-
-	evm_keys {
-		compatible = "gpio-keys";
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&evm_keys_pins>;
-
-		#address-cells = <7>;
-		#size-cells = <0>;
-
-		btn1 {
-			label = "BTN1";
-			linux,code = <169>;
-			gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;	/* gpio3_83 */
-			wakeup-source;
-			autorepeat;
-			debounce-interval = <50>;
-		};
-	};
-
-	evm_leds {
-		compatible = "gpio-leds";
-
-		led1 {
-			label = "omap5:red:led";
-			gpios = <&gpio9 17 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "mmc0";
-			default-state = "off";
-		};
-
-		led2 {
-			label = "omap5:green:led";
-			gpios = <&gpio9 18 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "mmc1";
-			default-state = "off";
-		};
-
-		led3 {
-			label = "omap5:blue:led";
-			gpios = <&gpio9 19 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "mmc2";
-			default-state = "off";
-		};
-
-		led4 {
-			label = "omap5:green:led1";
-			gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "heartbeat";
-			default-state = "off";
-		};
-
-		led5 {
-			label = "omap5:green:led2";
-			gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "default-on";
-			default-state = "off";
-		};
-
-		led6 {
-			label = "omap5:green:led3";
-			gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "heartbeat";
-			default-state = "off";
-		};
-
-		led7 {
-			label = "omap5:green:led4";
-			gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "default-on";
-			default-state = "off";
-		};
-
-		led8 {
-			label = "omap5:green:led5";
-			gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "heartbeat";
-			default-state = "off";
-		};
-	};
-};
-
-&hdmi {
-	vdda-supply = <&ldo4_reg>;
-};
-
-&i2c1 {
-	eeprom@50 {
-		compatible = "atmel,24c02";
-		reg = <0x50>;
-	};
-};
-
-&i2c5 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c5_pins>;
-
-	clock-frequency = <400000>;
-
-	gpio9: gpio@22 {
-		compatible = "ti,tca6424";
-		reg = <0x22>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-};
-
-&mmc1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc1_pins>;
-
-	cd-gpios = <&gpio5 24 GPIO_ACTIVE_LOW>;	/* gpio5_152 */
-};
-
-&omap5_pmx_core {
-	evm_keys_pins: pinmux_evm_keys_gpio_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6)	/* gpio3_83 */
-		>;
-	};
-
-	i2c5_pins: pinmux_i2c5_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0)		/* i2c5_scl */
-			OMAP5_IOPAD(0x1c8, PIN_INPUT | MUX_MODE0)		/* i2c5_sda */
-		>;
-	};
-
-	mmc1_pins: pinmux_mmc1_pins {
-		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x1d4, PIN_INPUT_PULLUP | MUX_MODE6)	/* gpio5_152 */
-		>;
-	};
-};
-
-&tpd12s015 {
-	gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>,	/* TCA6424A P01, CT CP HPD */
-		<&gpio9 1 GPIO_ACTIVE_HIGH>,	/* TCA6424A P00, LS OE */
-		<&gpio7 1 GPIO_ACTIVE_HIGH>;	/* GPIO 193, HPD */
-};
-
-&twl6040 {
-	ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>;  /* gpio line 141 */
-};
-
-&twl6040_pins {
-	pinctrl-single,pins = <
-		OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6)	/* mcspi1_somi.gpio5_141 */
-	>;
-};
-
-&usbhsehci {
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	hub@2 {
-		compatible = "usb424,3503";
-		reg = <2>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	ethernet: usbether@3 {
-		compatible = "usb424,9730";
-		reg = <3>;
-	};
-};
-
-&wlcore {
-	compatible = "ti,wl1837";
-};
diff --git a/arch/arm/dts/omap5.dtsi b/arch/arm/dts/omap5.dtsi
deleted file mode 100644
index 2ac7f02..0000000
--- a/arch/arm/dts/omap5.dtsi
+++ /dev/null
@@ -1,583 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Based on "omap4.dtsi"
- */
-
-#include <dt-bindings/bus/ti-sysc.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/omap.h>
-#include <dt-bindings/clock/omap5.h>
-
-/ {
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	compatible = "ti,omap5";
-	interrupt-parent = <&wakeupgen>;
-	chosen { };
-
-	aliases {
-		i2c0 = &i2c1;
-		i2c1 = &i2c2;
-		i2c2 = &i2c3;
-		i2c3 = &i2c4;
-		i2c4 = &i2c5;
-		serial0 = &uart1;
-		serial1 = &uart2;
-		serial2 = &uart3;
-		serial3 = &uart4;
-		serial4 = &uart5;
-		serial5 = &uart6;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			reg = <0x0>;
-
-			operating-points = <
-				/* kHz    uV */
-				1000000 1060000
-				1500000 1250000
-			>;
-
-			clocks = <&dpll_mpu_ck>;
-			clock-names = "cpu";
-
-			clock-latency = <300000>; /* From omap-cpufreq driver */
-
-			/* cooling options */
-			#cooling-cells = <2>; /* min followed by max */
-		};
-		cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			reg = <0x1>;
-
-			operating-points = <
-				/* kHz    uV */
-				1000000 1060000
-				1500000 1250000
-			>;
-
-			clocks = <&dpll_mpu_ck>;
-			clock-names = "cpu";
-
-			clock-latency = <300000>; /* From omap-cpufreq driver */
-
-			/* cooling options */
-			#cooling-cells = <2>; /* min followed by max */
-		};
-	};
-
-	thermal-zones {
-		#include "omap4-cpu-thermal.dtsi"
-		#include "omap5-gpu-thermal.dtsi"
-		#include "omap5-core-thermal.dtsi"
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		/* PPI secure/nonsecure IRQ */
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
-		interrupt-parent = <&gic>;
-	};
-
-	pmu {
-		compatible = "arm,cortex-a15-pmu";
-		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	gic: interrupt-controller@48211000 {
-		compatible = "arm,cortex-a15-gic";
-		interrupt-controller;
-		#interrupt-cells = <3>;
-		reg = <0 0x48211000 0 0x1000>,
-		      <0 0x48212000 0 0x2000>,
-		      <0 0x48214000 0 0x2000>,
-		      <0 0x48216000 0 0x2000>;
-		interrupt-parent = <&gic>;
-	};
-
-	wakeupgen: interrupt-controller@48281000 {
-		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
-		interrupt-controller;
-		#interrupt-cells = <3>;
-		reg = <0 0x48281000 0 0x1000>;
-		interrupt-parent = <&gic>;
-	};
-
-	/*
-	 * The soc node represents the soc top level view. It is used for IPs
-	 * that are not memory mapped in the MPU view or for the MPU itself.
-	 */
-	soc {
-		compatible = "ti,omap-infra";
-		mpu {
-			compatible = "ti,omap4-mpu";
-			ti,hwmods = "mpu";
-			sram = <&ocmcram>;
-		};
-	};
-
-	/*
-	 * XXX: Use a flat representation of the OMAP3 interconnect.
-	 * The real OMAP interconnect network is quite complex.
-	 * Since it will not bring real advantage to represent that in DT for
-	 * the moment, just use a fake OCP bus entry to represent the whole bus
-	 * hierarchy.
-	 */
-	ocp {
-		compatible = "ti,omap5-l3-noc", "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0 0 0xc0000000>;
-		dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
-		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
-		reg = <0 0x44000000 0 0x2000>,
-		      <0 0x44800000 0 0x3000>,
-		      <0 0x45000000 0 0x4000>;
-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-
-		l4_wkup: interconnect@4ae00000 {
-		};
-
-		l4_cfg: interconnect@4a000000 {
-		};
-
-		l4_per: interconnect@48000000 {
-		};
-
-		l4_abe: interconnect@40100000 {
-		};
-
-		ocmcram: sram@40300000 {
-			compatible = "mmio-sram";
-			reg = <0x40300000 0x20000>; /* 128k */
-		};
-
-		gpmc: gpmc@50000000 {
-			compatible = "ti,omap4430-gpmc";
-			reg = <0x50000000 0x1000>;
-			#address-cells = <2>;
-			#size-cells = <1>;
-			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&sdma 4>;
-			dma-names = "rxtx";
-			gpmc,num-cs = <8>;
-			gpmc,num-waitpins = <4>;
-			ti,hwmods = "gpmc";
-			clocks = <&l3_iclk_div>;
-			clock-names = "fck";
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		target-module@55082000 {
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x55082000 0x4>,
-			      <0x55082010 0x4>,
-			      <0x55082014 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>;
-			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
-			clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
-			clock-names = "fck";
-			resets = <&prm_core 2>;
-			reset-names = "rstctrl";
-			ranges = <0x0 0x55082000 0x100>;
-			#size-cells = <1>;
-			#address-cells = <1>;
-
-			mmu_ipu: mmu@0 {
-				compatible = "ti,omap4-iommu";
-				reg = <0x0 0x100>;
-				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
-				#iommu-cells = <0>;
-				ti,iommu-bus-err-back;
-			};
-		};
-
-		dmm@4e000000 {
-			compatible = "ti,omap5-dmm";
-			reg = <0x4e000000 0x800>;
-			interrupts = <0 113 0x4>;
-			ti,hwmods = "dmm";
-		};
-
-		emif1: emif@4c000000 {
-			compatible	= "ti,emif-4d5";
-			ti,hwmods	= "emif1";
-			ti,no-idle-on-init;
-			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
-			reg = <0x4c000000 0x400>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-			hw-caps-read-idle-ctrl;
-			hw-caps-ll-interface;
-			hw-caps-temp-alert;
-		};
-
-		emif2: emif@4d000000 {
-			compatible	= "ti,emif-4d5";
-			ti,hwmods	= "emif2";
-			ti,no-idle-on-init;
-			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
-			reg = <0x4d000000 0x400>;
-			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-			hw-caps-read-idle-ctrl;
-			hw-caps-ll-interface;
-			hw-caps-temp-alert;
-		};
-
-		bandgap: bandgap@4a0021e0 {
-			reg = <0x4a0021e0 0xc
-			       0x4a00232c 0xc
-			       0x4a002380 0x2c
-			       0x4a0023C0 0x3c>;
-			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
-			compatible = "ti,omap5430-bandgap";
-
-			#thermal-sensor-cells = <1>;
-		};
-
-		/* OCP2SCP3 */
-		sata: sata@4a141100 {
-			compatible = "snps,dwc-ahci";
-			reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
-			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-			phys = <&sata_phy>;
-			phy-names = "sata-phy";
-			clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
-			ti,hwmods = "sata";
-			ports-implemented = <0x1>;
-		};
-
-		target-module@56000000 {
-			compatible = "ti,sysc-omap4", "ti,sysc";
-			reg = <0x5600fe00 0x4>,
-			      <0x5600fe10 0x4>;
-			reg-names = "rev", "sysc";
-			ti,sysc-midle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>;
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
-					<SYSC_IDLE_SMART>;
-			clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
-			clock-names = "fck";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x56000000 0x2000000>;
-
-			/*
-			 * Closed source PowerVR driver, no child device
-			 * binding or driver in mainline
-			 */
-		};
-
-		target-module@58000000 {
-			compatible = "ti,sysc-omap2", "ti,sysc";
-			reg = <0x58000000 4>,
-			      <0x58000014 4>;
-			reg-names = "rev", "syss";
-			ti,syss-mask = <1>;
-			clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
-				 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
-				 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
-				 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
-			clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x58000000 0x1000000>;
-
-			dss: dss@0 {
-				compatible = "ti,omap5-dss";
-				reg = <0 0x80>;
-				status = "disabled";
-				clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
-				clock-names = "fck";
-				#address-cells = <1>;
-				#size-cells = <1>;
-				ranges = <0 0 0x1000000>;
-
-				target-module@1000 {
-					compatible = "ti,sysc-omap2", "ti,sysc";
-					reg = <0x1000 0x4>,
-					      <0x1010 0x4>,
-					      <0x1014 0x4>;
-					reg-names = "rev", "sysc", "syss";
-					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-							<SYSC_IDLE_NO>,
-							<SYSC_IDLE_SMART>;
-					ti,sysc-midle = <SYSC_IDLE_FORCE>,
-							<SYSC_IDLE_NO>,
-							<SYSC_IDLE_SMART>;
-					ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
-							 SYSC_OMAP2_ENAWAKEUP |
-							 SYSC_OMAP2_SOFTRESET |
-							 SYSC_OMAP2_AUTOIDLE)>;
-					ti,syss-mask = <1>;
-					clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
-					clock-names = "fck";
-					#address-cells = <1>;
-					#size-cells = <1>;
-					ranges = <0 0x1000 0x1000>;
-
-					dispc@0 {
-						compatible = "ti,omap5-dispc";
-						reg = <0 0x1000>;
-						interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-						clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
-						clock-names = "fck";
-					};
-				};
-
-				target-module@2000 {
-					compatible = "ti,sysc-omap2", "ti,sysc";
-					reg = <0x2000 0x4>,
-					      <0x2010 0x4>,
-					      <0x2014 0x4>;
-					reg-names = "rev", "sysc", "syss";
-					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-							<SYSC_IDLE_NO>,
-							<SYSC_IDLE_SMART>;
-					ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
-							 SYSC_OMAP2_AUTOIDLE)>;
-					ti,syss-mask = <1>;
-					clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
-					clock-names = "fck";
-					#address-cells = <1>;
-					#size-cells = <1>;
-					ranges = <0 0x2000 0x1000>;
-
-					rfbi: encoder@0  {
-						compatible = "ti,omap5-rfbi";
-						reg = <0 0x100>;
-						status = "disabled";
-						clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
-						clock-names = "fck", "ick";
-					};
-				};
-
-				target-module@5000 {
-					compatible = "ti,sysc-omap2", "ti,sysc";
-					reg = <0x5000 0x4>,
-					      <0x5010 0x4>,
-					      <0x5014 0x4>;
-					reg-names = "rev", "sysc", "syss";
-					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-							<SYSC_IDLE_NO>,
-							<SYSC_IDLE_SMART>;
-					ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
-							 SYSC_OMAP2_ENAWAKEUP |
-							 SYSC_OMAP2_SOFTRESET |
-							 SYSC_OMAP2_AUTOIDLE)>;
-					ti,syss-mask = <1>;
-					#address-cells = <1>;
-					#size-cells = <1>;
-					ranges = <0 0x5000 0x1000>;
-
-					dsi1: encoder@0 {
-						compatible = "ti,omap5-dsi";
-						reg = <0 0x200>,
-						      <0x200 0x40>,
-						      <0x300 0x40>;
-						reg-names = "proto", "phy", "pll";
-						interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
-						status = "disabled";
-						clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
-						clock-names = "fck";
-					};
-				};
-
-				target-module@9000 {
-					compatible = "ti,sysc-omap2", "ti,sysc";
-					reg = <0x9000 0x4>,
-					      <0x9010 0x4>,
-					      <0x9014 0x4>;
-					reg-names = "rev", "sysc", "syss";
-					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-							<SYSC_IDLE_NO>,
-							<SYSC_IDLE_SMART>;
-					ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
-							 SYSC_OMAP2_ENAWAKEUP |
-							 SYSC_OMAP2_SOFTRESET |
-							 SYSC_OMAP2_AUTOIDLE)>;
-					ti,syss-mask = <1>;
-					#address-cells = <1>;
-					#size-cells = <1>;
-					ranges = <0 0x9000 0x1000>;
-
-					dsi2: encoder@0 {
-						compatible = "ti,omap5-dsi";
-						reg = <0 0x200>,
-						      <0x200 0x40>,
-						      <0x300 0x40>;
-						reg-names = "proto", "phy", "pll";
-						interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-						status = "disabled";
-						clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
-						clock-names = "fck";
-					};
-				};
-
-				target-module@40000 {
-					compatible = "ti,sysc-omap4", "ti,sysc";
-					reg = <0x40000 0x4>,
-					      <0x40010 0x4>;
-					reg-names = "rev", "sysc";
-					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-							<SYSC_IDLE_NO>,
-							<SYSC_IDLE_SMART>,
-							<SYSC_IDLE_SMART_WKUP>;
-					ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
-					clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
-						 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
-					clock-names = "fck", "dss_clk";
-					#address-cells = <1>;
-					#size-cells = <1>;
-					ranges = <0 0x40000 0x40000>;
-
-					hdmi: encoder@0 {
-						compatible = "ti,omap5-hdmi";
-						reg = <0 0x200>,
-						      <0x200 0x80>,
-						      <0x300 0x80>,
-						      <0x20000 0x19000>;
-						reg-names = "wp", "pll", "phy", "core";
-						interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
-						status = "disabled";
-						clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
-							 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
-						clock-names = "fck", "sys_clk";
-						dmas = <&sdma 76>;
-						dma-names = "audio_tx";
-					};
-				};
-			};
-		};
-
-		abb_mpu: regulator-abb-mpu {
-			compatible = "ti,abb-v2";
-			regulator-name = "abb_mpu";
-			#address-cells = <0>;
-			#size-cells = <0>;
-			clocks = <&sys_clkin>;
-			ti,settling-time = <50>;
-			ti,clock-cycles = <16>;
-
-			reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
-			      <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
-			reg-names = "base-address", "int-address",
-				    "efuse-address", "ldo-address";
-			ti,tranxdone-status-mask = <0x80>;
-			/* LDOVBBMPU_MUX_CTRL */
-			ti,ldovbb-override-mask = <0x400>;
-			/* LDOVBBMPU_VSET_OUT */
-			ti,ldovbb-vset-mask = <0x1F>;
-
-			/*
-			 * NOTE: only FBB mode used but actual vset will
-			 * determine final biasing
-			 */
-			ti,abb_info = <
-			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
-			1060000		0	0x0	0 0x02000000 0x01F00000
-			1250000		0	0x4	0 0x02000000 0x01F00000
-			>;
-		};
-
-		abb_mm: regulator-abb-mm {
-			compatible = "ti,abb-v2";
-			regulator-name = "abb_mm";
-			#address-cells = <0>;
-			#size-cells = <0>;
-			clocks = <&sys_clkin>;
-			ti,settling-time = <50>;
-			ti,clock-cycles = <16>;
-
-			reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
-			      <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
-			reg-names = "base-address", "int-address",
-				    "efuse-address", "ldo-address";
-			ti,tranxdone-status-mask = <0x80000000>;
-			/* LDOVBBMM_MUX_CTRL */
-			ti,ldovbb-override-mask = <0x400>;
-			/* LDOVBBMM_VSET_OUT */
-			ti,ldovbb-vset-mask = <0x1F>;
-
-			/*
-			 * NOTE: only FBB mode used but actual vset will
-			 * determine final biasing
-			 */
-			ti,abb_info = <
-			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
-			1025000		0	0x0	0 0x02000000 0x01F00000
-			1120000		0	0x4	0 0x02000000 0x01F00000
-			>;
-		};
-	};
-};
-
-&cpu_thermal {
-	polling-delay = <500>; /* milliseconds */
-	coefficients = <65 (-1791)>;
-};
-
-#include "omap5-l4.dtsi"
-#include "omap54xx-clocks.dtsi"
-
-&gpu_thermal {
-	coefficients = <117 (-2992)>;
-};
-
-&core_thermal {
-	coefficients = <0 2000>;
-};
-
-#include "omap5-l4-abe.dtsi"
-#include "omap54xx-clocks.dtsi"
-
-&prm {
-	prm_dsp: prm@400 {
-		compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
-		reg = <0x400 0x100>;
-		#reset-cells = <1>;
-	};
-
-	prm_core: prm@700 {
-		compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
-		reg = <0x700 0x100>;
-		#reset-cells = <1>;
-	};
-
-	prm_iva: prm@1200 {
-		compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
-		reg = <0x1200 0x100>;
-		#reset-cells = <1>;
-	};
-
-	prm_device: prm@1c00 {
-		compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
-		reg = <0x1c00 0x100>;
-		#reset-cells = <1>;
-	};
-};
diff --git a/arch/arm/dts/omap54xx-clocks.dtsi b/arch/arm/dts/omap54xx-clocks.dtsi
deleted file mode 100644
index 42f2c44..0000000
--- a/arch/arm/dts/omap54xx-clocks.dtsi
+++ /dev/null
@@ -1,1208 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for OMAP5 clock data
- *
- * Copyright (C) 2013 Texas Instruments, Inc.
- */
-&cm_core_aon_clocks {
-	pad_clks_src_ck: pad_clks_src_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <12000000>;
-	};
-
-	pad_clks_ck: pad_clks_ck@108 {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&pad_clks_src_ck>;
-		ti,bit-shift = <8>;
-		reg = <0x0108>;
-	};
-
-	secure_32k_clk_src_ck: secure_32k_clk_src_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <32768>;
-	};
-
-	slimbus_src_clk: slimbus_src_clk {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <12000000>;
-	};
-
-	slimbus_clk: slimbus_clk@108 {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&slimbus_src_clk>;
-		ti,bit-shift = <10>;
-		reg = <0x0108>;
-	};
-
-	sys_32k_ck: sys_32k_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <32768>;
-	};
-
-	virt_12000000_ck: virt_12000000_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <12000000>;
-	};
-
-	virt_13000000_ck: virt_13000000_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <13000000>;
-	};
-
-	virt_16800000_ck: virt_16800000_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <16800000>;
-	};
-
-	virt_19200000_ck: virt_19200000_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <19200000>;
-	};
-
-	virt_26000000_ck: virt_26000000_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <26000000>;
-	};
-
-	virt_27000000_ck: virt_27000000_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <27000000>;
-	};
-
-	virt_38400000_ck: virt_38400000_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <38400000>;
-	};
-
-	xclk60mhsp1_ck: xclk60mhsp1_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <60000000>;
-	};
-
-	xclk60mhsp2_ck: xclk60mhsp2_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <60000000>;
-	};
-
-	dpll_abe_ck: dpll_abe_ck@1e0 {
-		#clock-cells = <0>;
-		compatible = "ti,omap4-dpll-m4xen-clock";
-		clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
-		reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
-	};
-
-	dpll_abe_x2_ck: dpll_abe_x2_ck {
-		#clock-cells = <0>;
-		compatible = "ti,omap4-dpll-x2-clock";
-		clocks = <&dpll_abe_ck>;
-	};
-
-	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_abe_x2_ck>;
-		ti,max-div = <31>;
-		reg = <0x01f0>;
-		ti,index-starts-at-one;
-	};
-
-	abe_24m_fclk: abe_24m_fclk {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&dpll_abe_m2x2_ck>;
-		clock-mult = <1>;
-		clock-div = <8>;
-	};
-
-	abe_clk: abe_clk@108 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_abe_m2x2_ck>;
-		ti,max-div = <4>;
-		reg = <0x0108>;
-		ti,index-power-of-two;
-	};
-
-	abe_iclk: abe_iclk@528 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&aess_fclk>;
-		ti,bit-shift = <24>;
-		reg = <0x0528>;
-		ti,dividers = <2>, <1>;
-	};
-
-	abe_lp_clk_div: abe_lp_clk_div {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&dpll_abe_m2x2_ck>;
-		clock-mult = <1>;
-		clock-div = <16>;
-	};
-
-	dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_abe_x2_ck>;
-		ti,max-div = <31>;
-		reg = <0x01f4>;
-		ti,index-starts-at-one;
-	};
-
-	dpll_core_byp_mux: dpll_core_byp_mux@12c {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
-		ti,bit-shift = <23>;
-		reg = <0x012c>;
-	};
-
-	dpll_core_ck: dpll_core_ck@120 {
-		#clock-cells = <0>;
-		compatible = "ti,omap4-dpll-core-clock";
-		clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
-		reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
-	};
-
-	dpll_core_x2_ck: dpll_core_x2_ck {
-		#clock-cells = <0>;
-		compatible = "ti,omap4-dpll-x2-clock";
-		clocks = <&dpll_core_ck>;
-	};
-
-	dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_core_x2_ck>;
-		ti,max-div = <63>;
-		reg = <0x0150>;
-		ti,index-starts-at-one;
-	};
-
-	c2c_fclk: c2c_fclk {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&dpll_core_h21x2_ck>;
-		clock-mult = <1>;
-		clock-div = <1>;
-	};
-
-	c2c_iclk: c2c_iclk {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&c2c_fclk>;
-		clock-mult = <1>;
-		clock-div = <2>;
-	};
-
-	dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_core_x2_ck>;
-		ti,max-div = <63>;
-		reg = <0x0138>;
-		ti,index-starts-at-one;
-	};
-
-	dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_core_x2_ck>;
-		ti,max-div = <63>;
-		reg = <0x013c>;
-		ti,index-starts-at-one;
-	};
-
-	dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_core_x2_ck>;
-		ti,max-div = <63>;
-		reg = <0x0140>;
-		ti,index-starts-at-one;
-	};
-
-	dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_core_x2_ck>;
-		ti,max-div = <63>;
-		reg = <0x0144>;
-		ti,index-starts-at-one;
-	};
-
-	dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_core_x2_ck>;
-		ti,max-div = <63>;
-		reg = <0x0154>;
-		ti,index-starts-at-one;
-	};
-
-	dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_core_x2_ck>;
-		ti,max-div = <63>;
-		reg = <0x0158>;
-		ti,index-starts-at-one;
-	};
-
-	dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_core_x2_ck>;
-		ti,max-div = <63>;
-		reg = <0x015c>;
-		ti,index-starts-at-one;
-	};
-
-	dpll_core_m2_ck: dpll_core_m2_ck@130 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_core_ck>;
-		ti,max-div = <31>;
-		reg = <0x0130>;
-		ti,index-starts-at-one;
-	};
-
-	dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_core_x2_ck>;
-		ti,max-div = <31>;
-		reg = <0x0134>;
-		ti,index-starts-at-one;
-	};
-
-	iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&dpll_core_h12x2_ck>;
-		clock-mult = <1>;
-		clock-div = <1>;
-	};
-
-	dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
-		ti,bit-shift = <23>;
-		reg = <0x01ac>;
-	};
-
-	dpll_iva_ck: dpll_iva_ck@1a0 {
-		#clock-cells = <0>;
-		compatible = "ti,omap4-dpll-clock";
-		clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
-		reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
-		assigned-clocks = <&dpll_iva_ck>;
-		assigned-clock-rates = <1165000000>;
-	};
-
-	dpll_iva_x2_ck: dpll_iva_x2_ck {
-		#clock-cells = <0>;
-		compatible = "ti,omap4-dpll-x2-clock";
-		clocks = <&dpll_iva_ck>;
-	};
-
-	dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_iva_x2_ck>;
-		ti,max-div = <63>;
-		reg = <0x01b8>;
-		ti,index-starts-at-one;
-		assigned-clocks = <&dpll_iva_h11x2_ck>;
-		assigned-clock-rates = <465920000>;
-	};
-
-	dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_iva_x2_ck>;
-		ti,max-div = <63>;
-		reg = <0x01bc>;
-		ti,index-starts-at-one;
-		assigned-clocks = <&dpll_iva_h12x2_ck>;
-		assigned-clock-rates = <388300000>;
-	};
-
-	mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&dpll_core_h12x2_ck>;
-		clock-mult = <1>;
-		clock-div = <1>;
-	};
-
-	dpll_mpu_ck: dpll_mpu_ck@160 {
-		#clock-cells = <0>;
-		compatible = "ti,omap5-mpu-dpll-clock";
-		clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
-		reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
-	};
-
-	dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_mpu_ck>;
-		ti,max-div = <31>;
-		reg = <0x0170>;
-		ti,index-starts-at-one;
-	};
-
-	per_dpll_hs_clk_div: per_dpll_hs_clk_div {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&dpll_abe_m3x2_ck>;
-		clock-mult = <1>;
-		clock-div = <2>;
-	};
-
-	usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&dpll_abe_m3x2_ck>;
-		clock-mult = <1>;
-		clock-div = <3>;
-	};
-
-	l3_iclk_div: l3_iclk_div@100 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		ti,max-div = <2>;
-		ti,bit-shift = <4>;
-		reg = <0x100>;
-		clocks = <&dpll_core_h12x2_ck>;
-		ti,index-power-of-two;
-	};
-
-	gpu_l3_iclk: gpu_l3_iclk {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&l3_iclk_div>;
-		clock-mult = <1>;
-		clock-div = <1>;
-	};
-
-	l4_root_clk_div: l4_root_clk_div@100 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		ti,max-div = <2>;
-		ti,bit-shift = <8>;
-		reg = <0x100>;
-		clocks = <&l3_iclk_div>;
-		ti,index-power-of-two;
-	};
-
-	slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&slimbus_clk>;
-		ti,bit-shift = <11>;
-		reg = <0x0560>;
-	};
-
-	aess_fclk: aess_fclk@528 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&abe_clk>;
-		ti,bit-shift = <24>;
-		ti,max-div = <2>;
-		reg = <0x0528>;
-	};
-
-	mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
-		ti,bit-shift = <26>;
-		reg = <0x0540>;
-	};
-
-	mcasp_gfclk: mcasp_gfclk@540 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
-		ti,bit-shift = <24>;
-		reg = <0x0540>;
-	};
-
-	dummy_ck: dummy_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <0>;
-	};
-};
-&prm_clocks {
-	sys_clkin: sys_clkin@110 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
-		reg = <0x0110>;
-		ti,index-starts-at-one;
-	};
-
-	abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&sys_clkin>, <&sys_32k_ck>;
-		reg = <0x0108>;
-	};
-
-	abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&sys_clkin>, <&sys_32k_ck>;
-		reg = <0x010c>;
-	};
-
-	custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&sys_clkin>;
-		clock-mult = <1>;
-		clock-div = <2>;
-	};
-
-	dss_syc_gfclk_div: dss_syc_gfclk_div {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&sys_clkin>;
-		clock-mult = <1>;
-		clock-div = <1>;
-	};
-
-	wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&sys_clkin>, <&abe_lp_clk_div>;
-		reg = <0x0108>;
-	};
-
-	l3instr_ts_gclk_div: l3instr_ts_gclk_div {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&wkupaon_iclk_mux>;
-		clock-mult = <1>;
-		clock-div = <1>;
-	};
-};
-
-&cm_core_clocks {
-
-	dpll_per_byp_mux: dpll_per_byp_mux@14c {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
-		ti,bit-shift = <23>;
-		reg = <0x014c>;
-	};
-
-	dpll_per_ck: dpll_per_ck@140 {
-		#clock-cells = <0>;
-		compatible = "ti,omap4-dpll-clock";
-		clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
-		reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
-	};
-
-	dpll_per_x2_ck: dpll_per_x2_ck {
-		#clock-cells = <0>;
-		compatible = "ti,omap4-dpll-x2-clock";
-		clocks = <&dpll_per_ck>;
-	};
-
-	dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_per_x2_ck>;
-		ti,max-div = <63>;
-		reg = <0x0158>;
-		ti,index-starts-at-one;
-	};
-
-	dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_per_x2_ck>;
-		ti,max-div = <63>;
-		reg = <0x015c>;
-		ti,index-starts-at-one;
-	};
-
-	dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_per_x2_ck>;
-		ti,max-div = <63>;
-		reg = <0x0164>;
-		ti,index-starts-at-one;
-	};
-
-	dpll_per_m2_ck: dpll_per_m2_ck@150 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_per_ck>;
-		ti,max-div = <31>;
-		reg = <0x0150>;
-		ti,index-starts-at-one;
-	};
-
-	dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_per_x2_ck>;
-		ti,max-div = <31>;
-		reg = <0x0150>;
-		ti,index-starts-at-one;
-	};
-
-	dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_per_x2_ck>;
-		ti,max-div = <31>;
-		reg = <0x0154>;
-		ti,index-starts-at-one;
-	};
-
-	dpll_unipro1_ck: dpll_unipro1_ck@200 {
-		#clock-cells = <0>;
-		compatible = "ti,omap4-dpll-clock";
-		clocks = <&sys_clkin>, <&sys_clkin>;
-		reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
-	};
-
-	dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&dpll_unipro1_ck>;
-		clock-mult = <1>;
-		clock-div = <1>;
-	};
-
-	dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_unipro1_ck>;
-		ti,max-div = <127>;
-		reg = <0x0210>;
-		ti,index-starts-at-one;
-	};
-
-	dpll_unipro2_ck: dpll_unipro2_ck@1c0 {
-		#clock-cells = <0>;
-		compatible = "ti,omap4-dpll-clock";
-		clocks = <&sys_clkin>, <&sys_clkin>;
-		reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
-	};
-
-	dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&dpll_unipro2_ck>;
-		clock-mult = <1>;
-		clock-div = <1>;
-	};
-
-	dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_unipro2_ck>;
-		ti,max-div = <127>;
-		reg = <0x01d0>;
-		ti,index-starts-at-one;
-	};
-
-	dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
-		ti,bit-shift = <23>;
-		reg = <0x018c>;
-	};
-
-	dpll_usb_ck: dpll_usb_ck@180 {
-		#clock-cells = <0>;
-		compatible = "ti,omap4-dpll-j-type-clock";
-		clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
-		reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
-	};
-
-	dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&dpll_usb_ck>;
-		clock-mult = <1>;
-		clock-div = <1>;
-	};
-
-	dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_usb_ck>;
-		ti,max-div = <127>;
-		reg = <0x0190>;
-		ti,index-starts-at-one;
-	};
-
-	func_128m_clk: func_128m_clk {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&dpll_per_h11x2_ck>;
-		clock-mult = <1>;
-		clock-div = <2>;
-	};
-
-	func_12m_fclk: func_12m_fclk {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&dpll_per_m2x2_ck>;
-		clock-mult = <1>;
-		clock-div = <16>;
-	};
-
-	func_24m_clk: func_24m_clk {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&dpll_per_m2_ck>;
-		clock-mult = <1>;
-		clock-div = <4>;
-	};
-
-	func_48m_fclk: func_48m_fclk {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&dpll_per_m2x2_ck>;
-		clock-mult = <1>;
-		clock-div = <4>;
-	};
-
-	func_96m_fclk: func_96m_fclk {
-		#clock-cells = <0>;
-		compatible = "fixed-factor-clock";
-		clocks = <&dpll_per_m2x2_ck>;
-		clock-mult = <1>;
-		clock-div = <2>;
-	};
-
-	l3init_60m_fclk: l3init_60m_fclk@104 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_usb_m2_ck>;
-		reg = <0x0104>;
-		ti,dividers = <1>, <8>;
-	};
-
-	iss_ctrlclk: iss_ctrlclk@1320 {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&func_96m_fclk>;
-		ti,bit-shift = <8>;
-		reg = <0x1320>;
-	};
-
-	lli_txphy_clk: lli_txphy_clk@f20 {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&dpll_unipro1_clkdcoldo>;
-		ti,bit-shift = <8>;
-		reg = <0x0f20>;
-	};
-
-	lli_txphy_ls_clk: lli_txphy_ls_clk@f20 {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&dpll_unipro1_m2_ck>;
-		ti,bit-shift = <9>;
-		reg = <0x0f20>;
-	};
-
-	usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&sys_32k_ck>;
-		ti,bit-shift = <8>;
-		reg = <0x0640>;
-	};
-
-	fdif_fclk: fdif_fclk@1328 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_per_h11x2_ck>;
-		ti,bit-shift = <24>;
-		ti,max-div = <2>;
-		reg = <0x1328>;
-	};
-
-	gpu_core_gclk_mux: gpu_core_gclk_mux@1520 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
-		ti,bit-shift = <24>;
-		reg = <0x1520>;
-	};
-
-	gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
-		ti,bit-shift = <25>;
-		reg = <0x1520>;
-	};
-
-	hsi_fclk: hsi_fclk@1638 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_per_m2x2_ck>;
-		ti,bit-shift = <24>;
-		ti,max-div = <2>;
-		reg = <0x1638>;
-	};
-};
-
-&cm_core_clockdomains {
-	l3init_clkdm: l3init_clkdm {
-		compatible = "ti,clockdomain";
-		clocks = <&dpll_usb_ck>;
-	};
-};
-
-&scrm_clocks {
-	auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
-		#clock-cells = <0>;
-		compatible = "ti,composite-no-wait-gate-clock";
-		clocks = <&dpll_core_m3x2_ck>;
-		ti,bit-shift = <8>;
-		reg = <0x0310>;
-	};
-
-	auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
-		#clock-cells = <0>;
-		compatible = "ti,composite-mux-clock";
-		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
-		ti,bit-shift = <1>;
-		reg = <0x0310>;
-	};
-
-	auxclk0_src_ck: auxclk0_src_ck {
-		#clock-cells = <0>;
-		compatible = "ti,composite-clock";
-		clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
-	};
-
-	auxclk0_ck: auxclk0_ck@310 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&auxclk0_src_ck>;
-		ti,bit-shift = <16>;
-		ti,max-div = <16>;
-		reg = <0x0310>;
-	};
-
-	auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
-		#clock-cells = <0>;
-		compatible = "ti,composite-no-wait-gate-clock";
-		clocks = <&dpll_core_m3x2_ck>;
-		ti,bit-shift = <8>;
-		reg = <0x0314>;
-	};
-
-	auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
-		#clock-cells = <0>;
-		compatible = "ti,composite-mux-clock";
-		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
-		ti,bit-shift = <1>;
-		reg = <0x0314>;
-	};
-
-	auxclk1_src_ck: auxclk1_src_ck {
-		#clock-cells = <0>;
-		compatible = "ti,composite-clock";
-		clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
-	};
-
-	auxclk1_ck: auxclk1_ck@314 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&auxclk1_src_ck>;
-		ti,bit-shift = <16>;
-		ti,max-div = <16>;
-		reg = <0x0314>;
-	};
-
-	auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
-		#clock-cells = <0>;
-		compatible = "ti,composite-no-wait-gate-clock";
-		clocks = <&dpll_core_m3x2_ck>;
-		ti,bit-shift = <8>;
-		reg = <0x0318>;
-	};
-
-	auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
-		#clock-cells = <0>;
-		compatible = "ti,composite-mux-clock";
-		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
-		ti,bit-shift = <1>;
-		reg = <0x0318>;
-	};
-
-	auxclk2_src_ck: auxclk2_src_ck {
-		#clock-cells = <0>;
-		compatible = "ti,composite-clock";
-		clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
-	};
-
-	auxclk2_ck: auxclk2_ck@318 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&auxclk2_src_ck>;
-		ti,bit-shift = <16>;
-		ti,max-div = <16>;
-		reg = <0x0318>;
-	};
-
-	auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
-		#clock-cells = <0>;
-		compatible = "ti,composite-no-wait-gate-clock";
-		clocks = <&dpll_core_m3x2_ck>;
-		ti,bit-shift = <8>;
-		reg = <0x031c>;
-	};
-
-	auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
-		#clock-cells = <0>;
-		compatible = "ti,composite-mux-clock";
-		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
-		ti,bit-shift = <1>;
-		reg = <0x031c>;
-	};
-
-	auxclk3_src_ck: auxclk3_src_ck {
-		#clock-cells = <0>;
-		compatible = "ti,composite-clock";
-		clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
-	};
-
-	auxclk3_ck: auxclk3_ck@31c {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&auxclk3_src_ck>;
-		ti,bit-shift = <16>;
-		ti,max-div = <16>;
-		reg = <0x031c>;
-	};
-
-	auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
-		#clock-cells = <0>;
-		compatible = "ti,composite-no-wait-gate-clock";
-		clocks = <&dpll_core_m3x2_ck>;
-		ti,bit-shift = <8>;
-		reg = <0x0320>;
-	};
-
-	auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
-		#clock-cells = <0>;
-		compatible = "ti,composite-mux-clock";
-		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
-		ti,bit-shift = <1>;
-		reg = <0x0320>;
-	};
-
-	auxclk4_src_ck: auxclk4_src_ck {
-		#clock-cells = <0>;
-		compatible = "ti,composite-clock";
-		clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
-	};
-
-	auxclk4_ck: auxclk4_ck@320 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&auxclk4_src_ck>;
-		ti,bit-shift = <16>;
-		ti,max-div = <16>;
-		reg = <0x0320>;
-	};
-
-	auxclkreq0_ck: auxclkreq0_ck@210 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
-		ti,bit-shift = <2>;
-		reg = <0x0210>;
-	};
-
-	auxclkreq1_ck: auxclkreq1_ck@214 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
-		ti,bit-shift = <2>;
-		reg = <0x0214>;
-	};
-
-	auxclkreq2_ck: auxclkreq2_ck@218 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
-		ti,bit-shift = <2>;
-		reg = <0x0218>;
-	};
-
-	auxclkreq3_ck: auxclkreq3_ck@21c {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
-		ti,bit-shift = <2>;
-		reg = <0x021c>;
-	};
-};
-
-&cm_core_aon {
-	mpu_cm: mpu_cm@300 {
-		compatible = "ti,omap4-cm";
-		reg = <0x300 0x100>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x300 0x100>;
-
-		mpu_clkctrl: clk@20 {
-			compatible = "ti,clkctrl";
-			reg = <0x20 0x4>;
-			#clock-cells = <2>;
-		};
-	};
-
-	dsp_cm: dsp_cm@400 {
-		compatible = "ti,omap4-cm";
-		reg = <0x400 0x100>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x400 0x100>;
-
-		dsp_clkctrl: clk@20 {
-			compatible = "ti,clkctrl";
-			reg = <0x20 0x4>;
-			#clock-cells = <2>;
-		};
-	};
-
-	abe_cm: abe_cm@500 {
-		compatible = "ti,omap4-cm";
-		reg = <0x500 0x100>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x500 0x100>;
-
-		abe_clkctrl: clk@20 {
-			compatible = "ti,clkctrl";
-			reg = <0x20 0x64>;
-			#clock-cells = <2>;
-		};
-	};
-
-};
-
-&cm_core {
-	l3main1_cm: l3main1_cm@700 {
-		compatible = "ti,omap4-cm";
-		reg = <0x700 0x100>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x700 0x100>;
-
-		l3main1_clkctrl: clk@20 {
-			compatible = "ti,clkctrl";
-			reg = <0x20 0x4>;
-			#clock-cells = <2>;
-		};
-	};
-
-	l3main2_cm: l3main2_cm@800 {
-		compatible = "ti,omap4-cm";
-		reg = <0x800 0x100>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x800 0x100>;
-
-		l3main2_clkctrl: clk@20 {
-			compatible = "ti,clkctrl";
-			reg = <0x20 0x4>;
-			#clock-cells = <2>;
-		};
-	};
-
-	ipu_cm: ipu_cm@900 {
-		compatible = "ti,omap4-cm";
-		reg = <0x900 0x100>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x900 0x100>;
-
-		ipu_clkctrl: clk@20 {
-			compatible = "ti,clkctrl";
-			reg = <0x20 0x4>;
-			#clock-cells = <2>;
-		};
-	};
-
-	dma_cm: dma_cm@a00 {
-		compatible = "ti,omap4-cm";
-		reg = <0xa00 0x100>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0xa00 0x100>;
-
-		dma_clkctrl: clk@20 {
-			compatible = "ti,clkctrl";
-			reg = <0x20 0x4>;
-			#clock-cells = <2>;
-		};
-	};
-
-	emif_cm: emif_cm@b00 {
-		compatible = "ti,omap4-cm";
-		reg = <0xb00 0x100>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0xb00 0x100>;
-
-		emif_clkctrl: clk@20 {
-			compatible = "ti,clkctrl";
-			reg = <0x20 0x1c>;
-			#clock-cells = <2>;
-		};
-	};
-
-	l4cfg_cm: l4cfg_cm@d00 {
-		compatible = "ti,omap4-cm";
-		reg = <0xd00 0x100>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0xd00 0x100>;
-
-		l4cfg_clkctrl: clk@20 {
-			compatible = "ti,clkctrl";
-			reg = <0x20 0x14>;
-			#clock-cells = <2>;
-		};
-	};
-
-	l3instr_cm: l3instr_cm@e00 {
-		compatible = "ti,omap4-cm";
-		reg = <0xe00 0x100>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0xe00 0x100>;
-
-		l3instr_clkctrl: clk@20 {
-			compatible = "ti,clkctrl";
-			reg = <0x20 0xc>;
-			#clock-cells = <2>;
-		};
-	};
-
-	l4per_cm: l4per_cm@1000 {
-		compatible = "ti,omap4-cm";
-		reg = <0x1000 0x200>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x1000 0x200>;
-
-		l4per_clkctrl: clock@20 {
-			compatible = "ti,clkctrl-l4per", "ti,clkctrl";
-			reg = <0x20 0x15c>;
-			#clock-cells = <2>;
-		};
-
-		l4sec_clkctrl: clock@1a0 {
-			compatible = "ti,clkctrl-l4sec", "ti,clkctrl";
-			reg = <0x1a0 0x3c>;
-			#clock-cells = <2>;
-		};
-	};
-
-	dss_cm: dss_cm@1400 {
-		compatible = "ti,omap4-cm";
-		reg = <0x1400 0x100>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x1400 0x100>;
-
-		dss_clkctrl: clk@20 {
-			compatible = "ti,clkctrl";
-			reg = <0x20 0x4>;
-			#clock-cells = <2>;
-		};
-	};
-
-	gpu_cm: gpu_cm@1500 {
-		compatible = "ti,omap4-cm";
-		reg = <0x1500 0x100>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x1500 0x100>;
-
-		gpu_clkctrl: clk@20 {
-			compatible = "ti,clkctrl";
-			reg = <0x20 0x4>;
-			#clock-cells = <2>;
-		};
-	};
-
-	l3init_cm: l3init_cm@1600 {
-		compatible = "ti,omap4-cm";
-		reg = <0x1600 0x100>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x1600 0x100>;
-
-		l3init_clkctrl: clk@20 {
-			compatible = "ti,clkctrl";
-			reg = <0x20 0xd4>;
-			#clock-cells = <2>;
-		};
-	};
-};
-
-&prm {
-	wkupaon_cm: wkupaon_cm@1900 {
-		compatible = "ti,omap4-cm";
-		reg = <0x1900 0x100>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x1900 0x100>;
-
-		wkupaon_clkctrl: clk@20 {
-			compatible = "ti,clkctrl";
-			reg = <0x20 0x5c>;
-			#clock-cells = <2>;
-		};
-	};
-};
-
-&scm_wkup_pad_conf_clocks {
-	fref_xtal_ck: fref_xtal_ck {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&sys_clkin>;
-		ti,bit-shift = <28>;
-		reg = <0x14>;
-	};
-};
diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index 607af27..3b86b93 100644
--- a/arch/arm/dts/sdm845.dtsi
+++ b/arch/arm/dts/sdm845.dtsi
@@ -51,16 +51,21 @@
 			};
 		};
 
-		debug_uart: serial@a84000 {
-			compatible = "qcom,msm-geni-uart";
-			reg = <0xa84000 0x4000>;
-			reg-names = "se_phys";
-			clock-names = "se-clk";
-			clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&qup_uart9>;
-			qcom,wrapper-core = <0x8a>;
-			status = "disabled";
+		qupv3_id_1: geniqup@ac0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x00ac0000 0x6000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			uart9: serial@a84000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0xa84000 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart9>;
+			};
 		};
 
 		spmi@c440000 {
diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts
index 34a4f59..eec51d1 100644
--- a/arch/arm/dts/starqltechn.dts
+++ b/arch/arm/dts/starqltechn.dts
@@ -9,6 +9,8 @@
 /dts-v1/;
 
 #include "sdm845.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 
 / {
 	model = "Samsung S9 (SM-G9600)";
@@ -21,7 +23,7 @@
 	};
 
 	aliases {
-		serial0 = &debug_uart;
+		serial0 = &uart9;
 	};
 
 	memory {
@@ -43,6 +45,22 @@
 		format = "a8r8g8b8";
 	};
 
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		key-pwr {
+			label = "Power";
+			linux,code = <KEY_ENTER>;
+			gpios = <&pm8998_pon 0 GPIO_ACTIVE_LOW>;
+		};
+
+		key-vol-down {
+			label = "Volume Down";
+			linux,code = <KEY_DOWN>;
+			gpios = <&pm8998_pon 1 GPIO_ACTIVE_LOW>;
+		};
+	};
+
 	soc: soc {
 		serial@a84000 {
 			status = "okay";
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
index e959eb2..af419c7 100644
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -29,6 +29,11 @@
 		pad-byte = <0xff>;
 
 		blob {
+			/*
+			 * This value matches SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
+			 * and SYS_SPI_U_BOOT_OFFS if those are defined.
+			 */
+			min-size = <0x8000>;
 			filename = "spl/sunxi-spl.bin";
 		};
 
@@ -105,7 +110,6 @@
 		};
 #else
 		u-boot-img {
-			offset = <CONFIG_SPL_PAD_TO>;
 		};
 #endif
 	};
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 8ae4971..81af89c 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -41,6 +41,8 @@
 	MXC_SATA_CLK,
 	MXC_NFC_CLK,
 	MXC_I2C_CLK,
+	MXC_LCDIF1_CLK,
+	MXC_LCDIF2_CLK,
 };
 
 enum ldb_di_clock {
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 437e864..6eaeece 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -209,7 +209,6 @@
 
 /* Virtual AXP0 GPIOs */
 #define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
-#define SUNXI_GPIO_AXP0_VBUS_DETECT	4
 #define SUNXI_GPIO_AXP0_VBUS_ENABLE	5
 #define SUNXI_GPIO_AXP0_GPIO_COUNT	6
 
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 9f58ced..19a9e11 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -49,10 +49,13 @@
 #define PTE_TYPE_BLOCK		(1 << 0)
 #define PTE_TYPE_VALID		(1 << 0)
 
-#define PTE_TABLE_PXN		(1UL << 59)
-#define PTE_TABLE_XN		(1UL << 60)
-#define PTE_TABLE_AP		(1UL << 61)
-#define PTE_TABLE_NS		(1UL << 63)
+#define PTE_RDONLY		BIT(7)
+#define PTE_DBM			BIT(51)
+
+#define PTE_TABLE_PXN		BIT(59)
+#define PTE_TABLE_XN		BIT(60)
+#define PTE_TABLE_AP		BIT(61)
+#define PTE_TABLE_NS		BIT(63)
 
 /*
  * Block
@@ -99,6 +102,15 @@
 #define TCR_TG0_16K		(2 << 14)
 #define TCR_EPD1_DISABLE	(1 << 23)
 
+#define TCR_EL1_HA		BIT(39)
+#define TCR_EL1_HD		BIT(40)
+
+#define TCR_EL2_HA		BIT(21)
+#define TCR_EL2_HD		BIT(22)
+
+#define TCR_EL3_HA		BIT(21)
+#define TCR_EL3_HD		BIT(22)
+
 #define TCR_EL1_RSVD		(1U << 31)
 #define TCR_EL2_RSVD		(1U << 31 | 1 << 23)
 #define TCR_EL3_RSVD		(1U << 31 | 1 << 23)
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 8698783..0c13075 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -52,6 +52,8 @@
 #if defined(CONFIG_ARM64)
 	unsigned long tlb_fillptr;
 	unsigned long tlb_emerg;
+	unsigned int first_block_level;
+	bool has_hafdbs;
 #endif
 #endif
 #ifdef CFG_SYS_MEM_RESERVE_SECURE
diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c
index 2e09141..125dc0b 100644
--- a/arch/arm/lib/interrupts_64.c
+++ b/arch/arm/lib/interrupts_64.c
@@ -37,6 +37,40 @@
 	efi_print_image_infos((void *)regs->elr);
 }
 
+static void dump_far(unsigned long esr)
+{
+	unsigned long el, far;
+
+	switch ((esr >> 26) & 0b111111) {
+	case 0x20:
+	case 0x21:
+	case 0x24:
+	case 0x25:
+	case 0x22:
+	case 0x34:
+	case 0x35:
+		break;
+	default:
+		return;
+	}
+
+	asm("mrs	%0, CurrentEl": "=r" (el));
+
+	switch (el >> 2) {
+	case 1:
+		asm("mrs	%0, FAR_EL1": "=r" (far));
+		break;
+	case 2:
+		asm("mrs	%0, FAR_EL2": "=r" (far));
+		break;
+	default:
+		/* don't print anything to make output pretty */
+		return;
+	}
+
+	printf(", far 0x%lx", far);
+}
+
 static void dump_instr(struct pt_regs *regs)
 {
 	u32 *addr = (u32 *)(regs->elr & ~3UL);
@@ -165,7 +199,9 @@
 	    smh_emulate_trap(pt_regs))
 		return;
 	efi_restore_gd();
-	printf("\"Synchronous Abort\" handler, esr 0x%08lx\n", pt_regs->esr);
+	printf("\"Synchronous Abort\" handler, esr 0x%08lx", pt_regs->esr);
+	dump_far(pt_regs->esr);
+	printf("\n");
 	show_regs(pt_regs);
 	show_efi_loaded_images(pt_regs);
 	panic("Resetting CPU ...\n");
diff --git a/arch/arm/mach-histb/Kconfig b/arch/arm/mach-histb/Kconfig
new file mode 100644
index 0000000..012dbfe
--- /dev/null
+++ b/arch/arm/mach-histb/Kconfig
@@ -0,0 +1,39 @@
+if ARCH_HISTB
+
+choice
+	prompt "Select a HiSTB SoC"
+
+config ARCH_HI3798MV2X
+	bool "Hi3798M V2XX series SoC"
+	select ARM64
+	help
+	  Support for Hi3798MV2XX series SoCs.
+
+endchoice
+
+if ARCH_HI3798MV2X
+
+choice
+	prompt "Select a Hi3798M V2XX based board"
+
+config TARGET_HC2910_2AGHD05
+	bool "Skyworth HC2910 with board label 2AGHD05"
+	help
+	  Support for Skyworth HC2910 with board label 2AGHD05. This board features:
+	  - Hisilicon Hi3798MV200 SoC (4xCortex-A53, Mali MP-450)
+	  - 2GiB DRAM
+	  - 8GiB eMMC, uSD slot
+	  - Wifi and Bluetooth module
+	  - 1x USB 2.0, 1x USB 3.0 host port
+	  - HDMI
+	  - SCI
+	  - 3 LED - power, Wifi, Lock(?)
+	  - 1x Fast Ethernet Controller, 1x GBe Ethernet Controller
+
+endchoice
+
+endif
+
+source "board/skyworth/hc2910-2aghd05/Kconfig"
+
+endif
diff --git a/arch/arm/mach-histb/Makefile b/arch/arm/mach-histb/Makefile
new file mode 100644
index 0000000..7975c0f
--- /dev/null
+++ b/arch/arm/mach-histb/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier:	GPL-2.0+
+
+obj-y += sysmap-histb.o
+obj-y += board_common.o
diff --git a/arch/arm/mach-histb/board_common.c b/arch/arm/mach-histb/board_common.c
new file mode 100644
index 0000000..a26c206
--- /dev/null
+++ b/arch/arm/mach-histb/board_common.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board init file for all histb boards
+ *
+ * (C) Copyright 2023 Yang Xiwen <forbidden405@outlook.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/system.h>
+
+int __weak board_init(void)
+{
+	return 0;
+}
+
+int __weak dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+int __weak dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+void __weak reset_cpu(void)
+{
+	psci_system_reset();
+}
diff --git a/arch/arm/mach-histb/sysmap-histb.c b/arch/arm/mach-histb/sysmap-histb.c
new file mode 100644
index 0000000..83a2bb9
--- /dev/null
+++ b/arch/arm/mach-histb/sysmap-histb.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hisilicon HiSTB memory map
+ *
+ * (C) Copyright 2023 Yang Xiwen <forbidden405@outlook.com>
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region histb_mem_map[] = {
+	{
+		.virt = 0x0UL, /* DRAM */
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x80000000UL, /* Peripheral block */
+		.phys = 0x80000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* Terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = histb_mem_map;
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 018b87b..15f844f 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -91,6 +91,13 @@
 	select SUPPORT_SPL
 	select IMX8QM
 
+config TARGET_IMX8QM_DMSSE20_A1
+	bool "Support i.MX8QM DMS-SE20-A1 board"
+	select BINMAN
+	select BOARD_LATE_INIT
+	select SUPPORT_SPL
+	select IMX8QM
+
 config TARGET_IMX8QXP_MEK
 	bool "Support i.MX8QXP MEK board"
 	select BINMAN
@@ -105,6 +112,7 @@
 source "board/freescale/imx8qm_mek/Kconfig"
 source "board/freescale/imx8qxp_mek/Kconfig"
 source "board/congatec/cgtqmx8/Kconfig"
+source "board/advantech/imx8qm_dmsse20_a1/Kconfig"
 source "board/advantech/imx8qm_rom7720_a1/Kconfig"
 source "board/toradex/apalis-imx8/Kconfig"
 source "board/toradex/colibri-imx8x/Kconfig"
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index dc51f97..7639439 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -60,6 +60,12 @@
 	select IMX8MQ
 	select IMX8M_LPDDR4
 
+config TARGET_IMX8MQ_REFORM2
+	bool "imx8mq_reform2"
+	select BINMAN
+	select IMX8MQ
+	select IMX8M_LPDDR4
+
 config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
 	bool "Data Modul eDM SBC i.MX8M Mini"
 	select BINMAN
@@ -362,6 +368,7 @@
 source "board/kontron/sl-mx8mm/Kconfig"
 source "board/menlo/mx8menlo/Kconfig"
 source "board/msc/sm2s_imx8mp/Kconfig"
+source "board/mntre/imx8mq_reform2/Kconfig"
 source "board/phytec/phycore_imx8mm/Kconfig"
 source "board/phytec/phycore_imx8mp/Kconfig"
 source "board/purism/librem5/Kconfig"
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index df865e9..4705e6c 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -914,6 +914,8 @@
 
 	if (cnt != 7)
 		printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt);
+	if (cnt < 2)
+		return -1;
 
 	assignedclks[cnt - 1] = 200000000;
 	assignedclks[cnt - 2] = 200000000;
@@ -1395,40 +1397,6 @@
 }
 #endif
 
-#ifdef CONFIG_OF_BOARD_FIXUP
-#ifndef CONFIG_SPL_BUILD
-int board_fix_fdt(void *fdt)
-{
-	if (is_imx8mpul()) {
-		int i = 0;
-		int nodeoff, ret;
-		const char *status = "disabled";
-		static const char * const dsi_nodes[] = {
-			"/soc@0/bus@32c00000/mipi_dsi@32e60000",
-			"/soc@0/bus@32c00000/lcd-controller@32e80000",
-			"/dsi-host"
-		};
-
-		for (i = 0; i < ARRAY_SIZE(dsi_nodes); i++) {
-			nodeoff = fdt_path_offset(fdt, dsi_nodes[i]);
-			if (nodeoff > 0) {
-set_status:
-				ret = fdt_setprop(fdt, nodeoff, "status", status,
-						  strlen(status) + 1);
-				if (ret == -FDT_ERR_NOSPACE) {
-					ret = fdt_increase_size(fdt, 512);
-					if (!ret)
-						goto set_status;
-				}
-			}
-		}
-	}
-
-	return 0;
-}
-#endif
-#endif
-
 #if !CONFIG_IS_ENABLED(SYSRESET)
 void reset_cpu(void)
 {
diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
index cb9d629..1bdc568 100644
--- a/arch/arm/mach-imx/mx6/clock.c
+++ b/arch/arm/mach-imx/mx6/clock.c
@@ -213,6 +213,7 @@
 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 {
 	u32 div, test_div, pll_num, pll_denom;
+	u64 temp64;
 
 	switch (pll) {
 	case PLL_SYS:
@@ -272,7 +273,10 @@
 		}
 		test_div = 1 << (2 - test_div);
 
-		return infreq * (div + pll_num / pll_denom) / test_div;
+		temp64 = (u64)infreq;
+		temp64 *= pll_num;
+		do_div(temp64, pll_denom);
+		return infreq * div + (unsigned long)temp64;
 	default:
 		return 0;
 	}
@@ -414,6 +418,60 @@
 	return freq / (uart_podf + 1);
 }
 
+static u32 get_lcd_clk(unsigned int ifnum)
+{
+	u32 pll_rate;
+	u32 pred, postd;
+
+	if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
+	    !is_mx6sll()) {
+		debug("This chip does't support lcd\n");
+		return 0;
+	}
+
+	pll_rate = decode_pll(PLL_VIDEO, MXC_HCLK);
+	if (ifnum == 1) {
+		if (!is_mx6sl()) {
+			pred = __raw_readl(&imx_ccm->cscdr2);
+			pred &= MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK;
+			pred = pred >> MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET;
+
+			postd = readl(&imx_ccm->cbcmr);
+			postd &= MXC_CCM_CBCMR_LCDIF1_PODF_MASK;
+			postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET;
+		} else {
+			pred = __raw_readl(&imx_ccm->cscdr2);
+			pred &= MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK;
+			pred = pred >> MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET;
+
+			postd = readl(&imx_ccm->cscmr1);
+			postd &= MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET;
+			postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET;
+		}
+	} else if (ifnum == 2) {
+		if (is_mx6sx()) {
+			pred = __raw_readl(&imx_ccm->cscdr2);
+			pred &= MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK;
+			pred = pred >> MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET;
+
+			postd = readl(&imx_ccm->cscmr1);
+			postd &= MXC_CCM_CSCMR1_LCDIF2_PODF_MASK;
+			postd = postd >> MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET;
+
+		} else {
+			goto if_err;
+		}
+	} else {
+		goto if_err;
+	}
+
+	return DIV_ROUND_UP_ULL((u64)pll_rate, (postd + 1) * (pred + 1));
+
+if_err:
+	debug("This chip not support lcd iterface %d\n", ifnum);
+	return 0;
+}
+
 static u32 get_cspi_clk(void)
 {
 	u32 reg, cspi_podf;
@@ -744,6 +802,7 @@
 		}
 
 		enable_lcdif_clock(base_addr, 1);
+		debug("pixel clock = %u\n", mxc_get_clock(MXC_LCDIF1_CLK));
 	} else if (is_mx6sx()) {
 		/* Setting LCDIF2 for i.MX6SX */
 		if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
@@ -765,6 +824,7 @@
 				 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
 
 		enable_lcdif_clock(base_addr, 1);
+		debug("pixel clock = %u\n", mxc_get_clock(MXC_LCDIF2_CLK));
 	}
 }
 
@@ -1269,6 +1329,10 @@
 		return get_usdhc_clk(3);
 	case MXC_SATA_CLK:
 		return get_ahb_clk();
+	case MXC_LCDIF1_CLK:
+		return get_lcd_clk(1);
+	case MXC_LCDIF2_CLK:
+		return get_lcd_clk(2);
 	default:
 		printf("Unsupported MXC CLK: %d\n", clk);
 		break;
diff --git a/arch/arm/mach-imx/romapi.c b/arch/arm/mach-imx/romapi.c
index b49e7f8..ff0522c 100644
--- a/arch/arm/mach-imx/romapi.c
+++ b/arch/arm/mach-imx/romapi.c
@@ -70,6 +70,8 @@
 		boot_dev = SPI_NOR_BOOT;
 		break;
 	case BT_DEV_TYPE_USB:
+		if (!is_imx8ulp() && !is_imx9())
+			boot_instance = 0;
 		boot_dev = boot_instance + USB_BOOT;
 		break;
 	default:
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 7edbac2..0ffbbf9 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -52,7 +52,7 @@
 config SYS_K3_MCU_SCRATCHPAD_BASE
 	hex
 	default 0x40280000 if SOC_K3_AM654
-	default 0x40280000 if SOC_K3_J721E || SOC_K3_J721S2
+	default 0x41cff9fc if SOC_K3_J721E || SOC_K3_J721S2
 	help
 	  Describes the base address of MCU Scratchpad RAM.
 
@@ -187,11 +187,6 @@
 	help
 	  SWRV for X509 certificate used for boot images
 
-config K3_BOARD_DETECT
-	bool "Support for Board detection"
-	help
-	   Support for board detection.
-
 source "board/ti/am65x/Kconfig"
 source "board/ti/am64x/Kconfig"
 source "board/ti/am62x/Kconfig"
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
index a91c15c..026c4f9 100644
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am625_init.c
@@ -9,7 +9,7 @@
 #include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/sysfw-loader.h>
+#include "sysfw-loader.h"
 #include "common.h"
 #include <dm.h>
 #include <dm/uclass-internal.h>
diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c
index 02da24a..1f51b04 100644
--- a/arch/arm/mach-k3/am62a7_init.c
+++ b/arch/arm/mach-k3/am62a7_init.c
@@ -8,7 +8,7 @@
 #include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/sysfw-loader.h>
+#include "sysfw-loader.h"
 #include "common.h"
 #include <dm.h>
 #include <dm/uclass-internal.h>
@@ -65,6 +65,20 @@
 	mmr_unlock(PADCFG_MMR1_BASE, 1);
 }
 
+#if (IS_ENABLED(CONFIG_CPU_V7R))
+static void setup_qos(void)
+{
+	u32 i;
+
+	for (i = 0; i < am62a_qos_count; i++)
+		writel(am62a_qos_data[i].val, (uintptr_t)am62a_qos_data[i].reg);
+}
+#else
+static void setup_qos(void)
+{
+}
+#endif
+
 void board_init_f(ulong dummy)
 {
 	struct udevice *dev;
@@ -158,6 +172,8 @@
 		panic("DRAM init failed: %d\n", ret);
 #endif
 
+	setup_qos();
+
 	printf("am62a_init: %s done\n", __func__);
 }
 
diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile
index c58e52d..02a9418 100644
--- a/arch/arm/mach-k3/am62ax/Makefile
+++ b/arch/arm/mach-k3/am62ax/Makefile
@@ -4,3 +4,4 @@
 
 obj-y += clk-data.o
 obj-y += dev-data.o
+obj-y += am62a_qos_data.o
diff --git a/arch/arm/mach-k3/am62ax/am62a_qos_data.c b/arch/arm/mach-k3/am62ax/am62a_qos_data.c
new file mode 100644
index 0000000..01b76f7
--- /dev/null
+++ b/arch/arm/mach-k3/am62ax/am62a_qos_data.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am62a Quality of Service (QoS) Configuration Data
+ * Auto generated from K3 Resource Partitioning tool
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include "common.h"
+
+struct k3_qos_data am62a_qos_data[] = {
+	/* modules_qosConfig0 - 1 endpoints, 4 channels */
+	{
+		.reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0,
+		.val = ORDERID_8,
+	},
+	{
+		.reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 1,
+		.val = ORDERID_8,
+	},
+	{
+		.reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 2,
+		.val = ORDERID_8,
+	},
+	{
+		.reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 3,
+		.val = ORDERID_8,
+	},
+
+	/* Following registers set 1:1 mapping for orderID MAP1/MAP2
+	 * remap registers. orderID x is remapped to orderID x again
+	 * This is to ensure orderID from MAP register is unchanged
+	 */
+
+	/* K3_DSS_UL_MAIN_0_VBUSM_DMA - 1 groups */
+	{
+		.reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0,
+		.val = 0x76543210,
+	},
+	{
+		.reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 4,
+		.val = 0xfedcba98,
+	},
+};
+
+uint32_t am62a_qos_count = sizeof(am62a_qos_data) / sizeof(am62a_qos_data[0]);
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index 1bf7e16..c871e92 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -12,19 +12,23 @@
 #include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/sysfw-loader.h>
-#include <asm/arch/sys_proto.h>
+#include "sysfw-loader.h"
 #include "common.h"
-#include <asm/arch/sys_proto.h>
 #include <linux/soc/ti/ti_sci_protocol.h>
 #include <dm.h>
 #include <dm/uclass-internal.h>
 #include <dm/pinctrl.h>
 #include <mmc.h>
 #include <dm/root.h>
+#include <command.h>
 
 #define CTRLMMR_MCU_RST_CTRL			0x04518170
 
+#define CTRLMMR_MCU_RST_SRC                    (MCU_CTRL_MMR0_BASE + 0x18178)
+#define COLD_BOOT                              0
+#define SW_POR_MCU                             BIT(24)
+#define SW_POR_MAIN                            BIT(25)
+
 static void ctrl_mmr_unlock(void)
 {
 	/* Unlock all PADCFG_MMR1 module registers */
@@ -100,8 +104,8 @@
 {
 	int ret, rescan;
 
-	if (IS_ENABLED(CONFIG_K3_BOARD_DETECT))
-		do_board_detect();
+	/* Perform board detection */
+	do_board_detect();
 
 	/*
 	 * Board detection has been done.
@@ -166,6 +170,7 @@
 #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM64_DDRSS) || defined(CONFIG_ESM_K3)
 	struct udevice *dev;
 	int ret;
+	int rst_src;
 #endif
 
 #if defined(CONFIG_CPU_V7R)
@@ -185,8 +190,6 @@
 
 	preloader_console_init();
 
-	do_dt_magic();
-
 #if defined(CONFIG_K3_LOAD_SYSFW)
 	/*
 	 * Process pinctrl for serial3 a.k.a. MAIN UART1 module and continue
@@ -210,9 +213,37 @@
 			k3_mmc_restart_clock);
 #endif
 
+#if defined(CONFIG_CPU_V7R)
+	/*
+	 * Errata ID i2331 CPSW: A device lockup can occur during the second
+	 * read of any CPSW subsystem register after any MAIN domain power on
+	 * reset (POR). A MAIN domain POR occurs using the hardware MCU_PORz
+	 * signal, or via software using CTRLMMR_RST_CTRL.SW_MAIN_POR or
+	 * CTRLMMR_MCU_RST_CTRL.SW_MAIN_POR. After these resets, the processor
+	 * and internal bus structures may get into a state which is only
+	 * recoverable with full device reset using MCU_PORz.
+	 * Workaround(s): To avoid the lockup, a warm reset should be issued
+	 * after a MAIN domain POR and before any access to the CPSW registers.
+	 * The warm reset realigns internal clocks and prevents the lockup from
+	 * happening.
+	 */
+	ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
+	if (ret)
+		printf("\n%s:uclass device error [%d]\n",__func__,ret);
+
+	rst_src = readl(CTRLMMR_MCU_RST_SRC);
+	if (rst_src == COLD_BOOT || rst_src & (SW_POR_MCU | SW_POR_MAIN)) {
+		printf("Resetting on cold boot to workaround ErrataID:i2331\n");
+		printf("Please resend tiboot3.bin in case of UART/DFU boot\n");
+		do_reset(NULL, 0, 0, NULL);
+	}
+#endif
+
 	/* Output System Firmware version info */
 	k3_sysfw_print_ver();
 
+	do_dt_magic();
+
 #if defined(CONFIG_ESM_K3)
 	/* Probe/configure ESM0 */
 	ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev);
@@ -346,54 +377,3 @@
 	else
 		return __get_backup_bootmedia(devstat);
 }
-
-#if defined(CONFIG_SYS_K3_SPL_ATF)
-
-#define AM64X_DEV_RTI8			127
-#define AM64X_DEV_RTI9			128
-#define AM64X_DEV_R5FSS0_CORE0		121
-#define AM64X_DEV_R5FSS0_CORE1		122
-
-void release_resources_for_core_shutdown(void)
-{
-	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
-	struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
-	struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
-	int ret;
-	u32 i;
-
-	const u32 put_device_ids[] = {
-		AM64X_DEV_RTI9,
-		AM64X_DEV_RTI8,
-	};
-
-	/* Iterate through list of devices to put (shutdown) */
-	for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
-		u32 id = put_device_ids[i];
-
-		ret = dev_ops->put_device(ti_sci, id);
-		if (ret)
-			panic("Failed to put device %u (%d)\n", id, ret);
-	}
-
-	const u32 put_core_ids[] = {
-		AM64X_DEV_R5FSS0_CORE1,
-		AM64X_DEV_R5FSS0_CORE0, /* Handle CPU0 after CPU1 */
-	};
-
-	/* Iterate through list of cores to put (shutdown) */
-	for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
-		u32 id = put_core_ids[i];
-
-		/*
-		 * Queue up the core shutdown request. Note that this call
-		 * needs to be followed up by an actual invocation of an WFE
-		 * or WFI CPU instruction.
-		 */
-		ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
-		if (ret)
-			panic("Failed sending core %u shutdown message (%d)\n",
-			      id, ret);
-	}
-}
-#endif
diff --git a/arch/arm/mach-k3/am654_init.c b/arch/arm/mach-k3/am654_init.c
index 70059ed..0d3889c 100644
--- a/arch/arm/mach-k3/am654_init.c
+++ b/arch/arm/mach-k3/am654_init.c
@@ -13,8 +13,7 @@
 #include <asm/io.h>
 #include <spl.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/sysfw-loader.h>
-#include <asm/arch/sys_proto.h>
+#include "sysfw-loader.h"
 #include "common.h"
 #include <dm.h>
 #include <dm/uclass-internal.h>
@@ -245,8 +244,8 @@
 	/* Output System Firmware version info */
 	k3_sysfw_print_ver();
 
-	if (IS_ENABLED(CONFIG_K3_BOARD_DETECT))
-		do_board_detect();
+	/* Perform board detection */
+	do_board_detect();
 
 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
 	ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
@@ -353,54 +352,3 @@
 	else
 		return __get_backup_bootmedia(devstat);
 }
-
-#ifdef CONFIG_SYS_K3_SPL_ATF
-
-#define AM6_DEV_MCU_RTI0			134
-#define AM6_DEV_MCU_RTI1			135
-#define AM6_DEV_MCU_ARMSS0_CPU0			159
-#define AM6_DEV_MCU_ARMSS0_CPU1			245
-
-void release_resources_for_core_shutdown(void)
-{
-	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
-	struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
-	struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
-	int ret;
-	u32 i;
-
-	const u32 put_device_ids[] = {
-		AM6_DEV_MCU_RTI0,
-		AM6_DEV_MCU_RTI1,
-	};
-
-	/* Iterate through list of devices to put (shutdown) */
-	for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
-		u32 id = put_device_ids[i];
-
-		ret = dev_ops->put_device(ti_sci, id);
-		if (ret)
-			panic("Failed to put device %u (%d)\n", id, ret);
-	}
-
-	const u32 put_core_ids[] = {
-		AM6_DEV_MCU_ARMSS0_CPU1,
-		AM6_DEV_MCU_ARMSS0_CPU0,	/* Handle CPU0 after CPU1 */
-	};
-
-	/* Iterate through list of cores to put (shutdown) */
-	for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
-		u32 id = put_core_ids[i];
-
-		/*
-		 * Queue up the core shutdown request. Note that this call
-		 * needs to be followed up by an actual invocation of an WFE
-		 * or WFI CPU instruction.
-		 */
-		ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
-		if (ret)
-			panic("Failed sending core %u shutdown message (%d)\n",
-			      id, ret);
-	}
-}
-#endif
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index a2adb79..3c85cae 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -19,7 +19,6 @@
 #include <asm/cache.h>
 #include <linux/soc/ti/ti_sci_protocol.h>
 #include <fdt_support.h>
-#include <asm/arch/sys_proto.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
 #include <fs_loader.h>
@@ -189,9 +188,37 @@
 	return size;
 }
 
-__weak void release_resources_for_core_shutdown(void)
+void release_resources_for_core_shutdown(void)
 {
-	debug("%s not implemented...\n", __func__);
+	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
+	struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
+	struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
+	int ret;
+	u32 i;
+
+	/* Iterate through list of devices to put (shutdown) */
+	for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
+		u32 id = put_device_ids[i];
+
+		ret = dev_ops->put_device(ti_sci, id);
+		if (ret)
+			panic("Failed to put device %u (%d)\n", id, ret);
+	}
+
+	/* Iterate through list of cores to put (shutdown) */
+	for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
+		u32 id = put_core_ids[i];
+
+		/*
+		 * Queue up the core shutdown request. Note that this call
+		 * needs to be followed up by an actual invocation of an WFE
+		 * or WFI CPU instruction.
+		 */
+		ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
+		if (ret)
+			panic("Failed sending core %u shutdown message (%d)\n",
+			      id, ret);
+	}
 }
 
 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
@@ -227,6 +254,31 @@
 	if (ret)
 		panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
 
+#if (CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS) && IS_ENABLED(CONFIG_SYS_K3_SPL_ATF))
+	/* Authenticate ATF */
+	void *image_addr = (void *)fit_image_info[IMAGE_ID_ATF].image_start;
+
+	debug("%s: Authenticating image: addr=%lx, size=%ld, os=%s\n", __func__,
+	      fit_image_info[IMAGE_ID_ATF].image_start,
+	      fit_image_info[IMAGE_ID_ATF].image_len,
+	      image_os_match[IMAGE_ID_ATF]);
+
+	ti_secure_image_post_process(&image_addr,
+				     (size_t *)&fit_image_info[IMAGE_ID_ATF].image_len);
+
+	/* Authenticate OPTEE */
+	image_addr = (void *)fit_image_info[IMAGE_ID_OPTEE].image_start;
+
+	debug("%s: Authenticating image: addr=%lx, size=%ld, os=%s\n", __func__,
+	      fit_image_info[IMAGE_ID_OPTEE].image_start,
+	      fit_image_info[IMAGE_ID_OPTEE].image_len,
+	      image_os_match[IMAGE_ID_OPTEE]);
+
+	ti_secure_image_post_process(&image_addr,
+				     (size_t *)&fit_image_info[IMAGE_ID_OPTEE].image_len);
+
+#endif
+
 	if (!fit_image_info[IMAGE_ID_DM_FW].image_len &&
 	    !(size > 0 && valid_elf_image(loadaddr))) {
 		shut_cpu = 1;
@@ -288,9 +340,15 @@
 			break;
 		}
 	}
+	/*
+	 * Only DM and the DTBs are being authenticated here,
+	 * rest will be authenticated when A72 cluster is up
+	 */
+	if ((i != IMAGE_ID_ATF) && (i != IMAGE_ID_OPTEE))
 #endif
-
-	ti_secure_image_post_process(p_image, p_size);
+	{
+		ti_secure_image_post_process(p_image, p_size);
+	}
 }
 #endif
 
@@ -367,24 +425,21 @@
 	return 0;
 }
 
-int fdt_disable_node(void *blob, char *node_path)
+#if defined(CONFIG_OF_SYSTEM_SETUP)
+int ft_system_setup(void *blob, struct bd_info *bd)
 {
-	int offs;
 	int ret;
 
-	offs = fdt_path_offset(blob, node_path);
-	if (offs < 0) {
-		printf("Node %s not found.\n", node_path);
-		return offs;
-	}
-	ret = fdt_setprop_string(blob, offs, "status", "disabled");
-	if (ret < 0) {
-		printf("Could not add status property to node %s: %s\n",
-		       node_path, fdt_strerror(ret));
-		return ret;
-	}
-	return 0;
+	ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
+	if (ret < 0)
+		ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
+					 "sram@70000000");
+	if (ret)
+		printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
+
+	return ret;
 }
+#endif
 
 #endif
 
@@ -472,26 +527,6 @@
 }
 #endif
 
-bool soc_is_j721e(void)
-{
-	u32 soc;
-
-	soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
-		JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
-
-	return soc == J721E;
-}
-
-bool soc_is_j7200(void)
-{
-	u32 soc;
-
-	soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
-		JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
-
-	return soc == J7200;
-}
-
 #ifdef CONFIG_ARM64
 void board_prep_linux(struct bootm_headers *images)
 {
@@ -545,7 +580,10 @@
 
 			fwl_ops->get_fwl_region(ti_sci, &region);
 
-			if (region.control != 0) {
+			/* Don't disable the background regions */
+			if (region.control != 0 &&
+			    ((region.control & K3_BACKGROUND_FIREWALL_BIT) ==
+			     0)) {
 				pr_debug("Attempting to disable firewall %5d (%25s)\n",
 					 region.fwl_id, fwl_data[i].name);
 				region.control = 0;
@@ -606,9 +644,19 @@
 			printf("Failed to probe am65_cpsw_nuss driver\n");
 	}
 
-	/* Default FIT boot on non-GP devices */
-	if (get_device_type() != K3_DEVICE_TYPE_GP)
+	/* Default FIT boot on HS-SE devices */
+	if (get_device_type() == K3_DEVICE_TYPE_HS_SE)
 		env_set("boot_fit", "1");
 
 	return 0;
 }
+
+/**
+ * do_board_detect() - Detect board description
+ *
+ * Function to detect board description. This is expected to be
+ * overridden in the SoC family board file where desired.
+ */
+void __weak do_board_detect(void)
+{
+}
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index 8f38fce..e7e59f5 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -11,6 +11,7 @@
 
 #define J721E  0xbb64
 #define J7200  0xbb6d
+#define K3_BACKGROUND_FIREWALL_BIT BIT(8)
 
 struct fwl_data {
 	const char *name;
@@ -38,3 +39,5 @@
 bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
 enum k3_device_type get_device_type(void);
 void ti_secure_image_post_process(void **p_image, size_t *p_size);
+struct ti_sci_handle *get_ti_sci_handle(void);
+void do_board_detect(void);
diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h
index db4a32c..88d5894 100644
--- a/arch/arm/mach-k3/include/mach/am62_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am62_hardware.h
@@ -57,4 +57,12 @@
 
 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START	0x43c30000
 
+#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
+
+static const u32 put_device_ids[] = {};
+
+static const u32 put_core_ids[] = {};
+
+#endif
+
 #endif /* __ASM_ARCH_AM62_HARDWARE_H */
diff --git a/arch/arm/mach-k3/include/mach/am62a_hardware.h b/arch/arm/mach-k3/include/mach/am62a_hardware.h
index 13bf50f..1108080 100644
--- a/arch/arm/mach-k3/include/mach/am62a_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am62a_hardware.h
@@ -86,4 +86,12 @@
 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START	0x70000001
 #endif /* CONFIG_CPU_V7R */
 
+#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
+
+static const u32 put_device_ids[] = {};
+
+static const u32 put_core_ids[] = {};
+
+#endif
+
 #endif /* __ASM_ARCH_AM62A_HARDWARE_H */
diff --git a/arch/arm/mach-k3/include/mach/am62a_qos.h b/arch/arm/mach-k3/include/mach/am62a_qos.h
new file mode 100644
index 0000000..c74d69a
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/am62a_qos.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define QOS_0	(0 << 0)
+#define QOS_1	(1 << 0)
+#define QOS_2	(2 << 0)
+#define QOS_3	(3 << 0)
+#define QOS_4	(4 << 0)
+#define QOS_5	(5 << 0)
+#define QOS_6	(6 << 0)
+#define QOS_7	(7 << 0)
+
+#define ORDERID_0	(0 << 4)
+#define ORDERID_1	(1 << 4)
+#define ORDERID_2	(2 << 4)
+#define ORDERID_3	(3 << 4)
+#define ORDERID_4	(4 << 4)
+#define ORDERID_5	(5 << 4)
+#define ORDERID_6	(6 << 4)
+#define ORDERID_7	(7 << 4)
+#define ORDERID_8	(8 << 4)
+#define ORDERID_9	(9 << 4)
+#define ORDERID_10	(10 << 4)
+#define ORDERID_11	(11 << 4)
+#define ORDERID_12	(12 << 4)
+#define ORDERID_13	(13 << 4)
+#define ORDERID_14	(14 << 4)
+#define ORDERID_15	(15 << 4)
+
+#define ASEL_0	(0 << 8)
+#define ASEL_1	(1 << 8)
+#define ASEL_2	(2 << 8)
+#define ASEL_3	(3 << 8)
+#define ASEL_4	(4 << 8)
+#define ASEL_5	(5 << 8)
+#define ASEL_6	(6 << 8)
+#define ASEL_7	(7 << 8)
+#define ASEL_8	(8 << 8)
+#define ASEL_9	(9 << 8)
+#define ASEL_10	(10 << 8)
+#define ASEL_11	(11 << 8)
+#define ASEL_12	(12 << 8)
+#define ASEL_13	(13 << 8)
+#define ASEL_14	(14 << 8)
+#define ASEL_15	(15 << 8)
+
+#define EPRIORITY_0	(0 << 12)
+#define EPRIORITY_1	(1 << 12)
+#define EPRIORITY_2	(2 << 12)
+#define EPRIORITY_3	(3 << 12)
+#define EPRIORITY_4	(4 << 12)
+#define EPRIORITY_5	(5 << 12)
+#define EPRIORITY_6	(6 << 12)
+#define EPRIORITY_7	(7 << 12)
+
+#define VIRTID_0	(0 << 16)
+#define VIRTID_1	(1 << 16)
+#define VIRTID_2	(2 << 16)
+#define VIRTID_3	(3 << 16)
+#define VIRTID_4	(4 << 16)
+#define VIRTID_5	(5 << 16)
+#define VIRTID_6	(6 << 16)
+#define VIRTID_7	(7 << 16)
+#define VIRTID_8	(8 << 16)
+#define VIRTID_9	(9 << 16)
+#define VIRTID_10	(10 << 16)
+#define VIRTID_11	(11 << 16)
+#define VIRTID_12	(12 << 16)
+#define VIRTID_13	(13 << 16)
+#define VIRTID_14	(14 << 16)
+#define VIRTID_15	(15 << 16)
+
+#define ATYPE_0	(0 << 28)
+#define ATYPE_1	(1 << 28)
+#define ATYPE_2	(2 << 28)
+#define ATYPE_3	(3 << 28)
+
+#define PULSAR_UL_WKUP_0_CPU0_RMST	0x45D14000
+#define PULSAR_UL_WKUP_0_CPU0_WMST	0x45D14400
+#define PULSAR_UL_WKUP_0_CPU0_PMST	0x45D14800
+#define PULSAR_ULS_MCU_0_CPU0_RMST	0x45D18000
+#define PULSAR_ULS_MCU_0_CPU0_WMST	0x45D18400
+#define PULSAR_ULS_MCU_0_CPU0_PMST	0x45D18800
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R	0x45D20400
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W	0x45D20800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW	0x45D21800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR	0x45D21C00
+#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM	0x45D22000
+#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM	0x45D22400
+#define EMMCSD8SS_MAIN_0_EMMCSDSS_RD	0x45D22800
+#define EMMCSD8SS_MAIN_0_EMMCSDSS_WR	0x45D22C00
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD	0x45D23000
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR	0x45D23400
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR	0x45D23800
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD	0x45D23C00
+#define USB2SS_16FFC_MAIN_0_MSTW0	0x45D24000
+#define USB2SS_16FFC_MAIN_0_MSTR0	0x45D24400
+#define USB2SS_16FFC_MAIN_1_MSTR0	0x45D24800
+#define USB2SS_16FFC_MAIN_1_MSTW0	0x45D24C00
+#define K3_DSS_UL_MAIN_0_VBUSM_DMA	0x45D25000
+#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA	0x45D25400
+#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_W	0x45D25800
+#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_R	0x45D25C00
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC	0x45D26800
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC	0x45D26C00
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC	0x45D27000
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC	0x45D27400
+#define SAM62A_C7XV_WRAP_MAIN_0_C7XV_SOC	0x45D27800
+#define SAM62A_VPAC_WRAP_MAIN_0_LDC0_M_MST	0x45D28000
diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h
index 207ef95..44df887 100644
--- a/arch/arm/mach-k3/include/mach/am64_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am64_hardware.h
@@ -7,6 +7,11 @@
 #ifndef __ASM_ARCH_AM64_HARDWARE_H
 #define __ASM_ARCH_AM64_HARDWARE_H
 
+#include <config.h>
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
 #define PADCFG_MMR1_BASE				0x000f0000
 #define MCU_PADCFG_MMR1_BASE				0x04080000
 #define WKUP_CTRL_MMR0_BASE				0x43000000
@@ -41,4 +46,23 @@
 /* Use Last 2K as Scratch pad */
 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START		0x7019f800
 
+#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
+
+#define AM64X_DEV_RTI8			127
+#define AM64X_DEV_RTI9			128
+#define AM64X_DEV_R5FSS0_CORE0		121
+#define AM64X_DEV_R5FSS0_CORE1		122
+
+static const u32 put_device_ids[] = {
+	AM64X_DEV_RTI9,
+	AM64X_DEV_RTI8,
+};
+
+static const u32 put_core_ids[] = {
+	AM64X_DEV_R5FSS0_CORE1,
+	AM64X_DEV_R5FSS0_CORE0, /* Handle CPU0 after CPU1 */
+};
+
+#endif
+
 #endif /* __ASM_ARCH_DRA8_HARDWARE_H */
diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h
index f9f3291..029041f 100644
--- a/arch/arm/mach-k3/include/mach/am6_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am6_hardware.h
@@ -39,4 +39,23 @@
 
 #define	NAVSS_NBSS_THREADMAP				0x10
 
+#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
+
+#define AM6_DEV_MCU_RTI0			134
+#define AM6_DEV_MCU_RTI1			135
+#define AM6_DEV_MCU_ARMSS0_CPU0			159
+#define AM6_DEV_MCU_ARMSS0_CPU1			245
+
+static const u32 put_device_ids[] = {
+	AM6_DEV_MCU_RTI0,
+	AM6_DEV_MCU_RTI1,
+};
+
+static const u32 put_core_ids[] = {
+	AM6_DEV_MCU_ARMSS0_CPU1,
+	AM6_DEV_MCU_ARMSS0_CPU0,	/* Handle CPU0 after CPU1 */
+};
+
+#endif
+
 #endif /* __ASM_ARCH_AM6_HARDWARE_H */
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index 2c60ef8..65742c4 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -6,6 +6,8 @@
 #ifndef _ASM_ARCH_HARDWARE_H_
 #define _ASM_ARCH_HARDWARE_H_
 
+#include <asm/io.h>
+
 #ifdef CONFIG_SOC_K3_AM654
 #include "am6_hardware.h"
 #endif
@@ -28,6 +30,7 @@
 
 #ifdef CONFIG_SOC_K3_AM62A7
 #include "am62a_hardware.h"
+#include "am62a_qos.h"
 #endif
 
 /* Assuming these addresses and definitions stay common across K3 devices */
@@ -36,6 +39,29 @@
 #define JTAG_ID_VARIANT_MASK	(0xf << 28)
 #define JTAG_ID_PARTNO_SHIFT	12
 #define JTAG_ID_PARTNO_MASK	(0xffff << 12)
+#define JTAG_ID_PARTNO_AM65X	0xbb5a
+#define JTAG_ID_PARTNO_J721E	0xbb64
+#define JTAG_ID_PARTNO_J7200	0xbb6d
+#define JTAG_ID_PARTNO_AM64X	0xbb38
+#define JTAG_ID_PARTNO_J721S2	0xbb75
+#define JTAG_ID_PARTNO_AM62X	0xbb7e
+#define JTAG_ID_PARTNO_AM62AX   0xbb8d
+
+#define K3_SOC_ID(id, ID) \
+static inline bool soc_is_##id(void) \
+{ \
+	u32 soc = (readl(CTRLMMR_WKUP_JTAG_ID) & \
+		JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; \
+	return soc == JTAG_ID_PARTNO_##ID; \
+}
+K3_SOC_ID(am65x, AM65X)
+K3_SOC_ID(j721e, J721E)
+K3_SOC_ID(j7200, J7200)
+K3_SOC_ID(am64x, AM64X)
+K3_SOC_ID(j721s2, J721S2)
+K3_SOC_ID(am62x, AM62X)
+K3_SOC_ID(am62ax, AM62AX)
+
 #define K3_SEC_MGR_SYS_STATUS		0x44234100
 #define SYS_STATUS_DEV_TYPE_SHIFT	0
 #define SYS_STATUS_DEV_TYPE_MASK	(0xf)
@@ -71,4 +97,12 @@
 	u32 num_components;
 };
 
+struct k3_qos_data {
+	u32 reg;
+	u32 val;
+};
+
+extern struct k3_qos_data am62a_qos_data[];
+extern u32 am62a_qos_count;
+
 #endif /* _ASM_ARCH_HARDWARE_H_ */
diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h
index 247dee9..376db38 100644
--- a/arch/arm/mach-k3/include/mach/j721e_hardware.h
+++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h
@@ -38,4 +38,23 @@
 /* MCU SCRATCHPAD usage */
 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START	CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
 
+#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
+
+#define J721E_DEV_MCU_RTI0			262
+#define J721E_DEV_MCU_RTI1			263
+#define J721E_DEV_MCU_ARMSS0_CPU0		250
+#define J721E_DEV_MCU_ARMSS0_CPU1		251
+
+static const u32 put_device_ids[] = {
+	J721E_DEV_MCU_RTI0,
+	J721E_DEV_MCU_RTI1,
+};
+
+static const u32 put_core_ids[] = {
+	J721E_DEV_MCU_ARMSS0_CPU1,
+	J721E_DEV_MCU_ARMSS0_CPU0,	/* Handle CPU0 after CPU1 */
+};
+
+#endif
+
 #endif /* __ASM_ARCH_J721E_HARDWARE_H */
diff --git a/arch/arm/mach-k3/include/mach/j721s2_hardware.h b/arch/arm/mach-k3/include/mach/j721s2_hardware.h
index 2e155ed..7948bcf 100644
--- a/arch/arm/mach-k3/include/mach/j721s2_hardware.h
+++ b/arch/arm/mach-k3/include/mach/j721s2_hardware.h
@@ -38,4 +38,23 @@
 /* MCU SCRATCHPAD usage */
 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START	CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
 
+#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
+
+#define J721S2_DEV_MCU_RTI0			295
+#define J721S2_DEV_MCU_RTI1			296
+#define J721S2_DEV_MCU_ARMSS0_CPU0		284
+#define J721S2_DEV_MCU_ARMSS0_CPU1		285
+
+static const u32 put_device_ids[] = {
+	J721S2_DEV_MCU_RTI0,
+	J721S2_DEV_MCU_RTI1,
+};
+
+static const u32 put_core_ids[] = {
+	J721S2_DEV_MCU_ARMSS0_CPU1,
+	J721S2_DEV_MCU_ARMSS0_CPU0,	/* Handle CPU0 after CPU1 */
+};
+
+#endif
+
 #endif /* __ASM_ARCH_J721S2_HARDWARE_H */
diff --git a/arch/arm/mach-k3/include/mach/sys_proto.h b/arch/arm/mach-k3/include/mach/sys_proto.h
deleted file mode 100644
index 3d3d90d..0000000
--- a/arch/arm/mach-k3/include/mach/sys_proto.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
- *	Andreas Dannenberg <dannenberg@ti.com>
- */
-
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-void sdelay(unsigned long loops);
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
-		  u32 bound);
-struct ti_sci_handle *get_ti_sci_handle(void);
-int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name);
-int do_board_detect(void);
-void release_resources_for_core_shutdown(void);
-int fdt_disable_node(void *blob, char *node_path);
-
-bool soc_is_j721e(void);
-bool soc_is_j7200(void);
-
-void k3_spl_init(void);
-void k3_mem_init(void);
-bool check_rom_loaded_sysfw(void);
-#endif
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 9cae3ac..0c5d41a 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -12,9 +12,8 @@
 #include <asm/io.h>
 #include <asm/armv7_mpu.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/sysfw-loader.h>
+#include "sysfw-loader.h"
 #include "common.h"
-#include <asm/arch/sys_proto.h>
 #include <linux/soc/ti/ti_sci_protocol.h>
 #include <dm.h>
 #include <dm/uclass-internal.h>
@@ -26,6 +25,7 @@
 
 #ifdef CONFIG_K3_LOAD_SYSFW
 struct fwl_data cbass_hc_cfg0_fwls[] = {
+#if defined(CONFIG_TARGET_J721E_R5_EVM)
 	{ "PCIE0_CFG", 2560, 8 },
 	{ "PCIE1_CFG", 2561, 8 },
 	{ "USB3SS0_CORE", 2568, 4 },
@@ -34,11 +34,16 @@
 	{ "UFS_HCI0_CFG", 2580, 4 },
 	{ "SERDES0", 2584, 1 },
 	{ "SERDES1", 2585, 1 },
+#elif defined(CONFIG_TARGET_J7200_R5_EVM)
+	{ "PCIE1_CFG", 2561, 7 },
+#endif
 }, cbass_hc0_fwls[] = {
+#if defined(CONFIG_TARGET_J721E_R5_EVM)
 	{ "PCIE0_HP", 2528, 24 },
 	{ "PCIE0_LP", 2529, 24 },
 	{ "PCIE1_HP", 2530, 24 },
 	{ "PCIE1_LP", 2531, 24 },
+#endif
 }, cbass_rc_cfg0_fwls[] = {
 	{ "EMMCSD4SS0_CFG", 2380, 4 },
 }, cbass_rc0_fwls[] = {
@@ -140,8 +145,8 @@
 	int ret, rescan, mmc_dev = -1;
 	static struct mmc *mmc;
 
-	if (IS_ENABLED(CONFIG_K3_BOARD_DETECT))
-		do_board_detect();
+	/* Perform board detection */
+	do_board_detect();
 
 	/*
 	 * Board detection has been done.
@@ -267,8 +272,8 @@
 	/* Output System Firmware version info */
 	k3_sysfw_print_ver();
 
-	if (IS_ENABLED(CONFIG_K3_BOARD_DETECT))
-		do_board_detect();
+	/* Perform board detection */
+	do_board_detect();
 
 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
 	ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
@@ -378,58 +383,3 @@
 	else
 		return __get_backup_bootmedia(main_devstat);
 }
-
-#ifdef CONFIG_SYS_K3_SPL_ATF
-
-#define J721E_DEV_MCU_RTI0			262
-#define J721E_DEV_MCU_RTI1			263
-#define J721E_DEV_MCU_ARMSS0_CPU0		250
-#define J721E_DEV_MCU_ARMSS0_CPU1		251
-
-void release_resources_for_core_shutdown(void)
-{
-	struct ti_sci_handle *ti_sci;
-	struct ti_sci_dev_ops *dev_ops;
-	struct ti_sci_proc_ops *proc_ops;
-	int ret;
-	u32 i;
-
-	const u32 put_device_ids[] = {
-		J721E_DEV_MCU_RTI0,
-		J721E_DEV_MCU_RTI1,
-	};
-
-	ti_sci = get_ti_sci_handle();
-	dev_ops = &ti_sci->ops.dev_ops;
-	proc_ops = &ti_sci->ops.proc_ops;
-
-	/* Iterate through list of devices to put (shutdown) */
-	for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
-		u32 id = put_device_ids[i];
-
-		ret = dev_ops->put_device(ti_sci, id);
-		if (ret)
-			panic("Failed to put device %u (%d)\n", id, ret);
-	}
-
-	const u32 put_core_ids[] = {
-		J721E_DEV_MCU_ARMSS0_CPU1,
-		J721E_DEV_MCU_ARMSS0_CPU0,	/* Handle CPU0 after CPU1 */
-	};
-
-	/* Iterate through list of cores to put (shutdown) */
-	for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
-		u32 id = put_core_ids[i];
-
-		/*
-		 * Queue up the core shutdown request. Note that this call
-		 * needs to be followed up by an actual invocation of an WFE
-		 * or WFI CPU instruction.
-		 */
-		ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
-		if (ret)
-			panic("Failed sending core %u shutdown message (%d)\n",
-			      id, ret);
-	}
-}
-#endif
diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c
index 09e55ed..712a7e2 100644
--- a/arch/arm/mach-k3/j721s2_init.c
+++ b/arch/arm/mach-k3/j721s2_init.c
@@ -12,16 +12,61 @@
 #include <asm/io.h>
 #include <asm/armv7_mpu.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/sysfw-loader.h>
+#include "sysfw-loader.h"
 #include "common.h"
-#include <asm/arch/sys_proto.h>
 #include <linux/soc/ti/ti_sci_protocol.h>
 #include <dm.h>
 #include <dm/uclass-internal.h>
 #include <dm/pinctrl.h>
+#include <dm/root.h>
 #include <mmc.h>
 #include <remoteproc.h>
 
+struct fwl_data cbass_hc_cfg0_fwls[] = {
+	{ "PCIE0_CFG", 2577, 7 },
+	{ "EMMC8SS0_CFG", 2579, 4 },
+	{ "USB3SS0_CORE", 2580, 4 },
+	{ "USB3SS1_CORE", 2581, 1 },
+}, cbass_hc2_fwls[] = {
+	{ "PCIE0", 2547, 24 },
+	{ "HC2_WIZ16B8M4CT2", 2552, 1 },
+}, cbass_rc_cfg0_fwls[] = {
+	{ "EMMCSD4SS0_CFG", 2400, 4 },
+}, infra_cbass0_fwls[] = {
+	{ "PSC0", 5, 1 },
+	{ "PLL_CTRL0", 6, 1 },
+	{ "PLL_MMR0", 8, 26 },
+	{ "CTRL_MMR0", 9, 16 },
+	{ "GPIO0", 16, 1 },
+}, mcu_cbass0_fwls[] = {
+	{ "MCU_R5FSS0_CORE0", 1024, 4 },
+	{ "MCU_R5FSS0_CORE0_CFG", 1025, 3 },
+	{ "MCU_R5FSS0_CORE1", 1028, 4 },
+	{ "MCU_R5FSS0_CORE1_CFG", 1029, 1 },
+	{ "MCU_FSS0_CFG", 1032, 12 },
+	{ "MCU_FSS0_S1", 1033, 8 },
+	{ "MCU_FSS0_S0", 1036, 8 },
+	{ "MCU_PSROM49152X32", 1048, 1 },
+	{ "MCU_MSRAM128KX64", 1050, 8 },
+	{ "MCU_MSRAM128KX64_CFG", 1051, 1 },
+	{ "MCU_TIMER0", 1056, 1 },
+	{ "MCU_TIMER9", 1065, 1 },
+	{ "MCU_USART0", 1120, 1 },
+	{ "MCU_I2C0", 1152, 1 },
+	{ "MCU_CTRL_MMR0", 1200, 8 },
+	{ "MCU_PLL_MMR0", 1201, 3 },
+	{ "MCU_CPSW0", 1220, 2 },
+}, wkup_cbass0_fwls[] = {
+	{ "WKUP_PSC0", 129, 1 },
+	{ "WKUP_PLL_CTRL0", 130, 1 },
+	{ "WKUP_CTRL_MMR0", 131, 16 },
+	{ "WKUP_GPIO0", 132, 1 },
+	{ "WKUP_I2C0", 144, 1 },
+	{ "WKUP_USART0", 160, 1 },
+}, navss_cbass0_fwls[] = {
+	{ "NACSS_VIRT0", 6253, 1 },
+};
+
 static void ctrl_mmr_unlock(void)
 {
 	/* Unlock all WKUP_CTRL_MMR0 module registers */
@@ -150,6 +195,14 @@
 			if (ret)
 				panic("Failed to initialize clk-k3!\n");
 		}
+
+		remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
+		remove_fwl_configs(cbass_hc2_fwls, ARRAY_SIZE(cbass_hc2_fwls));
+		remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
+		remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
+		remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
+		remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
+		remove_fwl_configs(navss_cbass0_fwls, ARRAY_SIZE(navss_cbass0_fwls));
 	}
 
 	/* Output System Firmware version info */
@@ -181,6 +234,69 @@
 	}
 	spl_enable_dcache();
 }
+
+/* Support for the various EVM / SK families */
+#if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT)
+void do_dt_magic(void)
+{
+	int ret, rescan, mmc_dev = -1;
+	static struct mmc *mmc;
+
+	do_board_detect();
+
+	/*
+	 * Board detection has been done.
+	 * Let us see if another dtb wouldn't be a better match
+	 * for our board
+	 */
+	if (IS_ENABLED(CONFIG_CPU_V7R)) {
+		ret = fdtdec_resetup(&rescan);
+		if (!ret && rescan) {
+			dm_uninit();
+			dm_init_and_scan(true);
+		}
+	}
+
+	/*
+	 * Because of multi DTB configuration, the MMC device has
+	 * to be re-initialized after reconfiguring FDT inorder to
+	 * boot from MMC. Do this when boot mode is MMC and ROM has
+	 * not loaded SYSFW.
+	 */
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+		mmc_dev = 0;
+		break;
+	case BOOT_DEVICE_MMC2:
+	case BOOT_DEVICE_MMC2_2:
+		mmc_dev = 1;
+		break;
+	}
+
+	if (mmc_dev > 0 && !check_rom_loaded_sysfw()) {
+		ret = mmc_init_device(mmc_dev);
+		if (!ret) {
+			mmc = find_mmc_device(mmc_dev);
+			if (mmc) {
+				ret = mmc_init(mmc);
+				if (ret)
+					printf("mmc init failed with error: %d\n", ret);
+			}
+		}
+	}
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+	k3_spl_init();
+#if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT)
+	do_dt_magic();
+#endif
+	k3_mem_init();
+}
+#endif
 
 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
 {
@@ -264,57 +380,3 @@
 	else
 		return __get_backup_bootmedia(main_devstat);
 }
-
-#define J721S2_DEV_MCU_RTI0			295
-#define J721S2_DEV_MCU_RTI1			296
-#define J721S2_DEV_MCU_ARMSS0_CPU0		284
-#define J721S2_DEV_MCU_ARMSS0_CPU1		285
-
-void release_resources_for_core_shutdown(void)
-{
-	if (IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)) {
-		struct ti_sci_handle *ti_sci;
-		struct ti_sci_dev_ops *dev_ops;
-		struct ti_sci_proc_ops *proc_ops;
-		int ret;
-		u32 i;
-
-		const u32 put_device_ids[] = {
-			J721S2_DEV_MCU_RTI0,
-			J721S2_DEV_MCU_RTI1,
-		};
-
-		ti_sci = get_ti_sci_handle();
-		dev_ops = &ti_sci->ops.dev_ops;
-		proc_ops = &ti_sci->ops.proc_ops;
-
-		/* Iterate through list of devices to put (shutdown) */
-		for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
-			u32 id = put_device_ids[i];
-
-			ret = dev_ops->put_device(ti_sci, id);
-			if (ret)
-				panic("Failed to put device %u (%d)\n", id, ret);
-		}
-
-		const u32 put_core_ids[] = {
-			J721S2_DEV_MCU_ARMSS0_CPU1,
-			J721S2_DEV_MCU_ARMSS0_CPU0,	/* Handle CPU0 after CPU1 */
-		};
-
-		/* Iterate through list of cores to put (shutdown) */
-		for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
-			u32 id = put_core_ids[i];
-
-			/*
-			 * Queue up the core shutdown request. Note that this call
-			 * needs to be followed up by an actual invocation of an WFE
-			 * or WFI CPU instruction.
-			 */
-			ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
-			if (ret)
-				panic("Failed sending core %u shutdown message (%d)\n",
-				      id, ret);
-		}
-	}
-}
diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c
index 092588f..6179f73 100644
--- a/arch/arm/mach-k3/security.c
+++ b/arch/arm/mach-k3/security.c
@@ -17,7 +17,6 @@
 #include <linux/soc/ti/ti_sci_protocol.h>
 #include <mach/spl.h>
 #include <spl.h>
-#include <asm/arch/sys_proto.h>
 #include <linux/dma-mapping.h>
 
 #include "common.h"
diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index c4c5c37..9be2d9e 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -23,7 +23,6 @@
 #include <spi_flash.h>
 
 #include <asm/io.h>
-#include <asm/arch/sys_proto.h>
 #include "common.h"
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-k3/include/mach/sysfw-loader.h b/arch/arm/mach-k3/sysfw-loader.h
similarity index 100%
rename from arch/arm/mach-k3/include/mach/sysfw-loader.h
rename to arch/arm/mach-k3/sysfw-loader.h
diff --git a/arch/arm/mach-omap2/omap3/lowlevel_init.S b/arch/arm/mach-omap2/omap3/lowlevel_init.S
index ab7cdcf..1ab9472 100644
--- a/arch/arm/mach-omap2/omap3/lowlevel_init.S
+++ b/arch/arm/mach-omap2/omap3/lowlevel_init.S
@@ -15,13 +15,14 @@
 #include <asm/arch/clocks_omap3.h>
 #include <linux/linkage.h>
 
+.arch_extension sec
+
 /*
  * Funtion for making PPA HAL API calls in secure devices
  * Input:
  *	R0 - Service ID
  *	R1 - paramer list
  */
-/* TODO: Re-evaluate the comment at the end regarding armv5 vs armv7 */
 ENTRY(do_omap3_emu_romcode_call)
 	PUSH {r4-r12, lr} @ Save all registers from ROM code!
 	MOV r12, r0	@ Copy the Secure Service ID in R12
@@ -32,8 +33,7 @@
 	MOV r6, #0xFF	@ Indicate new Task call
 	mcr     p15, 0, r0, c7, c10, 4	@ DSB
 	mcr     p15, 0, r0, c7, c10, 5	@ DMB
-	.word	0xe1600071	@ SMC #1 to call PPA service - hand assembled
-				@ because we use -march=armv5
+	SMC     #1	@ Call PPA service
 	POP {r4-r12, pc}
 ENDPROC(do_omap3_emu_romcode_call)
 
diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig
index 0787d19..5394529 100644
--- a/arch/arm/mach-omap2/omap5/Kconfig
+++ b/arch/arm/mach-omap2/omap5/Kconfig
@@ -17,9 +17,6 @@
 config TARGET_CM_T54
 	bool "CompuLab CM-T54"
 
-config TARGET_OMAP5_UEVM
-	bool "TI OMAP5 uEVM board"
-
 config TARGET_DRA7XX_EVM
 	bool "TI DRA7XX"
 	select BOARD_LATE_INIT
@@ -162,7 +159,6 @@
 endmenu
 endif
 
-source "board/ti/omap5_uevm/Kconfig"
 source "board/ti/dra7xx/Kconfig"
 source "board/ti/am57xx/Kconfig"
 
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index bee59c3..f20d58b 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -31,7 +31,7 @@
 	select CREATE_ARCH_SYMLINK
 	select BOARD_EARLY_INIT_F
 	imply CMD_REGINFO
-	imply WDT_MPC8xx
+	imply WDT_MPC8xxx
 
 endchoice
 
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index b695c7e..582e141 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -20,6 +20,10 @@
 	prompt "Target select"
 	optional
 
+config TARGET_CMPCPRO
+	bool "Support CMPCPRO board from CSSI"
+	select ARCH_MPC832X
+
 config TARGET_MPC837XERDB
 	bool "Support MPC837XERDB"
 	select ARCH_MPC837X
@@ -205,5 +209,6 @@
 
 source "board/freescale/mpc837xerdb/Kconfig"
 source "board/gdsys/mpc8308/Kconfig"
+source "board/cssi/cmpcpro/Kconfig"
 
 endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/bats/Kconfig b/arch/powerpc/cpu/mpc83xx/bats/Kconfig
index 218920c..1cdb390 100644
--- a/arch/powerpc/cpu/mpc83xx/bats/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/bats/Kconfig
@@ -65,18 +65,12 @@
 
 endchoice
 
-config BAT0_ICACHE_WRITETHROUGH
-	bool "I-cache Write-through"
-
 config BAT0_ICACHE_INHIBITED
 	bool "I-cache Inhibited"
 
 config BAT0_ICACHE_MEMORYCOHERENCE
 	bool "I-cache Memory coherence"
 
-config BAT0_ICACHE_GUARDED
-	bool "I-cache Guarded"
-
 config BAT0_DCACHE_WRITETHROUGH
 	bool "D-cache Write-through"
 
@@ -120,22 +114,10 @@
 
 config BAT0_WIMG_ICACHE
 	hex
-	default 0x0 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
-	default 0x8 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
-	default 0x10 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
-	default 0x18 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
-	default 0x20 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
-	default 0x28 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
-	default 0x30 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
-	default 0x38 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
-	default 0x40 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
-	default 0x48 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
-	default 0x50 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
-	default 0x58 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
-	default 0x60 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
-	default 0x68 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
-	default 0x70 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
-	default 0x78 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+	default 0x0 if !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE
+	default 0x10 if !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE
+	default 0x20 if BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE
+	default 0x30 if BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE
 
 config BAT0_WIMG_DCACHE
 	hex
@@ -228,18 +210,12 @@
 
 endchoice
 
-config BAT1_ICACHE_WRITETHROUGH
-	bool "I-cache Write-through"
-
 config BAT1_ICACHE_INHIBITED
 	bool "I-cache Inhibited"
 
 config BAT1_ICACHE_MEMORYCOHERENCE
 	bool "I-cache Memory coherence"
 
-config BAT1_ICACHE_GUARDED
-	bool "I-cache Guarded"
-
 config BAT1_DCACHE_WRITETHROUGH
 	bool "D-cache Write-through"
 
@@ -283,22 +259,10 @@
 
 config BAT1_WIMG_ICACHE
 	hex
-	default 0x0 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
-	default 0x8 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
-	default 0x10 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
-	default 0x18 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
-	default 0x20 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
-	default 0x28 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
-	default 0x30 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
-	default 0x38 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
-	default 0x40 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
-	default 0x48 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
-	default 0x50 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
-	default 0x58 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
-	default 0x60 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
-	default 0x68 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
-	default 0x70 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
-	default 0x78 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+	default 0x0 if !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE
+	default 0x10 if !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE
+	default 0x20 if BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE
+	default 0x30 if BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE
 
 config BAT1_WIMG_DCACHE
 	hex
@@ -391,18 +355,12 @@
 
 endchoice
 
-config BAT2_ICACHE_WRITETHROUGH
-	bool "I-cache Write-through"
-
 config BAT2_ICACHE_INHIBITED
 	bool "I-cache Inhibited"
 
 config BAT2_ICACHE_MEMORYCOHERENCE
 	bool "I-cache Memory coherence"
 
-config BAT2_ICACHE_GUARDED
-	bool "I-cache Guarded"
-
 config BAT2_DCACHE_WRITETHROUGH
 	bool "D-cache Write-through"
 
@@ -446,22 +404,10 @@
 
 config BAT2_WIMG_ICACHE
 	hex
-	default 0x0 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
-	default 0x8 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
-	default 0x10 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
-	default 0x18 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
-	default 0x20 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
-	default 0x28 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
-	default 0x30 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
-	default 0x38 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
-	default 0x40 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
-	default 0x48 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
-	default 0x50 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
-	default 0x58 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
-	default 0x60 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
-	default 0x68 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
-	default 0x70 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
-	default 0x78 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+	default 0x0 if !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE
+	default 0x10 if !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE
+	default 0x20 if BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE
+	default 0x30 if BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE
 
 config BAT2_WIMG_DCACHE
 	hex
@@ -554,18 +500,12 @@
 
 endchoice
 
-config BAT3_ICACHE_WRITETHROUGH
-	bool "I-cache Write-through"
-
 config BAT3_ICACHE_INHIBITED
 	bool "I-cache Inhibited"
 
 config BAT3_ICACHE_MEMORYCOHERENCE
 	bool "I-cache Memory coherence"
 
-config BAT3_ICACHE_GUARDED
-	bool "I-cache Guarded"
-
 config BAT3_DCACHE_WRITETHROUGH
 	bool "D-cache Write-through"
 
@@ -609,22 +549,10 @@
 
 config BAT3_WIMG_ICACHE
 	hex
-	default 0x0 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
-	default 0x8 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
-	default 0x10 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
-	default 0x18 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
-	default 0x20 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
-	default 0x28 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
-	default 0x30 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
-	default 0x38 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
-	default 0x40 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
-	default 0x48 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
-	default 0x50 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
-	default 0x58 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
-	default 0x60 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
-	default 0x68 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
-	default 0x70 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
-	default 0x78 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+	default 0x0 if !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE
+	default 0x10 if !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE
+	default 0x20 if BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE
+	default 0x30 if BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE
 
 config BAT3_WIMG_DCACHE
 	hex
@@ -719,18 +647,12 @@
 
 endchoice
 
-config BAT4_ICACHE_WRITETHROUGH
-	bool "I-cache Write-through"
-
 config BAT4_ICACHE_INHIBITED
 	bool "I-cache Inhibited"
 
 config BAT4_ICACHE_MEMORYCOHERENCE
 	bool "I-cache Memory coherence"
 
-config BAT4_ICACHE_GUARDED
-	bool "I-cache Guarded"
-
 config BAT4_DCACHE_WRITETHROUGH
 	bool "D-cache Write-through"
 
@@ -774,22 +696,10 @@
 
 config BAT4_WIMG_ICACHE
 	hex
-	default 0x0 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
-	default 0x8 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
-	default 0x10 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
-	default 0x18 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
-	default 0x20 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
-	default 0x28 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
-	default 0x30 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
-	default 0x38 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
-	default 0x40 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
-	default 0x48 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
-	default 0x50 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
-	default 0x58 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
-	default 0x60 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
-	default 0x68 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
-	default 0x70 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
-	default 0x78 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+	default 0x0 if !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE
+	default 0x10 if !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE
+	default 0x20 if BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE
+	default 0x30 if BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE
 
 config BAT4_WIMG_DCACHE
 	hex
@@ -882,18 +792,12 @@
 
 endchoice
 
-config BAT5_ICACHE_WRITETHROUGH
-	bool "I-cache Write-through"
-
 config BAT5_ICACHE_INHIBITED
 	bool "I-cache Inhibited"
 
 config BAT5_ICACHE_MEMORYCOHERENCE
 	bool "I-cache Memory coherence"
 
-config BAT5_ICACHE_GUARDED
-	bool "I-cache Guarded"
-
 config BAT5_DCACHE_WRITETHROUGH
 	bool "D-cache Write-through"
 
@@ -937,22 +841,10 @@
 
 config BAT5_WIMG_ICACHE
 	hex
-	default 0x0 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
-	default 0x8 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
-	default 0x10 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
-	default 0x18 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
-	default 0x20 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
-	default 0x28 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
-	default 0x30 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
-	default 0x38 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
-	default 0x40 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
-	default 0x48 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
-	default 0x50 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
-	default 0x58 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
-	default 0x60 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
-	default 0x68 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
-	default 0x70 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
-	default 0x78 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+	default 0x0 if !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE
+	default 0x10 if !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE
+	default 0x20 if BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE
+	default 0x30 if BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE
 
 config BAT5_WIMG_DCACHE
 	hex
@@ -1045,18 +937,12 @@
 
 endchoice
 
-config BAT6_ICACHE_WRITETHROUGH
-	bool "I-cache Write-through"
-
 config BAT6_ICACHE_INHIBITED
 	bool "I-cache Inhibited"
 
 config BAT6_ICACHE_MEMORYCOHERENCE
 	bool "I-cache Memory coherence"
 
-config BAT6_ICACHE_GUARDED
-	bool "I-cache Guarded"
-
 config BAT6_DCACHE_WRITETHROUGH
 	bool "D-cache Write-through"
 
@@ -1100,22 +986,10 @@
 
 config BAT6_WIMG_ICACHE
 	hex
-	default 0x0 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
-	default 0x8 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
-	default 0x10 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
-	default 0x18 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
-	default 0x20 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
-	default 0x28 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
-	default 0x30 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
-	default 0x38 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
-	default 0x40 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
-	default 0x48 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
-	default 0x50 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
-	default 0x58 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
-	default 0x60 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
-	default 0x68 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
-	default 0x70 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
-	default 0x78 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+	default 0x0 if !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE
+	default 0x10 if !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE
+	default 0x20 if BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE
+	default 0x30 if BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE
 
 config BAT6_WIMG_DCACHE
 	hex
@@ -1208,18 +1082,12 @@
 
 endchoice
 
-config BAT7_ICACHE_WRITETHROUGH
-	bool "I-cache Write-through"
-
 config BAT7_ICACHE_INHIBITED
 	bool "I-cache Inhibited"
 
 config BAT7_ICACHE_MEMORYCOHERENCE
 	bool "I-cache Memory coherence"
 
-config BAT7_ICACHE_GUARDED
-	bool "I-cache Guarded"
-
 config BAT7_DCACHE_WRITETHROUGH
 	bool "D-cache Write-through"
 
@@ -1263,22 +1131,10 @@
 
 config BAT7_WIMG_ICACHE
 	hex
-	default 0x0 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
-	default 0x8 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
-	default 0x10 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
-	default 0x18 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
-	default 0x20 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
-	default 0x28 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
-	default 0x30 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
-	default 0x38 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
-	default 0x40 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
-	default 0x48 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
-	default 0x50 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
-	default 0x58 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
-	default 0x60 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
-	default 0x68 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
-	default 0x70 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
-	default 0x78 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+	default 0x0 if !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE
+	default 0x10 if !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE
+	default 0x20 if BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE
+	default 0x30 if BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE
 
 config BAT7_WIMG_DCACHE
 	hex
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index a6c0635..f6ffe29 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -165,7 +165,7 @@
 }
 #endif
 
-#if defined(CONFIG_WATCHDOG)
+#if defined(CONFIG_WATCHDOG) && !defined(CONFIG_WDT)
 void watchdog_reset (void)
 {
 	int re_enable = disable_interrupts();
diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
index b67ccd6..44f66cd 100644
--- a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
@@ -539,8 +539,7 @@
 
 config SYSTEM_PLL_VCO_DIV
 	int
-	default 0 if ARCH_MPC832X
-	default 2 if ARCH_MPC8313
+	default 2 if ARCH_MPC8313 || ARCH_MPC832X
 	default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X
 	default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X
 	default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 && !ARCH_MPC837X
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index e3878e4..6749263 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -215,6 +215,7 @@
 	 * gt-regs BAT can be reused after board_init_f calls
 	 * board_early_init_f (EVB only).
 	 */
+#ifdef CONFIG_SYS_INIT_RAM_LOCK
 	/* enable address translation */
 	bl	enable_addr_trans
 	sync
@@ -222,7 +223,6 @@
 	/* enable the data cache */
 	bl	dcache_enable
 	sync
-#ifdef CONFIG_SYS_INIT_RAM_LOCK
 	bl	lock_ram_in_cache
 	sync
 #endif
@@ -483,6 +483,7 @@
 
 
 	lis	r3, CONFIG_SYS_IMMR@h
+#ifndef CONFIG_WDT_MPC8xxx
 #if defined(CONFIG_WATCHDOG)
 	/* Initialise the Watchdog values and reset it (if req) */
 	/*------------------------------------------------------*/
@@ -508,6 +509,7 @@
 	stw r4, SWCRR(r3)
 1:
 #endif /* CONFIG_WATCHDOG */
+#endif
 
 #if defined(CONFIG_MASK_AER_AO)
 	/* Write the Arbiter Event Enable to mask Address Only traps. */
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index 628d361..bfd903b 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -30,9 +30,6 @@
 
 endchoice
 
-config 8xx_GCLK_FREQ
-	int "CPU GCLK Frequency"
-
 comment "Specific commands"
 
 config CMD_IMMAP
@@ -51,7 +48,8 @@
 	  SIU Module Configuration (11-6)
 
 config SYS_SYPCR
-	hex "SYPCR register"
+	hex "SYPCR register" if !WDT_MPC8xxx
+	default 0
 	help
 	  System Protection Control (11-9)
 
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index 86b08a6..feef792 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -26,10 +26,9 @@
 
 	/* SYPCR - contains watchdog control (11-9) */
 
-#ifndef CONFIG_HW_WATCHDOG
 	/* deactivate watchdog if not enabled in config */
-	out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE);
-#endif
+	if (!IS_ENABLED(CONFIG_WDT_MPC8xxx))
+		out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE);
 
 	schedule();
 
diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c
index ad3d3f9..1a882a3 100644
--- a/arch/powerpc/cpu/mpc8xx/speed.c
+++ b/arch/powerpc/cpu/mpc8xx/speed.c
@@ -14,7 +14,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
- * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
+ * get_clocks() fills in gd->cpu_clk depending on CONFIG_SYS_CLK_FREQ
  */
 int get_clocks(void)
 {
@@ -28,7 +28,7 @@
 	 * (For example, the cogent CMA286-60 CPU module has no
 	 * separate oscillator for PITRTCLK)
 	 */
-	gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
+	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
 
 	if ((sccr & SCCR_EBDF11) == 0) {
 		/* No Bus Divider active */
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 26b592b..bb436f0 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -30,6 +30,7 @@
 dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
 dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
 dtb-$(CONFIG_TARGET_CMPC885) += cmpc885.dtb
+dtb-$(CONFIG_TARGET_CMPCPRO) += cmpcpro.dtb
 
 include $(srctree)/scripts/Makefile.dts
 
diff --git a/arch/powerpc/dts/cmpc885.dts b/arch/powerpc/dts/cmpc885.dts
index adda0f3..7b9566a 100644
--- a/arch/powerpc/dts/cmpc885.dts
+++ b/arch/powerpc/dts/cmpc885.dts
@@ -18,11 +18,6 @@
 		stdout-path = &SERIAL;
 	};
 
-	WDT: watchdog@0 {
-		device_type = "watchdog";
-		compatible = "fsl,pq1-wdt";
-	};
-
 	SERIAL: serial {
 		compatible = "fsl,pq1-smc";
 	};
@@ -43,6 +38,13 @@
 		ranges = <0 0xff000000 0x4000>;
 		reg = <0xff000000 0x00000200>;
 
+		WDT: watchdog@0 {
+			compatible = "fsl,pq1-wdt";
+			reg = <0x0 0x10>;
+			timeout-sec = <2>;
+			hw_margin_ms = <1000>;
+		};
+
 		CPM1_PIO_B: gpio-controller@ab8 {
 			#gpio-cells = <2>;
 			compatible = "fsl,cpm1-pario-bank-b";
diff --git a/arch/powerpc/dts/cmpcpro.dts b/arch/powerpc/dts/cmpcpro.dts
new file mode 100644
index 0000000..c27d9db
--- /dev/null
+++ b/arch/powerpc/dts/cmpcpro.dts
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * CMPC885 Device Tree Source
+ *
+ * Copyright 2020 CS GROUP France
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/clk/mpc83xx-clk.h>
+
+/ {
+	model = "CMPCPRO";
+	compatible = "fsl, cmpc85xx", "fsl,mod85xx", "CMPCPRO", "MPC8321E", "fsl,cmpcpro";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		stdout-path = &serial0;
+	};
+	WDT: watchdog@0 {
+		device_type = "watchdog";
+		compatible = "fsl,pq1-wdt";
+	};
+
+	aliases {
+		ethernet0 = &eth0;
+		etehrnet1 = &eth1;
+		serial0 = &serial0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		PowerPC,8321@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+			d-cache-line-size = <0x20>;	// 32 bytes
+			i-cache-line-size = <0x20>;	// 32 bytes
+			d-cache-size = <16384>;	// L1, 16K
+			i-cache-size = <16384>;	// L1, 16K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>;
+	};
+
+	soc8321@b0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+		ranges = <0x0 0xb0000000 0x00100000>;
+		reg = <0xb0000000 0x00000200>;
+		bus-frequency = <0>;
+		pmc: power@b00 {
+			compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
+			reg = <0xb00 0x100 0xa00 0x100>;
+			interrupts = <80 0x8>;
+			interrupt-parent = <&ipic>;
+		};
+		serial0: serial@4500 {
+			clocks = <&socclocks MPC83XX_CLK_CSB>;
+			cell-index = <0>;
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x4500 0x100>;
+			clock-frequency = <0>;
+			interrupts = <9 0x8>;
+			interrupt-parent = <&ipic>;
+		};
+		ipic:pic@700 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			reg = <0x700 0x100>;
+			device_type = "ipic";
+		};
+		par_io@1400 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x1400 0x100>;
+			ranges;
+			compatible = "fsl,mpc8323-qe-pario","simple-bus";
+			device_type = "par_io";
+			num-ports = <7>;
+			qe_pio_a: gpio-controller@1400 {
+				#gpio-cells = <2>;
+				compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio";
+				reg = <0x1400 0x18>;
+				gpio-controller;
+			};
+			qe_pio_b: gpio-controller@1418 {
+				#gpio-cells = <2>;
+				compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio";
+				reg = <0x1418 0x18>;
+				gpio-controller;
+			};
+			qe_pio_c: gpio-controller@1430 {
+				#gpio-cells = <2>;
+				compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio";
+				reg = <0x1430 0x18>;
+				gpio-controller;
+			};
+			qe_pio_d: gpio-controller@1448 {
+				#gpio-cells = <2>;
+				compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio";
+				reg = <0x1448 0x18>;
+				gpio-controller;
+			};
+		};
+	};
+	socclocks: clocks {
+		bootph-all;
+		compatible = "fsl,mpc832x-clk";
+		#clock-cells = <1>;
+	};
+	qe@b0100000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "qe";
+		compatible = "fsl,qe","simple-bus";
+		ranges = <0x0 0xb0100000 0x00100000>;
+		reg = <0xb0100000 0x480>;
+		brg-frequency = <0>;
+		bus-frequency = <198000000>;
+		fsl,qe-num-riscs = <1>;
+		fsl,qe-num-snums = <28>;
+		spi@4c0 {
+			clocks = <&socclocks MPC83XX_CLK_CSB>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			compatible = "fsl,mpc832x-spi";
+			reg = <0x4c0 0x40>;
+			mode = "cpu";
+			gpios = <&qe_pio_d 3 1>;
+			clock-frequency = <0>;
+			eeprom@3 {
+				compatible = "atmel,at25", "cs,eeprom";
+				cell-index = <1>;
+			};
+		};
+		eth0: ucc@3000 {
+			device_type = "network";
+			compatible = "ucc_geth";
+			cell-index = <2>;
+			reg = <0x3000 0x200>;
+			rx-clock-name = "clk17";
+			tx-clock-name = "clk17";
+			phy-handle = <&phy1>;
+			phy-connection-type = "rmii";
+		};
+		eth1: ucc@2200 {
+			device_type = "network";
+			compatible = "ucc_geth";
+			cell-index = <3>;
+			reg = <0x2200 0x200>;
+			rx-clock-name = "clk12";
+			tx-clock-name = "clk12";
+			phy-handle = <&phy2>;
+			phy-connection-type = "rmii";
+		};
+		mdio@3120 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3120 0x18>;
+			compatible = "fsl,ucc-mdio";
+			phy1:ethernet-phy@1 {
+				interrupt-parent = <&ipic>;
+				reg = <0x1>;
+				interrupts = <17 8>;
+				device_type = "ethernet-phy";
+			};
+			phy2:ethernet-phy@2 {
+				interrupt-parent = <&ipic>;
+				reg = <0x2>;
+				interrupts = <17 8>;
+				device_type = "ethernet-phy";
+			};
+		};
+	};
+};
diff --git a/arch/powerpc/dts/mcr3000.dts b/arch/powerpc/dts/mcr3000.dts
index 5f32d8a..c4d7737 100644
--- a/arch/powerpc/dts/mcr3000.dts
+++ b/arch/powerpc/dts/mcr3000.dts
@@ -9,9 +9,25 @@
 /dts-v1/;
 
 / {
-	WDT: watchdog@0 {
-		compatible = "fsl,pq1-wdt";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	soc: immr@ff000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device-type = "soc";
+		compatible = "simple-bus";
+		ranges = <0 0xff000000 0x4000>;
+		reg = <0xff000000 0x00000200>;
+
+		WDT: watchdog@0 {
+			compatible = "fsl,pq1-wdt";
+			reg = <0x0 0x10>;
+			timeout-sec = <2>;
+			hw_margin_ms = <1000>;
+		};
 	};
+
 	SERIAL: smc@0 {
 		compatible = "fsl,pq1-smc";
 	};
diff --git a/arch/powerpc/dts/mpc8379erdb.dts b/arch/powerpc/dts/mpc8379erdb.dts
index 2e7c8f1..3db5ece 100644
--- a/arch/powerpc/dts/mpc8379erdb.dts
+++ b/arch/powerpc/dts/mpc8379erdb.dts
@@ -13,6 +13,11 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -60,6 +65,28 @@
 			clock-frequency = <0>;
 		};
 
+		serial0: serial@4500 {
+			cell-index = <0>;
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x4500 0x100>;
+			clock-frequency = <333333000>;
+			interrupts = <9 0x8>;
+			interrupt-parent = <&ipic>;
+			bootph-all;
+		};
+
+		serial1: serial@4600 {
+			cell-index = <1>;
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x4600 0x100>;
+			clock-frequency = <333333000>;
+			interrupts = <10 0x8>;
+			interrupt-parent = <&ipic>;
+			bootph-all;
+		};
+
 		ipic: interrupt-controller@700 {
 			compatible = "fsl,ipic";
 			interrupt-controller;
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
index 19c2506..df95d22 100644
--- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
@@ -22,6 +22,11 @@
        uint ngpios;
 };
 
+struct qe_gpio_plat {
+	ulong addr;
+	unsigned long size;
+};
+
 #ifndef DM_GPIO
 void mpc83xx_gpio_init_f(void);
 void mpc83xx_gpio_init_r(void);
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/soc.h b/arch/powerpc/include/asm/arch-mpc83xx/soc.h
index 39bf7d5..ce54f9b 100644
--- a/arch/powerpc/include/asm/arch-mpc83xx/soc.h
+++ b/arch/powerpc/include/asm/arch-mpc83xx/soc.h
@@ -18,14 +18,14 @@
 	SOC_MPC8379,
 };
 
-bool mpc83xx_has_sdhc(int type)
+static inline bool mpc83xx_has_sdhc(int type)
 {
 	return (type == SOC_MPC8308) ||
 	       (type == SOC_MPC8309) ||
 	       (type == SOC_MPC8379);
 }
 
-bool mpc83xx_has_tsec(int type)
+static inline bool mpc83xx_has_tsec(int type)
 {
 	return (type == SOC_MPC8308) ||
 	       (type == SOC_MPC8313) ||
@@ -34,37 +34,37 @@
 	       (type == SOC_MPC8379);
 }
 
-bool mpc83xx_has_pcie1(int type)
+static inline bool mpc83xx_has_pcie1(int type)
 {
 	return (type == SOC_MPC8308) ||
 	       (type == SOC_MPC8315) ||
 	       (type == SOC_MPC8379);
 }
 
-bool mpc83xx_has_pcie2(int type)
+static inline bool mpc83xx_has_pcie2(int type)
 {
 	return (type == SOC_MPC8315) ||
 	       (type == SOC_MPC8379);
 }
 
-bool mpc83xx_has_sata(int type)
+static inline bool mpc83xx_has_sata(int type)
 {
 	return (type == SOC_MPC8315) ||
 	       (type == SOC_MPC8379);
 }
 
-bool mpc83xx_has_pci(int type)
+static inline bool mpc83xx_has_pci(int type)
 {
 	return type != SOC_MPC8308;
 }
 
-bool mpc83xx_has_second_i2c(int type)
+static inline bool mpc83xx_has_second_i2c(int type)
 {
 	return (type != SOC_MPC8315) &&
 	       (type != SOC_MPC832X);
 }
 
-bool mpc83xx_has_quicc_engine(int type)
+static inline bool mpc83xx_has_quicc_engine(int type)
 {
 	return (type == SOC_MPC8309) ||
 	       (type == SOC_MPC832X) ||
diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h
index 83cfe23..8e9411a 100644
--- a/arch/powerpc/include/asm/mpc8xxx_spi.h
+++ b/arch/powerpc/include/asm/mpc8xxx_spi.h
@@ -12,6 +12,7 @@
 
 #if defined(CONFIG_ARCH_MPC8308) || \
 	defined(CONFIG_ARCH_MPC8313) || \
+	defined(CONFIG_ARCH_MPC832X) || \
 	defined(CONFIG_ARCH_MPC834X) || \
 	defined(CONFIG_ARCH_MPC837X)
 
diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c
index 636d354..5149633 100644
--- a/arch/sandbox/cpu/cpu.c
+++ b/arch/sandbox/cpu/cpu.c
@@ -31,7 +31,7 @@
 unsigned long map_len;
 #endif
 
-void sandbox_exit(void)
+void __noreturn sandbox_exit(void)
 {
 	/* Do this here while it still has an effect */
 	os_fd_restore();
@@ -230,7 +230,7 @@
 	return mentry->tag;
 }
 
-unsigned int sandbox_read(const void *addr, enum sandboxio_size_t size)
+unsigned long sandbox_read(const void *addr, enum sandboxio_size_t size)
 {
 	struct sandbox_state *state = state_get_current();
 
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 5e66304..9e93a0f 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -166,7 +166,7 @@
 	return 0;
 }
 
-int os_filesize(int fd)
+off_t os_filesize(int fd)
 {
 	off_t size;
 
@@ -218,7 +218,7 @@
 int os_map_file(const char *pathname, int os_flags, void **bufp, int *sizep)
 {
 	void *ptr;
-	int size;
+	off_t size;
 	int ifd;
 
 	ifd = os_open(pathname, os_flags);
@@ -231,6 +231,10 @@
 		printf("Cannot get file size of '%s'\n", pathname);
 		return -EIO;
 	}
+	if ((unsigned long long)size > (unsigned long long)SIZE_MAX) {
+		printf("File '%s' too large to map\n", pathname);
+		return -EIO;
+	}
 
 	ptr = mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, ifd, 0);
 	if (ptr == MAP_FAILED) {
diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index 69da378..d678349 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -10,6 +10,7 @@
 #include <fdtdec.h>
 #include <log.h>
 #include <os.h>
+#include <trace.h>
 #include <asm/malloc.h>
 #include <asm/state.h>
 #include <asm/test.h>
@@ -525,6 +526,10 @@
 	if (state->jumped_fname)
 		os_unlink(state->jumped_fname);
 
+	/* Disable tracing before unmapping RAM */
+	if (IS_ENABLED(CONFIG_TRACE))
+		trace_set_enabled(0);
+
 	os_free(state->state_fdt);
 	os_free(state->ram_buf);
 	memset(state, '\0', sizeof(*state));
diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts
index f21fc18..1953655 100644
--- a/arch/sandbox/dts/sandbox64.dts
+++ b/arch/sandbox/dts/sandbox64.dts
@@ -89,6 +89,19 @@
 		cs-gpios = <0>, <&gpio_a 0>;
 	};
 
+	nvmxip-qspi1@08000000 {
+		compatible = "nvmxip,qspi";
+		reg = /bits/ 64 <0x08000000 0x00200000>;
+		lba_shift = <9>;
+		lba = <4096>;
+	};
+
+	nvmxip-qspi2@08200000 {
+		compatible = "nvmxip,qspi";
+		reg = /bits/ 64 <0x08200000 0x00100000>;
+		lba_shift = <9>;
+		lba = <2048>;
+	};
 };
 
 #include "sandbox.dtsi"
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 7c1ee71..453e53d 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -1802,6 +1802,24 @@
 		compatible = "u-boot,fwu-mdata-gpt";
 		fwu-mdata-store = <&mmc0>;
 	};
+
+	nvmxip-qspi1@08000000 {
+		compatible = "nvmxip,qspi";
+		reg = <0x08000000 0x00200000>;
+		lba_shift = <9>;
+		lba = <4096>;
+	};
+
+	nvmxip-qspi2@08200000 {
+		compatible = "nvmxip,qspi";
+		reg = <0x08200000 0x00100000>;
+		lba_shift = <9>;
+		lba = <2048>;
+	};
+
+	extcon {
+		compatible = "sandbox,extcon";
+	};
 };
 
 #include "sandbox_pmic.dtsi"
diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h
index ad6c29a..31ab728 100644
--- a/arch/sandbox/include/asm/io.h
+++ b/arch/sandbox/include/asm/io.h
@@ -45,7 +45,7 @@
 /* Map from a pointer to our RAM buffer */
 phys_addr_t map_to_sysmem(const void *ptr);
 
-unsigned int sandbox_read(const void *addr, enum sandboxio_size_t size);
+unsigned long sandbox_read(const void *addr, enum sandboxio_size_t size);
 void sandbox_write(void *addr, unsigned int val, enum sandboxio_size_t size);
 
 #define readb(addr) sandbox_read((const void *)addr, SB_SIZE_8)
diff --git a/arch/sandbox/include/asm/posix_types.h b/arch/sandbox/include/asm/posix_types.h
index ec18ed7..e1442c4 100644
--- a/arch/sandbox/include/asm/posix_types.h
+++ b/arch/sandbox/include/asm/posix_types.h
@@ -1,5 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
- *  linux/include/asm-arm/posix_types.h
+ * Based on linux/include/asm-arm/posix_types.h
  *
  *  Copyright (C) 1996-1998 Russell King.
  *
@@ -10,8 +11,8 @@
  *  Changelog:
  *   27-06-1996	RMK	Created
  */
-#ifndef __ARCH_ARM_POSIX_TYPES_H
-#define __ARCH_ARM_POSIX_TYPES_H
+#ifndef __ARCH_SANDBOX_POSIX_TYPES_H
+#define __ARCH_SANDBOX_POSIX_TYPES_H
 
 /*
  * This file is generally used by user-level software, so you need to
diff --git a/arch/sandbox/include/asm/u-boot-sandbox.h b/arch/sandbox/include/asm/u-boot-sandbox.h
index 9eb1932..e702774 100644
--- a/arch/sandbox/include/asm/u-boot-sandbox.h
+++ b/arch/sandbox/include/asm/u-boot-sandbox.h
@@ -87,6 +87,6 @@
 void sandbox_reset(void);
 
 /* Exit sandbox (quit U-Boot) */
-void sandbox_exit(void);
+void __noreturn sandbox_exit(void);
 
 #endif	/* _U_BOOT_SANDBOX_H_ */
diff --git a/board/advantech/imx8qm_dmsse20_a1/Kconfig b/board/advantech/imx8qm_dmsse20_a1/Kconfig
new file mode 100644
index 0000000..f249ab4
--- /dev/null
+++ b/board/advantech/imx8qm_dmsse20_a1/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX8QM_DMSSE20_A1
+
+config SYS_BOARD
+	default "imx8qm_dmsse20_a1"
+
+config SYS_VENDOR
+	default "advantech"
+
+config SYS_CONFIG_NAME
+	default "imx8qm_dmsse20"
+
+config IMX_CONFIG
+	default "board/advantech/imx8qm_dmsse20_a1/imximage.cfg"
+
+endif
diff --git a/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS b/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS
new file mode 100644
index 0000000..8292c6b
--- /dev/null
+++ b/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS
@@ -0,0 +1,7 @@
+i.MX8QM ROM DMSSE20 a1 BOARD
+M:	Oliver Graute <oliver.graute@kococonnector.com>
+S:	Maintained
+F:	board/advantech/imx8qm_dmsse20_a1/
+F:	arch/arm/dts/imx8qm-dmsse20-a1.dtb
+F:	include/configs/imx8qm_dmsse20.h
+F:	configs/imx8qm_dmsse20a1_defconfig
diff --git a/board/advantech/imx8qm_dmsse20_a1/Makefile b/board/advantech/imx8qm_dmsse20_a1/Makefile
new file mode 100644
index 0000000..262ffcd
--- /dev/null
+++ b/board/advantech/imx8qm_dmsse20_a1/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += imx8qm_dmsse20_a1.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env
new file mode 100644
index 0000000..0c9f9c4
--- /dev/null
+++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env
@@ -0,0 +1,48 @@
+script=boot.scr
+image=Image
+panel=NULL
+console=ttyLP0
+earlycon=lpuart32,0x5a060000
+fdt_addr=0x83000000
+boot_fdt=try
+fdt_file=imx8qm-dmsse20-a1.dtb
+mmcdev= __stringify(CONFIG_SYS_MMC_ENV_DEV)
+mmcpart= __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART)
+mmcroot=/dev/mmcblk1p2 rootwait rw
+mmcautodetect=yes
+mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}
+loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};
+bootscript=echo Running bootscript from mmc ...; source
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}
+mmcboot=echo Booting from mmc ...;
+	run mmcargs;
+	if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
+		if run loadfdt; then
+			booti ${loadaddr} - ${fdt_addr};
+		else
+			echo WARN: Cannot load the DT;
+		fi;
+	else
+		echo wait for boot;
+	fi;
+netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate}
+	root=/dev/nfs
+	ip=dhcp mac=${ethaddr} nfsroot=${serverip}:${nfsroot},v3,tcp rw
+netboot=echo Booting from net ...;
+	run netargs;
+	if test ${ip_dyn} = yes; then
+		setenv get_cmd dhcp;
+	else
+		setenv get_cmd tftp;
+	fi;
+	${get_cmd} ${loadaddr} ${image};
+	if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
+		if ${get_cmd} ${fdt_addr} ${fdt_file}; then
+			booti ${loadaddr} - ${fdt_addr};
+		else
+			echo WARN: Cannot load the DT;
+		fi;
+	else
+		booti;
+	fi;
diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c
new file mode 100644
index 0000000..867ceff
--- /dev/null
+++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ * Copyright 2019-2023 Kococonnector GmbH
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <linux/libfdt.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+/* #include <power-domain.h> */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart0_pads[] = {
+	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
+}
+
+int board_early_init_f(void)
+{
+	sc_pm_clock_rate_t rate = SC_80MHZ;
+	int ret;
+
+	/* Set UART0 clock root to 80 MHz */
+	ret = sc_pm_setup_uart(SC_R_UART_0, rate);
+	if (ret)
+		return ret;
+
+	setup_iomux_uart();
+
+	/* This is needed to because Kernel do not Power Up DC_0 */
+	sc_pm_set_resource_power_mode(-1, SC_R_DC_0, SC_PM_PW_MODE_ON);
+	sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON);
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MXC_GPIO
+
+#define LVDS_ENABLE IMX_GPIO_NR(1, 6)
+#define MIPI_ENABLE IMX_GPIO_NR(1, 7)
+
+#define BB_GPIO_3V3_1 IMX_GPIO_NR(4, 20)
+#define BB_GPIO_3V3_2 IMX_GPIO_NR(4, 24)
+#define BB_GPIO_3V3_3 IMX_GPIO_NR(4, 23)
+
+static void board_gpio_init(void)
+{
+	/* Enable BB 3V3 */
+	gpio_request(BB_GPIO_3V3_1, "bb_3v3_1");
+	gpio_direction_output(BB_GPIO_3V3_1, 1);
+	gpio_request(BB_GPIO_3V3_2, "bb_3v3_2");
+	gpio_direction_output(BB_GPIO_3V3_2, 1);
+	gpio_request(BB_GPIO_3V3_3, "bb_3v3_3");
+	gpio_direction_output(BB_GPIO_3V3_3, 1);
+
+	/* enable LVDS SAS boards */
+	gpio_request(LVDS_ENABLE, "lvds_enable");
+	gpio_direction_output(LVDS_ENABLE, 1);
+
+	/* enable MIPI SAS boards */
+	gpio_request(MIPI_ENABLE, "mipi_enable");
+	gpio_direction_output(MIPI_ENABLE, 1);
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: DMS-SE20A1 8GB\n");
+	build_info();
+	print_bootinfo();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	if (IS_ENABLED(CONFIG_XEN))
+		return 0;
+
+#ifdef CONFIG_MXC_GPIO
+	board_gpio_init();
+#endif
+
+	return 0;
+}
+
+void board_quiesce_devices(void)
+{
+	if (IS_ENABLED(CONFIG_XEN)) {
+		/* Clear magic number to let xen know uboot is over */
+		writel(0x0, (void __iomem *)0x80000000);
+		return;
+	}
+}
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(void)
+{
+	puts("SCI reboot request");
+
+	while (1)
+		putc('.');
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+	/* Use EMMC */
+	if (IS_ENABLED(CONFIG_XEN))
+		return 0;
+
+	return devno;
+}
+
+int mmc_map_to_kernel_blk(int dev_no)
+{
+	/* Use EMMC */
+	if (IS_ENABLED(CONFIG_XEN))
+		return 0;
+
+	return dev_no;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "DMS-SE20A1");
+	env_set("board_rev", "iMX8QM");
+#endif
+
+	env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+	env_set("sec_boot", "yes");
+#endif
+
+	return 0;
+}
diff --git a/board/advantech/imx8qm_dmsse20_a1/imximage.cfg b/board/advantech/imx8qm_dmsse20_a1/imximage.cfg
new file mode 100644
index 0000000..2e51e57
--- /dev/null
+++ b/board/advantech/imx8qm_dmsse20_a1/imximage.cfg
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier:	GPL-2.0-or-later */
+/*
+ * Copyright 2017-2018 NXP
+ * Copyright 2019-2023 Kococonnector GmbH
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+/* SoC type IMX8QM */
+BOOT_FROM	sd
+
+SOC_TYPE IMX8QM
+/* Append seco container image */
+APPEND mx8qm-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qm-val-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 bl31.bin 0x80000000
+/* Add U-Boot image with load attribute */
+DATA A35 u-boot-dtb.bin 0x80020000
diff --git a/board/advantech/imx8qm_dmsse20_a1/spl.c b/board/advantech/imx8qm_dmsse20_a1/spl.c
new file mode 100644
index 0000000..49067bb
--- /dev/null
+++ b/board/advantech/imx8qm_dmsse20_a1/spl.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2017-2018 NXP
+ * Copyright 2019-2023 Kococonnector GmbH
+ */
+#include <common.h>
+#include <dm.h>
+#include <spl.h>
+#include <init.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <fsl_esdhc_imx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ESDHC_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ESDHC_CLK_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_INPUT_PAD_CTRL	((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_NORMAL_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define FSPI_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define I2C_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+#ifdef CONFIG_FSL_ESDHC_IMX
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(5, 22)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(4, 12)
+
+static struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC3_BASE_ADDR, 0, 4},
+};
+
+static iomux_cfg_t emmc0[] = {
+	SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
+	SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+static iomux_cfg_t usdhc2_sd[] = {
+	SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
+	SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_WP   | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+void init_clk_usdhc(u32 index);
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 * mmc2                    USDHC3
+	 */
+	for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
+			if (ret != SC_ERR_NONE)
+				return ret;
+
+			imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
+			init_clk_usdhc(0);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		case 1:
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
+			if (ret != SC_ERR_NONE)
+				return ret;
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
+			if (ret != SC_ERR_NONE)
+				return ret;
+
+			imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
+			init_clk_usdhc(2);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			gpio_request(USDHC2_CD_GPIO, "sd2_cd");
+			gpio_direction_input(USDHC2_CD_GPIO);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return 0;
+		}
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+#endif /* CONFIG_FSL_ESDHC_IMX */
+
+void spl_board_init(void)
+{
+#if defined(CONFIG_SPL_SPI_SUPPORT)
+	if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
+		if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) {
+			puts("Warning: failed to initialize FSPI0\n");
+		}
+	}
+#endif
+
+	puts("Normal Boot\n");
+}
+
+void spl_board_prepare_for_boot(void)
+{
+#if defined(CONFIG_SPL_SPI_SUPPORT)
+	if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
+		if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) {
+			puts("Warning: failed to turn off FSPI0\n");
+		}
+	}
+#endif
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	board_init_r(NULL, 0);
+}
diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig
index 5616e22..cf998096 100644
--- a/board/armltd/vexpress64/Kconfig
+++ b/board/armltd/vexpress64/Kconfig
@@ -12,8 +12,13 @@
 config VEXPRESS64_BASE_MODEL
 	bool
 	select SEMIHOSTING
+	imply VIRTIO_MMIO
 	select VIRTIO_BLK if VIRTIO_MMIO
 	select VIRTIO_NET if VIRTIO_MMIO
+	select DM_ETH if VIRTIO_NET
+	imply RTC_PL031
+	select DM_RTC if RTC_PL031
+	imply EFI_SET_TIME if DM_RTC
 	select LINUX_KERNEL_IMAGE_HEADER
 	select POSITION_INDEPENDENT
 
@@ -23,7 +28,7 @@
 config TARGET_VEXPRESS64_BASE_FVP
 	bool "Support Versatile Express ARMv8a FVP BASE model"
 	select VEXPRESS64_BASE_MODEL
-	select OF_BOARD
+	imply OF_HAS_PRIOR_STAGE
 
 config TARGET_VEXPRESS64_BASER_FVP
 	bool "Support Versatile Express ARMv8r64 FVP BASE model"
diff --git a/board/broadcom/bcmns/Kconfig b/board/broadcom/bcmns/Kconfig
new file mode 100644
index 0000000..82f4709
--- /dev/null
+++ b/board/broadcom/bcmns/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_BCMNS
+
+config SYS_BOARD
+	default "bcmns"
+
+config SYS_VENDOR
+	default "broadcom"
+
+config SYS_CONFIG_NAME
+	default "bcmns"
+
+endif
diff --git a/board/broadcom/bcmns/MAINTAINERS b/board/broadcom/bcmns/MAINTAINERS
new file mode 100644
index 0000000..fd37c33
--- /dev/null
+++ b/board/broadcom/bcmns/MAINTAINERS
@@ -0,0 +1,6 @@
+BCMNS BOARD
+M:	Linus Walleij <linus.walleij@linaro.org>
+S:	Maintained
+F:	board/broadcom/bcmnsp/
+F:	configs/bcmnsp_defconfig
+F:	include/configs/bcmnsp.h
diff --git a/board/broadcom/bcmns/Makefile b/board/broadcom/bcmns/Makefile
new file mode 100644
index 0000000..8a6a854
--- /dev/null
+++ b/board/broadcom/bcmns/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+obj-y	:= ns.o
diff --git a/board/broadcom/bcmns/ns.c b/board/broadcom/bcmns/ns.c
new file mode 100644
index 0000000..1249e45
--- /dev/null
+++ b/board/broadcom/bcmns/ns.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Broadcom Northstar generic board set-up code
+ * Copyright (C) 2023 Linus Walleij <linus.walleij@linaro.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <ram.h>
+#include <serial.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+int board_late_init(void)
+{
+	/* LEDs etc can be initialized here */
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(void)
+{
+}
+
+int print_cpuinfo(void)
+{
+	printf("BCMNS Northstar SoC\n");
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+int ft_board_setup(void *fdt, struct bd_info *bd)
+{
+	printf("Northstar board setup: DTB at 0x%08lx\n", (ulong)fdt);
+	return 0;
+}
+
diff --git a/board/cssi/MAINTAINERS b/board/cssi/MAINTAINERS
index d8e7b5e..f82dd3b 100644
--- a/board/cssi/MAINTAINERS
+++ b/board/cssi/MAINTAINERS
@@ -6,3 +6,5 @@
 F:	configs/MCR3000_defconfig
 F:	include/configs/cmpc885.h
 F:	configs/CMPC885_defconfig
+F:	include/configs/cmpcpro.h
+F:	configs/CMPCPRO_defconfig
diff --git a/board/cssi/cmpc885/Makefile b/board/cssi/cmpc885/Makefile
index 6c05509..baf9e5a 100644
--- a/board/cssi/cmpc885/Makefile
+++ b/board/cssi/cmpc885/Makefile
@@ -5,6 +5,6 @@
 # Christophe Leroy <christophe.leroy@c-s.fr>
 #
 
-obj-y += cmpc885.o
+obj-y += cmpc885.o ../common/common.o
 obj-y += sdram.o
 obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/board/cssi/cmpc885/cmpc885.c b/board/cssi/cmpc885/cmpc885.c
index 5233c24..540b9d3 100644
--- a/board/cssi/cmpc885/cmpc885.c
+++ b/board/cssi/cmpc885/cmpc885.c
@@ -22,98 +22,28 @@
 #include <init.h>
 #include <fdt_support.h>
 #include <linux/delay.h>
-
 #include <spi.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
-#define BOARD_CMPC885		"cmpc885"
-#define BOARD_MCR3000_2G	"mcr3k_2g"
-#define BOARD_VGOIP		"vgoip"
-#define BOARD_MIAE		"miae"
+#include "../common/common.h"
 
-#define TYPE_MCR	0x22
-#define TYPE_MIAE	0x23
-
-#define FAR_CASRSA     2
-#define FAR_VGOIP      4
-#define FAV_CLA        7
-#define FAV_SRSA       8
+DECLARE_GLOBAL_DATA_PTR;
 
 #define ADDR_CPLD_R_RESET		((unsigned short __iomem *)CONFIG_CPLD_BASE)
 #define ADDR_CPLD_R_ETAT		((unsigned short __iomem *)(CONFIG_CPLD_BASE + 2))
 #define ADDR_CPLD_R_TYPE		((unsigned char  __iomem *)(CONFIG_CPLD_BASE + 3))
 
-#define ADDR_FPGA_R_BASE		((unsigned char  __iomem *)CONFIG_FPGA_BASE)
-#define ADDR_FPGA_R_ALARMES_IN		((unsigned char  __iomem *)CONFIG_FPGA_BASE + 0x31)
-#define ADDR_FPGA_R_FAV			((unsigned char  __iomem *)CONFIG_FPGA_BASE + 0x44)
-
 #define PATH_PHY2			"/soc@ff000000/mdio@e00/ethernet-phy@2"
 #define PATH_PHY3			"/soc@ff000000/mdio@e00/ethernet-phy@3"
 #define PATH_ETH1			"/soc@ff000000/ethernet@1e00"
 #define FIBER_PHY PATH_PHY2
 
-#define FPGA_R_ACQ_AL_FAV	0x04
 #define R_ETAT_PRES_BASE	0x0040
 
 #define R_RESET_STATUS		0x0400
 #define R_RST_STATUS		0x0004
 
-static int fdt_set_node_and_value(void *blob, char *node, const char *prop,
-				  void *var, int size)
-{
-	int ret, off;
-
-	off = fdt_path_offset(blob, node);
-
-	if (off < 0) {
-		printf("Cannot find %s node err:%s\n", node, fdt_strerror(off));
-
-		return off;
-	}
-
-	ret = fdt_setprop(blob, off, prop, var, size);
-
-	if (ret < 0)
-		printf("Cannot set %s/%s prop err: %s\n", node, prop, fdt_strerror(ret));
-
-	return ret;
-}
-
-/* Checks front/rear id and remove unneeded nodes from the blob */
-static void ft_cleanup(void *blob, uint32_t id, const char *prop, const char *compatible)
-{
-	int off;
-
-	off = fdt_node_offset_by_compatible(blob, -1, compatible);
-
-	while (off != -FDT_ERR_NOTFOUND) {
-		const struct fdt_property *ids;
-		int nb_ids, idx;
-		int tmp = -1;
-
-		ids = fdt_get_property(blob, off, prop, &nb_ids);
-
-		for (idx = 0; idx < nb_ids; idx += 4) {
-			if (*((uint32_t *)&ids->data[idx]) == id)
-				break;
-		}
-
-		if (idx >= nb_ids)
-			fdt_del_node(blob, off);
-		else
-			tmp = off;
-
-		off = fdt_node_offset_by_compatible(blob, tmp, compatible);
-	}
-
-	fdt_set_node_and_value(blob, "/", prop, &id, sizeof(uint32_t));
-}
-
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
-	u8 fav_id, far_id;
-
 	const char *sync = "receive";
 
 	ft_cpu_setup(blob, bd);
@@ -137,32 +67,19 @@
 	do_fixup_by_path(blob, "/localbus/e1", "rising-edge-sync-pulse", sync, strlen(sync), 1);
 
 	/* MIAE only */
-	if (!(in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE) || in_8(ADDR_FPGA_R_BASE) != TYPE_MIAE)
+	if (!(in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE))
 		return 0;
 
-	far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5;
-	ft_cleanup(blob, (u32)far_id, "far-id", "cs,mia-far");
-
-	/*
-	 * special case, with CASRSA (far_id: 2)
-	 * FAV-SRSA register itself as FAV-CLA
-	 */
-	fav_id = in_8(ADDR_FPGA_R_BASE + 0x44) >> 5;
-
-	if (far_id == FAR_CASRSA && fav_id == FAV_CLA)
-		fav_id = FAV_SRSA;
-
-	ft_cleanup(blob, (u32)fav_id, "fav-id", "cs,mia-fav");
-
-	if (far_id == FAR_CASRSA) {
-		/* switch to phy3 with gpio, we'll only use phy3 */
-		immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
-		cpm8xx_t __iomem *cp = (cpm8xx_t __iomem *)&immr->im_cpm;
+	return ft_board_setup_common(blob);
+}
 
-		setbits_be32(&cp->cp_pedat, 0x00002000);
-	}
+void ft_board_setup_phy3(void)
+{
+	/* switch to phy3 with gpio, we'll only use phy3 */
+	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	cpm8xx_t __iomem *cp = (cpm8xx_t __iomem *)&immr->im_cpm;
 
-	return 0;
+	setbits_be32(&cp->cp_pedat, 0x00002000);
 }
 
 int checkboard(void)
@@ -170,73 +87,29 @@
 	serial_puts("Board: ");
 
 	/* Is a motherboard present ? */
-	if (in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE) {
-		switch (in_8(ADDR_FPGA_R_BASE)) {
-			int far_id;
-		case TYPE_MCR:
-			printf("MCR3000_2G (CS GROUP)\n");
-			break;
-		case TYPE_MIAE:
-			far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5;
+	if (in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE)
+		return checkboard_common();
 
-			if (far_id == FAR_VGOIP)
-				printf("VGoIP (CS GROUP)\n");
-			else
-				printf("MIAE (CS GROUP)\n");
+	printf("CMPC885 (CS GROUP)\n");
 
-			break;
-		default:
-			printf("Unknown\n");
-			for (;;)
-				;
-			break;
-		}
-	} else {
-		printf("CMPC885 (CS GROUP)\n");
-	}
 	return 0;
 }
 
-#define SPI_EEPROM_READ	0x03
 #define MAX_SPI_BYTES	0x20
 
-#define EE_OFF_MAC1	0x13
-#define EE_OFF_MAC2	0x19
+#define EE_OFF_MAC1	0x10
+#define EE_OFF_MAC2	0x16
 
 /* Reads MAC addresses from SPI EEPROM */
 static int setup_mac(void)
 {
-	struct udevice *eeprom;
-	struct spi_slave *slave;
-	char name[30], *str;
 	uchar din[MAX_SPI_BYTES];
-	uchar dout[MAX_SPI_BYTES] = {SPI_EEPROM_READ, 0, 0};
-	int bitlen = 256, cs = 0, mode = 0, bus = 0, ret;
+	int ret;
 	unsigned long ident = 0x08005120;
 
-	snprintf(name, sizeof(name), "generic_%d:%d", bus, cs);
-
-	str = strdup(name);
-	if (!str)
-		return -1;
-
-	ret = uclass_get_device(UCLASS_SPI, 0, &eeprom);
-	if (ret) {
-		printf("Could not enable Serial Peripheral Interface (SPI).\n");
-		return -1;
-	}
-
-	ret = _spi_get_bus_and_cs(bus, cs, 1000000, mode, "spi_generic_drv", str, &eeprom, &slave);
+	ret = read_eeprom(din, sizeof(din));
 	if (ret)
 		return ret;
-
-	ret = spi_claim_bus(slave);
-
-	ret = spi_xfer(slave, bitlen, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
-	if (ret) {
-		printf("Error %d during SPI transaction\n", ret);
-		return ret;
-	}
 
 	if (memcmp(din + EE_OFF_MAC1, &ident, sizeof(ident)) == 0)
 		eth_env_set_enetaddr("ethaddr", din + EE_OFF_MAC1);
@@ -244,64 +117,17 @@
 	if (memcmp(din + EE_OFF_MAC2, &ident, sizeof(ident)) == 0)
 		eth_env_set_enetaddr("eth1addr", din + EE_OFF_MAC2);
 
-	spi_release_bus(slave);
-
 	return 0;
 }
 
 int misc_init_r(void)
 {
-	u8 val, tmp, far_id;
-	int count = 3;
-
-	val = in_8(ADDR_FPGA_R_BASE);
-
 	/* Verify mother board presence */
 	if (in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE) {
-		/* identify the type of mother board */
-		switch (val) {
-		case TYPE_MCR:
-			/* if at boot alarm button is pressed, delay boot */
-			if ((in_8(ADDR_FPGA_R_ALARMES_IN) & FPGA_R_ACQ_AL_FAV) == 0)
-				env_set("bootdelay", "60");
-
-			env_set("config", BOARD_MCR3000_2G);
-			env_set("hostname", BOARD_MCR3000_2G);
-			break;
-
-		case TYPE_MIAE:
-			do {
-				tmp = in_8(ADDR_FPGA_R_BASE + 0x41);
-				count--;
-				mdelay(10); /* 10msec wait */
-			} while (count && tmp != in_8(ADDR_FPGA_R_BASE + 0x41));
-
-			if (!count) {
-				printf("Cannot read the reset factory switch position\n");
-				hang();
-			}
-
-			if (tmp & 0x1)
-				env_set_default("Factory settings switch ON", 0);
-
-			env_set("config", BOARD_MIAE);
-			far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5;
-
-			if (far_id == FAR_VGOIP)
-				env_set("hostname", BOARD_VGOIP);
-			else
-				env_set("hostname", BOARD_MIAE);
-			break;
-
-		default:
-			env_set("config", BOARD_CMPC885);
-			env_set("hostname", BOARD_CMPC885);
-			break;
-		}
+		misc_init_r_common();
 	} else {
-		printf("no mother board detected");
-		env_set("config", BOARD_CMPC885);
-		env_set("hostname", BOARD_CMPC885);
+		env_set("config", CFG_BOARD_CMPCXXX);
+		env_set("hostname", CFG_BOARD_CMPCXXX);
 	}
 
 	if (setup_mac())
@@ -313,7 +139,7 @@
 	return 0;
 }
 
-static void iop_setup_mcr(void)
+void iop_setup_mcr(void)
 {
 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	iop8xx_t __iomem *iop = &immr->im_ioport;
@@ -616,7 +442,7 @@
 	clrbits_be32(&cp->cp_peso, 0x00031980);
 }
 
-static void iop_setup_miae(void)
+void iop_setup_miae(void)
 {
 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	iop8xx_t __iomem *iop = &immr->im_ioport;
@@ -626,7 +452,7 @@
 	udelay(100);
 
 	/* Set the front panel LED color to red */
-	clrbits_8(ADDR_FPGA_R_FAV, 0x02);
+	clrbits_8((unsigned char  __iomem *)CONFIG_FPGA_BASE + 0x44, 0x02);
 
 	/* We must initialize data before changing direction */
 	setbits_be16(&iop->iop_pcdat, 0x0888);
@@ -1084,20 +910,7 @@
 			mdelay(200);
 		}
 
-		/* Identify the type of mother board */
-		switch (in_8(ADDR_FPGA_R_BASE)) {
-		case TYPE_MCR:
-			iop_setup_mcr();
-			break;
-
-		case TYPE_MIAE:
-			iop_setup_miae();
-			break;
-
-		default:
-			break;
-		}
-	/* CMPC885 board alone */
+		iop_setup_common();
 	} else {
 		iop_setup_cmpc885();
 	}
diff --git a/board/cssi/cmpcpro/Kconfig b/board/cssi/cmpcpro/Kconfig
new file mode 100644
index 0000000..b5d998a
--- /dev/null
+++ b/board/cssi/cmpcpro/Kconfig
@@ -0,0 +1,26 @@
+if TARGET_CMPCPRO
+
+config SYS_BOARD
+	default "cmpcpro"
+
+config SYS_VENDOR
+	default "cssi"
+
+config SYS_CONFIG_NAME
+	default "cmpcpro"
+
+config TEXT_BASE
+	default 0x40000000
+
+config CPLD_BASE
+	hex
+	default 0x90000000
+
+config FPGA_BASE
+	hex
+	default 0x80000000
+
+config PCI
+	default no
+
+endif
diff --git a/board/cssi/cmpcpro/Makefile b/board/cssi/cmpcpro/Makefile
new file mode 100644
index 0000000..73ff451
--- /dev/null
+++ b/board/cssi/cmpcpro/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += cmpcpro.o nand.o ../common/common.o
diff --git a/board/cssi/cmpcpro/cmpcpro.c b/board/cssi/cmpcpro/cmpcpro.c
new file mode 100644
index 0000000..3e9ba6a
--- /dev/null
+++ b/board/cssi/cmpcpro/cmpcpro.c
@@ -0,0 +1,404 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2006-2023  CS GROUP France
+ */
+
+#include <command.h>
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <env_internal.h>
+#include <eeprom.h>
+#include <fdt_support.h>
+#include <hang.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <netdev.h>
+#include <spi.h>
+#include <stdarg.h>
+#include <stdlib.h>
+
+#include <linux/delay.h>
+#include <linux/immap_qe.h>
+#include <linux/libfdt.h>
+#include <linux/log2.h>
+#include <linux/sizes.h>
+
+#include <asm/io.h>
+#include <asm/global_data.h>
+#include <asm/mmu.h>
+
+#include <u-boot/crc.h>
+
+#include "../common/common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ADDR_FPGA_BASE		((unsigned char __iomem *)CONFIG_CPLD_BASE)
+#define ADDR_FPGA_RESET_G	(ADDR_FPGA_BASE + 0x40)
+#define ADDR_FPGA_REG_ETAT	(ADDR_FPGA_BASE + 0x42)
+
+#define R_ETAT_PRES_BASE	0x01
+#define RESET_G_OK		0x08
+
+/* SPI EEPROM parameters */
+#define MAX_SPI_BYTES	0x28
+#define EE_OFF_MAC1	0x10
+#define EE_OFF_MAC2	0x16
+#define EE_OFF_MAC3	0x1C
+
+static uint upma_table[] = {
+	/* Read Single-Beat (RSS) */
+	0x00AC0C00, 0x00FC1C40, 0x30FCE045, 0xFFFF0C00,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	/* Read Burst (RBS) */
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	/* Write Single-Beat (WSS) */
+	0x00A30C00, 0x00F31C40, 0x3FF3C045, 0xFFFF0C00,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	/* Write Burst (WBS) */
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	/* Refresh Timer (RTS) */
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	/* Exception Condition (EXS) */
+	0xFFFF0C01, 0xFFFF0C01, 0xFFFF0C01, 0xFFFF0C01,
+};
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+	/* ETH3 */
+	{1,  0, 1, 0, 1}, /* TxD0 */
+	{1,  1, 1, 0, 1}, /* TxD1 */
+	{1,  2, 1, 0, 1}, /* TxD2 */
+	{1,  3, 1, 0, 1}, /* TxD3 */
+	{1,  9, 1, 0, 1}, /* TxER */
+	{1, 12, 1, 0, 1}, /* TxEN */
+	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
+
+	{1,  4, 2, 0, 1}, /* RxD0 */
+	{1,  5, 2, 0, 1}, /* RxD1 */
+	{1,  6, 2, 0, 1}, /* RxD2 */
+	{1,  7, 2, 0, 1}, /* RxD3 */
+	{1,  8, 2, 0, 1}, /* RxER */
+	{1, 10, 2, 0, 1}, /* RxDV */
+	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
+	{1, 11, 2, 0, 1}, /* COL */
+	{1, 13, 2, 0, 1}, /* CRS */
+
+	/* ETH4 */
+	{1, 18, 1, 0, 1}, /* TxD0 */
+	{1, 19, 1, 0, 1}, /* TxD1 */
+	{1, 20, 1, 0, 1}, /* TxD2 */
+	{1, 21, 1, 0, 1}, /* TxD3 */
+	{1, 27, 1, 0, 1}, /* TxER */
+	{1, 30, 1, 0, 1}, /* TxEN */
+	{3,  6, 2, 0, 1}, /* TxCLK->CLK8 */
+
+	{1, 22, 2, 0, 1}, /* RxD0 */
+	{1, 23, 2, 0, 1}, /* RxD1 */
+	{1, 24, 2, 0, 1}, /* RxD2 */
+	{1, 25, 2, 0, 1}, /* RxD3 */
+	{1, 26, 1, 0, 1}, /* RxER */
+	{1, 28, 2, 0, 1}, /* Rx_DV */
+	{3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
+	{1, 29, 2, 0, 1}, /* COL */
+	{1, 31, 2, 0, 1}, /* CRS */
+
+	{3,  4, 3, 0, 2}, /* MDIO */
+	{3,  5, 1, 0, 2}, /* MDC */
+
+	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
+void iop_setup_miae(void)
+{
+	immap_t __iomem *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	/* PORTA configuration */
+	out_be32(&im->qepio.ioport[0].pdat, 0x00808000);
+	out_be32(&im->qepio.ioport[0].podr, 0x00008000);
+	out_be32(&im->qepio.ioport[0].dir1, 0x40800968);
+	out_be32(&im->qepio.ioport[0].dir2, 0x650A0896);
+	out_be32(&im->qepio.ioport[0].ppar1, 0x40400204);
+	out_be32(&im->qepio.ioport[0].ppar2, 0x05050464);
+
+	/* PORTB configuration */
+	out_be32(&im->qepio.ioport[1].pdat, 0x00018000);
+	out_be32(&im->qepio.ioport[1].podr, 0x00000000);
+	out_be32(&im->qepio.ioport[1].dir1, 0x50A08949);
+	out_be32(&im->qepio.ioport[1].dir2, 0x5C0C6890);
+	out_be32(&im->qepio.ioport[1].ppar1, 0x50504644);
+	out_be32(&im->qepio.ioport[1].ppar2, 0x080800A0);
+
+	/* PORTC configuration */
+	out_be32(&im->qepio.ioport[2].pdat, 0x3D000108);
+	out_be32(&im->qepio.ioport[2].podr, 0x00000000);
+	out_be32(&im->qepio.ioport[2].dir1, 0x45518000);
+	out_be32(&im->qepio.ioport[2].dir2, 0xA8119561);
+	out_be32(&im->qepio.ioport[2].ppar1, 0x80008000);
+	out_be32(&im->qepio.ioport[2].ppar2, 0x00000000);
+
+	/* PORTD configuration */
+	out_be32(&im->qepio.ioport[3].pdat, 0x1000E000);
+	out_be32(&im->qepio.ioport[3].podr, 0x0000E000);
+	out_be32(&im->qepio.ioport[3].dir1, 0xFDD20800);
+	out_be32(&im->qepio.ioport[3].dir2, 0x54155228);
+	out_be32(&im->qepio.ioport[3].ppar1, 0x54A30C00);
+	out_be32(&im->qepio.ioport[3].ppar2, 0x00000100);
+}
+
+void iop_setup_mcr(void)
+{
+	immap_t __iomem *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	/* PORTA configuration */
+	out_be32(&im->qepio.ioport[0].pdat, 0x00808004);
+	out_be32(&im->qepio.ioport[0].podr, 0x00000000);
+	out_be32(&im->qepio.ioport[0].dir1, 0x40800A68);
+	out_be32(&im->qepio.ioport[0].dir2, 0x650A0896);
+	out_be32(&im->qepio.ioport[0].ppar1, 0x40400004);
+	out_be32(&im->qepio.ioport[0].ppar2, 0x05050444);
+
+	/* PORTB configuration */
+	out_be32(&im->qepio.ioport[1].pdat, 0x00008000);
+	out_be32(&im->qepio.ioport[1].podr, 0x00000004);
+	out_be32(&im->qepio.ioport[1].dir1, 0x50A08A4A);
+	out_be32(&im->qepio.ioport[1].dir2, 0x5C0C6890);
+	out_be32(&im->qepio.ioport[1].ppar1, 0x50504444);
+	out_be32(&im->qepio.ioport[1].ppar2, 0x08080080);
+
+	/* PORTC configuration */
+	out_be32(&im->qepio.ioport[2].pdat, 0x3D000018);
+	out_be32(&im->qepio.ioport[2].podr, 0x00000400);
+	out_be32(&im->qepio.ioport[2].dir1, 0x45518000);
+	out_be32(&im->qepio.ioport[2].dir2, 0xA8129561);
+	out_be32(&im->qepio.ioport[2].ppar1, 0x80008000);
+	out_be32(&im->qepio.ioport[2].ppar2, 0x00000000);
+
+	/* PORTD configuration */
+	out_be32(&im->qepio.ioport[3].pdat, 0x1000E000);
+	out_be32(&im->qepio.ioport[3].podr, 0x0000E000);
+	out_be32(&im->qepio.ioport[3].dir1, 0xFDD20800);
+	out_be32(&im->qepio.ioport[3].dir2, 0x54155228);
+	out_be32(&im->qepio.ioport[3].ppar1, 0x54A30C00);
+	out_be32(&im->qepio.ioport[3].ppar2, 0x00000100);
+}
+
+static void iop_setup_cmpcpro(void)
+{
+	immap_t __iomem *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	/* PORTA configuration */
+	out_be32(&im->qepio.ioport[0].pdat, 0x00000000);
+	out_be32(&im->qepio.ioport[0].podr, 0x00000000);
+	out_be32(&im->qepio.ioport[0].dir1, 0x50A84020);
+	out_be32(&im->qepio.ioport[0].dir2, 0x00000000);
+	out_be32(&im->qepio.ioport[0].ppar1, 0xF0FCC000);
+	out_be32(&im->qepio.ioport[0].ppar2, 0x00000000);
+
+	/* PORTB configuration */
+	out_be32(&im->qepio.ioport[1].pdat, 0x00000000);
+	out_be32(&im->qepio.ioport[1].podr, 0x00000000);
+	out_be32(&im->qepio.ioport[1].dir1, 0x00000000);
+	out_be32(&im->qepio.ioport[1].dir2, 0x00006800);
+	out_be32(&im->qepio.ioport[1].ppar1, 0x00000000);
+	out_be32(&im->qepio.ioport[1].ppar2, 0x00000000);
+
+	/* PORTC configuration */
+	out_be32(&im->qepio.ioport[2].pdat, 0x19000000);
+	out_be32(&im->qepio.ioport[2].podr, 0x00000000);
+	out_be32(&im->qepio.ioport[2].dir1, 0x01410000);
+	out_be32(&im->qepio.ioport[2].dir2, 0xA8009400);
+	out_be32(&im->qepio.ioport[2].ppar1, 0x00000000);
+	out_be32(&im->qepio.ioport[2].ppar2, 0x00000000);
+
+	/* PORTD configuration */
+	out_be32(&im->qepio.ioport[3].pdat, 0x1000E000);
+	out_be32(&im->qepio.ioport[3].podr, 0x0000E000);
+	out_be32(&im->qepio.ioport[3].dir1, 0xFD020000);
+	out_be32(&im->qepio.ioport[3].dir2, 0x54055000);
+	out_be32(&im->qepio.ioport[3].ppar1, 0x54030000);
+	out_be32(&im->qepio.ioport[3].ppar2, 0x00000000);
+}
+
+int board_early_init_r(void)
+{
+	immap_t __iomem *im = (immap_t *)CONFIG_SYS_IMMR;
+	fsl_lbc_t *lbus = &im->im_lbc;
+
+	upmconfig(UPMA, upma_table, ARRAY_SIZE(upma_table));
+
+	out_be32(&lbus->mamr, 0x00044440);
+
+	/* configure LBCR register */
+	out_be32(&lbus->lbcr, 0x00000500);
+	sync();
+
+	if (in_8(ADDR_FPGA_REG_ETAT) & R_ETAT_PRES_BASE) {
+		int i;
+
+		/* Initialize signal PROG_FPGA_FIRMWARE */
+		setbits_be32(&im->qepio.ioport[0].pdat, 0x00008000);
+		setbits_be32(&im->qepio.ioport[0].dir2, 0x60000002);
+		setbits_be32(&im->qepio.ioport[0].podr, 0x00008000);
+
+		mdelay(1);
+
+		/* Now read CPDATA[31] to check if FPGA is loaded */
+		if (!in_be32(&im->qepio.ioport[0].pdat) & 0x00000001) {
+			printf("Reloading FPGA firmware.\n");
+
+			clrbits_be32(&im->qepio.ioport[0].pdat, 0x00008000);
+			udelay(1);
+			setbits_be32(&im->qepio.ioport[0].pdat, 0x00008000);
+
+			/* Wait 200 msec and check DONE_FPGA_FIRMWARE */
+			mdelay(200);
+			if (!(in_be32(&im->qepio.ioport[0].pdat) & 0x00000001)) {
+				for (;;) {
+					printf("error loading firmware.\n");
+					mdelay(500);
+				}
+			}
+
+			/* Send a reset signal and wait for 20 msec */
+			out_8(ADDR_FPGA_RESET_G, in_8(ADDR_FPGA_RESET_G) | RESET_G_OK);
+			mdelay(20);
+			out_8(ADDR_FPGA_RESET_G, in_8(ADDR_FPGA_RESET_G) & ~RESET_G_OK);
+		}
+
+		/* Wait 300 msec and check the reset state */
+		mdelay(300);
+		for (i = 0; !(in_8(ADDR_FPGA_REG_ETAT) & RESET_G_OK); i++) {
+			for (;;) {
+				printf("Could not reset FPGA.\n");
+				mdelay(500);
+			}
+		}
+
+		iop_setup_common();
+
+		/* clocks configuration */
+		out_be32(&qe_immr->qmx.cmxsi1cr_l, 0x00040004);
+		out_be32(&qe_immr->qmx.cmxsi1syr, 0x00000000);
+	} else {
+		iop_setup_cmpcpro();
+	}
+
+	return 0;
+}
+
+int dram_init(int board_type)
+{
+	immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	out_be32(&im->sysconf.ddrlaw[0].bar, CFG_SYS_DDR_SDRAM_BASE & LAWBAR_BAR);
+	out_be32(&im->sysconf.ddrlaw[0].ar, LAWAR_EN | ((ilog2(SZ_512M) - 1) & LAWAR_SIZE));
+
+	out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_CLK_CNTL);
+	out_be32(&im->ddr.csbnds[0].csbnds, CFG_SYS_DDR_CS0_BNDS);
+	out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG);
+
+	out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);
+	out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG);
+	out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2);
+	out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL);
+	udelay(200);
+
+	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+
+	gd->ram_size = SZ_512M;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: ");
+
+	/* Is a motherboard present ? */
+	if (in_8(ADDR_FPGA_REG_ETAT) & R_ETAT_PRES_BASE)
+		return checkboard_common();
+
+	printf("CMPCPRO (CS GROUP)\n");
+
+	return 0;
+}
+
+/* Reads MAC addresses from SPI EEPROM */
+static int setup_mac(void)
+{
+	uchar din[MAX_SPI_BYTES];
+	int ret;
+	unsigned long ident = 0x08005120;
+
+	ret = read_eeprom(din, sizeof(din));
+	if (ret)
+		return ret;
+
+	if (memcmp(din + EE_OFF_MAC1, &ident, sizeof(ident)) == 0) {
+		eth_env_set_enetaddr("ethaddr", din + EE_OFF_MAC1);
+		eth_env_set_enetaddr("eth3addr", din + EE_OFF_MAC1);
+	}
+
+	if (memcmp(din + EE_OFF_MAC2, &ident, sizeof(ident)) == 0)
+		eth_env_set_enetaddr("eth1addr", din + EE_OFF_MAC2);
+
+	if (memcmp(din + EE_OFF_MAC3, &ident, sizeof(ident)) == 0)
+		eth_env_set_enetaddr("eth2addr", din + EE_OFF_MAC3);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	/* we do not modify environment variable area if CRC is false */
+	/* Verify if mother board is present */
+	if (in_8(ADDR_FPGA_REG_ETAT) & R_ETAT_PRES_BASE) {
+		misc_init_r_common();
+	} else {
+		env_set("config", CFG_BOARD_CMPCXXX);
+		env_set("hostname", CFG_BOARD_CMPCXXX);
+	}
+
+	if (setup_mac())
+		printf("Error retrieving mac addresses\n");
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	/* MIAE only */
+	if (!(in_8(ADDR_FPGA_REG_ETAT) & R_ETAT_PRES_BASE))
+		return 0;
+
+	return ft_board_setup_common(blob);
+}
+
+void ft_board_setup_phy3(void)
+{
+	/* switch to phy3 with gpio, we'll only use phy3 */
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+	setbits_be32(&immr->qepio.ioport[2].pdat, 0x00000400);
+}
+
+#define ADDR_FPGA_R_BASE		((unsigned char  __iomem *)CONFIG_FPGA_BASE)
+#define ADDR_FPGA_R_ALARMES_IN		((unsigned char  __iomem *)CONFIG_FPGA_BASE + 0x31)
+#define ADDR_FPGA_R_FAV			((unsigned char  __iomem *)CONFIG_FPGA_BASE + 0x44)
+
diff --git a/board/cssi/cmpcpro/cmpcpro.env b/board/cssi/cmpcpro/cmpcpro.env
new file mode 100644
index 0000000..7394b83
--- /dev/null
+++ b/board/cssi/cmpcpro/cmpcpro.env
@@ -0,0 +1,8 @@
+loadaddr=0x1a00000
+filename=cmpcpro.itb
+netdev=eth0
+console_args=console=ttyS0,115200N8
+loadkernel=ubi part nand0;ubifsmount ubi0; ubifsload ${loadaddr} /boot/${filename}; ubifsumount; ubi detach
+flashboot=mw.w 90000040 0x000E 1; setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; run loadkernel; bootm $loadaddr#$config
+tftpboot=mw.w 90000040 0x000E 1; setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; tftp ${loadaddr} ${filename}; bootm $loadaddr#$config
+update=echo 'Updating ubi image'; mw.w 90000040 0x000E 1; if tftp $loadaddr $ubifile; then nand erase.chip; nand write $loadaddr 0x00 $filesize; fi;
diff --git a/board/cssi/cmpcpro/nand.c b/board/cssi/cmpcpro/nand.c
new file mode 100644
index 0000000..d8b4197
--- /dev/null
+++ b/board/cssi/cmpcpro/nand.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010-2023 CS GROUP France
+ * Florent TRINH THAI (florent.trinh-thai@csgroup.eu)
+ * Stephane FRANJOU (stephane.franjou@csgroup.eu)
+ */
+
+#include <config.h>
+#include <nand.h>
+#include <linux/bitops.h>
+#include <linux/mtd/rawnand.h>
+#include <asm/io.h>
+
+#define BIT_CLE		BIT(6)
+#define BIT_ALE		BIT(5)
+
+static u32 nand_mask(unsigned int ctrl)
+{
+	return ((ctrl & NAND_CLE) ? BIT_CLE : 0) |
+	       ((ctrl & NAND_ALE) ? BIT_ALE : 0);
+}
+
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
+{
+	immap_t __iomem *immr = (immap_t *)CONFIG_SYS_IMMR;
+	struct nand_chip *chip = mtd_to_nand(mtdinfo);
+
+	if (ctrl & NAND_CTRL_CHANGE)
+		clrsetbits_be32(&immr->qepio.ioport[2].pdat,
+				BIT_CLE | BIT_ALE, nand_mask(ctrl));
+
+	if (cmd != NAND_CMD_NONE)
+		out_8(chip->IO_ADDR_W, cmd);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->chip_delay	= 60;
+	nand->ecc.mode		= NAND_ECC_SOFT;
+	nand->cmd_ctrl		= nand_hwcontrol;
+
+	return 0;
+}
diff --git a/board/cssi/common/common.c b/board/cssi/common/common.c
new file mode 100644
index 0000000..7ecf772
--- /dev/null
+++ b/board/cssi/common/common.c
@@ -0,0 +1,219 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010-2020 CS Group
+ * Charles Frey <charles.frey@c-s.fr>
+ * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
+ * Christophe Leroy <christophe.leroy@c-s.fr>
+ *
+ * Common specific routines for the CS Group boards
+ */
+
+#include <dm.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <hang.h>
+#include <spi.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+
+#include "common.h"
+
+#define ADDR_FPGA_R_BASE		((unsigned char  __iomem *)CONFIG_FPGA_BASE)
+
+#define FPGA_R_ACQ_AL_FAV	0x04
+
+#define TYPE_MCR			0x22
+#define TYPE_MIAE			0x23
+
+#define FAR_CASRSA     2
+#define FAR_VGOIP      4
+#define FAV_CLA        7
+#define FAV_SRSA       8
+
+#define SPI_EEPROM_READ	0x03
+
+static int fdt_set_node_and_value(void *blob, char *node, const char *prop,
+				  void *var, int size)
+{
+	int ret, off;
+
+	off = fdt_path_offset(blob, node);
+
+	if (off < 0) {
+		printf("Cannot find %s node err:%s\n", node, fdt_strerror(off));
+
+		return off;
+	}
+
+	ret = fdt_setprop(blob, off, prop, var, size);
+
+	if (ret < 0)
+		printf("Cannot set %s/%s prop err: %s\n", node, prop, fdt_strerror(ret));
+
+	return ret;
+}
+
+/* Checks front/rear id and remove unneeded nodes from the blob */
+static void ft_cleanup(void *blob, unsigned long id, const char *prop, const char *compatible)
+{
+	int off;
+
+	off = fdt_node_offset_by_compatible(blob, -1, compatible);
+
+	while (off != -FDT_ERR_NOTFOUND) {
+		const struct fdt_property *ids;
+		int nb_ids, idx;
+		int tmp = -1;
+
+		ids = fdt_get_property(blob, off, prop, &nb_ids);
+
+		for (idx = 0; idx < nb_ids; idx += 4) {
+			if (*((uint32_t *)&ids->data[idx]) == id)
+				break;
+		}
+
+		if (idx >= nb_ids)
+			fdt_del_node(blob, off);
+		else
+			tmp = off;
+
+		off = fdt_node_offset_by_compatible(blob, tmp, compatible);
+	}
+
+	fdt_set_node_and_value(blob, "/", prop, &id, sizeof(uint32_t));
+}
+
+int read_eeprom(u8 *din, int len)
+{
+	struct udevice *eeprom;
+	struct spi_slave *slave;
+	uchar dout[3] = {SPI_EEPROM_READ, 0, 0};
+	int ret;
+
+	ret = uclass_get_device(UCLASS_SPI, 0, &eeprom);
+	if (ret)
+		return ret;
+
+	ret = _spi_get_bus_and_cs(0, 0, 1000000, 0, "spi_generic_drv",
+				  "generic_0:0", &eeprom, &slave);
+	if (ret)
+		return ret;
+
+	ret = spi_claim_bus(slave);
+
+	ret = spi_xfer(slave, sizeof(dout) << 3, dout, NULL, SPI_XFER_BEGIN);
+	if (ret)
+		return ret;
+
+	ret = spi_xfer(slave, len << 3, NULL, din, SPI_XFER_END);
+	if (ret)
+		return ret;
+
+	spi_release_bus(slave);
+
+	return 0;
+}
+
+int ft_board_setup_common(void *blob)
+{
+	u8 far_id, fav_id;
+
+	if (in_8(ADDR_FPGA_R_BASE) != TYPE_MIAE)
+		return 0;
+
+	far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5;
+	ft_cleanup(blob, far_id, "far-id", "cs,mia-far");
+
+	fav_id = in_8(ADDR_FPGA_R_BASE + 0x44) >> 5;
+
+	if (far_id == FAR_CASRSA && fav_id == FAV_CLA)
+		fav_id = FAV_SRSA;
+
+	ft_cleanup(blob, fav_id, "fav-id", "cs,mia-fav");
+
+	if (far_id == FAR_CASRSA)
+		ft_board_setup_phy3();
+
+	return 0;
+}
+
+int checkboard_common(void)
+{
+	switch (in_8(ADDR_FPGA_R_BASE)) {
+		int far_id;
+	case TYPE_MCR:
+		printf("MCR3000_2G (CS GROUP)\n");
+		break;
+	case TYPE_MIAE:
+		far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5;
+
+		if (far_id == FAR_VGOIP)
+			printf("VGoIP (CS GROUP)\n");
+		else
+			printf("MIAE (CS GROUP)\n");
+
+		break;
+	default:
+		printf("Unknown\n");
+		for (;;)
+			;
+		break;
+	}
+	return 0;
+}
+
+void misc_init_r_common(void)
+{
+	u8 tmp, far_id;
+	int count = 3;
+
+	switch (in_8(ADDR_FPGA_R_BASE)) {
+	case TYPE_MCR:
+		/* if at boot alarm button is pressed, delay boot */
+		if ((in_8(ADDR_FPGA_R_BASE + 0x31) & FPGA_R_ACQ_AL_FAV) == 0)
+			env_set("bootdelay", "60");
+
+		env_set("config", CFG_BOARD_MCR3000_2G);
+		env_set("hostname", CFG_BOARD_MCR3000_2G);
+		break;
+
+	case TYPE_MIAE:
+		do {
+			tmp = in_8(ADDR_FPGA_R_BASE + 0x41);
+			count--;
+			mdelay(10); /* 10msec wait */
+		} while (count && tmp != in_8(ADDR_FPGA_R_BASE + 0x41));
+
+		if (!count) {
+			printf("Cannot read the reset factory switch position\n");
+			hang();
+		}
+
+		if (tmp & 0x1)
+			env_set_default("Factory settings switch ON", 0);
+
+		env_set("config", CFG_BOARD_MIAE);
+		far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5;
+
+		if (far_id == FAR_VGOIP)
+			env_set("hostname", CFG_BOARD_VGOIP);
+		else
+			env_set("hostname", CFG_BOARD_MIAE);
+		break;
+
+	default:
+		env_set("config", CFG_BOARD_CMPCXXX);
+		env_set("hostname", CFG_BOARD_CMPCXXX);
+		break;
+	}
+}
+
+void iop_setup_common(void)
+{
+	u8 type = in_8(ADDR_FPGA_R_BASE);
+
+	if (type == TYPE_MCR)
+		iop_setup_mcr();
+	else if (type == TYPE_MIAE)
+		iop_setup_miae();
+}
diff --git a/board/cssi/common/common.h b/board/cssi/common/common.h
new file mode 100644
index 0000000..c5ecb03
--- /dev/null
+++ b/board/cssi/common/common.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _BOARD_CSSI_COMMON_H
+#define _BOARD_CSSI_COMMON_H
+
+int read_eeprom(u8 *din, int len);
+int ft_board_setup_common(void *blob);
+void ft_board_setup_phy3(void);
+int checkboard_common(void);
+void misc_init_r_common(void);
+void iop_setup_common(void);
+void iop_setup_mcr(void);
+void iop_setup_miae(void);
+
+#endif /* _BOARD_CSSI_COMMON_H */
diff --git a/board/cssi/mcr3000/mcr3000.c b/board/cssi/mcr3000/mcr3000.c
index 7b3ab12..3514f67 100644
--- a/board/cssi/mcr3000/mcr3000.c
+++ b/board/cssi/mcr3000/mcr3000.c
@@ -138,17 +138,3 @@
 
 	return 0;
 }
-
-int board_early_init_r(void)
-{
-	struct udevice *watchdog_dev = NULL;
-
-	if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
-		puts("Cannot find watchdog!\n");
-	} else {
-		puts("Enabling watchdog.\n");
-		wdt_start(watchdog_dev, 0xffff, 0);
-	}
-
-	return 0;
-}
diff --git a/board/emulation/common/qemu_dfu.c b/board/emulation/common/qemu_dfu.c
index 332d659..7e7d84f 100644
--- a/board/emulation/common/qemu_dfu.c
+++ b/board/emulation/common/qemu_dfu.c
@@ -48,7 +48,7 @@
 	    env_get("dfu_alt_info"))
 		return;
 
-	memset(buf, 0, sizeof(buf));
+	memset(buf, 0, DFU_ALT_BUF_LEN);
 
 	/*
 	 * Currently dfu_alt_info is needed on Qemu ARM64 for
diff --git a/board/mntre/imx8mq_reform2/Kconfig b/board/mntre/imx8mq_reform2/Kconfig
new file mode 100644
index 0000000..f9260cb
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX8MQ_REFORM2
+
+config SYS_BOARD
+	default "imx8mq_reform2"
+
+config SYS_VENDOR
+	default "mntre"
+
+config SYS_CONFIG_NAME
+	default "imx8mq_reform2"
+
+config IMX_CONFIG
+	default "arch/arm/mach-imx/imx8m/imximage.cfg"
+
+endif
diff --git a/board/mntre/imx8mq_reform2/MAINTAINERS b/board/mntre/imx8mq_reform2/MAINTAINERS
new file mode 100644
index 0000000..946f287
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/MAINTAINERS
@@ -0,0 +1,7 @@
+REFORM2 IMX8MQ BOARD
+M:	Lukas F. Hartmann <lukas@mntre.com>
+M:	Patrick Wildt <patrick@blueri.se>
+S:	Maintained
+F:	board/mntre/imx8mq_reform2/
+F:	include/configs/imx8mq_reform2.h
+F:	configs/imx8mq_reform2_defconfig
diff --git a/board/mntre/imx8mq_reform2/Makefile b/board/mntre/imx8mq_reform2/Makefile
new file mode 100644
index 0000000..2efd56b
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mq_reform2.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/mntre/imx8mq_reform2/imx8mq_reform2.c b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
new file mode 100644
index 0000000..be5c506
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Copyright (C) 2018, Boundary Devices <info@boundarydevices.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+	set_wdog_reset(wdog);
+
+	return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+
+#define PHY_RESET	IMX_GPIO_NR(1, 9)
+#define PHY_RX_CTL	IMX_GPIO_NR(1, 24)
+#define PHY_RXC		IMX_GPIO_NR(1, 25)
+#define PHY_RD0		IMX_GPIO_NR(1, 26)
+#define PHY_RD1		IMX_GPIO_NR(1, 27)
+#define PHY_RD2		IMX_GPIO_NR(1, 28)
+#define PHY_RD3		IMX_GPIO_NR(1, 29)
+
+#define STRAP_AR8035	(0x28) // 0010 1000
+
+static const iomux_v3_cfg_t enet_ar8035_gpio_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 | MUX_PAD_CTRL(0xd1),
+	IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 | MUX_PAD_CTRL(0x91),
+	/* 1.8V(1)/1.5V select(0) */
+	IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 | MUX_PAD_CTRL(0xd1),
+};
+
+static const iomux_v3_cfg_t enet_ar8035_pads[] = {
+	IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(0x91),
+};
+
+static void setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Pull PHY into reset */
+	gpio_request(PHY_RESET, "fec_rst");
+	gpio_direction_output(PHY_RESET, 0);
+
+	/* Configure ethernet pins value as GPIOs */
+	gpio_request(PHY_RD0, "fec_rd0");
+	gpio_direction_output(PHY_RD0, 0);
+	gpio_request(PHY_RD1, "fec_rd1");
+	gpio_direction_output(PHY_RD1, 0);
+	gpio_request(PHY_RD2, "fec_rd2");
+	gpio_direction_output(PHY_RD2, 0);
+	gpio_request(PHY_RD3, "fec_rd3");
+	gpio_direction_output(PHY_RD3, 1);
+	gpio_request(PHY_RX_CTL, "fec_rx_ctl");
+	gpio_direction_output(PHY_RX_CTL, 0);
+	gpio_request(PHY_RXC, "fec_rxc");
+	gpio_direction_output(PHY_RXC, 1);
+
+	/* Set ethernet pins to GPIO to bootstrap PHY */
+	imx_iomux_v3_setup_multiple_pads(enet_ar8035_gpio_pads,
+	    ARRAY_SIZE(enet_ar8035_gpio_pads));
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
+	/* Enable RGMII TX clk output */
+	setbits_le32(&gpr->gpr[1], BIT(22));
+	set_clk_enet(ENET_125MHZ);
+
+	/* 1 ms minimum reset pulse for ar8035 */
+	mdelay(1);
+
+	/* Release PHY from reset */
+	gpio_set_value(PHY_RESET, 1);
+
+	/* strap hold time for AR8035, 5 fails, 6 works, so 12 should be safe */
+	udelay(12);
+
+	/* Change ethernet pins back to normal function */
+	imx_iomux_v3_setup_multiple_pads(enet_ar8035_pads,
+	    ARRAY_SIZE(enet_ar8035_pads));
+}
+#endif
+
+#define USB1_HUB_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define USB1_HUB_RESET		IMX_GPIO_NR(1, 14)
+
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_pad(IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 |
+	    MUX_PAD_CTRL(USB1_HUB_PAD_CTRL));
+	gpio_request(USB1_HUB_RESET, "usb1_rst");
+	gpio_direction_output(USB1_HUB_RESET, 0);
+	mdelay(10);
+	gpio_set_value(USB1_HUB_RESET, 1);
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	setup_usb();
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
+	init_usb_clk();
+#endif
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "Reform2");
+	env_set("board_rev", "iMX8MQ");
+#endif
+
+	return 0;
+}
diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing.c b/board/mntre/imx8mq_reform2/lpddr4_timing.c
new file mode 100644
index 0000000..e5303db
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/lpddr4_timing.c
@@ -0,0 +1,1014 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
+ */
+#include "lpddr4_timing_ch2.h"
+
+static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ DDRC_DBG1(0), 1 },
+	/* selfref_en=1, SDRAM enter self-refresh state */
+	{ DDRC_PWRCTL(0), 1 },
+	{ DDRC_MSTR(0), 0xa0080020 | (CH2_LPDDR4_CS << 24) },
+	{ DDRC_MSTR2(0), 0 },
+	{ DDRC_DERATEEN(0), 0x0203 },
+	{ DDRC_DERATEINT(0), 0x0003e800 },
+	{ DDRC_RFSHTMG(0), 0x006100e0 },
+	{ DDRC_INIT0(0), 0xc003061c },
+	{ DDRC_INIT1(0), 0x009e0000 },
+	{ DDRC_INIT3(0), 0x00d4002d },
+	{ DDRC_INIT4(0), CH2_VAL_INIT4 },
+	{ DDRC_INIT6(0), 0x0066004a },
+	{ DDRC_INIT7(0), 0x0016004a },
+	{ DDRC_DRAMTMG0(0), 0x1a201b22 },
+	{ DDRC_DRAMTMG1(0), 0x00060633 },
+	{ DDRC_DRAMTMG3(0), 0x00c0c000 },
+	{ DDRC_DRAMTMG4(0), 0x0f04080f },
+	{ DDRC_DRAMTMG5(0), 0x02040c0c },
+	{ DDRC_DRAMTMG6(0), 0x01010007 },
+	{ DDRC_DRAMTMG7(0), 0x0401 },
+	{ DDRC_DRAMTMG12(0), 0x00020600 },
+	{ DDRC_DRAMTMG13(0), 0x0c100002 },
+	{ DDRC_DRAMTMG14(0), 0xe6 },
+	{ DDRC_DRAMTMG17(0), 0x00a00050 },
+	{ DDRC_ZQCTL0(0), 0xc3200018 },
+	{ DDRC_ZQCTL1(0), 0x028061a8 },
+	{ DDRC_ZQCTL2(0), 0 },
+	{ DDRC_DFITMG0(0), 0x0497820a },
+	{ DDRC_DFITMG1(0), 0x00080303 },
+	{ DDRC_DFIUPD0(0), 0xe0400018 },
+	{ DDRC_DFIUPD1(0), 0x00df00e4 },
+	{ DDRC_DFIUPD2(0), 0x80000000 },
+	{ DDRC_DFIMISC(0), 0x11 },
+	{ DDRC_DFITMG2(0), 0x170a },
+	{ DDRC_DBICTL(0), 1 },
+	{ DDRC_DFIPHYMSTR(0), 1 },
+	{ DDRC_RANKCTL(0), 0x0639 },
+	{ DDRC_DRAMTMG2(0), 0x070e1617 },
+
+	/* address mapping */
+	{ DDRC_ADDRMAP0(0), CH2_VAL_DDRC_ADDRMAP0 },
+	{ DDRC_ADDRMAP3(0), 0 },
+	/* addrmap_col_b10 and addrmap_col_b11 set to de-activated (5-bit width) */
+	{ DDRC_ADDRMAP4(0), 0x1f1f },
+	/* bank interleave */
+	/* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
+	{ DDRC_ADDRMAP1(0), 0x00080808 },
+	/* addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 */
+	{ DDRC_ADDRMAP5(0), 0x07070707 },
+	/* addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 */
+	{ DDRC_ADDRMAP6(0), CH2_VAL_DDRC_ADDRMAP6 },
+	{ DDRC_ADDRMAP7(0), 0x0f0f },
+	{ DDRC_FREQ1_DERATEEN(0), 1 },
+	{ DDRC_FREQ1_DERATEINT(0), 0xd0c0 },
+	{ DDRC_FREQ1_RFSHCTL0(0), 0x0020d040 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0x0014002f },
+	{ DDRC_FREQ1_INIT3(0), 0x00940009 },
+	{ DDRC_FREQ1_INIT4(0), CH2_VAL_INIT4 },
+	{ DDRC_FREQ1_INIT6(0), 0x0066004a },
+	{ DDRC_FREQ1_INIT7(0), 0x0016004a },
+	{ DDRC_FREQ1_DRAMTMG0(0), 0x0b070508 },
+	{ DDRC_FREQ1_DRAMTMG1(0), 0x0003040b },
+	{ DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
+	{ DDRC_FREQ1_DRAMTMG3(0), 0x00505000 },
+	{ DDRC_FREQ1_DRAMTMG4(0), 0x04040204 },
+	{ DDRC_FREQ1_DRAMTMG5(0), 0x02030303 },
+	{ DDRC_FREQ1_DRAMTMG6(0), 0x01010004 },
+	{ DDRC_FREQ1_DRAMTMG7(0), 0x0301 },
+	{ DDRC_FREQ1_DRAMTMG12(0), 0x00020300 },
+	{ DDRC_FREQ1_DRAMTMG13(0), 0x0a100002 },
+	{ DDRC_FREQ1_DRAMTMG14(0), 0x31 },
+	{ DDRC_FREQ1_DRAMTMG17(0), 0x00220011 },
+	{ DDRC_FREQ1_ZQCTL0(0), 0xc0a70006 },
+	{ DDRC_FREQ1_DFITMG0(0), 0x03858202 },
+	{ DDRC_FREQ1_DFITMG1(0), 0x00080303 },
+	{ DDRC_FREQ1_DFITMG2(0), 0x0502 },
+	{ DDRC_ODTMAP(0), 0 },
+	{ DDRC_SCHED(0), 0x29001505 },
+	{ DDRC_SCHED1(0), 0x2c },
+	{ DDRC_PERFHPR1(0), 0x5900575b },
+	{ DDRC_PERFLPR1(0), 0x90000096 },
+	{ DDRC_PERFWR1(0), 0x1000012c },
+	{ DDRC_DBG0(0), 0x16 },
+	{ DDRC_DBG1(0), 0 },
+	{ DDRC_DBGCMD(0), 0 },
+	{ DDRC_SWCTL(0), 1 },
+	{ DDRC_POISONCFG(0), 0x11 },
+	{ DDRC_PCCFG(0), 0x0111 },
+	{ DDRC_PCFGR_0(0), 0x10f3 },
+	{ DDRC_PCFGW_0(0), 0x72ff },
+	{ DDRC_PCTRL_0(0), 1 },
+	{ DDRC_PCFGQOS0_0(0), 0x0e00 },
+	{ DDRC_PCFGQOS1_0(0), 0x0062ffff },
+	{ DDRC_PCFGWQOS0_0(0), 0x0e00 },
+	{ DDRC_PCFGWQOS1_0(0), 0xffff },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+	{ 0x100a0, 0 },
+	{ 0x100a1, 1 },
+	{ 0x100a2, 2 },
+	{ 0x100a3, 3 },
+	{ 0x100a4, 4 },
+	{ 0x100a5, 5 },
+	{ 0x100a6, 6 },
+	{ 0x100a7, 7 },
+	{ 0x110a0, 0 },
+	{ 0x110a1, 1 },
+	{ 0x110a2, 2 },
+	{ 0x110a3, 3 },
+	{ 0x110a4, 4 },
+	{ 0x110a5, 5 },
+	{ 0x110a6, 6 },
+	{ 0x110a7, 7 },
+	{ 0x120a0, 0 },
+	{ 0x120a1, 1 },
+	{ 0x120a2, 2 },
+	{ 0x120a3, 3 },
+	{ 0x120a4, 4 },
+	{ 0x120a5, 5 },
+	{ 0x120a6, 6 },
+	{ 0x120a7, 7 },
+	{ 0x130a0, 0 },
+	{ 0x130a1, 1 },
+	{ 0x130a2, 2 },
+	{ 0x130a3, 3 },
+	{ 0x130a4, 4 },
+	{ 0x130a5, 5 },
+	{ 0x130a6, 6 },
+	{ 0x130a7, 7 },
+	{ 0x1005f, 0x01ff },
+	{ 0x1015f, 0x01ff },
+	{ 0x1105f, 0x01ff },
+	{ 0x1115f, 0x01ff },
+	{ 0x1205f, 0x01ff },
+	{ 0x1215f, 0x01ff },
+	{ 0x1305f, 0x01ff },
+	{ 0x1315f, 0x01ff },
+	{ 0x11005f, 0x01ff },
+	{ 0x11015f, 0x01ff },
+	{ 0x11105f, 0x01ff },
+	{ 0x11115f, 0x01ff },
+	{ 0x11205f, 0x01ff },
+	{ 0x11215f, 0x01ff },
+	{ 0x11305f, 0x01ff },
+	{ 0x11315f, 0x01ff },
+	{ 0x0055, 0x01ff },
+	{ 0x1055, 0x01ff },
+	{ 0x2055, 0x01ff },
+	{ 0x3055, 0x01ff },
+	{ 0x4055, 0x01ff },
+	{ 0x5055, 0x01ff },
+	{ 0x6055, 0x01ff },
+	{ 0x7055, 0x01ff },
+	{ 0x8055, 0x01ff },
+	{ 0x9055, 0x01ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 7 },
+	{ 0x2002e, 2 },
+	{ 0x12002e, 1 },
+	{ 0x90204, 0 },
+	{ 0x190204, 0 },
+	{ 0x20024, 0x01ab },
+	{ 0x2003a, 0 },
+	{ 0x120024, 0x01ab },
+	{ 0x2003a, 0 },
+	{ 0x20056, 3 },
+	{ 0x120056, 3 },
+	{ 0x1004d, 0x0e00 },
+	{ 0x1014d, 0x0e00 },
+	{ 0x1104d, 0x0e00 },
+	{ 0x1114d, 0x0e00 },
+	{ 0x1204d, 0x0e00 },
+	{ 0x1214d, 0x0e00 },
+	{ 0x1304d, 0x0e00 },
+	{ 0x1314d, 0x0e00 },
+	{ 0x11004d, 0x0e00 },
+	{ 0x11014d, 0x0e00 },
+	{ 0x11104d, 0x0e00 },
+	{ 0x11114d, 0x0e00 },
+	{ 0x11204d, 0x0e00 },
+	{ 0x11214d, 0x0e00 },
+	{ 0x11304d, 0x0e00 },
+	{ 0x11314d, 0x0e00 },
+	{ 0x10049, 0x0eba },
+	{ 0x10149, 0x0eba },
+	{ 0x11049, 0x0eba },
+	{ 0x11149, 0x0eba },
+	{ 0x12049, 0x0eba },
+	{ 0x12149, 0x0eba },
+	{ 0x13049, 0x0eba },
+	{ 0x13149, 0x0eba },
+	{ 0x110049, 0x0eba },
+	{ 0x110149, 0x0eba },
+	{ 0x111049, 0x0eba },
+	{ 0x111149, 0x0eba },
+	{ 0x112049, 0x0eba },
+	{ 0x112149, 0x0eba },
+	{ 0x113049, 0x0eba },
+	{ 0x113149, 0x0eba },
+	{ 0x0043, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 3 },
+	{ 0x20075, 4 },
+	{ 0x20050, 0 },
+	{ 0x20008, 0x0320 },
+	{ 0x120008, 0xa7 },
+	{ 0x20088, 9 },
+	{ 0x200b2, 0xdc },
+	{ 0x10043, 0x05a1 },
+	{ 0x10143, 0x05a1 },
+	{ 0x11043, 0x05a1 },
+	{ 0x11143, 0x05a1 },
+	{ 0x12043, 0x05a1 },
+	{ 0x12143, 0x05a1 },
+	{ 0x13043, 0x05a1 },
+	{ 0x13143, 0x05a1 },
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x05a1 },
+	{ 0x110143, 0x05a1 },
+	{ 0x111043, 0x05a1 },
+	{ 0x111143, 0x05a1 },
+	{ 0x112043, 0x05a1 },
+	{ 0x112143, 0x05a1 },
+	{ 0x113043, 0x05a1 },
+	{ 0x113143, 0x05a1 },
+	{ 0x200fa, 1 },
+	{ 0x1200fa, 1 },
+	{ 0x20019, 1 },
+	{ 0x120019, 1 },
+	{ 0x200f0, 0 },
+	{ 0x200f1, 0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0 },
+	{ 0x200f6, 0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0 },
+	{ 0x2002d, 0 },
+	{ 0x12002d, 0 },
+	{ 0x200c7, 0x80 },
+	{ 0x1200c7, 0x80 },
+	{ 0x200ca, 0x0106 },
+	{ 0x1200ca, 0x0106 },
+	{ 0x20110, 2 },
+	{ 0x20111, 3 },
+	{ 0x20112, 4 },
+	{ 0x20113, 5 },
+	{ 0x20114, 0 },
+	{ 0x20115, 1 },
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+	{ 0xd0000, 0 },
+	{ 0x54003, 0x0c80 },
+	{ 0x54004, 2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54008, 0x131f },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400b, 2 },
+	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, CH2_LPDDR4_CS },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x084a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x084a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 1 },
+};
+
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+	{ 0xd0000, 0 },
+	{ 0x54002, 1 },
+	{ 0x54003, 0x029c },
+	{ 0x54004, 2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54008, 0x121f },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400b, 2 },
+	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
+	{ 0x54019, 0x0994 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x0994 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, CH2_LPDDR4_CS },
+	{ 0x54032, 0x9400 },
+	{ 0x54033, 0x3109 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x084a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x9400 },
+	{ 0x54039, 0x3109 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x084a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 1 },
+};
+
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0 },
+	{ 0x54003, 0x0c80 },
+	{ 0x54004, 2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54008, 0x61 },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400b, 2 },
+	{ 0x5400d, 0x0100 },
+	{ 0x5400f, 0x0100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, CH2_LPDDR4_CS },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x084a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x084a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param lpddr4_phy_pie[] = {
+	{ 0xd0000, 0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x0400 },
+	{ 0x90002, 0x010e },
+	{ 0x90003, 0 },
+	{ 0x90004, 0 },
+	{ 0x90005, 8 },
+	{ 0x90029, 0x0b },
+	{ 0x9002a, 0x0480 },
+	{ 0x9002b, 0x0109 },
+	{ 0x9002c, 8 },
+	{ 0x9002d, 0x0448 },
+	{ 0x9002e, 0x0139 },
+	{ 0x9002f, 8 },
+	{ 0x90030, 0x0478 },
+	{ 0x90031, 0x0109 },
+	{ 0x90032, 0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x0109 },
+	{ 0x90035, 2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x0139 },
+	{ 0x90038, 0x0f },
+	{ 0x90039, 0x07c0 },
+	{ 0x9003a, 0x0139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x0630 },
+	{ 0x9003d, 0x0159 },
+	{ 0x9003e, 0x014f },
+	{ 0x9003f, 0x0630 },
+	{ 0x90040, 0x0159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x0630 },
+	{ 0x90043, 0x0149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x0630 },
+	{ 0x90046, 0x0179 },
+	{ 0x90047, 8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x0109 },
+	{ 0x9004a, 0 },
+	{ 0x9004b, 0x07c8 },
+	{ 0x9004c, 0x0109 },
+	{ 0x9004d, 0 },
+	{ 0x9004e, 1 },
+	{ 0x9004f, 8 },
+	{ 0x90050, 0 },
+	{ 0x90051, 0x045a },
+	{ 0x90052, 9 },
+	{ 0x90053, 0 },
+	{ 0x90054, 0x0448 },
+	{ 0x90055, 0x0109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x0630 },
+	{ 0x90058, 0x0179 },
+	{ 0x90059, 1 },
+	{ 0x9005a, 0x0618 },
+	{ 0x9005b, 0x0109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x0630 },
+	{ 0x9005e, 0x0149 },
+	{ 0x9005f, 8 },
+	{ 0x90060, 4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x0630 },
+	{ 0x90064, 0x0149 },
+	{ 0x90065, 0 },
+	{ 0x90066, 4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x0630 },
+	{ 0x9006a, 0x0149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0 },
+	{ 0x9006f, 4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x0549 },
+	{ 0x90072, 0x0630 },
+	{ 0x90073, 0x0159 },
+	{ 0x90074, 0x0d49 },
+	{ 0x90075, 0x0630 },
+	{ 0x90076, 0x0159 },
+	{ 0x90077, 0x094a },
+	{ 0x90078, 0x0630 },
+	{ 0x90079, 0x0159 },
+	{ 0x9007a, 0x0441 },
+	{ 0x9007b, 0x0630 },
+	{ 0x9007c, 0x0149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x0630 },
+	{ 0x9007f, 0x0149 },
+	{ 0x90080, 1 },
+	{ 0x90081, 0x0630 },
+	{ 0x90082, 0x0149 },
+	{ 0x90083, 0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x0109 },
+	{ 0x90086, 0x0a },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x0109 },
+	{ 0x90089, 9 },
+	{ 0x9008a, 0x03c0 },
+	{ 0x9008b, 0x0149 },
+	{ 0x9008c, 9 },
+	{ 0x9008d, 0x03c0 },
+	{ 0x9008e, 0x0159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x0109 },
+	{ 0x90092, 0 },
+	{ 0x90093, 0x03c0 },
+	{ 0x90094, 0x0109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0x0a },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x0109 },
+	{ 0x9009e, 2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x0109 },
+	{ 0x900a1, 5 },
+	{ 0x900a2, 0x07c0 },
+	{ 0x900a3, 0x0109 },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x0109 },
+	{ 0x40000, 0x0811 },
+	{ 0x40020, 0x0880 },
+	{ 0x40040, 0 },
+	{ 0x40060, 0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0 },
+	{ 0x40003, 0x0811 },
+	{ 0x40023, 0x0880 },
+	{ 0x40043, 0 },
+	{ 0x40063, 0 },
+	{ 0x40004, 0x0720 },
+	{ 0x40024, 0x0f },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0 },
+	{ 0x40006, 0x0716 },
+	{ 0x40026, 0x0f },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0 },
+	{ 0x40007, 0x0716 },
+	{ 0x40027, 0x0f },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0 },
+	{ 0x40008, 0x0716 },
+	{ 0x40028, 0x0f },
+	{ 0x40048, 0x0f00 },
+	{ 0x40068, 0 },
+	{ 0x40009, 0x0720 },
+	{ 0x40029, 0x0f },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0 },
+	{ 0x4000a, 0x0e08 },
+	{ 0x4002a, 0x0c15 },
+	{ 0x4004a, 0 },
+	{ 0x4006a, 0 },
+	{ 0x4000b, 0x0623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0 },
+	{ 0x4006b, 0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0 },
+	{ 0x4006c, 0 },
+	{ 0x4000d, 0x0e08 },
+	{ 0x4002d, 0x0c1a },
+	{ 0x4004d, 0 },
+	{ 0x4006d, 0 },
+	{ 0x4000e, 0x0623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0 },
+	{ 0x4006e, 0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0 },
+	{ 0x4006f, 0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0 },
+	{ 0x40070, 0 },
+	{ 0x40011, 0x0708 },
+	{ 0x40031, 5 },
+	{ 0x40051, 0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0 },
+	{ 0x40072, 0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0 },
+	{ 0x40073, 0 },
+	{ 0x40014, 0x0708 },
+	{ 0x40034, 0x0a },
+	{ 0x40054, 0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0 },
+	{ 0x40075, 0 },
+	{ 0x40016, 0x060a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0 },
+	{ 0x40017, 0x061a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0 },
+	{ 0x40018, 0x060a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0 },
+	{ 0x40019, 0x0642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x0880 },
+	{ 0x4005a, 0 },
+	{ 0x4007a, 0 },
+	{ 0x900a7, 0 },
+	{ 0x900a8, 0x0790 },
+	{ 0x900a9, 0x011a },
+	{ 0x900aa, 8 },
+	{ 0x900ab, 0x07aa },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x10 },
+	{ 0x900ae, 0x07b2 },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0 },
+	{ 0x900b1, 0x07c8 },
+	{ 0x900b2, 0x0109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x02a8 },
+	{ 0x900b5, 0x0129 },
+	{ 0x900b6, 8 },
+	{ 0x900b7, 0x0370 },
+	{ 0x900b8, 0x0129 },
+	{ 0x900b9, 0x0a },
+	{ 0x900ba, 0x03c8 },
+	{ 0x900bb, 0x01a9 },
+	{ 0x900bc, 0x0c },
+	{ 0x900bd, 0x0408 },
+	{ 0x900be, 0x0199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x0790 },
+	{ 0x900c1, 0x011a },
+	{ 0x900c2, 8 },
+	{ 0x900c3, 4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0x0e },
+	{ 0x900c6, 0x0408 },
+	{ 0x900c7, 0x0199 },
+	{ 0x900c8, 8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x0108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x0790 },
+	{ 0x900cd, 0x016a },
+	{ 0x900ce, 8 },
+	{ 0x900cf, 0x01d8 },
+	{ 0x900d0, 0x0169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x0168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x0788 },
+	{ 0x900d6, 0x016a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x01e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x0798 },
+	{ 0x900dc, 0x016a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x07a0 },
+	{ 0x900df, 0x016a },
+	{ 0x900e0, 8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x0168 },
+	{ 0x900e3, 8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x0168 },
+	{ 0x900e6, 0x0a },
+	{ 0x900e7, 0x0408 },
+	{ 0x900e8, 0x0169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0 },
+	{ 0x900ed, 0x0408 },
+	{ 0x900ee, 0x0169 },
+	{ 0x900ef, 0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x0168 },
+	{ 0x900f2, 0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x0168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x01e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x0798 },
+	{ 0x900fa, 0x016a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x07a0 },
+	{ 0x900fd, 0x016a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x0790 },
+	{ 0x90100, 0x016a },
+	{ 0x90101, 8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x0168 },
+	{ 0x90104, 8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x0168 },
+	{ 0x90107, 0x0a },
+	{ 0x90108, 0x0408 },
+	{ 0x90109, 0x0169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0 },
+	{ 0x9010e, 0x0408 },
+	{ 0x9010f, 0x0169 },
+	{ 0x90110, 0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x0168 },
+	{ 0x90113, 0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x0168 },
+	{ 0x90116, 0 },
+	{ 0x90117, 0x01d8 },
+	{ 0x90118, 0x0169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x0790 },
+	{ 0x9011b, 0x016a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x07aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0x0a },
+	{ 0x90120, 0 },
+	{ 0x90121, 0x01e9 },
+	{ 0x90122, 8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x0108 },
+	{ 0x90125, 0x0f },
+	{ 0x90126, 0x0408 },
+	{ 0x90127, 0x0169 },
+	{ 0x90128, 0x0c },
+	{ 0x90129, 0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 9 },
+	{ 0x9012c, 0 },
+	{ 0x9012d, 0x01a9 },
+	{ 0x9012e, 0 },
+	{ 0x9012f, 0x0408 },
+	{ 0x90130, 0x0169 },
+	{ 0x90131, 0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x0108 },
+	{ 0x90134, 8 },
+	{ 0x90135, 0x07aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x0108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x0790 },
+	{ 0x9013c, 0x016a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x0168 },
+	{ 0x90143, 0x0f },
+	{ 0x90144, 0x0408 },
+	{ 0x90145, 0x0169 },
+	{ 0x90146, 0x0c },
+	{ 0x90147, 0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0 },
+	{ 0x9014a, 0x0408 },
+	{ 0x9014b, 0x0169 },
+	{ 0x9014c, 0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x0168 },
+	{ 0x9014f, 8 },
+	{ 0x90150, 0x03c8 },
+	{ 0x90151, 0x01a9 },
+	{ 0x90152, 3 },
+	{ 0x90153, 0x0370 },
+	{ 0x90154, 0x0129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x02aa },
+	{ 0x90157, 9 },
+	{ 0x90158, 0 },
+	{ 0x90159, 0x0400 },
+	{ 0x9015a, 0x010e },
+	{ 0x9015b, 8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x0109 },
+	{ 0x9015e, 0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x010c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x010c },
+	{ 0x90164, 8 },
+	{ 0x90165, 0x07c8 },
+	{ 0x90166, 0x0101 },
+	{ 0x90167, 8 },
+	{ 0x90168, 0 },
+	{ 0x90169, 8 },
+	{ 0x9016a, 8 },
+	{ 0x9016b, 0x0448 },
+	{ 0x9016c, 0x0109 },
+	{ 0x9016d, 0x0f },
+	{ 0x9016e, 0x07c0 },
+	{ 0x9016f, 0x0109 },
+	{ 0x90170, 0 },
+	{ 0x90171, 0xe8 },
+	{ 0x90172, 0x0109 },
+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x0630 },
+	{ 0x90175, 0x0109 },
+	{ 0x90176, 8 },
+	{ 0x90177, 0x0618 },
+	{ 0x90178, 0x0109 },
+	{ 0x90179, 8 },
+	{ 0x9017a, 0xe0 },
+	{ 0x9017b, 0x0109 },
+	{ 0x9017c, 0 },
+	{ 0x9017d, 0x07c8 },
+	{ 0x9017e, 0x0109 },
+	{ 0x9017f, 8 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x010c },
+	{ 0x90182, 0 },
+	{ 0x90183, 1 },
+	{ 0x90184, 8 },
+	{ 0x90185, 8 },
+	{ 0x90186, 4 },
+	{ 0x90187, 8 },
+	{ 0x90188, 8 },
+	{ 0x90189, 0x07c8 },
+	{ 0x9018a, 0x0101 },
+	{ 0x90006, 0 },
+	{ 0x90007, 0 },
+	{ 0x90008, 8 },
+	{ 0x90009, 0 },
+	{ 0x9000a, 0 },
+	{ 0x9000b, 0 },
+	{ 0xd00e7, 0x0400 },
+	{ 0x90017, 0 },
+	{ 0x9001f, 0x2a },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0 },
+	{ 0x400d1, 0x0101 },
+	{ 0x400d2, 0x0105 },
+	{ 0x400d3, 0x0107 },
+	{ 0x400d4, 0x010f },
+	{ 0x400d5, 0x0202 },
+	{ 0x400d6, 0x020a },
+	{ 0x400d7, 0x020b },
+	{ 0x2003a, 2 },
+	{ 0x2000b, 0x64 },
+	{ 0x2000c, 0xc8 },
+	{ 0x2000d, 0x07d0 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x14 },
+	{ 0x12000c, 0x29 },
+	{ 0x12000d, 0x01a1 },
+	{ 0x12000e, 0x10 },
+	{ 0x9000c, 0 },
+	{ 0x9000d, 0x0173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x400fd, 0x0f },
+	{ 0x10011, 1 },
+	{ 0x10012, 1 },
+	{ 0x10013, 0x0180 },
+	{ 0x10018, 1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 1 },
+	{ 0x101b4, 1 },
+	{ 0x102b4, 1 },
+	{ 0x103b4, 1 },
+	{ 0x104b4, 1 },
+	{ 0x105b4, 1 },
+	{ 0x106b4, 1 },
+	{ 0x107b4, 1 },
+	{ 0x108b4, 1 },
+	{ 0x11011, 1 },
+	{ 0x11012, 1 },
+	{ 0x11013, 0x0180 },
+	{ 0x11018, 1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 1 },
+	{ 0x111b4, 1 },
+	{ 0x112b4, 1 },
+	{ 0x113b4, 1 },
+	{ 0x114b4, 1 },
+	{ 0x115b4, 1 },
+	{ 0x116b4, 1 },
+	{ 0x117b4, 1 },
+	{ 0x118b4, 1 },
+	{ 0x12011, 1 },
+	{ 0x12012, 1 },
+	{ 0x12013, 0x0180 },
+	{ 0x12018, 1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 1 },
+	{ 0x121b4, 1 },
+	{ 0x122b4, 1 },
+	{ 0x123b4, 1 },
+	{ 0x124b4, 1 },
+	{ 0x125b4, 1 },
+	{ 0x126b4, 1 },
+	{ 0x127b4, 1 },
+	{ 0x128b4, 1 },
+	{ 0x13011, 1 },
+	{ 0x13012, 1 },
+	{ 0x13013, 0x0180 },
+	{ 0x13018, 1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 1 },
+	{ 0x131b4, 1 },
+	{ 0x132b4, 1 },
+	{ 0x133b4, 1 },
+	{ 0x134b4, 1 },
+	{ 0x135b4, 1 },
+	{ 0x136b4, 1 },
+	{ 0x137b4, 1 },
+	{ 0x138b4, 1 },
+	{ 0x2003a, 2 },
+	{ 0xc0080, 2 },
+	{ 0xd0000, 1 }
+};
+
+static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_ch2 = {
+	.ddrc_cfg = lpddr4_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+	.ddrphy_cfg = lpddr4_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+	.fsp_msg = lpddr4_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+	.ddrphy_pie = lpddr4_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+	.fsp_table = { 3200, 667, },
+};
diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
new file mode 100644
index 0000000..a55086b
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <config.h>
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+/* MNT Reform2 */
+#define CFG_DDR_MB 4096
+#define CFG_DDR_RANK_BITS 1
+#define CFG_DDR_CHANNEL_CNT 2
+
+#ifdef WR_POST_EXT_3200
+#define CH2_VAL_INIT4	((LPDDR4_MR3 << 16) | 0x00020008)
+#else
+#define CH2_VAL_INIT4	((LPDDR4_MR3 << 16) | 8)
+#endif
+
+#if CFG_DDR_MB == 1024
+	/* Address map is from MSB 28: r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R0	0x0000001F
+#define CH2_VAL_DDRC_ADDRMAP6_R0	0x0F070707
+
+#elif CFG_DDR_MB == 2048
+	/* Address map is from MSB 28: r15, r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R0	0x0000001F
+#define CH2_VAL_DDRC_ADDRMAP6_R0	0x07070707
+	/* Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000016
+#define CH2_VAL_DDRC_ADDRMAP6_R1	0x0F070707
+
+#elif CFG_DDR_MB == 3072
+	/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000015
+#define CH2_VAL_DDRC_ADDRMAP6_R1	0x48080707
+
+#elif CFG_DDR_MB == 4096
+	/* Address map is from MSB 29: cs, r15, r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000017
+#define CH2_VAL_DDRC_ADDRMAP6_R1	0x07070707
+#else
+#error unsupported memory size
+#endif
+
+#define LPDDR4_CS_R0	0x1	/* 0 rank bits, 1 chip select */
+#define LPDDR4_CS_R1	0x3	/* 1 rank bit, 2 chip selects */
+
+#if (CFG_DDR_RANK_BITS == 0) || !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#ifdef CH2_VAL_DDRC_ADDRMAP0_R0
+#define CH2_LPDDR4_CS			LPDDR4_CS_R0
+#define CH2_VAL_DDRC_ADDRMAP0		CH2_VAL_DDRC_ADDRMAP0_R0
+#define CH2_VAL_DDRC_ADDRMAP6		CH2_VAL_DDRC_ADDRMAP6_R0
+#else
+#error unsupported memory rank/size
+#endif
+/*
+ * rank0 will succeed, even if really rank 1, so we need
+ * to probe memory if rank0 succeeds
+ */
+#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#define CH2_LPDDR4_CS_NEW		LPDDR4_CS_R1
+#define CH2_VAL_DDRC_ADDRMAP0_NEW	CH2_VAL_DDRC_ADDRMAP0_R1
+#define CH2_VAL_DDRC_ADDRMAP6_NEW	CH2_VAL_DDRC_ADDRMAP6_R1
+#endif
+
+#elif (CFG_DDR_RANK_BITS == 1) || !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
+#ifdef CH2_VAL_DDRC_ADDRMAP0_R1
+#define CH2_LPDDR4_CS			LPDDR4_CS_R1
+#define CH2_VAL_DDRC_ADDRMAP0		CH2_VAL_DDRC_ADDRMAP0_R1
+#define CH2_VAL_DDRC_ADDRMAP6		CH2_VAL_DDRC_ADDRMAP6_R1
+#else
+#error unsupported memory rank/size
+#endif
+
+#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#define CH2_LPDDR4_CS_NEW		LPDDR4_CS_R0
+#define CH2_VAL_DDRC_ADDRMAP0_NEW	CH2_VAL_DDRC_ADDRMAP0_R0
+#define CH2_VAL_DDRC_ADDRMAP6_NEW	CH2_VAL_DDRC_ADDRMAP6_R0
+#endif
+
+#else
+#error unsupported rank bits
+#endif
+
+#if (CFG_DDR_CHANNEL_CNT == 2)
+#if (CFG_DDR_RANK_BITS == 0) && !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
+#error unsupported options
+#endif
+#if (CFG_DDR_RANK_BITS == 1) && !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#error unsupported options
+#endif
+#endif
diff --git a/board/mntre/imx8mq_reform2/spl.c b/board/mntre/imx8mq_reform2/spl.c
new file mode 100644
index 0000000..21fad49
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/spl.c
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern struct dram_timing_info dram_timing_ch2;
+
+static void spl_dram_init(void)
+{
+	ddr_init(&dram_timing_ch2);
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+#define USDHC2_VSEL	IMX_GPIO_NR(1, 8)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		return ret;
+	}
+
+	return 1;
+}
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(0x91),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			init_clk_usdhc(0);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+							 ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+			init_clk_usdhc(1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+							 ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_VSEL, "usdhc2_vsel");
+			gpio_direction_output(USDHC2_VSEL, 0);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#define I2C1_PCA9546_RESET	IMX_GPIO_NR(1, 4)
+#define ARM_DRAM_VSEL		IMX_GPIO_NR(3, 24)
+#define DRAM_1P1_VSEL		IMX_GPIO_NR(2, 11)
+#define SOC_GPU_VPU_VSEL	IMX_GPIO_NR(2, 20)
+
+#define I2C_MUX_ADDR		0x70
+#define I2C_FAN53555_ADDR	0x60
+
+static iomux_v3_cfg_t const power_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46),
+};
+
+int power_init_board(void)
+{
+	uint8_t val;
+
+	imx_iomux_v3_setup_multiple_pads(power_pads,
+					 ARRAY_SIZE(usdhc2_pads));
+
+	/* Release I2C multiplexer reset */
+	gpio_request(I2C1_PCA9546_RESET, "pca9546_reset");
+	gpio_direction_output(I2C1_PCA9546_RESET, 1);
+
+	/* Select VSEL0 on voltage regulators */
+	gpio_request(ARM_DRAM_VSEL, "arm_dram_vsel");
+	gpio_direction_output(ARM_DRAM_VSEL, 0);
+	gpio_request(DRAM_1P1_VSEL, "dram_1p1_vsel");
+	gpio_direction_output(DRAM_1P1_VSEL, 0);
+	gpio_request(SOC_GPU_VPU_VSEL, "soc_gpu_vpu_vsel");
+	gpio_direction_output(SOC_GPU_VPU_VSEL, 0);
+
+	/* Set mux to target ARM/DRAM regulator */
+	i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0);
+	/* .6 + .40 = 1.00 */
+	val = 0x80 + 40;
+	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
+	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
+
+	/* Set mux to target DRAM regulator */
+	i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0);
+	/* .6 + .50 = 1.10 */
+	val = 0x80 + 50;
+	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
+	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
+
+	/* Set mux to target SoC/GPU/VPU regulator */
+	i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0);
+	/*  .6 + .30 = .90 */
+	val = 0x80 + 30;
+	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
+	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
+
+	/* Set mux to target peripherals */
+	i2c_write(I2C_MUX_ADDR, 8, 1, NULL, 0);
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+	init_uart_clk(0);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/board/qualcomm/dragonboard845c/Makefile b/board/qualcomm/dragonboard845c/Makefile
index 0abefda..fe585ad 100644
--- a/board/qualcomm/dragonboard845c/Makefile
+++ b/board/qualcomm/dragonboard845c/Makefile
@@ -3,7 +3,7 @@
 # (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
 #
 # This empty file prevents make error.
-# Board logic defined in board/qualcomm/common/sdm845.c, no custom logic for dragonboard845c so far.
+# Board logic defined in arch/arm/mach-snapdragon/init_sdm845.c, no custom logic for dragonboard845c so far.
 #
 
 obj-y += dragonboard845c.o
diff --git a/board/samsung/starqltechn/Makefile b/board/samsung/starqltechn/Makefile
index c38c0b4..e017c82 100644
--- a/board/samsung/starqltechn/Makefile
+++ b/board/samsung/starqltechn/Makefile
@@ -3,7 +3,7 @@
 # (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
 #
 # This empty file prevents make error.
-# Board logic defined in board/qualcomm/common/sdm845.c, no custom logic for starqltechn so far.
+# Board logic defined in arch/arm/mach-snapdragon/init_sdm845.c, no custom logic for starqltechn so far.
 #
 
 obj-y += starqltechn.o
diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c
index df705b7..2653e10 100644
--- a/board/siemens/iot2050/board.c
+++ b/board/siemens/iot2050/board.c
@@ -21,7 +21,6 @@
 #include <spl.h>
 #include <version.h>
 #include <linux/delay.h>
-#include <asm/arch/sys_proto.h>
 #include <asm/arch/hardware.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
@@ -482,19 +481,10 @@
 
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
-	int ret;
-
-	ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
-	if (ret < 0)
-		ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
-					 "sram@70000000");
-	if (ret)
-		pr_err("%s: fixing up msmc ram failed %d\n", __func__, ret);
-
 	if (board_is_m2())
 		m2_fdt_fixup(blob);
 
-	return ret;
+	return 0;
 }
 #endif
 
diff --git a/board/skyworth/hc2910-2aghd05/Kconfig b/board/skyworth/hc2910-2aghd05/Kconfig
new file mode 100644
index 0000000..f85f1f2
--- /dev/null
+++ b/board/skyworth/hc2910-2aghd05/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_HC2910_2AGHD05
+
+config SYS_BOARD
+	default "hc2910-2aghd05"
+
+config SYS_VENDOR
+	default "skyworth"
+
+config SYS_SOC
+	default "hi3798mv200"
+
+config SYS_CONFIG_NAME
+	default "hc2910-2aghd05"
+
+endif
diff --git a/board/skyworth/hc2910-2aghd05/MAINTAINERS b/board/skyworth/hc2910-2aghd05/MAINTAINERS
new file mode 100644
index 0000000..2c1e750
--- /dev/null
+++ b/board/skyworth/hc2910-2aghd05/MAINTAINERS
@@ -0,0 +1,6 @@
+HC2910 2AGHD05 BOARD
+M: Yang Xiwen <firbidden405@outlook.com>
+S: Maintained
+F: board/skyworth/hc2910-2aghd05
+F: include/configs/hc2910-2aghd05.h
+F: configs/hc2910_2aghd05_defconfig
diff --git a/board/skyworth/hc2910-2aghd05/Makefile b/board/skyworth/hc2910-2aghd05/Makefile
new file mode 100644
index 0000000..193fd15
--- /dev/null
+++ b/board/skyworth/hc2910-2aghd05/Makefile
@@ -0,0 +1 @@
+obj-y	:= hc2910-2aghd05.o
diff --git a/board/skyworth/hc2910-2aghd05/README b/board/skyworth/hc2910-2aghd05/README
new file mode 100644
index 0000000..a838956
--- /dev/null
+++ b/board/skyworth/hc2910-2aghd05/README
@@ -0,0 +1,25 @@
+================================================================================
+			Board Information
+================================================================================
+
+The board features the Hi3798M V200 with an integrated quad-core 64-bit ARM
+Cortex A53 processor.
+SOC  Hisilicon Hi3798CV200
+CPU  Quad-core ARM Cortex-A53 64 bit
+DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
+USB  1x USB 2.0 ports 1x USB 3.0 ports
+CONSOLE  USB-micro port for console support
+ETHERNET  1 GBe Ethernet, 1 MBe Ethernet
+WIFI  802.11n with Bluebooth
+CONNECTORS  One connector for Smart Card One connector for TSI
+
+
+================================================================================
+			BUILD INSTRUCTIONS
+================================================================================
+
+The U-Boot relies on a modified l-loader and TF-A for Hi3798MV200.
+The source for l-loader can be obtained at: [l-loader](https://github.com/185264646/l-loader)
+The mainline port for TF-A is still under development. For now, you can use the TF-A for poplar directly.
+
+For more information, please refer to <board/hisilicon/poplar/README>.
diff --git a/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c b/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c
new file mode 100644
index 0000000..abad5ef
--- /dev/null
+++ b/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board init file for Skyworth HC2910 2AGHD05
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/system.h>
+#include <linux/io.h>
+
+#define HI3798MV200_PERI_CTRL_BASE 0xf8a20000
+#define SDIO0_LDO_OFFSET 0x11c
+
+static int sdio0_set_ldo(void)
+{
+	// SDIO LDO bypassed, 3.3V
+	writel(HI3798MV200_PERI_CTRL_BASE + SDIO0_LDO_OFFSET, 0x60);
+	return 0;
+}
+
+int board_init(void)
+{
+	sdio0_set_ldo();
+	return 0;
+}
diff --git a/board/storopack/smegw01/Kconfig b/board/storopack/smegw01/Kconfig
index d8f2469..390214c 100644
--- a/board/storopack/smegw01/Kconfig
+++ b/board/storopack/smegw01/Kconfig
@@ -12,4 +12,11 @@
 config IMX_CONFIG
 	default "board/storopack/smegw01/imximage.cfg"
 
+config SYS_BOOT_LOCKED
+	bool "Lock boot process to EMMC"
+	default y
+	help
+	  Say N here if you want to boot from eMMC and SD.
+	  Say Y to boot from eMMC.
+
 endif
diff --git a/board/storopack/smegw01/smegw01.c b/board/storopack/smegw01/smegw01.c
index e6bff80..20c0970 100644
--- a/board/storopack/smegw01/smegw01.c
+++ b/board/storopack/smegw01/smegw01.c
@@ -14,9 +14,11 @@
 #include <asm/io.h>
 #include <common.h>
 #include <env.h>
+#include <env_internal.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/setup.h>
 #include <asm/bootm.h>
+#include <mmc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -80,6 +82,7 @@
 int board_late_init(void)
 {
 	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+	unsigned char eth1addr[6];
 
 	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 
@@ -91,5 +94,35 @@
 	 */
 	clrsetbits_le16(&wdog->wcr, 0, 0x10);
 
+	/* Get the second MAC address */
+	imx_get_mac_from_fuse(1, eth1addr);
+	if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
+		eth_env_set_enetaddr("eth1addr", eth1addr);
+
 	return 0;
 }
+
+uint board_mmc_get_env_part(struct mmc *mmc)
+{
+	uint part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
+
+	if (part == 7)
+		part = 0;
+	return part;
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	if (op == ENVOP_SAVE || op == ENVOP_ERASE)
+		return ENVL_MMC;
+
+	switch (prio) {
+	case 0:
+		return ENVL_NOWHERE;
+
+	case 1:
+		return ENVL_MMC;
+	}
+
+	return ENVL_UNKNOWN;
+}
diff --git a/board/storopack/smegw01/smegw01.env b/board/storopack/smegw01/smegw01.env
new file mode 100644
index 0000000..25bc7cd
--- /dev/null
+++ b/board/storopack/smegw01/smegw01.env
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+#ifdef CONFIG_SYS_BOOT_LOCKED
+#define SETUP_BOOT_MENU setup_boot_menu=setenv bootmenu_0 eMMC=run bootcmd
+#else
+#define SETUP_BOOT_MENU setup_boot_menu= \
+			if test "${mmcdev}" = 1; then \
+				setenv emmc_priority 0; \
+				setenv sd_priority 1; \
+			else setenv emmc_priority 1; \
+				setenv sd_priority 0; \
+			fi; \
+			setenv bootmenu_${emmc_priority} eMMC=run boot_emmc; \
+			setenv bootmenu_${sd_priority} SD=run boot_sd;
+#endif
+
+altbootcmd=
+	echo Performing rollback...;
+	if test "${mmcpart_committed}" = 1; then
+		setenv mmcpart 2;
+		setenv mmcpart_committed 2;
+	else
+		setenv mmcpart 1;
+		setenv mmcpart_committed 1;
+	fi;
+	setenv bootcount 0;
+	setenv upgrade_available;
+	setenv ustate 3;
+	saveenv;
+	run bootcmd;
+boot_emmc=setenv mmcdev_wanted 1; run persist_mmcdev; run bootcmd;
+boot_sd=setenv mmcdev_wanted 0; run persist_mmcdev; run bootcmd;
+bootcmd=run finduuid; run distro_bootcmd
+bootdelay=2
+bootlimit=3
+bootm_size=0x10000000
+commit_mmc=
+	if test "${ustate}" = 1 -a "${mmcpart}" != "${mmcpart_committed}"; then
+		setenv mmcpart_committed ${mmcpart};
+		saveenv;
+	fi;
+console=ttymxc0
+fdt_addr=0x83000000
+fdtfile=imx7d-smegw01.dtb
+fit_addr=0x88000000
+image=fitImage
+loadaddr=0x80800000
+loadbootpart=mmc partconf 1 boot_part
+loadimage=load mmc ${mmcdev}:${gpt_partition_entry} ${fit_addr} boot/${image}
+loadpart=gpt setenv mmc ${mmcdev} rootfs-${mmcpart_committed}
+mmcargs=
+	setenv bootargs console=${console},${baudrate} root=/dev/mmcblk${mmcdev}p${gpt_partition_entry} rootwait rw SM_ROOT_DEV=${mmcdev} SM_ROOT_PART=${gpt_partition_entry} SM_BOOT_PART=${boot_part}
+mmcboot=
+	echo Booting...;
+	echo mmcdev: ${mmcdev};
+	run commit_mmc;
+	echo mmcpart: ${mmcpart_committed};
+	run loadpart;
+	echo gptpart: ${gpt_partition_entry};
+	run loadbootpart;
+	if run loadimage; then
+		;
+	else
+		run altbootcmd;
+	fi;
+	run mmcargs;
+	if bootm ${fit_addr}; then
+		;
+	else
+		run altbootcmd;
+	fi;
+mmcdev=1
+mmcpart=1
+mmcpart_committed=1
+persist_mmcdev=
+	if test "${mmcdev}" != "${mmcdev_wanted}"; then
+		setenv mmcdev "${mmcdev_wanted}";
+		saveenv;
+	fi;
+setup_boot_menu=
+	if test "${mmcdev}" = 1; then
+		setenv emmc_priority 0;
+		setenv sd_priority 1;
+	else
+		setenv emmc_priority 1;
+		setenv sd_priority 0;
+	fi;
+	setenv bootmenu_${emmc_priority} eMMC=run boot_emmc;
+	setenv bootmenu_${sd_priority} SD=run boot_sd;
+SETUP_BOOT_MENU
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 827e545..f321cd5 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -311,7 +311,7 @@
 	return 0;
 }
 
-#if defined(CONFIG_NAND_SUNXI)
+#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
 static void nand_pinmux_setup(void)
 {
 	unsigned int pin;
@@ -347,9 +347,6 @@
 {
 	nand_pinmux_setup();
 	nand_clock_setup();
-#ifndef CONFIG_SPL_BUILD
-	sunxi_nand_init();
-#endif
 }
 #endif /* CONFIG_NAND_SUNXI */
 
diff --git a/board/ti/am62ax/evm.c b/board/ti/am62ax/evm.c
index beef3f2..f2dd3b4 100644
--- a/board/ti/am62ax/evm.c
+++ b/board/ti/am62ax/evm.c
@@ -7,7 +7,6 @@
  */
 
 #include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <common.h>
 #include <dm/uclass.h>
diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c
index 1b7b439..e00e42e 100644
--- a/board/ti/am62x/evm.c
+++ b/board/ti/am62x/evm.c
@@ -15,7 +15,6 @@
 #include <fdt_support.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
 #include <dm/uclass.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/ti/am64x/am64x.env b/board/ti/am64x/am64x.env
new file mode 100644
index 0000000..c3960be
--- /dev/null
+++ b/board/ti/am64x/am64x.env
@@ -0,0 +1,63 @@
+#include <environment/ti/ti_armv7_common.env>
+#include <environment/ti/mmc.env>
+#include <environment/ti/k3_dfu.env>
+
+findfdt=
+	if test $board_name = am64x_gpevm; then
+		setenv name_fdt k3-am642-evm.dtb; fi;
+	if test $board_name = am64x_skevm; then
+		setenv name_fdt k3-am642-sk.dtb; fi;
+	if test $name_fdt = undefined; then
+		echo WARNING: Could not determine device tree to use; fi;
+name_kern=Image
+console=ttyS2,115200n8
+args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 ${mtdparts}
+run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+
+boot=mmc
+mmcdev=1
+bootpart=1:2
+bootdir=/boot
+rd_spec=-
+init_mmc=run args_all args_mmc
+get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}
+get_overlay_mmc=
+	fdt address ${fdtaddr};
+	fdt resize 0x100000;
+	for overlay in $name_overlays;
+	do;
+	load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} &&
+	fdt apply ${dtboaddr};
+	done;
+get_kern_mmc=load mmc ${bootpart} ${loadaddr}
+	${bootdir}/${name_kern}
+get_fit_mmc=load mmc ${bootpart} ${addr_fit}
+	${bootdir}/${name_fit}
+partitions=name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}
+
+args_usb=run finduuid;setenv bootargs console=${console}
+	${optargs}
+	root=PARTUUID=${uuid} rw
+	rootfstype=${mmcrootfstype}
+init_usb=run args_all args_usb
+get_fdt_usb=load usb ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}
+get_overlay_usb=
+	fdt address ${fdtaddr};
+	fdt resize 0x100000;
+	for overlay in $name_overlays;
+	do;
+	load usb ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && fdt apply
+	${dtboaddr};
+	done;
+get_kern_usb=load usb ${bootpart} ${loadaddr}
+	${bootdir}/${name_kern}
+get_fit_usb=load usb ${bootpart} ${addr_fit}
+	${bootdir}/${name_fit}
+usbboot=setenv boot usb;
+	setenv bootpart 0:2;
+	usb start;
+	run findfdt;
+	run init_usb;
+	run get_kern_usb;
+	run get_fdt_usb;
+	run run_kern;
diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c
index c88139a..b63792e 100644
--- a/board/ti/am64x/evm.c
+++ b/board/ti/am64x/evm.c
@@ -14,7 +14,6 @@
 #include <spl.h>
 #include <fdt_support.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
 #include <env.h>
 
 #include "../common/board_detect.h"
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index b266ccb..706b219 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -13,7 +13,6 @@
 #include <image.h>
 #include <init.h>
 #include <net.h>
-#include <asm/arch/sys_proto.h>
 #include <asm/arch/hardware.h>
 #include <asm/global_data.h>
 #include <asm/gpio.h>
@@ -21,7 +20,6 @@
 #include <asm/omap_common.h>
 #include <env.h>
 #include <spl.h>
-#include <asm/arch/sys_proto.h>
 
 #include "../common/board_detect.h"
 
@@ -101,24 +99,6 @@
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	int ret;
-
-	ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
-	if (ret < 0)
-		ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
-					 "sram@70000000");
-	if (ret) {
-		printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
-		return ret;
-	}
-
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_TI_I2C_BOARD_DETECT
 int do_board_detect(void)
 {
diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig
index f03357c..49edd98 100644
--- a/board/ti/common/Kconfig
+++ b/board/ti/common/Kconfig
@@ -1,6 +1,5 @@
 config TI_I2C_BOARD_DETECT
 	bool "Support for Board detection for TI platforms"
-	select K3_BOARD_DETECT if ARCH_K3
 	help
 	   Support for detection board information on Texas Instrument's
 	   Evaluation Boards which have I2C based EEPROM detection
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index d4e672a..2398bea 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -15,13 +15,11 @@
 #include <init.h>
 #include <log.h>
 #include <net.h>
-#include <asm/arch/sys_proto.h>
 #include <asm/arch/hardware.h>
 #include <asm/global_data.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <spl.h>
-#include <asm/arch/sys_proto.h>
 #include <dm.h>
 #include <dm/uclass-internal.h>
 
@@ -144,18 +142,9 @@
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
-	int ret;
-
-	ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
-	if (ret < 0)
-		ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
-					 "sram@70000000");
-	if (ret)
-		printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
-
 	detect_enable_hyperflash(blob);
 
-	return ret;
+	return 0;
 }
 #endif
 
diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env
index 446395a..c181741 100644
--- a/board/ti/j721e/j721e.env
+++ b/board/ti/j721e/j721e.env
@@ -12,6 +12,8 @@
 	setenv name_fdt ${default_device_tree};
 	if test $board_name = j721e; then
 		setenv name_fdt k3-j721e-common-proc-board.dtb; fi;
+	if test $board_name = j7200; then
+		setenv name_fdt k3-j7200-common-proc-board.dtb; fi;
 	if test $board_name = j721e-eaik || test $board_name = j721e-sk; then
 		setenv name_fdt k3-j721e-sk.dtb; fi;
 	setenv fdtfile ${name_fdt}
@@ -21,7 +23,6 @@
 	${mtdparts}
 run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
 
-#if CONFIG_SYS_K3_SPL_ATF
 #if CONFIG_TARGET_J721E_R5_EVM
 addr_mcur5f0_0load=0x89000000
 name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw
@@ -29,7 +30,6 @@
 addr_mcur5f0_0load=0x89000000
 name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw
 #endif
-#endif
 
 boot=mmc
 mmcdev=1
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index c86715f..8eaca9d 100644
--- a/board/ti/j721s2/evm.c
+++ b/board/ti/j721s2/evm.c
@@ -15,12 +15,10 @@
 #include <init.h>
 #include <log.h>
 #include <net.h>
-#include <asm/arch/sys_proto.h>
 #include <asm/arch/hardware.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <spl.h>
-#include <asm/arch/sys_proto.h>
 #include <dm.h>
 #include <dm/uclass-internal.h>
 #include <dm/root.h>
@@ -73,22 +71,6 @@
 	return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	int ret;
-
-	ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
-	if (ret < 0)
-		ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
-					 "sram@70000000");
-	if (ret)
-		printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
-
-	return ret;
-}
-#endif
-
 #ifdef CONFIG_TI_I2C_BOARD_DETECT
 /*
  * Functions specific to EVM and SK designs of J721S2/AM68 family.
@@ -171,6 +153,135 @@
 	snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial);
 	env_set("serial#", serial_string);
 }
+
+/*
+ * Declaration of daughtercards to probe. Note that when adding more
+ * cards they should be grouped by the 'i2c_addr' field to allow for a
+ * more efficient probing process.
+ */
+static const struct {
+	u8 i2c_addr;		/* I2C address of card EEPROM */
+	char *card_name;	/* EEPROM-programmed card name */
+	char *dtbo_name;	/* Device tree overlay to apply */
+	u8 eth_offset;		/* ethXaddr MAC address index offset */
+} ext_cards[] = {
+	{
+		0x52,
+		"J7X-GESI-EXP",
+		"k3-j721s2-gesi-exp-board.dtbo",
+		1,		/* Start populating from eth1addr */
+	},
+};
+
+#define DAUGHTER_CARD_NO_OF_MAC_ADDR	5
+static bool daughter_card_detect_flags[ARRAY_SIZE(ext_cards)];
+
+static int probe_daughtercards(void)
+{
+	char mac_addr[DAUGHTER_CARD_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN];
+	bool eeprom_read_success;
+	struct ti_am6_eeprom ep;
+	u8 previous_i2c_addr;
+	u8 mac_addr_cnt;
+	int i;
+	int ret;
+
+	/* Mark previous I2C address variable as not populated */
+	previous_i2c_addr = 0xff;
+
+	/* No EEPROM data was read yet */
+	eeprom_read_success = false;
+
+	/* Iterate through list of daughtercards */
+	for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
+		/* Obtain card-specific I2C address */
+		u8 i2c_addr = ext_cards[i].i2c_addr;
+
+		/* Read card EEPROM if not already read previously */
+		if (i2c_addr != previous_i2c_addr) {
+			/* Store I2C address so we can avoid reading twice */
+			previous_i2c_addr = i2c_addr;
+
+			/* Get and parse the daughter card EEPROM record */
+			ret = ti_i2c_eeprom_am6_get(CONFIG_EEPROM_BUS_ADDRESS,
+						    i2c_addr,
+						    &ep,
+						    (char **)mac_addr,
+						    DAUGHTER_CARD_NO_OF_MAC_ADDR,
+						    &mac_addr_cnt);
+			if (ret) {
+				debug("%s: No daughtercard EEPROM at 0x%02x found %d\n",
+				      __func__, i2c_addr, ret);
+				eeprom_read_success = false;
+				/* Skip to the next daughtercard to probe */
+				continue;
+			}
+
+			/* EEPROM read successful, okay to further process. */
+			eeprom_read_success = true;
+		}
+
+		/* Only continue processing if EEPROM data was read */
+		if (!eeprom_read_success)
+			continue;
+
+		/* Only process the parsed data if we found a match */
+		if (strncmp(ep.name, ext_cards[i].card_name, sizeof(ep.name)))
+			continue;
+
+		printf("Detected: %s rev %s\n", ep.name, ep.version);
+		daughter_card_detect_flags[i] = true;
+
+		if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+			int j;
+			/*
+			 * Populate any MAC addresses from daughtercard into the U-Boot
+			 * environment, starting with a card-specific offset so we can
+			 * have multiple ext_cards contribute to the MAC pool in a well-
+			 * defined manner.
+			 */
+			for (j = 0; j < mac_addr_cnt; j++) {
+				if (!is_valid_ethaddr((u8 *)mac_addr[j]))
+					continue;
+
+				eth_env_set_enetaddr_by_index("eth", ext_cards[i].eth_offset + j,
+							      (uchar *)mac_addr[j]);
+			}
+		}
+	}
+
+	if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+		char name_overlays[1024] = { 0 };
+
+		for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
+			if (!daughter_card_detect_flags[i])
+				continue;
+
+			/* Skip if no overlays are to be added */
+			if (!strlen(ext_cards[i].dtbo_name))
+				continue;
+
+			/*
+			 * Make sure we are not running out of buffer space by checking
+			 * if we can fit the new overlay, a trailing space to be used
+			 * as a separator, plus the terminating zero.
+			 */
+			if (strlen(name_overlays) + strlen(ext_cards[i].dtbo_name) + 2 >
+			    sizeof(name_overlays))
+				return -ENOMEM;
+
+			/* Append to our list of overlays */
+			strcat(name_overlays, ext_cards[i].dtbo_name);
+			strcat(name_overlays, " ");
+		}
+
+		/* Apply device tree overlay(s) to the U-Boot environment, if any */
+		if (strlen(name_overlays))
+			return env_set("name_overlays", name_overlays);
+	}
+
+	return 0;
+}
 #endif
 
 /*
@@ -200,6 +311,7 @@
 	if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
 		setup_board_eeprom_env();
 		setup_serial();
+		probe_daughtercards();
 	}
 
 	return 0;
@@ -207,67 +319,4 @@
 
 void spl_board_init(void)
 {
-}
-
-/* Support for the various EVM / SK families */
-#if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT)
-void do_dt_magic(void)
-{
-	int ret, rescan, mmc_dev = -1;
-	static struct mmc *mmc;
-
-	do_board_detect();
-
-	/*
-	 * Board detection has been done.
-	 * Let us see if another dtb wouldn't be a better match
-	 * for our board
-	 */
-	if (IS_ENABLED(CONFIG_CPU_V7R)) {
-		ret = fdtdec_resetup(&rescan);
-		if (!ret && rescan) {
-			dm_uninit();
-			dm_init_and_scan(true);
-		}
-	}
-
-	/*
-	 * Because of multi DTB configuration, the MMC device has
-	 * to be re-initialized after reconfiguring FDT inorder to
-	 * boot from MMC. Do this when boot mode is MMC and ROM has
-	 * not loaded SYSFW.
-	 */
-	switch (spl_boot_device()) {
-	case BOOT_DEVICE_MMC1:
-		mmc_dev = 0;
-		break;
-	case BOOT_DEVICE_MMC2:
-	case BOOT_DEVICE_MMC2_2:
-		mmc_dev = 1;
-		break;
-	}
-
-	if (mmc_dev > 0 && !check_rom_loaded_sysfw()) {
-		ret = mmc_init_device(mmc_dev);
-		if (!ret) {
-			mmc = find_mmc_device(mmc_dev);
-			if (mmc) {
-				ret = mmc_init(mmc);
-				if (ret)
-					printf("mmc init failed with error: %d\n", ret);
-			}
-		}
-	}
-}
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-void board_init_f(ulong dummy)
-{
-	k3_spl_init();
-#if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT)
-	do_dt_magic();
-#endif
-	k3_mem_init();
 }
-#endif
diff --git a/board/ti/j721s2/j721s2.env b/board/ti/j721s2/j721s2.env
index 2152f88..f446777 100644
--- a/board/ti/j721s2/j721s2.env
+++ b/board/ti/j721s2/j721s2.env
@@ -25,12 +25,10 @@
 mmcdev=1
 bootpart=1:2
 bootdir=/boot
-#if CONFIG_SYS_K3_SPL_ATF
 #if CONFIG_TARGET_J721S2_R5_EVM
 addr_mcur5f0_0load=0x89000000
 name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw
 #endif
-#endif
 rd_spec=-
 init_mmc=run args_all args_mmc
 get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}
diff --git a/board/ti/omap5_uevm/Kconfig b/board/ti/omap5_uevm/Kconfig
deleted file mode 100644
index aa13844..0000000
--- a/board/ti/omap5_uevm/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OMAP5_UEVM
-
-config SYS_BOARD
-	default "omap5_uevm"
-
-config SYS_VENDOR
-	default "ti"
-
-config SYS_CONFIG_NAME
-	default "omap5_uevm"
-
-endif
diff --git a/board/ti/omap5_uevm/MAINTAINERS b/board/ti/omap5_uevm/MAINTAINERS
deleted file mode 100644
index ce54482..0000000
--- a/board/ti/omap5_uevm/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-OMAP5_UEVM BOARD
-M:	Tom Rini <trini@konsulko.com>
-S:	Maintained
-F:	board/ti/omap5_uevm/
-F:	include/configs/omap5_uevm.h
-F:	configs/omap5_uevm_defconfig
diff --git a/board/ti/omap5_uevm/Makefile b/board/ti/omap5_uevm/Makefile
deleted file mode 100644
index 17ee516..0000000
--- a/board/ti/omap5_uevm/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	:= evm.o
diff --git a/board/ti/omap5_uevm/README b/board/ti/omap5_uevm/README
deleted file mode 100644
index 970e2ec..0000000
--- a/board/ti/omap5_uevm/README
+++ /dev/null
@@ -1,25 +0,0 @@
-Summary
-=======
-
-This document covers various features of the 'omap5_uevm' build and some
-related uses.
-
-eMMC boot partition use
-=======================
-
-It is possible, depending on SYSBOOT configuration to boot from the eMMC
-boot partitions using (name depending on documentation referenced)
-Alternative Boot operation mode or Boot Sequence Option 1/2.  In this
-example we load MLO and u-boot.img from the build into DDR and then use
-'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
-set boot0 as the boot device.
-U-Boot # setenv autoload no
-U-Boot # usb start
-U-Boot # dhcp
-U-Boot # mmc dev 1 1
-U-Boot # tftp ${loadaddr} omap5uevm/MLO
-U-Boot # mmc write ${loadaddr} 0 100
-U-Boot # tftp ${loadaddr} omap5uevm/u-boot.img
-U-Boot # mmc write ${loadaddr} 300 400
-U-Boot # mmc bootbus 1 2 0 2
-U-Boot # mmc partconf 1 1 1 0
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
deleted file mode 100644
index 09cbd6b..0000000
--- a/board/ti/omap5_uevm/evm.c
+++ /dev/null
@@ -1,226 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Texas Instruments Incorporated, <www.ti.com>
- * Aneesh V       <aneesh@ti.com>
- * Steve Sakoman  <steve@sakoman.com>
- */
-#include <common.h>
-#include <init.h>
-#include <net.h>
-#include <palmas.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mmc_host_def.h>
-#include <serial.h>
-#include <tca642x.h>
-#include <usb.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-#include <linux/usb/gadget.h>
-#include <dwc3-uboot.h>
-#include <dwc3-omap-uboot.h>
-#include <ti-usb-phy-uboot.h>
-
-#include "mux_data.h"
-
-#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP)
-#include <sata.h>
-#include <usb.h>
-#include <asm/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/ehci.h>
-#include <asm/ehci-omap.h>
-#include <asm/arch/sata.h>
-
-#define DIE_ID_REG_BASE     (OMAP54XX_L4_CORE_BASE + 0x2000)
-#define DIE_ID_REG_OFFSET	0x200
-
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const struct omap_sysinfo sysinfo = {
-	"Board: OMAP5432 uEVM\n"
-};
-
-/**
- * @brief tca642x_init - uEVM default values for the GPIO expander
- * input reg, output reg, polarity reg, configuration reg
- */
-struct tca642x_bank_info tca642x_init[] = {
-	{ .input_reg = 0x00,
-	  .output_reg = 0x04,
-	  .polarity_reg = 0x00,
-	  .configuration_reg = 0x80 },
-	{ .input_reg = 0x00,
-	  .output_reg = 0x00,
-	  .polarity_reg = 0x00,
-	  .configuration_reg = 0xff },
-	{ .input_reg = 0x00,
-	  .output_reg = 0x00,
-	  .polarity_reg = 0x00,
-	  .configuration_reg = 0x40 },
-};
-
-#ifdef CONFIG_USB_DWC3
-static struct dwc3_device usb_otg_ss = {
-	.maximum_speed = USB_SPEED_SUPER,
-	.base = OMAP5XX_USB_OTG_SS_BASE,
-	.tx_fifo_resize = false,
-	.index = 0,
-};
-
-static struct dwc3_omap_device usb_otg_ss_glue = {
-	.base = (void *)OMAP5XX_USB_OTG_SS_GLUE_BASE,
-	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
-	.index = 0,
-};
-
-static struct ti_usb_phy_device usb_phy_device = {
-	.pll_ctrl_base = (void *)OMAP5XX_USB3_PHY_PLL_CTRL,
-	.usb2_phy_power = (void *)OMAP5XX_USB2_PHY_POWER,
-	.usb3_phy_power = (void *)OMAP5XX_USB3_PHY_POWER,
-	.index = 0,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	if (index) {
-		printf("Invalid Controller Index\n");
-		return -EINVAL;
-	}
-
-	if (init == USB_INIT_DEVICE) {
-		usb_otg_ss.dr_mode = USB_DR_MODE_PERIPHERAL;
-		usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
-	} else {
-		usb_otg_ss.dr_mode = USB_DR_MODE_HOST;
-		usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
-	}
-
-	enable_usb_clocks(index);
-	ti_usb_phy_uboot_init(&usb_phy_device);
-	dwc3_omap_uboot_init(&usb_otg_ss_glue);
-	dwc3_uboot_init(&usb_otg_ss);
-
-	return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	if (index) {
-		printf("Invalid Controller Index\n");
-		return -EINVAL;
-	}
-
-	ti_usb_phy_uboot_exit(index);
-	dwc3_uboot_exit(index);
-	dwc3_omap_uboot_exit(index);
-	disable_usb_clocks(index);
-
-	return 0;
-}
-
-int usb_gadget_handle_interrupts(int index)
-{
-	u32 status;
-
-	status = dwc3_omap_uboot_interrupt_status(index);
-	if (status)
-		dwc3_uboot_handle_interrupt(index);
-
-	return 0;
-}
-#endif
-
-/**
- * @brief board_init
- *
- * Return: 0
- */
-int board_init(void)
-{
-	gpmc_init();
-	gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
-	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
-
-	tca642x_set_inital_state(CFG_SYS_I2C_TCA642X_ADDR, tca642x_init);
-
-	return 0;
-}
-
-#if defined(CONFIG_SPL_OS_BOOT)
-int spl_start_uboot(void)
-{
-	/* break into full u-boot on 'c' */
-	if (serial_tstc() && serial_getc() == 'c')
-		return 1;
-
-	return 0;
-}
-#endif /* CONFIG_SPL_OS_BOOT */
-
-int board_eth_init(struct bd_info *bis)
-{
-	return 0;
-}
-
-/**
- * @brief misc_init_r - Configure EVM board specific configurations
- * such as power configurations, ethernet initialization as phase2 of
- * boot sequence
- *
- * Return: 0
- */
-int misc_init_r(void)
-{
-#ifdef CONFIG_PALMAS_POWER
-	palmas_init_settings();
-#endif
-
-	omap_die_id_usbethaddr();
-
-	return 0;
-}
-
-void set_muxconf_regs(void)
-{
-	do_set_mux((*ctrl)->control_padconf_core_base,
-		   core_padconf_array_essential,
-		   sizeof(core_padconf_array_essential) /
-		   sizeof(struct pad_conf_entry));
-
-	do_set_mux((*ctrl)->control_padconf_wkup_base,
-		   wkup_padconf_array_essential,
-		   sizeof(wkup_padconf_array_essential) /
-		   sizeof(struct pad_conf_entry));
-}
-
-#if defined(CONFIG_MMC)
-int board_mmc_init(struct bd_info *bis)
-{
-	omap_mmc_init(0, 0, 0, -1, -1);
-	omap_mmc_init(1, 0, 0, -1, -1);
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_XHCI_OMAP
-/**
- * @brief board_usb_init - Configure EVM board specific configurations
- * for the LDO's and clocks for the USB blocks.
- *
- * Return: 0
- */
-int board_usb_init(int index, enum usb_init_type init)
-{
-	int ret;
-#ifdef CONFIG_PALMAS_USB_SS_PWR
-	ret = palmas_enable_ss_ldo();
-#endif
-
-	return 0;
-}
-#endif
diff --git a/board/ti/omap5_uevm/mux_data.h b/board/ti/omap5_uevm/mux_data.h
deleted file mode 100644
index 3c4ba47..0000000
--- a/board/ti/omap5_uevm/mux_data.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010
- * Texas Instruments Incorporated, <www.ti.com>
- *
- *	Sricharan R		<r.sricharan@ti.com>
- */
-#ifndef _EVM5430_MUX_DATA_H
-#define _EVM5430_MUX_DATA_H
-
-#include <asm/arch/mux_omap5.h>
-
-const struct pad_conf_entry core_padconf_array_essential[] = {
-
-	{EMMC_CLK, (PTU | IEN | M0)}, /*  EMMC_CLK   */
-	{EMMC_CMD, (PTU | IEN | M0)}, /*  EMMC_CMD   */
-	{EMMC_DATA0, (PTU | IEN | M0)}, /*  EMMC_DATA0 */
-	{EMMC_DATA1, (PTU | IEN | M0)}, /*  EMMC_DATA1 */
-	{EMMC_DATA2, (PTU | IEN | M0)}, /*  EMMC_DATA2 */
-	{EMMC_DATA3, (PTU | IEN | M0)}, /*  EMMC_DATA3 */
-	{EMMC_DATA4, (PTU | IEN | M0)}, /*  EMMC_DATA4 */
-	{EMMC_DATA5, (PTU | IEN | M0)}, /*  EMMC_DATA5 */
-	{EMMC_DATA6, (PTU | IEN | M0)}, /*  EMMC_DATA6 */
-	{EMMC_DATA7, (PTU | IEN | M0)}, /*  EMMC_DATA7 */
-	{SDCARD_CLK, (PTU | IEN | M0)}, /*  SDCARD_CLK  */
-	{SDCARD_CMD, (PTU | IEN | M0)}, /*  SDCARD_CMD  */
-	{SDCARD_DATA0, (PTU | IEN | M0)}, /*  SDCARD_DATA0*/
-	{SDCARD_DATA1, (PTU | IEN | M0)}, /*  SDCARD_DATA1*/
-	{SDCARD_DATA2, (PTU | IEN | M0)}, /*  SDCARD_DATA2*/
-	{SDCARD_DATA3, (PTU | IEN | M0)}, /*  SDCARD_DATA3*/
-	{UART3_RX_IRRX, (PTU | IEN | M0)}, /*  UART3_RX_IRRX    */
-	{UART3_TX_IRTX, (M0)},    /*  UART3_TX_IRTX    */
-	{USBB1_HSIC_STROBE, (PTU | IEN | M0)},    /*  USBB1_HSIC_STROBE */
-	{USBB1_HSIC_DATA, (PTU | IEN | M0)},    /*  USBB1_HSIC_DATA */
-	{USBB2_HSIC_STROBE, (PTU | IEN | M0)},    /*  USBB2_HSIC_STROBE */
-	{USBB2_HSIC_DATA, (PTU | IEN | M0)},    /*  USBB2_HSIC_DATA  */
-	{USBB3_HSIC_STROBE, (PTU | IEN | M0)},    /*  USBB3_HSIC_STROBE*/
-	{USBB3_HSIC_DATA, (PTU | IEN | M0)},    /*  USBB3_HSIC_DATA  */
-	{USBD0_HS_DP, (IEN | M0)},	/*  USBD0_HS_DP */
-	{USBD0_HS_DM, (IEN | M0)},	/*  USBD0_HS_DM */
-	{USBD0_SS_RX, (IEN | M0)},	/*  USBD0_SS_RX */
-	{I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */
-	{I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */
-	{HSI2_ACWAKE, (PTU | M6)},    /*  HSI2_ACWAKE */
-	{HSI2_CAFLAG, (PTU | M6)},    /*  HSI2_CAFLAG */
-};
-
-const struct pad_conf_entry wkup_padconf_array_essential[] = {
-
-	{SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */
-	{SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */
-	{SYS_32K, (IEN | M0)}, /*  SYS_32K     */
-	{FREF_CLK1_OUT, (PTD | IEN | M0)},    /*  FREF_CLK1_OUT  */
-
-};
-
-#endif /* _EVM4430_MUX_DATA_H */
diff --git a/boot/Kconfig b/boot/Kconfig
index d95a2a7..8c27f52 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -231,7 +231,7 @@
 	depends on SPL_LOAD_FIT
 	select OF_LIBFDT_OVERLAY
 	help
-	  The device tree is loaded from the FIT image. Allow the SPL is to
+	  The device tree is loaded from the FIT image. Allow the SPL to
 	  also load device-tree overlays from the FIT image an apply them
 	  over the device tree.
 
diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c
index d34b7e3..57d2944 100644
--- a/boot/bootdev-uclass.c
+++ b/boot/bootdev-uclass.c
@@ -174,6 +174,8 @@
 	} else {
 		ret = fs_set_blk_dev_with_part(desc, bflow->part);
 		bflow->state = BOOTFLOWST_PART;
+		if (ret)
+			return log_msg_ret("fs", ret);
 
 		/* Use an #ifdef due to info.sys_ind */
 #ifdef CONFIG_DOS_PARTITION
@@ -181,8 +183,7 @@
 			  blk->name, bflow->part, info.sys_ind,
 			  ret ? -1 : fs_get_type());
 #endif
-		if (ret)
-			return log_msg_ret("fs", ret);
+		bflow->blk = blk;
 		bflow->state = BOOTFLOWST_FS;
 	}
 
@@ -364,7 +365,8 @@
  * @seqp: Returns the sequence number, or -1 if none
  * @method_flagsp: If non-NULL, returns any flags implied by the label
  * (enum bootflow_meth_flags_t), 0 if none
- * Returns: sequence number on success, else -ve error code
+ * Returns: sequence number on success, -EPFNOSUPPORT is the uclass is not
+ * known, other -ve error code on other error
  */
 static int label_to_uclass(const char *label, int *seqp, int *method_flagsp)
 {
@@ -394,8 +396,7 @@
 			id = UCLASS_ETH;
 			method_flags |= BOOTFLOW_METHF_DHCP_ONLY;
 		} else {
-			log_warning("Unknown uclass '%s' in label\n", label);
-			return -EINVAL;
+			return -EPFNOSUPPORT;
 		}
 	}
 	if (id == UCLASS_USB)
@@ -458,7 +459,6 @@
 		}
 		log_debug("- no device in %s\n", media->name);
 	}
-	log_warning("Unknown seq %d for label '%s'\n", seq, label);
 
 	return -ENOENT;
 }
@@ -577,9 +577,28 @@
 
 	log_debug("next\n");
 	for (dev = NULL; !dev && iter->labels[++iter->cur_label];) {
-		log_debug("Scanning: %s\n", iter->labels[iter->cur_label]);
-		bootdev_hunt_and_find_by_label(iter->labels[iter->cur_label],
-					       &dev, method_flagsp);
+		const char *label = iter->labels[iter->cur_label];
+		int ret;
+
+		log_debug("Scanning: %s\n", label);
+		ret = bootdev_hunt_and_find_by_label(label, &dev,
+						     method_flagsp);
+		if (iter->flags & BOOTFLOWIF_SHOW) {
+			if (ret == -EPFNOSUPPORT) {
+				log_warning("Unknown uclass '%s' in label\n",
+					    label);
+			} else if (ret == -ENOENT) {
+				/*
+				 * looking for, e.g. 'scsi0' should find
+				 * something if SCSI is present
+				 */
+				if (!trailing_strtol(label)) {
+					log_warning("No bootdevs for '%s'\n",
+						    label);
+				}
+			}
+		}
+
 	}
 
 	if (!dev)
diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c
index 6a97ac0..6f70f22 100644
--- a/boot/bootmeth_efi.c
+++ b/boot/bootmeth_efi.c
@@ -94,7 +94,7 @@
 	return 0;
 }
 
-static int efiload_read_file(struct blk_desc *desc, struct bootflow *bflow)
+static void set_efi_bootdev(struct blk_desc *desc, struct bootflow *bflow)
 {
 	const struct udevice *media_dev;
 	int size = bflow->size;
@@ -102,11 +102,6 @@
 	char devnum_str[9];
 	char dirname[200];
 	char *last_slash;
-	int ret;
-
-	ret = bootmeth_alloc_file(bflow, 0x2000000, 0x10000);
-	if (ret)
-		return log_msg_ret("read", ret);
 
 	/*
 	 * This is a horrible hack to tell EFI about this boot device. Once we
@@ -117,7 +112,9 @@
 	 * this can go away.
 	 */
 	media_dev = dev_get_parent(bflow->dev);
-	snprintf(devnum_str, sizeof(devnum_str), "%x", dev_seq(media_dev));
+	snprintf(devnum_str, sizeof(devnum_str), "%x:%x",
+		 desc ? desc->devnum : dev_seq(media_dev),
+		 bflow->part);
 
 	strlcpy(dirname, bflow->fname, sizeof(dirname));
 	last_slash = strrchr(dirname, '/');
@@ -130,6 +127,15 @@
 	dev_name = device_get_uclass_id(media_dev) == UCLASS_MASS_STORAGE ?
 		 "usb" : dev_get_uclass_name(media_dev);
 	efi_set_bootdev(dev_name, devnum_str, bflow->fname, bflow->buf, size);
+}
+
+static int efiload_read_file(struct blk_desc *desc, struct bootflow *bflow)
+{
+	int ret;
+
+	ret = bootmeth_alloc_file(bflow, 0x2000000, 0x10000);
+	if (ret)
+		return log_msg_ret("read", ret);
 
 	return 0;
 }
@@ -235,21 +241,21 @@
 
 	/* try the various available names */
 	ret = -ENOENT;
-	for (seq = 0; ret; seq++) {
+	*fname = '\0';
+	for (seq = 0; ret == -ENOENT; seq++) {
 		ret = distro_efi_get_fdt_name(fname, sizeof(fname), seq);
-		if (ret == -EALREADY) {
+		if (ret == -EALREADY)
 			bflow->flags = BOOTFLOWF_USE_PRIOR_FDT;
-			break;
-		}
-		if (ret)
-			return log_msg_ret("nam", ret);
-		ret = bootmeth_common_read_file(dev, bflow, fname, fdt_addr,
-						&size);
+		if (!ret)
+			ret = bootmeth_common_read_file(dev, bflow, fname,
+							fdt_addr, &size);
 	}
 
-	bflow->fdt_fname = strdup(fname);
-	if (!bflow->fdt_fname)
-		return log_msg_ret("fil", -ENOMEM);
+	if (*fname) {
+		bflow->fdt_fname = strdup(fname);
+		if (!bflow->fdt_fname)
+			return log_msg_ret("fil", -ENOMEM);
+	}
 
 	if (!ret) {
 		bflow->fdt_size = size;
@@ -373,6 +379,13 @@
 
 	/* A non-zero buffer indicates the kernel is there */
 	if (bflow->buf) {
+		/* Set the EFI bootdev again, since reading an FDT loses it! */
+		if (bflow->blk) {
+			struct blk_desc *desc = dev_get_uclass_plat(bflow->blk);
+
+			set_efi_bootdev(desc, bflow);
+		}
+
 		kernel = (ulong)map_to_sysmem(bflow->buf);
 
 		/*
diff --git a/boot/image-board.c b/boot/image-board.c
index c602832..d500da1 100644
--- a/boot/image-board.c
+++ b/boot/image-board.c
@@ -328,7 +328,7 @@
 	bool done_select = !select;
 	bool done = false;
 	int rd_noffset;
-	ulong rd_addr;
+	ulong rd_addr = 0;
 	char *buf;
 
 	if (CONFIG_IS_ENABLED(FIT)) {
diff --git a/boot/vbe_simple.c b/boot/vbe_simple.c
index 59676d8..12682ab 100644
--- a/boot/vbe_simple.c
+++ b/boot/vbe_simple.c
@@ -148,11 +148,13 @@
 {
 	int ret;
 
-	if (vbe_phase() == VBE_PHASE_FIRMWARE) {
-		ret = vbe_simple_read_bootflow_fw(dev, bflow);
-		if (ret)
-			return log_msg_ret("fw", ret);
-		return 0;
+	if (CONFIG_IS_ENABLED(BOOTMETH_VBE_SIMPLE_FW)) {
+		if (vbe_phase() == VBE_PHASE_FIRMWARE) {
+			ret = vbe_simple_read_bootflow_fw(dev, bflow);
+			if (ret)
+				return log_msg_ret("fw", ret);
+			return 0;
+		}
 	}
 
 	return -EINVAL;
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index f709904..365357c 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -11,6 +11,7 @@
 #include <dm.h>
 #include <env.h>
 #include <lmb.h>
+#include <mapmem.h>
 #include <net.h>
 #include <video.h>
 #include <vsprintf.h>
@@ -41,17 +42,26 @@
 	printf("%-12s= 0x%.*llx\n", name, 2 * (int)sizeof(ulong), value);
 }
 
-static void print_eth(int idx)
+static void print_eth(void)
 {
-	char name[10], *val;
+	const int idx = eth_get_dev_index();
+	uchar enetaddr[6];
+	char name[10];
+	int ret;
+
 	if (idx)
 		sprintf(name, "eth%iaddr", idx);
 	else
 		strcpy(name, "ethaddr");
-	val = env_get(name);
-	if (!val)
-		val = "(not set)";
-	printf("%-12s= %s\n", name, val);
+
+	ret = eth_env_get_enetaddr_by_index("eth", idx, enetaddr);
+
+	printf("current eth = %s\n", eth_get_name());
+	if (!ret)
+		printf("%-12s= (not set)\n", name);
+	else
+		printf("%-12s= %pM\n", name, enetaddr);
+	printf("IP addr     = %s\n", env_get("ipaddr"));
 }
 
 void bdinfo_print_mhz(const char *name, unsigned long hz)
@@ -123,13 +133,10 @@
 	bdinfo_print_num_l("relocaddr", gd->relocaddr);
 	bdinfo_print_num_l("reloc off", gd->reloc_off);
 	printf("%-12s= %u-bit\n", "Build", (uint)sizeof(void *) * 8);
-	if (IS_ENABLED(CONFIG_CMD_NET)) {
-		printf("current eth = %s\n", eth_get_name());
-		print_eth(0);
-		printf("IP addr     = %s\n", env_get("ipaddr"));
-	}
-	bdinfo_print_num_l("fdt_blob", (ulong)gd->fdt_blob);
-	bdinfo_print_num_l("new_fdt", (ulong)gd->new_fdt);
+	if (IS_ENABLED(CONFIG_CMD_NET))
+		print_eth();
+	bdinfo_print_num_l("fdt_blob", (ulong)map_to_sysmem(gd->fdt_blob));
+	bdinfo_print_num_l("new_fdt", (ulong)map_to_sysmem(gd->new_fdt));
 	bdinfo_print_num_l("fdt_size", (ulong)gd->fdt_size);
 	if (IS_ENABLED(CONFIG_VIDEO))
 		show_video_info();
diff --git a/cmd/bootflow.c b/cmd/bootflow.c
index 42f6e14..cfe3422 100644
--- a/cmd/bootflow.c
+++ b/cmd/bootflow.c
@@ -181,6 +181,9 @@
 	if (list)
 		show_footer(i, num_valid);
 
+	if (IS_ENABLED(CONFIG_CMD_BOOTFLOW_FULL) && !num_valid && !list)
+		printf("No bootflows found; try again with -l\n");
+
 	return 0;
 }
 
@@ -387,6 +390,11 @@
 	bool text_mode = false;
 	int ret;
 
+	if (!IS_ENABLED(CONFIG_EXPO)) {
+		printf("Menu not supported\n");
+		return CMD_RET_FAILURE;
+	}
+
 	if (argc > 1 && *argv[1] == '-')
 		text_mode = strchr(argv[1], 't');
 
@@ -394,20 +402,15 @@
 	if (ret)
 		return CMD_RET_FAILURE;
 
-	if (IS_ENABLED(CONFIG_EXPO)) {
-		ret = bootflow_menu_run(std, text_mode, &bflow);
-		if (ret) {
-			if (ret == -EAGAIN)
-				printf("Nothing chosen\n");
-			else
-				printf("Menu failed (err=%d)\n", ret);
+	ret = bootflow_menu_run(std, text_mode, &bflow);
+	if (ret) {
+		if (ret == -EAGAIN)
+			printf("Nothing chosen\n");
+		else {
+			printf("Menu failed (err=%d)\n", ret);
+			return CMD_RET_FAILURE;
 		}
-	} else {
-		printf("Menu not supported\n");
-		ret = -ENOSYS;
 	}
-	if (ret)
-		return CMD_RET_FAILURE;
 
 	printf("Selected: %s\n", bflow->os_name ? bflow->os_name : bflow->name);
 	std->cur_bootflow = bflow;
diff --git a/cmd/ide.c b/cmd/ide.c
index 6739f0b..ddc87d3 100644
--- a/cmd/ide.c
+++ b/cmd/ide.c
@@ -10,12 +10,15 @@
 
 #include <common.h>
 #include <blk.h>
+#include <dm.h>
 #include <config.h>
 #include <watchdog.h>
 #include <command.h>
 #include <image.h>
 #include <asm/byteorder.h>
 #include <asm/io.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
 
 #include <ide.h>
 #include <ata.h>
@@ -31,8 +34,25 @@
 {
 	if (argc == 2) {
 		if (strncmp(argv[1], "res", 3) == 0) {
+			struct udevice *dev;
+			int ret;
+
 			puts("\nReset IDE: ");
-			ide_init();
+			ret = uclass_find_first_device(UCLASS_IDE, &dev);
+			ret = device_remove(dev, DM_REMOVE_NORMAL);
+			if (!ret)
+				ret = device_chld_unbind(dev, NULL);
+			if (ret) {
+				printf("Cannot remove IDE (err=%dE)\n", ret);
+				return CMD_RET_FAILURE;
+			}
+
+			ret = uclass_first_device_err(UCLASS_IDE, &dev);
+			if (ret) {
+				printf("Init failed (err=%dE)\n", ret);
+				return CMD_RET_FAILURE;
+			}
+
 			return 0;
 		}
 	}
diff --git a/cmd/tpm_test.c b/cmd/tpm_test.c
index b35eae8..c4ed8e5 100644
--- a/cmd/tpm_test.c
+++ b/cmd/tpm_test.c
@@ -471,6 +471,7 @@
 			break;
 		case TPM_MAXNVWRITES:
 			assert(i >= TPM_MAX_NV_WRITES_NOOWNER);
+			break;
 		default:
 			pr_err("\tunexpected error code %d (0x%x)\n",
 			      result, result);
diff --git a/common/Kconfig b/common/Kconfig
index 7c72186..bbabadb 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -559,7 +559,7 @@
 
 config DISPLAY_CPUINFO
 	bool "Display information about the CPU during start up"
-	default y if ARC|| ARM || NIOS2 || X86 || XTENSA || M68K
+	default y if ARC || ARM || NIOS2 || X86 || XTENSA || M68K
 	help
 	  Display information about the CPU that U-Boot is running on
 	  when U-Boot starts up. The function print_cpuinfo() is called
@@ -626,7 +626,7 @@
 	bool "Enable event debugging assistance"
 	default y if SANDBOX
 	help
-	  Enable this get usefui features for seeing what is happening with
+	  Enable this to get useful features for seeing what is happening with
 	  events, such as event-type names. This adds to the code size of
 	  U-Boot so can be turned off for production builds.
 
diff --git a/common/board_r.c b/common/board_r.c
index 6b4180b..d798c00 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -519,20 +519,6 @@
 }
 #endif
 
-#if defined(CONFIG_IDE) && !defined(CONFIG_BLK)
-static int initr_ide(void)
-{
-	puts("IDE:   ");
-#if defined(CONFIG_START_IDE)
-	if (board_start_ide())
-		ide_init();
-#else
-	ide_init();
-#endif
-	return 0;
-}
-#endif
-
 #if defined(CFG_PRAM)
 /*
  * Export available size of memory for Linux, taking into account the
@@ -783,9 +769,6 @@
 #ifdef CONFIG_POST
 	initr_post,
 #endif
-#if defined(CONFIG_IDE) && !defined(CONFIG_BLK)
-	initr_ide,
-#endif
 #ifdef CONFIG_LAST_STAGE_INIT
 	INIT_FUNC_WATCHDOG_RESET
 	/*
diff --git a/common/cli_hush.c b/common/cli_hush.c
index 1ad7a50..171069f 100644
--- a/common/cli_hush.c
+++ b/common/cli_hush.c
@@ -2171,12 +2171,18 @@
 	 * NAME=VALUE format.  So the first order of business is to
 	 * split 's' on the '=' into 'name' and 'value' */
 	value = strchr(name, '=');
-	if (value == NULL || *(value + 1) == 0) {
+	if (!value) {
 		free(name);
 		return -1;
 	}
 	*value++ = 0;
 
+	if (!*value) {
+		unset_local_var(name);
+		free(name);
+		return 0;
+	}
+
 	for(cur = top_vars; cur; cur = cur->next) {
 		if(strcmp(cur->name, name)==0)
 			break;
diff --git a/common/fdt_simplefb.c b/common/fdt_simplefb.c
index 282c34f..069ced7 100644
--- a/common/fdt_simplefb.c
+++ b/common/fdt_simplefb.c
@@ -71,7 +71,13 @@
 	return fdt_simplefb_configure_node(blob, off);
 }
 
-int fdt_simplefb_enable_existing_node(void *blob)
+/**
+ * fdt_simplefb_enable_existing_node() - enable simple-framebuffer DT node
+ *
+ * @blob:	device-tree
+ * Return:	0 on success, non-zero otherwise
+ */
+static int fdt_simplefb_enable_existing_node(void *blob)
 {
 	int off;
 
diff --git a/common/fdt_support.c b/common/fdt_support.c
index dbceec6..2053fe3 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -1486,11 +1486,11 @@
 }
 
 /**
- * fdt_node_offset_by_compat_reg: Find a node that matches compatiable and
+ * fdt_node_offset_by_compat_reg: Find a node that matches compatible and
  * who's reg property matches a physical cpu address
  *
  * @blob: ptr to device tree
- * @compat: compatiable string to match
+ * @compat: compatible string to match
  * @compat_off: property name
  *
  */
diff --git a/configs/A33-OLinuXino_defconfig b/configs/A33-OLinuXino_defconfig
index fc32a86..df4acaf 100644
--- a/configs/A33-OLinuXino_defconfig
+++ b/configs/A33-OLinuXino_defconfig
@@ -7,7 +7,6 @@
 CONFIG_DRAM_ZQ=15291
 CONFIG_DRAM_ODT_EN=y
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PB3"
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0"
@@ -15,5 +14,6 @@
 CONFIG_VIDEO_LCD_BL_EN="PB2"
 CONFIG_VIDEO_LCD_BL_PWM="PH0"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig
index 9ae3893..51f26f4 100644
--- a/configs/Ainol_AW1_defconfig
+++ b/configs/Ainol_AW1_defconfig
@@ -6,7 +6,6 @@
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_ZQ=123
 CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:40000,le:87,ri:112,up:38,lo:141,hs:1,vs:1,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_POWER="PH8"
@@ -17,4 +16,5 @@
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/CMPC885_defconfig b/configs/CMPC885_defconfig
index 7dff6ff..0a24684 100644
--- a/configs/CMPC885_defconfig
+++ b/configs/CMPC885_defconfig
@@ -4,14 +4,14 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="cmpc885"
 CONFIG_SYS_PROMPT="S3K> "
+CONFIG_SYS_CLK_FREQ=132000000
 CONFIG_ENV_ADDR=0x40004000
 CONFIG_MPC8xx=y
+# CONFIG_PCI is not set
 CONFIG_TARGET_CMPC885=y
 CONFIG_MPC885=y
-CONFIG_8xx_GCLK_FREQ=132000000
 CONFIG_CMD_IMMAP=y
 CONFIG_SYS_SIUMCR=0x00620000
-CONFIG_SYS_SYPCR=0xFFFFFF8F
 CONFIG_SYS_TBSCR=0x00C3
 CONFIG_SYS_PISCR=0x0000
 CONFIG_SYS_PLPRCR_BOOL=y
@@ -24,8 +24,11 @@
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_BOOTDELAY=5
 CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_FLUSH_STDIN=y
 CONFIG_AUTOBOOT_PROMPT="\nEnter password - autoboot in %d sec...\n"
-CONFIG_AUTOBOOT_DELAY_STR="root"
+CONFIG_AUTOBOOT_ENCRYPTION=y
+CONFIG_AUTOBOOT_STOP_STR_ENABLE=y
+CONFIG_AUTOBOOT_STOP_STR_SHA256="4813494d137e1631bba301d5acab6e7bb7aa74ce1185d456565ef51d737677b2"
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run flashboot"
 CONFIG_BOARD_EARLY_INIT_R=y
@@ -100,11 +103,11 @@
 CONFIG_MPC8XX_FEC=y
 CONFIG_FEC1_PHY=1
 CONFIG_FEC2_PHY=2
-# CONFIG_PCI is not set
 CONFIG_DM_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_MPC8XX_SPI=y
 CONFIG_WDT=y
+CONFIG_WDT_MPC8xxx_BME=y
 # CONFIG_REGEX is not set
 CONFIG_LZMA=y
diff --git a/configs/CMPCPRO_defconfig b/configs/CMPCPRO_defconfig
new file mode 100644
index 0000000..7313715
--- /dev/null
+++ b/configs/CMPCPRO_defconfig
@@ -0,0 +1,209 @@
+CONFIG_PPC=y
+CONFIG_SYS_IMMR=0xB0000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="cmpcpro"
+CONFIG_SYS_PROMPT="MPC_PRO> "
+CONFIG_SYS_CLK_FREQ=66666667
+CONFIG_ENV_ADDR=0x400e0000
+CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_CMPCPRO=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="FLASH"
+CONFIG_BAT0_BASE=0x40000000
+CONFIG_BAT0_LENGTH_64_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_WRITETHROUGH=y
+CONFIG_BAT0_DCACHE_WRITETHROUGH=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="DDR"
+CONFIG_BAT1_BASE=0x00000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="DDR2"
+CONFIG_BAT2_BASE=0x10000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="BCSR"
+CONFIG_BAT3_BASE=0xA0000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_GUARDED=y
+CONFIG_BAT3_DCACHE_WRITETHROUGH=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="PERIPHETH"
+CONFIG_BAT4_BASE=0x90000000
+CONFIG_BAT4_LENGTH_64_MBYTES=y
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_ICACHE_GUARDED=y
+CONFIG_BAT4_DCACHE_WRITETHROUGH=y
+CONFIG_BAT4_DCACHE_INHIBITED=y
+CONFIG_BAT4_DCACHE_GUARDED=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="CARTEBASE"
+CONFIG_BAT5_BASE=0x80000000
+CONFIG_BAT5_LENGTH_64_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_WRITETHROUGH=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="IMMRBAR"
+CONFIG_BAT6_BASE=0xB0000000
+CONFIG_BAT6_LENGTH_4_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT7=y
+CONFIG_BAT7_NAME="STACK"
+CONFIG_BAT7_BASE=0xE6000000
+CONFIG_BAT7_ACCESS_RW=y
+CONFIG_BAT7_USER_MODE_VALID=y
+CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0x40000000
+CONFIG_LBLAW0_LENGTH_64_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xA0000000
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0x90000000
+CONFIG_LBLAW2_LENGTH_64_MBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0x80000000
+CONFIG_LBLAW3_LENGTH_64_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_IFEB=y
+CONFIG_HID2_EBPX=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_3=y
+CONFIG_ACR_RPTCNT_3=y
+CONFIG_SPCR_OPT_SPEC_READ=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
+CONFIG_SYS_MONITOR_LEN=393216
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=5
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_FLUSH_STDIN=y
+CONFIG_AUTOBOOT_PROMPT="\nEnter password - autoboot in %d sec...\n"
+CONFIG_AUTOBOOT_ENCRYPTION=y
+CONFIG_AUTOBOOT_STOP_STR_ENABLE=y
+CONFIG_AUTOBOOT_STOP_STR_SHA256="4813494d137e1631bba301d5acab6e7bb7aa74ce1185d456565ef51d737677b2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run flashboot"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_MISC_INIT_R=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_SYS_BOOTM_LEN=0x10000000
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_BOOTFILESIZE=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+# CONFIG_CMD_SLEEP is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="UEC0"
+CONFIG_USE_HOSTNAME=y
+CONFIG_HOSTNAME="cmpcpro"
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.0.3"
+CONFIG_USE_NETMASK=y
+CONFIG_NETMASK="255.255.255.0"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.0.1"
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_CLK=y
+CONFIG_CPU=y
+CONFIG_CPU_MPC83XX=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0x40001001
+CONFIG_SYS_OR0_PRELIM=0xFC001080
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xA0000801
+CONFIG_SYS_OR1_PRELIM=0xFFFF9030
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0x90001001
+CONFIG_SYS_OR2_PRELIM=0xfc001090
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0x80001081
+CONFIG_SYS_OR3_PRELIM=0xfc000100
+CONFIG_MPC8XXX_GPIO=y
+CONFIG_QE_GPIO=y
+# CONFIG_I2C is not set
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_MII=y
+CONFIG_RMII=y
+CONFIG_QE_UEC=y
+CONFIG_QE=y
+CONFIG_U_QE=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MPC8XXX_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_MPC83XX=y
+CONFIG_WDT=y
+CONFIG_WDT_MPC8xxx=y
+# CONFIG_REGEX is not set
+CONFIG_LZMA=y
diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig
index 5eee23f..2f93a7b 100644
--- a/configs/Cubieboard4_defconfig
+++ b/configs/Cubieboard4_defconfig
@@ -6,10 +6,11 @@
 CONFIG_DRAM_CLK=672
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH16"
 CONFIG_USB1_VBUS_PIN="PH14"
 CONFIG_USB3_VBUS_PIN="PH15"
 CONFIG_AXP_GPIO=y
 CONFIG_SYS_I2C_SUN8I_RSB=y
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP809_POWER=y
diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig
index 13f9589..29f4df2 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -8,7 +8,6 @@
 CONFIG_DRAM_ODT_EN=y
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH11"
 CONFIG_USB1_VBUS_PIN="PD29"
 CONFIG_USB2_VBUS_PIN="PL6"
@@ -22,6 +21,7 @@
 CONFIG_SYS_I2C_SPEED=400000
 CONFIG_PHY_REALTEK=y
 CONFIG_SUN8I_EMAC=y
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DLDO3_VOLT=2500
 CONFIG_AXP_DLDO4_VOLT=3300
 CONFIG_AXP_FLDO1_VOLT=1200
diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig
index f96a2f2..36c9a7e 100644
--- a/configs/M5235EVB_Flash32_defconfig
+++ b/configs/M5235EVB_Flash32_defconfig
@@ -45,11 +45,8 @@
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.162.1.1"
 CONFIG_SYS_RX_ETH_BUFFER=8
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x300
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=80000
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y
@@ -61,4 +58,3 @@
 CONFIG_MII=y
 CONFIG_MCFUART=y
 CONFIG_WATCHDOG_TIMEOUT_MSECS=5000
-CONFIG_DM_I2C=y
diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig
index 67991b5..ff87a3a 100644
--- a/configs/M5235EVB_defconfig
+++ b/configs/M5235EVB_defconfig
@@ -44,11 +44,8 @@
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.162.1.1"
 CONFIG_SYS_RX_ETH_BUFFER=8
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x300
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=80000
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
@@ -60,4 +57,3 @@
 CONFIG_MII=y
 CONFIG_MCFUART=y
 CONFIG_WATCHDOG_TIMEOUT_MSECS=5000
-CONFIG_DM_I2C=y
diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig
index 7014e2f..af9876d 100644
--- a/configs/M53017EVB_defconfig
+++ b/configs/M53017EVB_defconfig
@@ -24,7 +24,6 @@
 CONFIG_MII_INIT=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_USE_HOSTNAME=y
 CONFIG_HOSTNAME="M53017"
diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig
index 1857cf7..2eb503b 100644
--- a/configs/M5329AFEE_defconfig
+++ b/configs/M5329AFEE_defconfig
@@ -23,7 +23,6 @@
 CONFIG_MII_INIT=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_USE_HOSTNAME=y
 CONFIG_HOSTNAME="M5329EVB"
diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig
index 449ad2a..a9b1472 100644
--- a/configs/M5329BFEE_defconfig
+++ b/configs/M5329BFEE_defconfig
@@ -24,7 +24,6 @@
 CONFIG_MII_INIT=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_USE_HOSTNAME=y
 CONFIG_HOSTNAME="M5329EVB"
diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig
index 05c3b37..4198cf7 100644
--- a/configs/M5373EVB_defconfig
+++ b/configs/M5373EVB_defconfig
@@ -24,7 +24,6 @@
 CONFIG_MII_INIT=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_USE_HOSTNAME=y
 CONFIG_HOSTNAME="M5373EVB"
@@ -40,11 +39,7 @@
 CONFIG_SERVERIP="192.162.1.1"
 CONFIG_SYS_RX_ETH_BUFFER=8
 CONFIG_DM_I2C=y
-CONFIG_DM_RTC=y
 CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x58000
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=80000
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
@@ -57,6 +52,7 @@
 CONFIG_MCFFEC=y
 CONFIG_SYS_UNIFY_CACHE=y
 CONFIG_MII=y
+CONFIG_DM_RTC=y
 CONFIG_MCFRTC=y
 CONFIG_SYS_MCFRTC_BASE=0xFC0A8000
 CONFIG_MCFUART=y
diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig
index f96e9f0..e391e1d 100644
--- a/configs/MCR3000_defconfig
+++ b/configs/MCR3000_defconfig
@@ -4,14 +4,14 @@
 CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="mcr3000"
 CONFIG_SYS_PROMPT="S3K> "
+CONFIG_SYS_CLK_FREQ=132000000
 CONFIG_SYS_LOAD_ADDR=0x200000
 CONFIG_ENV_ADDR=0x4004000
 CONFIG_MPC8xx=y
+# CONFIG_PCI is not set
 CONFIG_TARGET_MCR3000=y
-CONFIG_8xx_GCLK_FREQ=132000000
 CONFIG_CMD_IMMAP=y
 CONFIG_SYS_SIUMCR=0x00600400
-CONFIG_SYS_SYPCR=0xFFFFFF8F
 CONFIG_SYS_TBSCR=0x00C3
 CONFIG_SYS_PISCR=0x0000
 CONFIG_SYS_PLPRCR_BOOL=y
@@ -25,11 +25,13 @@
 CONFIG_SYS_MONITOR_BASE=0x04000000
 CONFIG_BOOTDELAY=5
 CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_FLUSH_STDIN=y
 CONFIG_AUTOBOOT_PROMPT="\nEnter password - autoboot in %d sec...\n"
-CONFIG_AUTOBOOT_DELAY_STR="root"
+CONFIG_AUTOBOOT_ENCRYPTION=y
+CONFIG_AUTOBOOT_STOP_STR_ENABLE=y
+CONFIG_AUTOBOOT_STOP_STR_SHA256="4813494d137e1631bba301d5acab6e7bb7aa74ce1185d456565ef51d737677b2"
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run flashboot"
-CONFIG_BOARD_EARLY_INIT_R=y
 # CONFIG_HWCONFIG is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_HUSH_PARSER=y
@@ -99,7 +101,7 @@
 CONFIG_SYS_MAX_FLASH_SECT=35
 CONFIG_MTD_RAW_NAND=y
 CONFIG_MPC8XX_FEC=y
-# CONFIG_PCI is not set
 CONFIG_DM_SERIAL=y
 CONFIG_WDT=y
+CONFIG_WDT_MPC8xxx_BME=y
 CONFIG_LZMA=y
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 8f3f54c..a402ffa 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -4,6 +4,8 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb"
+CONFIG_DEBUG_UART_BASE=0xe0004500
+CONFIG_DEBUG_UART_CLOCK=333333000
 CONFIG_SYS_CLK_FREQ=66666667
 CONFIG_ENV_ADDR=0xFE080000
 # CONFIG_SYS_PCI_64BIT is not set
@@ -45,7 +47,6 @@
 CONFIG_BAT2_LENGTH_8_MBYTES=y
 CONFIG_BAT2_ACCESS_RW=y
 CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
 CONFIG_BAT2_DCACHE_INHIBITED=y
 CONFIG_BAT2_DCACHE_GUARDED=y
 CONFIG_BAT2_USER_MODE_VALID=y
@@ -55,7 +56,6 @@
 CONFIG_BAT3_BASE=0xF0000000
 CONFIG_BAT3_ACCESS_RW=y
 CONFIG_BAT3_ICACHE_INHIBITED=y
-CONFIG_BAT3_ICACHE_GUARDED=y
 CONFIG_BAT3_DCACHE_INHIBITED=y
 CONFIG_BAT3_DCACHE_GUARDED=y
 CONFIG_BAT3_USER_MODE_VALID=y
@@ -91,7 +91,6 @@
 CONFIG_BAT7_LENGTH_256_MBYTES=y
 CONFIG_BAT7_ACCESS_RW=y
 CONFIG_BAT7_ICACHE_INHIBITED=y
-CONFIG_BAT7_ICACHE_GUARDED=y
 CONFIG_BAT7_DCACHE_INHIBITED=y
 CONFIG_BAT7_DCACHE_GUARDED=y
 CONFIG_BAT7_USER_MODE_VALID=y
@@ -118,6 +117,7 @@
 CONFIG_LCRR_CLKDIV_8=y
 CONFIG_FSL_SERDES=y
 CONFIG_USE_UBOOTPATH=y
+CONFIG_DEBUG_UART=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -185,7 +185,9 @@
 CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_RTC_DS1374=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_FSL=y
diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig
index e77b007..d60eedb 100644
--- a/configs/MSI_Primo81_defconfig
+++ b/configs/MSI_Primo81_defconfig
@@ -6,13 +6,13 @@
 CONFIG_DRAM_CLK=360
 CONFIG_DRAM_ZQ=122
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:768,y:1024,depth:18,pclk_khz:66000,le:56,ri:60,up:30,lo:36,hs:64,vs:50,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_BL_EN="PA25"
 CONFIG_VIDEO_LCD_BL_PWM="PH13"
 CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DLDO1_VOLT=3300
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index b9ccfcf..f0c54e2 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -6,10 +6,11 @@
 CONFIG_DRAM_CLK=672
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH3"
 CONFIG_USB1_VBUS_PIN="PH4"
 CONFIG_USB3_VBUS_PIN="PH5"
 CONFIG_AXP_GPIO=y
 CONFIG_SYS_I2C_SUN8I_RSB=y
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP809_POWER=y
diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig
index 18fa377..3046f45 100644
--- a/configs/Nintendo_NES_Classic_Edition_defconfig
+++ b/configs/Nintendo_NES_Classic_Edition_defconfig
@@ -6,7 +6,6 @@
 CONFIG_DRAM_CLK=600
 CONFIG_DRAM_ZQ=15291
 CONFIG_DRAM_ODT_EN=y
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_AXP_GPIO=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 # CONFIG_CMD_FLASH is not set
@@ -20,6 +19,7 @@
 CONFIG_SYS_NAND_PAGE_SIZE=0x800
 CONFIG_SYS_NAND_OOBSIZE=0x40
 CONFIG_SYS_NAND_MAX_ECCPOS=1664
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_AXP_ELDO2_VOLT=1800
 CONFIG_CONS_INDEX=5
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index e0ffb16..ecbe959 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0x11000000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
@@ -113,7 +114,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index 71e17d9..851f94c 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xEFF40000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
@@ -77,7 +78,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index 0df2a55..3e1c779 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
@@ -98,7 +99,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index 086bfcb..59b7cf0 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -100,7 +101,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index aa8aeda..41ada95 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0x11000000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
@@ -112,7 +113,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index 5807e8b..aad962d 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xEFF40000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
@@ -76,7 +77,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index 30ff3ad..d29294a 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
@@ -97,7 +98,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index d7d8219..d97df4e 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -99,7 +100,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 6e05387..cec50ed 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0x11000000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
@@ -116,7 +117,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index 7328c14..77a469a 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xEFF40000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
@@ -79,7 +80,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index 216e14c..60615df 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
@@ -100,7 +101,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index 35943d1..3256a1c 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -102,7 +103,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index c2c851c..8ee391b 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0x11000000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
@@ -115,7 +116,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index 0f109c5..28639db 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xEFF40000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
@@ -78,7 +79,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index b8e0a92..d8711132 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
@@ -99,7 +100,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index f403e67..3315c9a 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -101,7 +102,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 02f0f3c..686f45d 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0x11000000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
@@ -126,7 +127,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index 84cc6bd..1e88fc0 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
@@ -108,7 +109,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index 427b67c..281afee 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -110,7 +111,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index e2373d0..fd963cd 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xEFF40000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
@@ -88,7 +89,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index e1e6af7..17e1482 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0x11000000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
@@ -125,7 +126,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index d9477f1..1e09d74 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
@@ -107,7 +108,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index f27c9c3..db31ef3 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -109,7 +110,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index ca828ea..68877c5 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xEFF40000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
@@ -87,7 +88,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index 1d364fe..d1b1826 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0x11000000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
@@ -128,7 +129,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index 4dc2457..577b5f8 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
@@ -110,7 +111,6 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index bf6d223..537968d 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -112,7 +113,6 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index 5377aba..5e08f15 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xEFF40000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
@@ -90,7 +91,6 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 7646e90..aafc4a2 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0x11000000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
@@ -131,7 +132,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index 8151259..7d3c90e 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
@@ -113,7 +114,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index 3f106c6..233c03b 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -115,7 +116,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index d266ce8..791c5ff 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xEFF40000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
@@ -93,7 +94,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 11d59d1..922faa7 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0x11000000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
@@ -130,7 +131,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index 9416d93..cf2f086 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
@@ -112,7 +113,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index 74d26f1..6428e80 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0x100000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -114,7 +115,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index 4d5569c..e1dd5e9 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xEFF40000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
@@ -92,7 +93,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index bf3365a..411eb50 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xFFF40000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0xE0000
 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
@@ -90,7 +91,6 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_ELBC=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHYLIB_10G=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index 69f30d4..7a39414 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xFFF40000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xCF400
 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
@@ -85,7 +86,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHYLIB_10G=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index c2dc0f2..99ef9d0 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xFFF40000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -87,7 +88,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHYLIB_10G=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 306432e..c535217 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xEFF40000
 CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
@@ -82,7 +83,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHYLIB_10G=y
diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index 5116fab..5642e52 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -9,7 +9,6 @@
 CONFIG_DRAM_ODT_EN=y
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH11"
 CONFIG_USB1_VBUS_PIN="PD24"
 CONFIG_AXP_GPIO=y
@@ -19,6 +18,7 @@
 CONFIG_PHY_REALTEK=y
 CONFIG_SUN8I_EMAC=y
 CONFIG_INITIAL_USB_SCAN_DELAY=500
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DCDC5_VOLT=1200
 CONFIG_AXP_DLDO3_VOLT=3300
 CONFIG_AXP_SW_ON=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index bedea01..1913ccd 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0xa00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
@@ -117,7 +118,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index f06bb02..bd0de9f 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0xa00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
@@ -111,7 +112,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 4f91dce..83fe210 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_LEN=0xa00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -114,7 +115,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index c9d771e..1b51529 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xEFF40000
 CONFIG_SYS_MALLOC_LEN=0xa00000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
@@ -86,7 +87,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index a55797e..3b3f596 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -2,6 +2,7 @@
 CONFIG_TEXT_BASE=0x30000000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x180000
 CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
@@ -115,7 +116,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_REALTEK=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index 2f5a1a3..7c756e9 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -2,6 +2,7 @@
 CONFIG_TEXT_BASE=0x30000000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
@@ -109,7 +110,6 @@
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_REALTEK=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index afce81b..c486558 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -2,6 +2,7 @@
 CONFIG_TEXT_BASE=0x30000000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -112,7 +113,6 @@
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_REALTEK=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 29b240f..c325f15 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xEFF40000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
@@ -84,7 +85,6 @@
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_REALTEK=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index ca960d3..c54a1f7 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -2,6 +2,7 @@
 CONFIG_TEXT_BASE=0x00200000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x140000
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
@@ -126,7 +127,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index eba73ee..97d3946 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -2,6 +2,7 @@
 CONFIG_TEXT_BASE=0x00200000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
@@ -120,7 +121,6 @@
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index ae98a35..70c2104 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xEFF40000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_MPC85xx=y
@@ -94,7 +95,6 @@
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 76a1e583..d176d3b 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -2,6 +2,7 @@
 CONFIG_TEXT_BASE=0x00200000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -123,7 +124,6 @@
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index fe440a4..9fd0daf 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xFFF40000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_ADDR=0xFFE20000
@@ -83,7 +84,6 @@
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index f4f90d5..330bed0 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xEFF40000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
@@ -95,7 +96,6 @@
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 18baf56..667bdc4 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -2,6 +2,7 @@
 CONFIG_TEXT_BASE=0x00200000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
@@ -121,7 +122,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index df98e33..237ddba 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -2,6 +2,7 @@
 CONFIG_TEXT_BASE=0x00200000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
@@ -115,7 +116,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index efa48af..2a66d77 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -2,6 +2,7 @@
 CONFIG_TEXT_BASE=0x00200000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -118,7 +119,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 8e07b2a..f2086b5 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xEFF40000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
@@ -90,7 +91,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig
index 69bebfa..3cc1391 100644
--- a/configs/T2080RDB_revD_NAND_defconfig
+++ b/configs/T2080RDB_revD_NAND_defconfig
@@ -2,6 +2,7 @@
 CONFIG_TEXT_BASE=0x00200000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
@@ -122,7 +123,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig
index 179fc63..8b0ce62 100644
--- a/configs/T2080RDB_revD_SDCARD_defconfig
+++ b/configs/T2080RDB_revD_SDCARD_defconfig
@@ -2,6 +2,7 @@
 CONFIG_TEXT_BASE=0x00200000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
@@ -116,7 +117,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig
index 1d8a6b5..644932a 100644
--- a/configs/T2080RDB_revD_SPIFLASH_defconfig
+++ b/configs/T2080RDB_revD_SPIFLASH_defconfig
@@ -2,6 +2,7 @@
 CONFIG_TEXT_BASE=0x00200000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -119,7 +120,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig
index a1332a9..eeb744b 100644
--- a/configs/T2080RDB_revD_defconfig
+++ b/configs/T2080RDB_revD_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xEFF40000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
@@ -91,7 +92,6 @@
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index d906035..0d994f8 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -2,6 +2,7 @@
 CONFIG_TEXT_BASE=0x00200000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
@@ -104,7 +105,6 @@
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHYLIB_10G=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index d2b270d..22872d4 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xEFF40000
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
@@ -79,7 +80,6 @@
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHYLIB_10G=y
diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig
index 101ce57..40aeb66 100644
--- a/configs/Wexler_TAB7200_defconfig
+++ b/configs/Wexler_TAB7200_defconfig
@@ -5,7 +5,6 @@
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH4"
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
@@ -17,6 +16,7 @@
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
index 4f2290c..9b13659 100644
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -7,7 +7,6 @@
 CONFIG_MMC1_PINS_PH=y
 CONFIG_MMC_SUNXI_SLOT_EXTRA=1
 CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:63000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -21,4 +20,5 @@
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig
index b33c825..de69ebe 100644
--- a/configs/Yones_Toptech_BS1078_V2_defconfig
+++ b/configs/Yones_Toptech_BS1078_V2_defconfig
@@ -6,7 +6,6 @@
 CONFIG_DRAM_CLK=420
 CONFIG_DRAM_ZQ=251
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PA15"
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:70000,le:120,ri:180,up:17,lo:15,hs:20,vs:3,sync:3,vmode:0"
@@ -15,5 +14,6 @@
 CONFIG_VIDEO_LCD_BL_PWM="PH13"
 CONFIG_VIDEO_LCD_PANEL_LVDS=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/alt_defconfig b/configs/alt_defconfig
index 5852a34..6575c4c 100644
--- a/configs/alt_defconfig
+++ b/configs/alt_defconfig
@@ -29,6 +29,7 @@
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x50000000
 CONFIG_ENV_ADDR=0xC0000
+CONFIG_PCI=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
@@ -89,7 +90,6 @@
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
 CONFIG_SH_ETHER=y
-CONFIG_PCI=y
 CONFIG_PCI_RCAR_GEN2=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index a116c4c..c42d2a0 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -6,6 +6,7 @@
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
 CONFIG_AM33XX=y
 CONFIG_CLOCK_SYNTHESIZER=y
@@ -66,7 +67,6 @@
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_SMSC=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 84fb0c2..ffeeb85 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
 CONFIG_AM33XX=y
 CONFIG_CLOCK_SYNTHESIZER=y
@@ -91,7 +92,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHY_ATHEROS=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 3e70aca..09d5e80 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -4,11 +4,13 @@
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
 CONFIG_AM33XX=y
 CONFIG_CLOCK_SYNTHESIZER=y
+# CONFIG_OF_LIBFDT_OVERLAY is not set
 # CONFIG_SPL_MMC is not set
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -83,7 +85,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHY_ATHEROS=y
@@ -114,4 +115,3 @@
 CONFIG_DYNAMIC_CRC_TABLE=y
 CONFIG_RSA=y
 CONFIG_LZO=y
-# CONFIG_OF_LIBFDT_OVERLAY is not set
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index db7838f..1e93439 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -5,10 +5,12 @@
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
 CONFIG_SPL_TEXT_BASE=0x40300350
 CONFIG_AM33XX=y
 CONFIG_CLOCK_SYNTHESIZER=y
+# CONFIG_OF_LIBFDT_OVERLAY is not set
 CONFIG_SPL=y
 CONFIG_TIMESTAMP=y
 CONFIG_SPL_LOAD_FIT=y
@@ -70,7 +72,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_SMSC=y
@@ -102,4 +103,3 @@
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_RSA=y
 CONFIG_LZO=y
-# CONFIG_OF_LIBFDT_OVERLAY is not set
diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index 14f779d..6e4d327 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -5,10 +5,12 @@
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
 CONFIG_SPL_TEXT_BASE=0x40301950
 CONFIG_AM33XX=y
 CONFIG_CLOCK_SYNTHESIZER=y
+# CONFIG_OF_LIBFDT_OVERLAY is not set
 # CONFIG_SPL_MMC is not set
 CONFIG_SPL=y
 # CONFIG_SPL_FS_FAT is not set
@@ -71,7 +73,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_SMSC=y
@@ -103,4 +104,3 @@
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_RSA=y
 CONFIG_LZO=y
-# CONFIG_OF_LIBFDT_OVERLAY is not set
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 6d50422..34525d6 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -5,6 +5,7 @@
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
+CONFIG_SF_DEFAULT_SPEED=48000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
@@ -79,7 +80,6 @@
 CONFIG_SYS_NAND_OOBSIZE=0xe0
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
-CONFIG_SF_DEFAULT_SPEED=48000000
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_PHY_GIGE=y
 CONFIG_MII=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index ab02b49..8604c88 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
+CONFIG_SF_DEFAULT_SPEED=48000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x110000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -49,7 +50,6 @@
 CONFIG_DFU_SF=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_MMC_OMAP_HS=y
-CONFIG_SF_DEFAULT_SPEED=48000000
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig
index a8c740e..9cafe9c 100644
--- a/configs/am43xx_evm_rtconly_defconfig
+++ b/configs/am43xx_evm_rtconly_defconfig
@@ -5,6 +5,7 @@
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
+CONFIG_SF_DEFAULT_SPEED=48000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
@@ -66,7 +67,6 @@
 CONFIG_SYS_NAND_OOBSIZE=0xe0
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
-CONFIG_SF_DEFAULT_SPEED=48000000
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_PHY_GIGE=y
 CONFIG_MII=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 6a607ad..64ecd92 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -4,6 +4,7 @@
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
+CONFIG_SF_DEFAULT_SPEED=48000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
@@ -82,7 +83,6 @@
 CONFIG_SYS_NAND_OOBSIZE=0xe0
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
-CONFIG_SF_DEFAULT_SPEED=48000000
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_PHY_GIGE=y
 CONFIG_MII=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index 4ab32d2..6715a25 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -6,6 +6,7 @@
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
+CONFIG_SF_DEFAULT_SPEED=48000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
@@ -77,7 +78,6 @@
 CONFIG_SYS_NAND_OOBSIZE=0xe0
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
-CONFIG_SF_DEFAULT_SPEED=48000000
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_PHY_GIGE=y
 CONFIG_MII=y
diff --git a/configs/am43xx_hs_evm_qspi_defconfig b/configs/am43xx_hs_evm_qspi_defconfig
index 2a0859b..ad6ce2b 100644
--- a/configs/am43xx_hs_evm_qspi_defconfig
+++ b/configs/am43xx_hs_evm_qspi_defconfig
@@ -5,6 +5,7 @@
 CONFIG_TI_SECURE_DEVICE=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
+CONFIG_SF_DEFAULT_SPEED=48000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x110000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -51,7 +52,6 @@
 CONFIG_DFU_SF=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_MMC_OMAP_HS=y
-CONFIG_SF_DEFAULT_SPEED=48000000
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index e61be98..6db5922 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -4,6 +4,7 @@
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037ff00
+CONFIG_SF_DEFAULT_SPEED=76800000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="am572x-idk"
@@ -94,7 +95,6 @@
 CONFIG_HSMMC2_8BIT=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=76800000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 32b68fd..1b03848 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -5,6 +5,7 @@
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037ff00
+CONFIG_SF_DEFAULT_SPEED=76800000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="am572x-idk"
@@ -91,7 +92,6 @@
 CONFIG_HSMMC2_8BIT=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=76800000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index 9d8ab5e..fe71738 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -5,6 +5,7 @@
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037ff00
+CONFIG_SF_DEFAULT_SPEED=76800000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
@@ -90,7 +91,6 @@
 CONFIG_HSMMC2_8BIT=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=76800000
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index 46a95a6..41fa6f3 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -12,6 +12,7 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
 CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-sk"
 CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -74,4 +75,3 @@
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_TI_SCI=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig
index e5bee14..05c30cb 100644
--- a/configs/am62ax_evm_r5_defconfig
+++ b/configs/am62ax_evm_r5_defconfig
@@ -24,7 +24,6 @@
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
-CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
 CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig
index cc9c8ea..a2cd4f7 100644
--- a/configs/am62x_evm_a53_defconfig
+++ b/configs/am62x_evm_a53_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -9,9 +10,11 @@
 CONFIG_TARGET_AM625_A53_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
+CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am625-sk"
 CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -68,7 +71,6 @@
 CONFIG_SPL_MMC_SDHCI_ADMA=y
 CONFIG_MMC_SDHCI_AM654=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_SOFT_RESET=y
 CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
@@ -97,4 +99,3 @@
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_TI_SCI=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig
index 44a9130..642600f 100644
--- a/configs/am62x_evm_r5_defconfig
+++ b/configs/am62x_evm_r5_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
 CONFIG_SYS_MALLOC_LEN=0x08000000
 CONFIG_SYS_MALLOC_F_LEN=0x9000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -9,6 +10,8 @@
 CONFIG_TARGET_AM625_R5_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0
+CONFIG_SF_DEFAULT_SPEED=25000000
+CONFIG_SF_DEFAULT_MODE=0
 CONFIG_ENV_SIZE=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
@@ -95,8 +98,6 @@
 CONFIG_SPL_MMC_SDHCI_ADMA=y
 CONFIG_MMC_SDHCI_AM654=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_SOFT_RESET=y
 CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index 6543ae7..4589624 100644
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@@ -18,6 +18,7 @@
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am642-evm"
 CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -165,4 +166,3 @@
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig
index b75cae6..bb705a1 100644
--- a/configs/am64x_evm_r5_defconfig
+++ b/configs/am64x_evm_r5_defconfig
@@ -169,3 +169,6 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index bddd94c..f294a45 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -16,6 +16,7 @@
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
 CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -27,10 +28,11 @@
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 # CONFIG_PSCI_RESET is not set
+CONFIG_PCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
 CONFIG_LOGLEVEL=7
@@ -133,7 +135,6 @@
 CONFIG_E1000=y
 CONFIG_CMD_E1000=y
 CONFIG_TI_AM65_CPSW_NUSS=y
-CONFIG_PCI=y
 CONFIG_PCI_KEYSTONE=y
 CONFIG_PHY=y
 CONFIG_SPL_PHY=y
@@ -177,5 +178,4 @@
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6162
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_PHANDLE_CHECK_SEQ=y
diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig
index 898403a..e0277d4 100644
--- a/configs/am65x_hs_evm_a53_defconfig
+++ b/configs/am65x_hs_evm_a53_defconfig
@@ -17,6 +17,7 @@
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
 CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -28,9 +29,10 @@
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 # CONFIG_PSCI_RESET is not set
+CONFIG_PCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_fit_${boot}; run get_overlaystring; run run_fit"
 CONFIG_LOGLEVEL=7
@@ -120,7 +122,6 @@
 CONFIG_E1000=y
 CONFIG_CMD_E1000=y
 CONFIG_TI_AM65_CPSW_NUSS=y
-CONFIG_PCI=y
 CONFIG_PCI_KEYSTONE=y
 CONFIG_PHY=y
 CONFIG_AM654_PHY=y
@@ -156,4 +157,3 @@
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6162
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig
index d9a4658..b726ee3 100644
--- a/configs/apalis-imx8_defconfig
+++ b/configs/apalis-imx8_defconfig
@@ -14,6 +14,7 @@
 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
 CONFIG_TARGET_APALIS_IMX8=y
 CONFIG_SYS_PROMPT="Apalis iMX8 # "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_LOAD_ADDR=0x95400000
 CONFIG_SYS_MEMTEST_START=0x88000000
 CONFIG_SYS_MEMTEST_END=0x89000000
@@ -89,5 +90,4 @@
 CONFIG_FSL_LPUART=y
 CONFIG_DM_THERMAL=y
 CONFIG_IMX_SCU_THERMAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig
index e23a31e..36d28a2 100644
--- a/configs/apalis-tk1_defconfig
+++ b/configs/apalis-tk1_defconfig
@@ -9,11 +9,13 @@
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-apalis"
 CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_PROMPT="Apalis TK1 # "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_STACK=0x800ffffc
 CONFIG_TEGRA124=y
 CONFIG_TARGET_APALIS_TK1=y
 CONFIG_TEGRA_GPU=y
 CONFIG_SYS_LOAD_ADDR=0x81000000
+CONFIG_PCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_SYSTEM_SETUP=y
@@ -66,7 +68,6 @@
 CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK=y
 CONFIG_E1000=y
 CONFIG_E1000_NO_NVM=y
-CONFIG_PCI=y
 CONFIG_PCI_TEGRA=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_AS3722=y
@@ -82,4 +83,3 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 231c933..e9e8736 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -18,6 +18,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="imx6q-apalis-eval"
 CONFIG_SPL_TEXT_BASE=0x00908000
 CONFIG_SYS_PROMPT="Apalis iMX6 # "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL=y
@@ -121,4 +122,3 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index 5a765ad..5165525 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -9,10 +9,12 @@
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis"
 CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_PROMPT="Apalis T30 # "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_STACK=0x800ffffc
 CONFIG_TEGRA30=y
 CONFIG_TARGET_APALIS_T30=y
 CONFIG_SYS_LOAD_ADDR=0x81000000
+CONFIG_PCI=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_CONSOLE_MUX=y
 CONFIG_SYS_STDIO_DEREGISTER=y
@@ -51,7 +53,6 @@
 CONFIG_SYS_I2C_TEGRA=y
 CONFIG_E1000=y
 CONFIG_E1000_NO_NVM=y
-CONFIG_PCI=y
 CONFIG_PCI_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
@@ -63,4 +64,3 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig
index bd7947b..db68b21 100644
--- a/configs/aristainetos2c_defconfig
+++ b/configs/aristainetos2c_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TEXT_BASE=0x17800000
 CONFIG_SYS_MALLOC_F_LEN=0x13000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0xD0000
 CONFIG_MX6DL=y
 CONFIG_TARGET_ARISTAINETOS2C=y
@@ -85,7 +86,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_MTD_UBI_FASTMAP=y
diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig
index 3fb6e71..d369505 100644
--- a/configs/aristainetos2ccslb_defconfig
+++ b/configs/aristainetos2ccslb_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TEXT_BASE=0x17800000
 CONFIG_SYS_MALLOC_F_LEN=0x13000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0xD0000
 CONFIG_MX6DL=y
 CONFIG_TARGET_ARISTAINETOS2CCSLB=y
@@ -85,7 +86,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_MTD_UBI_FASTMAP=y
diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig
index f12859b..be6ab46 100644
--- a/configs/astro_mcf5373l_defconfig
+++ b/configs/astro_mcf5373l_defconfig
@@ -26,7 +26,6 @@
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
 CONFIG_CMD_JFFS2=y
 # CONFIG_NET is not set
 CONFIG_FPGA_ALTERA=y
diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig
index 60b1810..517ff16 100644
--- a/configs/at91sam9n12ek_mmc_defconfig
+++ b/configs/at91sam9n12ek_mmc_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x303f00
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek"
@@ -50,7 +51,6 @@
 CONFIG_NAND_ATMEL=y
 CONFIG_ATMEL_NAND_HW_PMECC=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_KS8851_MLL=y
 CONFIG_PINCTRL=y
diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig
index c84f747..e54a51d 100644
--- a/configs/at91sam9n12ek_nandflash_defconfig
+++ b/configs/at91sam9n12ek_nandflash_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x303f00
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek"
 CONFIG_SYS_PROMPT="U-Boot> "
@@ -50,7 +51,6 @@
 CONFIG_NAND_ATMEL=y
 CONFIG_ATMEL_NAND_HW_PMECC=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_KS8851_MLL=y
 CONFIG_PINCTRL=y
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index abe8e23..839c400 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x303f00
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0x5000
 CONFIG_ENV_SECT_SIZE=0x1000
@@ -52,7 +53,6 @@
 CONFIG_NAND_ATMEL=y
 CONFIG_ATMEL_NAND_HW_PMECC=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_KS8851_MLL=y
 CONFIG_PINCTRL=y
diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig
index d213c02..eb4f852 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -8,6 +8,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x4200
 CONFIG_ENV_OFFSET=0x4200
 CONFIG_ENV_SECT_SIZE=0x210
@@ -57,7 +58,6 @@
 CONFIG_NAND_ATMEL=y
 CONFIG_ATMEL_NAND_HW_PMECC=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig
index 5e5628f..a3ca030 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -8,6 +8,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
@@ -54,7 +55,6 @@
 CONFIG_NAND_ATMEL=y
 CONFIG_ATMEL_NAND_HW_PMECC=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig
index f73a65f..a1ee9dc 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -8,6 +8,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
 CONFIG_SYS_PROMPT="U-Boot> "
@@ -56,7 +57,6 @@
 CONFIG_NAND_ATMEL=y
 CONFIG_ATMEL_NAND_HW_PMECC=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index 4c4e2fc..d226fcc 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -8,6 +8,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0x5000
 CONFIG_ENV_SECT_SIZE=0x1000
@@ -58,7 +59,6 @@
 CONFIG_NAND_ATMEL=y
 CONFIG_ATMEL_NAND_HW_PMECC=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
diff --git a/configs/bananapi-cm4-cm4io_defconfig b/configs/bananapi-cm4-cm4io_defconfig
index 0801b9d..bb43cc4 100644
--- a/configs/bananapi-cm4-cm4io_defconfig
+++ b/configs/bananapi-cm4-cm4io_defconfig
@@ -2,17 +2,20 @@
 CONFIG_ARCH_MESON=y
 CONFIG_TEXT_BASE=0x01000000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-bananapi-cm4-cm4io"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING="bpi-cm4io"
 CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
 CONFIG_REMAKE_ELF=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_DISPLAY_CPUINFO is not set
@@ -40,7 +43,6 @@
 CONFIG_DM_MDIO_MUX=y
 CONFIG_ETH_DESIGNWARE_MESON8B=y
 CONFIG_MDIO_MUX_MESON_G12A=y
-CONFIG_PCI=y
 CONFIG_PCIE_DW_MESON=y
 CONFIG_MESON_G12A_USB_PHY=y
 CONFIG_PINCTRL=y
@@ -49,7 +51,6 @@
 CONFIG_MESON_EE_POWER_DOMAIN=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_MESON_SERIAL=y
@@ -81,4 +82,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/bananapi-m2-pro_defconfig b/configs/bananapi-m2-pro_defconfig
index 28b603f..4f8cec9 100644
--- a/configs/bananapi-m2-pro_defconfig
+++ b/configs/bananapi-m2-pro_defconfig
@@ -2,17 +2,19 @@
 CONFIG_ARCH_MESON=y
 CONFIG_TEXT_BASE=0x01000000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-bananapi-m2-pro"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING="bpi-m2-pro"
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_DEBUG_UART=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
 CONFIG_REMAKE_ELF=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_DISPLAY_CPUINFO is not set
@@ -44,7 +46,6 @@
 CONFIG_MESON_EE_POWER_DOMAIN=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_MESON_SERIAL=y
@@ -73,4 +74,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/bananapi-m2s_defconfig b/configs/bananapi-m2s_defconfig
index 3109e0c..3dd8ddc 100644
--- a/configs/bananapi-m2s_defconfig
+++ b/configs/bananapi-m2s_defconfig
@@ -2,18 +2,21 @@
 CONFIG_ARCH_MESON=y
 CONFIG_TEXT_BASE=0x01000000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-bananapi-m2s"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" bpi-m2s"
 CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
 CONFIG_REMAKE_ELF=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_DISPLAY_CPUINFO is not set
@@ -33,14 +36,12 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ADC=y
 CONFIG_SARADC_MESON=y
-CONFIG_AHCI_PCI=y
 CONFIG_MMC_MESON_GX=y
 CONFIG_PHY_REALTEK=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
 CONFIG_ETH_DESIGNWARE_MESON8B=y
 CONFIG_MDIO_MUX_MESON_G12A=y
-CONFIG_PCI=y
 CONFIG_PCIE_DW_MESON=y
 CONFIG_MESON_G12A_USB_PHY=y
 CONFIG_PINCTRL=y
@@ -50,7 +51,6 @@
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_MESON_SERIAL=y
@@ -79,4 +79,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/bananapi-m5_defconfig b/configs/bananapi-m5_defconfig
index 94b27d5..696d2fc 100644
--- a/configs/bananapi-m5_defconfig
+++ b/configs/bananapi-m5_defconfig
@@ -7,6 +7,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-bananapi-m5"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
@@ -74,4 +75,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/bcmns_defconfig b/configs/bcmns_defconfig
new file mode 100644
index 0000000..02e2fbe
--- /dev/null
+++ b/configs/bcmns_defconfig
@@ -0,0 +1,41 @@
+CONFIG_ARM=y
+CONFIG_TARGET_BCMNS=y
+CONFIG_TEXT_BASE=0x00008000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="ns-board"
+CONFIG_IDENT_STRING="Broadcom Northstar"
+CONFIG_SYS_LOAD_ADDR=0x00008000
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x00100000
+# CONFIG_BOOTSTD is not set
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Boot Northstar system in %d seconds\n"
+CONFIG_BOOTDELAY=1
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run bootcmd_dlink_dir8xxl"
+CONFIG_SYS_PROMPT="northstar> "
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_CMD_SEAMA=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_USE_HOSTNAME=y
+CONFIG_HOSTNAME="NS"
+CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_CMD_NAND=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+# CONFIG_NET is not set
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index 0a782ad..3820a33 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -5,6 +5,7 @@
 CONFIG_TEXT_BASE=0x80110000
 CONFIG_SYS_MALLOC_LEN=0x2500000
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-beaver"
@@ -14,6 +15,7 @@
 CONFIG_TEGRA30=y
 CONFIG_TARGET_BEAVER=y
 CONFIG_SYS_LOAD_ADDR=0x81000000
+CONFIG_PCI=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_CONSOLE_MUX=y
 CONFIG_SYS_STDIO_DEREGISTER=y
@@ -51,10 +53,8 @@
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
 CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_RTL8169=y
-CONFIG_PCI=y
 CONFIG_PCI_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_TEGRA20_SLINK=y
diff --git a/configs/beelink-gsking-x_defconfig b/configs/beelink-gsking-x_defconfig
index bcae9fe..c022097 100644
--- a/configs/beelink-gsking-x_defconfig
+++ b/configs/beelink-gsking-x_defconfig
@@ -8,6 +8,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-gsking-x"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
@@ -71,4 +72,3 @@
 CONFIG_VIDEO_DT_SIMPLEFB=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/beelink-gt1-ultimate_defconfig b/configs/beelink-gt1-ultimate_defconfig
index 4ec76cb..c0d22c4 100644
--- a/configs/beelink-gt1-ultimate_defconfig
+++ b/configs/beelink-gt1-ultimate_defconfig
@@ -7,6 +7,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-gt1-ultimate"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_GXM=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
@@ -75,4 +76,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/beelink-gtking_defconfig b/configs/beelink-gtking_defconfig
index 1f1fda6..42e1ba6 100644
--- a/configs/beelink-gtking_defconfig
+++ b/configs/beelink-gtking_defconfig
@@ -8,6 +8,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-gtking"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
@@ -71,4 +72,3 @@
 CONFIG_VIDEO_DT_SIMPLEFB=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/beelink-gtkingpro_defconfig b/configs/beelink-gtkingpro_defconfig
index 9962c72..a371332 100644
--- a/configs/beelink-gtkingpro_defconfig
+++ b/configs/beelink-gtkingpro_defconfig
@@ -8,6 +8,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-gtking-pro"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
@@ -71,4 +72,3 @@
 CONFIG_VIDEO_DT_SIMPLEFB=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig
index 66adeac..95f0c30 100644
--- a/configs/bk4r1_defconfig
+++ b/configs/bk4r1_defconfig
@@ -18,6 +18,7 @@
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_SYS_MEMTEST_START=0x80010000
 CONFIG_SYS_MEMTEST_END=0x87c00000
+CONFIG_LTO=y
 CONFIG_HAS_BOARD_SIZE_LIMIT=y
 CONFIG_BOARD_SIZE_LIMIT=520192
 CONFIG_FIT=y
diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig
index 983c558..7e296b7 100644
--- a/configs/blanche_defconfig
+++ b/configs/blanche_defconfig
@@ -18,6 +18,7 @@
 CONFIG_TARGET_BLANCHE=y
 CONFIG_SYS_LOAD_ADDR=0x50000000
 CONFIG_ENV_ADDR=0x40000
+CONFIG_PCI=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
@@ -65,7 +66,6 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SMC911X=y
-CONFIG_PCI=y
 CONFIG_PCI_RCAR_GEN2=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
diff --git a/configs/boston32r2_defconfig b/configs/boston32r2_defconfig
index 5368b09..5a8dc39 100644
--- a/configs/boston32r2_defconfig
+++ b/configs/boston32r2_defconfig
@@ -13,6 +13,7 @@
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
+CONFIG_PCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x90000000
 CONFIG_FIT=y
@@ -50,7 +51,6 @@
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_PCH_GBE=y
-CONFIG_PCI=y
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y
diff --git a/configs/boston32r2el_defconfig b/configs/boston32r2el_defconfig
index dc951ad..ccc8360 100644
--- a/configs/boston32r2el_defconfig
+++ b/configs/boston32r2el_defconfig
@@ -13,6 +13,7 @@
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
+CONFIG_PCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x90000000
 CONFIG_SYS_LITTLE_ENDIAN=y
@@ -51,7 +52,6 @@
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_PCH_GBE=y
-CONFIG_PCI=y
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y
diff --git a/configs/boston32r6_defconfig b/configs/boston32r6_defconfig
index 1e46447..fe7b280 100644
--- a/configs/boston32r6_defconfig
+++ b/configs/boston32r6_defconfig
@@ -14,6 +14,7 @@
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
+CONFIG_PCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x90000000
 CONFIG_FIT=y
@@ -51,7 +52,6 @@
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_PCH_GBE=y
-CONFIG_PCI=y
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y
diff --git a/configs/boston32r6el_defconfig b/configs/boston32r6el_defconfig
index 2043d4c..fc741aa 100644
--- a/configs/boston32r6el_defconfig
+++ b/configs/boston32r6el_defconfig
@@ -14,6 +14,7 @@
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
+CONFIG_PCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x90000000
 CONFIG_SYS_LITTLE_ENDIAN=y
@@ -52,7 +53,6 @@
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_PCH_GBE=y
-CONFIG_PCI=y
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y
diff --git a/configs/boston64r2_defconfig b/configs/boston64r2_defconfig
index d4de87f..41b8759 100644
--- a/configs/boston64r2_defconfig
+++ b/configs/boston64r2_defconfig
@@ -14,6 +14,7 @@
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
+CONFIG_PCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x90000000
 CONFIG_FIT=y
@@ -51,7 +52,6 @@
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_PCH_GBE=y
-CONFIG_PCI=y
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y
diff --git a/configs/boston64r2el_defconfig b/configs/boston64r2el_defconfig
index 8b1a95c..3afc90b 100644
--- a/configs/boston64r2el_defconfig
+++ b/configs/boston64r2el_defconfig
@@ -14,6 +14,7 @@
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
+CONFIG_PCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x90000000
 CONFIG_SYS_LITTLE_ENDIAN=y
@@ -52,7 +53,6 @@
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_PCH_GBE=y
-CONFIG_PCI=y
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y
diff --git a/configs/boston64r6_defconfig b/configs/boston64r6_defconfig
index 22f890a..da8cded 100644
--- a/configs/boston64r6_defconfig
+++ b/configs/boston64r6_defconfig
@@ -14,6 +14,7 @@
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
+CONFIG_PCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x90000000
 CONFIG_FIT=y
@@ -51,7 +52,6 @@
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_PCH_GBE=y
-CONFIG_PCI=y
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y
diff --git a/configs/boston64r6el_defconfig b/configs/boston64r6el_defconfig
index b2ec9c9..a5b72de 100644
--- a/configs/boston64r6el_defconfig
+++ b/configs/boston64r6el_defconfig
@@ -14,6 +14,7 @@
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
+CONFIG_PCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x90000000
 CONFIG_SYS_LITTLE_ENDIAN=y
@@ -52,7 +53,6 @@
 CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_PCH_GBE=y
-CONFIG_PCI=y
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index 0e0de73..2c9b066 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-mmc"
 CONFIG_AM33XX=y
 CONFIG_TARGET_BRPPT1=y
+# CONFIG_OF_LIBFDT_OVERLAY is not set
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL=y
@@ -111,5 +112,4 @@
 CONFIG_USB_GADGET=y
 CONFIG_FAT_WRITE=y
 CONFIG_LZO=y
-# CONFIG_OF_LIBFDT_OVERLAY is not set
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig
index fcc5e47..1e55ed7 100644
--- a/configs/brsmarc1_defconfig
+++ b/configs/brsmarc1_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x20000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -102,7 +103,6 @@
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig
index 49663eb..1c437e9 100644
--- a/configs/brxre1_defconfig
+++ b/configs/brxre1_defconfig
@@ -13,6 +13,7 @@
 CONFIG_AM33XX=y
 CONFIG_SYS_MPUCLK=1000
 CONFIG_TARGET_BRXRE1=y
+# CONFIG_OF_LIBFDT_OVERLAY is not set
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
@@ -100,5 +101,4 @@
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_SPL_TINY_MEMSET=y
-# CONFIG_OF_LIBFDT_OVERLAY is not set
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index 5435f0d..00fea793 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -4,6 +4,7 @@
 CONFIG_ARCH_TEGRA=y
 CONFIG_TEXT_BASE=0x80110000
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-cardhu"
@@ -13,6 +14,7 @@
 CONFIG_TEGRA30=y
 CONFIG_TARGET_CARDHU=y
 CONFIG_SYS_LOAD_ADDR=0x81000000
+CONFIG_PCI=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_CONSOLE_MUX=y
 CONFIG_SYS_STDIO_DEREGISTER=y
@@ -42,10 +44,8 @@
 CONFIG_SYS_MMC_ENV_PART=2
 CONFIG_SPL_DM=y
 CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_RTL8169=y
-CONFIG_PCI=y
 CONFIG_PCI_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_TEGRA20_SLINK=y
diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig
index 8d9351e..c00e6be 100644
--- a/configs/cei-tk1-som_defconfig
+++ b/configs/cei-tk1-som_defconfig
@@ -5,6 +5,7 @@
 CONFIG_TEXT_BASE=0x80110000
 CONFIG_SYS_MALLOC_LEN=0x2500000
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-cei-tk1-som"
@@ -17,6 +18,7 @@
 CONFIG_TEGRA_GPU=y
 CONFIG_ARMV7_PSCI_0_1=y
 CONFIG_SYS_LOAD_ADDR=0x81000000
+CONFIG_PCI=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_CONSOLE_MUX=y
 CONFIG_SYS_STDIO_DEREGISTER=y
@@ -53,10 +55,8 @@
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
 CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_RTL8169=y
-CONFIG_PCI=y
 CONFIG_PCI_TEGRA=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_AS3722=y
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index 771d7a8..f7b0bef 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
 CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_ROCKCHIP_RK3288=y
@@ -79,7 +80,6 @@
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
 CONFIG_SF_DEFAULT_BUS=2
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
index 5727ba1..dd6d406 100644
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob"
 CONFIG_SPL_TEXT_BASE=0xff8c2000
@@ -76,7 +77,6 @@
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 649a8ea..d649556 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry"
 CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_DM_RESET=y
@@ -82,7 +83,6 @@
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
 CONFIG_SF_DEFAULT_BUS=2
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig
index bc0e89d..3d2642f 100644
--- a/configs/chromebook_kevin_defconfig
+++ b/configs/chromebook_kevin_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-kevin"
 CONFIG_SPL_TEXT_BASE=0xff8c2000
@@ -77,7 +78,6 @@
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index bda3775..f035ddc 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
 CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_ROCKCHIP_RK3288=y
@@ -81,7 +82,6 @@
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
 CONFIG_SF_DEFAULT_BUS=2
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
index 13c0761..197e41d 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
 CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_ROCKCHIP_RK3288=y
@@ -80,7 +81,6 @@
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
 CONFIG_SF_DEFAULT_BUS=2
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig
index d1a044e..d4e70b2 100644
--- a/configs/cl-som-imx7_defconfig
+++ b/configs/cl-som-imx7_defconfig
@@ -5,6 +5,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -82,7 +83,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index 8cd35f9..deb8c25 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -18,6 +18,7 @@
 CONFIG_DEBUG_UART_BASE=0xf1012000
 CONFIG_DEBUG_UART_CLOCK=250000000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
@@ -46,7 +47,6 @@
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_MIN_ENTRIES=128
 CONFIG_ARP_TIMEOUT=200
@@ -59,7 +59,6 @@
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_I2C_EEPROM=y
 CONFIG_SPL_I2C_EEPROM=y
-CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_MV=y
@@ -72,7 +71,6 @@
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_MVMDIO=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SCSI=y
 CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig
index 2802751..7a49b44 100644
--- a/configs/clearfog_gt_8k_defconfig
+++ b/configs/clearfog_gt_8k_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEBUG_UART_BASE=0xf0512000
 CONFIG_DEBUG_UART_CLOCK=200000000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -23,7 +24,6 @@
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_BOOTM_LEN=0x800000
@@ -37,7 +37,6 @@
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MAC_PARTITION=y
@@ -64,7 +63,6 @@
 CONFIG_E1000=y
 CONFIG_MVPP2=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_DW_MVEBU=y
 CONFIG_PHY=y
 CONFIG_MVEBU_COMPHY_SUPPORT=y
diff --git a/configs/clearfog_sata_defconfig b/configs/clearfog_sata_defconfig
index e9b3615..32fecf1 100644
--- a/configs/clearfog_sata_defconfig
+++ b/configs/clearfog_sata_defconfig
@@ -6,20 +6,22 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
 CONFIG_TARGET_CLEARFOG=y
 CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
 CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK=0x4002c000
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xf1012000
 CONFIG_DEBUG_UART_CLOCK=250000000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
 CONFIG_BOOTDELAY=3
 CONFIG_USE_PREBOOT=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
@@ -31,7 +33,6 @@
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK=0x4002c000
 CONFIG_SPL_I2C=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_CMD_TLV_EEPROM=y
@@ -46,7 +47,6 @@
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_MIN_ENTRIES=128
 CONFIG_ARP_TIMEOUT=200
@@ -72,7 +72,6 @@
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_MVMDIO=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SCSI=y
 CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
diff --git a/configs/clearfog_spi_defconfig b/configs/clearfog_spi_defconfig
index 9dcf16f..30510da 100644
--- a/configs/clearfog_spi_defconfig
+++ b/configs/clearfog_spi_defconfig
@@ -18,6 +18,7 @@
 CONFIG_DEBUG_UART_BASE=0xf1012000
 CONFIG_DEBUG_UART_CLOCK=250000000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
@@ -46,7 +47,6 @@
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_MIN_ENTRIES=128
 CONFIG_ARP_TIMEOUT=200
@@ -72,7 +72,6 @@
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_MVMDIO=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SCSI=y
 CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index 0898c87..fa70097 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -89,7 +90,6 @@
 CONFIG_NAND_MXS=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index d691e5d..41f5038 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
+CONFIG_SF_DEFAULT_SPEED=48000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -83,7 +84,6 @@
 CONFIG_SYS_NAND_PAGE_SIZE=0x800
 CONFIG_SYS_NAND_OOBSIZE=0x40
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=48000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/colibri-imx6ull-emmc_defconfig b/configs/colibri-imx6ull-emmc_defconfig
index b47c8c0..bd21559 100644
--- a/configs/colibri-imx6ull-emmc_defconfig
+++ b/configs/colibri-imx6ull-emmc_defconfig
@@ -10,6 +10,7 @@
 CONFIG_TARGET_COLIBRI_IMX6ULL_EMMC=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri-emmc-eval-v3"
 CONFIG_SYS_PROMPT="Colibri iMX6ULL # "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_LOAD_ADDR=0x84200000
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
@@ -86,4 +87,3 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index 2f1a201..8cf62c2 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -11,6 +11,7 @@
 CONFIG_TARGET_COLIBRI_IMX6ULL_NAND=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri-eval-v3"
 CONFIG_SYS_PROMPT="Colibri iMX6ULL # "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_LOAD_ADDR=0x84200000
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
@@ -103,4 +104,3 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig
index 8716021..c7ddb7d 100644
--- a/configs/colibri-imx8x_defconfig
+++ b/configs/colibri-imx8x_defconfig
@@ -14,6 +14,7 @@
 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
 CONFIG_TARGET_COLIBRI_IMX8X=y
 CONFIG_SYS_PROMPT="Colibri iMX8X # "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_LOAD_ADDR=0x95c00000
 CONFIG_SYS_MEMTEST_START=0x88000000
 CONFIG_SYS_MEMTEST_END=0x89000000
@@ -21,10 +22,10 @@
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=1
 CONFIG_USE_PREBOOT=y
 CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri-${fdt_board}.dtb"
-CONFIG_DISTRO_DEFAULTS=y
 CONFIG_LOG=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -89,5 +90,4 @@
 CONFIG_FSL_LPUART=y
 CONFIG_DM_THERMAL=y
 CONFIG_IMX_SCU_THERMAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index a708977..7772990 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -18,6 +18,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="imx6dl-colibri-eval-v3"
 CONFIG_SPL_TEXT_BASE=0x00908000
 CONFIG_SYS_PROMPT="Colibri iMX6 # "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL=y
@@ -118,4 +119,3 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index 8439742..2716a98 100644
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -8,6 +8,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="imx7d-colibri-eval-v3"
 CONFIG_TARGET_COLIBRI_IMX7=y
 CONFIG_SYS_PROMPT="Colibri iMX7 # "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_IMX_RDC=y
 CONFIG_IMX_BOOTAUX=y
 CONFIG_IMX_HAB=y
@@ -101,4 +102,3 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig
index afd43b6..dbc1e33 100644
--- a/configs/colibri_imx7_emmc_defconfig
+++ b/configs/colibri_imx7_emmc_defconfig
@@ -8,6 +8,7 @@
 CONFIG_TARGET_COLIBRI_IMX7=y
 CONFIG_TARGET_COLIBRI_IMX7_EMMC=y
 CONFIG_SYS_PROMPT="Colibri iMX7 # "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
 CONFIG_IMX_RDC=y
 CONFIG_IMX_BOOTAUX=y
@@ -90,4 +91,3 @@
 CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index 1b38296..cdf9e8b 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -9,6 +9,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri"
 CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SYS_PROMPT="Colibri T20 # "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_STACK=0xffffc
 CONFIG_TEGRA20=y
 CONFIG_TARGET_COLIBRI_T20=y
@@ -79,4 +80,3 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index 01e6612..fed867a 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -9,6 +9,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri"
 CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_PROMPT="Colibri T30 # "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_STACK=0x800ffffc
 CONFIG_TEGRA30=y
 CONFIG_TARGET_COLIBRI_T30=y
@@ -60,4 +61,3 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index 2642e89..c47bfc8 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -10,6 +10,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri-eval-v3"
 CONFIG_SYS_PROMPT="Colibri VFxx # "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_TARGET_COLIBRI_VF=y
 CONFIG_SYS_LOAD_ADDR=0x80008000
 CONFIG_SYS_MEMTEST_START=0x80010000
@@ -104,6 +105,5 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_FDT_FIXUP_PARTITIONS=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig
index 89f063b..07bda04 100644
--- a/configs/colorfly_e708_q1_defconfig
+++ b/configs/colorfly_e708_q1_defconfig
@@ -6,7 +6,6 @@
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_ZQ=251
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PA15"
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:800,y:1280,depth:24,pclk_khz:64000,le:20,ri:34,up:1,lo:16,hs:10,vs:1,sync:3,vmode:0"
@@ -15,6 +14,7 @@
 CONFIG_VIDEO_LCD_BL_PWM="PH13"
 CONFIG_VIDEO_LCD_PANEL_LVDS=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_AXP_DLDO2_VOLT=1800
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig
index 9940258..50acfdf 100644
--- a/configs/controlcenterdc_defconfig
+++ b/configs/controlcenterdc_defconfig
@@ -21,6 +21,7 @@
 CONFIG_DEBUG_UART_BASE=0xf1012000
 CONFIG_DEBUG_UART_CLOCK=250000000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 CONFIG_OF_BOARD_FIXUP=y
@@ -90,7 +91,6 @@
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_MVMDIO=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SCSI=y
diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
index 383317f..2d39104 100644
--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
@@ -41,6 +41,7 @@
 CONFIG_REGMAP=y
 CONFIG_MISC=y
 # CONFIG_MMC is not set
+CONFIG_NVMXIP_QSPI=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_SMSC=y
 CONFIG_SMC911X=y
diff --git a/configs/crs305-1g-4s-bit_defconfig b/configs/crs305-1g-4s-bit_defconfig
index 80d7688..7b4305d 100644
--- a/configs/crs305-1g-4s-bit_defconfig
+++ b/configs/crs305-1g-4s-bit_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs305-1g-4s-bit"
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_BEST_MATCH=y
@@ -45,7 +46,6 @@
 CONFIG_SPI_FLASH_MACRONIX=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_SPI_FLASH_MTD=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SYS_NS16550=y
 CONFIG_KIRKWOOD_SPI=y
diff --git a/configs/crs305-1g-4s_defconfig b/configs/crs305-1g-4s_defconfig
index fad7512..8a155b3 100644
--- a/configs/crs305-1g-4s_defconfig
+++ b/configs/crs305-1g-4s_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs305-1g-4s"
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_BEST_MATCH=y
@@ -46,7 +47,6 @@
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_SPI_FLASH_MTD=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SYS_NS16550=y
 CONFIG_KIRKWOOD_SPI=y
diff --git a/configs/crs326-24g-2s-bit_defconfig b/configs/crs326-24g-2s-bit_defconfig
index cf6193a..94fdd8b 100644
--- a/configs/crs326-24g-2s-bit_defconfig
+++ b/configs/crs326-24g-2s-bit_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs326-24g-2s-bit"
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_BEST_MATCH=y
@@ -45,7 +46,6 @@
 CONFIG_SPI_FLASH_MACRONIX=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_SPI_FLASH_MTD=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SYS_NS16550=y
 CONFIG_KIRKWOOD_SPI=y
diff --git a/configs/crs326-24g-2s_defconfig b/configs/crs326-24g-2s_defconfig
index b1cc505..90a4a96 100644
--- a/configs/crs326-24g-2s_defconfig
+++ b/configs/crs326-24g-2s_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs326-24g-2s"
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_BEST_MATCH=y
@@ -45,7 +46,6 @@
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_SPI_FLASH_MTD=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SYS_NS16550=y
 CONFIG_KIRKWOOD_SPI=y
diff --git a/configs/crs328-4c-20s-4s-bit_defconfig b/configs/crs328-4c-20s-4s-bit_defconfig
index e847f5c..31058fd 100644
--- a/configs/crs328-4c-20s-4s-bit_defconfig
+++ b/configs/crs328-4c-20s-4s-bit_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs328-4c-20s-4s-bit"
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_BEST_MATCH=y
@@ -45,7 +46,6 @@
 CONFIG_SPI_FLASH_MACRONIX=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_SPI_FLASH_MTD=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SYS_NS16550=y
 CONFIG_KIRKWOOD_SPI=y
diff --git a/configs/crs328-4c-20s-4s_defconfig b/configs/crs328-4c-20s-4s_defconfig
index 82606da..567a4d2 100644
--- a/configs/crs328-4c-20s-4s_defconfig
+++ b/configs/crs328-4c-20s-4s_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs328-4c-20s-4s"
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_BEST_MATCH=y
@@ -45,7 +46,6 @@
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_SPI_FLASH_MTD=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SYS_NS16550=y
 CONFIG_KIRKWOOD_SPI=y
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index 9b04fff..2001327 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -13,6 +13,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0000f20
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x80000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -90,7 +91,6 @@
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index baa2632..936787b 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEXT_BASE=0x80110000
 CONFIG_SYS_MALLOC_LEN=0x2500000
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore"
@@ -50,7 +51,6 @@
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
 CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_TEGRA114_SPI=y
diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig
index b3ae142..71af33c 100644
--- a/configs/db-88f6820-amc_defconfig
+++ b/configs/db-88f6820-amc_defconfig
@@ -19,6 +19,7 @@
 CONFIG_DEBUG_UART_BASE=0xf1012000
 CONFIG_DEBUG_UART_CLOCK=200000000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -77,7 +78,6 @@
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_MVMDIO=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_SHIFT=2
diff --git a/configs/db-88f6820-amc_nand_defconfig b/configs/db-88f6820-amc_nand_defconfig
index e784c34..f565972 100644
--- a/configs/db-88f6820-amc_nand_defconfig
+++ b/configs/db-88f6820-amc_nand_defconfig
@@ -5,6 +5,8 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
 CONFIG_TARGET_DB_88F6820_AMC=y
 CONFIG_MVEBU_SPL_BOOT_DEVICE_NAND=y
 CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION=0x00
@@ -14,13 +16,13 @@
 CONFIG_DEFAULT_DEVICE_TREE="armada-385-db-88f6820-amc"
 CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK=0x4002c000
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xf1012000
 CONFIG_DEBUG_UART_CLOCK=200000000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTDELAY=3
@@ -34,7 +36,6 @@
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK=0x4002c000
 CONFIG_SPL_I2C=y
 CONFIG_SYS_MAXARGS=96
 # CONFIG_CMD_FLASH is not set
@@ -81,7 +82,6 @@
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_MVMDIO=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_SHIFT=2
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index f3b228a..ab16a54 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -19,6 +19,7 @@
 CONFIG_DEBUG_UART_BASE=0xf1012000
 CONFIG_DEBUG_UART_CLOCK=250000000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 CONFIG_BOOTDELAY=3
@@ -72,7 +73,6 @@
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_MVMDIO=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SCSI=y
 CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig
index c456081..6ebf412 100644
--- a/configs/db-mv784mp-gp_defconfig
+++ b/configs/db-mv784mp-gp_defconfig
@@ -19,6 +19,7 @@
 CONFIG_DEBUG_UART_BASE=0xf1012000
 CONFIG_DEBUG_UART_CLOCK=250000000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_BOOTDELAY=3
@@ -76,7 +77,6 @@
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_MVMDIO=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_SHIFT=2
diff --git a/configs/db-xc3-24g4xg_defconfig b/configs/db-xc3-24g4xg_defconfig
index cb30799..c5f60e4 100644
--- a/configs/db-xc3-24g4xg_defconfig
+++ b/configs/db-xc3-24g4xg_defconfig
@@ -11,6 +11,7 @@
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-db-xc3-24g4xg"
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_SYS_MEMTEST_START=0x00800000
 CONFIG_SYS_MEMTEST_END=0x00ffffff
 CONFIG_FIT=y
@@ -55,7 +56,6 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SYS_NS16550=y
 CONFIG_KIRKWOOD_SPI=y
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index fa2d7f3..b29f08b 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -16,6 +17,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6q-dhcom-pdk2"
 CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
@@ -86,7 +88,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
@@ -123,4 +124,3 @@
 CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
 CONFIG_IMX_WATCHDOG=y
 CONFIG_BZIP2=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index a05d6bf..a9af901 100644
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x120000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -30,7 +31,6 @@
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_MONITOR_LEN=409600
-CONFIG_STANDALONE_LOAD_ADDR=0x10001000
 CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SUPPORT_RAW_INITRD=y
@@ -109,7 +109,6 @@
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig
index 0ef41b6..06f1164 100644
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x120000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -27,7 +28,6 @@
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_MONITOR_LEN=409600
-CONFIG_STANDALONE_LOAD_ADDR=0x10001000
 CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SUPPORT_RAW_INITRD=y
@@ -111,7 +111,6 @@
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index ccec543..371c888 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -5,6 +5,7 @@
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037fef0
+CONFIG_SF_DEFAULT_SPEED=76800000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
@@ -112,7 +113,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x140000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=76800000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_TI_DP83867=y
 CONFIG_PHY_GIGE=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 6fe7e21..3165b9b 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037fef0
+CONFIG_SF_DEFAULT_SPEED=76800000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
@@ -105,7 +106,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x140000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=76800000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_TI_DP83867=y
 CONFIG_PHY_GIGE=y
diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig
index 0d6b8a9..6ed98cf 100644
--- a/configs/dra7xx_hs_evm_usb_defconfig
+++ b/configs/dra7xx_hs_evm_usb_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037fef0
+CONFIG_SF_DEFAULT_SPEED=76800000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
@@ -94,7 +95,6 @@
 CONFIG_HSMMC2_8BIT=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=76800000
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_TI_DP83867=y
diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
index ab962e4..84b0834 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -10,6 +10,7 @@
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c"
 CONFIG_SYS_PROMPT="dragonboard410c => "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C"
 CONFIG_SYS_LOAD_ADDR=0x80080000
 CONFIG_REMAKE_ELF=y
@@ -69,4 +70,3 @@
 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
 CONFIG_USB_GADGET_PRODUCT_NUM=0xd00d
 CONFIG_CI_UDC=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/ds116_defconfig b/configs/ds116_defconfig
index d7cf36f..dc7ce22 100644
--- a/configs/ds116_defconfig
+++ b/configs/ds116_defconfig
@@ -12,6 +12,7 @@
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
 CONFIG_TARGET_DS116=y
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x7E0000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -25,6 +26,7 @@
 CONFIG_DEBUG_UART_CLOCK=250000000
 CONFIG_IDENT_STRING="\nSynology DS116"
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
@@ -68,7 +70,6 @@
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_MARVELL=y
@@ -76,7 +77,6 @@
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_MVMDIO=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_ARMADA_38X=y
diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig
index b79f96c..3929ea9 100644
--- a/configs/ds414_defconfig
+++ b/configs/ds414_defconfig
@@ -23,6 +23,7 @@
 CONFIG_DEBUG_UART_BASE=0xf1012000
 CONFIG_DEBUG_UART_CLOCK=250000000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTARGS=y
@@ -74,7 +75,6 @@
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_MVMDIO=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_SHIFT=2
diff --git a/configs/durian_defconfig b/configs/durian_defconfig
index b4cb442..a5756c1 100644
--- a/configs/durian_defconfig
+++ b/configs/durian_defconfig
@@ -13,6 +13,7 @@
 # CONFIG_PSCI_RESET is not set
 CONFIG_SYS_LOAD_ADDR=0x90000000
 CONFIG_SYS_PCI_64BIT=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_USE_BOOTARGS=y
@@ -32,7 +33,6 @@
 CONFIG_SCSI_AHCI=y
 CONFIG_AHCI_PCI=y
 # CONFIG_MMC is not set
-CONFIG_PCI=y
 CONFIG_PCI_PHYTIUM=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
diff --git a/configs/eDPU_defconfig b/configs/eDPU_defconfig
index 22ffc40..77ea2b2 100644
--- a/configs/eDPU_defconfig
+++ b/configs/eDPU_defconfig
@@ -22,7 +22,6 @@
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=1048
@@ -41,7 +40,6 @@
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig
index f86635d..a8e6638 100644
--- a/configs/eb_cpu5282_defconfig
+++ b/configs/eb_cpu5282_defconfig
@@ -30,13 +30,11 @@
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_MII_INIT=y
-CONFIG_CMD_DATE=y
 CONFIG_OVERWRITE_ETHADDR_ONCE=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
 CONFIG_SYS_RX_ETH_BUFFER=8
-CONFIG_SYS_I2C_FSL=y
 CONFIG_DM_I2C=y
-CONFIG_DM_RTC=y
+CONFIG_SYS_I2C_FSL=y
 CONFIG_LED_STATUS=y
 CONFIG_LED_STATUS0=y
 CONFIG_LED_STATUS_BIT=8
@@ -51,5 +49,6 @@
 CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_MCFFEC=y
 CONFIG_MII=y
+CONFIG_DM_RTC=y
 CONFIG_RTC_DS1338=y
 CONFIG_MCFUART=y
diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig
index 1982fea..4475659 100644
--- a/configs/eb_cpu5282_internal_defconfig
+++ b/configs/eb_cpu5282_internal_defconfig
@@ -28,7 +28,6 @@
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
 CONFIG_MII_INIT=y
-CONFIG_CMD_DATE=y
 CONFIG_OVERWRITE_ETHADDR_ONCE=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
 CONFIG_SYS_RX_ETH_BUFFER=8
diff --git a/configs/ev-imx280-nano-x-mb_defconfig b/configs/ev-imx280-nano-x-mb_defconfig
index 0686916..0546cb7 100644
--- a/configs/ev-imx280-nano-x-mb_defconfig
+++ b/configs/ev-imx280-nano-x-mb_defconfig
@@ -6,6 +6,7 @@
 CONFIG_TARGET_O4_IMX6ULL_NANO=y
 CONFIG_DM_GPIO=y
 CONFIG_EV_IMX280_NANO_X_MB=y
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_IMX_MODULE_FUSE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
@@ -54,4 +55,3 @@
 CONFIG_USB_GADGET_VENDOR_NUM=0x3016
 CONFIG_USB_GADGET_PRODUCT_NUM=0x0001
 CONFIG_CI_UDC=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
index f49aa45..29f7516 100644
--- a/configs/evb-px5_defconfig
+++ b/configs/evb-px5_defconfig
@@ -35,7 +35,6 @@
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 112a59c..9dcd113 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -10,6 +10,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
 CONFIG_SPL_TEXT_BASE=0x10081000
 CONFIG_ROCKCHIP_RK3036=y
@@ -50,7 +51,6 @@
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PINCTRL=y
 # CONFIG_SPL_DM_SERIAL is not set
diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig
index 1644c20..bf3d2f4 100644
--- a/configs/evb-rk3128_defconfig
+++ b/configs/evb-rk3128_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="rk3128-evb"
 CONFIG_DM_RESET=y
@@ -39,7 +40,6 @@
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_PHY=y
 CONFIG_PINCTRL=y
 CONFIG_REGULATOR_PWM=y
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index c4aebee..bd4a004 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb"
 CONFIG_DM_RESET=y
@@ -69,7 +70,6 @@
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PINCTRL=y
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 7a14ffb..580ee50 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb"
 CONFIG_ROCKCHIP_RK3328=y
@@ -70,7 +71,6 @@
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PINCTRL=y
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index 415ef8a..f594f15 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb"
 CONFIG_DM_RESET=y
@@ -48,7 +49,6 @@
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index ddeadb8..7911cc7 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -12,7 +12,6 @@
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3588=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_TARGET_EVB_RK3588=y
diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig
index 09cb579..94b8f88 100644
--- a/configs/ficus-rk3399_defconfig
+++ b/configs/ficus-rk3399_defconfig
@@ -5,6 +5,7 @@
 CONFIG_TEXT_BASE=0x00200000
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus"
 CONFIG_SPL_TEXT_BASE=0xff8c2000
@@ -44,7 +45,6 @@
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_GMAC_ROCKCHIP=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 87ed2b2..d2bd750 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
 CONFIG_DM_RESET=y
@@ -65,7 +66,6 @@
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PINCTRL=y
diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
index 71891d2..0ece93b 100644
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly"
 CONFIG_DM_RESET=y
@@ -15,6 +16,7 @@
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -48,11 +50,9 @@
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig
index 599eeb9..935071d 100644
--- a/configs/ga10h_v1_1_defconfig
+++ b/configs/ga10h_v1_1_defconfig
@@ -7,7 +7,6 @@
 CONFIG_DRAM_ZQ=15291
 CONFIG_DRAM_ODT_EN=y
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH8"
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:52000,le:138,ri:162,up:22,lo:10,hs:20,vs:3,sync:3,vmode:0"
@@ -17,6 +16,7 @@
 CONFIG_VIDEO_LCD_BL_PWM="PH0"
 CONFIG_VIDEO_LCD_PANEL_LVDS=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_CONS_INDEX=5
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig
index 63488da..3d66313 100644
--- a/configs/gazerbeam_defconfig
+++ b/configs/gazerbeam_defconfig
@@ -34,7 +34,6 @@
 CONFIG_BAT1_LENGTH_8_MBYTES=y
 CONFIG_BAT1_ACCESS_RW=y
 CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
 CONFIG_BAT1_DCACHE_INHIBITED=y
 CONFIG_BAT1_DCACHE_GUARDED=y
 CONFIG_BAT1_USER_MODE_VALID=y
@@ -87,6 +86,7 @@
 CONFIG_LCRR_CLKDIV_2=y
 CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM=y
 CONFIG_CMD_IOLOOP=y
+# CONFIG_PCI is not set
 CONFIG_SYS_MEMTEST_START=0x00001000
 CONFIG_SYS_MEMTEST_END=0x07e00000
 CONFIG_SYS_BARGSIZE=1024
@@ -188,7 +188,6 @@
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
 CONFIG_TSEC_ENET=y
-# CONFIG_PCI is not set
 CONFIG_RAM=y
 CONFIG_MPC83XX_SDRAM=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig
index e644137..07e357e 100644
--- a/configs/ge_b1x5v2_defconfig
+++ b/configs/ge_b1x5v2_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -90,7 +91,6 @@
 CONFIG_LED_GPIO=y
 CONFIG_FSL_USDHC=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHYLIB=y
diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig
index 82f6cc3..f005e91 100644
--- a/configs/ge_bx50v3_defconfig
+++ b/configs/ge_bx50v3_defconfig
@@ -4,12 +4,14 @@
 CONFIG_SYS_MALLOC_LEN=0xa00000
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_MX6Q=y
 CONFIG_TARGET_GE_BX50V3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6q-bx50v3"
 CONFIG_BOOTCOUNT_BOOTLIMIT=10
+CONFIG_PCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FIT=y
 CONFIG_SUPPORT_RAW_INITRD=y
@@ -61,7 +63,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHYLIB=y
@@ -70,7 +71,6 @@
 CONFIG_CMD_E1000=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
-CONFIG_PCI=y
 CONFIG_PCI_SCAN_SHOW=y
 CONFIG_PCIE_IMX=y
 CONFIG_PINCTRL=y
diff --git a/configs/gose_defconfig b/configs/gose_defconfig
index 265c7a6..91c2cfb 100644
--- a/configs/gose_defconfig
+++ b/configs/gose_defconfig
@@ -29,6 +29,7 @@
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x50000000
 CONFIG_ENV_ADDR=0xC0000
+CONFIG_PCI=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
@@ -87,7 +88,6 @@
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
 CONFIG_SH_ETHER=y
-CONFIG_PCI=y
 CONFIG_PCI_RCAR_GEN2=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig
index d0af2b8..04edcf3 100644
--- a/configs/grpeach_defconfig
+++ b/configs/grpeach_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach-u-boot"
 CONFIG_RZA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_CLK_FREQ=66666666
 CONFIG_SYS_LOAD_ADDR=0x20400000
 CONFIG_SYS_MONITOR_LEN=524288
@@ -64,5 +65,4 @@
 CONFIG_USB=y
 CONFIG_USB_R8A66597_HCD=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig
index f5e3a72..205eab2 100644
--- a/configs/gt90h_v4_defconfig
+++ b/configs/gt90h_v4_defconfig
@@ -6,7 +6,6 @@
 CONFIG_DRAM_CLK=480
 CONFIG_DRAM_ZQ=32767
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH8"
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:55000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
@@ -15,6 +14,7 @@
 CONFIG_VIDEO_LCD_BL_EN="PH6"
 CONFIG_VIDEO_LCD_BL_PWM="PH0"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_CONS_INDEX=5
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig
index ee833a5..9863867 100644
--- a/configs/gwventana_emmc_defconfig
+++ b/configs/gwventana_emmc_defconfig
@@ -24,6 +24,7 @@
 CONFIG_SPL=y
 CONFIG_ENV_OFFSET_REDUND=0xD1400
 CONFIG_CMD_HDMIDETECT=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_SYS_MONITOR_LEN=409600
 CONFIG_FIT=y
@@ -121,7 +122,6 @@
 CONFIG_FEC_MXC=y
 CONFIG_MV88E6XXX=y
 CONFIG_MII=y
-CONFIG_PCI=y
 CONFIG_PCIE_IMX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig
index 194faa5..bc549ca 100644
--- a/configs/gwventana_nand_defconfig
+++ b/configs/gwventana_nand_defconfig
@@ -24,6 +24,7 @@
 CONFIG_SPL=y
 CONFIG_ENV_OFFSET_REDUND=0x1080000
 CONFIG_CMD_HDMIDETECT=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_SYS_MONITOR_LEN=409600
 CONFIG_FIT=y
@@ -128,7 +129,6 @@
 CONFIG_E1000=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
-CONFIG_PCI=y
 CONFIG_PCIE_IMX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
diff --git a/configs/gxp_defconfig b/configs/gxp_defconfig
index c97cbbf..549bef7 100644
--- a/configs/gxp_defconfig
+++ b/configs/gxp_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_SF_DEFAULT_MODE=3
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x60000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -42,7 +43,6 @@
 CONFIG_MISC=y
 # CONFIG_MMC is not set
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=3
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index 7f8cd90..b1d9399 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -13,6 +13,7 @@
 CONFIG_TARGET_HARMONY=y
 CONFIG_TEGRA_ENABLE_UARTD=y
 CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_PCI=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_STDIO_DEREGISTER=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
@@ -51,7 +52,6 @@
 CONFIG_TEGRA_NAND=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_PCI=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/hc2910_2aghd05_defconfig b/configs/hc2910_2aghd05_defconfig
new file mode 100644
index 0000000..dfd3e65
--- /dev/null
+++ b/configs/hc2910_2aghd05_defconfig
@@ -0,0 +1,50 @@
+CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_HISTB=y
+CONFIG_TEXT_BASE=0x00000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x1F0000
+CONFIG_DEFAULT_DEVICE_TREE="hi3798mv200-hc2910-2aghd05"
+CONFIG_SYS_PROMPT="HC2910# "
+CONFIG_IDENT_STRING="HC2910"
+CONFIG_SYS_LOAD_ADDR=0x800000
+# CONFIG_EXPERT is not set
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=537
+CONFIG_CMD_BOOTDEV=y
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_CMD_NVEDIT_INFO=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MBR=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_EROFS=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
+# CONFIG_GPIO is not set
+# CONFIG_I2C is not set
+# CONFIG_INPUT is not set
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_K3=y
+# CONFIG_POWER is not set
+CONFIG_FS_BTRFS=y
+CONFIG_FAT_WRITE=y
+CONFIG_REGEX=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig
index d40ccb8..d74bf72 100644
--- a/configs/helios4_defconfig
+++ b/configs/helios4_defconfig
@@ -18,6 +18,7 @@
 CONFIG_DEBUG_UART_BASE=0xf1012000
 CONFIG_DEBUG_UART_CLOCK=250000000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
@@ -47,7 +48,6 @@
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_MIN_ENTRIES=128
 CONFIG_ARP_TIMEOUT=200
@@ -60,7 +60,6 @@
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_I2C_EEPROM=y
 CONFIG_SPL_I2C_EEPROM=y
-CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_MV=y
@@ -73,7 +72,6 @@
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_MVMDIO=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SCSI=y
 CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig
index a6523b1..a663aa7 100644
--- a/configs/hihope_rzg2_defconfig
+++ b/configs/hihope_rzg2_defconfig
@@ -84,4 +84,3 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/hikey960_defconfig b/configs/hikey960_defconfig
index be85dbe..5cf822b 100644
--- a/configs/hikey960_defconfig
+++ b/configs/hikey960_defconfig
@@ -9,6 +9,7 @@
 CONFIG_ENV_SIZE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="hi3660-hikey960"
 CONFIG_SYS_PROMPT="U-Boot => "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_IDENT_STRING="\nHikey960"
 CONFIG_SYS_LOAD_ADDR=0x80000
 CONFIG_DISTRO_DEFAULTS=y
@@ -34,4 +35,3 @@
 CONFIG_MMC_DW_K3=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_SINGLE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
index 19459be..e50a2ca 100644
--- a/configs/hikey_defconfig
+++ b/configs/hikey_defconfig
@@ -8,6 +8,7 @@
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_IDENT_STRING="hikey"
 CONFIG_SYS_LOAD_ADDR=0x80000
 CONFIG_REMAKE_ELF=y
@@ -41,4 +42,3 @@
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/iNet_D978_rev2_defconfig b/configs/iNet_D978_rev2_defconfig
index e01e184..ed6a603 100644
--- a/configs/iNet_D978_rev2_defconfig
+++ b/configs/iNet_D978_rev2_defconfig
@@ -6,7 +6,6 @@
 CONFIG_DRAM_CLK=456
 CONFIG_DRAM_ZQ=15291
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH8"
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:65000,le:120,ri:180,up:22,lo:13,hs:20,vs:3,sync:3,vmode:0"
@@ -16,6 +15,7 @@
 CONFIG_VIDEO_LCD_BL_PWM="PH0"
 CONFIG_VIDEO_LCD_PANEL_LVDS=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DLDO1_VOLT=3300
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_CONS_INDEX=5
diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig
index 9d20865..4f6e55c 100644
--- a/configs/iconnect_defconfig
+++ b/configs/iconnect_defconfig
@@ -17,6 +17,7 @@
 CONFIG_SYS_PROMPT="iConnect> "
 CONFIG_IDENT_STRING=" Iomega iConnect"
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part rootfs; ubifsmount ubi:rootfs; ubifsload 0x800000 ${kernel}; bootm 0x800000"
@@ -54,7 +55,6 @@
 CONFIG_PHY_MARVELL=y
 CONFIG_MVGBE=y
 CONFIG_MII=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig
index e73a7ab..06dd6b1 100644
--- a/configs/imx28_xea_defconfig
+++ b/configs/imx28_xea_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_IMX_CONFIG=""
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
@@ -95,7 +96,6 @@
 CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=3
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/imx28_xea_sb_defconfig b/configs/imx28_xea_sb_defconfig
index b7edd3b..bb7bf5d 100644
--- a/configs/imx28_xea_sb_defconfig
+++ b/configs/imx28_xea_sb_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="imx28-xea"
@@ -76,7 +77,6 @@
 CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=3
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig
index 524b22f..6839a2f 100644
--- a/configs/imx8mm-cl-iot-gate-optee_defconfig
+++ b/configs/imx8mm-cl-iot-gate-optee_defconfig
@@ -11,6 +11,7 @@
 CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE=y
 CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -152,7 +153,6 @@
 CONFIG_TPM=y
 CONFIG_LZO=y
 CONFIG_BZIP2=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_SET_TIME=y
 CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
 CONFIG_EFI_CAPSULE_ON_DISK=y
diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig
index 010fa91..85e418f 100644
--- a/configs/imx8mm-cl-iot-gate_defconfig
+++ b/configs/imx8mm-cl-iot-gate_defconfig
@@ -12,6 +12,7 @@
 CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MM_CL_IOT_GATE=y
 CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -155,7 +156,6 @@
 CONFIG_TPM=y
 CONFIG_LZO=y
 CONFIG_BZIP2=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_SET_TIME=y
 CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
 CONFIG_EFI_CAPSULE_ON_DISK=y
diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig
index 0a374aa..81af9dd 100644
--- a/configs/imx8mm-mx8menlo_defconfig
+++ b/configs/imx8mm-mx8menlo_defconfig
@@ -12,6 +12,7 @@
 CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MM_MX8MENLO=y
 CONFIG_SYS_PROMPT="Verdin iMX8MM # "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -143,4 +144,3 @@
 CONFIG_SDP_LOADADDR=0x40400000
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_IMX_WATCHDOG=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index 163a2ff..597fe25 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -5,6 +5,7 @@
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DM_GPIO=y
@@ -99,7 +100,6 @@
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig
index 7131d8d..55dd54f 100644
--- a/configs/imx8mm_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x40000
 CONFIG_ENV_OFFSET=0xFFFC0000
 CONFIG_IMX_CONFIG="board/data_modul/imx8mm_edm_sbc/imximage.cfg"
@@ -14,6 +15,7 @@
 CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MM_DATA_MODUL_EDM_SBC=y
 CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -184,7 +186,6 @@
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 # CONFIG_SPI_FLASH_UNLOCK_ALL is not set
 CONFIG_SPI_FLASH_WINBOND=y
@@ -235,4 +236,3 @@
 CONFIG_SDP_LOADADDR=0x0
 CONFIG_USB_FUNCTION_ACM=y
 CONFIG_IMX_WATCHDOG=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig
index 3f9c94e..c5d0ffc 100644
--- a/configs/imx8mm_evk_fspi_defconfig
+++ b/configs/imx8mm_evk_fspi_defconfig
@@ -5,6 +5,8 @@
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_IMX_CONFIG="board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg"
@@ -79,8 +81,6 @@
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_FSL_USDHC=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index db2da79..d85d9ad 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -12,6 +12,7 @@
 CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MM_VENICE=y
 CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -151,4 +152,3 @@
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_IMX_WATCHDOG=y
 CONFIG_HEXDUMP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig
index 51148c9..c87cdd6 100644
--- a/configs/imx8mn_beacon_2g_defconfig
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DM_GPIO=y
@@ -14,6 +15,7 @@
 CONFIG_TARGET_IMX8MN_BEACON=y
 CONFIG_IMX8MN_BEACON_2GB_LPDDR=y
 CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -107,7 +109,6 @@
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_FSL_USDHC=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
@@ -141,4 +142,3 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_SDP_LOADADDR=0x0
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
index b39595b..d68c120 100644
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DM_GPIO=y
@@ -13,6 +14,7 @@
 CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_TARGET_IMX8MN_BEACON=y
 CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -109,7 +111,6 @@
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_MTD=y
@@ -149,4 +150,3 @@
 CONFIG_CI_UDC=y
 CONFIG_SDP_LOADADDR=0x0
 CONFIG_IMX_WATCHDOG=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig
index 0ad3a0e..ecd383a 100644
--- a/configs/imx8mn_beacon_fspi_defconfig
+++ b/configs/imx8mn_beacon_fspi_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DM_GPIO=y
@@ -13,6 +14,7 @@
 CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_TARGET_IMX8MN_BEACON=y
 CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -109,7 +111,6 @@
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_MTD=y
@@ -149,6 +150,5 @@
 CONFIG_CI_UDC=y
 CONFIG_SDP_LOADADDR=0x0
 CONFIG_IMX_WATCHDOG=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_FSPI_CONF_HEADER=y
 CONFIG_FSPI_CONF_FILE="fspi_header.bin"
diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig
index 8c0086f..ec18db3 100644
--- a/configs/imx8mn_bsh_smm_s2_defconfig
+++ b/configs/imx8mn_bsh_smm_s2_defconfig
@@ -12,6 +12,7 @@
 CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_TARGET_IMX8MN_BSH_SMM_S2=y
 CONFIG_SYS_PROMPT="> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x980000
@@ -114,4 +115,3 @@
 CONFIG_CI_UDC=y
 CONFIG_IMX_WATCHDOG=y
 # CONFIG_FAT_WRITE is not set
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig
index 57405d7..55d7297 100644
--- a/configs/imx8mn_bsh_smm_s2pro_defconfig
+++ b/configs/imx8mn_bsh_smm_s2pro_defconfig
@@ -12,6 +12,7 @@
 CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_TARGET_IMX8MN_BSH_SMM_S2PRO=y
 CONFIG_SYS_PROMPT="> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -103,4 +104,3 @@
 CONFIG_CI_UDC=y
 CONFIG_IMX_WATCHDOG=y
 # CONFIG_FAT_WRITE is not set
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index f02cbab..1b4f94c 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -13,6 +13,7 @@
 CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_TARGET_IMX8MN_VAR_SOM=y
 CONFIG_SYS_PROMPT="> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -109,4 +110,3 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_IMX_WATCHDOG=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig
index e9cb264..9482995 100644
--- a/configs/imx8mn_venice_defconfig
+++ b/configs/imx8mn_venice_defconfig
@@ -12,6 +12,7 @@
 CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_TARGET_IMX8MN_VENICE=y
 CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -152,4 +153,3 @@
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_IMX_WATCHDOG=y
 CONFIG_HEXDUMP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig
index ca6ee2f..e8ddd53 100644
--- a/configs/imx8mp_beacon_defconfig
+++ b/configs/imx8mp_beacon_defconfig
@@ -6,6 +6,9 @@
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SOURCE_FILE="imx8mp_beacon"
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DM_GPIO=y
@@ -30,13 +33,13 @@
 CONFIG_ARMV8_EA_EL3_FIRST=y
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
 CONFIG_SYS_LOAD_ADDR=0x40480000
-CONFIG_DISTRO_DEFAULTS=y
 CONFIG_SYS_MONITOR_LEN=524288
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
 CONFIG_DEFAULT_FDT_FILE="imx8mp-beacon-kit.dtb"
 # CONFIG_SYS_DEVICE_NULLDEV is not set
@@ -78,7 +81,6 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
-CONFIG_ENV_SOURCE_FILE="imx8mp_beacon"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -112,8 +114,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig
index 950d557..4abb899 100644
--- a/configs/imx8mp_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mp_data_modul_edm_sbc_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x40000
 CONFIG_ENV_OFFSET=0xFFFC0000
 CONFIG_DM_GPIO=y
@@ -15,11 +16,14 @@
 CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_IMX8MP_DATA_MODUL_EDM_SBC=y
 CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
+CONFIG_SPL_STACK=0x96fc00
 CONFIG_SPL=y
 CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
 CONFIG_DEBUG_UART_BASE=0x30880000
@@ -38,7 +42,6 @@
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
-# CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_USE_BOOTARGS=y
@@ -57,7 +60,6 @@
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK=0x96fc00
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
 CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x4c000000
@@ -197,7 +199,6 @@
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 # CONFIG_SPI_FLASH_UNLOCK_ALL is not set
 CONFIG_SPI_FLASH_WINBOND=y
@@ -228,10 +229,8 @@
 CONFIG_SPL_DM_REGULATOR_PCA9450=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_RESET=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_M41T62=y
-CONFIG_CONS_INDEX=3
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
@@ -264,4 +263,3 @@
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_IMX_WATCHDOG=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig
index c065706..dbffc36 100644
--- a/configs/imx8mp_dhcom_pdk2_defconfig
+++ b/configs/imx8mp_dhcom_pdk2_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xFE0000
 CONFIG_ENV_SECT_SIZE=0x1000
@@ -15,6 +16,7 @@
 CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y
 CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -192,7 +194,6 @@
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 # CONFIG_SPI_FLASH_UNLOCK_ALL is not set
 CONFIG_SPI_FLASH_WINBOND=y
@@ -260,4 +261,3 @@
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_IMX_WATCHDOG=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig
index 9966c50..2c54fa5 100644
--- a/configs/imx8mp_dhcom_pdk3_defconfig
+++ b/configs/imx8mp_dhcom_pdk3_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xFE0000
 CONFIG_ENV_SECT_SIZE=0x1000
@@ -15,6 +16,7 @@
 CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y
 CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -195,7 +197,6 @@
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 # CONFIG_SPI_FLASH_UNLOCK_ALL is not set
 CONFIG_SPI_FLASH_WINBOND=y
@@ -263,4 +264,3 @@
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_IMX_WATCHDOG=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig
index 325242c..42569b3 100644
--- a/configs/imx8mp_rsb3720a1_4G_defconfig
+++ b/configs/imx8mp_rsb3720a1_4G_defconfig
@@ -6,6 +6,8 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=3
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -15,6 +17,7 @@
 CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_IMX8MP_RSB3720A1_4G=y
 CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -121,8 +124,6 @@
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_FSL_USDHC=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_REALTEK=y
@@ -161,7 +162,6 @@
 CONFIG_SHA384=y
 CONFIG_LZO=y
 CONFIG_BZIP2=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_SET_TIME=y
 CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
 CONFIG_EFI_CAPSULE_ON_DISK=y
diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig
index ede81fb..e756c4f 100644
--- a/configs/imx8mp_rsb3720a1_6G_defconfig
+++ b/configs/imx8mp_rsb3720a1_6G_defconfig
@@ -6,6 +6,8 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=3
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -15,6 +17,7 @@
 CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_IMX8MP_RSB3720A1_6G=y
 CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -121,8 +124,6 @@
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_FSL_USDHC=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
@@ -162,7 +163,6 @@
 CONFIG_SHA384=y
 CONFIG_LZO=y
 CONFIG_BZIP2=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_SET_TIME=y
 CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
 CONFIG_EFI_CAPSULE_ON_DISK=y
diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig
index 4d04320..a1704f2 100644
--- a/configs/imx8mp_venice_defconfig
+++ b/configs/imx8mp_venice_defconfig
@@ -12,6 +12,7 @@
 CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_IMX8MP_VENICE=y
 CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -151,4 +152,3 @@
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_IMX_WATCHDOG=y
 CONFIG_HEXDUMP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig
new file mode 100644
index 0000000..9b14a1b
--- /dev/null
+++ b/configs/imx8mq_reform2_defconfig
@@ -0,0 +1,107 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x600000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-mnt-reform2"
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MQ_REFORM2=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_DEFAULT_FDT_FILE="freescale/imx8mq-mnt-reform2.dtb"
+CONFIG_CONSOLE_MUX=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x1f000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x180000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0x187ff0
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_PBSIZE=1050
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="FEC"
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_KEYBOARD=y
diff --git a/configs/imx8qm_dmsse20a1_defconfig b/configs/imx8qm_dmsse20a1_defconfig
new file mode 100644
index 0000000..3341b5e
--- /dev/null
+++ b/configs/imx8qm_dmsse20a1_defconfig
@@ -0,0 +1,129 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8=y
+CONFIG_TEXT_BASE=0x80020000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_SYS_MALLOC_LEN=0x2800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SYS_MMC_IMG_LOAD_PART=0
+CONFIG_TARGET_IMX8QM_DMSSE20_A1=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_ENV_OFFSET=0x80000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x80280000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xC0000000
+CONFIG_REMAKE_ELF=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_CONTROL=y
+CONFIG_CI_UDC=y
+CONFIG_DM_PCA953X=y
+CONFIG_EVENT=y
+CONFIG_DM_EVENT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BSS_START_ADDR=0x00128000
+CONFIG_SPL_MAX_SIZE=0x1f000
+CONFIG_SPL_BSS_MAX_SIZE=0x1000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SYS_BOOTM_LEN=0x04000000
+CONFIG_HUSH_PARSER=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_FS_FAT=y
+CONFIG_FS_EXT4=y
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_BROKEN_CD=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FUSE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8qm-dmsse20-a1"
+CONFIG_ENV_SOURCE_FILE="imx8qm_dmsse20-a1"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_MMC_ENV_PART=0
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_GIGE=y
+CONFIG_DM_ETH=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_FEC1_ENET_DEV=0
+CONFIG_ETHPRIME="eth0"
+CONFIG_FEC1_MXC_PHYADDR=0x4
+CONFIG_FEC2_ENET_DEV=1
+CONFIG_ETHPRIME1="eth1"
+CONFIG_FEC2_MXC_PHYADDR=0x4
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_IMX_SMMU=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_BAUDRATE=115200
+CONFIG_MISC=y
+CONFIG_SMC_FUSE=y
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_AHAB_BOOT=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_RV8803=y
+CONFIG_CMD_DATE=y
diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig
index 66e02e7..580cb5f 100644
--- a/configs/imx8ulp_evk_defconfig
+++ b/configs/imx8ulp_evk_defconfig
@@ -5,6 +5,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_IMX_CONFIG=""
@@ -71,7 +72,6 @@
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_FSL_USDHC=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig
index 2035a34..d215a83 100644
--- a/configs/inet86dz_defconfig
+++ b/configs/inet86dz_defconfig
@@ -6,7 +6,6 @@
 CONFIG_DRAM_CLK=552
 CONFIG_DRAM_ZQ=63351
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH8"
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:138,ri:162,up:22,lo:10,hs:20,vs:3,sync:3,vmode:0"
@@ -15,6 +14,7 @@
 CONFIG_VIDEO_LCD_BL_EN="PH6"
 CONFIG_VIDEO_LCD_BL_PWM="PH0"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_CONS_INDEX=5
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet_q972_defconfig b/configs/inet_q972_defconfig
index 85a3b4e..24ff6c0 100644
--- a/configs/inet_q972_defconfig
+++ b/configs/inet_q972_defconfig
@@ -6,7 +6,6 @@
 CONFIG_DRAM_CLK=384
 CONFIG_DRAM_ZQ=251
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PA15"
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:65000,le:280,ri:20,up:22,lo:8,hs:20,vs:8,sync:3,vmode:0"
@@ -14,6 +13,7 @@
 CONFIG_VIDEO_LCD_BL_EN="PA25"
 CONFIG_VIDEO_LCD_BL_PWM="PH13"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
diff --git a/configs/iot2050_pg1_defconfig b/configs/iot2050_pg1_defconfig
index b027696..cc1b967 100644
--- a/configs/iot2050_pg1_defconfig
+++ b/configs/iot2050_pg1_defconfig
@@ -19,15 +19,18 @@
 CONFIG_DEFAULT_DEVICE_TREE="k3-am6528-iot2050-basic"
 CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_SYS_PROMPT="IOT2050> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_ENV_OFFSET_REDUND=0x6a0000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
+CONFIG_PCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTSTAGE=y
 CONFIG_SHOW_BOOT_PROGRESS=y
@@ -109,7 +112,6 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PCI=y
 CONFIG_PCI_KEYSTONE=y
 CONFIG_PHY=y
 CONFIG_AM654_PHY=y
@@ -145,5 +147,4 @@
 CONFIG_WDT=y
 CONFIG_WDT_K3_RTI=y
 CONFIG_WDT_K3_RTI_LOAD_FW=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_SCROLL_ON_CLEAR_SCREEN=y
diff --git a/configs/iot2050_pg2_defconfig b/configs/iot2050_pg2_defconfig
index b206677..c5741a4 100644
--- a/configs/iot2050_pg2_defconfig
+++ b/configs/iot2050_pg2_defconfig
@@ -19,15 +19,19 @@
 CONFIG_DEFAULT_DEVICE_TREE="k3-am6528-iot2050-basic-pg2"
 CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_SYS_PROMPT="IOT2050> "
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_ENV_OFFSET_REDUND=0x6a0000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
-CONFIG_DISTRO_DEFAULTS=y
+CONFIG_PCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTSTAGE=y
 CONFIG_SHOW_BOOT_PROGRESS=y
 CONFIG_SPL_SHOW_BOOT_PROGRESS=y
@@ -108,7 +112,6 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PCI=y
 CONFIG_PCI_KEYSTONE=y
 CONFIG_PHY=y
 CONFIG_AM654_PHY=y
@@ -121,7 +124,6 @@
 CONFIG_POWER_DOMAIN=y
 CONFIG_TI_SCI_POWER_DOMAIN=y
 CONFIG_REMOTEPROC_TI_K3_R5F=y
-CONFIG_DM_RESET=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SOC_DEVICE=y
@@ -145,5 +147,4 @@
 CONFIG_WDT=y
 CONFIG_WDT_K3_RTI=y
 CONFIG_WDT_K3_RTI_LOAD_FW=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_SCROLL_ON_CLEAR_SCREEN=y
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 9b6512b..e40900f 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
 CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_SPL_GPIO=y
@@ -16,6 +17,7 @@
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-common-proc-board"
 CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -31,8 +33,9 @@
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
 CONFIG_LOGLEVEL=7
 CONFIG_SPL_MAX_SIZE=0xc0000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -200,4 +203,3 @@
 CONFIG_UFS=y
 CONFIG_CADENCE_UFS=y
 CONFIG_TI_J721E_UFS=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 00ec48b..dd44549 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
 CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MALLOC_F_LEN=0x70000
 CONFIG_SPL_GPIO=y
diff --git a/configs/j7200_hs_evm_a72_defconfig b/configs/j7200_hs_evm_a72_defconfig
deleted file mode 100644
index cfd2e80..0000000
--- a/configs/j7200_hs_evm_a72_defconfig
+++ /dev/null
@@ -1,204 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SOC_K3_J721E=y
-CONFIG_TARGET_J7200_A72_EVM=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x680000
-CONFIG_DM_GPIO=y
-CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-common-proc-board"
-CONFIG_SPL_TEXT_BASE=0x80080000
-CONFIG_DM_RESET=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_ENV_OFFSET_REDUND=0x6A0000
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-# CONFIG_PSCI_RESET is not set
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
-CONFIG_LOGLEVEL=7
-CONFIG_SPL_MAX_SIZE=0xc0000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x80a00000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
-CONFIG_SPL_DMA=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_I2C=y
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-# CONFIG_SPL_SPI_FLASH_TINY is not set
-CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_REMOTEPROC=y
-CONFIG_CMD_UFS=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)"
-CONFIG_CMD_UBI=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
-CONFIG_CLK_CCF=y
-CONFIG_CLK_TI_SCI=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_DFU_SF=y
-CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
-CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
-CONFIG_DMA_CHANNELS=y
-CONFIG_TI_K3_NAVSS_UDMA=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_TI_SCI_PROTOCOL=y
-CONFIG_DA8XX_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_DM_I2C_GPIO=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_DM_MAILBOX=y
-CONFIG_K3_SEC_PROXY=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_SPL_MMC_HS400_SUPPORT=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ADMA=y
-CONFIG_SPL_MMC_SDHCI_ADMA=y
-CONFIG_MMC_SDHCI_AM654=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_SHOW_PROGRESS=0
-CONFIG_CFI_FLASH=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_HBMC_AM654=y
-CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_MULTIPLEXER=y
-CONFIG_MUX_MMIO=y
-CONFIG_PHY_FIXED=y
-CONFIG_TI_AM65_CPSW_NUSS=y
-CONFIG_PHY=y
-CONFIG_SPL_PHY=y
-CONFIG_PHY_CADENCE_TORRENT=y
-CONFIG_PHY_J721E_WIZ=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_GENERIC is not set
-CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_GENERIC is not set
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_RAM=y
-CONFIG_SPL_RAM=y
-CONFIG_REMOTEPROC_TI_K3_R5F=y
-CONFIG_RESET_TI_SCI=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SOC_DEVICE=y
-CONFIG_SOC_DEVICE_TI_K3=y
-CONFIG_SOC_TI=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_HAS_CQSPI_REF_CLK=y
-CONFIG_CQSPI_REF_CLK=133333333
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_TI_SCI=y
-CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
-CONFIG_SPL_DM_USB_GADGET=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_CDNS3=y
-CONFIG_USB_CDNS3_GADGET=y
-CONFIG_USB_CDNS3_HOST=y
-CONFIG_SPL_USB_CDNS3_GADGET=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
-CONFIG_UFS=y
-CONFIG_CADENCE_UFS=y
-CONFIG_TI_J721E_UFS=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/j7200_hs_evm_r5_defconfig b/configs/j7200_hs_evm_r5_defconfig
deleted file mode 100644
index 94a6523..0000000
--- a/configs/j7200_hs_evm_r5_defconfig
+++ /dev/null
@@ -1,170 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x70000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SOC_K3_J721E=y
-CONFIG_K3_EARLY_CONS=y
-CONFIG_TARGET_J7200_R5_EVM=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf5bfc
-CONFIG_ENV_SIZE=0x20000
-CONFIG_DM_GPIO=y
-CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-r5-common-proc-board"
-CONFIG_SPL_TEXT_BASE=0x41c00000
-CONFIG_DM_RESET=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
-CONFIG_USE_BOOTCOMMAND=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_MAX_SIZE=0xc0000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x41cf5bfc
-CONFIG_SPL_BSS_MAX_SIZE=0xa000
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
-CONFIG_SPL_EARLY_BSS=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
-CONFIG_SPL_DMA=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_FS_EXT4=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
-# CONFIG_SPL_SPI_FLASH_TINY is not set
-CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x4000000
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
-CONFIG_SPL_CLK_CCF=y
-CONFIG_SPL_CLK_K3_PLL=y
-CONFIG_SPL_CLK_K3=y
-CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
-CONFIG_DMA_CHANNELS=y
-CONFIG_TI_K3_NAVSS_UDMA=y
-CONFIG_TI_SCI_PROTOCOL=y
-CONFIG_DA8XX_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_DM_MAILBOX=y
-CONFIG_K3_SEC_PROXY=y
-CONFIG_FS_LOADER=y
-CONFIG_SPL_FS_LOADER=y
-CONFIG_K3_AVS0=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_SPL_MMC_HS400_SUPPORT=y
-CONFIG_MMC_SDHCI=y
-CONFIG_SPL_MMC_SDHCI_ADMA=y
-CONFIG_MMC_SDHCI_AM654=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_SHOW_PROGRESS=0
-CONFIG_CFI_FLASH=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_HBMC_AM654=y
-CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_GENERIC is not set
-CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_GENERIC is not set
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_TI_POWER_DOMAIN=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_TPS65941=y
-CONFIG_DM_REGULATOR=y
-CONFIG_SPL_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_TPS65941=y
-CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
-CONFIG_RESET_TI_SCI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SOC_DEVICE=y
-CONFIG_SOC_DEVICE_TI_K3=y
-CONFIG_SOC_TI=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_HAS_CQSPI_REF_CLK=y
-CONFIG_CQSPI_REF_CLK=133333333
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_TI_SCI=y
-CONFIG_TIMER=y
-CONFIG_SPL_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
-CONFIG_SPL_DM_USB_GADGET=y
-CONFIG_USB_CDNS3=y
-CONFIG_USB_CDNS3_GADGET=y
-CONFIG_SPL_USB_CDNS3_GADGET=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_FS_EXT4=y
-CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
-CONFIG_LIB_RATIONAL=y
-CONFIG_SPL_LIB_RATIONAL=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 452e4b9..d5f37b1 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -15,6 +15,7 @@
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
 CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -29,6 +30,7 @@
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
 CONFIG_LOGLEVEL=7
@@ -204,4 +206,3 @@
 CONFIG_UFS=y
 CONFIG_CADENCE_UFS=y
 CONFIG_TI_J721E_UFS=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig
index 651df4a..c7f4462 100644
--- a/configs/j721e_hs_evm_a72_defconfig
+++ b/configs/j721e_hs_evm_a72_defconfig
@@ -16,6 +16,7 @@
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
 CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -30,6 +31,7 @@
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_fit_${boot}; run get_overlay_${boot}; run run_fit"
 CONFIG_LOGLEVEL=7
@@ -205,4 +207,3 @@
 CONFIG_UFS=y
 CONFIG_CADENCE_UFS=y
 CONFIG_TI_J721E_UFS=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 3a91df7..594c8da 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
 CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_SPL_GPIO=y
@@ -15,6 +16,7 @@
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-common-proc-board"
 CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -28,9 +30,9 @@
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
 CONFIG_LOGLEVEL=7
 CONFIG_SPL_MAX_SIZE=0xc0000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -209,4 +211,3 @@
 CONFIG_UFS=y
 CONFIG_CADENCE_UFS=y
 CONFIG_TI_J721E_UFS=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index 343e3c1..7416ba2 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
 CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MALLOC_F_LEN=0x10000
 CONFIG_SPL_GPIO=y
diff --git a/configs/j721s2_hs_evm_a72_defconfig b/configs/j721s2_hs_evm_a72_defconfig
deleted file mode 100644
index 453f2aa..0000000
--- a/configs/j721s2_hs_evm_a72_defconfig
+++ /dev/null
@@ -1,212 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SOC_K3_J721S2=y
-CONFIG_TARGET_J721S2_A72_EVM=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x680000
-CONFIG_DM_GPIO=y
-CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-common-proc-board"
-CONFIG_SPL_TEXT_BASE=0x80080000
-CONFIG_DM_RESET=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_ENV_OFFSET_REDUND=0x6A0000
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-# CONFIG_PSCI_RESET is not set
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
-CONFIG_LOGLEVEL=7
-CONFIG_SPL_MAX_SIZE=0xc0000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x80a00000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
-CONFIG_SPL_DMA=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_I2C=y
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-# CONFIG_SPL_SPI_FLASH_TINY is not set
-CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
-CONFIG_SPL_THERMAL=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_REMOTEPROC=y
-CONFIG_CMD_UFS=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),-@8m(hbmc.rootfs)"
-CONFIG_CMD_UBI=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
-CONFIG_CLK_CCF=y
-CONFIG_CLK_TI_SCI=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_DFU_SF=y
-CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
-CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
-CONFIG_DMA_CHANNELS=y
-CONFIG_TI_K3_NAVSS_UDMA=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_TI_SCI_PROTOCOL=y
-CONFIG_DA8XX_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_DM_I2C_GPIO=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_DM_MAILBOX=y
-CONFIG_K3_SEC_PROXY=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_SPL_MMC_HS400_SUPPORT=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ADMA=y
-CONFIG_SPL_MMC_SDHCI_ADMA=y
-CONFIG_MMC_SDHCI_AM654=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_SHOW_PROGRESS=0
-CONFIG_CFI_FLASH=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPI_FLASH_SOFT_RESET=y
-CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_MT35XU=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_MULTIPLEXER=y
-CONFIG_MUX_MMIO=y
-CONFIG_PHY_TI_DP83867=y
-CONFIG_PHY_FIXED=y
-CONFIG_TI_AM65_CPSW_NUSS=y
-CONFIG_PHY=y
-CONFIG_SPL_PHY=y
-CONFIG_PHY_CADENCE_TORRENT=y
-CONFIG_PHY_J721E_WIZ=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_GENERIC is not set
-CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_GENERIC is not set
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_RAM=y
-CONFIG_SPL_RAM=y
-CONFIG_REMOTEPROC_TI_K3_DSP=y
-CONFIG_REMOTEPROC_TI_K3_R5F=y
-CONFIG_RESET_TI_SCI=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SOC_DEVICE=y
-CONFIG_SOC_DEVICE_TI_K3=y
-CONFIG_SOC_TI=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_HAS_CQSPI_REF_CLK=y
-CONFIG_CQSPI_REF_CLK=133333333
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_TI_SCI=y
-CONFIG_DM_THERMAL=y
-CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
-CONFIG_SPL_DM_USB_GADGET=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_CDNS3=y
-CONFIG_USB_CDNS3_GADGET=y
-CONFIG_USB_CDNS3_HOST=y
-CONFIG_SPL_USB_CDNS3_GADGET=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
-CONFIG_UFS=y
-CONFIG_CADENCE_UFS=y
-CONFIG_TI_J721E_UFS=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/j721s2_hs_evm_r5_defconfig b/configs/j721s2_hs_evm_r5_defconfig
deleted file mode 100644
index c8433a1..0000000
--- a/configs/j721s2_hs_evm_r5_defconfig
+++ /dev/null
@@ -1,175 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SOC_K3_J721S2=y
-CONFIG_K3_EARLY_CONS=y
-CONFIG_TARGET_J721S2_R5_EVM=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_DM_GPIO=y
-CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-r5-common-proc-board"
-CONFIG_SPL_TEXT_BASE=0x41c00000
-CONFIG_DM_RESET=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_SIZE_LIMIT=0x80000
-CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
-CONFIG_USE_BOOTCOMMAND=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
-CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
-CONFIG_SPL_MAX_SIZE=0xc0000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x41c76000
-CONFIG_SPL_BSS_MAX_SIZE=0xa000
-CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
-CONFIG_SPL_EARLY_BSS=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
-CONFIG_SPL_DMA=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_FS_EXT4=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
-# CONFIG_SPL_SPI_FLASH_TINY is not set
-CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_THERMAL=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x4000000
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
-CONFIG_SPL_CLK_CCF=y
-CONFIG_SPL_CLK_K3_PLL=y
-CONFIG_SPL_CLK_K3=y
-CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
-CONFIG_DMA_CHANNELS=y
-CONFIG_TI_K3_NAVSS_UDMA=y
-CONFIG_TI_SCI_PROTOCOL=y
-CONFIG_DA8XX_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_DM_MAILBOX=y
-CONFIG_K3_SEC_PROXY=y
-CONFIG_FS_LOADER=y
-CONFIG_SPL_FS_LOADER=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_SPL_MMC_HS400_SUPPORT=y
-CONFIG_MMC_SDHCI=y
-CONFIG_SPL_MMC_SDHCI_ADMA=y
-CONFIG_MMC_SDHCI_AM654=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_SHOW_PROGRESS=0
-CONFIG_CFI_FLASH=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPI_FLASH_SOFT_RESET=y
-CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_MT35XU=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_GENERIC is not set
-CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_GENERIC is not set
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_TI_POWER_DOMAIN=y
-CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
-CONFIG_RESET_TI_SCI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SOC_DEVICE=y
-CONFIG_SOC_DEVICE_TI_K3=y
-CONFIG_SOC_TI=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_HAS_CQSPI_REF_CLK=y
-CONFIG_CQSPI_REF_CLK=133333333
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_TI_SCI=y
-CONFIG_DM_THERMAL=y
-CONFIG_TIMER=y
-CONFIG_SPL_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
-CONFIG_SPL_DM_USB_GADGET=y
-CONFIG_USB_CDNS3=y
-CONFIG_USB_CDNS3_GADGET=y
-CONFIG_SPL_USB_CDNS3_GADGET=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_FS_EXT4=y
-CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
-CONFIG_PANIC_HANG=y
-CONFIG_LIB_RATIONAL=y
-CONFIG_SPL_LIB_RATIONAL=y
diff --git a/configs/jethub_j100_defconfig b/configs/jethub_j100_defconfig
index 514005d..549d551 100644
--- a/configs/jethub_j100_defconfig
+++ b/configs/jethub_j100_defconfig
@@ -9,6 +9,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-axg-jethome-jethub-j100"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_AXG=y
 CONFIG_DEBUG_UART_BASE=0xff803000
@@ -67,4 +68,3 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/jethub_j80_defconfig b/configs/jethub_j80_defconfig
index 7f404dd..df9b8f3 100644
--- a/configs/jethub_j80_defconfig
+++ b/configs/jethub_j80_defconfig
@@ -9,6 +9,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905w-jethome-jethub-j80"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_GXL=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
@@ -71,4 +72,3 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index fb1f337..b2a39e0 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -5,6 +5,7 @@
 CONFIG_TEXT_BASE=0x80110000
 CONFIG_SYS_MALLOC_LEN=0x2500000
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1"
@@ -16,6 +17,7 @@
 CONFIG_TEGRA_ENABLE_UARTD=y
 CONFIG_TEGRA_GPU=y
 CONFIG_SYS_LOAD_ADDR=0x81000000
+CONFIG_PCI=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_CONSOLE_MUX=y
 CONFIG_SYS_STDIO_DEREGISTER=y
@@ -53,10 +55,8 @@
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
 CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_RTL8169=y
-CONFIG_PCI=y
 CONFIG_PCI_TEGRA=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_AS3722=y
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index c8fa5c9..6d9d825 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -14,6 +14,7 @@
 CONFIG_TARGET_K2E_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0fff10
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_SPL_DM_SPI=y
@@ -81,7 +82,6 @@
 CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y
 CONFIG_NAND_DAVINCI=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MARVELL=y
diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
index 6d4f599..c782bf1 100644
--- a/configs/k2e_hs_evm_defconfig
+++ b/configs/k2e_hs_evm_defconfig
@@ -12,6 +12,7 @@
 CONFIG_TARGET_K2E_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0fff10
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
@@ -56,7 +57,6 @@
 CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y
 CONFIG_NAND_DAVINCI=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MARVELL=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 4550e37..756e750 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -14,6 +14,7 @@
 CONFIG_TARGET_K2G_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc09ff10
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x40000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
@@ -80,7 +81,6 @@
 CONFIG_SYS_NAND_USE_FLASH_BBT=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig
index 1928e9e..f0de323 100644
--- a/configs/k2g_hs_evm_defconfig
+++ b/configs/k2g_hs_evm_defconfig
@@ -12,6 +12,7 @@
 CONFIG_TARGET_K2G_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc09ff10
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x40000
 CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
 CONFIG_TIMESTAMP=y
@@ -56,7 +57,6 @@
 CONFIG_SYS_NAND_USE_FLASH_BBT=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 4966aa8..74ef066 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -14,6 +14,7 @@
 CONFIG_TARGET_K2HK_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc1fff10
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_SPL_DM_SPI=y
@@ -81,7 +82,6 @@
 CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y
 CONFIG_NAND_DAVINCI=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MARVELL=y
diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig
index f7a6c6d..5bd8c28 100644
--- a/configs/k2hk_hs_evm_defconfig
+++ b/configs/k2hk_hs_evm_defconfig
@@ -12,6 +12,7 @@
 CONFIG_TARGET_K2HK_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc1fff10
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
@@ -56,7 +57,6 @@
 CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y
 CONFIG_NAND_DAVINCI=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MARVELL=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index e4c3f8c..378a71f 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -14,6 +14,7 @@
 CONFIG_TARGET_K2L_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0fff10
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_SPL_DM_SPI=y
@@ -82,7 +83,6 @@
 CONFIG_NAND_DAVINCI=y
 CONFIG_SYS_NAND_PAGE_4K=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MARVELL=y
diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig
index dd6246f..31ec302 100644
--- a/configs/k2l_hs_evm_defconfig
+++ b/configs/k2l_hs_evm_defconfig
@@ -12,6 +12,7 @@
 CONFIG_TARGET_K2L_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0fff10
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x40000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm"
@@ -60,7 +61,6 @@
 CONFIG_NAND_DAVINCI=y
 CONFIG_SYS_NAND_PAGE_4K=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MARVELL=y
diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig
index fc76b1a..38b9b2b 100644
--- a/configs/khadas-vim2_defconfig
+++ b/configs/khadas-vim2_defconfig
@@ -7,6 +7,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-khadas-vim2"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_GXM=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
@@ -70,4 +71,3 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig
index fdc5e1e..ccd6f6f 100644
--- a/configs/khadas-vim3_android_ab_defconfig
+++ b/configs/khadas-vim3_android_ab_defconfig
@@ -9,12 +9,14 @@
 CONFIG_ENV_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-khadas-vim3"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" khadas-vim3"
 CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_REMAKE_ELF=y
 CONFIG_OF_BOARD_SETUP=y
@@ -66,7 +68,6 @@
 CONFIG_ETH_DESIGNWARE_MESON8B=y
 CONFIG_MDIO_MUX_MESON_G12A=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_DW_MESON=y
 CONFIG_MESON_G12A_USB_PHY=y
 CONFIG_PINCTRL=y
@@ -109,4 +110,3 @@
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
 CONFIG_LIBAVB=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig
index 90aba62..5c3d565 100644
--- a/configs/khadas-vim3_android_defconfig
+++ b/configs/khadas-vim3_android_defconfig
@@ -9,12 +9,14 @@
 CONFIG_ENV_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-khadas-vim3"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" khadas-vim3"
 CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_REMAKE_ELF=y
 CONFIG_OF_BOARD_SETUP=y
@@ -64,7 +66,6 @@
 CONFIG_ETH_DESIGNWARE_MESON8B=y
 CONFIG_MDIO_MUX_MESON_G12A=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_DW_MESON=y
 CONFIG_MESON_G12A_USB_PHY=y
 CONFIG_PINCTRL=y
@@ -107,4 +108,3 @@
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
 CONFIG_LIBAVB=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig
index 1a7a494..d611124 100644
--- a/configs/khadas-vim3_defconfig
+++ b/configs/khadas-vim3_defconfig
@@ -8,12 +8,14 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-khadas-vim3"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" khadas-vim3"
 CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_REMAKE_ELF=y
 CONFIG_OF_BOARD_SETUP=y
@@ -52,7 +54,6 @@
 CONFIG_ETH_DESIGNWARE_MESON8B=y
 CONFIG_MDIO_MUX_MESON_G12A=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_DW_MESON=y
 CONFIG_MESON_G12A_USB_PHY=y
 CONFIG_PINCTRL=y
@@ -95,4 +96,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig
index f966018..0d6de80 100644
--- a/configs/khadas-vim3l_android_ab_defconfig
+++ b/configs/khadas-vim3l_android_ab_defconfig
@@ -9,12 +9,14 @@
 CONFIG_ENV_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-khadas-vim3l"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" khadas-vim3l"
 CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_REMAKE_ELF=y
 CONFIG_OF_BOARD_SETUP=y
@@ -66,7 +68,6 @@
 CONFIG_ETH_DESIGNWARE_MESON8B=y
 CONFIG_MDIO_MUX_MESON_G12A=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_DW_MESON=y
 CONFIG_MESON_G12A_USB_PHY=y
 CONFIG_PINCTRL=y
@@ -109,4 +110,3 @@
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
 CONFIG_LIBAVB=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig
index 34d2325..827752f 100644
--- a/configs/khadas-vim3l_android_defconfig
+++ b/configs/khadas-vim3l_android_defconfig
@@ -9,12 +9,14 @@
 CONFIG_ENV_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-khadas-vim3l"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" khadas-vim3l"
 CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_REMAKE_ELF=y
 CONFIG_OF_BOARD_SETUP=y
@@ -64,7 +66,6 @@
 CONFIG_ETH_DESIGNWARE_MESON8B=y
 CONFIG_MDIO_MUX_MESON_G12A=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_DW_MESON=y
 CONFIG_MESON_G12A_USB_PHY=y
 CONFIG_PINCTRL=y
@@ -107,4 +108,3 @@
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
 CONFIG_LIBAVB=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/khadas-vim3l_defconfig b/configs/khadas-vim3l_defconfig
index 595092e..f959d33 100644
--- a/configs/khadas-vim3l_defconfig
+++ b/configs/khadas-vim3l_defconfig
@@ -8,12 +8,14 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-khadas-vim3l"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" khadas-vim3l"
 CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_REMAKE_ELF=y
 CONFIG_OF_BOARD_SETUP=y
@@ -52,7 +54,6 @@
 CONFIG_ETH_DESIGNWARE_MESON8B=y
 CONFIG_MDIO_MUX_MESON_G12A=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_DW_MESON=y
 CONFIG_MESON_G12A_USB_PHY=y
 CONFIG_PINCTRL=y
@@ -95,4 +96,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig
index a766bdf..6a9e851 100644
--- a/configs/khadas-vim_defconfig
+++ b/configs/khadas-vim_defconfig
@@ -7,6 +7,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-khadas-vim"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_GXL=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
@@ -61,4 +62,3 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig
index 29c8653..ea2eee3 100644
--- a/configs/kmcent2_defconfig
+++ b/configs/kmcent2_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xebf40000
 CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_ENV_SOURCE_FILE="kmcent2"
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="kmcent2"
@@ -52,7 +53,6 @@
 CONFIG_CMD_UBI=y
 # CONFIG_CMD_UBIFS is not set
 CONFIG_OF_CONTROL=y
-CONFIG_ENV_SOURCE_FILE="kmcent2"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index 40e2b22..0de6ae0 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xF0000000
+CONFIG_ENV_SOURCE_FILE="km83xx"
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="kmcoge5ne"
@@ -26,7 +27,6 @@
 CONFIG_BAT0_LENGTH_256_MBYTES=y
 CONFIG_BAT0_ACCESS_RW=y
 CONFIG_BAT0_ICACHE_INHIBITED=y
-CONFIG_BAT0_ICACHE_GUARDED=y
 CONFIG_BAT0_DCACHE_INHIBITED=y
 CONFIG_BAT0_DCACHE_GUARDED=y
 CONFIG_BAT0_USER_MODE_VALID=y
@@ -37,7 +37,6 @@
 CONFIG_BAT1_LENGTH_4_MBYTES=y
 CONFIG_BAT1_ACCESS_RW=y
 CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
 CONFIG_BAT1_DCACHE_INHIBITED=y
 CONFIG_BAT1_DCACHE_GUARDED=y
 CONFIG_BAT1_USER_MODE_VALID=y
@@ -94,7 +93,6 @@
 CONFIG_BAT7_LENGTH_256_MBYTES=y
 CONFIG_BAT7_ACCESS_RW=y
 CONFIG_BAT7_ICACHE_INHIBITED=y
-CONFIG_BAT7_ICACHE_GUARDED=y
 CONFIG_BAT7_DCACHE_INHIBITED=y
 CONFIG_BAT7_DCACHE_GUARDED=y
 CONFIG_BAT7_USER_MODE_VALID=y
@@ -122,6 +120,7 @@
 CONFIG_LCRR_EADC_2=y
 CONFIG_LCRR_CLKDIV_4=y
 CONFIG_83XX_PCICLK=0x3ef1480
+# CONFIG_PCI is not set
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -159,7 +158,6 @@
 CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);app:-(ubi1);"
 CONFIG_CMD_UBI=y
 # CONFIG_CMD_UBIFS is not set
-CONFIG_ENV_SOURCE_FILE="km83xx"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR_REDUND=0xF00E0000
@@ -199,7 +197,6 @@
 CONFIG_NAND_KMETER1=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_QE_UEC=y
-# CONFIG_PCI is not set
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_QE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index f493675..568e55f 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xF0000000
 CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_ENV_SOURCE_FILE="km83xx"
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="kmeter1"
@@ -27,7 +28,6 @@
 CONFIG_BAT0_LENGTH_256_MBYTES=y
 CONFIG_BAT0_ACCESS_RW=y
 CONFIG_BAT0_ICACHE_INHIBITED=y
-CONFIG_BAT0_ICACHE_GUARDED=y
 CONFIG_BAT0_DCACHE_INHIBITED=y
 CONFIG_BAT0_DCACHE_GUARDED=y
 CONFIG_BAT0_USER_MODE_VALID=y
@@ -38,7 +38,6 @@
 CONFIG_BAT1_LENGTH_4_MBYTES=y
 CONFIG_BAT1_ACCESS_RW=y
 CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
 CONFIG_BAT1_DCACHE_INHIBITED=y
 CONFIG_BAT1_DCACHE_GUARDED=y
 CONFIG_BAT1_USER_MODE_VALID=y
@@ -101,6 +100,7 @@
 CONFIG_LCRR_DBYP_PLL_BYPASSED=y
 CONFIG_LCRR_EADC_2=y
 CONFIG_LCRR_CLKDIV_4=y
+# CONFIG_PCI is not set
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -137,7 +137,6 @@
 CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
 CONFIG_CMD_UBI=y
 # CONFIG_CMD_UBIFS is not set
-CONFIG_ENV_SOURCE_FILE="km83xx"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR_REDUND=0xF00E0000
@@ -172,6 +171,5 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_QE_UEC=y
-# CONFIG_PCI is not set
 CONFIG_QE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index 9a1b6b8..facd686 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xF0000000
+CONFIG_ENV_SOURCE_FILE="km83xx"
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="kmopti2"
@@ -21,7 +22,6 @@
 CONFIG_BAT0_LENGTH_256_MBYTES=y
 CONFIG_BAT0_ACCESS_RW=y
 CONFIG_BAT0_ICACHE_INHIBITED=y
-CONFIG_BAT0_ICACHE_GUARDED=y
 CONFIG_BAT0_DCACHE_INHIBITED=y
 CONFIG_BAT0_DCACHE_GUARDED=y
 CONFIG_BAT0_USER_MODE_VALID=y
@@ -32,7 +32,6 @@
 CONFIG_BAT1_LENGTH_4_MBYTES=y
 CONFIG_BAT1_ACCESS_RW=y
 CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
 CONFIG_BAT1_DCACHE_INHIBITED=y
 CONFIG_BAT1_DCACHE_GUARDED=y
 CONFIG_BAT1_USER_MODE_VALID=y
@@ -109,6 +108,7 @@
 CONFIG_LCRR_EADC_1=y
 CONFIG_LCRR_CLKDIV_2=y
 CONFIG_83XX_PCICLK=0x3ef1480
+# CONFIG_PCI is not set
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -144,7 +144,6 @@
 CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
 CONFIG_CMD_UBI=y
 # CONFIG_CMD_UBIFS is not set
-CONFIG_ENV_SOURCE_FILE="km83xx"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR_REDUND=0xF00E0000
@@ -181,7 +180,6 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_QE_UEC=y
-# CONFIG_PCI is not set
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_QE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index cafe39a..c00e626 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xF0000000
+CONFIG_ENV_SOURCE_FILE="km83xx"
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="kmsupm5"
@@ -21,7 +22,6 @@
 CONFIG_BAT0_LENGTH_256_MBYTES=y
 CONFIG_BAT0_ACCESS_RW=y
 CONFIG_BAT0_ICACHE_INHIBITED=y
-CONFIG_BAT0_ICACHE_GUARDED=y
 CONFIG_BAT0_DCACHE_INHIBITED=y
 CONFIG_BAT0_DCACHE_GUARDED=y
 CONFIG_BAT0_USER_MODE_VALID=y
@@ -32,7 +32,6 @@
 CONFIG_BAT1_LENGTH_4_MBYTES=y
 CONFIG_BAT1_ACCESS_RW=y
 CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
 CONFIG_BAT1_DCACHE_INHIBITED=y
 CONFIG_BAT1_DCACHE_GUARDED=y
 CONFIG_BAT1_USER_MODE_VALID=y
@@ -95,6 +94,7 @@
 CONFIG_LCRR_EADC_1=y
 CONFIG_LCRR_CLKDIV_2=y
 CONFIG_83XX_PCICLK=0x3ef1480
+# CONFIG_PCI is not set
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -129,7 +129,6 @@
 CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
 CONFIG_CMD_UBI=y
 # CONFIG_CMD_UBIFS is not set
-CONFIG_ENV_SOURCE_FILE="km83xx"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR_REDUND=0xF00E0000
@@ -164,7 +163,6 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_QE_UEC=y
-# CONFIG_PCI is not set
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_QE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index 0b88ebd..8122124 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xF0000000
+CONFIG_ENV_SOURCE_FILE="km83xx"
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="kmtepr2"
@@ -21,7 +22,6 @@
 CONFIG_BAT0_LENGTH_256_MBYTES=y
 CONFIG_BAT0_ACCESS_RW=y
 CONFIG_BAT0_ICACHE_INHIBITED=y
-CONFIG_BAT0_ICACHE_GUARDED=y
 CONFIG_BAT0_DCACHE_INHIBITED=y
 CONFIG_BAT0_DCACHE_GUARDED=y
 CONFIG_BAT0_USER_MODE_VALID=y
@@ -32,7 +32,6 @@
 CONFIG_BAT1_LENGTH_4_MBYTES=y
 CONFIG_BAT1_ACCESS_RW=y
 CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
 CONFIG_BAT1_DCACHE_INHIBITED=y
 CONFIG_BAT1_DCACHE_GUARDED=y
 CONFIG_BAT1_USER_MODE_VALID=y
@@ -109,6 +108,7 @@
 CONFIG_LCRR_EADC_1=y
 CONFIG_LCRR_CLKDIV_2=y
 CONFIG_83XX_PCICLK=0x3ef1480
+# CONFIG_PCI is not set
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -143,7 +143,6 @@
 CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
 CONFIG_CMD_UBI=y
 # CONFIG_CMD_UBIFS is not set
-CONFIG_ENV_SOURCE_FILE="km83xx"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR_REDUND=0xF00E0000
@@ -180,7 +179,6 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_QE_UEC=y
-# CONFIG_PCI is not set
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_QE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig
index 45fa507..8db5867 100644
--- a/configs/koelsch_defconfig
+++ b/configs/koelsch_defconfig
@@ -29,6 +29,7 @@
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x50000000
 CONFIG_ENV_ADDR=0xC0000
+CONFIG_PCI=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
@@ -87,7 +88,6 @@
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
 CONFIG_SH_ETHER=y
-CONFIG_PCI=y
 CONFIG_PCI_RCAR_GEN2=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig
index 155e3ac..0dbf7ea 100644
--- a/configs/kontron-sl-mx6ul_defconfig
+++ b/configs/kontron-sl-mx6ul_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xF0000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -76,7 +77,6 @@
 CONFIG_MTD_SPI_NAND=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig
index d630f60..9558cf1 100644
--- a/configs/kontron-sl-mx8mm_defconfig
+++ b/configs/kontron-sl-mx8mm_defconfig
@@ -5,6 +5,7 @@
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=80000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x1E0000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -99,7 +100,6 @@
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=80000000
 CONFIG_SPI_FLASH_MACRONIX=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig
index 1226227..dd20762 100644
--- a/configs/kontron_sl28_defconfig
+++ b/configs/kontron_sl28_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-kontron-sl28"
 CONFIG_SPL_TEXT_BASE=0x18010000
 CONFIG_SYS_FSL_SDHC_CLK_DIV=1
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x18009ff0
@@ -130,7 +131,6 @@
 CONFIG_WDT_SL28CPLD=y
 CONFIG_WDT_SP805=y
 CONFIG_OF_LIBFDT_ASSUME_MASK=0x0
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_SET_TIME=y
 CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
 CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 666ed4a..d232f5c 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -10,6 +10,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
 CONFIG_SPL_TEXT_BASE=0x10081000
@@ -54,7 +55,6 @@
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PINCTRL=y
 CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index c9dbf69..bf6fac6 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig
@@ -29,6 +29,7 @@
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x50000000
 CONFIG_ENV_ADDR=0xC0000
+CONFIG_PCI=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
@@ -89,7 +90,6 @@
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
 CONFIG_SH_ETHER=y
-CONFIG_PCI=y
 CONFIG_PCI_RCAR_GEN2=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig
index bec73ca..d739e18 100644
--- a/configs/legoev3_defconfig
+++ b/configs/legoev3_defconfig
@@ -8,6 +8,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80010000
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DEFAULT_DEVICE_TREE="da850-lego-ev3"
 CONFIG_SYS_LOAD_ADDR=0xc0700000
@@ -50,7 +51,6 @@
 CONFIG_SYS_I2C_DAVINCI=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig
index 4e08de3..0fa7f3d 100644
--- a/configs/libretech-ac_defconfig
+++ b/configs/libretech-ac_defconfig
@@ -10,6 +10,7 @@
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s805x-libretech-ac"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_GXL=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
@@ -89,4 +90,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig
index be5a318..dee03b3 100644
--- a/configs/libretech-cc_defconfig
+++ b/configs/libretech-cc_defconfig
@@ -7,6 +7,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-libretech-cc"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_GXL=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
@@ -72,4 +73,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig
index ea71f05..628c6ba 100644
--- a/configs/libretech-cc_v2_defconfig
+++ b/configs/libretech-cc_v2_defconfig
@@ -9,6 +9,7 @@
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-libretech-cc-v2"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_GXL=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
@@ -76,4 +77,3 @@
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_MESON=y
 CONFIG_VIDEO_DT_SIMPLEFB=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/libretech-s905d-pc_defconfig b/configs/libretech-s905d-pc_defconfig
index 6c775cb..1c8787c 100644
--- a/configs/libretech-s905d-pc_defconfig
+++ b/configs/libretech-s905d-pc_defconfig
@@ -10,6 +10,7 @@
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905d-libretech-pc"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_GXL=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
@@ -83,4 +84,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/libretech-s912-pc_defconfig b/configs/libretech-s912-pc_defconfig
index 6e9e1a6..170492e 100644
--- a/configs/libretech-s912-pc_defconfig
+++ b/configs/libretech-s912-pc_defconfig
@@ -9,6 +9,7 @@
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-s912-libretech-pc"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_GXM=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
@@ -82,4 +83,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index b12f127..2a18060 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -32,7 +32,6 @@
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-lion-haikou.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
index b32a8e1..7e12f6e 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
+CONFIG_PCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
@@ -55,7 +56,6 @@
 CONFIG_FSL_PFE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_SYS_NS16550_SERIAL=y
diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig
index f2ed3ab..3c9a748 100644
--- a/configs/ls1012afrdm_tfa_defconfig
+++ b/configs/ls1012afrdm_tfa_defconfig
@@ -13,6 +13,7 @@
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
@@ -53,7 +54,6 @@
 CONFIG_FSL_PFE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_SYS_NS16550_SERIAL=y
diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
index fc857d4..4e5079d 100644
--- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
@@ -10,6 +10,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
 CONFIG_FSL_LS_PPA=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
@@ -57,7 +58,6 @@
 CONFIG_FSL_PFE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig
index 68b87b2..b944f80 100644
--- a/configs/ls1012afrwy_qspi_defconfig
+++ b/configs/ls1012afrwy_qspi_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
 CONFIG_FSL_LS_PPA=y
 CONFIG_ENV_ADDR=0x401D0000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -60,7 +61,6 @@
 CONFIG_FSL_PFE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
index dd6870a..56dcbcc 100644
--- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
@@ -10,6 +10,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
@@ -55,7 +56,6 @@
 CONFIG_FSL_PFE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig
index 48ec006..90083fa 100644
--- a/configs/ls1012afrwy_tfa_defconfig
+++ b/configs/ls1012afrwy_tfa_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -58,7 +59,6 @@
 CONFIG_FSL_PFE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index efa6023..34bdb1a 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x300000
 CONFIG_ENV_SECT_SIZE=0x40000
@@ -13,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -69,7 +71,6 @@
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=10000000
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -79,7 +80,6 @@
 CONFIG_FSL_PFE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF8563=y
diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
index 2f1c5aa..dc0f1c5 100644
--- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
@@ -5,12 +5,14 @@
 CONFIG_TEXT_BASE=0x82000000
 CONFIG_SYS_MALLOC_LEN=0x500000
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -59,7 +61,6 @@
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=10000000
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -69,7 +70,6 @@
 CONFIG_FSL_PFE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF8563=y
diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig
index a4d6a51..7884f38 100644
--- a/configs/ls1012aqds_tfa_defconfig
+++ b/configs/ls1012aqds_tfa_defconfig
@@ -5,6 +5,7 @@
 CONFIG_TEXT_BASE=0x82000000
 CONFIG_SYS_MALLOC_LEN=0x500000
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x500000
 CONFIG_ENV_SECT_SIZE=0x40000
@@ -13,6 +14,7 @@
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -68,7 +70,6 @@
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=10000000
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -78,7 +79,6 @@
 CONFIG_FSL_PFE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF8563=y
diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
index f3bfdb6..dcd18b4 100644
--- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
@@ -11,6 +11,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
@@ -60,7 +61,6 @@
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index 4bc318a..10fe826 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -14,6 +14,7 @@
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ENV_ADDR=0x40300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -63,7 +64,6 @@
 CONFIG_FSL_PFE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
index 89b94bc..336692b 100644
--- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
@@ -11,6 +11,7 @@
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
@@ -59,7 +60,6 @@
 CONFIG_FSL_PFE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig
index d396d52..647e8ea 100644
--- a/configs/ls1012ardb_tfa_defconfig
+++ b/configs/ls1012ardb_tfa_defconfig
@@ -13,6 +13,7 @@
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -60,7 +61,6 @@
 CONFIG_FSL_PFE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig
index e6cd6a7..0c72f8a 100644
--- a/configs/ls1021aiot_qspi_defconfig
+++ b/configs/ls1021aiot_qspi_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
 CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 # CONFIG_DEEP_SLEEP is not set
 CONFIG_LAYERSCAPE_NS_ACCESS=y
@@ -64,7 +65,6 @@
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
index 9c298b0..cfe9cc4 100644
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig
@@ -19,6 +19,7 @@
 CONFIG_SPL_STACK=0x1001d000
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 # CONFIG_DEEP_SLEEP is not set
 CONFIG_LAYERSCAPE_NS_ACCESS=y
@@ -92,7 +93,6 @@
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_U_QE=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index e694619..b28ae07 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_ENV_ADDR=0x60300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -92,7 +93,6 @@
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x60940000
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index e4e49ba..136246b 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_ENV_ADDR=0x60300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -92,7 +93,6 @@
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x60940000
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index de632a3..1921510 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -21,6 +21,7 @@
 CONFIG_SPL_STACK=0x1001d000
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -126,7 +127,6 @@
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index 40228ac..78eb747 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
@@ -91,7 +92,6 @@
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x60940000
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index 47eb897..04223a9 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_ENV_ADDR=0x60300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -94,7 +95,6 @@
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x60940000
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index 7dad323..3a7bc40 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_ENV_ADDR=0x60300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -94,7 +95,6 @@
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x60940000
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index ebf6fdb..cfb6bcf 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -80,7 +81,6 @@
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index 27784e3..dbd9797 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -22,6 +22,7 @@
 CONFIG_SPL_STACK=0x1001d000
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -123,7 +124,6 @@
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index d8973bf..9f50862 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -22,6 +22,7 @@
 CONFIG_SPL_STACK=0x1001d000
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -108,7 +109,6 @@
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig
index 065e006..f0ab507 100644
--- a/configs/ls1021atsn_qspi_defconfig
+++ b/configs/ls1021atsn_qspi_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
 CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -66,7 +67,6 @@
 CONFIG_SJA1105=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SCSI_AHCI_PLAT=y
 CONFIG_SYS_NS16550_SERIAL=y
diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
index 76d9d57..ffb8663 100644
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig
@@ -19,6 +19,7 @@
 CONFIG_SPL_STACK=0x1001d000
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -93,7 +94,6 @@
 CONFIG_SJA1105=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SCSI_AHCI_PLAT=y
 CONFIG_SYS_NS16550_SERIAL=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index d48d3d7..dcb48c3 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
 CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
@@ -76,7 +77,6 @@
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x60940000
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 845a8a5..61e9edf 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_ENV_ADDR=0x60300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -79,7 +80,6 @@
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x60940000
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index 955376a..9975f6a 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart"
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_ENV_ADDR=0x60300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -79,7 +80,6 @@
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x60940000
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index 90f6833..2e7d786 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
 CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -74,7 +75,6 @@
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550_SERIAL=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index ee6acb4..26450ae 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -21,6 +21,7 @@
 CONFIG_SPL_STACK=0x1001d000
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_PCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -107,7 +108,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_U_QE=y
 CONFIG_SYS_QE_FW_ADDR=0x940000
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index d7beb15..f4f47de 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -21,6 +21,7 @@
 CONFIG_SPL_STACK=0x1001d000
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -108,7 +109,6 @@
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550_SERIAL=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 4bc4ed6..e77a6a5 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -21,6 +21,7 @@
 CONFIG_SPL_STACK=0x1001d000
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -102,7 +103,6 @@
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550_SERIAL=y
diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
index 15ac90f..63c5506 100644
--- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
@@ -11,8 +11,10 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart"
 CONFIG_FSPI_AHB_EN_4BYTE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_SYS_FSL_NUM_CC_PLLS=3
@@ -79,7 +81,6 @@
 CONFIG_MSCC_FELIX_SWITCH=y
 CONFIG_MDIO_MUX_I2CREG=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_ECAM_GENERIC=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
@@ -98,5 +99,4 @@
 CONFIG_WDT=y
 CONFIG_WDT_SP805=y
 CONFIG_RSA=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig
index 78dd20a..149bc57 100644
--- a/configs/ls1028aqds_tfa_defconfig
+++ b/configs/ls1028aqds_tfa_defconfig
@@ -13,9 +13,11 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart"
 CONFIG_FSPI_AHB_EN_4BYTE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x20500000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_SYS_FSL_NUM_CC_PLLS=3
 CONFIG_FSL_QIXIS=y
@@ -85,7 +87,6 @@
 CONFIG_MSCC_FELIX_SWITCH=y
 CONFIG_MDIO_MUX_I2CREG=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_ECAM_GENERIC=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
@@ -103,5 +104,4 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_WDT=y
 CONFIG_WDT_SP805=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig
index e1b9f6e..4750a57 100644
--- a/configs/ls1028aqds_tfa_lpuart_defconfig
+++ b/configs/ls1028aqds_tfa_lpuart_defconfig
@@ -12,9 +12,11 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-lpuart"
 CONFIG_FSPI_AHB_EN_4BYTE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x20500000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_SYS_FSL_NUM_CC_PLLS=3
 CONFIG_FSL_QIXIS=y
@@ -83,7 +85,6 @@
 CONFIG_FSL_ENETC=y
 CONFIG_MDIO_MUX_I2CREG=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_ECAM_GENERIC=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
@@ -103,5 +104,4 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_WDT=y
 CONFIG_WDT_SP805=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
index 2c3c9bd..9be2f32 100644
--- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
@@ -11,8 +11,10 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb"
 CONFIG_FSPI_AHB_EN_4BYTE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_SYS_FSL_NUM_CC_PLLS=3
@@ -73,7 +75,6 @@
 CONFIG_E1000=y
 CONFIG_MSCC_FELIX_SWITCH=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_ECAM_GENERIC=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
@@ -92,5 +93,4 @@
 CONFIG_WDT=y
 CONFIG_WDT_SP805=y
 CONFIG_RSA=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig
index 3384b98..d158187 100644
--- a/configs/ls1028ardb_tfa_defconfig
+++ b/configs/ls1028ardb_tfa_defconfig
@@ -13,9 +13,11 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb"
 CONFIG_FSPI_AHB_EN_4BYTE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x20500000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_SYS_FSL_NUM_CC_PLLS=3
 CONFIG_FSL_QIXIS=y
@@ -79,7 +81,6 @@
 CONFIG_E1000=y
 CONFIG_MSCC_FELIX_SWITCH=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_ECAM_GENERIC=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
@@ -101,5 +102,4 @@
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_WDT=y
 CONFIG_WDT_SP805=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index 2f10462..18bf4bd 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -16,6 +16,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_FSL_LS_PPA=y
 CONFIG_ENV_ADDR=0x60300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -95,7 +96,6 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index 5517081..9dcbe71 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -16,6 +16,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart"
 CONFIG_FSL_LS_PPA=y
 CONFIG_ENV_ADDR=0x60300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -95,7 +96,6 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index 76410d6..3ab81d2 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -22,6 +22,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x1001d000
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -126,7 +127,6 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index d5ebb90..67d8288 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -16,6 +16,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_FSL_LS_PPA=y
 CONFIG_ENV_ADDR=0x60300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -96,7 +97,6 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index afcc249..fa0b47f 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -17,6 +17,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_FSL_LS_PPA=y
 CONFIG_ENV_ADDR=0x40300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -85,7 +86,6 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index 31817f3..09e2240 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -23,6 +23,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x1001e000
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -123,7 +124,6 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index d5f4d1c..7480c29 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -23,6 +23,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x1001e000
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -111,7 +112,6 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
index 39a317d..3e1d234 100644
--- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
@@ -94,7 +95,6 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig
index 6c35208..2c50162 100644
--- a/configs/ls1043aqds_tfa_defconfig
+++ b/configs/ls1043aqds_tfa_defconfig
@@ -17,6 +17,7 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x60500000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -103,7 +104,6 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index e120c40..069a8dc 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_FSL_LS_PPA=y
+CONFIG_PCI=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
@@ -82,7 +83,6 @@
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x60900000
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x60940000
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index fca5d91..e796c0a 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -16,6 +16,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_FSL_LS_PPA=y
 CONFIG_ENV_ADDR=0x60300000
+CONFIG_PCI=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -85,7 +86,6 @@
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x60900000
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x60940000
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
index 18e00c7..1224375 100644
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
@@ -17,6 +17,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x1001d000
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
@@ -107,7 +108,6 @@
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x900000
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550_SERIAL=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index 989b8e0..e72102c 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -22,6 +22,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x1001d000
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -114,7 +115,6 @@
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x900000
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_SYS_NS16550_SERIAL=y
diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
index 405b71b..c1d2143 100644
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
@@ -18,6 +18,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x1001e000
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
@@ -106,7 +107,6 @@
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x940000
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index 3a0fb1d..6252886 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -23,6 +23,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x1001e000
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -111,7 +112,6 @@
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x900000
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x940000
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
index 1dd2fe3..cf4623e 100644
--- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
@@ -81,7 +82,6 @@
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x900000
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x940000
 CONFIG_SYS_NS16550_SERIAL=y
diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
index 86f2ece..15e2916 100644
--- a/configs/ls1043ardb_tfa_defconfig
+++ b/configs/ls1043ardb_tfa_defconfig
@@ -17,6 +17,7 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x60500000
+CONFIG_PCI=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -87,7 +88,6 @@
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x900000
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x940000
 CONFIG_SYS_NS16550_SERIAL=y
diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
index f7e5b38..8d6a137 100644
--- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
@@ -11,6 +11,7 @@
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
@@ -64,7 +65,6 @@
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550_SERIAL=y
diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig
index e2061c8..e5d2b55 100644
--- a/configs/ls1046afrwy_tfa_defconfig
+++ b/configs/ls1046afrwy_tfa_defconfig
@@ -14,6 +14,7 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x40500000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -71,7 +72,6 @@
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x900000
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig
index 395cb25..5bdcc86 100644
--- a/configs/ls1046aqds_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_SECURE_BOOT_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
 CONFIG_FSL_LS_PPA=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
@@ -93,7 +94,6 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
index 931759f..51aa5dc 100644
--- a/configs/ls1046aqds_defconfig
+++ b/configs/ls1046aqds_defconfig
@@ -16,6 +16,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
 CONFIG_FSL_LS_PPA=y
 CONFIG_ENV_ADDR=0x60300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -96,7 +97,6 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig
index 6bdf758..9c1df24 100644
--- a/configs/ls1046aqds_lpuart_defconfig
+++ b/configs/ls1046aqds_lpuart_defconfig
@@ -16,6 +16,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart"
 CONFIG_FSL_LS_PPA=y
 CONFIG_ENV_ADDR=0x60300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -96,7 +97,6 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig
index c4b17d6..3c44732 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -22,6 +22,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x1001f000
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -125,7 +126,6 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig
index 8498f6f..f3796f3 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -17,6 +17,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
 CONFIG_FSL_LS_PPA=y
 CONFIG_ENV_ADDR=0x40300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -86,7 +87,6 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig
index cd7ee60..9692fc4 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -23,6 +23,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x10020000
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -125,7 +126,6 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig
index 76d5b3f..621f859 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -23,6 +23,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x10020000
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -113,7 +114,6 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
index 9a9db30..9cb79e1 100644
--- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
@@ -94,7 +95,6 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig
index c277f25..fde5659 100644
--- a/configs/ls1046aqds_tfa_defconfig
+++ b/configs/ls1046aqds_tfa_defconfig
@@ -17,6 +17,7 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x60500000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -104,7 +105,6 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
index d820f64..ef8c9a3 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -23,6 +23,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x10020000
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -104,7 +105,6 @@
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x900000
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_POWER_LEGACY=y
diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
index d32a3d5..3cefae0 100644
--- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
@@ -15,6 +15,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
@@ -79,7 +80,6 @@
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x40900000
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_POWER_LEGACY=y
diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
index 735fcbf..02979dd 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -18,6 +18,7 @@
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ENV_ADDR=0x40300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -83,7 +84,6 @@
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x40900000
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_POWER_LEGACY=y
diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig
index b93efd0..5b765d5 100644
--- a/configs/ls1046ardb_qspi_spl_defconfig
+++ b/configs/ls1046ardb_qspi_spl_defconfig
@@ -25,6 +25,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x10020000
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -111,7 +112,6 @@
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x40900000
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_POWER_LEGACY=y
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
index 7ca3f76..b69b71a 100644
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
@@ -22,6 +22,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x10020000
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -102,7 +103,6 @@
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_POWER_LEGACY=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index 3905576..3a41d8a 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -23,6 +23,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x10020000
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -104,7 +105,6 @@
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x900000
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_POWER_LEGACY=y
diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
index 4426121..3eaa985 100644
--- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
@@ -15,6 +15,7 @@
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
@@ -73,7 +74,6 @@
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x900000
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_POWER_LEGACY=y
diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
index fb0907a..7e8d86d 100644
--- a/configs/ls1046ardb_tfa_defconfig
+++ b/configs/ls1046ardb_tfa_defconfig
@@ -18,6 +18,7 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x40500000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
@@ -79,7 +80,6 @@
 CONFIG_FMAN_ENET=y
 CONFIG_SYS_FMAN_FW_ADDR=0x900000
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_POWER_LEGACY=y
diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig
index d4793f8..f53fbad 100644
--- a/configs/ls1088aqds_defconfig
+++ b/configs/ls1088aqds_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
 CONFIG_FSL_LS_PPA=y
 CONFIG_ENV_ADDR=0x80300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
@@ -97,7 +98,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
index ff57140..921240c 100644
--- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
@@ -11,6 +11,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_FSL_USE_PCA9547_MUX=y
@@ -89,7 +90,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig
index 21d3a38..45c93c8 100644
--- a/configs/ls1088aqds_qspi_defconfig
+++ b/configs/ls1088aqds_qspi_defconfig
@@ -14,6 +14,7 @@
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ENV_ADDR=0x20300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
@@ -92,7 +93,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig
index 1d429a0..6022152 100644
--- a/configs/ls1088aqds_sdcard_ifc_defconfig
+++ b/configs/ls1088aqds_sdcard_ifc_defconfig
@@ -19,6 +19,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x18009ff0
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
@@ -117,7 +118,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig
index a0a8a2b..b8b66ef 100644
--- a/configs/ls1088aqds_sdcard_qspi_defconfig
+++ b/configs/ls1088aqds_sdcard_qspi_defconfig
@@ -19,6 +19,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x18009ff0
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
@@ -112,7 +113,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig
index 09e273a..05f5496 100644
--- a/configs/ls1088aqds_tfa_defconfig
+++ b/configs/ls1088aqds_tfa_defconfig
@@ -15,6 +15,7 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x20500000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
@@ -113,7 +114,6 @@
 CONFIG_MII=y
 CONFIG_MDIO_MUX_I2CREG=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
index bc935f0..48bd56b 100644
--- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
@@ -11,6 +11,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_FSL_USE_PCA9547_MUX=y
@@ -86,7 +87,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550_SERIAL=y
diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig
index 9e745e0..7dcd12d 100644
--- a/configs/ls1088ardb_qspi_defconfig
+++ b/configs/ls1088ardb_qspi_defconfig
@@ -14,6 +14,7 @@
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ENV_ADDR=0x20300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
@@ -89,7 +90,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550_SERIAL=y
diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
index 3cfe179..8cbe0f8 100644
--- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
@@ -18,6 +18,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x18009ff0
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
@@ -108,7 +109,6 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SCSI_AHCI_PLAT=y
 CONFIG_SYS_NS16550_SERIAL=y
diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig
index 2e76aa9..6a89160 100644
--- a/configs/ls1088ardb_sdcard_qspi_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_defconfig
@@ -19,6 +19,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x18009ff0
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
@@ -109,7 +110,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550_SERIAL=y
diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
index 558958c..4291aa9 100644
--- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
@@ -12,6 +12,7 @@
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_FSL_USE_PCA9547_MUX=y
@@ -85,7 +86,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig
index 89f8141..de3a082 100644
--- a/configs/ls1088ardb_tfa_defconfig
+++ b/configs/ls1088ardb_tfa_defconfig
@@ -15,6 +15,7 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x20500000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
@@ -91,7 +92,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index 7d7b4d8..9e8efc7 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -10,6 +10,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
 CONFIG_FSL_LS_PPA=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_FSL_USE_PCA9547_MUX=y
@@ -91,7 +92,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index 6de99f3..7d00c2f 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
 CONFIG_FSL_LS_PPA=y
 CONFIG_ENV_ADDR=0x80300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_FSL_QIXIS=y
@@ -94,7 +95,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 8787b9a..291a5de 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -18,6 +18,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x18009ff0
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_FSL_QIXIS=y
@@ -107,7 +108,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index 0ef4d12..6a262f6 100644
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -12,6 +12,7 @@
 CONFIG_ENV_OFFSET=0x300000
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_FSL_QIXIS=y
@@ -87,7 +88,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig
index 2fa28a2..13975f3 100644
--- a/configs/ls2080aqds_sdcard_defconfig
+++ b/configs/ls2080aqds_sdcard_defconfig
@@ -20,6 +20,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x18009ff0
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_FSL_QIXIS=y
@@ -101,7 +102,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index 9d5a651..51c13e0 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -10,6 +10,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
 CONFIG_FSL_LS_PPA=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_FSL_USE_PCA9547_MUX=y
@@ -89,7 +90,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_RTC_DS3231=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index 77cfad3..f69ba92 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
 CONFIG_FSL_LS_PPA=y
 CONFIG_ENV_ADDR=0x80300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
@@ -92,7 +93,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_RTC_DS3231=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index 9e9a5d8..1fe85e6 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -18,6 +18,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x18009ff0
 CONFIG_SPL=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
@@ -111,7 +112,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_RTC_DS3231=y
diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig
index 0380bc0..abe9953 100644
--- a/configs/ls2081ardb_defconfig
+++ b/configs/ls2081ardb_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2081a-rdb"
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
@@ -79,7 +80,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_RTC_PCF8563=y
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig
index 9f10dd2..df87998 100644
--- a/configs/ls2088aqds_tfa_defconfig
+++ b/configs/ls2088aqds_tfa_defconfig
@@ -14,6 +14,7 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x580500000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_FSL_QIXIS=y
@@ -106,7 +107,6 @@
 CONFIG_MII=y
 CONFIG_MDIO_MUX_I2CREG=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
index e9fbe8d..860218d 100644
--- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_FSL_USE_PCA9547_MUX=y
@@ -78,7 +79,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_RTC_DS3231=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig
index 3b0c959..c176acd 100644
--- a/configs/ls2088ardb_qspi_defconfig
+++ b/configs/ls2088ardb_qspi_defconfig
@@ -15,6 +15,7 @@
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ENV_ADDR=0x20300000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
@@ -85,7 +86,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_RTC_DS3231=y
 CONFIG_DM_SCSI=y
diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
index f110bee..508261a 100644
--- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
@@ -13,6 +13,7 @@
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_NXP_ESBC=y
 CONFIG_FSL_USE_PCA9547_MUX=y
@@ -95,7 +96,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS3231=y
diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index 6ff4e49..f01e1a5 100644
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig
@@ -16,6 +16,7 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x580500000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
@@ -103,7 +104,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS3231=y
diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig
index 5974fb8..d7c77f8 100644
--- a/configs/lschlv2_defconfig
+++ b/configs/lschlv2_defconfig
@@ -10,6 +10,7 @@
 CONFIG_TEXT_BASE=0x600000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_TARGET_LSXL=y
+CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x70000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -55,7 +56,6 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_MDIO=y
 CONFIG_MVGBE=y
diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig
index 91b179b..d729bcb 100644
--- a/configs/lsxhl_defconfig
+++ b/configs/lsxhl_defconfig
@@ -11,6 +11,7 @@
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_TARGET_LSXL=y
 CONFIG_LSXHL=y
+CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x70000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -56,7 +57,6 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_MDIO=y
 CONFIG_MVGBE=y
diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
index ea3f2ac..4e387f3 100644
--- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
@@ -13,6 +13,7 @@
 CONFIG_FSPI_AHB_EN_4BYTE=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_NXP_ESBC=y
@@ -91,7 +92,6 @@
 CONFIG_MII=y
 CONFIG_MDIO_MUX_I2CREG=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_RTC=y
diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index 9be7ac9..4fde9d5 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -16,6 +16,7 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x20500000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_FSL_USE_PCA9547_MUX=y
@@ -98,7 +99,6 @@
 CONFIG_MII=y
 CONFIG_MDIO_MUX_I2CREG=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_RTC=y
diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
index e82e623..39a52e6 100644
--- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
@@ -14,6 +14,7 @@
 CONFIG_FSPI_AHB_EN_4BYTE=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_NXP_ESBC=y
@@ -82,7 +83,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_RTC=y
diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index 10ed60a..e2fbde6 100644
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -17,6 +17,7 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x20500000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_FSL_USE_PCA9547_MUX=y
@@ -91,7 +92,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_RTC=y
diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig
index 42b6421..1b43c84 100644
--- a/configs/lx2160ardb_tfa_stmm_defconfig
+++ b/configs/lx2160ardb_tfa_stmm_defconfig
@@ -17,6 +17,7 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x20500000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_FSL_USE_PCA9547_MUX=y
@@ -91,7 +92,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_RTC=y
diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
index ad1b123..9507b7f 100644
--- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
@@ -13,6 +13,7 @@
 CONFIG_FSPI_AHB_EN_4BYTE=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_NXP_ESBC=y
@@ -92,7 +93,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_MDIO_MUX_I2CREG=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig
index ee37dfd..a24b1b3 100644
--- a/configs/lx2162aqds_tfa_defconfig
+++ b/configs/lx2162aqds_tfa_defconfig
@@ -16,6 +16,7 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x20500000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_FSL_USE_PCA9547_MUX=y
@@ -100,7 +101,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_MDIO_MUX_I2CREG=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig
index 0fe96e3..ba0151c 100644
--- a/configs/lx2162aqds_tfa_verified_boot_defconfig
+++ b/configs/lx2162aqds_tfa_verified_boot_defconfig
@@ -16,6 +16,7 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x20500000
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_FSL_USE_PCA9547_MUX=y
@@ -101,7 +102,6 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_MDIO_MUX_I2CREG=y
-CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index 27c5ebe..e3fd682 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TEXT_BASE=0x17800000
 CONFIG_SYS_MALLOC_LEN=0xa00000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_ENV_SECT_SIZE=0x2000
@@ -41,7 +42,6 @@
 CONFIG_SYS_I2C_MXC=y
 CONFIG_FSL_USDHC=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ATHEROS=y
diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig
index e5f7a64..6afddd2 100644
--- a/configs/mccmon6_nor_defconfig
+++ b/configs/mccmon6_nor_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_IMX_CONFIG="board/liebherr/mccmon6/mon6_imximage_nor.cfg"
@@ -70,7 +71,6 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_FLASH_VERIFY=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
index d99d80f..260bf1f 100644
--- a/configs/mccmon6_sd_defconfig
+++ b/configs/mccmon6_sd_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_IMX_CONFIG="board/liebherr/mccmon6/mon6_imximage_sd.cfg"
@@ -68,7 +69,6 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_FLASH_VERIFY=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig
index e48b93b..c03c8ec 100644
--- a/configs/microchip_mpfs_icicle_defconfig
+++ b/configs/microchip_mpfs_icicle_defconfig
@@ -11,7 +11,6 @@
 CONFIG_TARGET_MICROCHIP_ICICLE=y
 CONFIG_ARCH_RV64I=y
 CONFIG_RISCV_SMODE=y
-CONFIG_STANDALONE_LOAD_ADDR=0x80200000
 CONFIG_FIT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_DISPLAY_CPUINFO=y
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index fad85ff..7ee1475 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-miqi"
 CONFIG_SPL_TEXT_BASE=0xff704000
@@ -63,7 +64,6 @@
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PINCTRL=y
diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig
index b7dcd16..bf851cb 100644
--- a/configs/mk808_defconfig
+++ b/configs/mk808_defconfig
@@ -12,6 +12,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x78000000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3066a-mk808"
 CONFIG_SPL_TEXT_BASE=0x60000000
@@ -92,7 +93,6 @@
 CONFIG_SPL_MMC_UHS_SUPPORT=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_PINCTRL=y
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
diff --git a/configs/mt7621_rfb_defconfig b/configs/mt7621_rfb_defconfig
index 06c04e5..b50fbec 100644
--- a/configs/mt7621_rfb_defconfig
+++ b/configs/mt7621_rfb_defconfig
@@ -4,6 +4,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7621-rfb"
 CONFIG_SPL_SERIAL=y
@@ -61,7 +62,6 @@
 # CONFIG_MMC_QUIRKS is not set
 # CONFIG_MMC_HW_PARTITIONING is not set
 CONFIG_MMC_MTK=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig
index c09c222..a3ad927 100644
--- a/configs/mt7622_rfb_defconfig
+++ b/configs/mt7622_rfb_defconfig
@@ -10,6 +10,7 @@
 CONFIG_DEBUG_UART_BASE=0x11002000
 CONFIG_DEBUG_UART_CLOCK=25000000
 CONFIG_SYS_LOAD_ADDR=0x4007ff28
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_DEFAULT_FDT_FILE="mt7622-rfb"
@@ -45,7 +46,6 @@
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHY_FIXED=y
 CONFIG_MEDIATEK_ETH=y
-CONFIG_PCI=y
 CONFIG_PCIE_MEDIATEK=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
diff --git a/configs/mt7986a_bpir3_emmc_defconfig b/configs/mt7986a_bpir3_emmc_defconfig
index 2d4876f..5b76512 100644
--- a/configs/mt7986a_bpir3_emmc_defconfig
+++ b/configs/mt7986a_bpir3_emmc_defconfig
@@ -7,15 +7,15 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x80000
 CONFIG_ENV_OFFSET=0x300000
-CONFIG_DEFAULT_DEVICE_TREE="mt7986a-emmc-rfb"
-CONFIG_SYS_PROMPT="MT7986> "
+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-emmc"
+CONFIG_SYS_PROMPT="BPI-R3> "
 CONFIG_TARGET_MT7986=y
 CONFIG_DEBUG_UART_BASE=0x11002000
 CONFIG_DEBUG_UART_CLOCK=40000000
 CONFIG_SYS_LOAD_ADDR=0x46000000
 CONFIG_DEBUG_UART=y
 # CONFIG_AUTOBOOT is not set
-CONFIG_DEFAULT_FDT_FILE="mt7986a-emmc-rfb"
+CONFIG_DEFAULT_FDT_FILE="mt7986a-bpi-r3-emmc"
 CONFIG_LOGLEVEL=7
 CONFIG_LOG=y
 CONFIG_SYS_CBSIZE=512
diff --git a/configs/mt7986a_bpir3_sd_defconfig b/configs/mt7986a_bpir3_sd_defconfig
index 08edfe7..36547db 100644
--- a/configs/mt7986a_bpir3_sd_defconfig
+++ b/configs/mt7986a_bpir3_sd_defconfig
@@ -7,15 +7,15 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x80000
 CONFIG_ENV_OFFSET=0x300000
-CONFIG_DEFAULT_DEVICE_TREE="mt7986a-sd-rfb"
-CONFIG_SYS_PROMPT="MT7986> "
+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-sd"
+CONFIG_SYS_PROMPT="BPI-R3> "
 CONFIG_TARGET_MT7986=y
 CONFIG_DEBUG_UART_BASE=0x11002000
 CONFIG_DEBUG_UART_CLOCK=40000000
 CONFIG_SYS_LOAD_ADDR=0x46000000
 CONFIG_DEBUG_UART=y
 # CONFIG_AUTOBOOT is not set
-CONFIG_DEFAULT_FDT_FILE="mt7986a-sd-rfb"
+CONFIG_DEFAULT_FDT_FILE="mt7986a-bpi-r3-sd"
 CONFIG_LOGLEVEL=7
 CONFIG_LOG=y
 CONFIG_SYS_CBSIZE=512
diff --git a/configs/mt8183_pumpkin_defconfig b/configs/mt8183_pumpkin_defconfig
index 49d12bf..fdfe2a1 100644
--- a/configs/mt8183_pumpkin_defconfig
+++ b/configs/mt8183_pumpkin_defconfig
@@ -9,6 +9,7 @@
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="mt8183-pumpkin"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_TARGET_MT8183=y
 CONFIG_DEBUG_UART_BASE=0x11002000
 CONFIG_DEBUG_UART_CLOCK=26000000
@@ -83,5 +84,4 @@
 CONFIG_WDT=y
 CONFIG_WDT_MTK=y
 # CONFIG_REGEX is not set
-CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig
index 4f13040..0a4c218 100644
--- a/configs/mvebu_ac5_rd_defconfig
+++ b/configs/mvebu_ac5_rd_defconfig
@@ -21,7 +21,6 @@
 CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
 CONFIG_CMD_MEMTEST=y
@@ -35,7 +34,6 @@
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_UBI=y
diff --git a/configs/mvebu_crb_cn9130_defconfig b/configs/mvebu_crb_cn9130_defconfig
index 3ff5329..d7a3d6f 100644
--- a/configs/mvebu_crb_cn9130_defconfig
+++ b/configs/mvebu_crb_cn9130_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DEBUG_UART_BASE=0xf0512000
 CONFIG_DEBUG_UART_CLOCK=200000000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -22,7 +23,6 @@
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=1051
@@ -37,7 +37,6 @@
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
 CONFIG_MVEBU_MMC_BOOT=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MAC_PARTITION=y
@@ -71,7 +70,6 @@
 CONFIG_E1000=y
 CONFIG_MVPP2=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_DW_MVEBU=y
 CONFIG_PHY=y
 CONFIG_MVEBU_COMPHY_SUPPORT=y
diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig
index ed0d28f..8295670 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="armada-3720-db"
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_SYS_LOAD_ADDR=0x6000000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -22,7 +23,6 @@
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_MAXARGS=32
 # CONFIG_CMD_FLASH is not set
@@ -37,7 +37,6 @@
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
@@ -65,7 +64,6 @@
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_PCI_AARDVARK=y
 CONFIG_PHY=y
 CONFIG_MVEBU_COMPHY_SUPPORT=y
diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig
index 92c3827..e611990 100644
--- a/configs/mvebu_db_armada8k_defconfig
+++ b/configs/mvebu_db_armada8k_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DEBUG_UART_BASE=0xf0512000
 CONFIG_DEBUG_UART_CLOCK=200000000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -22,7 +23,6 @@
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_BOOTM_LEN=0x800000
@@ -35,7 +35,6 @@
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
@@ -59,7 +58,6 @@
 CONFIG_E1000=y
 CONFIG_MVPP2=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_DW_MVEBU=y
 CONFIG_PHY=y
 CONFIG_MVEBU_COMPHY_SUPPORT=y
diff --git a/configs/mvebu_db_cn9130_defconfig b/configs/mvebu_db_cn9130_defconfig
index 1d4c8bf..aa8ac20 100644
--- a/configs/mvebu_db_cn9130_defconfig
+++ b/configs/mvebu_db_cn9130_defconfig
@@ -15,6 +15,7 @@
 CONFIG_DEBUG_UART_BASE=0xf0512000
 CONFIG_DEBUG_UART_CLOCK=200000000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -24,7 +25,6 @@
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=1051
@@ -39,7 +39,6 @@
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
@@ -76,7 +75,6 @@
 CONFIG_E1000=y
 CONFIG_MVPP2=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_DW_MVEBU=y
 CONFIG_PHY=y
 CONFIG_MVEBU_COMPHY_SUPPORT=y
diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig
index ce69678..fc394a7 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -6,6 +6,7 @@
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
 CONFIG_TARGET_MVEBU_ARMADA_37XX=y
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x3F0000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -13,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="armada-3720-espressobin"
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_SYS_LOAD_ADDR=0x6000000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -23,7 +25,6 @@
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_LAST_STAGE_INIT=y
@@ -43,7 +44,6 @@
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
 CONFIG_CMD_BTRFS=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_SQUASHFS=y
@@ -69,7 +69,6 @@
 CONFIG_MMC_SDHCI_XENON=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
@@ -84,7 +83,6 @@
 CONFIG_MVNETA=y
 CONFIG_MVMDIO=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCI_AARDVARK=y
 CONFIG_PHY=y
 CONFIG_MVEBU_COMPHY_SUPPORT=y
diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig
index 058c043..3839d7d 100644
--- a/configs/mvebu_mcbin-88f8040_defconfig
+++ b/configs/mvebu_mcbin-88f8040_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEBUG_UART_BASE=0xf0512000
 CONFIG_DEBUG_UART_CLOCK=200000000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -23,7 +24,6 @@
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_BOOTM_LEN=0x800000
@@ -37,7 +37,6 @@
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MAC_PARTITION=y
@@ -64,7 +63,6 @@
 CONFIG_E1000=y
 CONFIG_MVPP2=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_DW_MVEBU=y
 CONFIG_PHY=y
 CONFIG_MVEBU_COMPHY_SUPPORT=y
diff --git a/configs/mvebu_puzzle-m801-88f8040_defconfig b/configs/mvebu_puzzle-m801-88f8040_defconfig
index 28cbef7..4576335 100644
--- a/configs/mvebu_puzzle-m801-88f8040_defconfig
+++ b/configs/mvebu_puzzle-m801-88f8040_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEBUG_UART_BASE=0xf0512000
 CONFIG_DEBUG_UART_CLOCK=200000000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -27,7 +28,6 @@
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_BOOTM_LEN=0x800000
@@ -41,7 +41,6 @@
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MAC_PARTITION=y
@@ -68,7 +67,6 @@
 CONFIG_E1000=y
 CONFIG_MVPP2=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_DW_MVEBU=y
 CONFIG_PHY=y
 CONFIG_MVEBU_COMPHY_SUPPORT=y
diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index f497ccf..0e68b79 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig
@@ -7,9 +7,6 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_TARGET_MX53LOCO=y
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx53-qsb"
 # CONFIG_CMD_BMODE is not set
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index 6869b90..82082c9 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -4,6 +4,7 @@
 CONFIG_SYS_MALLOC_LEN=0xa00000
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6q.cfg"
@@ -61,7 +62,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index f53045c..1a5fce4 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_MX6QDL=y
@@ -79,7 +80,6 @@
 CONFIG_NAND_MXS=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ATHEROS=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 2770b12..110b2b7 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_MX6QDL=y
@@ -18,6 +19,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_PCI=y
 CONFIG_SYS_MONITOR_LEN=409600
 CONFIG_FIT=y
 CONFIG_SPL_FIT_PRINT=y
@@ -84,14 +86,12 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_FEC_MXC=y
 CONFIG_RGMII=y
 CONFIG_MII=y
-CONFIG_PCI=y
 CONFIG_PCI_SCAN_SHOW=y
 CONFIG_PCIE_IMX=y
 CONFIG_PINCTRL=y
@@ -99,8 +99,8 @@
 CONFIG_DM_PMIC=y
 CONFIG_DM_PMIC_PFUZE100=y
 CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig
index 3dba1b3..1748f9f 100644
--- a/configs/mx6slevk_defconfig
+++ b/configs/mx6slevk_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TEXT_BASE=0x87800000
 CONFIG_SYS_MALLOC_LEN=0x300000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x80000
 CONFIG_MX6SL=y
@@ -45,7 +46,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_SMSC=y
diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig
index c970271..4d477f9 100644
--- a/configs/mx6slevk_spinor_defconfig
+++ b/configs/mx6slevk_spinor_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TEXT_BASE=0x87800000
 CONFIG_SYS_MALLOC_LEN=0x300000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -45,7 +46,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_SMSC=y
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index 0d6bc24..096edb3 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x80000
 CONFIG_MX6SL=y
@@ -61,7 +62,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_SMSC=y
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index 3e8ba78..d41cbfe 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TEXT_BASE=0x87800000
 CONFIG_SYS_MALLOC_LEN=0x300000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x80000
 CONFIG_MX6SX=y
@@ -50,7 +51,6 @@
 CONFIG_NAND_MXS=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ATHEROS=y
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index 2e52e30..d5c6821 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TEXT_BASE=0x87800000
 CONFIG_SYS_MALLOC_LEN=0x300000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xE0000
 CONFIG_MX6SX=y
@@ -11,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
 # CONFIG_CMD_BMODE is not set
 CONFIG_NXP_BOARD_REVISION=y
+CONFIG_PCI=y
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run findfdt; mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
@@ -51,14 +53,12 @@
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
-CONFIG_PCI=y
 CONFIG_PCI_SCAN_SHOW=y
 CONFIG_PCIE_IMX=y
 CONFIG_PINCTRL=y
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index 0436622..765480c 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_MX6UL=y
@@ -73,7 +74,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index 99475ea..5eecbf4 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x80000
 CONFIG_MX6UL=y
@@ -66,7 +67,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig
index c9a44d6..8b8a804 100644
--- a/configs/mx6ull_14x14_evk_defconfig
+++ b/configs/mx6ull_14x14_evk_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TEXT_BASE=0x87800000
 CONFIG_SYS_MALLOC_LEN=0x1000000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_MX6ULL=y
@@ -49,7 +50,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig
index 6010287..4bed72d 100644
--- a/configs/mx6ull_14x14_evk_plugin_defconfig
+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TEXT_BASE=0x87800000
 CONFIG_SYS_MALLOC_LEN=0x1000000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_MX6ULL=y
@@ -50,7 +51,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig
index 2df2ccd..4abb575 100644
--- a/configs/mx6ulz_14x14_evk_defconfig
+++ b/configs/mx6ulz_14x14_evk_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TEXT_BASE=0x87800000
 CONFIG_SYS_MALLOC_LEN=0x1000000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_MX6ULL=y
@@ -43,7 +44,6 @@
 CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig
index 2db2d1d..333d933 100644
--- a/configs/mx7dsabresd_qspi_defconfig
+++ b/configs/mx7dsabresd_qspi_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_MX7=y
 CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_DM_GPIO=y
@@ -54,7 +55,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_PHYLIB=y
diff --git a/configs/mx7ulp_com_defconfig b/configs/mx7ulp_com_defconfig
index 2788db0b..00fd6aa 100644
--- a/configs/mx7ulp_com_defconfig
+++ b/configs/mx7ulp_com_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TEXT_BASE=0x67800000
 CONFIG_SYS_MALLOC_LEN=0x800000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_DM_GPIO=y
@@ -40,7 +41,6 @@
 CONFIG_SYS_I2C_IMX_LPI2C=y
 CONFIG_FSL_USDHC=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX7ULP=y
diff --git a/configs/n2350_defconfig b/configs/n2350_defconfig
index 247533e..7f0c3f2 100644
--- a/configs/n2350_defconfig
+++ b/configs/n2350_defconfig
@@ -12,6 +12,7 @@
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
 CONFIG_TARGET_N2350=y
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x1000
@@ -26,6 +27,7 @@
 CONFIG_IDENT_STRING="\nThecus N2350"
 CONFIG_SYS_LOAD_ADDR=0x800000
 CONFIG_ENV_ADDR=0x100000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
@@ -72,7 +74,6 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_PXA3XX=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_MARVELL=y
@@ -80,7 +81,6 @@
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_MVMDIO=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_ARMADA_38X=y
diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig
index c12ca20..75589bb 100644
--- a/configs/nanopc-t4-rk3399_defconfig
+++ b/configs/nanopc-t4-rk3399_defconfig
@@ -15,6 +15,7 @@
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -48,7 +49,6 @@
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig
index 99ba53a..ef101cf 100644
--- a/configs/nanopi-k2_defconfig
+++ b/configs/nanopi-k2_defconfig
@@ -7,6 +7,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-nanopi-k2"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
@@ -41,4 +42,3 @@
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig
index 38954a8..21d7a07 100644
--- a/configs/nanopi-r2s-rk3328_defconfig
+++ b/configs/nanopi-r2s-rk3328_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s"
 CONFIG_DM_RESET=y
@@ -72,7 +73,6 @@
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PINCTRL=y
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index 87ca848..9d2bad4 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -4,6 +4,7 @@
 CONFIG_SYS_MALLOC_LEN=0xa00000
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_ENV_SECT_SIZE=0x2000
@@ -66,7 +67,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index 1bdd2f0..3911aba 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -4,6 +4,7 @@
 CONFIG_SYS_MALLOC_LEN=0xa00000
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_ENV_SECT_SIZE=0x2000
@@ -66,7 +67,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index dc010b0..9a88b34 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -4,6 +4,7 @@
 CONFIG_SYS_MALLOC_LEN=0xa00000
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_ENV_SECT_SIZE=0x2000
@@ -69,7 +70,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index fe3291d..d6c3cf0 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -4,6 +4,7 @@
 CONFIG_SYS_MALLOC_LEN=0xa00000
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_ENV_SECT_SIZE=0x2000
@@ -69,7 +70,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index b316524..821d428 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -4,6 +4,7 @@
 CONFIG_SYS_MALLOC_LEN=0xa00000
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_ENV_SECT_SIZE=0x2000
@@ -66,7 +67,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index eb11959..2e4db46 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -4,6 +4,7 @@
 CONFIG_SYS_MALLOC_LEN=0xa00000
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_ENV_SECT_SIZE=0x2000
@@ -66,7 +67,6 @@
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 2017d5c..a9c10cd 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEXT_BASE=0x81000100
 CONFIG_SYS_MALLOC_LEN=0x2500000
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big"
@@ -71,7 +72,6 @@
 CONFIG_CROS_EC_KEYB=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_SPI=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_AS3722=y
diff --git a/configs/o4-imx6ull-nano_defconfig b/configs/o4-imx6ull-nano_defconfig
index 94cdf24..a94828b 100644
--- a/configs/o4-imx6ull-nano_defconfig
+++ b/configs/o4-imx6ull-nano_defconfig
@@ -6,6 +6,7 @@
 CONFIG_TARGET_O4_IMX6ULL_NANO=y
 CONFIG_DM_GPIO=y
 CONFIG_MT41K256M16HA_125E=y
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_IMX_MODULE_FUSE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
@@ -62,4 +63,3 @@
 CONFIG_USB_GADGET_VENDOR_NUM=0x3016
 CONFIG_USB_GADGET_PRODUCT_NUM=0x0001
 CONFIG_CI_UDC=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig
index a642a64..24f4038 100644
--- a/configs/octeon_ebb7304_defconfig
+++ b/configs/octeon_ebb7304_defconfig
@@ -13,6 +13,7 @@
 # CONFIG_MIPS_CACHE_SETUP is not set
 # CONFIG_MIPS_CACHE_DISABLE is not set
 CONFIG_MIPS_RELOCATION_TABLE_SIZE=0xc000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
@@ -68,7 +69,6 @@
 CONFIG_DM_ETH_PHY=y
 CONFIG_E1000=y
 CONFIG_NET_OCTEON=y
-CONFIG_PCI=y
 CONFIG_PCIE_OCTEON=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/octeon_nic23_defconfig b/configs/octeon_nic23_defconfig
index f6b8629..455c3b2 100644
--- a/configs/octeon_nic23_defconfig
+++ b/configs/octeon_nic23_defconfig
@@ -15,6 +15,7 @@
 # CONFIG_MIPS_CACHE_SETUP is not set
 # CONFIG_MIPS_CACHE_DISABLE is not set
 CONFIG_MIPS_RELOCATION_TABLE_SIZE=0xc000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 CONFIG_OF_BOARD_FIXUP=y
@@ -66,7 +67,6 @@
 CONFIG_DM_MDIO=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_NET_OCTEON=y
-CONFIG_PCI=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_RAM=y
diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig
index 7b744e3..dace990 100644
--- a/configs/octeontx2_95xx_defconfig
+++ b/configs/octeontx2_95xx_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40ffff0
+CONFIG_SF_DEFAULT_SPEED=125000000
 CONFIG_ENV_SIZE=0x8000
 CONFIG_ENV_OFFSET=0xF00000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -17,6 +18,7 @@
 CONFIG_DEBUG_UART_BASE=0x87e028000000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SYS_LOAD_ADDR=0x4000000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_MEMTEST_START=0x04000000
 CONFIG_SYS_MEMTEST_END=0x040f0000
@@ -90,14 +92,12 @@
 CONFIG_MMC_OCTEONTX=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=125000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NET_OCTEONTX2=y
 CONFIG_OCTEONTX_SMI=y
-CONFIG_PCI=y
 CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_PCI_SRIOV=y
 CONFIG_PCI_ARID=y
diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig
index 7aeca7a..f8dcbf1 100644
--- a/configs/octeontx2_96xx_defconfig
+++ b/configs/octeontx2_96xx_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40ffff0
+CONFIG_SF_DEFAULT_SPEED=125000000
 CONFIG_ENV_SIZE=0x8000
 CONFIG_ENV_OFFSET=0xF00000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -17,6 +18,7 @@
 CONFIG_DEBUG_UART_BASE=0x87e028000000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SYS_LOAD_ADDR=0x4000000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -96,7 +98,6 @@
 CONFIG_MMC_OCTEONTX=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=125000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -111,7 +112,6 @@
 CONFIG_NET_OCTEONTX2=y
 CONFIG_OCTEONTX_SMI=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_PCI_SRIOV=y
 CONFIG_PCI_ARID=y
diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig
index d88b1b2..2d51abe 100644
--- a/configs/octeontx_81xx_defconfig
+++ b/configs/octeontx_81xx_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x28ffff0
+CONFIG_SF_DEFAULT_SPEED=16000000
 CONFIG_ENV_SIZE=0x8000
 CONFIG_ENV_OFFSET=0xF00000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -17,6 +18,7 @@
 CONFIG_DEBUG_UART_BASE=0x87e028000000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SYS_LOAD_ADDR=0x2800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x2800000
@@ -93,7 +95,6 @@
 CONFIG_MMC_OCTEONTX=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=16000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -112,7 +113,6 @@
 CONFIG_NET_OCTEONTX=y
 CONFIG_OCTEONTX_SMI=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_PCI_SRIOV=y
 CONFIG_PCI_ARID=y
diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig
index bcd82e4..656ff53 100644
--- a/configs/octeontx_83xx_defconfig
+++ b/configs/octeontx_83xx_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x28ffff0
+CONFIG_SF_DEFAULT_SPEED=16000000
 CONFIG_ENV_SIZE=0x8000
 CONFIG_ENV_OFFSET=0xF00000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -17,6 +18,7 @@
 CONFIG_DEBUG_UART_BASE=0x87e028000000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SYS_LOAD_ADDR=0x2800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 CONFIG_FIT=y
@@ -90,7 +92,6 @@
 CONFIG_MMC_OCTEONTX=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=16000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -109,7 +110,6 @@
 CONFIG_NET_OCTEONTX=y
 CONFIG_OCTEONTX_SMI=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_PCI_SRIOV=y
 CONFIG_PCI_ARID=y
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
index 8c06165..9481cbc 100644
--- a/configs/odroid-c2_defconfig
+++ b/configs/odroid-c2_defconfig
@@ -7,6 +7,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
@@ -66,4 +67,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/odroid-c4_defconfig b/configs/odroid-c4_defconfig
index 38b774e..315dc5c 100644
--- a/configs/odroid-c4_defconfig
+++ b/configs/odroid-c4_defconfig
@@ -8,6 +8,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-odroid-c4"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
@@ -75,4 +76,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/odroid-go-ultra_defconfig b/configs/odroid-go-ultra_defconfig
index 102469e..fb8ce5c 100644
--- a/configs/odroid-go-ultra_defconfig
+++ b/configs/odroid-go-ultra_defconfig
@@ -8,6 +8,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-odroid-go-ultra"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
@@ -67,4 +68,3 @@
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/odroid-hc4_defconfig b/configs/odroid-hc4_defconfig
index 2cf5241..b250715 100644
--- a/configs/odroid-hc4_defconfig
+++ b/configs/odroid-hc4_defconfig
@@ -8,12 +8,14 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-odroid-hc4"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" odroid-hc4"
 CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 CONFIG_REMAKE_ELF=y
@@ -49,7 +51,6 @@
 CONFIG_DM_MDIO_MUX=y
 CONFIG_ETH_DESIGNWARE_MESON8B=y
 CONFIG_MDIO_MUX_MESON_G12A=y
-CONFIG_PCI=y
 CONFIG_PCIE_DW_MESON=y
 CONFIG_MESON_G12A_USB_PHY=y
 CONFIG_PINCTRL=y
@@ -93,4 +94,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/odroid-n2_defconfig b/configs/odroid-n2_defconfig
index abf642c..e55de38 100644
--- a/configs/odroid-n2_defconfig
+++ b/configs/odroid-n2_defconfig
@@ -8,6 +8,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-odroid-n2"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
@@ -72,4 +73,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/odroid-n2l_defconfig b/configs/odroid-n2l_defconfig
index d5d30b8..983ac88 100644
--- a/configs/odroid-n2l_defconfig
+++ b/configs/odroid-n2l_defconfig
@@ -8,6 +8,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-odroid-n2l"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
@@ -67,4 +68,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
deleted file mode 100644
index c1ac60e..0000000
--- a/configs/omap5_uevm_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4031ff00
-CONFIG_DEFAULT_DEVICE_TREE="omap5-uevm"
-CONFIG_SPL_TEXT_BASE=0x40300000
-CONFIG_OMAP54XX=y
-CONFIG_TARGET_OMAP5_UEVM=y
-CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=16296
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x280000
-CONFIG_ARMV7_LPAE=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; "
-CONFIG_DEFAULT_FDT_FILE="omap5-uevm.dtb"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_MAX_SIZE=0x1dc00
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_FALCON_BOOT_MMCSD=y
-CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
-CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
-CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_SPL=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SCSI_AHCI=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_TCA642X=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_HSMMC2_8BIT=y
-CONFIG_PALMAS_POWER=y
-CONFIG_SCSI=y
-CONFIG_SCSI_AHCI_PLAT=y
-CONFIG_CONS_INDEX=3
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0403
-CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
-CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/openpiton_riscv64_defconfig b/configs/openpiton_riscv64_defconfig
index 4f7f377..6256072 100644
--- a/configs/openpiton_riscv64_defconfig
+++ b/configs/openpiton_riscv64_defconfig
@@ -6,6 +6,7 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64"
 CONFIG_SYS_PROMPT="openpiton$ "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_LOAD_ADDR=0x87000000
 CONFIG_TARGET_OPENPITON_RISCV64=y
 CONFIG_ARCH_RV64I=y
@@ -78,5 +79,4 @@
 CONFIG_SHA256=y
 CONFIG_MD5=y
 CONFIG_GETOPT=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/openpiton_riscv64_spl_defconfig b/configs/openpiton_riscv64_spl_defconfig
index 71a98e9..b7696d7 100644
--- a/configs/openpiton_riscv64_spl_defconfig
+++ b/configs/openpiton_riscv64_spl_defconfig
@@ -6,6 +6,7 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64"
 CONFIG_SYS_PROMPT="openpiton$ "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_STACK=0x83fffe80
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
 CONFIG_SPL=y
@@ -95,5 +96,4 @@
 CONFIG_SHA256=y
 CONFIG_MD5=y
 CONFIG_GETOPT=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig
index 867b89d..d926df6 100644
--- a/configs/opos6uldev_defconfig
+++ b/configs/opos6uldev_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="imx6ul-opos6uldev"
 CONFIG_SPL_TEXT_BASE=0x00908000
 CONFIG_SYS_PROMPT="BIOS> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
@@ -122,5 +123,4 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/p200_defconfig b/configs/p200_defconfig
index 51add0c..42e7eb8 100644
--- a/configs/p200_defconfig
+++ b/configs/p200_defconfig
@@ -7,6 +7,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-p200"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
@@ -40,4 +41,3 @@
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/p201_defconfig b/configs/p201_defconfig
index 48e53c0..5c98375 100644
--- a/configs/p201_defconfig
+++ b/configs/p201_defconfig
@@ -8,6 +8,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-p201"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
@@ -41,4 +42,3 @@
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/p212_defconfig b/configs/p212_defconfig
index 2b76437..2fcf3b3 100644
--- a/configs/p212_defconfig
+++ b/configs/p212_defconfig
@@ -7,6 +7,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-p212"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_GXL=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
@@ -49,4 +50,3 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_MESON_GXL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
index 2962a7d..7e75f44 100644
--- a/configs/p2371-0000_defconfig
+++ b/configs/p2371-0000_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEXT_BASE=0x80080000
 CONFIG_SYS_MALLOC_LEN=0x2500000
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-0000"
@@ -38,7 +39,6 @@
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
 CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_TEGRA114_SPI=y
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
index 6b44361..2543a2d 100644
--- a/configs/p2371-2180_defconfig
+++ b/configs/p2371-2180_defconfig
@@ -6,6 +6,7 @@
 CONFIG_TEXT_BASE=0x80080000
 CONFIG_SYS_MALLOC_LEN=0x2500000
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-2180"
@@ -14,6 +15,7 @@
 CONFIG_TARGET_P2371_2180=y
 CONFIG_TEGRA_GPU=y
 CONFIG_SYS_LOAD_ADDR=0x80080000
+CONFIG_PCI=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_CONSOLE_MUX=y
@@ -44,10 +46,8 @@
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
 CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_RTL8169=y
-CONFIG_PCI=y
 CONFIG_PCI_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_TEGRA114_SPI=y
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
index 00b0dc6..47a0a62 100644
--- a/configs/p2571_defconfig
+++ b/configs/p2571_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEXT_BASE=0x80080000
 CONFIG_SYS_MALLOC_LEN=0x2500000
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2571"
@@ -39,7 +40,6 @@
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
 CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_TEGRA114_SPI=y
diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig
index 682be7d..e3b978e 100644
--- a/configs/p2771-0000-000_defconfig
+++ b/configs/p2771-0000-000_defconfig
@@ -11,6 +11,7 @@
 CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-000) # "
 CONFIG_TEGRA186=y
 CONFIG_SYS_LOAD_ADDR=0x80080000
+CONFIG_PCI=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_CONSOLE_MUX=y
@@ -36,7 +37,6 @@
 CONFIG_DWC_ETH_QOS=y
 CONFIG_E1000=y
 CONFIG_RTL8169=y
-CONFIG_PCI=y
 CONFIG_PCI_TEGRA=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_TEGRA186_POWER_DOMAIN=y
diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig
index c5925b1..c99a24e 100644
--- a/configs/p2771-0000-500_defconfig
+++ b/configs/p2771-0000-500_defconfig
@@ -11,6 +11,7 @@
 CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-500) # "
 CONFIG_TEGRA186=y
 CONFIG_SYS_LOAD_ADDR=0x80080000
+CONFIG_PCI=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_CONSOLE_MUX=y
@@ -36,7 +37,6 @@
 CONFIG_DWC_ETH_QOS=y
 CONFIG_E1000=y
 CONFIG_RTL8169=y
-CONFIG_PCI=y
 CONFIG_PCI_TEGRA=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_TEGRA186_POWER_DOMAIN=y
diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig
index d35bea4..e280be8 100644
--- a/configs/p3450-0000_defconfig
+++ b/configs/p3450-0000_defconfig
@@ -6,6 +6,7 @@
 CONFIG_TEXT_BASE=0x80080000
 CONFIG_SYS_MALLOC_LEN=0x2500000
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_ENV_SECT_SIZE=0x1000
@@ -15,6 +16,7 @@
 CONFIG_TARGET_P3450_0000=y
 CONFIG_TEGRA_GPU=y
 CONFIG_SYS_LOAD_ADDR=0x80080000
+CONFIG_PCI=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_CONSOLE_MUX=y
@@ -46,11 +48,9 @@
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
 CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_RTL8169=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCI_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_TEGRA114_SPI=y
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index 733172c..6769634 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -5,6 +5,7 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_DEFAULT_DEVICE_TREE="am335x-wega-rdk"
 CONFIG_AM33XX=y
 CONFIG_TARGET_PCM051=y
@@ -51,7 +52,6 @@
 CONFIG_MMC_OMAP_HS=y
 CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHY_SMSC=y
 CONFIG_MII=y
diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig
index 7c3814f..85858e6 100644
--- a/configs/pcm058_defconfig
+++ b/configs/pcm058_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -74,7 +75,6 @@
 CONFIG_NAND_MXS_DT=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index 131c7fa..2b57f23 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -11,6 +11,7 @@
 CONFIG_NR_DRAM_BANKS=7
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2073800
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x3FC000
 CONFIG_ENV_SECT_SIZE=0x4000
@@ -58,7 +59,6 @@
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_S5P=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SMC911X=y
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index b4ca60f..d4118fe 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -10,6 +10,7 @@
 CONFIG_TARGET_PEACH_PIT=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2073800
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x3FC000
 CONFIG_ENV_SECT_SIZE=0x4000
@@ -57,7 +58,6 @@
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_S5P=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SMC911X=y
diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig
index 11d634c..f89aa3e 100644
--- a/configs/pg_wcom_expu1_defconfig
+++ b/configs/pg_wcom_expu1_defconfig
@@ -5,6 +5,7 @@
 CONFIG_TEXT_BASE=0x60100000
 CONFIG_SYS_MALLOC_LEN=0x1004000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="pg-wcom-expu1"
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_SYS_I2C_MXC_I2C1=y
@@ -63,7 +64,6 @@
 CONFIG_CMD_UBI=y
 # CONFIG_CMD_UBIFS is not set
 CONFIG_OF_CONTROL=y
-CONFIG_ENV_SOURCE_FILE="pg-wcom-expu1"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig
index b6dd8e3..c5b150b 100644
--- a/configs/pg_wcom_expu1_update_defconfig
+++ b/configs/pg_wcom_expu1_update_defconfig
@@ -5,6 +5,7 @@
 CONFIG_TEXT_BASE=0x60240000
 CONFIG_SYS_MALLOC_LEN=0x1004000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="pg-wcom-expu1"
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_SYS_I2C_MXC_I2C1=y
@@ -61,7 +62,6 @@
 CONFIG_CMD_UBI=y
 # CONFIG_CMD_UBIFS is not set
 CONFIG_OF_CONTROL=y
-CONFIG_ENV_SOURCE_FILE="pg-wcom-expu1"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig
index 0cf6bbb..5bc0c00 100644
--- a/configs/pg_wcom_seli8_defconfig
+++ b/configs/pg_wcom_seli8_defconfig
@@ -5,6 +5,7 @@
 CONFIG_TEXT_BASE=0x60100000
 CONFIG_SYS_MALLOC_LEN=0x1004000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="pg-wcom-seli8"
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_SYS_I2C_MXC_I2C1=y
@@ -63,7 +64,6 @@
 CONFIG_CMD_UBI=y
 # CONFIG_CMD_UBIFS is not set
 CONFIG_OF_CONTROL=y
-CONFIG_ENV_SOURCE_FILE="pg-wcom-seli8"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig
index ab47721..78404d4 100644
--- a/configs/pg_wcom_seli8_update_defconfig
+++ b/configs/pg_wcom_seli8_update_defconfig
@@ -5,6 +5,7 @@
 CONFIG_TEXT_BASE=0x60240000
 CONFIG_SYS_MALLOC_LEN=0x1004000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="pg-wcom-seli8"
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_SYS_I2C_MXC_I2C1=y
@@ -61,7 +62,6 @@
 CONFIG_CMD_UBI=y
 # CONFIG_CMD_UBIFS is not set
 CONFIG_OF_CONTROL=y
-CONFIG_ENV_SOURCE_FILE="pg-wcom-seli8"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig
index c73a7d9..3b2eb0a 100644
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -5,6 +5,7 @@
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SF_DEFAULT_SPEED=80000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x3C0000
 CONFIG_DM_GPIO=y
@@ -97,7 +98,6 @@
 CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=3
-CONFIG_SF_DEFAULT_SPEED=80000000
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index cfe1a39..4e72762 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-phycore-rdk"
 CONFIG_SPL_TEXT_BASE=0xff704000
@@ -65,7 +66,6 @@
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PINCTRL=y
diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index dcee179..4e60159 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -76,6 +76,7 @@
 CONFIG_DM_REGULATOR_PFUZE100=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_USB=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig
index a994337..112c111 100644
--- a/configs/pico-imx7d_bl33_defconfig
+++ b/configs/pico-imx7d_bl33_defconfig
@@ -9,6 +9,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
 CONFIG_TARGET_PICO_IMX7D=y
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL=y
@@ -92,4 +93,3 @@
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig
index dff4695..7a4fcc9 100644
--- a/configs/pinebook-pro-rk3399_defconfig
+++ b/configs/pinebook-pro-rk3399_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x8000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro"
@@ -18,6 +19,7 @@
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_PREBOOT=y
@@ -63,11 +65,9 @@
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_DM_PMIC_FAN53555=y
diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig
index 54f9b90..4edea88 100644
--- a/configs/pinephone-pro-rk3399_defconfig
+++ b/configs/pinephone-pro-rk3399_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x8000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro"
@@ -63,7 +64,6 @@
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig
index cda7a32..3e3e811 100644
--- a/configs/pogo_v4_defconfig
+++ b/configs/pogo_v4_defconfig
@@ -16,6 +16,7 @@
 CONFIG_SYS_PROMPT="Pogo_V4> "
 CONFIG_IDENT_STRING="\nPogoplug V4"
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTSTAGE=y
 CONFIG_SHOW_BOOT_PROGRESS=y
@@ -66,7 +67,6 @@
 CONFIG_PHY_MARVELL=y
 CONFIG_MVGBE=y
 CONFIG_MII=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_EMULATION=y
diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig
index 023f880..6ec7c83 100644
--- a/configs/polaroid_mid2407pxe03_defconfig
+++ b/configs/polaroid_mid2407pxe03_defconfig
@@ -6,7 +6,6 @@
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_ZQ=63351
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH8"
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
@@ -15,6 +14,7 @@
 CONFIG_VIDEO_LCD_BL_EN="PH6"
 CONFIG_VIDEO_LCD_BL_PWM="PH0"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_CONS_INDEX=5
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig
index 2e9efd0..1aefc50 100644
--- a/configs/polaroid_mid2809pxe04_defconfig
+++ b/configs/polaroid_mid2809pxe04_defconfig
@@ -6,7 +6,6 @@
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_ZQ=63351
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH8"
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:36,ri:210,up:18,lo:22,hs:10,vs:5,sync:3,vmode:0"
@@ -15,6 +14,7 @@
 CONFIG_VIDEO_LCD_BL_EN="PH6"
 CONFIG_VIDEO_LCD_BL_PWM="PH0"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_CONS_INDEX=5
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index 7857f39..7bbac22 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-popmetal"
 CONFIG_SPL_TEXT_BASE=0xff704000
@@ -62,7 +63,6 @@
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PINCTRL=y
diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index 1d74621..d676e05 100644
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig
@@ -29,6 +29,7 @@
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x50000000
 CONFIG_ENV_ADDR=0xC0000
+CONFIG_PCI=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
@@ -87,7 +88,6 @@
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
 CONFIG_SH_ETHER=y
-CONFIG_PCI=y
 CONFIG_PCI_RCAR_GEN2=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index 59017b2..b632fa3 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-haikou"
@@ -74,7 +75,6 @@
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig
index 3bfc5c5..0f8c30e 100644
--- a/configs/q8_a23_tablet_800x480_defconfig
+++ b/configs/q8_a23_tablet_800x480_defconfig
@@ -6,7 +6,6 @@
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_ZQ=63306
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH8"
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:36,ri:210,up:18,lo:22,hs:10,vs:5,sync:3,vmode:0"
@@ -15,6 +14,7 @@
 CONFIG_VIDEO_LCD_BL_EN="PH6"
 CONFIG_VIDEO_LCD_BL_PWM="PH0"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_CONS_INDEX=5
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig
index 9166ec0..b3b5cc7 100644
--- a/configs/q8_a33_tablet_1024x600_defconfig
+++ b/configs/q8_a33_tablet_1024x600_defconfig
@@ -6,7 +6,6 @@
 CONFIG_DRAM_CLK=456
 CONFIG_DRAM_ZQ=15291
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH8"
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
@@ -15,6 +14,7 @@
 CONFIG_VIDEO_LCD_BL_EN="PH6"
 CONFIG_VIDEO_LCD_BL_PWM="PH0"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_CONS_INDEX=5
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig
index 6114fcb..37ee08f 100644
--- a/configs/q8_a33_tablet_800x480_defconfig
+++ b/configs/q8_a33_tablet_800x480_defconfig
@@ -6,7 +6,6 @@
 CONFIG_DRAM_CLK=456
 CONFIG_DRAM_ZQ=15291
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH8"
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
@@ -15,6 +14,7 @@
 CONFIG_VIDEO_LCD_BL_EN="PH6"
 CONFIG_VIDEO_LCD_BL_PWM="PH0"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_CONS_INDEX=5
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig
index 54a07ad..e8a7a09 100644
--- a/configs/qemu-riscv32_defconfig
+++ b/configs/qemu-riscv32_defconfig
@@ -8,7 +8,6 @@
 CONFIG_SYS_LOAD_ADDR=0x80200000
 CONFIG_TARGET_QEMU_VIRT=y
 CONFIG_SYS_MONITOR_LEN=786432
-CONFIG_STANDALONE_LOAD_ADDR=0x80200000
 CONFIG_FIT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_DISPLAY_CPUINFO=y
diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig
index 74918de..d73a51e 100644
--- a/configs/qemu-riscv32_smode_defconfig
+++ b/configs/qemu-riscv32_smode_defconfig
@@ -9,7 +9,6 @@
 CONFIG_TARGET_QEMU_VIRT=y
 CONFIG_RISCV_SMODE=y
 CONFIG_SYS_MONITOR_LEN=786432
-CONFIG_STANDALONE_LOAD_ADDR=0x80200000
 CONFIG_FIT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_DISPLAY_CPUINFO=y
diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig
index c93f96b..7b8d562 100644
--- a/configs/qemu-riscv32_spl_defconfig
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -11,7 +11,6 @@
 CONFIG_RISCV_SMODE=y
 # CONFIG_OF_BOARD_FIXUP is not set
 CONFIG_SYS_MONITOR_LEN=786432
-CONFIG_STANDALONE_LOAD_ADDR=0x80200000
 CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index d64f340..9a8bbef 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -8,7 +8,6 @@
 CONFIG_SYS_LOAD_ADDR=0x80200000
 CONFIG_TARGET_QEMU_VIRT=y
 CONFIG_ARCH_RV64I=y
-CONFIG_STANDALONE_LOAD_ADDR=0x80200000
 CONFIG_FIT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_DISPLAY_CPUINFO=y
diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
index 53c2f48..1d0f021 100644
--- a/configs/qemu-riscv64_smode_defconfig
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -9,7 +9,6 @@
 CONFIG_TARGET_QEMU_VIRT=y
 CONFIG_ARCH_RV64I=y
 CONFIG_RISCV_SMODE=y
-CONFIG_STANDALONE_LOAD_ADDR=0x80200000
 CONFIG_FIT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_USE_PREBOOT=y
diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
index 9c8eb15..bb10145 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -10,7 +10,6 @@
 CONFIG_TARGET_QEMU_VIRT=y
 CONFIG_ARCH_RV64I=y
 CONFIG_RISCV_SMODE=y
-CONFIG_STANDALONE_LOAD_ADDR=0x80200000
 CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig
index d2c3372..aa43889 100644
--- a/configs/qemu_arm64_defconfig
+++ b/configs/qemu_arm64_defconfig
@@ -13,6 +13,7 @@
 CONFIG_ARMV8_CRYPTO=y
 CONFIG_SYS_LOAD_ADDR=0x40200000
 CONFIG_ENV_ADDR=0x4000000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 CONFIG_FIT=y
@@ -59,7 +60,6 @@
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_ECAM_GENERIC=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig
index 698c1af..7c51468 100644
--- a/configs/qemu_arm_defconfig
+++ b/configs/qemu_arm_defconfig
@@ -14,6 +14,7 @@
 CONFIG_ARMV7_LPAE=y
 CONFIG_SYS_LOAD_ADDR=0x40200000
 CONFIG_ENV_ADDR=0x4000000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 CONFIG_FIT=y
@@ -60,7 +61,6 @@
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_ECAM_GENERIC=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig
index 0653089..21b0fd5 100644
--- a/configs/r2dplus_defconfig
+++ b/configs/r2dplus_defconfig
@@ -8,6 +8,7 @@
 CONFIG_SYS_CLK_FREQ=60000000
 CONFIG_SYS_LOAD_ADDR=0x8e000000
 CONFIG_ENV_ADDR=0xA0040000
+CONFIG_PCI=y
 CONFIG_TARGET_R2DPLUS=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0xA0000000
@@ -52,7 +53,6 @@
 CONFIG_PCNET=y
 CONFIG_RTL8139=y
 CONFIG_TULIP=y
-CONFIG_PCI=y
 CONFIG_SH7751_PCI=y
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig
index 37af576..711e2f0 100644
--- a/configs/r8a77970_eagle_defconfig
+++ b/configs/r8a77970_eagle_defconfig
@@ -81,4 +81,3 @@
 CONFIG_RENESAS_RPC_SPI=y
 CONFIG_TEE=y
 CONFIG_OPTEE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig
index 687a894..4c895cd 100644
--- a/configs/r8a77980_condor_defconfig
+++ b/configs/r8a77980_condor_defconfig
@@ -90,4 +90,3 @@
 CONFIG_SYSINFO=y
 CONFIG_TEE=y
 CONFIG_OPTEE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig
index 9960e7a..c13f25e 100644
--- a/configs/r8a77990_ebisu_defconfig
+++ b/configs/r8a77990_ebisu_defconfig
@@ -109,4 +109,3 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig
index a09b33e..c76ddef 100644
--- a/configs/r8a77995_draak_defconfig
+++ b/configs/r8a77995_draak_defconfig
@@ -106,4 +106,3 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig
index 14feaf1..a8a0bc8 100644
--- a/configs/r8a779a0_falcon_defconfig
+++ b/configs/r8a779a0_falcon_defconfig
@@ -9,10 +9,8 @@
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="r8a779a0-falcon-u-boot"
-CONFIG_SPL_TEXT_BASE=0xe6338000
 CONFIG_RCAR_GEN4=y
 CONFIG_TARGET_FALCON=y
-CONFIG_SPL_STACK=0xe6304000
 CONFIG_SYS_CLK_FREQ=16666666
 # CONFIG_PSCI_RESET is not set
 CONFIG_ARMV8_PSCI=y
@@ -28,10 +26,6 @@
 CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a779a0-falcon.dtb; booti 0x48080000 - 0x48000000"
 CONFIG_DEFAULT_FDT_FILE="r8a779a0-falcon.dtb"
 CONFIG_SYS_MALLOC_BOOTPARAMS=y
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0xe631f000
-CONFIG_SPL_BSS_MAX_SIZE=0x1000
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_PBSIZE=2068
@@ -79,4 +73,3 @@
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_RENESAS_RPC_SPI=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/radxa-zero2_defconfig b/configs/radxa-zero2_defconfig
index 2218b0d..b1aa3c2 100644
--- a/configs/radxa-zero2_defconfig
+++ b/configs/radxa-zero2_defconfig
@@ -2,17 +2,19 @@
 CONFIG_ARCH_MESON=y
 CONFIG_TEXT_BASE=0x01000000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-radxa-zero2"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" radxa-zero2"
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_DEBUG_UART=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
 CONFIG_REMAKE_ELF=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_DISPLAY_CPUINFO is not set
@@ -33,11 +35,6 @@
 CONFIG_MMC_MESON_GX=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
-# CONFIG_PHY_REALTEK is not set
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
-# CONFIG_ETH_DESIGNWARE_MESON8B is not set
-CONFIG_MDIO_MUX_MESON_G12A=y
 CONFIG_MESON_G12A_USB_PHY=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_MESON_G12A=y
@@ -45,7 +42,6 @@
 CONFIG_MESON_EE_POWER_DOMAIN=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_MESON_SERIAL=y
@@ -74,4 +70,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/radxa-zero_defconfig b/configs/radxa-zero_defconfig
index c9ff1a5..23f30f6 100644
--- a/configs/radxa-zero_defconfig
+++ b/configs/radxa-zero_defconfig
@@ -7,6 +7,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-radxa-zero"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
@@ -66,4 +67,3 @@
 CONFIG_VIDEO_DT_SIMPLEFB=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig
index 32b213f..6e11ba4 100644
--- a/configs/rcar3_salvator-x_defconfig
+++ b/configs/rcar3_salvator-x_defconfig
@@ -12,6 +12,7 @@
 CONFIG_TARGET_SALVATOR_X=y
 CONFIG_SPL_STACK=0xe6304000
 CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_PCI=y
 CONFIG_LTO=y
 CONFIG_REMAKE_ELF=y
 CONFIG_SYS_MONITOR_LEN=1048576
@@ -98,7 +99,6 @@
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_RENESAS_RAVB=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_PCI_RCAR_GEN3=y
 CONFIG_DM_REGULATOR=y
@@ -116,5 +116,4 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_UNICODE_CAPITALIZATION is not set
diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig
index ea523e8..30cbd77 100644
--- a/configs/rcar3_ulcb_defconfig
+++ b/configs/rcar3_ulcb_defconfig
@@ -111,4 +111,3 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index faa5bd7..79a1ca4 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x60000
 CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6s1g.cfg"
@@ -58,7 +59,6 @@
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_FSL_USDHC=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ATHEROS=y
diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig
index 4fc6dc7..6b3bc75 100644
--- a/configs/roc-cc-rk3328_defconfig
+++ b/configs/roc-cc-rk3328_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3328-roc-cc"
 CONFIG_DM_RESET=y
@@ -73,7 +74,6 @@
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig
index 8b04125..9321292 100644
--- a/configs/roc-pc-mezzanine-rk3399_defconfig
+++ b/configs/roc-pc-mezzanine-rk3399_defconfig
@@ -20,6 +20,7 @@
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb"
@@ -62,7 +63,6 @@
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PMIC_RK8XX=y
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index effffee..824b404 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x8000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_ENV_SECT_SIZE=0x1000
@@ -58,7 +59,6 @@
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig
index 4ecc06d..1e96fa7 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -8,6 +8,7 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4b"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_TARGET_EVB_RK3399=y
@@ -15,6 +16,7 @@
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4b.dtb"
@@ -58,7 +60,6 @@
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PMIC_RK8XX=y
@@ -92,6 +93,5 @@
 CONFIG_DISPLAY_ROCKCHIP_HDMI=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_CAPSULE_ON_DISK=y
 CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig
index 899a666..1c7648c 100644
--- a/configs/rock-pi-4c-rk3399_defconfig
+++ b/configs/rock-pi-4c-rk3399_defconfig
@@ -8,6 +8,7 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4c"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_TARGET_EVB_RK3399=y
@@ -15,6 +16,7 @@
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb"
@@ -58,7 +60,6 @@
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PMIC_RK8XX=y
@@ -92,6 +93,5 @@
 CONFIG_DISPLAY_ROCKCHIP_HDMI=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_CAPSULE_ON_DISK=y
 CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig
index 4b0f517..9c67d0c 100644
--- a/configs/rock-pi-e-rk3328_defconfig
+++ b/configs/rock-pi-e-rk3328_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e"
 CONFIG_DM_RESET=y
@@ -74,7 +75,6 @@
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PHY=y
diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig
index 1a0380d..8eb17d8 100644
--- a/configs/rock-pi-n10-rk3399pro_defconfig
+++ b/configs/rock-pi-n10-rk3399pro_defconfig
@@ -16,6 +16,7 @@
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb"
@@ -53,7 +54,6 @@
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PMIC_RK8XX=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index 25a9757..e5e4882 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock2-square"
 CONFIG_SPL_TEXT_BASE=0xff704000
@@ -63,7 +64,6 @@
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PINCTRL=y
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
index 39b39c9..74a9cc0 100644
--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64"
 CONFIG_DM_RESET=y
@@ -72,7 +73,6 @@
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
index 6fefa15..3d6aeaa 100644
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
@@ -15,6 +15,7 @@
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
@@ -54,7 +55,6 @@
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PMIC_RK8XX=y
diff --git a/configs/rock_defconfig b/configs/rock_defconfig
index b1f09df..e62e3f0 100644
--- a/configs/rock_defconfig
+++ b/configs/rock_defconfig
@@ -9,6 +9,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
 CONFIG_SPL_TEXT_BASE=0x10080800
@@ -54,7 +55,6 @@
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_PINCTRL=y
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
index 4961423..2b89b1b 100644
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
@@ -18,6 +18,7 @@
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
@@ -68,7 +69,6 @@
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PMIC_RK8XX=y
diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig
index 2a44237..5da334a 100644
--- a/configs/rpi_0_w_defconfig
+++ b/configs/rpi_0_w_defconfig
@@ -10,6 +10,7 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-zero-w"
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
@@ -48,5 +49,4 @@
 CONFIG_VIDEO_BCM2835=y
 CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_PHYS_TO_BUS=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER=y
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index 1c462f3..9908621 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -11,6 +11,7 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b"
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
@@ -49,4 +50,3 @@
 CONFIG_VIDEO_BCM2835=y
 CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_PHYS_TO_BUS=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
index ed14571..80885aa 100644
--- a/configs/rpi_3_32b_defconfig
+++ b/configs/rpi_3_32b_defconfig
@@ -10,6 +10,7 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
@@ -50,4 +51,3 @@
 CONFIG_VIDEO_BCM2835=y
 CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_PHYS_TO_BUS=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig
index d29bc7d..0acce8b 100644
--- a/configs/rpi_3_b_plus_defconfig
+++ b/configs/rpi_3_b_plus_defconfig
@@ -9,6 +9,7 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b-plus"
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
@@ -49,4 +50,3 @@
 CONFIG_VIDEO_BCM2835=y
 CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_PHYS_TO_BUS=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
index eb92519..bb6fe12 100644
--- a/configs/rpi_3_defconfig
+++ b/configs/rpi_3_defconfig
@@ -9,6 +9,7 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
@@ -49,4 +50,3 @@
 CONFIG_VIDEO_BCM2835=y
 CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_PHYS_TO_BUS=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
index 2fdc4b2..f621334 100644
--- a/configs/rpi_4_32b_defconfig
+++ b/configs/rpi_4_32b_defconfig
@@ -7,8 +7,10 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b"
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_PCI=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_USE_PREBOOT=y
@@ -37,7 +39,6 @@
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_BCM2835=y
 CONFIG_BCMGENET=y
-CONFIG_PCI=y
 CONFIG_PCI_BRCMSTB=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
@@ -66,4 +67,3 @@
 CONFIG_PHYS_TO_BUS=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=2
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
index efa4256..bbc0fd6 100644
--- a/configs/rpi_4_defconfig
+++ b/configs/rpi_4_defconfig
@@ -7,8 +7,10 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b"
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_PCI=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_USE_PREBOOT=y
@@ -37,7 +39,6 @@
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_BCM2835=y
 CONFIG_BCMGENET=y
-CONFIG_PCI=y
 CONFIG_PCI_BRCMSTB=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
@@ -64,4 +65,3 @@
 CONFIG_VIDEO_BCM2835=y
 CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_PHYS_TO_BUS=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
index 53bf410..5d9a273 100644
--- a/configs/rpi_arm64_defconfig
+++ b/configs/rpi_arm64_defconfig
@@ -7,8 +7,10 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b"
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_PCI=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_USE_PREBOOT=y
@@ -32,7 +34,6 @@
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_BCM2835=y
 CONFIG_BCMGENET=y
-CONFIG_PCI=y
 CONFIG_PCI_BRCMSTB=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
@@ -56,4 +57,3 @@
 CONFIG_VIDEO_BCM2835=y
 CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_PHYS_TO_BUS=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index dfd0c6b..550b8dc 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -10,6 +10,7 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-b"
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
@@ -48,5 +49,4 @@
 CONFIG_VIDEO_BCM2835=y
 CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_PHYS_TO_BUS=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER=y
diff --git a/configs/rzg2_beacon_defconfig b/configs/rzg2_beacon_defconfig
index b4ea6c6..ef1f862 100644
--- a/configs/rzg2_beacon_defconfig
+++ b/configs/rzg2_beacon_defconfig
@@ -86,4 +86,3 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/s400_defconfig b/configs/s400_defconfig
index c3c7dda..9a7d520 100644
--- a/configs/s400_defconfig
+++ b/configs/s400_defconfig
@@ -7,6 +7,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-axg-s400"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_AXG=y
 CONFIG_DEBUG_UART_BASE=0xff803000
@@ -53,4 +54,3 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sam9x60_curiosity_mmc1_defconfig b/configs/sam9x60_curiosity_mmc1_defconfig
index 4a1b2b9..21b2cc2e 100644
--- a/configs/sam9x60_curiosity_mmc1_defconfig
+++ b/configs/sam9x60_curiosity_mmc1_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sam9x60_curiosity"
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=200000000
 CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -89,4 +90,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sam9x60_curiosity_mmc_defconfig b/configs/sam9x60_curiosity_mmc_defconfig
index f9ab17a..10937d6 100644
--- a/configs/sam9x60_curiosity_mmc_defconfig
+++ b/configs/sam9x60_curiosity_mmc_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sam9x60_curiosity"
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=200000000
 CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -76,4 +77,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig
index b0307ec..2a13997 100644
--- a/configs/sam9x60ek_mmc_defconfig
+++ b/configs/sam9x60ek_mmc_defconfig
@@ -9,10 +9,12 @@
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000bf00
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek"
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=200000000
 CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -76,7 +78,6 @@
 CONFIG_DM_NAND_ATMEL=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -100,4 +101,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig
index 4c58178..c6c4686 100644
--- a/configs/sam9x60ek_nandflash_defconfig
+++ b/configs/sam9x60ek_nandflash_defconfig
@@ -9,9 +9,11 @@
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000bf00
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek"
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=200000000
 CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -77,7 +79,6 @@
 CONFIG_DM_NAND_ATMEL=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_MACRONIX=y
@@ -102,4 +103,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sam9x60ek_qspiflash_defconfig b/configs/sam9x60ek_qspiflash_defconfig
index 32aa49d..ef2e2db 100644
--- a/configs/sam9x60ek_qspiflash_defconfig
+++ b/configs/sam9x60ek_qspiflash_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek"
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=200000000
 CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -101,4 +102,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d27_giantboard_defconfig b/configs/sama5d27_giantboard_defconfig
index 39d1dcd..84bd2f5 100644
--- a/configs/sama5d27_giantboard_defconfig
+++ b/configs/sama5d27_giantboard_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_giantboard"
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -98,4 +99,3 @@
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig
index cdb000f..fd88ce8 100644
--- a/configs/sama5d27_som1_ek_mmc1_defconfig
+++ b/configs/sama5d27_som1_ek_mmc1_defconfig
@@ -9,10 +9,12 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0
+CONFIG_SF_DEFAULT_SPEED=66000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -83,7 +85,6 @@
 CONFIG_MMC_SDHCI_ATMEL=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=66000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -119,4 +120,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig
index 1471ceb..e6e5fef 100644
--- a/configs/sama5d27_som1_ek_mmc_defconfig
+++ b/configs/sama5d27_som1_ek_mmc_defconfig
@@ -10,10 +10,12 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0
+CONFIG_SF_DEFAULT_SPEED=66000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -83,7 +85,6 @@
 CONFIG_MMC_SDHCI_ATMEL=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=66000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -119,4 +120,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig
index 1c8adfb..cc0f08c4 100644
--- a/configs/sama5d27_som1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_som1_ek_qspiflash_defconfig
@@ -10,10 +10,12 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0
+CONFIG_SF_DEFAULT_SPEED=66000000
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -82,7 +84,6 @@
 CONFIG_MMC_SDHCI_ATMEL=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=66000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -118,4 +119,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig
index eeb8d20..fde3ab8 100644
--- a/configs/sama5d27_wlsom1_ek_mmc_defconfig
+++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig
@@ -8,10 +8,12 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek"
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -86,7 +88,6 @@
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=2
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_MACRONIX=y
@@ -124,5 +125,4 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER_HII is not set
diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
index e7445fe..8106018 100644
--- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
@@ -8,11 +8,13 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek"
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
@@ -90,7 +92,6 @@
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=2
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_MACRONIX=y
@@ -128,5 +129,4 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER_HII is not set
diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig
index e1b602d..1a92501 100644
--- a/configs/sama5d2_icp_mmc_defconfig
+++ b/configs/sama5d2_icp_mmc_defconfig
@@ -9,9 +9,11 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0
+CONFIG_SF_DEFAULT_SPEED=66000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_icp"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -86,7 +88,6 @@
 CONFIG_MMC_SDHCI_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=2
-CONFIG_SF_DEFAULT_SPEED=66000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_MACRONIX=y
@@ -110,5 +111,4 @@
 CONFIG_SPL_TIMER=y
 CONFIG_ATMEL_TCB_TIMER=y
 CONFIG_SPL_ATMEL_TCB_TIMER=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER_HII is not set
diff --git a/configs/sama5d2_icp_qspiflash_defconfig b/configs/sama5d2_icp_qspiflash_defconfig
index 1fe72e8..a884bc2 100644
--- a/configs/sama5d2_icp_qspiflash_defconfig
+++ b/configs/sama5d2_icp_qspiflash_defconfig
@@ -5,9 +5,11 @@
 CONFIG_TARGET_SAMA5D2_ICP=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0
+CONFIG_SF_DEFAULT_SPEED=66000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_icp"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DEBUG_UART_BASE=0xf801c000
 CONFIG_DEBUG_UART_CLOCK=83000000
 CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -73,7 +75,6 @@
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=2
-CONFIG_SF_DEFAULT_SPEED=66000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_MACRONIX=y
@@ -98,5 +99,4 @@
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER_HII is not set
diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig b/configs/sama5d2_ptc_ek_mmc_defconfig
index 3e72444..70f6102 100644
--- a/configs/sama5d2_ptc_ek_mmc_defconfig
+++ b/configs/sama5d2_ptc_ek_mmc_defconfig
@@ -10,6 +10,7 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_ptc_ek"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DEBUG_UART_BASE=0xf801c000
 CONFIG_DEBUG_UART_CLOCK=82000000
 CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -82,4 +83,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig b/configs/sama5d2_ptc_ek_nandflash_defconfig
index 5bfe90b..e55b140 100644
--- a/configs/sama5d2_ptc_ek_nandflash_defconfig
+++ b/configs/sama5d2_ptc_ek_nandflash_defconfig
@@ -9,6 +9,7 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_ptc_ek"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DEBUG_UART_BASE=0xf801c000
 CONFIG_DEBUG_UART_CLOCK=82000000
 CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -82,4 +83,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig
index 33f1b69..c1babc4 100644
--- a/configs/sama5d2_xplained_emmc_defconfig
+++ b/configs/sama5d2_xplained_emmc_defconfig
@@ -9,10 +9,12 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -82,7 +84,6 @@
 CONFIG_MMC_SDHCI_ATMEL=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -118,4 +119,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index 7b6a3d2..afc4604 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -10,10 +10,12 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -84,7 +86,6 @@
 CONFIG_MMC_SDHCI_ATMEL=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -120,4 +121,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig
index b189223..cecee28 100644
--- a/configs/sama5d2_xplained_qspiflash_defconfig
+++ b/configs/sama5d2_xplained_qspiflash_defconfig
@@ -10,10 +10,12 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -84,7 +86,6 @@
 CONFIG_MMC_SDHCI_ATMEL=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -120,4 +121,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index afa24d9..9a15026 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -10,6 +10,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x6000
 CONFIG_ENV_SECT_SIZE=0x1000
@@ -17,6 +18,7 @@
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
@@ -88,7 +90,6 @@
 CONFIG_MMC_SDHCI_ATMEL=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -124,4 +125,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig
index 4af21d0..066c624 100644
--- a/configs/sama5d36ek_cmp_mmc_defconfig
+++ b/configs/sama5d36ek_cmp_mmc_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
@@ -57,7 +58,6 @@
 CONFIG_PMECC_CAP=4
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig
index db2915b..857e55d 100644
--- a/configs/sama5d36ek_cmp_nandflash_defconfig
+++ b/configs/sama5d36ek_cmp_nandflash_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
 CONFIG_DEBUG_UART_BASE=0xffffee00
@@ -57,7 +58,6 @@
 CONFIG_PMECC_CAP=4
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig
index 3136813..4fbda88 100644
--- a/configs/sama5d36ek_cmp_spiflash_defconfig
+++ b/configs/sama5d36ek_cmp_spiflash_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x6000
 CONFIG_ENV_SECT_SIZE=0x1000
@@ -59,7 +60,6 @@
 CONFIG_PMECC_CAP=4
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index 8bc2b84..e73dc0d 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
 CONFIG_SPL_TEXT_BASE=0x300000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -110,4 +111,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index 32c5b3e..7939f3d 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
 CONFIG_SPL_TEXT_BASE=0x300000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x318000
@@ -113,4 +114,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index 8c501b2..5a0b551 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -10,6 +10,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
@@ -93,7 +94,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index 1958f58..cba36f7 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -10,6 +10,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
 CONFIG_SPL_TEXT_BASE=0x300000
@@ -95,7 +96,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index f56442f..1ed1179 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -10,6 +10,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x6000
 CONFIG_ENV_SECT_SIZE=0x1000
@@ -94,7 +95,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index 60d8ea2..fce8bed 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -10,10 +10,12 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -84,7 +86,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
@@ -115,4 +116,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index 25bbe28..0640e20 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -10,9 +10,11 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
@@ -88,7 +90,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
@@ -119,4 +120,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index 0485c69..2d8628e 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -10,6 +10,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x6000
 CONFIG_ENV_SECT_SIZE=0x1000
@@ -17,6 +18,7 @@
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
 CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
@@ -90,7 +92,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
@@ -121,4 +122,3 @@
 CONFIG_W1_GPIO=y
 CONFIG_W1_EEPROM=y
 CONFIG_W1_EEPROM_DS24XXX=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index a1b53a4..4d3042b 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -10,6 +10,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
@@ -82,7 +83,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index e76b18c..3d453c5 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -10,6 +10,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
 CONFIG_SPL_TEXT_BASE=0x200000
@@ -86,7 +87,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index 022ac91..afa6ddf 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -10,6 +10,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x6000
 CONFIG_ENV_SECT_SIZE=0x1000
@@ -85,7 +86,6 @@
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
diff --git a/configs/sama7g5ek_mmc1_defconfig b/configs/sama7g5ek_mmc1_defconfig
index 44b9d15..2f3ccb3 100644
--- a/configs/sama7g5ek_mmc1_defconfig
+++ b/configs/sama7g5ek_mmc1_defconfig
@@ -9,6 +9,7 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama7g5ek"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DEBUG_UART_BASE=0xe1824200
 CONFIG_DEBUG_UART_CLOCK=200000000
 CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -77,6 +78,5 @@
 CONFIG_SYSRESET_AT91=y
 CONFIG_TIMER=y
 CONFIG_MCHP_PIT64B_TIMER=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER_HII is not set
 CONFIG_PHANDLE_CHECK_SEQ=y
diff --git a/configs/sama7g5ek_mmc_defconfig b/configs/sama7g5ek_mmc_defconfig
index bac919d..c5cbd89 100644
--- a/configs/sama7g5ek_mmc_defconfig
+++ b/configs/sama7g5ek_mmc_defconfig
@@ -9,6 +9,7 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama7g5ek"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DEBUG_UART_BASE=0xe1824200
 CONFIG_DEBUG_UART_CLOCK=200000000
 CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -77,6 +78,5 @@
 CONFIG_SYSRESET_AT91=y
 CONFIG_TIMER=y
 CONFIG_MCHP_PIT64B_TIMER=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER_HII is not set
 CONFIG_PHANDLE_CHECK_SEQ=y
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index af2c56a..f5cfdc4 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -6,6 +6,7 @@
 CONFIG_PRE_CON_BUF_ADDR=0x100000
 CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_SYS_LOAD_ADDR=0x0
+CONFIG_PCI=y
 CONFIG_SANDBOX64=y
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_MEMTEST_START=0x00100000
@@ -141,7 +142,6 @@
 CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_I2C_CROS_EC_LDO=y
 CONFIG_DM_I2C_GPIO=y
-CONFIG_SYS_I2C_SANDBOX=y
 CONFIG_I2C_MUX=y
 CONFIG_I2C_ARB_GPIO_CHALLENGE=y
 CONFIG_CROS_EC_KEYB=y
@@ -173,8 +173,8 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_NVMXIP_QSPI=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCI_SANDBOX=y
 CONFIG_PHY=y
 CONFIG_PHY_SANDBOX=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 657de0a..24a4448 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -6,6 +6,7 @@
 CONFIG_PRE_CON_BUF_ADDR=0xf0000
 CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_SYS_LOAD_ADDR=0x0
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_MEMTEST_START=0x00100000
 CONFIG_SYS_MEMTEST_END=0x00101000
@@ -100,6 +101,7 @@
 CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
 CONFIG_CMD_ETHSW=y
+CONFIG_CMD_2048=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_BOOTCOUNT=y
 CONFIG_CMD_EFIDEBUG=y
@@ -188,7 +190,6 @@
 CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_I2C_CROS_EC_LDO=y
 CONFIG_DM_I2C_GPIO=y
-CONFIG_SYS_I2C_SANDBOX=y
 CONFIG_I2C_MUX=y
 CONFIG_I2C_ARB_GPIO_CHALLENGE=y
 CONFIG_CROS_EC_KEYB=y
@@ -226,7 +227,6 @@
 CONFIG_MULTIPLEXER=y
 CONFIG_MUX_MMIO=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_PCI_SANDBOX=y
 CONFIG_PHY=y
@@ -342,4 +342,3 @@
 CONFIG_UNIT_TEST=y
 CONFIG_UT_TIME=y
 CONFIG_UT_DM=y
-CONFIG_CMD_2048=y
diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig
index 8c2bcea..5b6b28a 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -5,6 +5,7 @@
 CONFIG_DM_RESET=y
 CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_SYS_LOAD_ADDR=0x0
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_MEMTEST_START=0x00100000
 CONFIG_SYS_MEMTEST_END=0x00101000
@@ -116,7 +117,6 @@
 CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_I2C_CROS_EC_LDO=y
 CONFIG_DM_I2C_GPIO=y
-CONFIG_SYS_I2C_SANDBOX=y
 CONFIG_I2C_MUX=y
 CONFIG_I2C_ARB_GPIO_CHALLENGE=y
 CONFIG_CROS_EC_KEYB=y
@@ -149,7 +149,6 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_PCI_SANDBOX=y
 CONFIG_PHY=y
@@ -217,7 +216,6 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_CMD_DHRYSTONE=y
-CONFIG_RSA_VERIFY_WITH_PKEY=y
 CONFIG_TPM=y
 CONFIG_LZ4=y
 CONFIG_ZSTD=y
diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig
index 0b52bf8..fc20317 100644
--- a/configs/sandbox_noinst_defconfig
+++ b/configs/sandbox_noinst_defconfig
@@ -12,6 +12,7 @@
 CONFIG_SPL=y
 CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_SYS_LOAD_ADDR=0x0
+CONFIG_PCI=y
 CONFIG_SANDBOX_SPL=y
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_MEMTEST_START=0x00100000
@@ -132,7 +133,6 @@
 CONFIG_I2C_CROS_EC_LDO=y
 CONFIG_DM_I2C_GPIO=y
 # CONFIG_SPL_DM_I2C_GPIO is not set
-CONFIG_SYS_I2C_SANDBOX=y
 CONFIG_I2C_MUX=y
 CONFIG_I2C_ARB_GPIO_CHALLENGE=y
 CONFIG_CROS_EC_KEYB=y
@@ -164,7 +164,6 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCI_SANDBOX=y
 CONFIG_PHY=y
 CONFIG_PHY_SANDBOX=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index bf5469b..dd848c5 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -12,6 +12,7 @@
 CONFIG_SPL=y
 CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_SYS_LOAD_ADDR=0x0
+CONFIG_PCI=y
 CONFIG_SANDBOX_SPL=y
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_MEMTEST_START=0x00100000
@@ -136,7 +137,6 @@
 CONFIG_I2C_CROS_EC_LDO=y
 CONFIG_DM_I2C_GPIO=y
 # CONFIG_SPL_DM_I2C_GPIO is not set
-CONFIG_SYS_I2C_SANDBOX=y
 CONFIG_I2C_MUX=y
 CONFIG_I2C_ARB_GPIO_CHALLENGE=y
 CONFIG_CROS_EC_KEYB=y
@@ -170,7 +170,6 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCI_SANDBOX=y
 CONFIG_PHY=y
 CONFIG_PHY_SANDBOX=y
diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig
index 232f2ff..27971c0 100644
--- a/configs/sandbox_vpl_defconfig
+++ b/configs/sandbox_vpl_defconfig
@@ -17,6 +17,7 @@
 CONFIG_SPL=y
 CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_SYS_LOAD_ADDR=0x0
+CONFIG_PCI=y
 CONFIG_SANDBOX_SPL=y
 CONFIG_SANDBOX_TPL=y
 CONFIG_SANDBOX_VPL=y
@@ -148,7 +149,6 @@
 CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_I2C_CROS_EC_LDO=y
 CONFIG_DM_I2C_GPIO=y
-CONFIG_SYS_I2C_SANDBOX=y
 CONFIG_I2C_MUX=y
 CONFIG_I2C_ARB_GPIO_CHALLENGE=y
 CONFIG_CROS_EC_KEYB=y
@@ -179,7 +179,6 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_NVME=y
-CONFIG_PCI=y
 CONFIG_PCI_SANDBOX=y
 CONFIG_PHY=y
 CONFIG_PHY_SANDBOX=y
diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig
index 19362c9..63e4ebe 100644
--- a/configs/sei510_defconfig
+++ b/configs/sei510_defconfig
@@ -11,6 +11,7 @@
 CONFIG_ENV_OFFSET=0xFFFF0000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-sei510"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
@@ -94,4 +95,3 @@
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
 CONFIG_LIBAVB=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sei610_defconfig b/configs/sei610_defconfig
index 677b618..ff7bcb3 100644
--- a/configs/sei610_defconfig
+++ b/configs/sei610_defconfig
@@ -11,6 +11,7 @@
 CONFIG_ENV_OFFSET=0xFFFF0000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-sei610"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
@@ -94,4 +95,3 @@
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
 CONFIG_LIBAVB=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig
index ae0f9b4..f9f0346 100644
--- a/configs/sifive_unleashed_defconfig
+++ b/configs/sifive_unleashed_defconfig
@@ -17,7 +17,6 @@
 CONFIG_TARGET_SIFIVE_UNLEASHED=y
 CONFIG_ARCH_RV64I=y
 CONFIG_RISCV_SMODE=y
-CONFIG_STANDALONE_LOAD_ADDR=0x80200000
 CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
index c24feb6..ffae865 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -16,11 +16,11 @@
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x80200000
 CONFIG_SYS_PCI_64BIT=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_TARGET_SIFIVE_UNMATCHED=y
 CONFIG_ARCH_RV64I=y
 CONFIG_RISCV_SMODE=y
-CONFIG_STANDALONE_LOAD_ADDR=0x80200000
 CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
 CONFIG_DISTRO_DEFAULTS=y
@@ -56,7 +56,6 @@
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCIE_DW_SIFIVE=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
diff --git a/configs/silinux_ek874_defconfig b/configs/silinux_ek874_defconfig
index 65dead7..f79848e 100644
--- a/configs/silinux_ek874_defconfig
+++ b/configs/silinux_ek874_defconfig
@@ -85,4 +85,3 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index a212098..0f68e8a 100644
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig
@@ -29,6 +29,7 @@
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x50000000
 CONFIG_ENV_ADDR=0xC0000
+CONFIG_PCI=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
@@ -89,7 +90,6 @@
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
 CONFIG_SH_ETHER=y
-CONFIG_PCI=y
 CONFIG_PCI_RCAR_GEN2=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig
index 33f7fdc..a349b3d 100644
--- a/configs/smdk5250_defconfig
+++ b/configs/smdk5250_defconfig
@@ -13,6 +13,7 @@
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2050000
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x3FC000
 CONFIG_ENV_SECT_SIZE=0x4000
@@ -53,7 +54,6 @@
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_S5P=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SMC911X=y
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index 3493902..da66c5f 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -11,6 +11,7 @@
 CONFIG_NR_DRAM_BANKS=7
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2073800
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x3FC000
 CONFIG_ENV_SECT_SIZE=0x4000
@@ -48,7 +49,6 @@
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_S5P=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SMC911X=y
diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index 1e0b9aa..3d2713f 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -7,6 +7,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx7d-smegw01"
 CONFIG_TARGET_SMEGW01=y
+# CONFIG_SYS_BOOT_LOCKED is not set
 CONFIG_ENV_OFFSET_REDUND=0x110000
 CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
 # CONFIG_ARMV7_VIRT is not set
@@ -17,19 +18,27 @@
 CONFIG_SYS_MEMTEST_END=0xa0000000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_AUTOBOOT_MENU_SHOW=y
+# CONFIG_BOOTSTD is not set
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="if run loadimage; then run mmcboot; fi; "
+CONFIG_BOOTCOMMAND="if test \"${bootcount}\" -gt \"${bootlimit}\"; then run altbootcmd; else if test \"${ustate}\" = 1; then setenv upgrade_available 1; saveenv; fi; run mmcboot; fi;"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run setup_boot_menu;"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
 # CONFIG_CMD_BOOTD is not set
 CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_BOOTMENU=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_XIMG is not set
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_UNZIP=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
 CONFIG_CMD_DHCP=y
@@ -38,13 +47,20 @@
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_SQUASHFS=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_WRITEABLE_LIST=y
+CONFIG_ENV_ACCESS_IGNORE_FORCE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_BOUNCE_BUFFER=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
 CONFIG_DFU_MMC=y
 CONFIG_DM_I2C=y
 CONFIG_SUPPORT_EMMC_BOOT=y
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index f7aa033..bb066a6 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -13,6 +13,7 @@
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2050000
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x3FC000
 CONFIG_ENV_SECT_SIZE=0x4000
@@ -67,7 +68,6 @@
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_S5P=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SMC911X=y
diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig
index 123eb68..0785157 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x200
 CONFIG_DM_GPIO=y
@@ -74,7 +75,6 @@
 CONFIG_SYS_MMC_MAX_BLK_COUNT=256
 CONFIG_MMC_DW=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
index 8770e64..406fe71 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x101000
+CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x200
 CONFIG_DM_GPIO=y
@@ -68,7 +69,6 @@
 CONFIG_SYS_I2C_DW=y
 CONFIG_SYS_MMC_MAX_BLK_COUNT=256
 CONFIG_MMC_DW=y
-CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig
index 3117f39..037597f 100644
--- a/configs/socfpga_agilex_vab_defconfig
+++ b/configs/socfpga_agilex_vab_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x200
 CONFIG_DM_GPIO=y
@@ -75,7 +76,6 @@
 CONFIG_SYS_MMC_MAX_BLK_COUNT=256
 CONFIG_MMC_DW=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig
index 454e381..f308239 100644
--- a/configs/socfpga_n5x_atf_defconfig
+++ b/configs/socfpga_n5x_atf_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x200
 CONFIG_DM_GPIO=y
@@ -73,7 +74,6 @@
 CONFIG_SYS_MMC_MAX_BLK_COUNT=256
 CONFIG_MMC_DW=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig
index 8d911cd..99a12df 100644
--- a/configs/socfpga_n5x_defconfig
+++ b/configs/socfpga_n5x_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x101000
+CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x200
 CONFIG_DM_GPIO=y
@@ -65,7 +66,6 @@
 CONFIG_SYS_I2C_DW=y
 CONFIG_SYS_MMC_MAX_BLK_COUNT=256
 CONFIG_MMC_DW=y
-CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig
index dbd8184..e82f6cd 100644
--- a/configs/socfpga_n5x_vab_defconfig
+++ b/configs/socfpga_n5x_vab_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x200
 CONFIG_DM_GPIO=y
@@ -74,7 +75,6 @@
 CONFIG_SYS_MMC_MAX_BLK_COUNT=256
 CONFIG_MMC_DW=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig
index 3dc98a2..157391a 100644
--- a/configs/socfpga_secu1_defconfig
+++ b/configs/socfpga_secu1_defconfig
@@ -3,6 +3,7 @@
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_ENV_SOURCE_FILE="socfpga_secu"
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000
 CONFIG_ENV_SIZE=0x2000
@@ -65,7 +66,6 @@
 # CONFIG_CMD_UBIFS is not set
 # CONFIG_ISO_PARTITION is not set
 # CONFIG_EFI_PARTITION is not set
-CONFIG_ENV_SOURCE_FILE="socfpga_secu"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index b609afc..b07e0a3 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -4,6 +4,7 @@
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000
+CONFIG_SF_DEFAULT_SPEED=100000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0xE0000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -65,7 +66,6 @@
 CONFIG_SYS_MMC_MAX_BLK_COUNT=256
 CONFIG_MMC_DW=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=100000000
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig
index d83d7f8..e3e8a63 100644
--- a/configs/socfpga_stratix10_atf_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x200
 CONFIG_DM_GPIO=y
@@ -75,7 +76,6 @@
 CONFIG_SYS_MMC_MAX_BLK_COUNT=256
 CONFIG_MMC_DW=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index ff47984..7d078dd 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -6,6 +6,7 @@
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x101000
+CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x200
 CONFIG_DM_GPIO=y
@@ -73,7 +74,6 @@
 CONFIG_SYS_MMC_MAX_BLK_COUNT=256
 CONFIG_MMC_DW=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 2b07e02..62caec7 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -4,6 +4,7 @@
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -94,7 +95,6 @@
 CONFIG_SYS_MMC_MAX_BLK_COUNT=256
 CONFIG_MMC_DW=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/spring_defconfig b/configs/spring_defconfig
index 64b2296..392d8d6 100644
--- a/configs/spring_defconfig
+++ b/configs/spring_defconfig
@@ -13,6 +13,7 @@
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2050000
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x3FC000
 CONFIG_ENV_SECT_SIZE=0x4000
@@ -63,7 +64,6 @@
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_S5P=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SMC911X=y
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 550d0ff..ffbc4b9 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -5,10 +5,12 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000000
+CONFIG_SF_DEFAULT_SPEED=100000000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.3b"
 CONFIG_SPL_TEXT_BASE=0x8000000
 CONFIG_SYS_PROMPT="StarFive #"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_STACK=0x8180000
@@ -21,8 +23,8 @@
 CONFIG_ARCH_RV64I=y
 CONFIG_CMODEL_MEDANY=y
 CONFIG_RISCV_SMODE=y
-CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_QSPI_BOOT=y
 CONFIG_SD_BOOT=y
 CONFIG_USE_BOOTARGS=y
@@ -60,7 +62,6 @@
 CONFIG_SPL_MMC_HS400_SUPPORT=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_SNPS=y
-CONFIG_SF_DEFAULT_SPEED=100000000
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_ISSI=y
@@ -76,4 +77,3 @@
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_TIMER_EARLY=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/starqltechn_defconfig b/configs/starqltechn_defconfig
index 3d96e0a..5b85ce5 100644
--- a/configs/starqltechn_defconfig
+++ b/configs/starqltechn_defconfig
@@ -17,18 +17,24 @@
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_CBSIZE=512
 CONFIG_SYS_PBSIZE=532
+CONFIG_CMD_BOOTMENU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_BMP=y
 # CONFIG_NET is not set
+CONFIG_BUTTON=y
 CONFIG_CLK=y
 CONFIG_MSM_GPIO=y
 CONFIG_QCOM_PMIC_GPIO=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_BUTTON_KEYBOARD=y
 CONFIG_PINCTRL=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_QCOM=y
 CONFIG_MSM_GENI_SERIAL=y
 CONFIG_SPMI_MSM=y
 CONFIG_VIDEO=y
+# CONFIG_VIDEO_FONT_8X16 is not set
+CONFIG_VIDEO_FONT_16X32=y
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_SIMPLE=y
 CONFIG_VIDEO_DT_SIMPLEFB=y
diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig
index 4965680..edfb195 100644
--- a/configs/stih410-b2260_defconfig
+++ b/configs/stih410-b2260_defconfig
@@ -10,6 +10,7 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DEFAULT_DEVICE_TREE="stih410-b2260"
 CONFIG_SYS_PROMPT="stih410-b2260 => "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_IDENT_STRING="STMicroelectronics STiH410-B2260"
 CONFIG_SYS_LOAD_ADDR=0x40000000
 CONFIG_FIT=y
@@ -67,4 +68,3 @@
 CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
 CONFIG_USB_GADGET_VENDOR_NUM=0x483
 CONFIG_USB_GADGET_PRODUCT_NUM=0x7270
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/stm32746g-eval_defconfig b/configs/stm32746g-eval_defconfig
index b150001..d7c30b6 100644
--- a/configs/stm32746g-eval_defconfig
+++ b/configs/stm32746g-eval_defconfig
@@ -8,6 +8,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="stm32746g-eval"
 CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_STM32F7=y
 CONFIG_TARGET_STM32F746_DISCO=y
 CONFIG_SYS_LOAD_ADDR=0x8008000
@@ -65,4 +66,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig
index 1a4ff8d..8c3997f 100644
--- a/configs/stm32746g-eval_spl_defconfig
+++ b/configs/stm32746g-eval_spl_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="stm32746g-eval"
 CONFIG_SPL_TEXT_BASE=0x8000000
 CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_SIZE_LIMIT=0x9000
@@ -91,4 +92,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index ca288e1..3ce50ae 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -8,6 +8,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco"
 CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_STM32F7=y
 CONFIG_TARGET_STM32F746_DISCO=y
 CONFIG_SYS_LOAD_ADDR=0x8008000
@@ -65,4 +66,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig
index 4e42e1d..95fb629 100644
--- a/configs/stm32f746-disco_spl_defconfig
+++ b/configs/stm32f746-disco_spl_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco"
 CONFIG_SPL_TEXT_BASE=0x8000000
 CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_SIZE_LIMIT=0x9000
@@ -91,4 +92,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig
index 68c4105..3454f58 100644
--- a/configs/stm32f769-disco_defconfig
+++ b/configs/stm32f769-disco_defconfig
@@ -8,6 +8,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco"
 CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_STM32F7=y
 CONFIG_TARGET_STM32F746_DISCO=y
 CONFIG_SYS_LOAD_ADDR=0x8008000
@@ -67,4 +68,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig
index e849bff..b4e9feb 100644
--- a/configs/stm32f769-disco_spl_defconfig
+++ b/configs/stm32f769-disco_spl_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco"
 CONFIG_SPL_TEXT_BASE=0x8000000
 CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_SIZE_LIMIT=0x9000
@@ -93,4 +94,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/stm32h743-disco_defconfig b/configs/stm32h743-disco_defconfig
index 4e4325c..3d9d8fc 100644
--- a/configs/stm32h743-disco_defconfig
+++ b/configs/stm32h743-disco_defconfig
@@ -8,6 +8,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-disco"
 CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_STM32H7=y
 CONFIG_TARGET_STM32H743_DISCO=y
 CONFIG_SYS_LOAD_ADDR=0xd0400000
@@ -32,4 +33,3 @@
 # CONFIG_NET is not set
 CONFIG_STM32_SDMMC2=y
 # CONFIG_PINCTRL_FULL is not set
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/stm32h743-eval_defconfig b/configs/stm32h743-eval_defconfig
index d5513c5..57aa48f 100644
--- a/configs/stm32h743-eval_defconfig
+++ b/configs/stm32h743-eval_defconfig
@@ -8,6 +8,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-eval"
 CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_STM32H7=y
 CONFIG_TARGET_STM32H743_EVAL=y
 CONFIG_SYS_LOAD_ADDR=0xd0400000
@@ -32,4 +33,3 @@
 # CONFIG_NET is not set
 CONFIG_STM32_SDMMC2=y
 # CONFIG_PINCTRL_FULL is not set
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/stm32h750-art-pi_defconfig b/configs/stm32h750-art-pi_defconfig
index e4b6596..3e4c7f9 100644
--- a/configs/stm32h750-art-pi_defconfig
+++ b/configs/stm32h750-art-pi_defconfig
@@ -8,6 +8,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="stm32h750i-art-pi"
 CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_STM32H7=y
 CONFIG_TARGET_STM32H750_ART_PI=y
 CONFIG_SYS_LOAD_ADDR=0xc1800000
@@ -40,4 +41,3 @@
 CONFIG_STM32_SDMMC2=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_BAUDRATE=2000000
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index 086e6bc..13355eb 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -46,7 +46,6 @@
 CONFIG_SPL_SPI_FLASH_MTD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
 CONFIG_FDT_SIMPLEFB=y
-CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
 CONFIG_SYS_PBSIZE=1050
 CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_CMD_ADTIMG=y
@@ -169,6 +168,7 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_ONBOARD_HUB=y
+CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0483
diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig
index a8eda7b..2669aae 100644
--- a/configs/stm32mp15_defconfig
+++ b/configs/stm32mp15_defconfig
@@ -22,7 +22,6 @@
 CONFIG_BOOTDELAY=1
 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
 CONFIG_FDT_SIMPLEFB=y
-CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
 CONFIG_SYS_PBSIZE=1050
 CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_CMD_ADTIMG=y
@@ -145,6 +144,7 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_ONBOARD_HUB=y
+CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0483
diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
index 02892c6..93494f8 100644
--- a/configs/stm32mp15_dhcom_basic_defconfig
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_F_LEN=0x3000
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_SPL_DM_SPI=y
@@ -124,7 +125,6 @@
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig
index 1133b23..b54ff93 100644
--- a/configs/stm32mp15_dhcor_basic_defconfig
+++ b/configs/stm32mp15_dhcor_basic_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_F_LEN=0x3000
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_SPL_DM_SPI=y
@@ -121,7 +122,6 @@
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index 2269156..5f0fb45 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -23,7 +23,6 @@
 CONFIG_BOOTDELAY=1
 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
 CONFIG_FDT_SIMPLEFB=y
-CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
 CONFIG_SYS_PBSIZE=1050
 CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_CMD_ADTIMG=y
@@ -145,6 +144,7 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_ONBOARD_HUB=y
+CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0483
diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig
index b8d354f..adb64e9 100644
--- a/configs/stmark2_defconfig
+++ b/configs/stmark2_defconfig
@@ -1,6 +1,7 @@
 CONFIG_M68K=y
 CONFIG_TEXT_BASE=0x47E00000
 CONFIG_SYS_MALLOC_LEN=0x40000
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x40000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -26,6 +27,7 @@
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
@@ -39,9 +41,10 @@
 CONFIG_USE_HOSTNAME=y
 CONFIG_HOSTNAME="stmark2"
 # CONFIG_NET is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_FSL=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_MCFUART=y
@@ -49,7 +52,3 @@
 CONFIG_DM_SPI=y
 CONFIG_CF_SPI=y
 CONFIG_REGEX=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_DM_I2C=y
-CONFIG_CMD_I2C=y
-CONFIG_SYS_I2C_FSL=y
diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index fb7ec0a..4eba6db 100644
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig
@@ -29,6 +29,7 @@
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x50000000
 CONFIG_ENV_ADDR=0xC0000
+CONFIG_PCI=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
@@ -87,7 +88,6 @@
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
 CONFIG_SH_ETHER=y
-CONFIG_PCI=y
 CONFIG_PCI_RCAR_GEN2=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig
index 08f19a9..68f7bac 100644
--- a/configs/synquacer_developerbox_defconfig
+++ b/configs/synquacer_developerbox_defconfig
@@ -5,6 +5,7 @@
 CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xe0000000
+CONFIG_SF_DEFAULT_SPEED=31250000
 CONFIG_ENV_SIZE=0x30000
 CONFIG_ENV_OFFSET=0x300000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -65,7 +66,6 @@
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=31250000
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 112a8da..ee4dca4 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -12,6 +12,7 @@
 CONFIG_SYS_PROMPT="Matrix U-Boot> "
 CONFIG_PRE_CON_BUF_ADDR=0x7c000000
 CONFIG_CMD_HDMIDETECT=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x10000000
 CONFIG_SYS_MEMTEST_END=0x2f400000
@@ -80,7 +81,6 @@
 CONFIG_PHY_ATHEROS=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
-CONFIG_PCI=y
 # CONFIG_PCI_PNP is not set
 CONFIG_PCI_SCAN_SHOW=y
 CONFIG_PCIE_IMX=y
diff --git a/configs/tbs_a711_defconfig b/configs/tbs_a711_defconfig
index b3c2e69..9a70b6b 100644
--- a/configs/tbs_a711_defconfig
+++ b/configs/tbs_a711_defconfig
@@ -9,11 +9,11 @@
 CONFIG_DRAM_ODT_EN=y
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH11"
 CONFIG_AXP_GPIO=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DCDC5_VOLT=1200
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index e0b0469..442cee3 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -3,6 +3,7 @@
 CONFIG_ARCH_TEGRA=y
 CONFIG_TEXT_BASE=0x80110000
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-tec-ng"
@@ -42,7 +43,6 @@
 CONFIG_SYS_MMC_ENV_PART=2
 CONFIG_SPL_DM=y
 CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_TEGRA20_SLINK=y
diff --git a/configs/ten64_tfa_defconfig b/configs/ten64_tfa_defconfig
index 2396d9e..9797a34 100644
--- a/configs/ten64_tfa_defconfig
+++ b/configs/ten64_tfa_defconfig
@@ -12,6 +12,7 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_TEN64_CONTROLLER=y
+CONFIG_PCI=y
 CONFIG_AHCI=y
 CONFIG_SYS_FSL_NUM_CC_PLLS=3
 CONFIG_MP=y
@@ -75,13 +76,14 @@
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_RX8025=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
index 9828a9a..e3444fc 100644
--- a/configs/theadorable_debug_defconfig
+++ b/configs/theadorable_debug_defconfig
@@ -8,6 +8,7 @@
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
 CONFIG_TARGET_THEADORABLE=y
+CONFIG_SF_DEFAULT_SPEED=27777777
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x40000
@@ -20,6 +21,7 @@
 CONFIG_DEBUG_UART_CLOCK=250000000
 CONFIG_SYS_MEM_TOP_HIDE=0x80000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FIT=y
@@ -74,7 +76,6 @@
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MVTWSI=y
 # CONFIG_MMC is not set
-CONFIG_SF_DEFAULT_SPEED=27777777
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_MARVELL=y
@@ -82,7 +83,6 @@
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_MVMDIO=y
-CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index 2a9a4ba..63f9566 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -8,6 +8,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker"
 CONFIG_DM_RESET=y
@@ -68,7 +69,6 @@
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PINCTRL=y
diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig
index e9c6d52..2566525 100644
--- a/configs/tinker-s-rk3288_defconfig
+++ b/configs/tinker-s-rk3288_defconfig
@@ -9,6 +9,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker-s"
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3288=y
@@ -68,7 +69,6 @@
 CONFIG_I2C_EEPROM=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PINCTRL=y
diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig
index 23e1f0e..2bc3bd9 100644
--- a/configs/tools-only_defconfig
+++ b/configs/tools-only_defconfig
@@ -3,6 +3,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="sandbox"
 CONFIG_SYS_LOAD_ADDR=0x0
+CONFIG_PCI=y
 # CONFIG_SANDBOX_SDL is not set
 CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_FIT=y
@@ -24,7 +25,6 @@
 CONFIG_AXI=y
 CONFIG_AXI_SANDBOX=y
 CONFIG_SANDBOX_GPIO=y
-CONFIG_PCI=y
 CONFIG_PCI_SANDBOX=y
 CONFIG_DM_RTC=y
 CONFIG_SOUND=y
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index c9fadb2..ef1b66e 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -5,6 +5,7 @@
 CONFIG_SYS_L2CACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_TEXT_BASE=0x4000000
+CONFIG_SF_DEFAULT_SPEED=108000000
 CONFIG_ENV_SIZE=0x8000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami"
@@ -61,7 +62,6 @@
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SF_DEFAULT_SPEED=108000000
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_DEBUG_UART_ZYNQ=y
diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index 9c63f22..af829ac 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -5,6 +5,7 @@
 CONFIG_SYS_L2CACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_TEXT_BASE=0x4000000
+CONFIG_SF_DEFAULT_SPEED=108000000
 CONFIG_ENV_SIZE=0x8000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite"
@@ -61,7 +62,6 @@
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SF_DEFAULT_SPEED=108000000
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_DEBUG_UART_ZYNQ=y
diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index a436f26..9287b1d 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -5,6 +5,7 @@
 CONFIG_SYS_L2CACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_TEXT_BASE=0x4000000
+CONFIG_SF_DEFAULT_SPEED=108000000
 CONFIG_ENV_SIZE=0x8000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus"
@@ -61,7 +62,6 @@
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SF_DEFAULT_SPEED=108000000
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_DEBUG_UART_ZYNQ=y
diff --git a/configs/total_compute_defconfig b/configs/total_compute_defconfig
index dd9f509..d25ed38 100644
--- a/configs/total_compute_defconfig
+++ b/configs/total_compute_defconfig
@@ -8,6 +8,7 @@
 CONFIG_ENV_SIZE=0x2a00000
 CONFIG_DEFAULT_DEVICE_TREE="total_compute"
 CONFIG_SYS_PROMPT="TOTAL_COMPUTE# "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_LOAD_ADDR=0x90000000
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0xff000000
@@ -60,4 +61,3 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_LIBAVB=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig
index 34d0ddd..e439214 100644
--- a/configs/tqma6dl_mba6_mmc_defconfig
+++ b/configs/tqma6dl_mba6_mmc_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_MALLOC_LEN=0x202000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_MX6DL=y
@@ -46,7 +47,6 @@
 CONFIG_SYS_I2C_MXC=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x50
 CONFIG_FSL_USDHC=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig
index 1bd7f8d..c4509c6 100644
--- a/configs/tqma6dl_mba6_spi_defconfig
+++ b/configs/tqma6dl_mba6_spi_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_MALLOC_LEN=0x202000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x80000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -50,7 +51,6 @@
 CONFIG_SYS_I2C_MXC=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x50
 CONFIG_FSL_USDHC=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig
index f1f4232..64f7160 100644
--- a/configs/tqma6q_mba6_mmc_defconfig
+++ b/configs/tqma6q_mba6_mmc_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_MALLOC_LEN=0x202000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_MX6Q=y
@@ -46,7 +47,6 @@
 CONFIG_SYS_I2C_MXC=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x50
 CONFIG_FSL_USDHC=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig
index cc8616f..8256f53 100644
--- a/configs/tqma6q_mba6_spi_defconfig
+++ b/configs/tqma6q_mba6_spi_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_MALLOC_LEN=0x202000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x80000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -50,7 +51,6 @@
 CONFIG_SYS_I2C_MXC=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x50
 CONFIG_FSL_USDHC=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig
index bd9476c..cdf0add 100644
--- a/configs/tqma6s_mba6_mmc_defconfig
+++ b/configs/tqma6s_mba6_mmc_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_MALLOC_LEN=0x202000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_MX6S=y
@@ -46,7 +47,6 @@
 CONFIG_SYS_I2C_MXC=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x50
 CONFIG_FSL_USDHC=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig
index a9aa3fc..06fe342 100644
--- a/configs/tqma6s_mba6_spi_defconfig
+++ b/configs/tqma6s_mba6_spi_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_MALLOC_LEN=0x202000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x80000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -50,7 +51,6 @@
 CONFIG_SYS_I2C_MXC=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x50
 CONFIG_FSL_USDHC=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index 0dd304a..d94a0b4 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -14,6 +14,7 @@
 CONFIG_TEGRA20=y
 CONFIG_TARGET_TRIMSLICE=y
 CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_PCI=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_CONSOLE_MUX=y
 CONFIG_SYS_STDIO_DEREGISTER=y
@@ -46,7 +47,6 @@
 CONFIG_SYS_I2C_TEGRA=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_RTL8169=y
-CONFIG_PCI=y
 CONFIG_PCI_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_TEGRA20_SFLASH=y
diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index 6df74b5..c10b5c2 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xF0000000
+CONFIG_ENV_SOURCE_FILE="km83xx"
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="kmtuge1"
@@ -21,7 +22,6 @@
 CONFIG_BAT0_LENGTH_256_MBYTES=y
 CONFIG_BAT0_ACCESS_RW=y
 CONFIG_BAT0_ICACHE_INHIBITED=y
-CONFIG_BAT0_ICACHE_GUARDED=y
 CONFIG_BAT0_DCACHE_INHIBITED=y
 CONFIG_BAT0_DCACHE_GUARDED=y
 CONFIG_BAT0_USER_MODE_VALID=y
@@ -32,7 +32,6 @@
 CONFIG_BAT1_LENGTH_4_MBYTES=y
 CONFIG_BAT1_ACCESS_RW=y
 CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
 CONFIG_BAT1_DCACHE_INHIBITED=y
 CONFIG_BAT1_DCACHE_GUARDED=y
 CONFIG_BAT1_USER_MODE_VALID=y
@@ -95,6 +94,7 @@
 CONFIG_LCRR_EADC_1=y
 CONFIG_LCRR_CLKDIV_2=y
 CONFIG_83XX_PCICLK=0x3ef1480
+# CONFIG_PCI is not set
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -129,7 +129,6 @@
 CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
 CONFIG_CMD_UBI=y
 # CONFIG_CMD_UBIFS is not set
-CONFIG_ENV_SOURCE_FILE="km83xx"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR_REDUND=0xF00E0000
@@ -164,7 +163,6 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_QE_UEC=y
-# CONFIG_PCI is not set
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_QE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig
index db442a1..234f1e7 100644
--- a/configs/turris_mox_defconfig
+++ b/configs/turris_mox_defconfig
@@ -6,6 +6,7 @@
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
 CONFIG_TARGET_TURRIS_MOX=y
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x180000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -13,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="armada-3720-turris-mox"
 CONFIG_DEBUG_UART_BASE=0xd0012000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 CONFIG_OF_BOARD_FIXUP=y
@@ -26,7 +28,6 @@
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SYS_MAXARGS=32
@@ -47,7 +48,6 @@
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
 CONFIG_CMD_AES=y
 CONFIG_CMD_HASH=y
 CONFIG_CMD_BTRFS=y
@@ -76,7 +76,6 @@
 CONFIG_MMC_SDHCI_XENON=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -87,7 +86,6 @@
 CONFIG_MVNETA=y
 CONFIG_MVMDIO=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCI_AARDVARK=y
 CONFIG_PHY=y
 CONFIG_MVEBU_COMPHY_SUPPORT=y
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index 70a1fad..22aaee2 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -11,9 +11,9 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
 CONFIG_TARGET_TURRIS_OMNIA=y
 CONFIG_DDR_RESET_ON_TRAINING_FAILURE=y
-CONFIG_MVEBU_EFUSE=y
 CONFIG_MVEBU_EFUSE_VHV_GPIO="mcu_56"
 CONFIG_MVEBU_EFUSE_VHV_GPIO_ACTIVE_LOW=y
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xF0000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -25,6 +25,7 @@
 CONFIG_DEBUG_UART_BASE=0xf1012000
 CONFIG_DEBUG_UART_CLOCK=250000000
 CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 CONFIG_OF_BOARD_FIXUP=y
@@ -89,7 +90,6 @@
 CONFIG_MMC_SDHCI_MV=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
-CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_WINBOND=y
@@ -101,7 +101,6 @@
 CONFIG_MII=y
 CONFIG_MVMDIO=y
 CONFIG_NVME_PCI=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_ARMADA_38X=y
diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index 837098f..f61fb96 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_TEXT_BASE=0xF0000000
+CONFIG_ENV_SOURCE_FILE="km83xx"
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="kmtuxa1"
@@ -21,7 +22,6 @@
 CONFIG_BAT0_LENGTH_256_MBYTES=y
 CONFIG_BAT0_ACCESS_RW=y
 CONFIG_BAT0_ICACHE_INHIBITED=y
-CONFIG_BAT0_ICACHE_GUARDED=y
 CONFIG_BAT0_DCACHE_INHIBITED=y
 CONFIG_BAT0_DCACHE_GUARDED=y
 CONFIG_BAT0_USER_MODE_VALID=y
@@ -32,7 +32,6 @@
 CONFIG_BAT1_LENGTH_4_MBYTES=y
 CONFIG_BAT1_ACCESS_RW=y
 CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
 CONFIG_BAT1_DCACHE_INHIBITED=y
 CONFIG_BAT1_DCACHE_GUARDED=y
 CONFIG_BAT1_USER_MODE_VALID=y
@@ -109,6 +108,7 @@
 CONFIG_LCRR_EADC_1=y
 CONFIG_LCRR_CLKDIV_2=y
 CONFIG_83XX_PCICLK=0x3ef1480
+# CONFIG_PCI is not set
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -143,7 +143,6 @@
 CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
 CONFIG_CMD_UBI=y
 # CONFIG_CMD_UBIFS is not set
-CONFIG_ENV_SOURCE_FILE="km83xx"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR_REDUND=0xF00E0000
@@ -181,7 +180,6 @@
 CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_QE_UEC=y
-# CONFIG_PCI is not set
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_QE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/u200_defconfig b/configs/u200_defconfig
index 83f5235..a841a66 100644
--- a/configs/u200_defconfig
+++ b/configs/u200_defconfig
@@ -7,6 +7,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-u200"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
 CONFIG_DEBUG_UART_BASE=0xff803000
@@ -56,4 +57,3 @@
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig
index 2b7814d..fa19895 100644
--- a/configs/uDPU_defconfig
+++ b/configs/uDPU_defconfig
@@ -22,7 +22,6 @@
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=1048
@@ -41,7 +40,6 @@
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index c30bd25..fd538da 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEXT_BASE=0x80110000
 CONFIG_SYS_MALLOC_LEN=0x2500000
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2"
@@ -49,7 +50,6 @@
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
 CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_TEGRA114_SPI=y
diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig
index 7b54d07..56e0958 100644
--- a/configs/verdin-imx8mm_defconfig
+++ b/configs/verdin-imx8mm_defconfig
@@ -12,6 +12,7 @@
 CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_VERDIN_IMX8MM=y
 CONFIG_SYS_PROMPT="Verdin iMX8MM # "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -142,4 +143,3 @@
 CONFIG_USB_HOST_ETHER=y
 CONFIG_IMX_WATCHDOG=y
 CONFIG_HEXDUMP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig
index 4efe6f9..f0856ac 100644
--- a/configs/verdin-imx8mp_defconfig
+++ b/configs/verdin-imx8mp_defconfig
@@ -16,10 +16,12 @@
 CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_VERDIN_IMX8MP=y
 CONFIG_SYS_PROMPT="Verdin iMX8MP # "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x960000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
 CONFIG_SPL=y
 CONFIG_IMX_BOOTAUX=y
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
@@ -50,7 +52,6 @@
 CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
 CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
@@ -168,4 +169,3 @@
 CONFIG_USB_HOST_ETHER=y
 CONFIG_IMX_WATCHDOG=y
 CONFIG_HEXDUMP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig
index 376d2be..10d55c5 100644
--- a/configs/vexpress_aemv8a_juno_defconfig
+++ b/configs/vexpress_aemv8a_juno_defconfig
@@ -8,6 +8,7 @@
 CONFIG_SYS_PROMPT="VExpress64# "
 CONFIG_IDENT_STRING=" vexpress_aemv8a"
 CONFIG_TARGET_VEXPRESS64_JUNO=y
+CONFIG_PCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0xff000000
 CONFIG_REMAKE_ELF=y
@@ -35,5 +36,4 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_SECT=259
-CONFIG_PCI=y
 CONFIG_USB=y
diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig
index 4b22d49..b642f10 100644
--- a/configs/vexpress_aemv8a_semi_defconfig
+++ b/configs/vexpress_aemv8a_semi_defconfig
@@ -32,4 +32,3 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_SECT=256
-CONFIG_VIRTIO_MMIO=y
diff --git a/configs/vexpress_aemv8r_defconfig b/configs/vexpress_aemv8r_defconfig
index 495eb1d..4055d29 100644
--- a/configs/vexpress_aemv8r_defconfig
+++ b/configs/vexpress_aemv8r_defconfig
@@ -15,4 +15,3 @@
 CONFIG_SYS_CBSIZE=512
 CONFIG_SYS_PBSIZE=541
 # CONFIG_MMC is not set
-CONFIG_VIRTIO_MMIO=y
diff --git a/configs/vexpress_fvp_defconfig b/configs/vexpress_fvp_defconfig
new file mode 100644
index 0000000..7362c1f
--- /dev/null
+++ b/configs/vexpress_fvp_defconfig
@@ -0,0 +1,5 @@
+CONFIG_ARM=y
+CONFIG_ARCH_VEXPRESS64=y
+CONFIG_DEFAULT_DEVICE_TREE="arm_fvp"
+CONFIG_IDENT_STRING=" arm_fvp"
+# CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig
index 03c0a02..8a99bca 100644
--- a/configs/vinco_defconfig
+++ b/configs/vinco_defconfig
@@ -8,6 +8,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000f00
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x10000
 CONFIG_ENV_SECT_SIZE=0x1000
@@ -45,7 +46,6 @@
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_SMSC=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index 7f84209..85d8633 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -23,6 +23,7 @@
 CONFIG_ENV_OFFSET_REDUND=0x90000
 CONFIG_SPL_LIBDISK_SUPPORT=y
 # CONFIG_CMD_BMODE is not set
+CONFIG_PCI=y
 CONFIG_SYS_MONITOR_LEN=409600
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -83,7 +84,6 @@
 CONFIG_PHY_SMSC=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
-CONFIG_PCI=y
 CONFIG_PCI_SCAN_SHOW=y
 CONFIG_PCIE_IMX=y
 CONFIG_PINCTRL=y
diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
index dc173fb..c7f2b82 100644
--- a/configs/vyasa-rk3288_defconfig
+++ b/configs/vyasa-rk3288_defconfig
@@ -9,6 +9,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-vyasa"
 CONFIG_DM_RESET=y
@@ -70,7 +71,6 @@
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MTD=y
-CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PINCTRL=y
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 6a1bf8d..e0ea5fe 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -70,7 +70,6 @@
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_PMIC=y
-CONFIG_SPL_DM_PMIC=y
 CONFIG_DM_PMIC_PFUZE100=y
 CONFIG_DM_SCSI=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig
index d1c0499..bb699cf 100644
--- a/configs/warp7_bl33_defconfig
+++ b/configs/warp7_bl33_defconfig
@@ -6,6 +6,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx7s-warp"
 CONFIG_TARGET_WARP7=y
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
 CONFIG_IMX_HAB=y
 CONFIG_SYS_MEMTEST_START=0x80000000
@@ -74,4 +75,3 @@
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/wetek-core2_defconfig b/configs/wetek-core2_defconfig
index 07d2587..324062e 100644
--- a/configs/wetek-core2_defconfig
+++ b/configs/wetek-core2_defconfig
@@ -7,6 +7,7 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-wetek-core2"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_GXM=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
@@ -69,4 +70,3 @@
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_MESON=y
 CONFIG_VIDEO_DT_SIMPLEFB=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/wetek-hub_defconfig b/configs/wetek-hub_defconfig
index 634833f..4091a19 100644
--- a/configs/wetek-hub_defconfig
+++ b/configs/wetek-hub_defconfig
@@ -1,17 +1,19 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_TEXT_BASE=0x01000000
-CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-wetek-hub"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" wetek-hub"
-CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-wetek-hub"
+CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_DEBUG_UART=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_MISC_INIT_R=y
@@ -31,10 +33,8 @@
 CONFIG_SARADC_MESON=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MESON=y
-CONFIG_DM_MMC=y
 CONFIG_MMC_MESON_GX=y
 CONFIG_PHY_REALTEK=y
-CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE_MESON8B=y
 CONFIG_PHY=y
 CONFIG_MESON_GXBB_USB_PHY=y
@@ -45,14 +45,12 @@
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_MESON_SERIAL=y
 CONFIG_SYSINFO=y
 CONFIG_SYSINFO_SMBIOS=y
 CONFIG_USB=y
-CONFIG_DM_USB=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_VIDEO=y
@@ -67,4 +65,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/wetek-play2_defconfig b/configs/wetek-play2_defconfig
index 6d33b09..3ef4390 100644
--- a/configs/wetek-play2_defconfig
+++ b/configs/wetek-play2_defconfig
@@ -1,17 +1,19 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_TEXT_BASE=0x01000000
-CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-wetek-play2"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" wetek-play2"
-CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-wetek-play2"
+CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_DEBUG_UART=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_MISC_INIT_R=y
@@ -31,10 +33,8 @@
 CONFIG_SARADC_MESON=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MESON=y
-CONFIG_DM_MMC=y
 CONFIG_MMC_MESON_GX=y
 CONFIG_PHY_REALTEK=y
-CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE_MESON8B=y
 CONFIG_PHY=y
 CONFIG_MESON_GXBB_USB_PHY=y
@@ -45,14 +45,12 @@
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_MESON_SERIAL=y
 CONFIG_SYSINFO=y
 CONFIG_SYSINFO_SMBIOS=y
 CONFIG_USB=y
-CONFIG_DM_USB=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_VIDEO=y
@@ -67,4 +65,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/x530_defconfig b/configs/x530_defconfig
index 68f8870..6e4f755 100644
--- a/configs/x530_defconfig
+++ b/configs/x530_defconfig
@@ -8,6 +8,7 @@
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
 CONFIG_TARGET_X530=y
+CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x40000
@@ -20,6 +21,7 @@
 CONFIG_DEBUG_UART_CLOCK=250000000
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_ENV_ADDR=0x100000
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -75,11 +77,9 @@
 CONFIG_NAND_PXA3XX=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
-CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1307=y
diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig
index aedb327..122c1a9 100644
--- a/configs/x96_mate_defconfig
+++ b/configs/x96_mate_defconfig
@@ -2,7 +2,6 @@
 CONFIG_ARCH_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h616-x96-mate"
 CONFIG_SPL=y
-CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION=y
 CONFIG_DRAM_SUN50I_H616_DX_ODT=0x03030303
 CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
 CONFIG_DRAM_SUN50I_H616_CA_DRI=0x1c12
diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig
index 348c6e3..27b59f8 100644
--- a/configs/xilinx_versal_mini_ospi_defconfig
+++ b/configs/xilinx_versal_mini_ospi_defconfig
@@ -8,6 +8,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE0000
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x80
 # CONFIG_DM_GPIO is not set
 CONFIG_DEFAULT_DEVICE_TREE="versal-mini-ospi-single"
@@ -54,7 +55,6 @@
 # CONFIG_DM_DEVICE_REMOVE is not set
 # CONFIG_MMC is not set
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_SOFT_RESET=y
 CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig
index bffc3b8..4b07934 100644
--- a/configs/xilinx_versal_mini_qspi_defconfig
+++ b/configs/xilinx_versal_mini_qspi_defconfig
@@ -7,6 +7,7 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE0000
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x80
 CONFIG_DEFAULT_DEVICE_TREE="versal-mini-qspi-single"
 CONFIG_SYS_PROMPT="Versal> "
@@ -59,7 +60,6 @@
 # CONFIG_INPUT is not set
 # CONFIG_MMC is not set
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 # CONFIG_SPI_FLASH_SMART_HWCAPS is not set
 # CONFIG_SPI_FLASH_UNLOCK_ALL is not set
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig
index aae01df..fb8f86c 100644
--- a/configs/xilinx_versal_net_virt_defconfig
+++ b/configs/xilinx_versal_net_virt_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SYS_MALLOC_F_LEN=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="xilinx-versal-net-virt"
 CONFIG_SYS_PROMPT="Versal NET> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_CMD_FRU=y
 CONFIG_SYS_LOAD_ADDR=0x8000000
@@ -133,4 +134,3 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_THOR=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index 018ec72..86cfbd6 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SYS_MALLOC_F_LEN=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="xilinx-versal-virt"
 CONFIG_SYS_PROMPT="Versal> "
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ENV_OFFSET_REDUND=0x7F00000
 CONFIG_CMD_FRU=y
@@ -137,4 +138,3 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_THOR=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index 94440ba..474abc7 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_L2CACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_TEXT_BASE=0x4000000
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_OFFSET=0xE00000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
@@ -117,7 +118,6 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_ZYNQ=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig
index fe78c5d..fc768b6 100644
--- a/configs/xilinx_zynqmp_mini_defconfig
+++ b/configs/xilinx_zynqmp_mini_defconfig
@@ -9,7 +9,6 @@
 CONFIG_ENV_SIZE=0x80
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini"
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
-# CONFIG_CMD_ZYNQMP is not set
 CONFIG_SYS_LOAD_ADDR=0x8000000
 CONFIG_SYS_MEMTEST_START=0x00000000
 CONFIG_SYS_MEMTEST_END=0x00001000
diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig
index 54b22ae..cf7c7ed 100644
--- a/configs/xilinx_zynqmp_mini_emmc0_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig
@@ -13,7 +13,6 @@
 CONFIG_SPL_STACK=0xfffffffc
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL=y
-# CONFIG_CMD_ZYNQMP is not set
 CONFIG_SYS_LOAD_ADDR=0x8000000
 CONFIG_REMAKE_ELF=y
 # CONFIG_MP is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig
index eb78e0a..a4a43b5 100644
--- a/configs/xilinx_zynqmp_mini_emmc1_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig
@@ -13,7 +13,6 @@
 CONFIG_SPL_STACK=0xfffffffc
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL=y
-# CONFIG_CMD_ZYNQMP is not set
 CONFIG_SYS_LOAD_ADDR=0x8000000
 CONFIG_REMAKE_ELF=y
 # CONFIG_MP is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig
index b099491..ce224f8 100644
--- a/configs/xilinx_zynqmp_mini_nand_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_defconfig
@@ -9,7 +9,6 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40000
 CONFIG_ENV_SIZE=0x80
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
-# CONFIG_CMD_ZYNQMP is not set
 CONFIG_SYS_LOAD_ADDR=0x8000000
 CONFIG_REMAKE_ELF=y
 # CONFIG_MP is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig
index b49633c..ce23cb1 100644
--- a/configs/xilinx_zynqmp_mini_nand_single_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig
@@ -9,7 +9,6 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40000
 CONFIG_ENV_SIZE=0x80
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
-# CONFIG_CMD_ZYNQMP is not set
 CONFIG_SYS_LOAD_ADDR=0x8000000
 CONFIG_REMAKE_ELF=y
 # CONFIG_MP is not set
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index a1dbef9..e6a9dd3 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -13,7 +13,6 @@
 CONFIG_SPL=y
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 CONFIG_ZYNQMP_NO_DDR=y
-# CONFIG_CMD_ZYNQMP is not set
 # CONFIG_PSCI_RESET is not set
 CONFIG_SYS_LOAD_ADDR=0x8000000
 # CONFIG_EXPERT is not set
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index fb6bf62..e1b241f 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK_R_ADDR=0x18000000
 CONFIG_SPL_STACK=0xfffffffc
@@ -232,7 +233,6 @@
 CONFIG_PANIC_HANG=y
 CONFIG_TPM=y
 CONFIG_SPL_GZIP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_SET_TIME=y
 CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
 CONFIG_EFI_CAPSULE_ON_DISK=y
diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig
index d3a350f..f5eeea4 100644
--- a/configs/xtfpga_defconfig
+++ b/configs/xtfpga_defconfig
@@ -9,7 +9,6 @@
 CONFIG_ENV_ADDR=0xF7FE0000
 CONFIG_XTFPGA_KC705=y
 CONFIG_SYS_MONITOR_LEN=262144
-CONFIG_STANDALONE_LOAD_ADDR=0x00800000
 CONFIG_SYS_MONITOR_BASE=0xF6000000
 CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_SHOW_BOOT_PROGRESS=y
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 658b4e9..08c5009 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -8,6 +8,7 @@
 CONFIG_ARCH_ZYNQ=y
 CONFIG_TEXT_BASE=0xFFFC0000
 CONFIG_SYS_MALLOC_LEN=0x1000
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_ENV_SIZE=0x190
 CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
 CONFIG_SPL_STACK_R_ADDR=0x200000
@@ -26,7 +27,6 @@
 # CONFIG_AUTOBOOT is not set
 CONFIG_USE_PREBOOT=y
 # CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_ARCH_EARLY_INIT_R is not set
 # CONFIG_BOARD_LATE_INIT is not set
 CONFIG_CLOCKS=y
 CONFIG_SPL_MAX_SIZE=0x30000
@@ -81,7 +81,6 @@
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_SPL_DM_SEQ_ALIAS=y
 # CONFIG_MMC is not set
-CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/doc/board/advantech/imx8qm-dmsse20-a1.rst b/doc/board/advantech/imx8qm-dmsse20-a1.rst
new file mode 100644
index 0000000..b83e678
--- /dev/null
+++ b/doc/board/advantech/imx8qm-dmsse20-a1.rst
@@ -0,0 +1,58 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+NXP i.MX8QM DMSSE20-a1 board
+============================
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get scfw_tcm.bin and ahab-container.img
+- Get imx-mkimage
+- Build U-Boot
+- Flash the binary into the SD card
+- Boot
+
+Get and Build the ARM Trusted Firmware
+--------------------------------------
+
+.. code-block:: bash
+
+     $ git clone https://github.com/nxp-imx/imx-atf
+     $ cd imx-atf/
+     $ git checkout lf-5.10.72-2.2.0 -b lf-5.10.72-2.2.0
+     $ make PLAT=imx8qm bl31
+     $ cp build/imx8qm/release/bl31.bin $(builddir)
+
+Get scfw_tcm.bin and ahab-container.img
+---------------------------------------
+
+.. code-block:: bash
+
+     $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.11.0.bin
+     $ chmod +x imx-sc-firmware-1.11.0.bin
+     $ ./imx-sc-firmware-1.11.0.bin
+     $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.8.5.bin
+     $ chmod +x imx-seco-3.8.5.bin
+     $ ./imx-seco-3.8.5.bin
+
+Or use this to avoid running random scripts from the internet,
+but note that you must agree to the license the script displays:
+
+.. code-block:: bash
+
+     $ dd if=imx-sc-firmware-1.11.0.bin of=imx-sc-firmware-1.11.0.tar.bz2 bs=42757 skip=1
+     $ tar -xf imx-sc-firmware-1.11.0.tar.bz2
+     $ cp imx-sc-firmware-1.11.0/mx8qm-val-scfw-tcm.bin $(builddir)
+     $ dd if=imx-seco-3.8.5.bin of=imx-seco-3.8.5.tar.bz2 bs=43978 skip=1
+     $ tar -xf imx-seco-3.8.5.tar.bz2
+     $ cp imx-seco-3.8.5/firmware/seco/mx8qmb0-ahab-container.img $(builddir)
+
+Build U-Boot
+------------
+.. code-block:: bash
+
+     $ export ATF_LOAD_ADDR=0x80000000
+     $ export BL33_LOAD_ADDR=0x80020000
+     $ make imx8qm_dmsse20a1_defconfig
+     $ make
diff --git a/doc/board/advantech/index.rst b/doc/board/advantech/index.rst
index e9b198c..125b98c 100644
--- a/doc/board/advantech/index.rst
+++ b/doc/board/advantech/index.rst
@@ -7,3 +7,4 @@
    :maxdepth: 2
 
    imx8qm-rom7720-a1.rst
+   imx8qm-dmsse20-a1.rst
diff --git a/doc/board/broadcom/index.rst b/doc/board/broadcom/index.rst
index a56bd1f..ca34afc 100644
--- a/doc/board/broadcom/index.rst
+++ b/doc/board/broadcom/index.rst
@@ -9,3 +9,4 @@
 
    bcm7xxx
    raspberrypi
+   northstar
diff --git a/doc/board/broadcom/northstar.rst b/doc/board/broadcom/northstar.rst
new file mode 100644
index 0000000..f4bc0ac
--- /dev/null
+++ b/doc/board/broadcom/northstar.rst
@@ -0,0 +1,44 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2023 Linus Walleij <linus.walleij@linaro.org>
+
+Broadcom Northstar Boards
+=========================
+
+This document describes how to use U-Boot on the Broadcom Northstar
+boards, comprised of the Cortex A9 ARM-based BCM470x and BCM5301x SoCs. These
+were introduced in 2012-2013 and some of them are also called StrataGX.
+
+Northstar is part of the iProc SoC family.
+
+A good overview of these boards can be found in Jon Mason's presentation
+"Enabling New Hardware in U-Boot" where the difference between Northstar
+and Northstar Plus and Northstar 2 (Aarch64) is addressed.
+
+The ROM in the Northstar SoC will typically look into NOR flash memory
+for a boot loader, and the way this works is undocumented. It should be
+possible to execute U-Boot as the first binary from the NOR flash but
+this usage path is unexplored. Please add information if you know more.
+
+D-Link Boards
+-------------
+
+When we use U-Boot with D-Link routers, the NOR flash has a boot loader
+and web server that can re-flash the bigger NAND flash memory for object
+code in the SEAMA format, so on these platforms U-Boot is converted into
+a SEAMA binary and installed in the SoC using the flash tool resident in
+the NOR flash. Details can be found in the OpenWrt project codebase.
+
+Configure
+---------
+
+.. code-block:: console
+
+	$ make CROSS_COMPILE=${CROSS_COMPILE} bcmns_defconfig
+
+Build
+-----
+
+.. code-block:: console
+
+	$ make CROSS_COMPILE=${CROSS_COMPILE}
+	$ ${CROSS_COMPILE}strip u-boot
diff --git a/doc/board/qualcomm/qcs404.rst b/doc/board/qualcomm/qcs404.rst
index bbb40b0..0cb71d9 100644
--- a/doc/board/qualcomm/qcs404.rst
+++ b/doc/board/qualcomm/qcs404.rst
@@ -9,8 +9,8 @@
 This document describes the information about Qualcomm QCS404 evaluation board
 and it's usage steps.
 
-U-Boot can be used as a replacement for Qualcomm's original ABL (UEFI) bootloader.
-It is loaded as an Android boot image through ABL
+The current boot flow support loading u-boot as an Android boot image via
+Qualcomm's UEFI-based ABL (Android) Bootloader.
 
 Installation
 ------------
diff --git a/doc/board/qualcomm/sdm845.rst b/doc/board/qualcomm/sdm845.rst
index 8ef4749..71879c2 100644
--- a/doc/board/qualcomm/sdm845.rst
+++ b/doc/board/qualcomm/sdm845.rst
@@ -12,8 +12,8 @@
 SDM845 - hi-end qualcomm chip, introduced in late 2017.
 Mostly used in flagship phones and tablets of 2018.
 
-U-Boot can be used as a replacement for Qualcomm's original ABL (UEFI) bootloader.
-It is loaded as an Android boot image through ABL
+The current boot flow support loading u-boot as an Android boot image via
+Qualcomm's UEFI-based ABL (Android) Bootloader.
 
 Installation
 ------------
diff --git a/doc/board/sifive/unmatched.rst b/doc/board/sifive/unmatched.rst
index a994422..de2aab5 100644
--- a/doc/board/sifive/unmatched.rst
+++ b/doc/board/sifive/unmatched.rst
@@ -56,8 +56,10 @@
 ZSBL loads the U-Boot SPL (u-boot-spl.bin) from a partition with GUID type
 5B193300-FC78-40CD-8002-E86C45580B47
 
-U-Boot SPL expects u-boot.itb from a partition with GUID
-type 2E54B353-1271-4842-806F-E436D6AF6985
+With the default configuration U-Boot SPL expects u-boot.itb starting at sector
+2082 (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x822). It is recommended to use a
+partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985 for storing
+main U-Boot.
 
 u-boot.itb is a combination of fw_dynamic.bin, u-boot-nodtb.bin and
 device tree blob (hifive-unmatched-a00.dtb)
diff --git a/doc/board/starfive/visionfive2.rst b/doc/board/starfive/visionfive2.rst
index 22d2a31..4d43ac9 100644
--- a/doc/board/starfive/visionfive2.rst
+++ b/doc/board/starfive/visionfive2.rst
@@ -51,6 +51,8 @@
 	cd opensbi
 	make PLATFORM=generic FW_TEXT_START=0x40000000 FW_OPTIONS=0
 
+The VisionFive 2 support for OpenSBI was introduced after the v1.2 release.
+
 More detailed description of steps required to build FW_DYNAMIC firmware
 is beyond the scope of this document. Please refer OpenSBI documenation.
 (Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git)
@@ -79,14 +81,19 @@
 Flashing
 ~~~~~~~~
 
-SPL loads the U-Boot SPL (u-boot-spl.bin.normal.out) from a partition with GUID type
-2E54B353-1271-4842-806F-E436D6AF6985
+The device firmware loads U-Boot SPL (u-boot-spl.bin.normal.out) from the
+partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985. You are free
+to choose any partition number.
 
-U-Boot SPL expects a U-Boot FIT image (u-boot.itb) from a partition with GUID
-type BC13C2FF-59E6-4262-A352-B275FD6F7172
+With the default configuration U-Boot SPL loads the U-Boot FIT image
+(u-boot.itb) from partition 2 (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2).
+When formatting it is recommended to use GUID
+BC13C2FF-59E6-4262-A352-B275FD6F7172 for this partition.
 
-FIT image (u-boot.itb) is a combination of fw_dynamic.bin, u-boot-nodtb.bin and
-device tree blob (jh7110-starfive-visionfive-2-v1.3b.dtb/jh7110-starfive-visionfive-2-v1.2a.dtb)
+The FIT image (u-boot.itb) is a combination of OpenSBI's fw_dynamic.bin,
+u-boot-nodtb.bin and the device tree blob
+(jh7110-starfive-visionfive-2-v1.3b.dtb or
+jh7110-starfive-visionfive-2-v1.2a.dtb).
 
 Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch)
 
@@ -117,7 +124,9 @@
 Booting
 ~~~~~~~
 
-Change DIP switches MSEL[1:0] are set to 10, select the boot mode to SD.
+The board provides the DIP switches MSEL[1:0] to select the boot device.
+To select booting from SD-card set the DIP switches MSEL[1:0] to 10.
+
 Once you plugin the sdcard and power up, you should see the U-Boot prompt.
 
 Sample boot log from StarFive VisionFive2 board
diff --git a/doc/develop/driver-model/index.rst b/doc/develop/driver-model/index.rst
index 7366ef8..8e12bbd 100644
--- a/doc/develop/driver-model/index.rst
+++ b/doc/develop/driver-model/index.rst
@@ -20,6 +20,7 @@
    livetree
    migration
    nvme
+   nvmxip
    of-plat
    pci-info
    pmic-framework
diff --git a/doc/develop/driver-model/nvmxip.rst b/doc/develop/driver-model/nvmxip.rst
new file mode 100644
index 0000000..e85dc22
--- /dev/null
+++ b/doc/develop/driver-model/nvmxip.rst
@@ -0,0 +1,91 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+NVM XIP Block Storage Emulation Driver
+=======================================
+
+Summary
+-------
+
+Non-Volatile Memory devices with addressable memory (e.g: QSPI NOR flash) could
+be used for block storage needs (e.g: parsing a GPT layout in a raw QSPI NOR flash).
+
+The NVMXIP Uclass provides this functionality and can be used for any 64-bit platform.
+
+The NVMXIP Uclass provides the following drivers:
+
+      nvmxip-blk block driver:
+
+        A generic block driver allowing to read from the XIP flash.
+	The driver belongs to UCLASS_BLK.
+	The driver implemented by drivers/mtd/nvmxip/nvmxip.c
+
+      nvmxip Uclass driver:
+
+        When a device is described in the DT and associated with UCLASS_NVMXIP,
+        the Uclass creates a block device and binds it with the nvmxip-blk.
+	The Uclass driver implemented by drivers/mtd/nvmxip/nvmxip-uclass.c
+
+      nvmxip_qspi driver :
+
+        The driver probed with the DT and is the parent of the blk#<id> device.
+        nvmxip_qspi can be reused by other platforms. If the platform
+        has custom settings to apply before using the flash, then the platform
+        can provide its own parent driver belonging to UCLASS_NVMXIP and reuse
+        nvmxip-blk. The custom driver can be implemented like nvmxip_qspi in
+        addition to the platform custom settings.
+	The nvmxip_qspi driver belongs to UCLASS_NVMXIP.
+	The driver implemented by drivers/mtd/nvmxip/nvmxip_qspi.c
+
+	For example, if we have two NVMXIP devices described in the DT
+	The devices hierarchy is as follows:
+
+::
+
+   => dm tree
+
+        Class     Index  Probed  Driver                Name
+    -----------------------------------------------------------
+    ...
+     nvmxip        0  [ + ]   nvmxip_qspi           |-- nvmxip-qspi1@08000000
+     blk           3  [ + ]   nvmxip-blk                    |   `-- nvmxip-qspi1@08000000.blk#1
+     nvmxip        1  [ + ]   nvmxip_qspi           |-- nvmxip-qspi2@08200000
+     blk           4  [ + ]   nvmxip-blk                    |   `-- nvmxip-qspi2@08200000.blk#2
+
+The implementation is generic and can be used by different platforms.
+
+Supported hardware
+--------------------------------
+
+Any plaform supporting readq().
+
+Configuration
+----------------------
+
+config NVMXIP
+	  This option allows the emulation of a block storage device
+	  on top of a direct access non volatile memory XIP flash devices.
+	  This support provides the read operation.
+	  This option provides the block storage driver nvmxip-blk which
+	  handles the read operation. This driver is HW agnostic and can support
+	  multiple flash devices at the same time.
+
+config NVMXIP_QSPI
+	  This option allows the emulation of a block storage device on top of a QSPI XIP flash.
+	  Any platform that needs to emulate one or multiple QSPI XIP flash devices can turn this
+	  option on to enable the functionality. NVMXIP config is selected automatically.
+	  Platforms that need to add custom treatments before accessing to the flash, can
+	  write their own driver (same as nvmxip_qspi in addition to the custom settings).
+
+Device Tree nodes
+--------------------
+
+Multiple QSPI XIP flash devices can be used at the same time by describing them through DT
+nodes.
+
+Please refer to the documentation of the DT binding at:
+
+doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt
+
+Contributors
+------------
+   * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
diff --git a/doc/develop/event.rst b/doc/develop/event.rst
index 4ff5934..e60cbf6 100644
--- a/doc/develop/event.rst
+++ b/doc/develop/event.rst
@@ -12,7 +12,7 @@
 often easier to use an event.
 
 An event consists of a type (e.g. EVT_DM_POST_INIT) and some optional data,
-in `union event_data`. An event spy can be creasted to watch for events of a
+in `union event_data`. An event spy can be created to watch for events of a
 particular type. When the event is created, it is sent to each spy in turn.
 
 
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 7d63cf4..7e9c931 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -50,8 +50,7 @@
 
 * U-Boot v2023.04 was released on Mon 03 April 2023.
 
-* The Merge Window for the next release (v2023.07) is **open** until the -rc1
-  release on Mon 24 April 2023.
+* The Merge Window for the next release (v2023.07) is **closed**.
 
 * The next branch is now **closed**.
 
@@ -63,9 +62,9 @@
 .. The following commented out dates are for when release candidates are
    planned to be tagged.
 
-.. For the next scheduled release, release candidates were made on::
+For the next scheduled release, release candidates were made on::
 
-.. * U-Boot v2023.07-rc1 was released on Mon 24 April 2023.
+* U-Boot v2023.07-rc1 was released on Mon 01 May 2023.
 
 .. * U-Boot v2023.07-rc2 was released on Mon 08 May 2023.
 
diff --git a/doc/develop/trace.rst b/doc/develop/trace.rst
index 8425d84..9bbe134 100644
--- a/doc/develop/trace.rst
+++ b/doc/develop/trace.rst
@@ -100,7 +100,7 @@
 
 .. code-block:: console
 
-    $ ./sandbox/tools/proftool -m sandbox/System.map -t trace dump-ftrace >trace.dat
+    $ ./sandbox/tools/proftool -m sandbox/System.map -t trace dump-ftrace -o trace.dat
 
 Finally run kernelshark to display it (note it only works with `.dat` files!):
 
diff --git a/doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt b/doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt
new file mode 100644
index 0000000..882728d
--- /dev/null
+++ b/doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt
@@ -0,0 +1,56 @@
+Specifying NVMXIP information for devices
+======================================
+
+QSPI XIP flash device nodes
+---------------------------
+
+Each flash device should have its own node.
+
+Each node must specify the following fields:
+
+1)
+		compatible = "nvmxip,qspi";
+
+This allows to bind the flash device with the nvmxip_qspi driver
+If a platform has its own driver, please provide your own compatible
+string.
+
+2)
+		reg = /bits/ 64 <0x08000000 0x00200000>;
+
+The start address and size of the flash device. The values give here are an
+example (when the cell size is 2).
+
+When cell size is 1, the reg field looks like this:
+
+		reg = <0x08000000 0x00200000>;
+
+3)
+
+		lba_shift = <9>;
+
+The number of bit shifts used to calculate the size in bytes of one block.
+In this example the block size is 1 << 9 = 2 ^ 9 = 512 bytes
+
+4)
+
+		lba = <4096>;
+
+The number of blocks.
+
+Example of multiple flash devices
+----------------------------------------------------
+
+	nvmxip-qspi1@08000000 {
+		compatible = "nvmxip,qspi";
+		reg = /bits/ 64 <0x08000000 0x00200000>;
+		lba_shift = <9>;
+		lba = <4096>;
+	};
+
+	nvmxip-qspi2@08200000 {
+		compatible = "nvmxip,qspi";
+		reg = /bits/ 64 <0x08200000 0x00100000>;
+		lba_shift = <9>;
+		lba = <2048>;
+	};
diff --git a/doc/device-tree-bindings/serial/msm-geni-serial.txt b/doc/device-tree-bindings/serial/msm-geni-serial.txt
index 9eadc25..eaa39c9 100644
--- a/doc/device-tree-bindings/serial/msm-geni-serial.txt
+++ b/doc/device-tree-bindings/serial/msm-geni-serial.txt
@@ -1,6 +1,6 @@
 Qualcomm GENI UART
 
 Required properties:
-- compatible: must be "qcom,msm-geni-uart"
+- compatible: must be "qcom,geni-debug-uart"
 - reg: start address and size of the registers
 - clock: interface clock (must accept baudrate as a frequency)
diff --git a/doc/usage/cmd/cp.rst b/doc/usage/cmd/cp.rst
new file mode 100644
index 0000000..12a24e1
--- /dev/null
+++ b/doc/usage/cmd/cp.rst
@@ -0,0 +1,83 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+cp command
+==========
+
+Synopsis
+--------
+
+::
+
+    cp source target count
+    cp.b source target count
+    cp.w source target count
+    cp.l source target count
+    cp.q source target count
+
+Description
+-----------
+
+The cp command is used to copy *count* chunks of memory from the *source*
+address to the *target* address. If the *target* address points to NOR flash,
+the flash is programmed.
+
+The number bytes in one chunk is defined by the suffix defaulting to 4 bytes:
+
+====== ==========
+suffix chunk size
+====== ==========
+.b     1 byte
+.w     2 bytes
+.l     4 bytes
+.q     8 bytes
+<none> 4 bytes
+====== ==========
+
+source
+        source address, hexadecimal
+
+target
+        target address, hexadecimal
+
+count
+        number of words to be copied, hexadecimal
+
+Examples
+--------
+
+The example device has a NOR flash where the lower part of the flash is
+protected. We first copy to RAM, then to unprotected flash. Last we try to
+write to protectd flash.
+
+::
+
+    => mtd list
+    List of MTD devices:
+    * nor0
+      - device: flash@0
+      - parent: root_driver
+      - driver: cfi_flash
+      - path: /flash@0
+      - type: NOR flash
+      - block size: 0x20000 bytes
+      - min I/O: 0x1 bytes
+      - 0x000000000000-0x000002000000 : "nor0"
+    => cp.b 4020000 5000000 200000
+    => cp.b 4020000 1e00000 20000
+    Copy to Flash... done
+    => cp.b 4020000 0 20000
+    Copy to Flash... Can't write to protected Flash sectors
+    =>
+
+Configuration
+-------------
+
+The cp command is available if CONFIG_CMD_MEMORY=y. Support for 64 bit words
+(cp.q) depends on CONFIG_MEM_SUPPORT_64BIT_DATA=y. Copying to flash depends on
+CONFIG_MTD_NOR_FLASH=y.
+
+Return value
+------------
+
+The return value $? is set to 0 (true) if the command was successfully,
+1 (false) otherwise.
diff --git a/doc/usage/cmd/mmc.rst b/doc/usage/cmd/mmc.rst
index 55e3f9c..71a0303 100644
--- a/doc/usage/cmd/mmc.rst
+++ b/doc/usage/cmd/mmc.rst
@@ -213,10 +213,10 @@
 The raw data can be read/written via 'mmc read/write' command:
 ::
 
-    => mmc read 0x40000000 0x5000 0x100
+    => mmc read 40000000 5000 100
     MMC read: dev # 0, block # 20480, count 256 ... 256 blocks read: OK
 
-    => mmc write 0x40000000 0x5000 0x10
+    => mmc write 40000000 5000 100
     MMC write: dev # 0, block # 20480, count 256 ... 256 blocks written: OK
 
 The partition list can be shown via 'mmc part' command:
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index cdf7109..0fde130 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -41,6 +41,7 @@
    cmd/cmp
    cmd/coninfo
    cmd/conitrace
+   cmd/cp
    cmd/cyclic
    cmd/dm
    cmd/ebtupdate
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 9101e53..75937fb 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -36,6 +36,8 @@
 
 source "drivers/dma/Kconfig"
 
+source "drivers/extcon/Kconfig"
+
 source "drivers/fastboot/Kconfig"
 
 source "drivers/firmware/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 928a8b0..29be78a 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -9,6 +9,7 @@
 obj-$(CONFIG_$(SPL_TPL_)DMA) += dma/
 obj-$(CONFIG_$(SPL_TPL_)DMA_LEGACY) += dma/
 obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/
+obj-$(CONFIG_$(SPL_TPL_)EXTCON) += extcon/
 obj-$(CONFIG_$(SPL_TPL_)GPIO) += gpio/
 obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC) += misc/
 obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset/
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 6998b82..cb2c648 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1152,7 +1152,12 @@
 int ahci_probe_scsi_pci(struct udevice *ahci_dev)
 {
 	ulong base;
-	u16 vendor, device;
+	u16 vendor, device, cmd;
+
+	/* Enable bus mastering */
+	dm_pci_read_config16(ahci_dev, PCI_COMMAND, &cmd);
+	cmd |= PCI_COMMAND_MASTER;
+	dm_pci_write_config16(ahci_dev, PCI_COMMAND, cmd);
 
 	base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5, 0, 0,
 				     PCI_REGION_TYPE, PCI_REGION_MEM);
diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index cb73faa..614b975 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -28,6 +28,7 @@
 	{ UCLASS_AHCI, "sata" },
 	{ UCLASS_HOST, "host" },
 	{ UCLASS_NVME, "nvme" },
+	{ UCLASS_NVMXIP, "nvmxip" },
 	{ UCLASS_EFI_MEDIA, "efi" },
 	{ UCLASS_EFI_LOADER, "efiloader" },
 	{ UCLASS_VIRTIO, "virtio" },
diff --git a/drivers/block/host_dev.c b/drivers/block/host_dev.c
index 5885fc3..6442241 100644
--- a/drivers/block/host_dev.c
+++ b/drivers/block/host_dev.c
@@ -24,7 +24,8 @@
 	struct host_sb_plat *plat = dev_get_plat(dev);
 	struct blk_desc *desc;
 	struct udevice *blk;
-	int ret, fd, size;
+	int ret, fd;
+	off_t size;
 	char *fname;
 
 	if (!filename)
diff --git a/drivers/block/ide.c b/drivers/block/ide.c
index 1ad9b6c..89201dd 100644
--- a/drivers/block/ide.c
+++ b/drivers/block/ide.c
@@ -36,9 +36,8 @@
 #endif
 };
 
-static int ide_bus_ok[CONFIG_SYS_IDE_MAXBUS];
-
-struct blk_desc ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
+#define ATA_CURR_BASE(dev)	(CONFIG_SYS_ATA_BASE_ADDR + \
+		ide_bus_offset[IDE_BUS(dev)])
 
 #define IDE_TIME_OUT	2000	/* 2 sec timeout */
 
@@ -46,35 +45,57 @@
 
 #define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
 
-#ifdef CONFIG_IDE_RESET
-extern void ide_set_reset(int idereset);
-
 static void ide_reset(void)
 {
-	int i;
+	if (IS_ENABLED(CONFIG_IDE_RESET)) {
+		/* assert reset */
+		ide_set_reset(1);
 
-	for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; ++i)
-		ide_bus_ok[i] = 0;
-	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i)
-		ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
+		/* the reset signal shall be asserted for et least 25 us */
+		udelay(25);
 
-	ide_set_reset(1);	/* assert reset */
+		schedule();
 
-	/* the reset signal shall be asserted for et least 25 us */
-	udelay(25);
+		/* de-assert RESET signal */
+		ide_set_reset(0);
 
-	schedule();
+		mdelay(250);
+	}
+}
 
-	/* de-assert RESET signal */
-	ide_set_reset(0);
+static void ide_outb(int dev, int port, u8 val)
+{
+	log_debug("(dev= %d, port= %#x, val= 0x%02x) : @ 0x%08lx\n",
+		  dev, port, val, ATA_CURR_BASE(dev) + port);
 
-	/* wait 250 ms */
-	for (i = 0; i < 250; ++i)
-		udelay(1000);
+	outb(val, ATA_CURR_BASE(dev) + port);
 }
-#else
-#define ide_reset()	/* dummy */
-#endif /* CONFIG_IDE_RESET */
+
+static u8 ide_inb(int dev, int port)
+{
+	uchar val;
+
+	val = inb(ATA_CURR_BASE(dev) + port);
+
+	log_debug("(dev= %d, port= %#x) : @ 0x%08lx -> 0x%02x\n",
+		  dev, port, ATA_CURR_BASE(dev) + port, val);
+	return val;
+}
+
+static void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+	uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	ushort *dbuf = (ushort *)sect_buf;
+
+	log_debug("in input swap data base for read is %p\n", (void *)paddr);
+
+	while (words--) {
+		EIEIO;
+		*dbuf++ = be16_to_cpu(inw(paddr));
+		EIEIO;
+		*dbuf++ = be16_to_cpu(inw(paddr));
+	}
+}
 
 /*
  * Wait until Busy bit is off, or timeout (in ms)
@@ -87,7 +108,7 @@
 
 	while ((c = ide_inb(dev, ATA_STATUS)) & ATA_STAT_BUSY) {
 		udelay(100);
-		if (delay-- == 0)
+		if (!delay--)
 			break;
 	}
 	return c;
@@ -98,10 +119,9 @@
  * terminate the string
  * "len" is the size of available memory including the terminating '\0'
  */
-static void ident_cpy(unsigned char *dst, unsigned char *src,
-		      unsigned int len)
+static void ident_cpy(u8 *dst, u8 *src, uint len)
 {
-	unsigned char *end, *last;
+	u8 *end, *last;
 
 	last = dst;
 	end = src + len - 1;
@@ -124,21 +144,20 @@
 	*last = '\0';
 }
 
-#ifdef CONFIG_ATAPI
 /****************************************************************************
  * ATAPI Support
  */
 
 /* since ATAPI may use commands with not 4 bytes alligned length
  * we have our own transfer functions, 2 bytes alligned */
-__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+static void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
 {
-	uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	uintptr_t paddr = ATA_CURR_BASE(dev) + ATA_DATA_REG;
 	ushort *dbuf;
 
 	dbuf = (ushort *)sect_buf;
 
-	debug("in output data shorts base for read is %p\n", (void *)paddr);
+	log_debug("in output data shorts base for read is %p\n", (void *)paddr);
 
 	while (shorts--) {
 		EIEIO;
@@ -146,14 +165,14 @@
 	}
 }
 
-__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+static void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
 {
-	uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	uintptr_t paddr = ATA_CURR_BASE(dev) + ATA_DATA_REG;
 	ushort *dbuf;
 
 	dbuf = (ushort *)sect_buf;
 
-	debug("in input data shorts base for read is %p\n", (void *)paddr);
+	log_debug("in input data shorts base for read is %p\n", (void *)paddr);
 
 	while (shorts--) {
 		EIEIO;
@@ -175,12 +194,12 @@
 	/* prevents to read the status before valid */
 	c = ide_inb(dev, ATA_DEV_CTL);
 
-	while (((c = ide_inb(dev, ATA_STATUS)) & mask) != res) {
+	while (c = ide_inb(dev, ATA_STATUS) & mask, c != res) {
 		/* break if error occurs (doesn't make sense to wait more) */
 		if ((c & ATA_STAT_ERR) == ATA_STAT_ERR)
 			break;
 		udelay(100);
-		if (delay-- == 0)
+		if (!delay--)
 			break;
 	}
 	return c;
@@ -189,10 +208,9 @@
 /*
  * issue an atapi command
  */
-unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
-			  unsigned char *buffer, int buflen)
+static u8 atapi_issue(int device, u8 *ccb, int ccblen, u8 *buffer, int buflen)
 {
-	unsigned char c, err, mask, res;
+	u8 c, err, mask, res;
 	int n;
 
 	/* Select device
@@ -202,18 +220,17 @@
 	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
 	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
 	if ((c & mask) != res) {
-		printf("ATAPI_ISSUE: device %d not ready status %X\n", device,
+		printf("ATAPI_ISSUE: device %d not ready status %x\n", device,
 		       c);
-		err = 0xFF;
+		err = 0xff;
 		goto AI_OUT;
 	}
 	/* write taskfile */
 	ide_outb(device, ATA_ERROR_REG, 0);	/* no DMA, no overlaped */
 	ide_outb(device, ATA_SECT_CNT, 0);
 	ide_outb(device, ATA_SECT_NUM, 0);
-	ide_outb(device, ATA_CYL_LOW, (unsigned char) (buflen & 0xFF));
-	ide_outb(device, ATA_CYL_HIGH,
-		 (unsigned char) ((buflen >> 8) & 0xFF));
+	ide_outb(device, ATA_CYL_LOW, (u8)(buflen & 0xff));
+	ide_outb(device, ATA_CYL_HIGH, (u8)((buflen >> 8) & 0xff));
 	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
 
 	ide_outb(device, ATA_COMMAND, ATA_CMD_PACKET);
@@ -224,17 +241,17 @@
 	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
 
 	if ((c & mask) != res) {	/* DRQ must be 1, BSY 0 */
-		printf("ATAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",
+		printf("ATAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status %#02x\n",
 		       device, c);
-		err = 0xFF;
+		err = 0xff;
 		goto AI_OUT;
 	}
 
 	/* write command block */
-	ide_output_data_shorts(device, (unsigned short *)ccb, ccblen / 2);
+	ide_output_data_shorts(device, (ushort *)ccb, ccblen / 2);
 
 	/* ATAPI Command written wait for completition */
-	udelay(5000);		/* device must set bsy */
+	mdelay(5);		/* device must set bsy */
 
 	mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
 	/*
@@ -248,12 +265,12 @@
 	if ((c & mask) != res) {
 		if (c & ATA_STAT_ERR) {
 			err = (ide_inb(device, ATA_ERROR_REG)) >> 4;
-			debug("atapi_issue 1 returned sense key %X status %02X\n",
-			      err, c);
+			log_debug("1 returned sense key %x status %02x\n",
+				  err, c);
 		} else {
-			printf("ATAPI_ISSUE: (no DRQ) after sending ccb (%x)  status 0x%02x\n",
+			printf("ATAPI_ISSUE: (no DRQ) after sending ccb (%x)  status %#02x\n",
 			       ccb[0], c);
-			err = 0xFF;
+			err = 0xff;
 		}
 		goto AI_OUT;
 	}
@@ -266,38 +283,36 @@
 		err = 0xff;
 		goto AI_OUT;
 	}
-	if ((n == 0) && (buflen < 0)) {
+	if (!n && buflen < 0) {
 		printf("ERROR, transfer bytes %d requested %d\n", n, buflen);
 		err = 0xff;
 		goto AI_OUT;
 	}
 	if (n != buflen) {
-		debug("WARNING, transfer bytes %d not equal with requested %d\n",
-		      n, buflen);
+		log_debug("WARNING, transfer bytes %d not equal with requested %d\n",
+			  n, buflen);
 	}
-	if (n != 0) {		/* data transfer */
-		debug("ATAPI_ISSUE: %d Bytes to transfer\n", n);
+	if (n) {		/* data transfer */
+		log_debug("ATAPI_ISSUE: %d Bytes to transfer\n", n);
 		/* we transfer shorts */
 		n >>= 1;
 		/* ok now decide if it is an in or output */
-		if ((ide_inb(device, ATA_SECT_CNT) & 0x02) == 0) {
-			debug("Write to device\n");
-			ide_output_data_shorts(device, (unsigned short *)buffer,
-					       n);
+		if (!(ide_inb(device, ATA_SECT_CNT) & 0x02)) {
+			log_debug("Write to device\n");
+			ide_output_data_shorts(device, (ushort *)buffer, n);
 		} else {
-			debug("Read from device @ %p shorts %d\n", buffer, n);
-			ide_input_data_shorts(device, (unsigned short *)buffer,
-					      n);
+			log_debug("Read from device @ %p shorts %d\n", buffer,
+				  n);
+			ide_input_data_shorts(device, (ushort *)buffer, n);
 		}
 	}
-	udelay(5000);		/* seems that some CD ROMs need this... */
+	mdelay(5);		/* seems that some CD ROMs need this... */
 	mask = ATA_STAT_BUSY | ATA_STAT_ERR;
 	res = 0;
 	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
 	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
 		err = (ide_inb(device, ATA_ERROR_REG) >> 4);
-		debug("atapi_issue 2 returned sense key %X status %X\n", err,
-		      c);
+		log_debug("2 returned sense key %x status %x\n", err, c);
 	} else {
 		err = 0;
 	}
@@ -313,13 +328,11 @@
 #define ATAPI_DRIVE_NOT_READY	100
 #define ATAPI_UNIT_ATTN		10
 
-unsigned char atapi_issue_autoreq(int device,
-				  unsigned char *ccb,
-				  int ccblen,
-				  unsigned char *buffer, int buflen)
+static u8 atapi_issue_autoreq(int device, u8 *ccb, int ccblen, u8 *buffer,
+			      int buflen)
 {
-	unsigned char sense_data[18], sense_ccb[12];
-	unsigned char res, key, asc, ascq;
+	u8 sense_data[18], sense_ccb[12];
+	u8 res, key, asc, ascq;
 	int notready, unitattn;
 
 	unitattn = ATAPI_UNIT_ATTN;
@@ -327,13 +340,13 @@
 
 retry:
 	res = atapi_issue(device, ccb, ccblen, buffer, buflen);
-	if (res == 0)
+	if (!res)
 		return 0;	/* Ok */
 
-	if (res == 0xFF)
-		return 0xFF;	/* error */
+	if (res == 0xff)
+		return 0xff;	/* error */
 
-	debug("(auto_req)atapi_issue returned sense key %X\n", res);
+	log_debug("(auto_req)atapi_issue returned sense key %x\n", res);
 
 	memset(sense_ccb, 0, sizeof(sense_ccb));
 	memset(sense_data, 0, sizeof(sense_data));
@@ -341,29 +354,29 @@
 	sense_ccb[4] = 18;	/* allocation Length */
 
 	res = atapi_issue(device, sense_ccb, 12, sense_data, 18);
-	key = (sense_data[2] & 0xF);
+	key = (sense_data[2] & 0xf);
 	asc = (sense_data[12]);
 	ascq = (sense_data[13]);
 
-	debug("ATAPI_CMD_REQ_SENSE returned %x\n", res);
-	debug(" Sense page: %02X key %02X ASC %02X ASCQ %02X\n",
-	      sense_data[0], key, asc, ascq);
+	log_debug("ATAPI_CMD_REQ_SENSE returned %x\n", res);
+	log_debug(" Sense page: %02X key %02X ASC %02X ASCQ %02X\n",
+		  sense_data[0], key, asc, ascq);
 
-	if ((key == 0))
+	if (!key)
 		return 0;	/* ok device ready */
 
-	if ((key == 6) || (asc == 0x29) || (asc == 0x28)) { /* Unit Attention */
+	if (key == 6 || asc == 0x29 || asc == 0x28) { /* Unit Attention */
 		if (unitattn-- > 0) {
-			udelay(200 * 1000);
+			mdelay(200);
 			goto retry;
 		}
 		printf("Unit Attention, tried %d\n", ATAPI_UNIT_ATTN);
 		goto error;
 	}
-	if ((asc == 0x4) && (ascq == 0x1)) {
+	if (asc == 0x4 && ascq == 0x1) {
 		/* not ready, but will be ready soon */
 		if (notready-- > 0) {
-			udelay(200 * 1000);
+			mdelay(200);
 			goto retry;
 		}
 		printf("Drive not ready, tried %d times\n",
@@ -371,15 +384,15 @@
 		goto error;
 	}
 	if (asc == 0x3a) {
-		debug("Media not present\n");
+		log_debug("Media not present\n");
 		goto error;
 	}
 
 	printf("ERROR: Unknown Sense key %02X ASC %02X ASCQ %02X\n", key, asc,
 	       ascq);
 error:
-	debug("ERROR Sense key %02X ASC %02X ASCQ %02X\n", key, asc, ascq);
-	return 0xFF;
+	log_debug("ERROR Sense key %02X ASC %02X ASCQ %02X\n", key, asc, ascq);
+	return 0xff;
 }
 
 /*
@@ -391,16 +404,17 @@
 #define ATAPI_READ_BLOCK_SIZE	2048	/* assuming CD part */
 #define ATAPI_READ_MAX_BLOCK	(ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
 
-ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
-		 void *buffer)
+static ulong atapi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+			void *buffer)
 {
-	int device = block_dev->devnum;
+	struct blk_desc *desc = dev_get_uclass_plat(dev);
+	int device = desc->devnum;
 	ulong n = 0;
-	unsigned char ccb[12];	/* Command descriptor block */
+	u8 ccb[12];	/* Command descriptor block */
 	ulong cnt;
 
-	debug("atapi_read dev %d start " LBAF " blocks " LBAF
-	      " buffer at %lX\n", device, blknr, blkcnt, (ulong) buffer);
+	log_debug("%d start " LBAF " blocks " LBAF " buffer at %lx\n", device,
+		  blknr, blkcnt, (ulong)buffer);
 
 	do {
 		if (blkcnt > ATAPI_READ_MAX_BLOCK)
@@ -410,143 +424,141 @@
 
 		ccb[0] = ATAPI_CMD_READ_12;
 		ccb[1] = 0;	/* reserved */
-		ccb[2] = (unsigned char) (blknr >> 24) & 0xFF;	/* MSB Block */
-		ccb[3] = (unsigned char) (blknr >> 16) & 0xFF;	/*  */
-		ccb[4] = (unsigned char) (blknr >> 8) & 0xFF;
-		ccb[5] = (unsigned char) blknr & 0xFF;	/* LSB Block */
-		ccb[6] = (unsigned char) (cnt >> 24) & 0xFF; /* MSB Block cnt */
-		ccb[7] = (unsigned char) (cnt >> 16) & 0xFF;
-		ccb[8] = (unsigned char) (cnt >> 8) & 0xFF;
-		ccb[9] = (unsigned char) cnt & 0xFF;	/* LSB Block */
+		ccb[2] = (u8)(blknr >> 24) & 0xff;	/* MSB Block */
+		ccb[3] = (u8)(blknr >> 16) & 0xff;	/*  */
+		ccb[4] = (u8)(blknr >> 8) & 0xff;
+		ccb[5] = (u8)blknr & 0xff;	/* LSB Block */
+		ccb[6] = (u8)(cnt >> 24) & 0xff; /* MSB Block cnt */
+		ccb[7] = (u8)(cnt >> 16) & 0xff;
+		ccb[8] = (u8)(cnt >> 8) & 0xff;
+		ccb[9] = (u8)cnt & 0xff;	/* LSB Block */
 		ccb[10] = 0;	/* reserved */
 		ccb[11] = 0;	/* reserved */
 
 		if (atapi_issue_autoreq(device, ccb, 12,
-					(unsigned char *)buffer,
-					cnt * ATAPI_READ_BLOCK_SIZE)
-		    == 0xFF) {
+					(u8 *)buffer,
+					cnt * ATAPI_READ_BLOCK_SIZE) == 0xff)
 			return n;
-		}
 		n += cnt;
 		blkcnt -= cnt;
 		blknr += cnt;
-		buffer += (cnt * ATAPI_READ_BLOCK_SIZE);
+		buffer += cnt * ATAPI_READ_BLOCK_SIZE;
 	} while (blkcnt > 0);
 	return n;
 }
 
-static void atapi_inquiry(struct blk_desc *dev_desc)
+static void atapi_inquiry(struct blk_desc *desc)
 {
-	unsigned char ccb[12];	/* Command descriptor block */
-	unsigned char iobuf[64];	/* temp buf */
-	unsigned char c;
+	u8 ccb[12];	/* Command descriptor block */
+	u8 iobuf[64];	/* temp buf */
+	u8 c;
 	int device;
 
-	device = dev_desc->devnum;
-	dev_desc->type = DEV_TYPE_UNKNOWN;	/* not yet valid */
+	device = desc->devnum;
+	desc->type = DEV_TYPE_UNKNOWN;	/* not yet valid */
 
 	memset(ccb, 0, sizeof(ccb));
 	memset(iobuf, 0, sizeof(iobuf));
 
 	ccb[0] = ATAPI_CMD_INQUIRY;
 	ccb[4] = 40;		/* allocation Legnth */
-	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 40);
+	c = atapi_issue_autoreq(device, ccb, 12, (u8 *)iobuf, 40);
 
-	debug("ATAPI_CMD_INQUIRY returned %x\n", c);
-	if (c != 0)
+	log_debug("ATAPI_CMD_INQUIRY returned %x\n", c);
+	if (c)
 		return;
 
 	/* copy device ident strings */
-	ident_cpy((unsigned char *)dev_desc->vendor, &iobuf[8], 8);
-	ident_cpy((unsigned char *)dev_desc->product, &iobuf[16], 16);
-	ident_cpy((unsigned char *)dev_desc->revision, &iobuf[32], 5);
+	ident_cpy((u8 *)desc->vendor, &iobuf[8], 8);
+	ident_cpy((u8 *)desc->product, &iobuf[16], 16);
+	ident_cpy((u8 *)desc->revision, &iobuf[32], 5);
 
-	dev_desc->lun = 0;
-	dev_desc->lba = 0;
-	dev_desc->blksz = 0;
-	dev_desc->log2blksz = LOG2_INVALID(typeof(dev_desc->log2blksz));
-	dev_desc->type = iobuf[0] & 0x1f;
+	desc->lun = 0;
+	desc->lba = 0;
+	desc->blksz = 0;
+	desc->log2blksz = LOG2_INVALID(typeof(desc->log2blksz));
+	desc->type = iobuf[0] & 0x1f;
 
-	if ((iobuf[1] & 0x80) == 0x80)
-		dev_desc->removable = 1;
+	if (iobuf[1] & 0x80)
+		desc->removable = 1;
 	else
-		dev_desc->removable = 0;
+		desc->removable = 0;
 
 	memset(ccb, 0, sizeof(ccb));
 	memset(iobuf, 0, sizeof(iobuf));
 	ccb[0] = ATAPI_CMD_START_STOP;
 	ccb[4] = 0x03;		/* start */
 
-	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
+	c = atapi_issue_autoreq(device, ccb, 12, (u8 *)iobuf, 0);
 
-	debug("ATAPI_CMD_START_STOP returned %x\n", c);
-	if (c != 0)
+	log_debug("ATAPI_CMD_START_STOP returned %x\n", c);
+	if (c)
 		return;
 
 	memset(ccb, 0, sizeof(ccb));
 	memset(iobuf, 0, sizeof(iobuf));
-	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
+	c = atapi_issue_autoreq(device, ccb, 12, (u8 *)iobuf, 0);
 
-	debug("ATAPI_CMD_UNIT_TEST_READY returned %x\n", c);
-	if (c != 0)
+	log_debug("ATAPI_CMD_UNIT_TEST_READY returned %x\n", c);
+	if (c)
 		return;
 
 	memset(ccb, 0, sizeof(ccb));
 	memset(iobuf, 0, sizeof(iobuf));
 	ccb[0] = ATAPI_CMD_READ_CAP;
-	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 8);
-	debug("ATAPI_CMD_READ_CAP returned %x\n", c);
-	if (c != 0)
+	c = atapi_issue_autoreq(device, ccb, 12, (u8 *)iobuf, 8);
+	log_debug("ATAPI_CMD_READ_CAP returned %x\n", c);
+	if (c)
 		return;
 
-	debug("Read Cap: LBA %02X%02X%02X%02X blksize %02X%02X%02X%02X\n",
-	      iobuf[0], iobuf[1], iobuf[2], iobuf[3],
-	      iobuf[4], iobuf[5], iobuf[6], iobuf[7]);
+	log_debug("Read Cap: LBA %02X%02X%02X%02X blksize %02X%02X%02X%02X\n",
+		  iobuf[0], iobuf[1], iobuf[2], iobuf[3],
+		  iobuf[4], iobuf[5], iobuf[6], iobuf[7]);
 
-	dev_desc->lba = ((unsigned long) iobuf[0] << 24) +
-		((unsigned long) iobuf[1] << 16) +
-		((unsigned long) iobuf[2] << 8) + ((unsigned long) iobuf[3]);
-	dev_desc->blksz = ((unsigned long) iobuf[4] << 24) +
-		((unsigned long) iobuf[5] << 16) +
-		((unsigned long) iobuf[6] << 8) + ((unsigned long) iobuf[7]);
-	dev_desc->log2blksz = LOG2(dev_desc->blksz);
-#ifdef CONFIG_LBA48
+	desc->lba = (ulong)iobuf[0] << 24 | (ulong)iobuf[1] << 16 |
+		(ulong)iobuf[2] << 8 | (ulong)iobuf[3];
+	desc->blksz = (ulong)iobuf[4] << 24 | (ulong)iobuf[5] << 16 |
+		(ulong)iobuf[6] << 8 | (ulong)iobuf[7];
+	desc->log2blksz = LOG2(desc->blksz);
+
 	/* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */
-	dev_desc->lba48 = 0;
-#endif
-	return;
+	desc->lba48 = false;
 }
 
-#endif /* CONFIG_ATAPI */
-
-static void ide_ident(struct blk_desc *dev_desc)
+/**
+ * ide_ident() - Identify an IDE device
+ *
+ * @device: Device number to use
+ * @desc: Block descriptor to fill in
+ * Returns: 0 if OK, -ENOENT if no device is found
+ */
+static int ide_ident(int device, struct blk_desc *desc)
 {
-	unsigned char c;
 	hd_driveid_t iop;
-#ifdef CONFIG_ATAPI
 	bool is_atapi = false;
-	int retries = 0;
-#endif
-	int device;
+	int tries = 1;
+	u8 c;
 
-	device = dev_desc->devnum;
+	memset(desc, '\0', sizeof(*desc));
+	desc->devnum = device;
+	desc->type = DEV_TYPE_UNKNOWN;
+	desc->uclass_id = UCLASS_IDE;
+	desc->log2blksz = LOG2_INVALID(typeof(desc->log2blksz));
 	printf("  Device %d: ", device);
 
 	/* Select device
 	 */
 	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-	dev_desc->uclass_id = UCLASS_IDE;
-#ifdef CONFIG_ATAPI
+	if (IS_ENABLED(CONFIG_ATAPI))
+		tries = 2;
 
-	retries = 0;
-
-	/* Warning: This will be tricky to read */
-	while (retries <= 1) {
+	while (tries) {
 		/* check signature */
-		if ((ide_inb(device, ATA_SECT_CNT) == 0x01) &&
-		    (ide_inb(device, ATA_SECT_NUM) == 0x01) &&
-		    (ide_inb(device, ATA_CYL_LOW) == 0x14) &&
-		    (ide_inb(device, ATA_CYL_HIGH) == 0xEB)) {
+		if (IS_ENABLED(CONFIG_ATAPI) &&
+		    ide_inb(device, ATA_SECT_CNT) == 0x01 &&
+		    ide_inb(device, ATA_SECT_NUM) == 0x01 &&
+		    ide_inb(device, ATA_CYL_LOW) == 0x14 &&
+		    ide_inb(device, ATA_CYL_HIGH) == 0xeb) {
 			/* ATAPI Signature found */
 			is_atapi = true;
 			/*
@@ -558,9 +570,7 @@
 			 * to become ready
 			 */
 			c = ide_wait(device, ATAPI_TIME_OUT);
-		} else
-#endif
-		{
+		} else {
 			/*
 			 * Start Ident Command
 			 */
@@ -572,86 +582,70 @@
 			c = ide_wait(device, IDE_TIME_OUT);
 		}
 
-		if (((c & ATA_STAT_DRQ) == 0) ||
-		    ((c & (ATA_STAT_FAULT | ATA_STAT_ERR)) != 0)) {
-#ifdef CONFIG_ATAPI
-			{
-				/*
-				 * Need to soft reset the device
-				 * in case it's an ATAPI...
-				 */
-				debug("Retrying...\n");
-				ide_outb(device, ATA_DEV_HD,
-					 ATA_LBA | ATA_DEVICE(device));
-				udelay(100000);
-				ide_outb(device, ATA_COMMAND, 0x08);
-				udelay(500000);	/* 500 ms */
-			}
+		if ((c & ATA_STAT_DRQ) &&
+		    !(c & (ATA_STAT_FAULT | ATA_STAT_ERR))) {
+			break;
+		} else if (IS_ENABLED(CONFIG_ATAPI)) {
 			/*
-			 * Select device
+			 * Need to soft reset the device
+			 * in case it's an ATAPI...
 			 */
+			log_debug("Retrying...\n");
 			ide_outb(device, ATA_DEV_HD,
 				 ATA_LBA | ATA_DEVICE(device));
-			retries++;
-#else
-			return;
-#endif
+			mdelay(100);
+			ide_outb(device, ATA_COMMAND, 0x08);
+			mdelay(500);
+			/* Select device */
+			ide_outb(device, ATA_DEV_HD,
+				 ATA_LBA | ATA_DEVICE(device));
 		}
-#ifdef CONFIG_ATAPI
-		else
-			break;
-	}			/* see above - ugly to read */
+		tries--;
+	}
 
-	if (retries == 2)	/* Not found */
-		return;
-#endif
+	if (!tries)	/* Not found */
+		return -ENOENT;
 
 	ide_input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS);
 
-	ident_cpy((unsigned char *)dev_desc->revision, iop.fw_rev,
-		  sizeof(dev_desc->revision));
-	ident_cpy((unsigned char *)dev_desc->vendor, iop.model,
-		  sizeof(dev_desc->vendor));
-	ident_cpy((unsigned char *)dev_desc->product, iop.serial_no,
-		  sizeof(dev_desc->product));
+	ident_cpy((u8 *)desc->revision, iop.fw_rev, sizeof(desc->revision));
+	ident_cpy((u8 *)desc->vendor, iop.model, sizeof(desc->vendor));
+	ident_cpy((u8 *)desc->product, iop.serial_no, sizeof(desc->product));
 
-	if ((iop.config & 0x0080) == 0x0080)
-		dev_desc->removable = 1;
+	if (iop.config & 0x0080)
+		desc->removable = 1;
 	else
-		dev_desc->removable = 0;
+		desc->removable = 0;
 
-#ifdef CONFIG_ATAPI
-	if (is_atapi) {
-		atapi_inquiry(dev_desc);
-		return;
+	if (IS_ENABLED(CONFIG_ATAPI) && is_atapi) {
+		desc->atapi = true;
+		atapi_inquiry(desc);
+		return 0;
 	}
-#endif /* CONFIG_ATAPI */
 
 	iop.lba_capacity[0] = be16_to_cpu(iop.lba_capacity[0]);
 	iop.lba_capacity[1] = be16_to_cpu(iop.lba_capacity[1]);
-	dev_desc->lba =
-			((unsigned long)iop.lba_capacity[0]) |
-			((unsigned long)iop.lba_capacity[1] << 16);
+	desc->lba = (ulong)iop.lba_capacity[0] |
+		(ulong)iop.lba_capacity[1] << 16;
 
-#ifdef CONFIG_LBA48
-	if (iop.command_set_2 & 0x0400) {	/* LBA 48 support */
-		dev_desc->lba48 = 1;
+	if (IS_ENABLED(CONFIG_LBA48) && (iop.command_set_2 & 0x0400)) {
+		/* LBA 48 support */
+		desc->lba48 = true;
 		for (int i = 0; i < 4; i++)
 			iop.lba48_capacity[i] = be16_to_cpu(iop.lba48_capacity[i]);
-		dev_desc->lba =
-			((unsigned long long)iop.lba48_capacity[0] |
-			((unsigned long long)iop.lba48_capacity[1] << 16) |
-			((unsigned long long)iop.lba48_capacity[2] << 32) |
-			((unsigned long long)iop.lba48_capacity[3] << 48));
+		desc->lba = (unsigned long long)iop.lba48_capacity[0] |
+			(unsigned long long)iop.lba48_capacity[1] << 16 |
+			(unsigned long long)iop.lba48_capacity[2] << 32 |
+			(unsigned long long)iop.lba48_capacity[3] << 48;
 	} else {
-		dev_desc->lba48 = 0;
+		desc->lba48 = false;
 	}
-#endif /* CONFIG_LBA48 */
+
 	/* assuming HD */
-	dev_desc->type = DEV_TYPE_HARDDISK;
-	dev_desc->blksz = ATA_BLOCKSIZE;
-	dev_desc->log2blksz = LOG2(dev_desc->blksz);
-	dev_desc->lun = 0;	/* just to fill something in... */
+	desc->type = DEV_TYPE_HARDDISK;
+	desc->blksz = ATA_BLOCKSIZE;
+	desc->log2blksz = LOG2(desc->blksz);
+	desc->lun = 0;	/* just to fill something in... */
 
 #if 0				/* only used to test the powersaving mode,
 				 * if enabled, the drive goes after 5 sec
@@ -667,123 +661,58 @@
 	udelay(50);
 	c = ide_wait(device, IDE_TIME_OUT);	/* can't take over 500 ms */
 #endif
-}
 
-__weak void ide_outb(int dev, int port, unsigned char val)
-{
-	debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
-	      dev, port, val, ATA_CURR_BASE(dev) + port);
-
-	outb(val, ATA_CURR_BASE(dev) + port);
-}
-
-__weak unsigned char ide_inb(int dev, int port)
-{
-	uchar val;
-
-	val = inb(ATA_CURR_BASE(dev) + port);
-
-	debug("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
-	      dev, port, ATA_CURR_BASE(dev) + port, val);
-	return val;
+	return 0;
 }
 
-void ide_init(void)
+/**
+ * ide_init_one() - Init one IDE device
+ *
+ * @bus: Bus to use
+ * Return: 0 iuf OK, -EIO if not available, -ETIMEDOUT if timed out
+ */
+static int ide_init_one(int bus)
 {
-	struct udevice *dev;
-	unsigned char c;
-	int i, bus;
-
-	schedule();
-
-	/* ATAPI Drives seems to need a proper IDE Reset */
-	ide_reset();
-
-	/*
-	 * Wait for IDE to get ready.
-	 * According to spec, this can take up to 31 seconds!
-	 */
-	for (bus = 0; bus < CONFIG_SYS_IDE_MAXBUS; ++bus) {
-		int dev =
-			bus * (CONFIG_SYS_IDE_MAXDEVICE /
-			       CONFIG_SYS_IDE_MAXBUS);
-
-		printf("Bus %d: ", bus);
-
-		ide_bus_ok[bus] = 0;
-
-		/* Select device
-		 */
-		udelay(100000);	/* 100 ms */
-		ide_outb(dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
-		udelay(100000);	/* 100 ms */
-		i = 0;
-		do {
-			udelay(10000);	/* 10 ms */
+	int dev = bus * CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS;
+	int i;
+	u8 c;
 
-			c = ide_inb(dev, ATA_STATUS);
-			i++;
-			if (i > (ATA_RESET_TIME * 100)) {
-				puts("** Timeout **\n");
-				return;
-			}
-			if ((i >= 100) && ((i % 100) == 0))
-				putc('.');
+	printf("Bus %d: ", bus);
 
-		} while (c & ATA_STAT_BUSY);
+	/* Select device */
+	mdelay(100);
+	ide_outb(dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
+	mdelay(100);
+	i = 0;
+	do {
+		mdelay(10);
 
-		if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) {
-			puts("not available  ");
-			debug("Status = 0x%02X ", c);
-#ifndef CONFIG_ATAPI		/* ATAPI Devices do not set DRDY */
-		} else if ((c & ATA_STAT_READY) == 0) {
-			puts("not available  ");
-			debug("Status = 0x%02X ", c);
-#endif
-		} else {
-			puts("OK ");
-			ide_bus_ok[bus] = 1;
+		c = ide_inb(dev, ATA_STATUS);
+		i++;
+		if (i > (ATA_RESET_TIME * 100)) {
+			puts("** Timeout **\n");
+			return -ETIMEDOUT;
 		}
-		schedule();
-	}
+		if (i >= 100 && !(i % 100))
+			putc('.');
+	} while (c & ATA_STAT_BUSY);
 
-	putc('\n');
-
-	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
-		ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
-		ide_dev_desc[i].uclass_id = UCLASS_IDE;
-		ide_dev_desc[i].devnum = i;
-		ide_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
-		ide_dev_desc[i].blksz = 0;
-		ide_dev_desc[i].log2blksz =
-			LOG2_INVALID(typeof(ide_dev_desc[i].log2blksz));
-		ide_dev_desc[i].lba = 0;
-		if (!ide_bus_ok[IDE_BUS(i)])
-			continue;
-		ide_ident(&ide_dev_desc[i]);
-		dev_print(&ide_dev_desc[i]);
+	if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) {
+		puts("not available  ");
+		log_debug("Status = %#02X ", c);
+		return -EIO;
+	} else if (IS_ENABLED(CONFIG_ATAPI) && !(c & ATA_STAT_READY)) {
+		/* ATAPI Devices do not set DRDY */
+		puts("not available  ");
+		log_debug("Status = %#02X ", c);
+		return -EIO;
 	}
-	schedule();
+	puts("OK ");
 
-	uclass_first_device(UCLASS_IDE, &dev);
-}
-
-__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
-{
-	uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
-	ushort *dbuf = (ushort *)sect_buf;
-
-	debug("in input swap data base for read is %p\n", (void *)paddr);
-
-	while (words--) {
-		EIEIO;
-		*dbuf++ = be16_to_cpu(inw(paddr));
-		EIEIO;
-		*dbuf++ = be16_to_cpu(inw(paddr));
-	}
+	return 0;
 }
 
-__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
+static void ide_output_data(int dev, const ulong *sect_buf, int words)
 {
 	uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
 	ushort *dbuf;
@@ -797,14 +726,14 @@
 	}
 }
 
-__weak void ide_input_data(int dev, ulong *sect_buf, int words)
+static void ide_input_data(int dev, ulong *sect_buf, int words)
 {
 	uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
 	ushort *dbuf;
 
 	dbuf = (ushort *)sect_buf;
 
-	debug("in input data base for read is %p\n", (void *)paddr);
+	log_debug("in input data base for read is %p\n", (void *)paddr);
 
 	while (words--) {
 		EIEIO;
@@ -814,25 +743,23 @@
 	}
 }
 
-ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
-	       void *buffer)
+static ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+		      void *buffer)
 {
-	struct blk_desc *block_dev = dev_get_uclass_plat(dev);
-	int device = block_dev->devnum;
+	struct blk_desc *desc = dev_get_uclass_plat(dev);
+	int device = desc->devnum;
+	bool lba48 = false;
 	ulong n = 0;
-	unsigned char c;
-	unsigned char pwrsave = 0;	/* power save */
+	u8 pwrsave = 0;	/* power save */
+	u8 c;
 
-#ifdef CONFIG_LBA48
-	unsigned char lba48 = 0;
-
-	if (blknr & 0x0000fffff0000000ULL) {
+	if (IS_ENABLED(CONFIG_LBA48) && (blknr & 0x0000fffff0000000ULL)) {
 		/* more than 28 bits used, use 48bit mode */
-		lba48 = 1;
+		lba48 = true;
 	}
-#endif
-	debug("ide_read dev %d start " LBAF ", blocks " LBAF " buffer at %lX\n",
-	      device, blknr, blkcnt, (ulong) buffer);
+
+	log_debug("dev %d start " LBAF ", blocks " LBAF " buffer at %lx\n",
+		  device, blknr, blkcnt, (ulong)buffer);
 
 	/* Select device
 	 */
@@ -856,11 +783,11 @@
 		goto IDE_READ_E;
 	}
 	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
-		printf("No Powersaving mode %X\n", c);
+		printf("No Powersaving mode %x\n", c);
 	} else {
 		c = ide_inb(device, ATA_SECT_CNT);
-		debug("Powersaving %02X\n", c);
-		if (c == 0)
+		log_debug("Powersaving %02X\n", c);
+		if (!c)
 			pwrsave = 1;
 	}
 
@@ -872,36 +799,31 @@
 			printf("IDE read: device %d not ready\n", device);
 			break;
 		}
-#ifdef CONFIG_LBA48
-		if (lba48) {
+		if (IS_ENABLED(CONFIG_LBA48) && lba48) {
 			/* write high bits */
 			ide_outb(device, ATA_SECT_CNT, 0);
-			ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
+			ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xff);
 #ifdef CONFIG_SYS_64BIT_LBA
-			ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
-			ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
+			ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xff);
+			ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xff);
 #else
 			ide_outb(device, ATA_LBA_MID, 0);
 			ide_outb(device, ATA_LBA_HIGH, 0);
 #endif
 		}
-#endif
 		ide_outb(device, ATA_SECT_CNT, 1);
-		ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
-		ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
-		ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
+		ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xff);
+		ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xff);
+		ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xff);
 
-#ifdef CONFIG_LBA48
-		if (lba48) {
+		if (IS_ENABLED(CONFIG_LBA48) && lba48) {
 			ide_outb(device, ATA_DEV_HD,
 				 ATA_LBA | ATA_DEVICE(device));
 			ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_READ_EXT);
 
-		} else
-#endif
-		{
+		} else {
 			ide_outb(device, ATA_DEV_HD, ATA_LBA |
-				 ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
+				 ATA_DEVICE(device) | ((blknr >> 24) & 0xf));
 			ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_READ);
 		}
 
@@ -934,22 +856,19 @@
 	return n;
 }
 
-ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
-		const void *buffer)
+static ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+		       const void *buffer)
 {
-	struct blk_desc *block_dev = dev_get_uclass_plat(dev);
-	int device = block_dev->devnum;
+	struct blk_desc *desc = dev_get_uclass_plat(dev);
+	int device = desc->devnum;
 	ulong n = 0;
-	unsigned char c;
+	bool lba48 = false;
+	u8 c;
 
-#ifdef CONFIG_LBA48
-	unsigned char lba48 = 0;
-
-	if (blknr & 0x0000fffff0000000ULL) {
+	if (IS_ENABLED(CONFIG_LBA48) && (blknr & 0x0000fffff0000000ULL)) {
 		/* more than 28 bits used, use 48bit mode */
-		lba48 = 1;
+		lba48 = true;
 	}
-#endif
 
 	/* Select device
 	 */
@@ -962,36 +881,31 @@
 			printf("IDE read: device %d not ready\n", device);
 			goto WR_OUT;
 		}
-#ifdef CONFIG_LBA48
-		if (lba48) {
+		if (IS_ENABLED(CONFIG_LBA48) && lba48) {
 			/* write high bits */
 			ide_outb(device, ATA_SECT_CNT, 0);
-			ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
+			ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xff);
 #ifdef CONFIG_SYS_64BIT_LBA
-			ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
-			ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
+			ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xff);
+			ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xff);
 #else
 			ide_outb(device, ATA_LBA_MID, 0);
 			ide_outb(device, ATA_LBA_HIGH, 0);
 #endif
 		}
-#endif
 		ide_outb(device, ATA_SECT_CNT, 1);
-		ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
-		ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
-		ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
+		ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xff);
+		ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xff);
+		ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xff);
 
-#ifdef CONFIG_LBA48
-		if (lba48) {
+		if (IS_ENABLED(CONFIG_LBA48) && lba48) {
 			ide_outb(device, ATA_DEV_HD,
 				 ATA_LBA | ATA_DEVICE(device));
 			ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_WRITE_EXT);
 
-		} else
-#endif
-		{
+		} else {
 			ide_outb(device, ATA_DEV_HD, ATA_LBA |
-				 ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
+				 ATA_DEVICE(device) | ((blknr >> 24) & 0xf));
 			ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_WRITE);
 		}
 
@@ -1017,35 +931,19 @@
 	return n;
 }
 
-#if defined(CONFIG_OF_IDE_FIXUP)
-int ide_device_present(int dev)
+ulong ide_or_atapi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+			void *buffer)
 {
-	if (dev >= CONFIG_SYS_IDE_MAXBUS)
-		return 0;
-	return ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN ? 0 : 1;
-}
-#endif
+	struct blk_desc *desc = dev_get_uclass_plat(dev);
 
-static int ide_blk_probe(struct udevice *udev)
-{
-	struct blk_desc *desc = dev_get_uclass_plat(udev);
+	if (IS_ENABLED(CONFIG_ATAPI) && desc->atapi)
+		return atapi_read(dev, blknr, blkcnt, buffer);
 
-	/* fill in device vendor/product/rev strings */
-	strncpy(desc->vendor, ide_dev_desc[desc->devnum].vendor,
-		BLK_VEN_SIZE);
-	desc->vendor[BLK_VEN_SIZE] = '\0';
-	strncpy(desc->product, ide_dev_desc[desc->devnum].product,
-		BLK_PRD_SIZE);
-	desc->product[BLK_PRD_SIZE] = '\0';
-	strncpy(desc->revision, ide_dev_desc[desc->devnum].revision,
-		BLK_REV_SIZE);
-	desc->revision[BLK_REV_SIZE] = '\0';
-
-	return 0;
+	return ide_read(dev, blknr, blkcnt, buffer);
 }
 
 static const struct blk_ops ide_blk_ops = {
-	.read	= ide_read,
+	.read	= ide_or_atapi_read,
 	.write	= ide_write,
 };
 
@@ -1053,7 +951,6 @@
 	.name		= "ide_blk",
 	.id		= UCLASS_BLK,
 	.ops		= &ide_blk_ops,
-	.probe		= ide_blk_probe,
 };
 
 static int ide_bootdev_bind(struct udevice *dev)
@@ -1067,7 +964,9 @@
 
 static int ide_bootdev_hunt(struct bootdev_hunter *info, bool show)
 {
-	ide_init();
+	struct udevice *dev;
+
+	uclass_first_device(UCLASS_IDE, &dev);
 
 	return 0;
 }
@@ -1097,40 +996,72 @@
 
 static int ide_probe(struct udevice *udev)
 {
-	struct udevice *blk_dev;
-	char name[20];
-	int blksz;
-	lbaint_t size;
-	int i;
-	int ret;
+	bool bus_ok[CONFIG_SYS_IDE_MAXBUS];
+	int i, bus;
+
+	schedule();
+
+	/* ATAPI Drives seems to need a proper IDE Reset */
+	ide_reset();
+
+	/*
+	 * Wait for IDE to get ready.
+	 * According to spec, this can take up to 31 seconds!
+	 */
+	for (bus = 0; bus < CONFIG_SYS_IDE_MAXBUS; ++bus) {
+		bus_ok[bus] = !ide_init_one(bus);
+		schedule();
+	}
+
+	putc('\n');
+
+	schedule();
 
 	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; i++) {
-		if (ide_dev_desc[i].type != DEV_TYPE_UNKNOWN) {
-			sprintf(name, "blk#%d", i);
+		struct blk_desc *desc, pdesc;
+		struct udevice *blk;
+		char name[20];
+		int ret;
+
+		if (!bus_ok[IDE_BUS(i)])
+			continue;
 
-			blksz = ide_dev_desc[i].blksz;
-			size = blksz * ide_dev_desc[i].lba;
+		ret = ide_ident(i, &pdesc);
+		dev_print(&pdesc);
 
-			/*
-			 * With CDROM, if there is no CD inserted, blksz will
-			 * be zero, don't bother to create IDE block device.
-			 */
-			if (!blksz)
-				continue;
-			ret = blk_create_devicef(udev, "ide_blk", name,
-						 UCLASS_IDE, i,
-						 blksz, size, &blk_dev);
-			if (ret)
-				return ret;
+		if (ret)
+			continue;
 
-			ret = blk_probe_or_unbind(blk_dev);
-			if (ret)
-				return ret;
+		sprintf(name, "blk#%d", i);
 
-			ret = bootdev_setup_for_dev(udev, "ide_bootdev");
-			if (ret)
-				return log_msg_ret("bootdev", ret);
-		}
+		/*
+		 * With CDROM, if there is no CD inserted, blksz will
+		 * be zero, don't bother to create IDE block device.
+		 */
+		if (!pdesc.blksz)
+			continue;
+		ret = blk_create_devicef(udev, "ide_blk", name, UCLASS_IDE, i,
+					 pdesc.blksz, pdesc.lba, &blk);
+		if (ret)
+			return ret;
+
+		ret = blk_probe_or_unbind(blk);
+		if (ret)
+			return ret;
+
+		/* fill in device vendor/product/rev strings */
+		desc = dev_get_uclass_plat(blk);
+		strlcpy(desc->vendor, pdesc.vendor, BLK_VEN_SIZE);
+		strlcpy(desc->product, pdesc.product, BLK_PRD_SIZE);
+		strlcpy(desc->revision, pdesc.revision, BLK_REV_SIZE);
+		desc->removable = pdesc.removable;
+		desc->atapi = pdesc.atapi;
+		desc->lba48 = pdesc.lba48;
+		desc->type = pdesc.type;
+
+		ret = bootdev_setup_for_dev(udev, "ide_bootdev");
+		if (ret)
+			return log_msg_ret("bootdev", ret);
 	}
 
 	return 0;
diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c
index 0255cca..cc73445 100644
--- a/drivers/clk/mpc83xx_clk.c
+++ b/drivers/clk/mpc83xx_clk.c
@@ -346,8 +346,10 @@
 
 	type = dev_get_driver_data(dev);
 
+#ifdef CONFIG_FSL_ESDHC
 	if (mpc83xx_has_sdhc(type))
 		gd->arch.sdhc_clk = priv->speed[MPC83XX_CLK_SDHC];
+#endif
 
 	gd->arch.core_clk = priv->speed[MPC83XX_CLK_CORE];
 	gd->arch.i2c1_clk = priv->speed[MPC83XX_CLK_I2C1];
@@ -362,6 +364,11 @@
 	gd->cpu_clk = priv->speed[MPC83XX_CLK_CORE];
 	gd->bus_clk = priv->speed[MPC83XX_CLK_CSB];
 
+#ifdef CONFIG_QE
+	gd->arch.qe_clk = priv->speed[MPC83XX_CLK_QE];
+	gd->arch.brg_clk = priv->speed[MPC83XX_CLK_BRG];
+#endif
+
 	return 0;
 }
 
diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index abd4e8b..f27306f 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -23,6 +23,7 @@
 	[CLK_AHB_MMC1]		= GATE(0x060, BIT(9)),
 	[CLK_AHB_MMC2]		= GATE(0x060, BIT(10)),
 	[CLK_AHB_MMC3]		= GATE(0x060, BIT(11)),
+	[CLK_AHB_NAND]		= GATE(0x060, BIT(13)),
 	[CLK_AHB_EMAC]		= GATE(0x060, BIT(17)),
 	[CLK_AHB_SPI0]		= GATE(0x060, BIT(20)),
 	[CLK_AHB_SPI1]		= GATE(0x060, BIT(21)),
@@ -47,6 +48,7 @@
 	[CLK_APB1_UART6]	= GATE(0x06c, BIT(22)),
 	[CLK_APB1_UART7]	= GATE(0x06c, BIT(23)),
 
+	[CLK_NAND]		= GATE(0x080, BIT(31)),
 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
 	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index e486ced..16ac589 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -20,6 +20,7 @@
 	[CLK_AHB_MMC0]		= GATE(0x060, BIT(8)),
 	[CLK_AHB_MMC1]		= GATE(0x060, BIT(9)),
 	[CLK_AHB_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_AHB_NAND]		= GATE(0x060, BIT(13)),
 	[CLK_AHB_EMAC]		= GATE(0x060, BIT(17)),
 	[CLK_AHB_SPI0]		= GATE(0x060, BIT(20)),
 	[CLK_AHB_SPI1]		= GATE(0x060, BIT(21)),
@@ -35,6 +36,7 @@
 	[CLK_APB1_UART2]	= GATE(0x06c, BIT(18)),
 	[CLK_APB1_UART3]	= GATE(0x06c, BIT(19)),
 
+	[CLK_NAND]		= GATE(0x080, BIT(31)),
 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
 	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index d94feca..45d5ba7 100644
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -17,6 +17,7 @@
 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_BUS_NAND]		= GATE(0x060, BIT(13)),
 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
 	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
@@ -34,6 +35,7 @@
 	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
 	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
 
+	[CLK_NAND]		= GATE(0x080, BIT(31)),
 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
 
@@ -52,6 +54,7 @@
 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
+	[RST_BUS_NAND]		= RESET(0x2c0, BIT(13)),
 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
 	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index 3606589..6ca8000 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -18,6 +18,8 @@
 	[CLK_AHB1_MMC1]		= GATE(0x060, BIT(9)),
 	[CLK_AHB1_MMC2]		= GATE(0x060, BIT(10)),
 	[CLK_AHB1_MMC3]		= GATE(0x060, BIT(11)),
+	[CLK_AHB1_NAND1]	= GATE(0x060, BIT(12)),
+	[CLK_AHB1_NAND0]	= GATE(0x060, BIT(13)),
 	[CLK_AHB1_EMAC]		= GATE(0x060, BIT(17)),
 	[CLK_AHB1_SPI0]		= GATE(0x060, BIT(20)),
 	[CLK_AHB1_SPI1]		= GATE(0x060, BIT(21)),
@@ -43,6 +45,8 @@
 	[CLK_APB2_UART4]	= GATE(0x06c, BIT(20)),
 	[CLK_APB2_UART5]	= GATE(0x06c, BIT(21)),
 
+	[CLK_NAND0]		= GATE(0x080, BIT(31)),
+	[CLK_NAND1]		= GATE(0x084, BIT(31)),
 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
 	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
@@ -65,6 +69,8 @@
 	[RST_AHB1_MMC1]		= RESET(0x2c0, BIT(9)),
 	[RST_AHB1_MMC2]		= RESET(0x2c0, BIT(10)),
 	[RST_AHB1_MMC3]		= RESET(0x2c0, BIT(11)),
+	[RST_AHB1_NAND1]	= RESET(0x2c0, BIT(12)),
+	[RST_AHB1_NAND0]	= RESET(0x2c0, BIT(13)),
 	[RST_AHB1_EMAC]		= RESET(0x2c0, BIT(17)),
 	[RST_AHB1_SPI0]		= RESET(0x2c0, BIT(20)),
 	[RST_AHB1_SPI1]		= RESET(0x2c0, BIT(21)),
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 136ba89..fd26cd4 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -20,6 +20,7 @@
 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_BUS_NAND]		= GATE(0x060, BIT(13)),
 	[CLK_BUS_EMAC]		= GATE(0x060, BIT(17)),
 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
 	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
@@ -45,6 +46,7 @@
 	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
 	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
 
+	[CLK_NAND]		= GATE(0x080, BIT(31)),
 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
 
@@ -74,6 +76,7 @@
 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
+	[RST_BUS_NAND]		= RESET(0x2c0, BIT(13)),
 	[RST_BUS_EMAC]		= RESET(0x2c0, BIT(17)),
 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
 	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
index 3c9eb14..c5834f4 100644
--- a/drivers/clk/sunxi/clk_a80.c
+++ b/drivers/clk/sunxi/clk_a80.c
@@ -14,12 +14,18 @@
 #include <linux/bitops.h>
 
 static const struct ccu_clk_gate a80_gates[] = {
+	[CLK_NAND0_0]		= GATE(0x400, BIT(31)),
+	[CLK_NAND0_1]		= GATE(0x404, BIT(31)),
+	[CLK_NAND1_0]		= GATE(0x408, BIT(31)),
+	[CLK_NAND1_1]		= GATE(0x40c, BIT(31)),
 	[CLK_SPI0]		= GATE(0x430, BIT(31)),
 	[CLK_SPI1]		= GATE(0x434, BIT(31)),
 	[CLK_SPI2]		= GATE(0x438, BIT(31)),
 	[CLK_SPI3]		= GATE(0x43c, BIT(31)),
 
 	[CLK_BUS_MMC]		= GATE(0x580, BIT(8)),
+	[CLK_BUS_NAND0]		= GATE(0x580, BIT(13)),
+	[CLK_BUS_NAND1]		= GATE(0x580, BIT(12)),
 	[CLK_BUS_SPI0]		= GATE(0x580, BIT(20)),
 	[CLK_BUS_SPI1]		= GATE(0x580, BIT(21)),
 	[CLK_BUS_SPI2]		= GATE(0x580, BIT(22)),
@@ -42,6 +48,8 @@
 
 static const struct ccu_reset a80_resets[] = {
 	[RST_BUS_MMC]		= RESET(0x5a0, BIT(8)),
+	[RST_BUS_NAND0]		= RESET(0x5a0, BIT(13)),
+	[RST_BUS_NAND1]		= RESET(0x5a0, BIT(12)),
 	[RST_BUS_SPI0]		= RESET(0x5a0, BIT(20)),
 	[RST_BUS_SPI1]		= RESET(0x5a0, BIT(21)),
 	[RST_BUS_SPI2]		= RESET(0x5a0, BIT(22)),
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index d5af37b..760d98c 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -18,6 +18,7 @@
 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_BUS_NAND]		= GATE(0x060, BIT(13)),
 	[CLK_BUS_EMAC]		= GATE(0x060, BIT(17)),
 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
 	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
@@ -42,6 +43,7 @@
 	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
 	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
 
+	[CLK_NAND]		= GATE(0x080, BIT(31)),
 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
 
@@ -70,6 +72,7 @@
 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
+	[RST_BUS_NAND]		= RESET(0x2c0, BIT(13)),
 	[RST_BUS_EMAC]		= RESET(0x2c0, BIT(17)),
 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
 	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index 213ab51..32bc95f 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -19,6 +19,7 @@
 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_BUS_NAND]		= GATE(0x060, BIT(13)),
 	[CLK_BUS_EMAC]		= GATE(0x060, BIT(17)),
 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
 	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
@@ -49,6 +50,7 @@
 
 	[CLK_BUS_EPHY]		= GATE(0x070, BIT(0)),
 
+	[CLK_NAND]		= GATE(0x080, BIT(31)),
 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
 
@@ -77,6 +79,7 @@
 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
+	[RST_BUS_NAND]		= RESET(0x2c0, BIT(13)),
 	[RST_BUS_EMAC]		= RESET(0x2c0, BIT(17)),
 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
 	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index 24eb972..071fd58 100644
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -21,6 +21,10 @@
 	[CLK_DE]		= GATE(0x600, BIT(31)),
 	[CLK_BUS_DE]		= GATE(0x60c, BIT(0)),
 
+	[CLK_NAND0]		= GATE(0x810, BIT(31)),
+	[CLK_NAND1]		= GATE(0x814, BIT(31)),
+	[CLK_BUS_NAND]		= GATE(0x82c, BIT(0)),
+
 	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
 	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
 	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
@@ -72,6 +76,7 @@
 
 static struct ccu_reset h6_resets[] = {
 	[RST_BUS_DE]		= RESET(0x60c, BIT(16)),
+	[RST_BUS_NAND]		= RESET(0x82c, BIT(16)),
 
 	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
 	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
index 88d6bf3..113dcff 100644
--- a/drivers/clk/sunxi/clk_h616.c
+++ b/drivers/clk/sunxi/clk_h616.c
@@ -20,6 +20,10 @@
 	[CLK_DE]		= GATE(0x600, BIT(31)),
 	[CLK_BUS_DE]		= GATE(0x60c, BIT(0)),
 
+	[CLK_NAND0]		= GATE(0x810, BIT(31)),
+	[CLK_NAND1]		= GATE(0x814, BIT(31)),
+	[CLK_BUS_NAND]		= GATE(0x82c, BIT(0)),
+
 	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
 	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
 	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
@@ -81,6 +85,7 @@
 
 static struct ccu_reset h616_resets[] = {
 	[RST_BUS_DE]		= RESET(0x60c, BIT(16)),
+	[RST_BUS_NAND]		= RESET(0x82c, BIT(16)),
 
 	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
 	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index 630e80d..0fef6f3 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -19,6 +19,7 @@
 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
 	[CLK_BUS_MMC3]		= GATE(0x060, BIT(11)),
+	[CLK_BUS_NAND]		= GATE(0x060, BIT(13)),
 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
 	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
 	[CLK_BUS_SPI2]		= GATE(0x060, BIT(22)),
@@ -57,6 +58,7 @@
 	[CLK_BUS_UART6]		= GATE(0x06c, BIT(22)),
 	[CLK_BUS_UART7]		= GATE(0x06c, BIT(23)),
 
+	[CLK_NAND]		= GATE(0x080, BIT(31)),
 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
 	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
@@ -91,6 +93,7 @@
 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
 	[RST_BUS_MMC3]		= RESET(0x2c0, BIT(11)),
+	[RST_BUS_NAND]		= RESET(0x2c0, BIT(13)),
 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
 	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
 	[RST_BUS_SPI2]		= RESET(0x2c0, BIT(22)),
diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c
index 91bcd1a..b9b0c28 100644
--- a/drivers/core/fdtaddr.c
+++ b/drivers/core/fdtaddr.c
@@ -12,6 +12,7 @@
 #include <dm.h>
 #include <fdt_support.h>
 #include <log.h>
+#include <mapmem.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <dm/device-internal.h>
@@ -97,7 +98,10 @@
 {
 	fdt_addr_t addr = devfdt_get_addr_index(dev, index);
 
-	return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr;
+	if (addr == FDT_ADDR_T_NONE)
+		return NULL;
+
+	return map_sysmem(addr, 0);
 }
 
 fdt_addr_t devfdt_get_addr_size_index(const struct udevice *dev, int index,
diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c
index 85f7da5..81a3079 100644
--- a/drivers/core/of_access.c
+++ b/drivers/core/of_access.c
@@ -33,7 +33,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* list of struct alias_prop aliases */
-LIST_HEAD(aliases_lookup);
+static LIST_HEAD(aliases_lookup);
 
 /* "/aliaes" node */
 static struct device_node *of_aliases;
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 1762a07..e46d571 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -411,18 +411,14 @@
 }
 
 #if CONFIG_IS_ENABLED(OF_REAL)
-int uclass_find_device_by_phandle(enum uclass_id id, struct udevice *parent,
-				  const char *name, struct udevice **devp)
+static int uclass_find_device_by_phandle_id(enum uclass_id id,
+					    uint find_phandle,
+					    struct udevice **devp)
 {
 	struct udevice *dev;
 	struct uclass *uc;
-	int find_phandle;
 	int ret;
 
-	*devp = NULL;
-	find_phandle = dev_read_u32_default(parent, name, -1);
-	if (find_phandle <= 0)
-		return -ENOENT;
 	ret = uclass_get(id, &uc);
 	if (ret)
 		return ret;
@@ -440,6 +436,19 @@
 
 	return -ENODEV;
 }
+
+int uclass_find_device_by_phandle(enum uclass_id id, struct udevice *parent,
+				  const char *name, struct udevice **devp)
+{
+	int find_phandle;
+
+	*devp = NULL;
+	find_phandle = dev_read_u32_default(parent, name, -1);
+	if (find_phandle <= 0)
+		return -ENOENT;
+
+	return uclass_find_device_by_phandle_id(id, find_phandle, devp);
+}
 #endif
 
 int uclass_get_device_by_driver(enum uclass_id id,
@@ -535,31 +544,22 @@
 	return uclass_get_device_tail(dev, ret, devp);
 }
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_REAL)
+int uclass_get_device_by_of_path(enum uclass_id id, const char *path,
+				 struct udevice **devp)
+{
+	return uclass_get_device_by_ofnode(id, ofnode_path(path), devp);
+}
+
 int uclass_get_device_by_phandle_id(enum uclass_id id, uint phandle_id,
 				    struct udevice **devp)
 {
 	struct udevice *dev;
-	struct uclass *uc;
 	int ret;
 
 	*devp = NULL;
-	ret = uclass_get(id, &uc);
-	if (ret)
-		return ret;
-
-	uclass_foreach_dev(dev, uc) {
-		uint phandle;
-
-		phandle = dev_read_phandle(dev);
-
-		if (phandle == phandle_id) {
-			*devp = dev;
-			return uclass_get_device_tail(dev, ret, devp);
-		}
-	}
-
-	return -ENODEV;
+	ret = uclass_find_device_by_phandle_id(id, phandle_id, &dev);
+	return uclass_get_device_tail(dev, ret, devp);
 }
 
 int uclass_get_device_by_phandle(enum uclass_id id, struct udevice *parent,
diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig
new file mode 100644
index 0000000..fbb7335
--- /dev/null
+++ b/drivers/extcon/Kconfig
@@ -0,0 +1,31 @@
+menu "Extcon Support"
+
+config EXTCON
+	bool "External Connector Class (extcon) support"
+	depends on DM
+	help
+	  Say Y here to enable external connector class (extcon) support.
+	  This allows monitoring external connectors and supports external
+	  connectors with multiple states; i.e., an extcon that may have
+	  multiple cables attached. For example, an external connector
+	  of a device may be used to connect an HDMI cable and a AC adaptor,
+	  and to host USB ports. Many of 30-pin connectors including PDMI
+	  are also good examples.
+
+config EXTCON_SANDBOX
+	bool "Sandbox extcon"
+	depends on EXTCON
+	help
+	  Enable extcon support for sandbox. This is an emulation of a real
+	  extcon. Currectly all configuration is done in the probe.
+
+config EXTCON_MAX14526
+	bool "Maxim MAX14526 EXTCON Support"
+	depends on DM_I2C
+	depends on EXTCON
+	help
+	  If you say yes here you get support for the MUIC device of
+	  Maxim MAX14526. The MAX14526 MUIC is a USB port accessory
+	  detector and switch.
+
+endmenu
diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile
new file mode 100644
index 0000000..3309f2a
--- /dev/null
+++ b/drivers/extcon/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+
+obj-$(CONFIG_EXTCON) += extcon-uclass.o
+obj-$(CONFIG_EXTCON_SANDBOX) += extcon-sandbox.o
+obj-$(CONFIG_EXTCON_MAX14526) += extcon-max14526.o
diff --git a/drivers/extcon/extcon-max14526.c b/drivers/extcon/extcon-max14526.c
new file mode 100644
index 0000000..a33b5ef
--- /dev/null
+++ b/drivers/extcon/extcon-max14526.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <log.h>
+#include <extcon.h>
+#include <asm/gpio.h>
+
+#define CONTROL_1	0x01
+#define SW_CONTROL	0x03
+
+#define ID_200		0x10
+#define ADC_EN		0x02
+#define CP_EN		0x01
+
+#define DP_USB		0x00
+#define DP_UART		0x08
+#define DP_AUDIO	0x10
+#define DP_OPEN		0x38
+
+#define DM_USB		0x00
+#define DM_UART		0x01
+#define DM_AUDIO	0x02
+#define DM_OPEN		0x07
+
+#define AP_USB		BIT(0)
+#define CP_USB		BIT(1)
+#define CP_UART		BIT(2)
+
+struct max14526_priv {
+	struct gpio_desc usif_gpio;
+	struct gpio_desc dp2t_gpio;
+	struct gpio_desc ifx_usb_vbus_gpio;
+};
+
+static void max14526_set_mode(struct udevice *dev, int mode)
+{
+	struct max14526_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	if ((mode & AP_USB) || (mode & CP_USB)) {
+		/* Connect CP UART signals to AP */
+		ret = dm_gpio_set_value(&priv->usif_gpio, 0);
+		if (ret)
+			log_debug("cp-uart > ap failed (%d)\n", ret);
+	}
+
+	if (mode & CP_UART) {
+		/* Connect CP UART signals to DP2T */
+		ret = dm_gpio_set_value(&priv->usif_gpio, 1);
+		if (ret)
+			log_debug("cp-uart > dp2t failed (%d)\n", ret);
+	}
+
+	if (mode & CP_USB) {
+		/* Connect CP USB to MUIC UART */
+		ret = dm_gpio_set_value(&priv->ifx_usb_vbus_gpio, 1);
+		if (ret)
+			log_debug("usb-vbus-gpio enable failed (%d)\n", ret);
+
+		ret = dm_gpio_set_value(&priv->dp2t_gpio, 1);
+		if (ret)
+			log_debug("cp-usb > muic-uart failed (%d)\n", ret);
+	}
+
+	if ((mode & AP_USB) || (mode & CP_UART)) {
+		/* Connect CP UART to MUIC UART */
+		ret = dm_gpio_set_value(&priv->dp2t_gpio, 0);
+		if (ret)
+			log_debug("cp-uart > muic-uart failed (%d)\n", ret);
+	}
+
+	if (mode & AP_USB) {
+		/* Enables USB Path */
+		ret = dm_i2c_reg_write(dev, SW_CONTROL, DP_USB | DM_USB);
+		if (ret)
+			log_debug("USB path set failed: %d\n", ret);
+	}
+
+	if ((mode & CP_USB) || (mode & CP_UART)) {
+		/* Enables UART Path */
+		ret = dm_i2c_reg_write(dev, SW_CONTROL, DP_UART | DM_UART);
+		if (ret)
+			log_debug("UART path set failed: %d\n", ret);
+	}
+
+	/* Enables 200K, Charger Pump, and ADC */
+	ret = dm_i2c_reg_write(dev, CONTROL_1, ID_200 | ADC_EN | CP_EN);
+	if (ret)
+		log_debug("200K, Charger Pump, and ADC set failed: %d\n", ret);
+}
+
+static int max14526_probe(struct udevice *dev)
+{
+	struct max14526_priv *priv = dev_get_priv(dev);
+	int ret, mode = 0;
+
+	ret = gpio_request_by_name(dev, "usif-gpios", 0,
+				   &priv->usif_gpio, GPIOD_IS_OUT);
+	if (ret) {
+		log_err("could not decode usif-gpios (%d)\n", ret);
+		return ret;
+	}
+
+	ret = gpio_request_by_name(dev, "dp2t-gpios", 0,
+				   &priv->dp2t_gpio, GPIOD_IS_OUT);
+	if (ret) {
+		log_err("could not decode dp2t-gpios (%d)\n", ret);
+		return ret;
+	}
+
+	if (dev_read_bool(dev, "maxim,ap-usb"))
+		mode |= AP_USB;
+
+	if (dev_read_bool(dev, "maxim,cp-usb")) {
+		mode |= CP_USB;
+
+		ret = gpio_request_by_name(dev, "usb-vbus-gpios", 0,
+					   &priv->ifx_usb_vbus_gpio, GPIOD_IS_OUT);
+		if (ret) {
+			log_err("could not decode usb-vbus-gpios (%d)\n", ret);
+			return ret;
+		}
+	}
+
+	if (dev_read_bool(dev, "maxim,cp-uart"))
+		mode |= CP_UART;
+
+	max14526_set_mode(dev, mode);
+
+	return 0;
+}
+
+static const struct udevice_id max14526_ids[] = {
+	{ .compatible = "maxim,max14526-muic" },
+	{ }
+};
+
+U_BOOT_DRIVER(extcon_max14526) = {
+	.name		= "extcon_max14526",
+	.id		= UCLASS_EXTCON,
+	.of_match	= max14526_ids,
+	.probe		= max14526_probe,
+	.priv_auto	= sizeof(struct max14526_priv),
+};
diff --git a/drivers/extcon/extcon-sandbox.c b/drivers/extcon/extcon-sandbox.c
new file mode 100644
index 0000000..ab6a6c1
--- /dev/null
+++ b/drivers/extcon/extcon-sandbox.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+
+static const struct udevice_id sandbox_extcon_ids[] = {
+	{ .compatible = "sandbox,extcon" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(extcon_sandbox) = {
+	.name		= "extcon_sandbox",
+	.id		= UCLASS_EXTCON,
+	.of_match	= sandbox_extcon_ids,
+};
diff --git a/drivers/extcon/extcon-uclass.c b/drivers/extcon/extcon-uclass.c
new file mode 100644
index 0000000..9dd22b5
--- /dev/null
+++ b/drivers/extcon/extcon-uclass.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#define LOG_CATEGORY UCLASS_EXTCON
+
+#include <common.h>
+#include <extcon.h>
+#include <dm.h>
+
+UCLASS_DRIVER(extcon) = {
+	.id			= UCLASS_EXTCON,
+	.name			= "extcon",
+	.per_device_plat_auto	= sizeof(struct extcon_uc_plat),
+};
diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
index ef3e983..c6b9efa 100644
--- a/drivers/firmware/psci.c
+++ b/drivers/firmware/psci.c
@@ -319,4 +319,5 @@
 #ifdef CONFIG_ARM_SMCCC_FEATURES
 	.plat_auto = sizeof(struct psci_plat_data),
 #endif
+	.flags = DM_FLAG_PRE_RELOC,
 };
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 7d5ddbd..9bf6e42 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -547,6 +547,24 @@
 	  value setting, the open-drain feature, which can configure individual
 	  GPIOs to work as open-drain outputs, is supported.
 
+config QE_GPIO
+	bool "Freescale QUICC ENGINE GPIO driver"
+	depends on DM_GPIO
+	depends on QE
+	help
+	  This driver supports the QUICC Engine GPIOs of MPC83XX CPUs.
+	  Each GPIO bank is identified by its own entry in the device tree,
+	  i.e.
+
+	  qe_pio_a: gpio-controller@1400 {
+		compatible = "fsl,mpc8323-qe-pario-bank";
+		reg = <0x1400 0x18>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	  };
+
+	  Each bank has 32 GPIOs.
+
 config MPC8XX_GPIO
 	bool "Freescale MPC8XX GPIO driver"
 	depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 1e81e36..64a36c4 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -38,6 +38,7 @@
 obj-$(CONFIG_DA8XX_GPIO)	+= da8xx_gpio.o
 obj-$(CONFIG_ALTERA_PIO)	+= altera_pio.o
 obj-$(CONFIG_MPC8XXX_GPIO)	+= mpc8xxx_gpio.o
+obj-$(CONFIG_QE_GPIO)	+= qe_gpio.o
 obj-$(CONFIG_MPC8XX_GPIO)	+= mpc8xx_gpio.o
 obj-$(CONFIG_MPC83XX_SPISEL_BOOT)	+= mpc83xx_spisel_boot.o
 obj-$(CONFIG_SH_GPIO_PFC)	+= sh_pfc.o
diff --git a/drivers/gpio/axp_gpio.c b/drivers/gpio/axp_gpio.c
index 35585dc..4967219 100644
--- a/drivers/gpio/axp_gpio.c
+++ b/drivers/gpio/axp_gpio.c
@@ -36,18 +36,11 @@
 {
 	u8 reg;
 
-	switch (pin) {
-#ifndef CONFIG_AXP152_POWER /* NA on axp152 */
-	case SUNXI_GPIO_AXP0_VBUS_DETECT:
-		return 0;
-#endif
-	default:
-		reg = axp_get_gpio_ctrl_reg(pin);
-		if (reg == 0)
-			return -EINVAL;
+	reg = axp_get_gpio_ctrl_reg(pin);
+	if (reg == 0)
+		return -EINVAL;
 
-		return pmic_bus_write(reg, AXP_GPIO_CTRL_INPUT);
-	}
+	return pmic_bus_write(reg, AXP_GPIO_CTRL_INPUT);
 }
 
 static int axp_gpio_direction_output(struct udevice *dev, unsigned pin,
@@ -83,12 +76,6 @@
 	int ret;
 
 	switch (pin) {
-#ifndef CONFIG_AXP152_POWER /* NA on axp152 */
-	case SUNXI_GPIO_AXP0_VBUS_DETECT:
-		ret = pmic_bus_read(AXP_POWER_STATUS, &val);
-		mask = AXP_POWER_STATUS_VBUS_PRESENT;
-		break;
-#endif
 #ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
 	/* Only available on later PMICs */
 	case SUNXI_GPIO_AXP0_VBUS_ENABLE:
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index c8be5a4..712119c 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -1219,7 +1219,7 @@
 	return count;
 
 err:
-	gpio_free_list_nodev(desc, count - 1);
+	gpio_free_list_nodev(desc, count);
 
 	return ret;
 }
diff --git a/drivers/gpio/qe_gpio.c b/drivers/gpio/qe_gpio.c
new file mode 100644
index 0000000..16e8d1e
--- /dev/null
+++ b/drivers/gpio/qe_gpio.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 CR GROUP France
+ * Christophe Leroy <christophe.leroy@csgroup.eu>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mapmem.h>
+#include <asm/gpio.h>
+#include <asm/immap_83xx.h>
+#include <asm/io.h>
+#include <dm/of_access.h>
+
+#define QE_DIR_NONE	0
+#define QE_DIR_OUT	1
+#define QE_DIR_IN	2
+#define QE_DIR_IN_OUT	3
+
+struct qe_gpio_data {
+	/* The bank's register base in memory */
+	struct gpio_n __iomem *base;
+	/* The address of the registers; used to identify the bank */
+	phys_addr_t addr;
+};
+
+static inline u32 gpio_mask(uint gpio)
+{
+	return 1U << (31 - (gpio));
+}
+
+static inline u32 gpio_mask2(uint gpio)
+{
+	return 1U << (30 - ((gpio & 15) << 1));
+}
+
+static int qe_gpio_direction_input(struct udevice *dev, uint gpio)
+{
+	struct qe_gpio_data *data = dev_get_priv(dev);
+	struct gpio_n __iomem *base = data->base;
+	u32 mask2 = gpio_mask2(gpio);
+
+	if (gpio < 16)
+		clrsetbits_be32(&base->dir1, mask2 * QE_DIR_OUT, mask2 * QE_DIR_IN);
+	else
+		clrsetbits_be32(&base->dir2, mask2 * QE_DIR_OUT, mask2 * QE_DIR_IN);
+
+	return 0;
+}
+
+static int qe_gpio_set_value(struct udevice *dev, uint gpio, int value)
+{
+	struct qe_gpio_data *data = dev_get_priv(dev);
+	struct gpio_n __iomem *base = data->base;
+	u32 mask = gpio_mask(gpio);
+	u32 mask2 = gpio_mask2(gpio);
+
+	if (gpio < 16)
+		clrsetbits_be32(&base->dir1, mask2 * QE_DIR_IN, mask2 * QE_DIR_OUT);
+	else
+		clrsetbits_be32(&base->dir2, mask2 * QE_DIR_IN, mask2 * QE_DIR_OUT);
+
+	if (value)
+		setbits_be32(&base->pdat, mask);
+	else
+		clrbits_be32(&base->pdat, mask);
+
+	return 0;
+}
+
+static int qe_gpio_get_value(struct udevice *dev, uint gpio)
+{
+	struct qe_gpio_data *data = dev_get_priv(dev);
+	struct gpio_n __iomem *base = data->base;
+	u32 mask = gpio_mask(gpio);
+
+	return !!(in_be32(&base->pdat) & mask);
+}
+
+static int qe_gpio_get_function(struct udevice *dev, uint gpio)
+{
+	struct qe_gpio_data *data = dev_get_priv(dev);
+	struct gpio_n __iomem *base = data->base;
+	u32 mask2 = gpio_mask2(gpio);
+	int dir;
+
+	if (gpio < 16)
+		dir = in_be32(&base->dir1);
+	else
+		dir = in_be32(&base->dir2);
+
+	if ((dir & (mask2 * QE_DIR_IN_OUT)) == (mask2 & QE_DIR_IN))
+		return GPIOF_INPUT;
+	else if ((dir & (mask2 * QE_DIR_IN_OUT)) == (mask2 & QE_DIR_OUT))
+		return GPIOF_OUTPUT;
+	else
+		return GPIOF_UNKNOWN;
+}
+
+static int qe_gpio_of_to_plat(struct udevice *dev)
+{
+	struct qe_gpio_plat *plat = dev_get_plat(dev);
+
+	plat->addr = dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size);
+
+	return 0;
+}
+
+static int qe_gpio_plat_to_priv(struct udevice *dev)
+{
+	struct qe_gpio_data *priv = dev_get_priv(dev);
+	struct qe_gpio_plat *plat = dev_get_plat(dev);
+	unsigned long size = plat->size;
+
+	if (size == 0)
+		size = sizeof(struct gpio_n);
+
+	priv->addr = plat->addr;
+	priv->base = (void __iomem *)plat->addr;
+
+	if (!priv->base)
+		return -ENOMEM;
+
+	return 0;
+}
+
+static int qe_gpio_probe(struct udevice *dev)
+{
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct qe_gpio_data *data = dev_get_priv(dev);
+	char name[32], *str;
+
+	qe_gpio_plat_to_priv(dev);
+
+	snprintf(name, sizeof(name), "QE@%.8llx",
+		 (unsigned long long)data->addr);
+	str = strdup(name);
+
+	if (!str)
+		return -ENOMEM;
+
+	uc_priv->bank_name = str;
+	uc_priv->gpio_count = 32;
+
+	return 0;
+}
+
+static const struct dm_gpio_ops gpio_qe_ops = {
+	.direction_input	= qe_gpio_direction_input,
+	.direction_output	= qe_gpio_set_value,
+	.get_value		= qe_gpio_get_value,
+	.set_value		= qe_gpio_set_value,
+	.get_function		= qe_gpio_get_function,
+};
+
+static const struct udevice_id qe_gpio_ids[] = {
+	{ .compatible = "fsl,mpc8323-qe-pario-bank"},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(gpio_qe) = {
+	.name	= "gpio_qe",
+	.id	= UCLASS_GPIO,
+	.ops	= &gpio_qe_ops,
+	.of_to_plat = qe_gpio_of_to_plat,
+	.plat_auto	= sizeof(struct qe_gpio_plat),
+	.of_match = qe_gpio_ids,
+	.probe	= qe_gpio_probe,
+	.priv_auto	= sizeof(struct qe_gpio_data),
+};
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 1e85db1..f0b42e4 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -117,11 +117,7 @@
 #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
 	char lookup[8];
 
-	if (strcasecmp(name, "AXP0-VBUS-DETECT") == 0) {
-		sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
-			SUNXI_GPIO_AXP0_VBUS_DETECT);
-		name = lookup;
-	} else if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
+	if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
 		sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
 			SUNXI_GPIO_AXP0_VBUS_ENABLE);
 		name = lookup;
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 4e1ae03..04460f1 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -511,6 +511,13 @@
 	  legacy UART or other devices in the Winbond Super IO chips
 	  on X86 platforms.
 
+config QCOM_GENI_SE
+	bool "Qualcomm GENI Serial Engine Driver"
+	depends on ARCH_SNAPDRAGON
+	help
+	  The driver manages Generic Interface (GENI) firmware based
+	  Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper.
+
 config QFW
 	bool
 	help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 3b792f2..52aed09 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -60,6 +60,7 @@
 obj-$(CONFIG_P2SB) += p2sb-uclass.o
 obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
 obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
+obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
 ifdef CONFIG_QFW
 obj-y += qfw.o
 obj-$(CONFIG_QFW_PIO) += qfw_pio.o
diff --git a/drivers/misc/esm_pmic.c b/drivers/misc/esm_pmic.c
index a195dc5..b971f32 100644
--- a/drivers/misc/esm_pmic.c
+++ b/drivers/misc/esm_pmic.c
@@ -26,6 +26,9 @@
 #define ESM_MCU_EN		BIT(6)
 #define ESM_MCU_ENDRV		BIT(5)
 
+#define ESM_MCU_MASK_REG	0x59
+#define ESM_MCU_MASK		0x7
+
 /**
  * pmic_esm_probe: configures and enables PMIC ESM functionality
  *
@@ -48,6 +51,12 @@
 		return ret;
 	}
 
+	ret = pmic_reg_write(dev->parent, ESM_MCU_MASK_REG, ESM_MCU_MASK);
+	if (ret) {
+		dev_err(dev, "clearing ESM masks failed: %d\n", ret);
+		return ret;
+	}
+
 	ret = pmic_reg_write(dev->parent, ESM_MCU_START_REG, ESM_MCU_START);
 	if (ret) {
 		dev_err(dev, "starting ESM failed: %d\n", ret);
diff --git a/drivers/misc/qcom-geni-se.c b/drivers/misc/qcom-geni-se.c
new file mode 100644
index 0000000..281a5ec
--- /dev/null
+++ b/drivers/misc/qcom-geni-se.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm Generic Interface (GENI) Serial Engine (SE) Wrapper
+ *
+ * Copyright (C) 2023 Linaro Ltd. <vladimir.zapolskiy@linaro.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <misc.h>
+#include <asm/io.h>
+
+static int geni_se_qup_read(struct udevice *dev, int offset,
+			    void *buf, int size)
+{
+	fdt_addr_t base = dev_read_addr(dev);
+
+	if (size != sizeof(u32))
+		return -EINVAL;
+
+	*(u32 *)buf = readl(base + offset);
+
+	return size;
+}
+
+static struct misc_ops geni_se_qup_ops = {
+	.read = geni_se_qup_read,
+};
+
+static const struct udevice_id geni_se_qup_ids[] = {
+	{ .compatible = "qcom,geni-se-qup" },
+	{}
+};
+
+U_BOOT_DRIVER(geni_se_qup) = {
+	.name = "geni_se_qup",
+	.id = UCLASS_MISC,
+	.of_match = geni_se_qup_ids,
+	.ops = &geni_se_qup_ops,
+	.flags  = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c
index 2cec5b9..71962cd 100644
--- a/drivers/mmc/hi6220_dw_mmc.c
+++ b/drivers/mmc/hi6220_dw_mmc.c
@@ -100,6 +100,8 @@
 	  .data = (ulong)&hi6220_mmc_data },
 	{ .compatible = "hisilicon,hi3798cv200-dw-mshc",
 	  .data = (ulong)&hi6220_mmc_data },
+	{ .compatible = "hisilicon,hi3798mv200-dw-mshc",
+	  .data = (ulong)&hi6220_mmc_data },
 	{ .compatible = "hisilicon,hi3660-dw-mshc",
 	  .data = (ulong)&hi3660_mmc_data },
 	{ }
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index af45ef0..5fa88da 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -270,4 +270,6 @@
 
 source "drivers/mtd/ubi/Kconfig"
 
+source "drivers/mtd/nvmxip/Kconfig"
+
 endmenu
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 3a78590..c638980 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -25,6 +25,7 @@
 obj-y += onenand/
 obj-y += spi/
 obj-$(CONFIG_MTD_UBI) += ubi/
+obj-$(CONFIG_NVMXIP) += nvmxip/
 
 #SPL/TPL build
 else
diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c
index c378f08..c0fa1e3 100644
--- a/drivers/mtd/nand/raw/sunxi_nand.c
+++ b/drivers/mtd/nand/raw/sunxi_nand.c
@@ -24,12 +24,13 @@
  * GNU General Public License for more details.
  */
 
+#include <clk.h>
 #include <common.h>
-#include <fdtdec.h>
+#include <dm.h>
 #include <malloc.h>
 #include <memalign.h>
 #include <nand.h>
-#include <asm/global_data.h>
+#include <reset.h>
 #include <dm/device_compat.h>
 #include <dm/devres.h>
 #include <linux/bitops.h>
@@ -45,8 +46,6 @@
 #include <asm/gpio.h>
 #include <asm/arch/clock.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #define NFC_REG_CTL		0x0000
 #define NFC_REG_ST		0x0004
 #define NFC_REG_INT		0x0008
@@ -263,7 +262,7 @@
  * NAND Controller structure: stores sunxi NAND controller information
  *
  * @controller:		base controller structure
- * @dev:		parent device (used to print error messages)
+ * @dev:		DM device (used to print error messages)
  * @regs:		NAND controller registers
  * @ahb_clk:		NAND Controller AHB clock
  * @mod_clk:		NAND Controller mod clock
@@ -276,7 +275,7 @@
  */
 struct sunxi_nfc {
 	struct nand_hw_control controller;
-	struct device *dev;
+	struct udevice *dev;
 	void __iomem *regs;
 	struct clk *ahb_clk;
 	struct clk *mod_clk;
@@ -1605,24 +1604,24 @@
 	return 0;
 }
 
-static int sunxi_nand_chip_init(int node, struct sunxi_nfc *nfc, int devnum)
+static int sunxi_nand_chip_init(struct udevice *dev, struct sunxi_nfc *nfc,
+				ofnode np, int devnum)
 {
 	const struct nand_sdr_timings *timings;
-	const void *blob = gd->fdt_blob;
 	struct sunxi_nand_chip *chip;
 	struct mtd_info *mtd;
 	struct nand_chip *nand;
 	int nsels;
 	int ret;
 	int i;
-	u32 cs[8], rb[8];
+	u32 tmp;
 
-	if (!fdt_getprop(blob, node, "reg", &nsels))
+	if (!ofnode_get_property(np, "reg", &nsels))
 		return -EINVAL;
 
 	nsels /= sizeof(u32);
 	if (!nsels || nsels > 8) {
-		dev_err(nfc->dev, "invalid reg property size\n");
+		dev_err(dev, "invalid reg property size\n");
 		return -EINVAL;
 	}
 
@@ -1630,7 +1629,7 @@
 		       (nsels * sizeof(struct sunxi_nand_chip_sel)),
 		       GFP_KERNEL);
 	if (!chip) {
-		dev_err(nfc->dev, "could not allocate chip\n");
+		dev_err(dev, "could not allocate chip\n");
 		return -ENOMEM;
 	}
 
@@ -1638,48 +1637,34 @@
 	chip->selected = -1;
 
 	for (i = 0; i < nsels; i++) {
-		cs[i] = -1;
-		rb[i] = -1;
-	}
-
-	ret = fdtdec_get_int_array(gd->fdt_blob, node, "reg", cs, nsels);
-	if (ret) {
-		dev_err(nfc->dev, "could not retrieve reg property: %d\n", ret);
-		return ret;
-	}
-
-	ret = fdtdec_get_int_array(gd->fdt_blob, node, "allwinner,rb", rb,
-				   nsels);
-	if (ret) {
-		dev_err(nfc->dev, "could not retrieve reg property: %d\n", ret);
-		return ret;
-	}
-
-	for (i = 0; i < nsels; i++) {
-		int tmp = cs[i];
+		ret = ofnode_read_u32_index(np, "reg", i, &tmp);
+		if (ret) {
+			dev_err(dev, "could not retrieve reg property: %d\n",
+				ret);
+			return ret;
+		}
 
 		if (tmp > NFC_MAX_CS) {
-			dev_err(nfc->dev,
+			dev_err(dev,
 				"invalid reg value: %u (max CS = 7)\n", tmp);
 			return -EINVAL;
 		}
 
 		if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
-			dev_err(nfc->dev, "CS %d already assigned\n", tmp);
+			dev_err(dev, "CS %d already assigned\n", tmp);
 			return -EINVAL;
 		}
 
 		chip->sels[i].cs = tmp;
 
-		tmp = rb[i];
-		if (tmp >= 0 && tmp < 2) {
+		if (!ofnode_read_u32_index(np, "allwinner,rb", i, &tmp) &&
+		    tmp < 2) {
 			chip->sels[i].rb.type = RB_NATIVE;
 			chip->sels[i].rb.info.nativeid = tmp;
 		} else {
-			ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
-						"rb-gpios", i,
-						&chip->sels[i].rb.info.gpio,
-						GPIOD_IS_IN);
+			ret = gpio_request_by_name(dev, "rb-gpios", i,
+						   &chip->sels[i].rb.info.gpio,
+						   GPIOD_IS_IN);
 			if (ret)
 				chip->sels[i].rb.type = RB_GPIO;
 			else
@@ -1690,7 +1675,7 @@
 	timings = onfi_async_timing_mode_to_sdr_timings(0);
 	if (IS_ERR(timings)) {
 		ret = PTR_ERR(timings);
-		dev_err(nfc->dev,
+		dev_err(dev,
 			"could not retrieve timings for ONFI mode 0: %d\n",
 			ret);
 		return ret;
@@ -1698,7 +1683,7 @@
 
 	ret = sunxi_nand_chip_set_timings(nfc, chip, timings);
 	if (ret) {
-		dev_err(nfc->dev, "could not configure chip timings: %d\n", ret);
+		dev_err(dev, "could not configure chip timings: %d\n", ret);
 		return ret;
 	}
 
@@ -1711,7 +1696,7 @@
 	 * in the DT.
 	 */
 	nand->ecc.mode = NAND_ECC_HW;
-	nand->flash_node = offset_to_ofnode(node);
+	nand->flash_node = np;
 	nand->select_chip = sunxi_nfc_select_chip;
 	nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
 	nand->read_buf = sunxi_nfc_read_buf;
@@ -1733,25 +1718,25 @@
 
 	ret = sunxi_nand_chip_init_timings(nfc, chip);
 	if (ret) {
-		dev_err(nfc->dev, "could not configure chip timings: %d\n", ret);
+		dev_err(dev, "could not configure chip timings: %d\n", ret);
 		return ret;
 	}
 
 	ret = sunxi_nand_ecc_init(mtd, &nand->ecc);
 	if (ret) {
-		dev_err(nfc->dev, "ECC init failed: %d\n", ret);
+		dev_err(dev, "ECC init failed: %d\n", ret);
 		return ret;
 	}
 
 	ret = nand_scan_tail(mtd);
 	if (ret) {
-		dev_err(nfc->dev, "nand_scan_tail failed: %d\n", ret);
+		dev_err(dev, "nand_scan_tail failed: %d\n", ret);
 		return ret;
 	}
 
 	ret = nand_register(devnum, mtd);
 	if (ret) {
-		dev_err(nfc->dev, "failed to register mtd device: %d\n", ret);
+		dev_err(dev, "failed to register mtd device: %d\n", ret);
 		return ret;
 	}
 
@@ -1760,25 +1745,13 @@
 	return 0;
 }
 
-static int sunxi_nand_chips_init(int node, struct sunxi_nfc *nfc)
+static int sunxi_nand_chips_init(struct udevice *dev, struct sunxi_nfc *nfc)
 {
-	const void *blob = gd->fdt_blob;
-	int nand_node;
+	ofnode nand_np;
 	int ret, i = 0;
 
-	for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
-	     nand_node = fdt_next_subnode(blob, nand_node))
-		i++;
-
-	if (i > 8) {
-		dev_err(nfc->dev, "too many NAND chips: %d (max = 8)\n", i);
-		return -EINVAL;
-	}
-
-	i = 0;
-	for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
-	     nand_node = fdt_next_subnode(blob, nand_node)) {
-		ret = sunxi_nand_chip_init(nand_node, nfc, i++);
+	dev_for_each_subnode(nand_np, dev) {
+		ret = sunxi_nand_chip_init(dev, nfc, nand_np, i++);
 		if (ret)
 			return ret;
 	}
@@ -1802,55 +1775,67 @@
 }
 #endif /* __UBOOT__ */
 
-void sunxi_nand_init(void)
+static int sunxi_nand_probe(struct udevice *dev)
 {
-	const void *blob = gd->fdt_blob;
-	struct sunxi_nfc *nfc;
-	fdt_addr_t regs;
-	int node;
+	struct sunxi_nfc *nfc = dev_get_priv(dev);
+	struct reset_ctl_bulk rst_bulk;
+	struct clk_bulk clk_bulk;
 	int ret;
 
-	nfc = kzalloc(sizeof(*nfc), GFP_KERNEL);
-	if (!nfc)
-		return;
-
+	nfc->dev = dev;
 	spin_lock_init(&nfc->controller.lock);
 	init_waitqueue_head(&nfc->controller.wq);
 	INIT_LIST_HEAD(&nfc->chips);
 
-	node = fdtdec_next_compatible(blob, 0, COMPAT_SUNXI_NAND);
-	if (node < 0) {
-		pr_err("unable to find nfc node in device tree\n");
-		goto err;
-	}
+	nfc->regs = dev_read_addr_ptr(dev);
+	if (!nfc->regs)
+		return -EINVAL;
 
-	if (!fdtdec_get_is_enabled(blob, node)) {
-		pr_err("nfc disabled in device tree\n");
-		goto err;
-	}
+	ret = reset_get_bulk(dev, &rst_bulk);
+	if (!ret)
+		reset_deassert_bulk(&rst_bulk);
 
-	regs = fdtdec_get_addr(blob, node, "reg");
-	if (regs == FDT_ADDR_T_NONE) {
-		pr_err("unable to find nfc address in device tree\n");
-		goto err;
-	}
-
-	nfc->regs = (void *)regs;
+	ret = clk_get_bulk(dev, &clk_bulk);
+	if (!ret)
+		clk_enable_bulk(&clk_bulk);
 
 	ret = sunxi_nfc_rst(nfc);
 	if (ret)
-		goto err;
+		return ret;
 
-	ret = sunxi_nand_chips_init(node, nfc);
+	ret = sunxi_nand_chips_init(dev, nfc);
 	if (ret) {
-		dev_err(nfc->dev, "failed to init nand chips\n");
-		goto err;
+		dev_err(dev, "failed to init nand chips\n");
+		return ret;
 	}
 
-	return;
+	return 0;
+}
 
-err:
-	kfree(nfc);
+static const struct udevice_id sunxi_nand_ids[] = {
+	{
+		.compatible = "allwinner,sun4i-a10-nand",
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(sunxi_nand) = {
+	.name		= "sunxi_nand",
+	.id		= UCLASS_MTD,
+	.of_match	= sunxi_nand_ids,
+	.probe		= sunxi_nand_probe,
+	.priv_auto	= sizeof(struct sunxi_nfc),
+};
+
+void board_nand_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_MTD,
+					  DM_DRIVER_GET(sunxi_nand), &dev);
+	if (ret && ret != -ENODEV)
+		pr_err("Failed to initialize sunxi NAND controller: %d\n", ret);
 }
 
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/mtd/nvmxip/Kconfig b/drivers/mtd/nvmxip/Kconfig
new file mode 100644
index 0000000..3ef7105
--- /dev/null
+++ b/drivers/mtd/nvmxip/Kconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# Authors:
+#   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+
+config NVMXIP
+	bool "NVM XIP devices support"
+	select BLK
+	help
+	  This option allows the emulation of a block storage device
+	  on top of a direct access non volatile memory XIP flash devices.
+	  This support provides the read operation.
+
+config NVMXIP_QSPI
+	bool "QSPI XIP  support"
+	select NVMXIP
+	help
+	  This option allows the emulation of a block storage device on top of a QSPI XIP flash
diff --git a/drivers/mtd/nvmxip/Makefile b/drivers/mtd/nvmxip/Makefile
new file mode 100644
index 0000000..54eacc1
--- /dev/null
+++ b/drivers/mtd/nvmxip/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# Authors:
+#   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+
+obj-y += nvmxip-uclass.o nvmxip.o
+obj-$(CONFIG_NVMXIP_QSPI) += nvmxip_qspi.o
diff --git a/drivers/mtd/nvmxip/nvmxip-uclass.c b/drivers/mtd/nvmxip/nvmxip-uclass.c
new file mode 100644
index 0000000..6d8eb17
--- /dev/null
+++ b/drivers/mtd/nvmxip/nvmxip-uclass.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#if CONFIG_IS_ENABLED(SANDBOX64)
+#include <asm/test.h>
+#endif
+#include <linux/bitops.h>
+#include "nvmxip.h"
+
+/* LBA Macros */
+
+#define DEFAULT_LBA_SHIFT 10 /* 1024 bytes per block */
+#define DEFAULT_LBA_COUNT 1024 /* block count */
+
+#define DEFAULT_LBA_SZ BIT(DEFAULT_LBA_SHIFT)
+
+/**
+ * nvmxip_post_bind() - post binding treatments
+ * @dev:	the NVMXIP device
+ *
+ * Create and probe a child block device.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int nvmxip_post_bind(struct udevice *udev)
+{
+	int ret;
+	struct udevice *bdev = NULL;
+	char bdev_name[NVMXIP_BLKDEV_NAME_SZ + 1];
+	int devnum;
+
+#if CONFIG_IS_ENABLED(SANDBOX64)
+	sandbox_set_enable_memio(true);
+#endif
+
+	devnum = uclass_id_count(UCLASS_NVMXIP);
+	snprintf(bdev_name, NVMXIP_BLKDEV_NAME_SZ, "blk#%d", devnum);
+
+	ret = blk_create_devicef(udev, NVMXIP_BLKDRV_NAME, bdev_name, UCLASS_NVMXIP,
+				 devnum, DEFAULT_LBA_SZ,
+				 DEFAULT_LBA_COUNT, &bdev);
+	if (ret) {
+		log_err("[%s]: failure during creation of the block device %s, error %d\n",
+			udev->name, bdev_name, ret);
+		return ret;
+	}
+
+	ret = blk_probe_or_unbind(bdev);
+	if (ret) {
+		log_err("[%s]: failure during probing the block device %s, error %d\n",
+			udev->name, bdev_name, ret);
+		return ret;
+	}
+
+	log_info("[%s]: the block device %s ready for use\n", udev->name, bdev_name);
+
+	return 0;
+}
+
+UCLASS_DRIVER(nvmxip) = {
+	.name	   = "nvmxip",
+	.id	   = UCLASS_NVMXIP,
+	.post_bind = nvmxip_post_bind,
+};
diff --git a/drivers/mtd/nvmxip/nvmxip.c b/drivers/mtd/nvmxip/nvmxip.c
new file mode 100644
index 0000000..a359e3b
--- /dev/null
+++ b/drivers/mtd/nvmxip/nvmxip.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <mapmem.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include "nvmxip.h"
+
+/**
+ * nvmxip_mmio_rawread() - read from the XIP flash
+ * @address:	address of the data
+ * @value:	pointer to where storing the value read
+ *
+ * Read raw data from the XIP flash.
+ *
+ * Return:
+ *
+ * Always return 0.
+ */
+static int nvmxip_mmio_rawread(const phys_addr_t address, u64 *value)
+{
+	*value = readq(address);
+	return 0;
+}
+
+/**
+ * nvmxip_blk_read() - block device read operation
+ * @dev:	the block device
+ * @blknr:	first block number to read from
+ * @blkcnt:	number of blocks to read
+ * @buffer:	destination buffer
+ *
+ * Read data from the block storage device.
+ *
+ * Return:
+ *
+ * number of blocks read on success. Otherwise, failure
+ */
+static ulong nvmxip_blk_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, void *buffer)
+{
+	struct nvmxip_plat *plat = dev_get_plat(dev->parent);
+	struct blk_desc *desc = dev_get_uclass_plat(dev);
+	/* number of the u64 words to read */
+	u32 qwords = (blkcnt * desc->blksz) / sizeof(u64);
+	/* physical address of the first block to read */
+	phys_addr_t blkaddr = plat->phys_base + blknr * desc->blksz;
+	u64 *virt_blkaddr;
+	u64 *pdst = buffer;
+	uint qdata_idx;
+
+	if (!pdst)
+		return -EINVAL;
+
+	log_debug("[%s]: reading from blknr: %lu , blkcnt: %lu\n", dev->name, blknr, blkcnt);
+
+	virt_blkaddr = map_sysmem(blkaddr, 0);
+
+	/* assumption: the data is virtually contiguous */
+
+	for (qdata_idx = 0 ; qdata_idx < qwords ; qdata_idx++)
+		nvmxip_mmio_rawread((phys_addr_t)(virt_blkaddr + qdata_idx), pdst++);
+
+	log_debug("[%s]:     src[0]: 0x%llx , dst[0]: 0x%llx , src[-1]: 0x%llx , dst[-1]: 0x%llx\n",
+		  dev->name,
+		  *virt_blkaddr,
+		  *(u64 *)buffer,
+		  *(u64 *)((u8 *)virt_blkaddr + desc->blksz * blkcnt - sizeof(u64)),
+		  *(u64 *)((u8 *)buffer + desc->blksz * blkcnt - sizeof(u64)));
+
+	unmap_sysmem(virt_blkaddr);
+
+	return blkcnt;
+}
+
+/**
+ * nvmxip_blk_probe() - block storage device probe
+ * @dev:	the block storage device
+ *
+ * Initialize the block storage descriptor.
+ *
+ * Return:
+ *
+ * Always return 0.
+ */
+static int nvmxip_blk_probe(struct udevice *dev)
+{
+	struct nvmxip_plat *plat = dev_get_plat(dev->parent);
+	struct blk_desc *desc = dev_get_uclass_plat(dev);
+
+	desc->lba = plat->lba;
+	desc->log2blksz = plat->lba_shift;
+	desc->blksz = BIT(plat->lba_shift);
+	desc->bdev = dev;
+
+	log_debug("[%s]: block storage layout\n    lbas: %lu , log2blksz: %d, blksz: %lu\n",
+		  dev->name, desc->lba, desc->log2blksz, desc->blksz);
+
+	return 0;
+}
+
+static const struct blk_ops nvmxip_blk_ops = {
+	.read	= nvmxip_blk_read,
+};
+
+U_BOOT_DRIVER(nvmxip_blk) = {
+	.name	= NVMXIP_BLKDRV_NAME,
+	.id	= UCLASS_BLK,
+	.probe	= nvmxip_blk_probe,
+	.ops	= &nvmxip_blk_ops,
+};
diff --git a/drivers/mtd/nvmxip/nvmxip.h b/drivers/mtd/nvmxip/nvmxip.h
new file mode 100644
index 0000000..f4ef377
--- /dev/null
+++ b/drivers/mtd/nvmxip/nvmxip.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#ifndef __DRIVER_NVMXIP_H__
+#define __DRIVER_NVMXIP_H__
+
+#include <blk.h>
+
+#define NVMXIP_BLKDRV_NAME    "nvmxip-blk"
+#define NVMXIP_BLKDEV_NAME_SZ 20
+
+/**
+ * struct nvmxip_plat - the NVMXIP driver plat
+ *
+ * @phys_base:	NVM XIP device base address
+ * @lba_shift:	block size shift count
+ * @lba:	number of blocks
+ *
+ * The NVMXIP information read from the DT.
+ */
+struct nvmxip_plat {
+	phys_addr_t phys_base;
+	u32 lba_shift;
+	lbaint_t lba;
+};
+
+#endif /* __DRIVER_NVMXIP_H__ */
diff --git a/drivers/mtd/nvmxip/nvmxip_qspi.c b/drivers/mtd/nvmxip/nvmxip_qspi.c
new file mode 100644
index 0000000..7221fd1
--- /dev/null
+++ b/drivers/mtd/nvmxip/nvmxip_qspi.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <linux/errno.h>
+#include "nvmxip.h"
+
+#include <asm/global_data.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define NVMXIP_QSPI_DRV_NAME "nvmxip_qspi"
+
+/**
+ * nvmxip_qspi_of_to_plat() -read from DT
+ * @dev:	the NVMXIP device
+ *
+ * Read from the DT the NVMXIP information.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int nvmxip_qspi_of_to_plat(struct udevice *dev)
+{
+	struct nvmxip_plat *plat = dev_get_plat(dev);
+	int ret;
+
+	plat->phys_base = (phys_addr_t)dev_read_addr(dev);
+	if (plat->phys_base == FDT_ADDR_T_NONE) {
+		log_err("[%s]: can not get base address from device tree\n", dev->name);
+		return -EINVAL;
+	}
+
+	ret = dev_read_u32(dev, "lba_shift", &plat->lba_shift);
+	if (ret) {
+		log_err("[%s]: can not get lba_shift from device tree\n", dev->name);
+		return -EINVAL;
+	}
+
+	ret = dev_read_u32(dev, "lba", (u32 *)&plat->lba);
+	if (ret) {
+		log_err("[%s]: can not get lba from device tree\n", dev->name);
+		return -EINVAL;
+	}
+
+	log_debug("[%s]: XIP device base addr: 0x%llx , lba_shift: %d , lbas: %lu\n",
+		  dev->name, plat->phys_base, plat->lba_shift, plat->lba);
+
+	return 0;
+}
+
+static const struct udevice_id nvmxip_qspi_ids[] = {
+	{ .compatible = "nvmxip,qspi" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(nvmxip_qspi) = {
+	.name = NVMXIP_QSPI_DRV_NAME,
+	.id = UCLASS_NVMXIP,
+	.of_match = nvmxip_qspi_ids,
+	.of_to_plat = nvmxip_qspi_of_to_plat,
+	.plat_auto = sizeof(struct nvmxip_plat),
+};
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index 3c01e3b..4fe5471 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -248,6 +248,7 @@
 		break;
 	case SPINOR_OP_READ_FAST:
 		sbsf->pad_addr_bytes = 1;
+		fallthrough;
 	case SPINOR_OP_READ:
 	case SPINOR_OP_PP:
 		sbsf->state = SF_ADDR;
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 2c3116e..6093277 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -669,6 +669,7 @@
 	case SNOR_MFR_MICRON:
 		/* Some Micron need WREN command; all will accept it */
 		need_wren = true;
+		fallthrough;
 	case SNOR_MFR_ISSI:
 	case SNOR_MFR_MACRONIX:
 	case SNOR_MFR_WINBOND:
@@ -903,6 +904,30 @@
 }
 #endif
 
+/**
+ * spi_nor_erase_chip() - Erase the entire flash memory.
+ * @nor:	pointer to 'struct spi_nor'.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_erase_chip(struct spi_nor *nor)
+{
+	struct spi_mem_op op =
+		SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 0),
+			   SPI_MEM_OP_NO_ADDR,
+			   SPI_MEM_OP_NO_DUMMY,
+			   SPI_MEM_OP_NO_DATA);
+	int ret;
+
+	spi_nor_setup_op(nor, &op, nor->write_proto);
+
+	ret = spi_mem_exec_op(nor->spi, &op);
+	if (ret)
+		return ret;
+
+	return nor->mtd.size;
+}
+
 /*
  * Initiate the erasure of a single sector. Returns the number of bytes erased
  * on success, a negative error code on error.
@@ -974,7 +999,12 @@
 		if (ret < 0)
 			goto erase_err;
 
-		ret = spi_nor_erase_sector(nor, addr);
+		if (len == mtd->size &&
+		    !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
+			ret = spi_nor_erase_chip(nor);
+		} else {
+			ret = spi_nor_erase_sector(nor, addr);
+		}
 		if (ret < 0)
 			goto erase_err;
 
@@ -3199,6 +3229,87 @@
 /* Use ID byte 4 to distinguish S25FS256T and S25Hx-T */
 #define S25FS256T_ID4	(0x08)
 
+/* Number of dummy cycle for Read Any Register (RDAR) op. */
+#define S25FS_S_RDAR_DUMMY	8
+
+static int s25fs_s_quad_enable(struct spi_nor *nor)
+{
+	return spansion_quad_enable_volatile(nor, 0, S25FS_S_RDAR_DUMMY);
+}
+
+static int s25fs_s_erase_non_uniform(struct spi_nor *nor, loff_t addr)
+{
+	/* Support 8 x 4KB sectors at bottom */
+	return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0, SZ_32K);
+}
+
+static int s25fs_s_setup(struct spi_nor *nor, const struct flash_info *info,
+			 const struct spi_nor_flash_parameter *params)
+{
+	int ret;
+	u8 cfr3v;
+
+	/* Bank Address Register is not supported */
+	if (CONFIG_IS_ENABLED(SPI_FLASH_BAR))
+		return -EOPNOTSUPP;
+
+	/*
+	 * Read CR3V to check if uniform sector is selected. If not, assign an
+	 * erase hook that supports non-uniform erase.
+	 */
+	ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V,
+				    S25FS_S_RDAR_DUMMY, &cfr3v);
+	if (ret)
+		return ret;
+	if (!(cfr3v & CFR3V_UNHYSA))
+		nor->erase = s25fs_s_erase_non_uniform;
+
+	return spi_nor_default_setup(nor, info, params);
+}
+
+static void s25fs_s_default_init(struct spi_nor *nor)
+{
+	nor->setup = s25fs_s_setup;
+}
+
+static int s25fs_s_post_bfpt_fixup(struct spi_nor *nor,
+				   const struct sfdp_parameter_header *header,
+				   const struct sfdp_bfpt *bfpt,
+				   struct spi_nor_flash_parameter *params)
+{
+	/* The erase size is set to 4K from BFPT, but it's wrong. Fix it. */
+	nor->erase_opcode = SPINOR_OP_SE;
+	nor->mtd.erasesize = nor->info->sector_size;
+
+	/* The S25FS-S chip family reports 512-byte pages in BFPT but
+	 * in reality the write buffer still wraps at the safe default
+	 * of 256 bytes.  Overwrite the page size advertised by BFPT
+	 * to get the writes working.
+	 */
+	params->page_size = 256;
+
+	return 0;
+}
+
+static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor,
+				    struct spi_nor_flash_parameter *params)
+{
+	/* READ_1_1_2 is not supported */
+	params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2;
+	/* READ_1_1_4 is not supported */
+	params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4;
+	/* PP_1_1_4 is not supported */
+	params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4;
+	/* Use volatile register to enable quad */
+	params->quad_enable = s25fs_s_quad_enable;
+}
+
+static struct spi_nor_fixups s25fs_s_fixups = {
+	.default_init = s25fs_s_default_init,
+	.post_bfpt = s25fs_s_post_bfpt_fixup,
+	.post_sfdp = s25fs_s_post_sfdp_fixup,
+};
+
 static int s25_mdp_ready(struct spi_nor *nor)
 {
 	u32 addr;
@@ -3897,6 +4008,10 @@
 	if (CONFIG_IS_ENABLED(SPI_FLASH_BAR) &&
 	    !strcmp(nor->info->name, "s25fl256l"))
 		nor->fixups = &s25fl256l_fixups;
+
+	/* For FS-S (family ID = 0x81)  */
+	if (JEDEC_MFR(nor->info) == SNOR_MFR_SPANSION && nor->info->id[5] == 0x81)
+		nor->fixups = &s25fs_s_fixups;
 #endif
 
 #ifdef CONFIG_SPI_FLASH_MT35XU
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 14fd3bb..0123036 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -580,10 +580,6 @@
 		break;
 #endif
 
-	case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
-		debug("PCI AutoConfig: Found PowerPC device\n");
-		/* fall through */
-
 	default:
 		dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
 		break;
diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c
index 8a81a74..249cfe6 100644
--- a/drivers/pci/pci_mpc85xx.c
+++ b/drivers/pci/pci_mpc85xx.c
@@ -22,10 +22,33 @@
 	struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
 	u32 addr;
 
-	addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
+	if (offset > 0xff) {
+		*value = pci_get_ff(size);
+		return 0;
+	}
+
+	/* Skip mpc85xx PCI controller's ATMU inbound registers */
+	if (PCI_BUS(bdf) == 0 && PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+	    (offset & ~3) >= PCI_BASE_ADDRESS_0 && (offset & ~3) <= PCI_BASE_ADDRESS_5) {
+		*value = 0;
+		return 0;
+	}
+
+	addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
 	out_be32(priv->cfg_addr, addr);
 	sync();
-	*value = pci_conv_32_to_size(in_le32(priv->cfg_data), offset, size);
+
+	switch (size) {
+	case PCI_SIZE_8:
+		*value = in_8(priv->cfg_data + (offset & 3));
+		break;
+	case PCI_SIZE_16:
+		*value = in_le16(priv->cfg_data + (offset & 2));
+		break;
+	case PCI_SIZE_32:
+		*value = in_le32(priv->cfg_data);
+		break;
+	}
 
 	return 0;
 }
@@ -37,10 +60,30 @@
 	struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
 	u32 addr;
 
-	addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
+	if (offset > 0xff)
+		return 0;
+
+	/* Skip mpc85xx PCI controller's ATMU inbound registers */
+	if (PCI_BUS(bdf) == 0 && PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+	    (offset & ~3) >= PCI_BASE_ADDRESS_0 && (offset & ~3) <= PCI_BASE_ADDRESS_5)
+		return 0;
+
+	addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
 	out_be32(priv->cfg_addr, addr);
 	sync();
+
+	switch (size) {
+	case PCI_SIZE_8:
+		out_8(priv->cfg_data + (offset & 3), value);
+		break;
+	case PCI_SIZE_16:
+		out_le16(priv->cfg_data + (offset & 2), value);
+		break;
+	case PCI_SIZE_32:
+		out_le32(priv->cfg_data, value);
+		break;
+	}
+	sync();
-	out_le32(priv->cfg_data, pci_conv_size_to_32(0, value, offset, size));
 
 	return 0;
 }
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 4600652..8d89a1e 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -58,6 +58,14 @@
 		return 0;
 	}
 
+	/* Skip Freescale PCIe controller's PEXCSRBAR register */
+	if (PCI_BUS(bdf) - dev_seq(bus) == 0 &&
+	    PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+	    (offset & ~3) == PCI_BASE_ADDRESS_0) {
+		*valuep = 0;
+		return 0;
+	}
+
 	val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus),
 				    PCI_DEV(bdf), PCI_FUNC(bdf),
 				    offset);
@@ -95,6 +103,12 @@
 	if (fsl_pcie_addr_valid(pcie, bdf))
 		return 0;
 
+	/* Skip Freescale PCIe controller's PEXCSRBAR register */
+	if (PCI_BUS(bdf) - dev_seq(bus) == 0 &&
+	    PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+	    (offset & ~3) == PCI_BASE_ADDRESS_0)
+		return 0;
+
 	val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus),
 				    PCI_DEV(bdf), PCI_FUNC(bdf),
 				    offset);
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index 17969e2..6a5bf88 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -403,6 +403,7 @@
 static const struct udevice_id ls_pcie_ids[] = {
 	{ .compatible = "fsl,ls-pcie" },
 	{ .compatible = "fsl,ls1028a-pcie", .data = (ulong)&ls1028a_drvdata },
+	{ .compatible = "fsl,ls1088a-pcie", .data = (ulong)&ls1028a_drvdata },
 	{ }
 };
 
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 2e969ab..6428163 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -224,6 +224,12 @@
 		initial_usb_scan_delay = 0;
 	}
 
+	/* For phy0 only turn on Vbus if we don't have an ext. Vbus */
+	if (phy->id == 0 && sun4i_usb_phy_vbus_detect(phy)) {
+		dev_warn(phy->dev, "External vbus detected, not enabling our own vbus\n");
+		return 0;
+	}
+
 	if (dm_gpio_is_valid(&usb_phy->gpio_vbus))
 		dm_gpio_set_value(&usb_phy->gpio_vbus, 1);
 
diff --git a/drivers/phy/phy-ti-am654.c b/drivers/phy/phy-ti-am654.c
index 27a3122..70a746d 100644
--- a/drivers/phy/phy-ti-am654.c
+++ b/drivers/phy/phy-ti-am654.c
@@ -16,7 +16,6 @@
 #include <dt-bindings/phy/phy.h>
 #include <generic-phy.h>
 #include <asm/io.h>
-#include <asm/arch/sys_proto.h>
 #include <power-domain.h>
 #include <regmap.h>
 #include <syscon.h>
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 47e2d67..5a4d58b 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -349,10 +349,10 @@
 {
 	int err;
 
-	/* try pupd_r1_r0 if pullen_pullsel return error */
+	/* set pupd_r1_r0 if pullen_pullsel succeeded */
 	err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup,
 						  val);
-	if (err)
+	if (!err)
 		return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable,
 						       pullup, val);
 
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index c4fbda7..e510218 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -269,6 +269,7 @@
 #endif
 	{ "mmc2",	3 },	/* PC6-PC15 */
 	{ "mmc3",	2 },	/* PI4-PI9 */
+	{ "nand0",	2 },	/* PC0-PC24 */
 	{ "spi0",	3 },	/* PC0-PC2, PC23 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	4 },	/* PF2-PF4 */
@@ -293,6 +294,7 @@
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG3-PG8 */
 	{ "mmc2",	3 },	/* PC6-PC15 */
+	{ "nand0",	2 },	/* PC0-PC19 */
 	{ "spi0",	3 },	/* PC0-PC3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	4 },	/* PF2-PF4 */
@@ -319,6 +321,7 @@
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC6-PC15, PC24 */
 	{ "mmc3",	4 },	/* PC6-PC15, PC24 */
+	{ "nand0",	2 },	/* PC0-PC26 */
 	{ "spi0",	3 },	/* PC0-PC2, PC27 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
@@ -363,6 +366,7 @@
 	{ "mmc1",	4 },	/* PG0-PG5 */
 #endif
 	{ "mmc2",	3 },	/* PC5-PC15, PC24 */
+	{ "nand0",	2 },	/* PC0-PC24 */
 	{ "spi0",	3 },	/* PC0-PC2, PC23 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	4 },	/* PF2-PF4 */
@@ -386,6 +390,7 @@
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC5-PC16 */
+	{ "nand0",	2 },	/* PC0-PC16 */
 	{ "spi0",	3 },	/* PC0-PC3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
@@ -424,6 +429,7 @@
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC5-PC16 */
+	{ "nand0",	2 },	/* PC0-PC16 */
 	{ "spi0",	3 },	/* PC0-PC3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
@@ -450,6 +456,7 @@
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC5-PC16 */
+	{ "nand0",	2 },	/* PC0-PC18 */
 	{ "spi0",	3 },	/* PC0-PC3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
@@ -491,6 +498,7 @@
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC5-PC16 */
+	{ "nand0",	2 },	/* PC0-PC16 */
 	{ "spi0",	3 },	/* PC0-PC3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
@@ -557,6 +565,7 @@
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC6-PC16 */
+	{ "nand0",	2 },	/* PC0-PC18 */
 	{ "spi0",	3 },	/* PC0-PC2, PC19 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	4 },	/* PF2-PF4 */
@@ -597,6 +606,7 @@
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC1-PC16 */
+	{ "nand0",	2 },	/* PC0-PC16 */
 	{ "pwm",	2 },	/* PD22 */
 	{ "spi0",	4 },	/* PC0-PC3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
@@ -639,6 +649,7 @@
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC1-PC16 */
+	{ "nand0",	2 },	/* PC0-PC16 */
 	{ "spi0",	3 },	/* PC0-PC3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
@@ -665,6 +676,7 @@
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC1-PC14 */
+	{ "nand0",	2 },	/* PC0-PC16 */
 	{ "spi0",	4 },	/* PC0-PC7 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
@@ -703,6 +715,7 @@
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC0-PC16 */
+	{ "nand0",	2 },	/* PC0-PC16 */
 	{ "spi0",	4 },	/* PC0-PC7, PC15-PC16 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index c346d03..eb5aa38 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -57,6 +57,13 @@
 	  Enable support in SPL for the regulators (DCDCs, LDOs) in the
 	  X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
 
+config REGULATOR_AXP_USB_POWER
+	bool "Enable driver for X-Powers AXP PMIC USB power supply"
+	depends on DM_REGULATOR && PMIC_AXP
+	help
+	  Enable support for reading the USB power supply status from
+	  X-Powers AXP2xx and AXP8xx PMICs.
+
 config DM_REGULATOR_BD71837
 	bool "Enable Driver Model for ROHM BD71837/BD71847 regulators"
 	depends on DM_REGULATOR && DM_PMIC_BD71837
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 2d97e10..d9e0cd5 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -8,6 +8,7 @@
 obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
 obj-$(CONFIG_REGULATOR_AS3722)	+= as3722_regulator.o
 obj-$(CONFIG_$(SPL_)REGULATOR_AXP) += axp_regulator.o
+obj-$(CONFIG_$(SPL_)REGULATOR_AXP_USB_POWER) += axp_usb_power.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_DA9063) += da9063.o
 obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
 obj-$(CONFIG_DM_REGULATOR_NPCM8XX) += npcm8xx_regulator.o
diff --git a/drivers/power/regulator/axp_usb_power.c b/drivers/power/regulator/axp_usb_power.c
new file mode 100644
index 0000000..f32fb6a
--- /dev/null
+++ b/drivers/power/regulator/axp_usb_power.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <dm/device.h>
+#include <errno.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+
+#define AXP_POWER_STATUS		0x00
+#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
+
+static int axp_usb_power_get_enable(struct udevice *dev)
+{
+	int ret;
+
+	ret = pmic_reg_read(dev->parent, AXP_POWER_STATUS);
+	if (ret < 0)
+		return ret;
+
+	return !!(ret & AXP_POWER_STATUS_VBUS_PRESENT);
+}
+
+static const struct dm_regulator_ops axp_usb_power_ops = {
+	.get_enable		= axp_usb_power_get_enable,
+};
+
+static int axp_usb_power_probe(struct udevice *dev)
+{
+	struct dm_regulator_uclass_plat *uc_plat = dev_get_uclass_plat(dev);
+
+	uc_plat->type = REGULATOR_TYPE_FIXED;
+
+	return 0;
+}
+
+static const struct udevice_id axp_usb_power_ids[] = {
+	{ .compatible = "x-powers,axp202-usb-power-supply" },
+	{ .compatible = "x-powers,axp221-usb-power-supply" },
+	{ .compatible = "x-powers,axp223-usb-power-supply" },
+	{ .compatible = "x-powers,axp813-usb-power-supply" },
+	{ }
+};
+
+U_BOOT_DRIVER(axp_usb_power) = {
+	.name		= "axp_usb_power",
+	.id		= UCLASS_REGULATOR,
+	.of_match	= axp_usb_power_ids,
+	.probe		= axp_usb_power_probe,
+	.ops		= &axp_usb_power_ops,
+};
diff --git a/drivers/ram/k3-am654-ddrss.c b/drivers/ram/k3-am654-ddrss.c
index 4453c24..b8338f8 100644
--- a/drivers/ram/k3-am654-ddrss.c
+++ b/drivers/ram/k3-am654-ddrss.c
@@ -13,11 +13,14 @@
 #include <ram.h>
 #include <asm/io.h>
 #include <power-domain.h>
-#include <asm/arch/sys_proto.h>
 #include <dm/device_compat.h>
 #include <power/regulator.h>
 #include "k3-am654-ddrss.h"
 
+void sdelay(unsigned long loops);
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
+		  u32 bound);
+
 #define LDELAY 10000
 
 /* DDRSS PHY configuration register fixed values */
diff --git a/drivers/remoteproc/ti_k3_arm64_rproc.c b/drivers/remoteproc/ti_k3_arm64_rproc.c
index 1f2415d..99f1100 100644
--- a/drivers/remoteproc/ti_k3_arm64_rproc.c
+++ b/drivers/remoteproc/ti_k3_arm64_rproc.c
@@ -36,6 +36,8 @@
  * @gtc_base:		Timer base address.
  */
 struct k3_arm64_privdata {
+	bool has_cluster_node;
+	struct power_domain cluster_pwrdmn;
 	struct power_domain rproc_pwrdmn;
 	struct power_domain gtc_pwrdmn;
 	struct reset_ctl rproc_rst;
@@ -55,6 +57,7 @@
 static int k3_arm64_load(struct udevice *dev, ulong addr, ulong size)
 {
 	struct k3_arm64_privdata *rproc = dev_get_priv(dev);
+	ulong gtc_rate;
 	int ret;
 
 	dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size);
@@ -64,26 +67,10 @@
 	if (ret)
 		return ret;
 
-	return ti_sci_proc_set_config(&rproc->tsp, addr, 0, 0);
-}
-
-/**
- * k3_arm64_start() - Start the remote processor
- * @dev:	rproc device pointer
- *
- * Return: 0 if all went ok, else return appropriate error
- */
-static int k3_arm64_start(struct udevice *dev)
-{
-	struct k3_arm64_privdata *rproc = dev_get_priv(dev);
-	ulong gtc_rate;
-	int ret;
-
-	dev_dbg(dev, "%s\n", __func__);
-
 	ret = power_domain_on(&rproc->gtc_pwrdmn);
 	if (ret) {
-		dev_err(dev, "power_domain_on() failed: %d\n", ret);
+		dev_err(dev, "power_domain_on(&rproc->gtc_pwrdmn) failed: %d\n",
+			ret);
 		return ret;
 	}
 
@@ -100,9 +87,36 @@
 	 * assigned-clock-rates during the device probe. So no need to
 	 * set the frequency again here.
 	 */
+	if (rproc->has_cluster_node) {
+		ret = power_domain_on(&rproc->cluster_pwrdmn);
+		if (ret) {
+			dev_err(dev,
+				"power_domain_on(&rproc->cluster_pwrdmn) failed: %d\n",
+				ret);
+			return ret;
+		}
+	}
+
+	return ti_sci_proc_set_config(&rproc->tsp, addr, 0, 0);
+}
+
+/**
+ * k3_arm64_start() - Start the remote processor
+ * @dev:	rproc device pointer
+ *
+ * Return: 0 if all went ok, else return appropriate error
+ */
+static int k3_arm64_start(struct udevice *dev)
+{
+	struct k3_arm64_privdata *rproc = dev_get_priv(dev);
+	int ret;
+
+	dev_dbg(dev, "%s\n", __func__);
 	ret = power_domain_on(&rproc->rproc_pwrdmn);
 	if (ret) {
-		dev_err(dev, "power_domain_on() failed: %d\n", ret);
+		dev_err(dev,
+			"power_domain_on(&rproc->rproc_pwrdmn) failed: %d\n",
+			ret);
 		return ret;
 	}
 
@@ -166,9 +180,17 @@
 
 	dev_dbg(dev, "%s\n", __func__);
 
+	/* Cluster needs to be powered on if firewalls are being configured */
+	rproc->has_cluster_node = true;
+	ret = power_domain_get_by_index(dev, &rproc->cluster_pwrdmn, 2);
+	if (ret) {
+		dev_dbg(dev, "warning: power_domain_get_cluster() failed: %d\n", ret);
+		rproc->has_cluster_node = false;
+	}
+
 	ret = power_domain_get_by_index(dev, &rproc->rproc_pwrdmn, 1);
 	if (ret) {
-		dev_err(dev, "power_domain_get() failed: %d\n", ret);
+		dev_err(dev, "power_domain_get_rproc() failed: %d\n", ret);
 		return ret;
 	}
 
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 10d07da..7faf678 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -946,6 +946,8 @@
 
 config MSM_GENI_SERIAL
 	bool "Qualcomm on-chip GENI UART"
+	select MISC
+	imply QCOM_GENI_SE
 	help
 	  Support UART based on Generic Interface (GENI) Serial Engine (SE),
 	  used on Qualcomm Snapdragon SoCs. Should support all qualcomm SOCs
diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index 3943ca4..78fd938 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -11,15 +11,10 @@
 #include <clk.h>
 #include <common.h>
 #include <dm.h>
-#include <dm/pinctrl.h>
 #include <errno.h>
-#include <linux/compiler.h>
-#include <log.h>
 #include <linux/delay.h>
-#include <malloc.h>
+#include <misc.h>
 #include <serial.h>
-#include <watchdog.h>
-#include <linux/bug.h>
 
 #define UART_OVERSAMPLING	32
 #define STALE_TIMEOUT	160
@@ -116,6 +111,10 @@
 #define TX_FIFO_DEPTH_MSK	(GENMASK(21, 16))
 #define TX_FIFO_DEPTH_SHFT	16
 
+/* GENI SE QUP Registers */
+#define QUP_HW_VER_REG		0x4
+#define  QUP_SE_VERSION_2_5	0x20050000
+
 /*
  * Predefined packing configuration of the serial engine (CFG0, CFG1 regs)
  * for uart mode.
@@ -133,11 +132,12 @@
 struct msm_serial_data {
 	phys_addr_t base;
 	u32 baud;
+	u32 oversampling;
 };
 
 unsigned long root_freq[] = {7372800,  14745600, 19200000, 29491200,
-					 32000000, 48000000, 64000000, 80000000,
-					 96000000, 100000000};
+			     32000000, 48000000, 64000000, 80000000,
+			     96000000, 100000000};
 
 /**
  * get_clk_cfg() - Get clock rate to apply on clock supplier.
@@ -166,8 +166,7 @@
  *
  * Return: frequency, supported by clock supplier, multiple of clk_freq.
  */
-static int get_clk_div_rate(u32 baud,
-							u64 sampling_rate, u32 *clk_div)
+static int get_clk_div_rate(u32 baud, u64 sampling_rate, u32 *clk_div)
 {
 	unsigned long ser_clk;
 	unsigned long desired_clk;
@@ -189,7 +188,7 @@
 	struct clk *clk;
 	int ret;
 
-	clk = devm_clk_get(dev, "se-clk");
+	clk = devm_clk_get(dev, NULL);
 	if (!clk)
 		return -EINVAL;
 
@@ -234,7 +233,7 @@
 }
 
 static inline void geni_serial_baud(phys_addr_t base_address, u32 clk_div,
-									int baud)
+				    int baud)
 {
 	u32 s_clk_cfg = 0;
 
@@ -245,15 +244,15 @@
 	writel(s_clk_cfg, base_address + GENI_SER_S_CLK_CFG);
 }
 
-int msm_serial_setbrg(struct udevice *dev, int baud)
+static int msm_serial_setbrg(struct udevice *dev, int baud)
 {
 	struct msm_serial_data *priv = dev_get_priv(dev);
+	u64 clk_rate;
+	u32 clk_div;
 
 	priv->baud = baud;
-	u32 clk_div;
-	u64 clk_rate;
 
-	clk_rate = get_clk_div_rate(baud, UART_OVERSAMPLING, &clk_div);
+	clk_rate = get_clk_div_rate(baud, priv->oversampling, &clk_div);
 	geni_serial_set_clock_rate(dev, clk_rate);
 	geni_serial_baud(priv->base, clk_div, baud);
 
@@ -274,7 +273,7 @@
  * reached.
  */
 static bool qcom_geni_serial_poll_bit(const struct udevice *dev, int offset,
-					  int field, bool set)
+				      int field, bool set)
 {
 	u32 reg;
 	struct msm_serial_data *priv = dev_get_priv(dev);
@@ -487,6 +486,31 @@
 	.setbrg = msm_serial_setbrg,
 };
 
+static void geni_set_oversampling(struct udevice *dev)
+{
+	struct msm_serial_data *priv = dev_get_priv(dev);
+	struct udevice *parent_dev = dev_get_parent(dev);
+	u32 geni_se_version;
+	int ret;
+
+	priv->oversampling = UART_OVERSAMPLING;
+
+	/*
+	 * It could happen that GENI SE IP is missing in the board's device
+	 * tree or GENI UART node is a direct child of SoC device tree node.
+	 */
+	if (device_get_uclass_id(parent_dev) != UCLASS_MISC)
+		return;
+
+	ret = misc_read(parent_dev, QUP_HW_VER_REG,
+			&geni_se_version, sizeof(geni_se_version));
+	if (ret != sizeof(geni_se_version))
+		return;
+
+	if (geni_se_version >= QUP_SE_VERSION_2_5)
+		priv->oversampling /= 2;
+}
+
 static inline void geni_serial_init(struct udevice *dev)
 {
 	struct msm_serial_data *priv = dev_get_priv(dev);
@@ -530,6 +554,8 @@
 {
 	struct msm_serial_data *priv = dev_get_priv(dev);
 
+	geni_set_oversampling(dev);
+
 	/* No need to reinitialize the UART after relocation */
 	if (gd->flags & GD_FLG_RELOC)
 		return 0;
@@ -554,7 +580,9 @@
 }
 
 static const struct udevice_id msm_serial_ids[] = {
-	{.compatible = "qcom,msm-geni-uart"}, {}};
+	{ .compatible = "qcom,geni-debug-uart" },
+	{ }
+};
 
 U_BOOT_DRIVER(serial_msm_geni) = {
 	.name = "serial_msm_geni",
@@ -564,6 +592,7 @@
 	.priv_auto = sizeof(struct msm_serial_data),
 	.probe = msm_serial_probe,
 	.ops = &msm_serial_ops,
+	.flags = DM_FLAG_PRE_RELOC,
 };
 
 #ifdef CONFIG_DEBUG_UART_MSM_GENI
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index acf555b..85dac9d 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -10,7 +10,7 @@
 	  specific device variant in use.
 
 config SOC_DEVICE_TI_K3
-	depends on SOC_DEVICE
+	depends on SOC_DEVICE && ARCH_K3
 	bool "Enable SoC Device ID driver for TI K3 SoCs"
 	help
 	  This allows Texas Instruments Keystone 3 SoCs to identify
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index 8af0ac7..b720131 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -8,21 +8,9 @@
 #include <dm.h>
 #include <soc.h>
 
+#include <asm/arch/hardware.h>
 #include <asm/io.h>
 
-#define AM65X			0xbb5a
-#define J721E			0xbb64
-#define J7200			0xbb6d
-#define AM64X			0xbb38
-#define J721S2			0xbb75
-#define AM62X			0xbb7e
-#define AM62AX			0xbb8d
-
-#define JTAG_ID_VARIANT_SHIFT	28
-#define JTAG_ID_VARIANT_MASK	(0xf << 28)
-#define JTAG_ID_PARTNO_SHIFT	12
-#define JTAG_ID_PARTNO_MASK	(0xffff << 12)
-
 struct soc_ti_k3_plat {
 	const char *family;
 	const char *revision;
@@ -36,25 +24,25 @@
 	soc = (idreg & JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
 
 	switch (soc) {
-	case AM65X:
+	case JTAG_ID_PARTNO_AM65X:
 		family = "AM65X";
 		break;
-	case J721E:
+	case JTAG_ID_PARTNO_J721E:
 		family = "J721E";
 		break;
-	case J7200:
+	case JTAG_ID_PARTNO_J7200:
 		family = "J7200";
 		break;
-	case AM64X:
+	case JTAG_ID_PARTNO_AM64X:
 		family = "AM64X";
 		break;
-	case J721S2:
+	case JTAG_ID_PARTNO_J721S2:
 		family = "J721S2";
 		break;
-	case AM62X:
+	case JTAG_ID_PARTNO_AM62X:
 		family = "AM62X";
 		break;
-	case AM62AX:
+	case JTAG_ID_PARTNO_AM62AX:
 		family = "AM62AX";
 		break;
 	default:
@@ -81,13 +69,13 @@
 	soc = (idreg & JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
 
 	switch (soc) {
-	case J721E:
-		if (rev > ARRAY_SIZE(j721e_rev_string_map))
+	case JTAG_ID_PARTNO_J721E:
+		if (rev >= ARRAY_SIZE(j721e_rev_string_map))
 			goto bail;
 		return j721e_rev_string_map[rev];
 
 	default:
-		if (rev > ARRAY_SIZE(typical_rev_string_map))
+		if (rev >= ARRAY_SIZE(typical_rev_string_map))
 			goto bail;
 		return typical_rev_string_map[rev];
 	};
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index c7f10c5..f931e4c 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -312,13 +312,12 @@
 		 * which is unsupported on some flash devices during register
 		 * reads, prefer STIG mode for such small reads.
 		 */
-		if (!op->addr.nbytes ||
-		    op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
+		if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
 			mode = CQSPI_STIG_READ;
 		else
 			mode = CQSPI_READ;
 	} else {
-		if (!op->addr.nbytes || !op->data.buf.out)
+		if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
 			mode = CQSPI_STIG_WRITE;
 		else
 			mode = CQSPI_WRITE;
@@ -362,8 +361,15 @@
 {
 	bool all_true, all_false;
 
-	all_true = op->cmd.dtr && op->addr.dtr && op->dummy.dtr &&
-		   op->data.dtr;
+	/*
+	 * op->dummy.dtr is required for converting nbytes into ncycles.
+	 * Also, don't check the dtr field of the op phase having zero nbytes.
+	 */
+	all_true = op->cmd.dtr &&
+		   (!op->addr.nbytes || op->addr.dtr) &&
+		   (!op->dummy.nbytes || op->dummy.dtr) &&
+		   (!op->data.nbytes || op->data.dtr);
+
 	all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
 		    !op->data.dtr;
 
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 21fe2e6..9ce2c0f 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -120,7 +120,16 @@
 {
 	int ret;
 
-	priv->dtr = op->data.dtr && op->cmd.dtr && op->addr.dtr;
+	/*
+	 * For an op to be DTR, cmd phase along with every other non-empty
+	 * phase should have dtr field set to 1. If an op phase has zero
+	 * nbytes, ignore its dtr field; otherwise, check its dtr field.
+	 * Also, dummy checks not performed here Since supports_op()
+	 * already checks that all or none of the fields are DTR.
+	 */
+	priv->dtr = op->cmd.dtr &&
+		    (!op->addr.nbytes || op->addr.dtr) &&
+		    (!op->data.nbytes || op->data.dtr);
 
 	ret = cadence_qspi_buswidth_to_inst_type(op->cmd.buswidth);
 	if (ret < 0)
@@ -367,6 +376,9 @@
 	if (!cadence_qspi_wait_idle(reg_base))
 		return -EIO;
 
+	/* Flush the CMDCTRL reg after the execution */
+	writel(0, reg_base + CQSPI_REG_CMDCTRL);
+
 	return 0;
 }
 
@@ -453,11 +465,6 @@
 	unsigned int dummy_clk;
 	u8 opcode;
 
-	if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
-		printf("QSPI: Invalid input arguments rxlen %u\n", rxlen);
-		return -EINVAL;
-	}
-
 	if (priv->dtr)
 		opcode = op->cmd.opcode >> 8;
 	else
@@ -540,26 +547,12 @@
 	unsigned int reg = 0;
 	unsigned int wr_data;
 	unsigned int wr_len;
+	unsigned int dummy_clk;
 	unsigned int txlen = op->data.nbytes;
 	const void *txbuf = op->data.buf.out;
 	void *reg_base = priv->regbase;
-	u32 addr;
 	u8 opcode;
 
-	/* Reorder address to SPI bus order if only transferring address */
-	if (!txlen) {
-		addr = cpu_to_be32(op->addr.val);
-		if (op->addr.nbytes == 3)
-			addr >>= 8;
-		txbuf = &addr;
-		txlen = op->addr.nbytes;
-	}
-
-	if (txlen > CQSPI_STIG_DATA_LEN_MAX) {
-		printf("QSPI: Invalid input arguments txlen %u\n", txlen);
-		return -EINVAL;
-	}
-
 	if (priv->dtr)
 		opcode = op->cmd.opcode >> 8;
 	else
@@ -567,6 +560,27 @@
 
 	reg |= opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 
+	/* setup ADDR BIT field */
+	if (op->addr.nbytes) {
+		writel(op->addr.val, priv->regbase + CQSPI_REG_CMDADDRESS);
+		/*
+		 * address bytes are zero indexed
+		 */
+		reg |= (((op->addr.nbytes - 1) &
+			  CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) <<
+			  CQSPI_REG_CMDCTRL_ADD_BYTES_LSB);
+		reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
+	}
+
+	/* Set up dummy cycles. */
+	dummy_clk = cadence_qspi_calc_dummy(op, priv->dtr);
+	if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
+		return -EOPNOTSUPP;
+
+	if (dummy_clk)
+		reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
+		     << CQSPI_REG_CMDCTRL_DUMMY_LSB;
+
 	if (txlen) {
 		/* writing data = yes */
 		reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c
index 6869d60..7889217 100644
--- a/drivers/spi/mpc8xxx_spi.c
+++ b/drivers/spi/mpc8xxx_spi.c
@@ -16,6 +16,7 @@
 #include <dm/device_compat.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
+#include <asm/arch/soc.h>
 
 enum {
 	SPI_EV_NE = BIT(31 - 22),	/* Receiver Not Empty */
@@ -30,6 +31,7 @@
 	SPI_MODE_REV   = BIT(31 - 5),	/* Reverse mode - MSB first */
 	SPI_MODE_MS    = BIT(31 - 6),	/* Always master */
 	SPI_MODE_EN    = BIT(31 - 7),	/* Enable interface */
+	SPI_MODE_OP    = BIT(31 - 17),	/* CPU Mode, QE otherwise */
 
 	SPI_MODE_LEN_MASK = 0xf00000,
 	SPI_MODE_LEN_SHIFT = 20,
@@ -89,6 +91,9 @@
 	 */
 	out_be32(&priv->spi->mode, SPI_MODE_REV | SPI_MODE_MS);
 
+	if (dev_get_driver_data(dev) == SOC_MPC832X)
+		setbits_be32(&priv->spi->mode, SPI_MODE_OP);
+
 	/* set len to 8 bits */
 	setbits_be32(&spi->mode, (8 - 1) << SPI_MODE_LEN_SHIFT);
 
@@ -130,6 +135,7 @@
 	u32 tmpdin = 0, tmpdout = 0, n;
 	const u8 *cout = dout;
 	u8 *cin = din;
+	ulong type = dev_get_driver_data(bus);
 
 	debug("%s: slave %s:%u dout %08X din %08X bitlen %u\n", __func__,
 	      bus->name, plat->cs, (uint)dout, (uint)din, bitlen);
@@ -157,6 +163,9 @@
 		if (cout)
 			tmpdout = *cout++;
 
+		if (type == SOC_MPC832X)
+			tmpdout <<= 24;
+
 		/* Write the data out */
 		out_be32(&spi->tx, tmpdout);
 
@@ -179,6 +188,9 @@
 			tmpdin = in_be32(&spi->rx);
 			setbits_be32(&spi->event, SPI_EV_NE);
 
+			if (type == SOC_MPC832X)
+				tmpdin >>= 16;
+
 			if (cin)
 				*cin++ = tmpdin;
 
@@ -271,6 +283,7 @@
 
 static const struct udevice_id mpc8xxx_spi_ids[] = {
 	{ .compatible = "fsl,spi" },
+	{ .compatible = "fsl,mpc832x-spi", .data = SOC_MPC832X },
 	{ }
 };
 
diff --git a/drivers/spi/npcm_fiu_spi.c b/drivers/spi/npcm_fiu_spi.c
index 7000fe5..73c5064 100644
--- a/drivers/spi/npcm_fiu_spi.c
+++ b/drivers/spi/npcm_fiu_spi.c
@@ -11,6 +11,7 @@
 #include <linux/bitfield.h>
 #include <linux/log2.h>
 #include <linux/iopoll.h>
+#include <power/regulator.h>
 
 #define DW_SIZE			4
 #define CHUNK_SIZE		16
@@ -34,6 +35,34 @@
 #define UMA_CTS_RDYST		BIT(24)
 #define UMA_CTS_DEV_NUM_MASK	GENMASK(9, 8)
 
+/* Direct Write Configuration Register */
+#define DWR_CFG_WBURST_MASK	GENMASK(25, 24)
+#define DWR_CFG_ADDSIZ_MASK	GENMASK(17, 16)
+#define DWR_CFG_ABPCK_MASK	GENMASK(11, 10)
+#define DRW_CFG_DBPCK_MASK	GENMASK(9, 8)
+#define DRW_CFG_WRCMD		2
+enum {
+	DWR_WBURST_1_BYTE,
+	DWR_WBURST_16_BYTE = 3,
+};
+
+enum {
+	DWR_ADDSIZ_24_BIT,
+	DWR_ADDSIZ_32_BIT,
+};
+
+enum {
+	DWR_ABPCK_BIT_PER_CLK,
+	DWR_ABPCK_2_BIT_PER_CLK,
+	DWR_ABPCK_4_BIT_PER_CLK,
+};
+
+enum {
+	DWR_DBPCK_BIT_PER_CLK,
+	DWR_DBPCK_2_BIT_PER_CLK,
+	DWR_DBPCK_4_BIT_PER_CLK,
+};
+
 struct npcm_fiu_regs {
 	unsigned int    drd_cfg;
 	unsigned int    dwr_cfg;
@@ -67,19 +96,10 @@
 
 struct npcm_fiu_priv {
 	struct npcm_fiu_regs *regs;
-	struct clk clk;
 };
 
 static int npcm_fiu_spi_set_speed(struct udevice *bus, uint speed)
 {
-	struct npcm_fiu_priv *priv = dev_get_priv(bus);
-	int ret;
-
-	debug("%s: set speed %u\n", bus->name, speed);
-	ret = clk_set_rate(&priv->clk, speed);
-	if (ret < 0)
-		return ret;
-
 	return 0;
 }
 
@@ -349,13 +369,38 @@
 static int npcm_fiu_spi_probe(struct udevice *bus)
 {
 	struct npcm_fiu_priv *priv = dev_get_priv(bus);
-	int ret;
+	struct udevice *vqspi_supply;
+	int vqspi_uv;
 
 	priv->regs = (struct npcm_fiu_regs *)dev_read_addr_ptr(bus);
 
-	ret = clk_get_by_index(bus, 0, &priv->clk);
-	if (ret < 0)
-		return ret;
+	if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
+		device_get_supply_regulator(bus, "vqspi-supply", &vqspi_supply);
+		vqspi_uv = dev_read_u32_default(bus, "vqspi-microvolt", 0);
+		/* Set IO voltage */
+		if (vqspi_supply && vqspi_uv)
+			regulator_set_value(vqspi_supply, vqspi_uv);
+	}
+
+	return 0;
+}
+
+static int npcm_fiu_spi_bind(struct udevice *bus)
+{
+	struct npcm_fiu_regs *regs;
+
+	if (dev_read_bool(bus, "nuvoton,spix-mode")) {
+		regs = dev_read_addr_ptr(bus);
+		if (!regs)
+			return -EINVAL;
+
+		/* Setup direct write cfg for SPIX */
+		writel(FIELD_PREP(DWR_CFG_WBURST_MASK, DWR_WBURST_16_BYTE) |
+		       FIELD_PREP(DWR_CFG_ADDSIZ_MASK, DWR_ADDSIZ_24_BIT) |
+		       FIELD_PREP(DWR_CFG_ABPCK_MASK, DWR_ABPCK_4_BIT_PER_CLK) |
+		       FIELD_PREP(DRW_CFG_DBPCK_MASK, DWR_DBPCK_4_BIT_PER_CLK) |
+		       DRW_CFG_WRCMD, &regs->dwr_cfg);
+	}
 
 	return 0;
 }
@@ -384,4 +429,5 @@
 	.ops    = &npcm_fiu_spi_ops,
 	.priv_auto = sizeof(struct npcm_fiu_priv),
 	.probe  = npcm_fiu_spi_probe,
+	.bind = npcm_fiu_spi_bind,
 };
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 8e8995f..b7eca58 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -181,8 +181,12 @@
 	if (op->dummy.nbytes && op->dummy.buswidth == 8 && op->dummy.nbytes % 2)
 		return false;
 
-	if (op->data.dir != SPI_MEM_NO_DATA &&
-	    op->dummy.buswidth == 8 && op->data.nbytes % 2)
+	/*
+	 * Transactions of odd length do not make sense for 8D-8D-8D mode
+	 * because a byte is transferred in just half a cycle.
+	 */
+	if (op->data.dir != SPI_MEM_NO_DATA && op->data.dir != SPI_MEM_DATA_IN &&
+	    op->data.buswidth == 8 && op->data.nbytes % 2)
 		return false;
 
 	return spi_mem_check_buswidth(slave, op);
diff --git a/drivers/spi/spi-sn-f-ospi.c b/drivers/spi/spi-sn-f-ospi.c
index ebf2903..e3633a5 100644
--- a/drivers/spi/spi-sn-f-ospi.c
+++ b/drivers/spi/spi-sn-f-ospi.c
@@ -556,7 +556,7 @@
 	if (!f_ospi_supports_op_width(op))
 		return false;
 
-	return true;
+	return spi_mem_default_supports_op(slave, op);
 }
 
 static int f_ospi_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op)
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c
index 0cae3df..0f5d0a3 100644
--- a/drivers/spi/spi-synquacer.c
+++ b/drivers/spi/spi-synquacer.c
@@ -186,7 +186,7 @@
 	struct udevice *bus = dev->parent;
 	struct synquacer_spi_priv *priv = dev_get_priv(bus);
 	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
-	u32 val, div, bus_width;
+	u32 val, div, bus_width = 1;
 	int rwflag;
 
 	rwflag = (rx ? 1 : 0) | (tx ? 2 : 0);
@@ -211,6 +211,8 @@
 		bus_width = 4;
 	else if (priv->mode & SPI_TX_OCTAL)
 		bus_width = 8;
+	else
+		log_warning("SPI mode not configured, setting to byte mode\n");
 
 	div = DIV_ROUND_UP(125000000, priv->speed);
 
diff --git a/drivers/sysreset/sysreset_psci.c b/drivers/sysreset/sysreset_psci.c
index 83ecbcb..a8a4152 100644
--- a/drivers/sysreset/sysreset_psci.c
+++ b/drivers/sysreset/sysreset_psci.c
@@ -9,6 +9,11 @@
 #include <linux/errno.h>
 #include <linux/psci.h>
 
+__weak int psci_sysreset_get_status(struct udevice *dev, char *buf, int size)
+{
+	return -EOPNOTSUPP;
+}
+
 static int psci_sysreset_request(struct udevice *dev, enum sysreset_t type)
 {
 	switch (type) {
@@ -28,10 +33,12 @@
 
 static struct sysreset_ops psci_sysreset_ops = {
 	.request = psci_sysreset_request,
+	.get_status = psci_sysreset_get_status,
 };
 
 U_BOOT_DRIVER(psci_sysreset) = {
 	.name = "psci-sysreset",
 	.id = UCLASS_SYSRESET,
 	.ops = &psci_sysreset_ops,
+	.flags = DM_FLAG_PRE_RELOC,
 };
diff --git a/drivers/sysreset/sysreset_sandbox.c b/drivers/sysreset/sysreset_sandbox.c
index 0ee286c..3750c60 100644
--- a/drivers/sysreset/sysreset_sandbox.c
+++ b/drivers/sysreset/sysreset_sandbox.c
@@ -65,7 +65,6 @@
 		if (!state->sysreset_allowed[type])
 			return -EACCES;
 		sandbox_exit();
-		break;
 	case SYSRESET_POWER:
 		if (!state->sysreset_allowed[type])
 			return -EACCES;
diff --git a/drivers/tee/sandbox.c b/drivers/tee/sandbox.c
index 35e8542..86219a9 100644
--- a/drivers/tee/sandbox.c
+++ b/drivers/tee/sandbox.c
@@ -119,6 +119,7 @@
 {
 	u32 res;
 	static bool enabled;
+	static bool provisioned;
 
 	switch (func) {
 	case PTA_CMD_ENABLE_SCP03:
@@ -130,12 +131,18 @@
 		if (res)
 			return res;
 
-		if (!enabled) {
+		/* If SCP03 was not enabled, enable it */
+		if (!enabled)
 			enabled = true;
-		} else {
-		}
+
+		/* If SCP03 was not provisioned, provision new keys */
+		if (params[0].u.value.a && !provisioned)
+			provisioned = true;
 
-		if (params[0].u.value.a)
+		/*
+		 * Either way, we asume both operations succeeded and that
+		 * the communication channel has now been stablished
+		 */
 
 		return TEE_SUCCESS;
 	default:
diff --git a/drivers/usb/emul/sandbox_flash.c b/drivers/usb/emul/sandbox_flash.c
index 01ccc4b..7c5c1ab 100644
--- a/drivers/usb/emul/sandbox_flash.c
+++ b/drivers/usb/emul/sandbox_flash.c
@@ -266,6 +266,7 @@
 		default:
 			break;
 		}
+		break;
 	case SANDBOX_FLASH_EP_IN:
 		switch (info->phase) {
 		case SCSIPH_DATA:
diff --git a/drivers/usb/emul/sandbox_hub.c b/drivers/usb/emul/sandbox_hub.c
index 041ec37..084cc16 100644
--- a/drivers/usb/emul/sandbox_hub.c
+++ b/drivers/usb/emul/sandbox_hub.c
@@ -220,13 +220,9 @@
 				udev->status = 0;
 				udev->act_len = sizeof(*hubsts);
 				return 0;
+			    }
 			}
-			default:
-				debug("%s: rx ctl requesttype=%x, request=%x\n",
-				      __func__, setup->requesttype,
-				      setup->request);
-				break;
-			}
+			break;
 		case USB_RT_PORT | USB_DIR_IN:
 			switch (setup->request) {
 			case USB_REQ_GET_STATUS: {
@@ -239,13 +235,12 @@
 				udev->status = 0;
 				udev->act_len = sizeof(*portsts);
 				return 0;
-			}
+			    }
 			}
-		default:
-			debug("%s: rx ctl requesttype=%x, request=%x\n",
-			      __func__, setup->requesttype, setup->request);
 			break;
 		}
+		debug("%s: rx ctl requesttype=%x, request=%x\n",
+		      __func__, setup->requesttype, setup->request);
 	} else if (pipe == usb_sndctrlpipe(udev, 0)) {
 		switch (setup->requesttype) {
 		case USB_RT_PORT:
@@ -263,7 +258,7 @@
 					debug("  ** Invalid feature\n");
 				}
 				return ret;
-			}
+			    }
 			case USB_REQ_CLEAR_FEATURE: {
 				int port;
 
@@ -279,18 +274,11 @@
 				}
 				udev->status = 0;
 				return 0;
+			    }
 			}
-			default:
-				debug("%s: tx ctl requesttype=%x, request=%x\n",
-				      __func__, setup->requesttype,
-				      setup->request);
-				break;
-			}
-		default:
-			debug("%s: tx ctl requesttype=%x, request=%x\n",
-			      __func__, setup->requesttype, setup->request);
-			break;
 		}
+		debug("%s: tx ctl requesttype=%x, request=%x\n",
+		      __func__, setup->requesttype, setup->request);
 	}
 	debug("pipe=%lx\n", pipe);
 
diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
index 45f0504..f46829e 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -1117,7 +1117,7 @@
 {
 	struct fsg_lun	*curlun = &common->luns[common->lun];
 	u8		*buf = (u8 *) bh->buf;
-	u32		sd, sdinfo;
+	u32		sd, sdinfo = 0;
 	int		valid;
 
 	/*
@@ -1145,7 +1145,6 @@
 	if (!curlun) {		/* Unsupported LUNs are okay */
 		common->bad_lun_okay = 1;
 		sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
-		sdinfo = 0;
 		valid = 0;
 	} else {
 		sd = curlun->sense_data;
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 91633f0..fae2083 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -703,6 +703,10 @@
 	usb_internal_phy_clock_gate(priv->phy_addr, 1);
 	usb_phy_enable(ehci, priv->phy_addr);
 #endif
+#else
+	ret = generic_setup_phy(dev, &priv->phy, 0);
+	if (ret)
+		goto err_regulator;
 #endif
 
 #if CONFIG_IS_ENABLED(DM_REGULATOR)
@@ -725,12 +729,6 @@
 
 	mdelay(10);
 
-#if defined(CONFIG_PHY)
-	ret = generic_setup_phy(dev, &priv->phy, 0);
-	if (ret)
-		goto err_regulator;
-#endif
-
 	hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
 	hcor = (struct ehci_hcor *)((uintptr_t)hccr +
 			HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
diff --git a/drivers/virtio/virtio-uclass.c b/drivers/virtio/virtio-uclass.c
index de9bc90..31bb21c 100644
--- a/drivers/virtio/virtio-uclass.c
+++ b/drivers/virtio/virtio-uclass.c
@@ -336,7 +336,7 @@
 	/* Transport features always preserved to pass to finalize_features */
 	for (i = VIRTIO_TRANSPORT_F_START; i < VIRTIO_TRANSPORT_F_END; i++)
 		if ((device_features & (1ULL << i)) &&
-		    (i == VIRTIO_F_VERSION_1))
+		    (i == VIRTIO_F_VERSION_1 || i == VIRTIO_F_IOMMU_PLATFORM))
 			__virtio_set_bit(vdev->parent, i);
 
 	debug("(%s) final negotiated features supported %016llx\n",
@@ -373,6 +373,12 @@
 {
 	int ret;
 
+	if (IS_ENABLED(CONFIG_PCI)) {
+		ret = uclass_probe_all(UCLASS_PCI);
+		if (ret && ret != -ENOENT)
+			return log_msg_ret("pci", ret);
+	}
+
 	ret = uclass_probe_all(UCLASS_VIRTIO);
 	if (ret && ret != -ENOENT)
 		return log_msg_ret("vir", ret);
diff --git a/drivers/virtio/virtio_pci_modern.c b/drivers/virtio/virtio_pci_modern.c
index cfde400..3cdc2d2 100644
--- a/drivers/virtio/virtio_pci_modern.c
+++ b/drivers/virtio/virtio_pci_modern.c
@@ -218,25 +218,6 @@
 	return 0;
 }
 
-static int virtio_pci_reset(struct udevice *udev)
-{
-	struct virtio_pci_priv *priv = dev_get_priv(udev);
-
-	/* 0 status means a reset */
-	iowrite8(0, &priv->common->device_status);
-
-	/*
-	 * After writing 0 to device_status, the driver MUST wait for a read
-	 * of device_status to return 0 before reinitializing the device.
-	 * This will flush out the status write, and flush in device writes,
-	 * including MSI-X interrupts, if any.
-	 */
-	while (ioread8(&priv->common->device_status))
-		udelay(1000);
-
-	return 0;
-}
-
 static int virtio_pci_get_features(struct udevice *udev, u64 *features)
 {
 	struct virtio_pci_priv *priv = dev_get_priv(udev);
@@ -363,6 +344,25 @@
 	return 0;
 }
 
+static int virtio_pci_reset(struct udevice *udev)
+{
+	struct virtio_pci_priv *priv = dev_get_priv(udev);
+
+	/* 0 status means a reset */
+	iowrite8(0, &priv->common->device_status);
+
+	/*
+	 * After writing 0 to device_status, the driver MUST wait for a read
+	 * of device_status to return 0 before reinitializing the device.
+	 * This will flush out the status write, and flush in device writes,
+	 * including MSI-X interrupts, if any.
+	 */
+	while (ioread8(&priv->common->device_status))
+		udelay(1000);
+
+	return virtio_pci_del_vqs(udev);
+}
+
 static int virtio_pci_notify(struct udevice *udev, struct virtqueue *vq)
 {
 	struct virtio_pci_priv *priv = dev_get_priv(udev);
diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c
index f71bab7..c9adcce 100644
--- a/drivers/virtio/virtio_ring.c
+++ b/drivers/virtio/virtio_ring.c
@@ -6,6 +6,7 @@
  * virtio ring implementation
  */
 
+#include <bouncebuf.h>
 #include <common.h>
 #include <dm.h>
 #include <log.h>
@@ -15,15 +16,63 @@
 #include <virtio_ring.h>
 #include <linux/bug.h>
 #include <linux/compat.h>
+#include <linux/kernel.h>
+
+static void *virtio_alloc_pages(struct udevice *vdev, u32 npages)
+{
+	return memalign(PAGE_SIZE, npages * PAGE_SIZE);
+}
+
+static void virtio_free_pages(struct udevice *vdev, void *ptr, u32 npages)
+{
+	free(ptr);
+}
+
+static int __bb_force_page_align(struct bounce_buffer *state)
+{
+	const ulong align_mask = PAGE_SIZE - 1;
+
+	if ((ulong)state->user_buffer & align_mask)
+		return 0;
+
+	if (state->len != state->len_aligned)
+		return 0;
+
+	return 1;
+}
 
 static unsigned int virtqueue_attach_desc(struct virtqueue *vq, unsigned int i,
 					  struct virtio_sg *sg, u16 flags)
 {
 	struct vring_desc_shadow *desc_shadow = &vq->vring_desc_shadow[i];
 	struct vring_desc *desc = &vq->vring.desc[i];
+	void *addr;
+
+	if (IS_ENABLED(CONFIG_BOUNCE_BUFFER) && vq->vring.bouncebufs) {
+		struct bounce_buffer *bb = &vq->vring.bouncebufs[i];
+		unsigned int bbflags;
+		int ret;
+
+		if (flags & VRING_DESC_F_WRITE)
+			bbflags = GEN_BB_WRITE;
+		else
+			bbflags = GEN_BB_READ;
+
+		ret = bounce_buffer_start_extalign(bb, sg->addr, sg->length,
+						   bbflags, PAGE_SIZE,
+						   __bb_force_page_align);
+		if (ret) {
+			debug("%s: failed to allocate bounce buffer (length 0x%zx)\n",
+			      vq->vdev->name, sg->length);
+		}
+
+		addr = bb->bounce_buffer;
+	} else {
+		addr = sg->addr;
+	}
 
 	/* Update the shadow descriptor. */
-	desc_shadow->addr = (u64)(uintptr_t)sg->addr;
+	desc_shadow->addr = (u64)(uintptr_t)addr;
 	desc_shadow->len = sg->length;
 	desc_shadow->flags = flags;
 
@@ -36,6 +85,19 @@
 	return desc_shadow->next;
 }
 
+static void virtqueue_detach_desc(struct virtqueue *vq, unsigned int idx)
+{
+	struct vring_desc *desc = &vq->vring.desc[idx];
+	struct bounce_buffer *bb;
+
+	if (!IS_ENABLED(CONFIG_BOUNCE_BUFFER) || !vq->vring.bouncebufs)
+		return;
+
+	bb = &vq->vring.bouncebufs[idx];
+	bounce_buffer_stop(bb);
+	desc->addr = cpu_to_virtio64(vq->vdev, (u64)(uintptr_t)bb->user_buffer);
+}
+
 int virtqueue_add(struct virtqueue *vq, struct virtio_sg *sgs[],
 		  unsigned int out_sgs, unsigned int in_sgs)
 {
@@ -154,10 +216,12 @@
 	i = head;
 
 	while (vq->vring_desc_shadow[i].flags & VRING_DESC_F_NEXT) {
+		virtqueue_detach_desc(vq, i);
 		i = vq->vring_desc_shadow[i].next;
 		vq->num_free++;
 	}
 
+	virtqueue_detach_desc(vq, i);
 	vq->vring_desc_shadow[i].next = vq->free_head;
 	vq->free_head = head;
 
@@ -271,8 +335,11 @@
 					 unsigned int vring_align,
 					 struct udevice *udev)
 {
+	struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
+	struct udevice *vdev = uc_priv->vdev;
 	struct virtqueue *vq;
 	void *queue = NULL;
+	struct bounce_buffer *bbs = NULL;
 	struct vring vring;
 
 	/* We assume num is a power of 2 */
@@ -283,7 +350,9 @@
 
 	/* TODO: allocate each queue chunk individually */
 	for (; num && vring_size(num, vring_align) > PAGE_SIZE; num /= 2) {
-		queue = memalign(PAGE_SIZE, vring_size(num, vring_align));
+		size_t sz = vring_size(num, vring_align);
+
+		queue = virtio_alloc_pages(vdev, DIV_ROUND_UP(sz, PAGE_SIZE));
 		if (queue)
 			break;
 	}
@@ -293,30 +362,44 @@
 
 	if (!queue) {
 		/* Try to get a single page. You are my only hope! */
-		queue = memalign(PAGE_SIZE, vring_size(num, vring_align));
+		queue = virtio_alloc_pages(vdev, 1);
 	}
 	if (!queue)
 		return NULL;
 
 	memset(queue, 0, vring_size(num, vring_align));
-	vring_init(&vring, num, queue, vring_align);
 
-	vq = __vring_new_virtqueue(index, vring, udev);
-	if (!vq) {
-		free(queue);
-		return NULL;
+	if (virtio_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM)) {
+		bbs = calloc(num, sizeof(*bbs));
+		if (!bbs)
+			goto err_free_queue;
 	}
+
+	vring_init(&vring, num, queue, vring_align, bbs);
+
+	vq = __vring_new_virtqueue(index, vring, udev);
+	if (!vq)
+		goto err_free_bbs;
+
 	debug("(%s): created vring @ %p for vq @ %p with num %u\n", udev->name,
 	      queue, vq, num);
 
 	return vq;
+
+err_free_bbs:
+	free(bbs);
+err_free_queue:
+	virtio_free_pages(vdev, queue, DIV_ROUND_UP(vring.size, PAGE_SIZE));
+	return NULL;
 }
 
 void vring_del_virtqueue(struct virtqueue *vq)
 {
-	free(vq->vring.desc);
+	virtio_free_pages(vq->vdev, vq->vring.desc,
+			  DIV_ROUND_UP(vq->vring.size, PAGE_SIZE));
 	free(vq->vring_desc_shadow);
 	list_del(&vq->list);
+	free(vq->vring.bouncebufs);
 	free(vq);
 }
 
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index a15fbd6..6466635 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -185,12 +185,28 @@
 	  Select this to enable Meson watchdog timer,
 	  which can be found on some Amlogic platforms.
 
-config WDT_MPC8xx
-	bool "MPC8xx watchdog timer support"
-	depends on WDT && MPC8xx
-	select HW_WATCHDOG
+config WDT_MPC8xxx
+	bool "MPC8xxx watchdog timer support"
+	depends on WDT && (MPC8xx || MPC83xx)
+	help
+	  Select this to enable mpc8xxx watchdog timer
+
+config WDT_MPC8xxx_BME
+	bool "Enable MPC8xx Bus Monitoring"
+	depends on WDT_MPC8xxx && MPC8xx
+	help
+	  Select this to enable mpc8xx Bus Monitor.
+
+config WDT_MPC8xxx_BMT
+	int "MPC8xx Bus Monitor Timing" if WDT_MPC8xxx_BME
+	range 0 255
+	default 255
+	depends on WDT_MPC8xxx
 	help
-	  Select this to enable mpc8xx watchdog timer
+	  Bus monitor timing. Defines the timeout period, in 8 system clock
+	  resolution, for the bus monitor.
+
+	  Maximum timeout is 2,040 clocks (255 x 8).
 
 config WDT_MT7620
 	bool "MediaTek MT7620 watchdog timer support"
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 4da3386..fd5d9c7 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -32,7 +32,7 @@
 obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o
 obj-$(CONFIG_WDT_MAX6370) += max6370_wdt.o
 obj-$(CONFIG_WDT_MESON_GXBB) += meson_gxbb_wdt.o
-obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
+obj-$(CONFIG_WDT_MPC8xxx) += mpc8xxx_wdt.o
 obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o
 obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
 obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
diff --git a/drivers/watchdog/mpc8xx_wdt.c b/drivers/watchdog/mpc8xx_wdt.c
deleted file mode 100644
index c8b104d..0000000
--- a/drivers/watchdog/mpc8xx_wdt.c
+++ /dev/null
@@ -1,75 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2017 CS Systemes d'Information
- */
-
-#include <common.h>
-#include <env.h>
-#include <dm.h>
-#include <wdt.h>
-#include <mpc8xx.h>
-#include <asm/cpm_8xx.h>
-#include <asm/io.h>
-
-void hw_watchdog_reset(void)
-{
-	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
-
-	out_be16(&immap->im_siu_conf.sc_swsr, 0x556c);	/* write magic1 */
-	out_be16(&immap->im_siu_conf.sc_swsr, 0xaa39);	/* write magic2 */
-}
-
-static int mpc8xx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
-{
-	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
-	u32 val = CONFIG_SYS_SYPCR;
-	const char *mode = env_get("watchdog_mode");
-
-	if (strcmp(mode, "off") == 0)
-		val = val & ~(SYPCR_SWE | SYPCR_SWRI);
-	else if (strcmp(mode, "nmi") == 0)
-		val = (val & ~SYPCR_SWRI) | SYPCR_SWE;
-
-	out_be32(&immap->im_siu_conf.sc_sypcr, val);
-
-	if (!(in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE))
-		return -EBUSY;
-	return 0;
-
-}
-
-static int mpc8xx_wdt_stop(struct udevice *dev)
-{
-	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
-
-	out_be32(&immap->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE);
-
-	if (in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE)
-		return -EBUSY;
-	return 0;
-}
-
-static int mpc8xx_wdt_reset(struct udevice *dev)
-{
-	hw_watchdog_reset();
-
-	return 0;
-}
-
-static const struct wdt_ops mpc8xx_wdt_ops = {
-	.start = mpc8xx_wdt_start,
-	.reset = mpc8xx_wdt_reset,
-	.stop = mpc8xx_wdt_stop,
-};
-
-static const struct udevice_id mpc8xx_wdt_ids[] = {
-	{ .compatible = "fsl,pq1-wdt" },
-	{}
-};
-
-U_BOOT_DRIVER(wdt_mpc8xx) = {
-	.name = "wdt_mpc8xx",
-	.id = UCLASS_WDT,
-	.of_match = mpc8xx_wdt_ids,
-	.ops = &mpc8xx_wdt_ops,
-};
diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c
new file mode 100644
index 0000000..f28636c
--- /dev/null
+++ b/drivers/watchdog/mpc8xxx_wdt.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 CS Systemes d'Information
+ */
+
+#include <common.h>
+#include <env.h>
+#include <dm.h>
+#include <wdt.h>
+#include <clock_legacy.h>
+#include <asm/io.h>
+
+struct mpc8xxx_wdt {
+	__be32 res0;
+	__be32 swcrr;	/* System watchdog control register */
+#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
+#define SWCRR_BME  0x00000080 /* Bus monitor enable (mpc8xx) */
+#define SWCRR_SWF  0x00000008 /* Software Watchdog Freeze (mpc8xx). */
+#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
+#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/
+#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
+	__be32 swcnr;	/* System watchdog count register */
+	u8 res1[2];
+	__be16 swsrr;	/* System watchdog service register */
+	u8 res2[0xf0];
+};
+
+struct mpc8xxx_wdt_priv {
+	struct mpc8xxx_wdt __iomem *base;
+};
+
+static int mpc8xxx_wdt_reset(struct udevice *dev)
+{
+	struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev);
+
+	out_be16(&priv->base->swsrr, 0x556c);	/* write magic1 */
+	out_be16(&priv->base->swsrr, 0xaa39);	/* write magic2 */
+
+	return 0;
+}
+
+static int mpc8xxx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+	struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev);
+	const char *mode = env_get("watchdog_mode");
+	ulong prescaler = dev_get_driver_data(dev);
+	u16 swtc = min_t(u16, timeout * get_board_sys_clk() / 1000 / prescaler, U16_MAX);
+	u32 val;
+
+	mpc8xxx_wdt_reset(dev);
+
+	if (strcmp(mode, "off") == 0)
+		val = (swtc << 16) | SWCRR_SWPR;
+	else if (strcmp(mode, "nmi") == 0)
+		val = (swtc << 16) | SWCRR_SWPR | SWCRR_SWEN;
+	else
+		val = (swtc << 16) | SWCRR_SWPR | SWCRR_SWEN | SWCRR_SWRI;
+
+	if (IS_ENABLED(CONFIG_WDT_MPC8xxx_BME))
+		val |= (CONFIG_WDT_MPC8xxx_BMT << 8) | SWCRR_BME;
+
+	out_be32(&priv->base->swcrr, val);
+
+	if (!(in_be32(&priv->base->swcrr) & SWCRR_SWEN))
+		return -EBUSY;
+	return 0;
+
+}
+
+static int mpc8xxx_wdt_stop(struct udevice *dev)
+{
+	struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev);
+
+	clrbits_be32(&priv->base->swcrr, SWCRR_SWEN);
+
+	if (in_be32(&priv->base->swcrr) & SWCRR_SWEN)
+		return -EBUSY;
+	return 0;
+}
+
+static int mpc8xxx_wdt_of_to_plat(struct udevice *dev)
+{
+	struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev);
+
+	priv->base = (void __iomem *)devfdt_remap_addr(dev);
+
+	if (!priv->base)
+		return -EINVAL;
+
+	return 0;
+}
+
+static const struct wdt_ops mpc8xxx_wdt_ops = {
+	.start = mpc8xxx_wdt_start,
+	.reset = mpc8xxx_wdt_reset,
+	.stop = mpc8xxx_wdt_stop,
+};
+
+static const struct udevice_id mpc8xxx_wdt_ids[] = {
+	{ .compatible = "fsl,pq1-wdt", .data = 0x800 },
+	{ .compatible = "fsl,pq2pro-wdt", .data = 0x10000 },
+	{}
+};
+
+U_BOOT_DRIVER(wdt_mpc8xxx) = {
+	.name = "wdt_mpc8xxx",
+	.id = UCLASS_WDT,
+	.of_match = mpc8xxx_wdt_ids,
+	.ops = &mpc8xxx_wdt_ops,
+	.of_to_plat = mpc8xxx_wdt_of_to_plat,
+	.priv_auto	= sizeof(struct mpc8xxx_wdt_priv),
+};
diff --git a/drivers/xen/Kconfig b/drivers/xen/Kconfig
index 0ee74d0..6cb9149 100644
--- a/drivers/xen/Kconfig
+++ b/drivers/xen/Kconfig
@@ -1,6 +1,6 @@
 config PVBLOCK
 	bool "Xen para-virtualized block device"
-	depends on DM
+	depends on DM && XEN
 	select BLK
 	help
 	  This driver implements the front-end of the Xen virtual
diff --git a/drivers/xen/hypervisor.c b/drivers/xen/hypervisor.c
index 16c7c96..0b2311b 100644
--- a/drivers/xen/hypervisor.c
+++ b/drivers/xen/hypervisor.c
@@ -264,8 +264,15 @@
 
 int xen_init(void)
 {
+	int el = current_el();
+
 	debug("%s\n", __func__);
 
+	if (el != 1) {
+		puts("XEN:\tnot running from EL1\n");
+		return 0;
+	}
+
 	map_shared_info(NULL);
 	init_events();
 	init_xenbus();
diff --git a/fs/yaffs2/yaffsfs.c b/fs/yaffs2/yaffsfs.c
index 510faae..d615f02 100644
--- a/fs/yaffs2/yaffsfs.c
+++ b/fs/yaffs2/yaffsfs.c
@@ -468,7 +468,7 @@
 	return 0;
 }
 
-LIST_HEAD(yaffsfs_deviceList);
+static LIST_HEAD(yaffsfs_deviceList);
 
 /*
  * yaffsfs_FindDevice
diff --git a/include/axp209.h b/include/axp209.h
index 414f88a..d8bf44f 100644
--- a/include/axp209.h
+++ b/include/axp209.h
@@ -77,7 +77,6 @@
 #ifdef CONFIG_AXP209_POWER
 #define AXP_POWER_STATUS		0x00
 #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
-#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
 #define AXP_GPIO0_CTRL			0x90
 #define AXP_GPIO1_CTRL			0x92
 #define AXP_GPIO2_CTRL			0x93
diff --git a/include/axp221.h b/include/axp221.h
index 8dfcc5b..32b988f 100644
--- a/include/axp221.h
+++ b/include/axp221.h
@@ -53,7 +53,6 @@
 #ifdef CONFIG_AXP221_POWER
 #define AXP_POWER_STATUS		0x00
 #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
-#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
 #define AXP_VBUS_IPSOUT			0x30
 #define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
 #define AXP_MISC_CTRL			0x8f
diff --git a/include/axp809.h b/include/axp809.h
index 8082e40..71a7cb2 100644
--- a/include/axp809.h
+++ b/include/axp809.h
@@ -47,7 +47,6 @@
 #ifdef CONFIG_AXP809_POWER
 #define AXP_POWER_STATUS		0x00
 #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
-#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
 #define AXP_VBUS_IPSOUT			0x30
 #define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
 #define AXP_MISC_CTRL			0x8f
diff --git a/include/axp818.h b/include/axp818.h
index 8ac517a..08ac35d 100644
--- a/include/axp818.h
+++ b/include/axp818.h
@@ -61,7 +61,6 @@
 #ifdef CONFIG_AXP818_POWER
 #define AXP_POWER_STATUS		0x00
 #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
-#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
 #define AXP_VBUS_IPSOUT			0x30
 #define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
 #define AXP_MISC_CTRL			0x8f
diff --git a/include/binman_sym.h b/include/binman_sym.h
index 528d7e4..49a95ea 100644
--- a/include/binman_sym.h
+++ b/include/binman_sym.h
@@ -71,7 +71,7 @@
  * value #defined above. This is used to check at runtime if the
  * symbol values were filled in and are OK to use.
  */
-extern ulong _binman_sym_magic;
+extern unsigned long _binman_sym_magic;
 
 /**
  * DECLARE_BINMAN_MAGIC_SYM - Declare the internal magic symbol
@@ -81,7 +81,7 @@
  * definitions of the symbol.
  */
 #define DECLARE_BINMAN_MAGIC_SYM \
-	ulong _binman_sym_magic \
+	unsigned long _binman_sym_magic \
 		__attribute__((aligned(4), section(".binman_sym")))
 
 /**
@@ -93,14 +93,14 @@
  * Return: 1 if binman symbol values are usable, 0 if not
  */
 #define BINMAN_SYMS_OK \
-	(*(ulong *)&_binman_sym_magic == BINMAN_SYM_MAGIC_VALUE)
+	(*(unsigned long *)&_binman_sym_magic == BINMAN_SYM_MAGIC_VALUE)
 
 /**
  * binman_sym() - Access a previously declared symbol
  *
  * This is used to get the value of a symbol. E.g.:
  *
- *    ulong address = binman_sym(ulong, u_boot_spl, pos);
+ *    unsigned long address = binman_sym(unsigned long, u_boot_spl, pos);
  *
  * @_type: Type f the symbol (e.g. unsigned long)
  * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl')
diff --git a/include/blk.h b/include/blk.h
index 1db203c..2c9c798 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -62,10 +62,9 @@
 	unsigned char	hwpart;		/* HW partition, e.g. for eMMC */
 	unsigned char	type;		/* device type */
 	unsigned char	removable;	/* removable device */
-#ifdef CONFIG_LBA48
 	/* device can use 48bit addr (ATA/ATAPI v7) */
-	unsigned char	lba48;
-#endif
+	bool	lba48;
+	unsigned char	atapi;		/* Use ATAPI protocol */
 	lbaint_t	lba;		/* number of blocks */
 	unsigned long	blksz;		/* block size */
 	int		log2blksz;	/* for convenience: log2(blksz) */
diff --git a/include/bootdev.h b/include/bootdev.h
index b92ff4d..e72ef36 100644
--- a/include/bootdev.h
+++ b/include/bootdev.h
@@ -258,7 +258,7 @@
  * @devp: returns the device found, on success
  * @method_flagsp: If non-NULL, returns any flags implied by the label
  * (enum bootflow_meth_flags_t), 0 if none. Unset if function fails
- * Return: 0 if OK, -EINVAL if the uclass is not supported by this board,
+ * Return: 0 if OK, -EPFNOSUPPORT if the uclass is not supported by this board,
  * -ENOENT if there is no device with that number
  */
 int bootdev_find_by_any(const char *name, struct udevice **devp,
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 70b1c39..3967cc2 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -140,7 +140,9 @@
 /*
  * Serial Port
  */
+#if !CONFIG_IS_ENABLED(DM_SERIAL) && !CONFIG_IS_ENABLED(DM_CLK)
 #define CFG_SYS_NS16550_CLK		get_bus_freq(0)
+#endif
 
 #define CFG_SYS_BAUDRATE_TABLE \
 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
index 26a7f25..1e37ab4 100644
--- a/include/configs/am64x_evm.h
+++ b/include/configs/am64x_evm.h
@@ -18,91 +18,6 @@
 /* DDR Configuration */
 #define CFG_SYS_SDRAM_BASE1		0x880000000
 
-#define PARTS_DEFAULT \
-	/* Linux partitions */ \
-	"name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
-
-/* U-Boot general configuration */
-#define EXTRA_ENV_AM642_BOARD_SETTINGS					\
-	"findfdt="							\
-		"if test $board_name = am64x_gpevm; then " \
-			"setenv fdtfile k3-am642-evm.dtb; fi; " \
-		"if test $board_name = am64x_skevm; then " \
-			"setenv fdtfile k3-am642-sk.dtb; fi;" \
-		"if test $fdtfile = undefined; then " \
-			"echo WARNING: Could not determine device tree to use; fi; \0" \
-	"name_kern=Image\0"						\
-	"console=ttyS2,115200n8\0"					\
-	"args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 "	\
-		"${mtdparts}\0"						\
-	"run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
-
-/* U-Boot MMC-specific configuration */
-#define EXTRA_ENV_AM642_BOARD_SETTINGS_MMC				\
-	"boot=mmc\0"							\
-	"mmcdev=1\0"							\
-	"bootpart=1:2\0"						\
-	"bootdir=/boot\0"						\
-	"rd_spec=-\0"							\
-	"init_mmc=run args_all args_mmc\0"				\
-	"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
-	"get_overlay_mmc="						\
-		"fdt address ${fdtaddr};"				\
-		"fdt resize 0x100000;"					\
-		"for overlay in $name_overlays;"			\
-		"do;"							\
-		"load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && "	\
-		"fdt apply ${dtboaddr};"				\
-		"done;\0"						\
-	"get_kern_mmc=load mmc ${bootpart} ${loadaddr} "		\
-		"${bootdir}/${name_kern}\0"				\
-	"get_fit_mmc=load mmc ${bootpart} ${addr_fit} "			\
-		"${bootdir}/${name_fit}\0"				\
-	"partitions=" PARTS_DEFAULT
-
-#define EXTRA_ENV_AM642_BOARD_SETTING_USBMSC				\
-	"args_usb=run finduuid;setenv bootargs console=${console} "	\
-		"${optargs} "						\
-		"root=PARTUUID=${uuid} rw "				\
-		"rootfstype=${mmcrootfstype}\0"				\
-	"init_usb=run args_all args_usb\0"				\
-	"get_fdt_usb=load usb ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
-	"get_overlay_usb="						\
-		"fdt address ${fdtaddr};"				\
-		"fdt resize 0x100000;"					\
-		"for overlay in $name_overlays;"			\
-		"do;"							\
-		"load usb ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && "	\
-		"fdt apply ${dtboaddr};"				\
-		"done;\0"						\
-	"get_kern_usb=load usb ${bootpart} ${loadaddr} "		\
-		"${bootdir}/${name_kern}\0"				\
-	"get_fit_usb=load usb ${bootpart} ${addr_fit} "			\
-		"${bootdir}/${name_fit}\0"				\
-	"usbboot=setenv boot usb;"					\
-		"setenv bootpart 0:2;"					\
-		"usb start;"						\
-		"run findfdt;"						\
-		"run init_usb;"						\
-		"run get_kern_usb;"					\
-		"run get_fdt_usb;"					\
-		"run run_kern\0"
-
-#define EXTRA_ENV_DFUARGS \
-	DFU_ALT_INFO_MMC \
-	DFU_ALT_INFO_EMMC \
-	DFU_ALT_INFO_RAM \
-	DFU_ALT_INFO_OSPI
-
-/* Incorporate settings into the U-Boot environment */
-#define CFG_EXTRA_ENV_SETTINGS					\
-	DEFAULT_LINUX_BOOT_ENV						\
-	DEFAULT_MMC_TI_ARGS						\
-	EXTRA_ENV_AM642_BOARD_SETTINGS					\
-	EXTRA_ENV_AM642_BOARD_SETTINGS_MMC				\
-	EXTRA_ENV_DFUARGS						\
-	EXTRA_ENV_AM642_BOARD_SETTING_USBMSC
-
 /* Now for the remaining common defines */
 #include <configs/ti_armv7_common.h>
 
diff --git a/include/configs/bcmns.h b/include/configs/bcmns.h
new file mode 100644
index 0000000..6f5f2b7
--- /dev/null
+++ b/include/configs/bcmns.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __BCM_NS_H
+#define __BCM_NS_H
+
+#include <linux/sizes.h>
+
+/* Physical Memory Map */
+#define V2M_BASE			0x00000000
+#define PHYS_SDRAM_1			V2M_BASE
+
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Called "periph_clk" in Linux, used by the global timer */
+#define CFG_SYS_HZ_CLOCK		500000000
+
+/* Called "iprocslow" in Linux */
+#define CFG_SYS_NS16550_CLK		125000000
+
+/* console configuration */
+#define CONSOLE_ARGS "console_args=console=ttyS0,115200n8\0"
+#define MAX_CPUS "max_cpus=maxcpus=2\0"
+#define EXTRA_ARGS "extra_args=earlycon=uart8250,mmio32,0x18000300\0"
+
+#define BASE_ARGS "${console_args} ${extra_args} ${pcie_args}"	\
+		  " ${max_cpus}  ${log_level} ${reserved_mem}"
+#define SETBOOTARGS "setbootargs=setenv bootargs " BASE_ARGS "\0"
+
+#define KERNEL_LOADADDR_CFG \
+	"loadaddr=0x01000000\0" \
+	"dtb_loadaddr=0x02000000\0"
+
+/*
+ * Hardcoded for the only boards we support, if you add more
+ * boards, add a more clever bootcmd!
+ */
+#define NS_BOOTCMD "bootcmd_dlink_dir8xxl=seama 0x00fe0000; go 0x01000000"
+
+#define ARCH_ENV_SETTINGS \
+	CONSOLE_ARGS \
+	MAX_CPUS \
+	EXTRA_ARGS \
+	KERNEL_LOADADDR_CFG \
+	NS_BOOTCMD
+
+#define CFG_EXTRA_ENV_SETTINGS \
+	ARCH_ENV_SETTINGS
+
+#endif /* __BCM_NS_H */
diff --git a/include/configs/cmpc885.h b/include/configs/cmpc885.h
index 4ce580c..b76230e 100644
--- a/include/configs/cmpc885.h
+++ b/include/configs/cmpc885.h
@@ -26,4 +26,10 @@
 /* NAND configuration part */
 #define CFG_SYS_NAND_BASE		0xC0000000
 
+/* Board names */
+#define CFG_BOARD_CMPCXXX		"cmpc885"
+#define CFG_BOARD_MCR3000_2G		"mcr3k_2g"
+#define CFG_BOARD_VGOIP			"vgoip"
+#define CFG_BOARD_MIAE			"miae"
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/cmpcpro.h b/include/configs/cmpcpro.h
new file mode 100644
index 0000000..24e62df
--- /dev/null
+++ b/include/configs/cmpcpro.h
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006-2023  CS GROUP France
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+/*
+ * System IO Config
+ */
+#define CFG_SYS_SICRL		0x00000000
+
+#define CFG_SYS_DDR_SDRAM_BASE	0x00000000
+
+#define CFG_SYS_DDRCDR		0x73000002	/* DDR II voltage is 1.8V */
+
+/*
+ * Manually set up DDR parameters
+ */
+
+/* DDR 512 M */
+#define CFG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_ODT_WR_CFG | CSCONFIG_BANK_BIT_3 | \
+				 CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10)
+/* 0x80840102 */
+#define CFG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) | \
+				 (0 << TIMING_CFG0_WRT_SHIFT) | \
+				 (0 << TIMING_CFG0_RRT_SHIFT) | \
+				 (0 << TIMING_CFG0_WWT_SHIFT) | \
+				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+/* 0x00220802 */
+#define CFG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) | \
+				 (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 (5 << TIMING_CFG1_CASLAT_SHIFT) | \
+				 (27 << TIMING_CFG1_REFREC_SHIFT) | \
+				 (2 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 (2 << TIMING_CFG1_WRTORD_SHIFT))
+/* 0x3935D322 */
+#define CFG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+				 (31 << TIMING_CFG2_CPO_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+				 (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
+/* 0x0F9048CA */
+#define CFG_SYS_DDR_TIMING_3	0x00000000
+#define CFG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+/* 0x02000000 */
+#define CFG_SYS_DDR_MODE	((0x4440 << SDRAM_MODE_ESD_SHIFT) | (0x0232 << SDRAM_MODE_SD_SHIFT))
+/* 0x44400232 */
+#define CFG_SYS_DDR_MODE2	0x8000c000
+#define CFG_SYS_DDR_INTERVAL	((800 << SDRAM_INTERVAL_REFINT_SHIFT) | \
+				 (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+#define CFG_SYS_DDR_CS0_BNDS	(CFG_SYS_DDR_SDRAM_BASE >> 8 | 0x0000001F)
+
+#define CFG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_32_BE)
+/* 0x43080000 */
+#define CFG_SYS_DDR_SDRAM_CFG2	0x00401000
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CFG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_IMMR + 0x110000)
+#define CFG_SYS_INIT_RAM_SIZE	0x4000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_SYS_FLASH_BASE	0x40000000	/* FLASH base address */
+#define CFG_SYS_FLASH_SIZE	64		/* FLASH size is 64M */
+
+/*
+ * NAND
+ */
+#define CFG_SYS_NAND_BASE	0xa0000000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+					/* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ	SZ_256M
+
+/* Board names */
+#define CFG_BOARD_CMPCXXX	"cmpcpro"
+#define CFG_BOARD_MCR3000_2G	"mcrpro"
+#define CFG_BOARD_VGOIP		"vgoippro"
+#define CFG_BOARD_MIAE		"miaepro"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/hc2910-2aghd05.h b/include/configs/hc2910-2aghd05.h
new file mode 100644
index 0000000..3db9a47
--- /dev/null
+++ b/include/configs/hc2910-2aghd05.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __HC2910_2AGHD05_CONFIG_H__
+#define __HC2910_2AGHD05_CONFIG_H__
+
+#endif
diff --git a/include/configs/imx8mq_reform2.h b/include/configs/imx8mq_reform2.h
new file mode 100644
index 0000000..3148e86
--- /dev/null
+++ b/include/configs/imx8mq_reform2.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8M_REFORM2_H
+#define __IMX8M_REFORM2_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CFG_MALLOC_F_ADDR		0x182000
+/* For RAW image gives a error info not panic */
+#endif
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CFG_FEC_MXC_PHYADDR		4
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#define CFG_EXTRA_ENV_SETTINGS		\
+	BOOTENV \
+	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"image=Image\0" \
+	"console=ttymxc0,115200\0" \
+	"fdt_addr_r=0x43000000\0" \
+	"ramdisk_addr_r=0x44000000\0" \
+	"boot_fdt=try\0" \
+	"fdtfile=imx8mq-mnt-reform2.dtb\0" \
+	"initrd_addr=0x43800000\0" \
+	"bootm_size=0x10000000\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
+	"stdin=serial,usbkbd\0"
+
+/* Link Definitions */
+
+#define CFG_SYS_INIT_RAM_ADDR		0x40000000
+#define CFG_SYS_INIT_RAM_SIZE		0x80000
+
+
+#define CFG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM			0x40000000
+#define PHYS_SDRAM_SIZE			0x100000000	/* 4 GiB DDR */
+
+#define CFG_MXC_UART_BASE		UART_BASE_ADDR(1)
+
+#define CFG_SYS_FSL_USDHC_NUM		2
+#define CFG_SYS_FSL_ESDHC_ADDR		0
+
+#endif
diff --git a/include/configs/imx8qm_dmsse20.h b/include/configs/imx8qm_dmsse20.h
new file mode 100644
index 0000000..f9cda5e
--- /dev/null
+++ b/include/configs/imx8qm_dmsse20.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017-2019 NXP
+ * Copyright 2019-2023 Kococonnector GmbH
+ */
+
+#ifndef __IMX8QM_DMSSE20_H
+#define __IMX8QM_DMSSE20_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+/* Flat Device Tree Definitions */
+
+#define CFG_SYS_FSL_ESDHC_ADDR		0
+#define USDHC1_BASE_ADDR		0x5B010000
+#define USDHC2_BASE_ADDR		0x5B020000
+#define USDHC3_BASE_ADDR		0x5B030000
+
+#define FEC_QUIRK_ENET_MAC
+
+#define IMX_FEC_BASE			0x5B040000
+/* FEC1 */
+#define IMX_FEC1_BASE			0x5B040000
+/* FEC2 */
+#define IMX_FEC2_BASE			0x5B050000
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
+#else
+#define MFG_NAND_PARTITION ""
+#endif
+
+/* Incorporate settings into the U-Boot environment */
+#define CFG_EXTRA_ENV_SETTINGS
+
+#define CFG_SYS_FSL_USDHC_NUM		2
+
+#define CFG_SYS_SDRAM_BASE		0x080000000
+#define PHYS_SDRAM_1			0x080000000
+#define PHYS_SDRAM_2			0x880000000
+#define PHYS_SDRAM_1_SIZE		0x080000000	/* 2 GB */
+#define PHYS_SDRAM_2_SIZE		0x180000000	/* 6 GB */
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		8000000	/* 8MHz */
+
+#endif /* __IMX8QM_DMSSE20_H */
diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h
index 2fa93b7..1e0da9f 100644
--- a/include/configs/j721s2_evm.h
+++ b/include/configs/j721s2_evm.h
@@ -16,7 +16,7 @@
 #define CFG_SYS_SDRAM_BASE1		0x880000000
 
 /* SPL Loader Configuration */
-#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
+#if defined(CONFIG_TARGET_J721S2_A72_EVM)
 #define CFG_SYS_UBOOT_BASE		0x50280000
 /* Image load address in RAM for DFU boot*/
 #else
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
deleted file mode 100644
index 39d0b40..0000000
--- a/include/configs/omap5_uevm.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013
- * Texas Instruments Incorporated.
- * Sricharan R	  <r.sricharan@ti.com>
- *
- * Configuration settings for the TI EVM5430 board.
- * See ti_omap5_common.h for omap5 common settings.
- */
-
-#ifndef __CONFIG_OMAP5_EVM_H
-#define __CONFIG_OMAP5_EVM_H
-
-#include <environment/ti/dfu.h>
-
-#ifndef CONFIG_SPL_BUILD
-/* Define the default GPT table for eMMC */
-#define PARTS_DEFAULT \
-	"uuid_disk=${uuid_gpt_disk};" \
-	"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
-#endif
-
-#define DFUARGS \
-	"dfu_bufsiz=0x10000\0" \
-	DFU_ALT_INFO_MMC \
-	DFU_ALT_INFO_EMMC \
-	DFU_ALT_INFO_RAM
-
-#include <configs/ti_omap5_common.h>
-
-#define CFG_SYS_NS16550_COM3		UART3_BASE
-
-/* MMC ENV related defines */
-
-/* Required support for the TCA642X GPIO we have on the uEVM */
-#define CFG_SYS_I2C_TCA642X_BUS_NUM 4
-#define CFG_SYS_I2C_TCA642X_ADDR 0x22
-
-/* Enabled commands */
-
-/* USB Networking options */
-
-#define CONSOLEDEV		"ttyS2"
-
-#endif /* __CONFIG_OMAP5_EVM_H */
diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h
index 8df481b..6fbd267 100644
--- a/include/configs/px30_common.h
+++ b/include/configs/px30_common.h
@@ -24,12 +24,11 @@
 	"kernel_addr_c=0x03e80000\0" \
 	"ramdisk_addr_r=0x0a200000\0"
 
-#include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
 	ENV_MEM_LAYOUT_SETTINGS \
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"partitions=" PARTS_DEFAULT \
 	ROCKCHIP_DEVICE_SETTINGS \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index ea6073f..c2abd14 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -21,8 +21,6 @@
 	"kernel_addr_r=0x62000000\0" \
 	"ramdisk_addr_r=0x64000000\0"
 
-#include <config_distro_bootcmd.h>
-
 /* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,
  * so limit the fdt reallocation to that */
 #define CFG_EXTRA_ENV_SETTINGS \
@@ -30,6 +28,6 @@
 	"fdt_high=0x7fffffff\0" \
 	"partitions=" PARTS_DEFAULT \
 	ENV_MEM_LAYOUT_SETTINGS \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h
index 1a6d367..d70c8f7 100644
--- a/include/configs/rk3066_common.h
+++ b/include/configs/rk3066_common.h
@@ -22,14 +22,12 @@
 	"kernel_addr_r=0x62000000\0" \
 	"ramdisk_addr_r=0x64000000\0"
 
-#include <config_distro_bootcmd.h>
-
 #define CFG_EXTRA_ENV_SETTINGS \
 	"fdt_high=0x6fffffff\0" \
 	"initrd_high=0x6fffffff\0" \
 	"partitions=" PARTS_DEFAULT \
 	ENV_MEM_LAYOUT_SETTINGS \
 	ROCKCHIP_DEVICE_SETTINGS \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h
index 8736b14..d8269b0 100644
--- a/include/configs/rk3128_common.h
+++ b/include/configs/rk3128_common.h
@@ -22,11 +22,10 @@
 	"kernel_addr_r=0x62000000\0" \
 	"ramdisk_addr_r=0x64000000\0"
 
-#include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
 	ENV_MEM_LAYOUT_SETTINGS \
 	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"partitions=" PARTS_DEFAULT \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index fcb2745..a8cee1e 100644
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -21,8 +21,6 @@
 	"kernel_addr_r=0x62000000\0" \
 	"ramdisk_addr_r=0x64000000\0"
 
-#include <config_distro_bootcmd.h>
-
 /* Linux fails to load the fdt if it's loaded above 256M on a Rock board,
  * so limit the fdt reallocation to that */
 #define CFG_EXTRA_ENV_SETTINGS \
@@ -32,6 +30,6 @@
 	"partitions=" PARTS_DEFAULT \
 	ENV_MEM_LAYOUT_SETTINGS \
 	ROCKCHIP_DEVICE_SETTINGS \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
index 39a40f4..15f77df 100644
--- a/include/configs/rk322x_common.h
+++ b/include/configs/rk322x_common.h
@@ -22,8 +22,6 @@
 	"kernel_addr_r=0x62000000\0" \
 	"ramdisk_addr_r=0x64000000\0"
 
-#include <config_distro_bootcmd.h>
-
 /* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,
  * so limit the fdt reallocation to that */
 #define CFG_EXTRA_ENV_SETTINGS \
@@ -31,6 +29,6 @@
 	"fdt_high=0x7fffffff\0" \
 	"partitions=" PARTS_DEFAULT \
 	ENV_MEM_LAYOUT_SETTINGS \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 71d2426..3063076 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -23,8 +23,6 @@
 	"kernel_addr_r=0x02000000\0" \
 	"ramdisk_addr_r=0x04000000\0"
 
-#include <config_distro_bootcmd.h>
-
 /* Linux fails to load the fdt if it's loaded above 256M on a Rock 2 board, so
  * limit the fdt reallocation to that */
 #define CFG_EXTRA_ENV_SETTINGS \
@@ -34,6 +32,6 @@
 	"partitions=" PARTS_DEFAULT \
 	ENV_MEM_LAYOUT_SETTINGS \
 	ROCKCHIP_DEVICE_SETTINGS \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index ba9ee11..7d55fcd 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -20,11 +20,10 @@
 	"kernel_addr_r=0x00680000\0" \
 	"ramdisk_addr_r=0x04000000\0"
 
-#include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
 	ENV_MEM_LAYOUT_SETTINGS \
 	"partitions=" PARTS_DEFAULT \
 	ROCKCHIP_DEVICE_SETTINGS \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index e565ccf..e920ec7 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -22,11 +22,10 @@
 	"kernel_comp_addr_r=0x08000000\0" \
 	"kernel_comp_size=0x2000000\0"
 
-#include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
 	ENV_MEM_LAYOUT_SETTINGS \
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"partitions=" PARTS_DEFAULT \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index 9aa256b..ccb5369 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -23,11 +23,9 @@
 	"kernel_addr_r=0x280000\0" \
 	"ramdisk_addr_r=0x5bf0000\0"
 
-#include <config_distro_bootcmd.h>
-
 #define CFG_EXTRA_ENV_SETTINGS \
 	"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
-	ENV_MEM_LAYOUT_SETTINGS	\
-	BOOTENV
+	ENV_MEM_LAYOUT_SETTINGS \
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h
index d6b5e7d..1b7d343 100644
--- a/include/configs/rk3568_common.h
+++ b/include/configs/rk3568_common.h
@@ -27,12 +27,11 @@
 	"kernel_comp_addr_r=0x08000000\0"	\
 	"kernel_comp_size=0x2000000\0"
 
-#include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS		\
 	ENV_MEM_LAYOUT_SETTINGS			\
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"partitions=" PARTS_DEFAULT		\
-	ROCKCHIP_DEVICE_SETTINGS		\
-	BOOTENV
+	ROCKCHIP_DEVICE_SETTINGS \
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3588_common.h b/include/configs/rk3588_common.h
index b9f4271..46389d0 100644
--- a/include/configs/rk3588_common.h
+++ b/include/configs/rk3588_common.h
@@ -26,12 +26,11 @@
 	"kernel_comp_addr_r=0x08000000\0"	\
 	"kernel_comp_size=0x2000000\0"
 
-#include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"partitions=" PARTS_DEFAULT		\
 	ENV_MEM_LAYOUT_SETTINGS			\
-	ROCKCHIP_DEVICE_SETTINGS		\
-	BOOTENV
+	ROCKCHIP_DEVICE_SETTINGS \
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif /* __CONFIG_RK3588_COMMON_H */
diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
index 18544d7..9121bba 100644
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -13,69 +13,7 @@
 
 #ifndef CONFIG_SPL_BUILD
 
-/* First try to boot from SD (index 1), then eMMC (index 0) */
-#if IS_ENABLED(CONFIG_CMD_MMC)
-	#define BOOT_TARGET_MMC(func) \
-		func(MMC, mmc, 1) \
-		func(MMC, mmc, 0)
-#else
-	#define BOOT_TARGET_MMC(func)
-#endif
-
-#if IS_ENABLED(CONFIG_CMD_NVME)
-	#define BOOT_TARGET_NVME(func) func(NVME, nvme, 0)
-#else
-	#define BOOT_TARGET_NVME(func)
-#endif
-
-#if IS_ENABLED(CONFIG_CMD_SCSI)
-	#define BOOT_TARGET_SCSI(func) func(SCSI, scsi, 0)
-#else
-	#define BOOT_TARGET_SCSI(func)
-#endif
-
-#if IS_ENABLED(CONFIG_CMD_USB)
-	#define BOOT_TARGET_USB(func) func(USB, usb, 0)
-#else
-	#define BOOT_TARGET_USB(func)
-#endif
-
-#if CONFIG_IS_ENABLED(CMD_PXE)
-	#define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
-#else
-	#define BOOT_TARGET_PXE(func)
-#endif
-
-#if CONFIG_IS_ENABLED(CMD_DHCP)
-	#define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
-#else
-	#define BOOT_TARGET_DHCP(func)
-#endif
-
-#if IS_ENABLED(CONFIG_CMD_SF)
-	#define BOOT_TARGET_SF(func)	func(SF, sf, 0)
-#else
-	#define BOOT_TARGET_SF(func)
-#endif
-
-#ifdef CONFIG_ROCKCHIP_RK3399
-#define BOOT_TARGET_DEVICES(func) \
-	BOOT_TARGET_MMC(func) \
-	BOOT_TARGET_NVME(func) \
-	BOOT_TARGET_SCSI(func) \
-	BOOT_TARGET_USB(func) \
-	BOOT_TARGET_PXE(func) \
-	BOOT_TARGET_DHCP(func) \
-	BOOT_TARGET_SF(func)
 #define BOOT_TARGETS	"mmc1 mmc0 nvme scsi usb pxe dhcp spi"
-#else
-#define BOOT_TARGET_DEVICES(func) \
-	BOOT_TARGET_MMC(func) \
-	BOOT_TARGET_USB(func) \
-	BOOT_TARGET_PXE(func) \
-	BOOT_TARGET_DHCP(func)
-#define BOOT_TARGETS	"mmc1 mmc0 usb pxe dhcp"
-#endif
 
 #ifdef CONFIG_ARM64
 #define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0"
diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index 050d37b..3bf70a0 100644
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -28,6 +28,6 @@
 	ENV_MEM_LAYOUT_SETTINGS \
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"partitions=" PARTS_DEFAULT \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h
index 2211751..673268d 100644
--- a/include/configs/sdm845.h
+++ b/include/configs/sdm845.h
@@ -16,7 +16,7 @@
 #define CFG_EXTRA_ENV_SETTINGS \
 	"bootm_size=0x4000000\0"	\
 	"bootm_low=0x80000000\0"	\
-	"stdin=serial\0"	\
+	"stdin=serial,button-kbd\0"	\
 	"stdout=serial,vidconsole\0"	\
 	"stderr=serial,vidconsole\0"	\
 	"preboot=source $prevbl_initrd_start_addr:prebootscript\0" \
diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 1103174..0aa25f9 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -17,23 +17,25 @@
 /* MMC Config*/
 #define CFG_SYS_FSL_ESDHC_ADDR	0
 
-#define CFG_EXTRA_ENV_SETTINGS \
-	"image=zImage\0" \
-	"console=ttymxc0\0" \
-	"fdtfile=imx7d-smegw01.dtb\0" \
-	"fdt_addr=0x83000000\0" \
-	"bootm_size=0x10000000\0" \
-	"mmcdev=0\0" \
-	"mmcpart=1\0" \
-	"mmcargs=setenv bootargs console=${console},${baudrate} " \
-		"root=/dev/mmcblk0p${mmcpart} rootwait rw\0" \
-	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
-	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
-	"mmcboot=echo Booting from mmc ...; " \
-		"run mmcargs; " \
-		"if run loadfdt; then " \
-			"bootz ${loadaddr} - ${fdt_addr}; " \
-		"fi;\0" \
+/* default to no extra bootparams, we need an empty define for stringification*/
+#ifndef EXTRA_BOOTPARAMS
+#define EXTRA_BOOTPARAMS
+#endif
+
+#ifdef CONFIG_SYS_BOOT_LOCKED
+#define EXTRA_ENV_FLAGS
+#else
+#define EXTRA_ENV_FLAGS "mmcdev:dw,"
+#endif
+
+#define CFG_ENV_FLAGS_LIST_STATIC \
+	"mmcpart:dw," \
+	"mmcpart_committed:dw," \
+	"ustate:dw," \
+	"bootcount:dw," \
+	"bootlimit:dw," \
+	"upgrade_available:dw," \
+	EXTRA_ENV_FLAGS
 
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index d54c208..149a74d 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -55,7 +55,8 @@
 		"do;" \
 		"setenv overlaystring ${overlaystring}'#'${overlay};" \
 		"done;\0" \
-	"run_fit=bootm ${addr_fit}#conf-${fdtfile}${overlaystring}\0" \
+	"get_fit_config=setexpr name_fit_config gsub / _ conf-${fdtfile}\0" \
+	"run_fit=run get_fit_config; bootm ${addr_fit}#${name_fit_config}${overlaystring}\0" \
 
 /*
  * DDR information.  If the CONFIG_NR_DRAM_BANKS is not defined,
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 576237b..307ad69 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -56,6 +56,7 @@
 	UCLASS_EFI_MEDIA,	/* Devices provided by UEFI firmware */
 	UCLASS_ETH,		/* Ethernet device */
 	UCLASS_ETH_PHY,		/* Ethernet PHY device */
+	UCLASS_EXTCON,		/* External Connector Class */
 	UCLASS_FIRMWARE,	/* Firmware */
 	UCLASS_FPGA,		/* FPGA device */
 	UCLASS_FUZZING_ENGINE,	/* Fuzzing engine */
@@ -89,6 +90,7 @@
 	UCLASS_NOP,		/* No-op devices */
 	UCLASS_NORTHBRIDGE,	/* Intel Northbridge / SDRAM controller */
 	UCLASS_NVME,		/* NVM Express device */
+	UCLASS_NVMXIP,		/* NVM XIP devices */
 	UCLASS_P2SB,		/* (x86) Primary-to-Sideband Bus */
 	UCLASS_PANEL,		/* Display panel, such as an LCD */
 	UCLASS_PANEL_BACKLIGHT,	/* Backlight controller for panel */
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index ee15c92..456eef7 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -265,6 +265,23 @@
 				struct udevice **devp);
 
 /**
+ * uclass_get_device_by_of_path() - Get a uclass device by device tree path
+ *
+ * This searches the devices in the uclass for one attached to the
+ * device tree node corresponding to the given path (which may also be
+ * an alias).
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @id: ID to look up
+ * @path: Device tree path to search for (if no such path then -ENODEV is returned)
+ * @devp: Returns pointer to device (there is only one for each node)
+ * Return: 0 if OK, -ve on error
+ */
+int uclass_get_device_by_of_path(enum uclass_id id, const char *path,
+				 struct udevice **devp);
+
+/**
  * uclass_get_device_by_phandle_id() - Get a uclass device by phandle id
  *
  * This searches the devices in the uclass for one with the given phandle id.
diff --git a/include/dt-bindings/clock/bcm-nsp.h b/include/dt-bindings/clock/bcm-nsp.h
new file mode 100644
index 0000000..ad5827c
--- /dev/null
+++ b/include/dt-bindings/clock/bcm-nsp.h
@@ -0,0 +1,51 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *	* Redistributions of source code must retain the above copyright
+ *	  notice, this list of conditions and the following disclaimer.
+ *	* Redistributions in binary form must reproduce the above copyright
+ *	  notice, this list of conditions and the following disclaimer in
+ *	  the documentation and/or other materials provided with the
+ *	  distribution.
+ *	* Neither the name of Broadcom Corporation nor the names of its
+ *	  contributors may be used to endorse or promote products derived
+ *	  from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_NSP_H
+#define _CLOCK_BCM_NSP_H
+
+/* GENPLL clock channel ID */
+#define BCM_NSP_GENPLL			0
+#define BCM_NSP_GENPLL_PHY_CLK		1
+#define BCM_NSP_GENPLL_ENET_SW_CLK	2
+#define BCM_NSP_GENPLL_USB_PHY_REF_CLK	3
+#define BCM_NSP_GENPLL_IPROCFAST_CLK	4
+#define BCM_NSP_GENPLL_SATA1_CLK	5
+#define BCM_NSP_GENPLL_SATA2_CLK	6
+
+/* LCPLL0 clock channel ID */
+#define BCM_NSP_LCPLL0			0
+#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK	1
+#define BCM_NSP_LCPLL0_SDIO_CLK		2
+#define BCM_NSP_LCPLL0_DDR_PHY_CLK	3
+
+#endif /* _CLOCK_BCM_NSP_H */
diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h
index 136de247..8a05790 100644
--- a/include/dt-bindings/clock/histb-clock.h
+++ b/include/dt-bindings/clock/histb-clock.h
@@ -70,6 +70,18 @@
 #define HISTB_USB3_UTMI_CLK1		48
 #define HISTB_USB3_PIPE_CLK1		49
 #define HISTB_USB3_SUSPEND_CLK1		50
+#define HISTB_SDIO1_BIU_CLK		51
+#define HISTB_SDIO1_CIU_CLK		52
+#define HISTB_SDIO1_DRV_CLK		53
+#define HISTB_SDIO1_SAMPLE_CLK		54
+
+/* Hi3798MV200 specific clocks */
+
+// reuse clocks of histb
+#define HI3798MV200_GMAC_CLK		HISTB_ETH0_MAC_CLK
+#define HI3798MV200_GMACIF_CLK		HISTB_ETH0_MACIF_CLK
+#define HI3798MV200_FEMAC_CLK		HISTB_ETH1_MAC_CLK
+#define HI3798MV200_FEMACIF_CLK		HISTB_ETH1_MACIF_CLK
 
 /* clocks provided by mcu CRG */
 #define HISTB_MCE_CLK			1
diff --git a/include/environment/ti/ti_armv7_common.env b/include/environment/ti/ti_armv7_common.env
index 4d33464..0c0929d 100644
--- a/include/environment/ti/ti_armv7_common.env
+++ b/include/environment/ti/ti_armv7_common.env
@@ -20,5 +20,6 @@
 	do;
 	setenv overlaystring ${overlaystring}'#'${overlay};
 	done;
-run_fit=bootm ${addr_fit}#conf-${fdtfile}${overlaystring}
+get_fit_config=setexpr name_fit_config gsub / _ conf-${fdtfile}
+run_fit=run get_fit_config; bootm ${addr_fit}#${name_fit_config}${overlaystring}
 
diff --git a/include/extcon.h b/include/extcon.h
new file mode 100644
index 0000000..d060f5a
--- /dev/null
+++ b/include/extcon.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef __EXTCON_H
+#define __EXTCON_H
+
+struct udevice;
+
+/**
+ * struct extcon_uc_plat - Platform data the uclass stores about each device
+ *
+ * To be filled
+ */
+struct extcon_uc_plat {
+};
+
+#endif
diff --git a/include/fdt_simplefb.h b/include/fdt_simplefb.h
index 41cd740..af93e3b 100644
--- a/include/fdt_simplefb.h
+++ b/include/fdt_simplefb.h
@@ -9,6 +9,5 @@
 #ifndef _FDT_SIMPLEFB_H_
 #define _FDT_SIMPLEFB_H_
 int fdt_simplefb_add_node(void *blob);
-int fdt_simplefb_enable_existing_node(void *blob);
 int fdt_simplefb_enable_and_mem_rsv(void *blob);
 #endif
diff --git a/include/fdtdec.h b/include/fdtdec.h
index aa61a0f..6716da9 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -187,7 +187,6 @@
 	COMPAT_INTEL_BAYTRAIL_FSP,	/* Intel Bay Trail FSP */
 	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP memory-down params */
 	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel Ivy Bridge FSP */
-	COMPAT_SUNXI_NAND,		/* SUNXI NAND controller */
 	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock initialization */
 	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/* SoCFPGA pinctrl-single */
 	COMPAT_ALTERA_SOCFPGA_H2F_BRG,          /* SoCFPGA hps2fpga bridge */
diff --git a/include/ide.h b/include/ide.h
index 426cef4..2c25e74 100644
--- a/include/ide.h
+++ b/include/ide.h
@@ -11,50 +11,14 @@
 
 #define IDE_BUS(dev)	(dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS))
 
-#define	ATA_CURR_BASE(dev)	(CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
-extern ulong ide_bus_offset[];
-
-/*
- * Function Prototypes
- */
-
-void ide_init(void);
-struct blk_desc;
-struct udevice;
-#ifdef CONFIG_BLK
-ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
-	       void *buffer);
-ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
-		const void *buffer);
-#else
-ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
-	       void *buffer);
-ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
-		const void *buffer);
-#endif
-
-#if defined(CONFIG_OF_IDE_FIXUP)
-int ide_device_present(int dev);
-#endif
-
-/*
- * I/O function overrides
- */
-unsigned char ide_inb(int dev, int port);
-void ide_outb(int dev, int port, unsigned char val);
-void ide_input_swap_data(int dev, ulong *sect_buf, int words);
-void ide_input_data(int dev, ulong *sect_buf, int words);
-void ide_output_data(int dev, const ulong *sect_buf, int words);
-void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts);
-void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts);
-
-void ide_led(uchar led, uchar status);
-
 /**
- * board_start_ide() - Start up the board IDE interfac
+ * ide_set_reset() - Assert or de-assert reset for the IDE device
  *
- * Return: 0 if ok
+ * This is provided by boards which need to reset the device through another
+ * means, e.g. a GPIO.
+ *
+ * @idereset: 1 to assert reset, 0 to de-assert it
  */
-int board_start_ide(void);
+void ide_set_reset(int idereset);
 
 #endif /* _IDE_H */
diff --git a/include/os.h b/include/os.h
index 0415f0f..968412b 100644
--- a/include/os.h
+++ b/include/os.h
@@ -64,7 +64,7 @@
  * @fd:		File descriptor as returned by os_open()
  * Return:	file size or negative error code
  */
-int os_filesize(int fd);
+off_t os_filesize(int fd);
 
 /**
  * Access to the OS open() system call
diff --git a/include/virtio_ring.h b/include/virtio_ring.h
index c77c212..e8e9104 100644
--- a/include/virtio_ring.h
+++ b/include/virtio_ring.h
@@ -86,6 +86,8 @@
 
 struct vring {
 	unsigned int num;
+	size_t size;
+	struct bounce_buffer *bouncebufs;
 	struct vring_desc *desc;
 	struct vring_avail *avail;
 	struct vring_used *used;
@@ -137,23 +139,26 @@
 #define vring_used_event(vr)	((vr)->avail->ring[(vr)->num])
 #define vring_avail_event(vr)	(*(__virtio16 *)&(vr)->used->ring[(vr)->num])
 
+static inline unsigned int vring_size(unsigned int num, unsigned long align)
+{
+	return ((sizeof(struct vring_desc) * num +
+		sizeof(__virtio16) * (3 + num)  + align - 1) & ~(align - 1)) +
+		sizeof(__virtio16) * 3 + sizeof(struct vring_used_elem) * num;
+}
+
 static inline void vring_init(struct vring *vr, unsigned int num, void *p,
-			      unsigned long align)
+			      unsigned long align,
+			      struct bounce_buffer *bouncebufs)
 {
 	vr->num = num;
+	vr->size = vring_size(num, align);
+	vr->bouncebufs = bouncebufs;
 	vr->desc = p;
 	vr->avail = p + num * sizeof(struct vring_desc);
 	vr->used = (void *)(((uintptr_t)&vr->avail->ring[num] +
 		   sizeof(__virtio16) + align - 1) & ~(align - 1));
 }
 
-static inline unsigned int vring_size(unsigned int num, unsigned long align)
-{
-	return ((sizeof(struct vring_desc) * num +
-		sizeof(__virtio16) * (3 + num)  + align - 1) & ~(align - 1)) +
-		sizeof(__virtio16) * 3 + sizeof(struct vring_used_elem) * num;
-}
-
 /*
  * The following is used with USED_EVENT_IDX and AVAIL_EVENT_IDX.
  * Assuming a given event_idx value from the other side, if we have just
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 0827e16..c60972d 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1,6 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * NOTE: Please do not add new devicetree-reading functionality into this file.
+ * Add it to the ofnode API instead, since that is compatible with livetree.
  */
 
 #ifndef USE_HOSTCC
@@ -65,7 +68,6 @@
 	COMPAT(INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
 	COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
 	COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
-	COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
 	COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
 	COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
 	COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"),
diff --git a/test/Kconfig b/test/Kconfig
index 4650282..6e859fb 100644
--- a/test/Kconfig
+++ b/test/Kconfig
@@ -3,7 +3,9 @@
 	help
 	  See doc/README.POST for more details
 
-menuconfig UNIT_TEST
+menu "Unit tests"
+
+config UNIT_TEST
 	bool "Unit tests"
 	help
 	  Select this to compile in unit tests for various parts of
@@ -107,3 +109,5 @@
 source "test/lib/Kconfig"
 source "test/optee/Kconfig"
 source "test/overlay/Kconfig"
+
+endmenu
diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c
index 4fe9fd7..8cf3f30 100644
--- a/test/boot/bootdev.c
+++ b/test/boot/bootdev.c
@@ -124,7 +124,8 @@
 		    mflags);
 
 	/* Check invalid uclass */
-	ut_asserteq(-EINVAL, bootdev_find_by_label("fred0", &dev, &mflags));
+	ut_asserteq(-EPFNOSUPPORT,
+		    bootdev_find_by_label("fred0", &dev, &mflags));
 
 	/* Check unknown sequence number */
 	ut_asserteq(-ENOENT, bootdev_find_by_label("mmc6", &dev, &mflags));
@@ -179,9 +180,8 @@
 
 	/* Check invalid uclass */
 	mflags = 123;
-	ut_asserteq(-EINVAL, bootdev_find_by_any("fred0", &dev, &mflags));
-	ut_assert_nextline("Unknown uclass 'fred0' in label");
-	ut_assert_nextline("Cannot find bootdev 'fred0' (err=-22)");
+	ut_asserteq(-EPFNOSUPPORT, bootdev_find_by_any("fred0", &dev, &mflags));
+	ut_assert_nextline("Cannot find bootdev 'fred0' (err=-96)");
 	ut_asserteq(123, mflags);
 	ut_assert_console_end();
 
@@ -376,7 +376,6 @@
 	ut_assert_nextline("Hunting with: simple_bus");
 	ut_assert_nextline("Found 2 extension board(s).");
 	ut_assert_nextline("Hunting with: ide");
-	ut_assert_nextline("Bus 0: not available  ");
 
 	/* mmc hunter has already been used so should not run again */
 
@@ -487,7 +486,6 @@
 	/* now try a different priority, verbosely */
 	ut_assertok(bootdev_hunt_prio(BOOTDEVP_5_SCAN_SLOW, true));
 	ut_assert_nextline("Hunting with: ide");
-	ut_assert_nextline("Bus 0: not available  ");
 	ut_assert_nextline("Hunting with: usb");
 	ut_assert_nextline(
 		"Bus usb@1: scanning bus usb@1 for devices... 5 USB Device(s) found");
@@ -512,9 +510,8 @@
 	old = (void *)&mflags;   /* arbitrary pointer to check against dev */
 	dev = old;
 	mflags = 123;
-	ut_asserteq(-EINVAL,
+	ut_asserteq(-EPFNOSUPPORT,
 		    bootdev_hunt_and_find_by_label("fred", &dev, &mflags));
-	ut_assert_nextline("Unknown uclass 'fred' in label");
 	ut_asserteq_ptr(old, dev);
 	ut_asserteq(123, mflags);
 	ut_assert_console_end();
@@ -525,7 +522,6 @@
 		    bootdev_hunt_and_find_by_label("mmc4", &dev, &mflags));
 	ut_asserteq_ptr(old, dev);
 	ut_asserteq(123, mflags);
-	ut_assert_nextline("Unknown seq 4 for label 'mmc4'");
 	ut_assert_console_end();
 
 	ut_assertok(bootstd_test_check_mmc_hunter(uts));
diff --git a/test/cmd/fdt.c b/test/cmd/fdt.c
index 7835da2..1f103a1 100644
--- a/test/cmd/fdt.c
+++ b/test/cmd/fdt.c
@@ -2,7 +2,7 @@
 /*
  * Tests for fdt command
  *
- * Copyright 2022 Google LLCmap_to_sysmem(fdt));
+ * Copyright 2022 Google LLC
  */
 
 #include <common.h>
diff --git a/test/dm/Makefile b/test/dm/Makefile
index e15bdbf..3799b1a 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 # Copyright (c) 2013 Google, Inc
+# Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
 
 obj-$(CONFIG_UT_DM) += test-dm.o
 
@@ -17,6 +18,10 @@
 obj-$(CONFIG_UT_DM) += core.o
 obj-$(CONFIG_UT_DM) += read.o
 obj-$(CONFIG_UT_DM) += phys2bus.o
+ifeq ($(CONFIG_NVMXIP_QSPI)$(CONFIG_SANDBOX64),yy)
+obj-y += nvmxip.o
+endif
+
 ifneq ($(CONFIG_SANDBOX),)
 ifeq ($(CONFIG_ACPIGEN),y)
 obj-y += acpi.o
@@ -44,6 +49,7 @@
 obj-$(CONFIG_ECDSA_VERIFY) += ecdsa.o
 obj-$(CONFIG_EFI_MEDIA_SANDBOX) += efi_media.o
 obj-$(CONFIG_DM_ETH) += eth.o
+obj-$(CONFIG_EXTCON) += extcon.o
 ifneq ($(CONFIG_EFI_PARTITION),)
 obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fastboot.o
 endif
diff --git a/test/dm/extcon.c b/test/dm/extcon.c
new file mode 100644
index 0000000..6a4e22b
--- /dev/null
+++ b/test/dm/extcon.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <dm/test.h>
+#include <extcon.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+static int dm_test_extcon(struct unit_test_state *uts)
+{
+	struct udevice *dev;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_EXTCON, "extcon", &dev));
+
+	return 0;
+}
+
+DM_TEST(dm_test_extcon, UT_TESTF_SCAN_FDT);
diff --git a/test/dm/nvmxip.c b/test/dm/nvmxip.c
new file mode 100644
index 0000000..e934748
--- /dev/null
+++ b/test/dm/nvmxip.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Functional tests for UCLASS_FFA  class
+ *
+ * Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#include <common.h>
+#include <blk.h>
+#include <console.h>
+#include <dm.h>
+#include <mapmem.h>
+#include <dm/test.h>
+#include <linux/bitops.h>
+#include <test/test.h>
+#include <test/ut.h>
+#include "../../drivers/mtd/nvmxip/nvmxip.h"
+
+/* NVMXIP devices described in the device tree */
+#define SANDBOX_NVMXIP_DEVICES 2
+
+/* reference device tree data for the probed devices */
+static struct nvmxip_plat nvmqspi_refdata[SANDBOX_NVMXIP_DEVICES] = {
+	{0x08000000, 9, 4096}, {0x08200000, 9, 2048}
+};
+
+#define NVMXIP_BLK_START_PATTERN 0x1122334455667788ULL
+#define NVMXIP_BLK_END_PATTERN 0xa1a2a3a4a5a6a7a8ULL
+
+/**
+ * dm_nvmxip_flash_sanity() - check flash data
+ * @uts: test state
+ * @device_idx:	the NVMXIP device index
+ * @buffer:	the user buffer where the blocks data is copied to
+ *
+ * Mode 1: When buffer is NULL, initialize the flash with pattern data at the start
+ * and at the end of each block. This pattern data will be used to check data consistency
+ * when verifying the data read.
+ * Mode 2: When the user buffer is provided in the argument (not NULL), compare the data
+ * of the start and the end of each block in the user buffer with the expected pattern data.
+ * Return an error when the check fails.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int dm_nvmxip_flash_sanity(struct unit_test_state *uts, u8 device_idx, void *buffer)
+{
+	int i;
+	u64 *ptr;
+	u8 *base;
+	unsigned long blksz;
+
+	blksz = BIT(nvmqspi_refdata[device_idx].lba_shift);
+
+	if (!buffer) {
+		/* Mode 1: point at the flash start address. Pattern data will be written */
+		base = map_sysmem(nvmqspi_refdata[device_idx].phys_base, 0);
+	} else {
+		/* Mode 2: point at the user buffer containing the data read and to be verified */
+		base = buffer;
+	}
+
+	for (i = 0; i < nvmqspi_refdata[device_idx].lba ; i++) {
+		ptr = (u64 *)(base + i * blksz);
+
+		/* write an 8 bytes pattern at the start of the current block */
+		if (!buffer)
+			*ptr = NVMXIP_BLK_START_PATTERN;
+		else
+			ut_asserteq_64(NVMXIP_BLK_START_PATTERN, *ptr);
+
+		ptr = (u64 *)((u8 *)ptr + blksz - sizeof(u64));
+
+		/* write an 8 bytes pattern at the end of the current block */
+		if (!buffer)
+			*ptr = NVMXIP_BLK_END_PATTERN;
+		else
+			ut_asserteq_64(NVMXIP_BLK_END_PATTERN, *ptr);
+	}
+
+	if (!buffer)
+		unmap_sysmem(base);
+
+	return 0;
+}
+
+/**
+ * dm_test_nvmxip() - check flash data
+ * @uts: test state
+ * Return:
+ *
+ * CMD_RET_SUCCESS on success. Otherwise, failure
+ */
+static int dm_test_nvmxip(struct unit_test_state *uts)
+{
+	struct nvmxip_plat *plat_data = NULL;
+	struct udevice *dev = NULL, *bdev = NULL;
+	u8 device_idx;
+	void *buffer = NULL;
+	unsigned long flashsz;
+
+	/* set the flash content first for both devices */
+	dm_nvmxip_flash_sanity(uts, 0, NULL);
+	dm_nvmxip_flash_sanity(uts, 1, NULL);
+
+	/* probing all NVM XIP QSPI devices */
+	for (device_idx = 0, uclass_first_device(UCLASS_NVMXIP, &dev);
+	     dev;
+	     uclass_next_device(&dev), device_idx++) {
+		plat_data = dev_get_plat(dev);
+
+		/* device tree entries checks */
+		ut_assertok(nvmqspi_refdata[device_idx].phys_base != plat_data->phys_base);
+		ut_assertok(nvmqspi_refdata[device_idx].lba_shift != plat_data->lba_shift);
+		ut_assertok(nvmqspi_refdata[device_idx].lba != plat_data->lba);
+
+		/* before reading all the flash blocks, let's calculate the flash size */
+		flashsz = plat_data->lba << plat_data->lba_shift;
+
+		/* allocate the user buffer where to copy the blocks data to */
+		buffer = calloc(flashsz, 1);
+		ut_assertok(!buffer);
+
+		/* the block device is the child of the parent device probed with DT */
+		ut_assertok(device_find_first_child(dev, &bdev));
+
+		/* reading all the flash blocks */
+		ut_asserteq(plat_data->lba, blk_read(bdev, 0, plat_data->lba, buffer));
+
+		/* compare the data read from flash with the expected data */
+		dm_nvmxip_flash_sanity(uts, device_idx, buffer);
+
+		free(buffer);
+	}
+
+	ut_assertok(device_idx != SANDBOX_NVMXIP_DEVICES);
+
+	return CMD_RET_SUCCESS;
+}
+
+DM_TEST(dm_test_nvmxip, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
index 8e6e42e..eeecd1d 100644
--- a/test/dm/test-fdt.c
+++ b/test/dm/test-fdt.c
@@ -617,6 +617,7 @@
 {
 	struct udevice *gpio, *dev;
 	void *ptr;
+	void *paddr;
 
 	/* Test for missing reg property */
 	ut_assertok(uclass_first_device_err(UCLASS_GPIO, &gpio));
@@ -624,7 +625,9 @@
 
 	ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, &dev));
 	ptr = devfdt_get_addr_ptr(dev);
-	ut_asserteq_ptr((void *)0x8000, ptr);
+
+	paddr = map_sysmem(0x8000, 0);
+	ut_asserteq_ptr(paddr, ptr);
 
 	return 0;
 }
diff --git a/test/lib/Kconfig b/test/lib/Kconfig
index dbb03e4..ae0aa2f 100644
--- a/test/lib/Kconfig
+++ b/test/lib/Kconfig
@@ -1,23 +1,24 @@
 # SPDX-License-Identifier: GPL-2.0+
 # Copyright 2022 Google LLC
 
-if SANDBOX
-
 config TEST_KCONFIG
 	bool "Enable detection of Kconfig macro errors"
+	depends on SANDBOX
 	help
 	  This is used to test that the IF_ENABLED_INT() macro causes a build error
-	  if the value is used when the CONFIG Is not enabled.
+	  if the value is used when the CONFIG is not enabled.
+
+if TEST_KCONFIG
 
 config TEST_KCONFIG_ENABLE
-	bool "Option to enable"
+	bool "Provide a value for the Kconfig test"
 	help
 	  This is the option that controls whether the value is present.
 
 config TEST_KCONFIG_VALUE
-	int "Value associated with the option"
+	int "Value used in Kconfig test"
 	depends on TEST_KCONFIG_ENABLE
 	help
-	  This is the value whgch is present if TEST_KCONFIG_ENABLE is enabled.
+	  This is the value which is present if TEST_KCONFIG_ENABLE is enabled.
 
-endif # SANDBOX
+endif # TEST_KCONFIG
diff --git a/test/py/tests/test_efi_bootmgr/conftest.py b/test/py/tests/test_efi_bootmgr/conftest.py
index a0a754a..eabafa5 100644
--- a/test/py/tests/test_efi_bootmgr/conftest.py
+++ b/test/py/tests/test_efi_bootmgr/conftest.py
@@ -1,7 +1,6 @@
 # SPDX-License-Identifier:      GPL-2.0+
 
-"""Fixture for UEFI bootmanager test
-"""
+"""Fixture for UEFI bootmanager test."""
 
 import os
 import shutil
@@ -10,8 +9,7 @@
 
 @pytest.fixture(scope='session')
 def efi_bootmgr_data(u_boot_config):
-    """Set up a file system to be used in UEFI bootmanager
-       tests
+    """Set up a file system to be used in UEFI bootmanager tests.
 
     Args:
         u_boot_config -- U-boot configuration.
diff --git a/test/py/tests/test_efi_capsule/capsule_defs.py b/test/py/tests/test_efi_capsule/capsule_defs.py
index 59b40f1..3cc695e 100644
--- a/test/py/tests/test_efi_capsule/capsule_defs.py
+++ b/test/py/tests/test_efi_capsule/capsule_defs.py
@@ -1,5 +1,7 @@
 # SPDX-License-Identifier:      GPL-2.0+
 
+"""Directoreis used for authentication and capsule tests."""
+
 # Directories
 CAPSULE_DATA_DIR = '/EFI/CapsuleTestData'
 CAPSULE_INSTALL_DIR = '/EFI/UpdateCapsule'
diff --git a/test/py/tests/test_efi_capsule/conftest.py b/test/py/tests/test_efi_capsule/conftest.py
index 0e5137d..a337e62 100644
--- a/test/py/tests/test_efi_capsule/conftest.py
+++ b/test/py/tests/test_efi_capsule/conftest.py
@@ -2,8 +2,7 @@
 # Copyright (c) 2020, Linaro Limited
 # Author: AKASHI Takahiro <takahiro.akashi@linaro.org>
 
-"""Fixture for UEFI capsule test
-"""
+"""Fixture for UEFI capsule test."""
 
 from subprocess import call, check_call, CalledProcessError
 import pytest
@@ -11,13 +10,15 @@
 
 @pytest.fixture(scope='session')
 def efi_capsule_data(request, u_boot_config):
-    """Set up a file system to be used in UEFI capsule and authentication test
-    and return a ath to disk image to be used for testing
+    """Set up a file system and return path to image.
+
+    The function sets up a file system to be used in UEFI capsule and
+    authentication test and returns a path to disk image to be used
+    for testing.
 
     request -- Pytest request object.
     u_boot_config -- U-boot configuration.
     """
-
     mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
     data_dir = mnt_point + CAPSULE_DATA_DIR
     install_dir = mnt_point + CAPSULE_INSTALL_DIR
diff --git a/test/py/tests/test_efi_secboot/conftest.py b/test/py/tests/test_efi_secboot/conftest.py
index 65cde7a..30ff702 100644
--- a/test/py/tests/test_efi_secboot/conftest.py
+++ b/test/py/tests/test_efi_secboot/conftest.py
@@ -2,7 +2,7 @@
 # Copyright (c) 2019, Linaro Limited
 # Author: AKASHI Takahiro <takahiro.akashi@linaro.org>
 
-""" Fixture for UEFI secure boot test """
+"""Fixture for UEFI secure boot test."""
 
 from subprocess import call, check_call, CalledProcessError
 import pytest
@@ -132,7 +132,9 @@
 
 @pytest.fixture(scope='session')
 def efi_boot_env_intca(request, u_boot_config):
-    """Set up a file system to be used in UEFI secure boot test
+    """Set up file system for secure boot test.
+
+    Set up a file system to be used in UEFI secure boot test
     of intermediate certificates.
 
     Args:
diff --git a/test/py/tests/test_efi_secboot/defs.py b/test/py/tests/test_efi_secboot/defs.py
index b7a2a11..6a2317e 100644
--- a/test/py/tests/test_efi_secboot/defs.py
+++ b/test/py/tests/test_efi_secboot/defs.py
@@ -1,5 +1,7 @@
 # SPDX-License-Identifier:      GPL-2.0+
 
+"""Constants used for secure boot test."""
+
 # Owner guid
 GUID = '11111111-2222-3333-4444-123456789abc'
 
diff --git a/test/py/tests/test_efi_selftest.py b/test/py/tests/test_efi_selftest.py
index e92d63c..43f2424 100644
--- a/test/py/tests/test_efi_selftest.py
+++ b/test/py/tests/test_efi_selftest.py
@@ -7,7 +7,7 @@
 import pytest
 
 @pytest.mark.buildconfigspec('cmd_bootefi_selftest')
-def test_efi_selftest(u_boot_console):
+def test_efi_selftest_base(u_boot_console):
     """Run UEFI unit tests
 
     u_boot_console -- U-Boot console
diff --git a/test/py/tests/test_hush_if_test.py b/test/py/tests/test_hush_if_test.py
index 37c1608..3b4b6fc 100644
--- a/test/py/tests/test_hush_if_test.py
+++ b/test/py/tests/test_hush_if_test.py
@@ -182,3 +182,16 @@
 
     expr = 'test -e hostfs - ' + test_file
     exec_hush_if(u_boot_console, expr, False)
+
+def test_hush_var(u_boot_console):
+    """Test the set and unset of variables"""
+    u_boot_console.run_command('ut_var_nonexistent=')
+    u_boot_console.run_command('ut_var_exists=1')
+    u_boot_console.run_command('ut_var_unset=1')
+    exec_hush_if(u_boot_console, 'test -z "$ut_var_nonexistent"', True)
+    exec_hush_if(u_boot_console, 'test -z "$ut_var_exists"', False)
+    exec_hush_if(u_boot_console, 'test -z "$ut_var_unset"', False)
+    exec_hush_if(u_boot_console, 'ut_var_unset=', True)
+    exec_hush_if(u_boot_console, 'test -z "$ut_var_unset"', True)
+    u_boot_console.run_command('ut_var_exists=')
+    u_boot_console.run_command('ut_var_unset=')
diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
index e8c8a6d..0b45863 100644
--- a/test/py/tests/test_ut.py
+++ b/test/py/tests/test_ut.py
@@ -213,7 +213,7 @@
               str(exc))
     finally:
         if mounted:
-            u_boot_utils.run_and_log(cons, 'sudo umount %s' % mnt)
+            u_boot_utils.run_and_log(cons, 'sudo umount --lazy %s' % mnt)
         if loop:
             u_boot_utils.run_and_log(cons, 'sudo losetup -d %s' % loop)
 
@@ -274,7 +274,7 @@
               str(exc))
     finally:
         if mounted:
-            u_boot_utils.run_and_log(cons, 'sudo umount %s' % mnt)
+            u_boot_utils.run_and_log(cons, 'sudo umount --lazy %s' % mnt)
         if loop:
             u_boot_utils.run_and_log(cons, 'sudo losetup -d %s' % loop)
 
diff --git a/tools/binman/cmdline.py b/tools/binman/cmdline.py
index 4b875a9..9632ec1 100644
--- a/tools/binman/cmdline.py
+++ b/tools/binman/cmdline.py
@@ -95,7 +95,7 @@
     parser.add_argument('-H', '--full-help', action='store_true',
         default=False, help='Display the README file')
     parser.add_argument('--tooldir', type=str,
-        default=os.path.join(os.getenv('HOME'), '.binman-tools'),
+        default=os.path.join(os.path.expanduser('~/.binman-tools')),
         help='Set the directory to store tools')
     parser.add_argument('--toolpath', type=str, action='append',
         help='Add a path to the list of directories containing tools')
diff --git a/tools/binman/control.py b/tools/binman/control.py
index 0febcb7..68597c4 100644
--- a/tools/binman/control.py
+++ b/tools/binman/control.py
@@ -7,7 +7,11 @@
 
 from collections import OrderedDict
 import glob
-import importlib.resources
+try:
+    import importlib.resources
+except ImportError:
+    # for Python 3.6
+    import importlib_resources
 import os
 import pkg_resources
 import re
diff --git a/tools/binman/test/blob_syms.c b/tools/binman/test/blob_syms.c
index d652c79..1df8d64 100644
--- a/tools/binman/test/blob_syms.c
+++ b/tools/binman/test/blob_syms.c
@@ -5,8 +5,6 @@
  * Simple program to create some binman symbols. This is used by binman tests.
  */
 
-typedef unsigned long ulong;
-
 #include <linux/kconfig.h>
 #include <binman_sym.h>
 
diff --git a/tools/binman/test/u_boot_binman_syms.c b/tools/binman/test/u_boot_binman_syms.c
index ed76124..147c902 100644
--- a/tools/binman/test/u_boot_binman_syms.c
+++ b/tools/binman/test/u_boot_binman_syms.c
@@ -5,8 +5,6 @@
  * Simple program to create some binman symbols. This is used by binman tests.
  */
 
-typedef unsigned long ulong;
-
 #include <linux/kconfig.h>
 #include <binman_sym.h>
 
diff --git a/tools/binman/test/u_boot_binman_syms_size.c b/tools/binman/test/u_boot_binman_syms_size.c
index fa41b3d..f686892 100644
--- a/tools/binman/test/u_boot_binman_syms_size.c
+++ b/tools/binman/test/u_boot_binman_syms_size.c
@@ -5,8 +5,6 @@
  * Simple program to create some binman symbols. This is used by binman tests.
  */
 
-typedef unsigned long ulong;
-
 #include <linux/kconfig.h>
 #include <binman_sym.h>
 
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index 879ff138..635865c 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -253,6 +253,7 @@
                     args.extend(['-j', str(self.builder.num_jobs)])
                 if self.builder.warnings_as_errors:
                     args.append('KCFLAGS=-Werror')
+                    args.append('HOSTCFLAGS=-Werror')
                 if self.builder.allow_missing:
                     args.append('BINMAN_ALLOW_MISSING=1')
                 if self.builder.no_lto:
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index 35f44c0..09a11f2 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -3,7 +3,11 @@
 #
 
 import multiprocessing
-import importlib.resources
+try:
+    import importlib.resources
+except ImportError:
+    # for Python 3.6
+    import importlib_resources
 import os
 import shutil
 import subprocess
diff --git a/tools/dtoc/test_fdt.py b/tools/dtoc/test_fdt.py
index 32fa69c..4fe8d12 100755
--- a/tools/dtoc/test_fdt.py
+++ b/tools/dtoc/test_fdt.py
@@ -784,8 +784,8 @@
 
     def test_ensure_compiled_tmpdir(self):
         """Test providing a temporary directory"""
+        old_outdir = tools.outdir
         try:
-            old_outdir = tools.outdir
             tools.outdir= None
             tmpdir = tempfile.mkdtemp(prefix='test_fdt.')
             dtb = fdt_util.EnsureCompiled(find_dtb_file('dtoc_test_simple.dts'),
@@ -793,7 +793,7 @@
             self.assertEqual(tmpdir, os.path.dirname(dtb))
             shutil.rmtree(tmpdir)
         finally:
-            tools.outdir= old_outdir
+            tools.outdir = old_outdir
 
     def test_get_phandle_name_offset(self):
         val = fdt_util.GetPhandleNameOffset(self.node, 'missing')
diff --git a/tools/env/README b/tools/env/README
index 7092513..480a893 100644
--- a/tools/env/README
+++ b/tools/env/README
@@ -59,5 +59,5 @@
 within which bad blocks are skipped, on NOR it is not used.
 
 To prevent losing changes to the environment and to prevent confusing the MTD
-drivers, a lock file at /var/lock/fw_printenv.lock is used to serialize access
+drivers, a lock file at /run/fw_printenv.lock is used to serialize access
 to the environment.
diff --git a/tools/patman/__main__.py b/tools/patman/__main__.py
index 48ffbc8..8eba5d3 100755
--- a/tools/patman/__main__.py
+++ b/tools/patman/__main__.py
@@ -7,7 +7,11 @@
 """See README for more information"""
 
 from argparse import ArgumentParser
-import importlib.resources
+try:
+    import importlib.resources
+except ImportError:
+    # for Python 3.6
+    import importlib_resources
 import os
 import re
 import sys
diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py
index 42ac4ed..e391849 100644
--- a/tools/patman/func_test.py
+++ b/tools/patman/func_test.py
@@ -489,8 +489,8 @@
         # pylint: disable=E1101
         self.repo.checkout(target, strategy=pygit2.GIT_CHECKOUT_FORCE)
         control.setup()
+        orig_dir = os.getcwd()
         try:
-            orig_dir = os.getcwd()
             os.chdir(self.gitdir)
 
             # Check that it can detect the current branch
@@ -679,8 +679,8 @@
         self.repo.checkout(target, strategy=pygit2.GIT_CHECKOUT_FORCE)
 
         # Check that it can detect the current branch
+        orig_dir = os.getcwd()
         try:
-            orig_dir = os.getcwd()
             os.chdir(self.gitdir)
             with self.assertRaises(ValueError) as exc:
                 gitutil.count_commits_to_branch(None)