Merge git://git.denx.de/u-boot-uniphier
diff --git a/arch/arm/dts/uniphier-v7-u-boot.dtsi b/arch/arm/dts/uniphier-v7-u-boot.dtsi
index 0094a45..9459bf0 100644
--- a/arch/arm/dts/uniphier-v7-u-boot.dtsi
+++ b/arch/arm/dts/uniphier-v7-u-boot.dtsi
@@ -14,22 +14,6 @@
u-boot,dm-pre-reloc;
};
- mioctrl@59810000 {
- u-boot,dm-pre-reloc;
-
- clock {
- u-boot,dm-pre-reloc;
- };
- };
-
- sdctrl@59810000 {
- u-boot,dm-pre-reloc;
-
- clock {
- u-boot,dm-pre-reloc;
- };
- };
-
soc-glue@5f800000 {
u-boot,dm-pre-reloc;
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
index 3666d84..a26ca8c 100644
--- a/drivers/clk/uniphier/Kconfig
+++ b/drivers/clk/uniphier/Kconfig
@@ -2,7 +2,6 @@
def_bool y
depends on ARCH_UNIPHIER
select CLK
- select SPL_CLK if SPL
help
Support for clock controllers on UniPhier SoCs.
Say Y if you want to control clocks provided by System Control
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 56a43ca..8e49b2f 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -330,8 +330,10 @@
static int renesas_sdhi_probe(struct udevice *dev)
{
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
u32 quirks = dev_get_driver_data(dev);
struct fdt_resource reg_res;
+ struct clk clk;
DECLARE_GLOBAL_DATA_PTR;
int ret;
@@ -348,6 +350,27 @@
quirks |= TMIO_SD_CAP_16BIT;
}
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get host clock\n");
+ return ret;
+ }
+
+ /* set to max rate */
+ priv->mclk = clk_set_rate(&clk, ULONG_MAX);
+ if (IS_ERR_VALUE(priv->mclk)) {
+ dev_err(dev, "failed to set rate for host clock\n");
+ clk_free(&clk);
+ return priv->mclk;
+ }
+
+ ret = clk_enable(&clk);
+ clk_free(&clk);
+ if (ret) {
+ dev_err(dev, "failed to enable host clock\n");
+ return ret;
+ }
+
ret = tmio_sd_probe(dev, quirks);
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
if (!ret)
diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
index 5f1c9c0..4ea6612 100644
--- a/drivers/mmc/tmio-common.c
+++ b/drivers/mmc/tmio-common.c
@@ -713,7 +713,6 @@
struct tmio_sd_priv *priv = dev_get_priv(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
fdt_addr_t base;
- struct clk clk;
int ret;
base = devfdt_get_addr(dev);
@@ -728,27 +727,6 @@
device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
#endif
- ret = clk_get_by_index(dev, 0, &clk);
- if (ret < 0) {
- dev_err(dev, "failed to get host clock\n");
- return ret;
- }
-
- /* set to max rate */
- priv->mclk = clk_set_rate(&clk, ULONG_MAX);
- if (IS_ERR_VALUE(priv->mclk)) {
- dev_err(dev, "failed to set rate for host clock\n");
- clk_free(&clk);
- return priv->mclk;
- }
-
- ret = clk_enable(&clk);
- clk_free(&clk);
- if (ret) {
- dev_err(dev, "failed to enable host clock\n");
- return ret;
- }
-
ret = mmc_of_parse(dev, &plat->cfg);
if (ret < 0) {
dev_err(dev, "failed to parse host caps\n");
diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
index 47379b0..61f8da4 100644
--- a/drivers/mmc/uniphier-sd.c
+++ b/drivers/mmc/uniphier-sd.c
@@ -32,6 +32,35 @@
static int uniphier_sd_probe(struct udevice *dev)
{
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+#ifndef CONFIG_SPL_BUILD
+ struct clk clk;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get host clock\n");
+ return ret;
+ }
+
+ /* set to max rate */
+ priv->mclk = clk_set_rate(&clk, ULONG_MAX);
+ if (IS_ERR_VALUE(priv->mclk)) {
+ dev_err(dev, "failed to set rate for host clock\n");
+ clk_free(&clk);
+ return priv->mclk;
+ }
+
+ ret = clk_enable(&clk);
+ clk_free(&clk);
+ if (ret) {
+ dev_err(dev, "failed to enable host clock\n");
+ return ret;
+ }
+#else
+ priv->mclk = 100000000;
+#endif
+
return tmio_sd_probe(dev, 0);
}
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 1b4140d..c39f13b 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -33,7 +33,7 @@
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_MONITOR_BASE 0
-#define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */
+#define CONFIG_SYS_MONITOR_LEN 0x00090000 /* 576KB */
#define CONFIG_SYS_FLASH_BASE 0
/*
@@ -186,6 +186,7 @@
"setexpr tmp_addr $nor_base + 0x70000 && " \
"tftpboot $tmp_addr $third_image\0" \
"emmcupdate=mmcsetn &&" \
+ "mmc dev $mmc_first_dev &&" \
"mmc partconf $mmc_first_dev 0 1 1 &&" \
"tftpboot $second_image && " \
"mmc write $loadaddr 0 100 && " \
@@ -219,7 +220,7 @@
#define CONFIG_SPL_TEXT_BASE 0x00100000
#endif
-#define CONFIG_SPL_STACK (0x00100000)
+#define CONFIG_SPL_STACK (0x00200000)
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000