ppc4xx: Change Kilauea to use the common DDR2 init function
This patch changes the kilauea and kilauea_nand (for NAND booting)
board port to not use a board specific DDR2 init routine anymore. Now
the common code from cpu/ppc4xx is used.
Thanks to Grant Erickson for all his basic work on this 405EX early
bootup.
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/nand_spl/board/amcc/kilauea/config.mk b/nand_spl/board/amcc/kilauea/config.mk
index 2249091..d89ed3f 100644
--- a/nand_spl/board/amcc/kilauea/config.mk
+++ b/nand_spl/board/amcc/kilauea/config.mk
@@ -29,8 +29,9 @@
#
# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
# in the last 4kBytes of memory space in cache.
-# We will copy this SPL into instruction-cache in start.S. So we set
-# TEXT_BASE to starting address in i-cache here.
+# We will copy this SPL into SDRAM since we can't access the NAND
+# controller at CS0 while running from this location. So we set
+# TEXT_BASE to starting address in SDRAM here.
#
TEXT_BASE = 0x00800000