| commit | a1dfa9a58969e2cdbfeea147ca258e22e3bbc416 | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <treding@nvidia.com> | Tue Sep 08 11:38:03 2015 +0200 |
| committer | Tom Warren <twarren@nvidia.com> | Wed Sep 16 16:11:31 2015 -0700 |
| tree | e9b32cefb1b3a59f06b14fd3b522997dc3bf8ee9 | |
| parent | 0633965d66f319bb056e7e8bc4974d93b1e25cb0 [diff] |
ARM: tegra124: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence").
Reported-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>