diff --git a/include/asm-ppc/4xx_pci.h b/include/asm-ppc/4xx_pci.h
index 3c1adec..30125a1 100644
--- a/include/asm-ppc/4xx_pci.h
+++ b/include/asm-ppc/4xx_pci.h
@@ -47,6 +47,6 @@
 #define PTM2MS          0xEF400038
 #define PTM2LA          0xEF40003C
 
-#define PCIDEVID_405GP 	0x0
+#define PCIDEVID_405GP	0x0
 
 #endif
diff --git a/include/asm-ppc/5xx_immap.h b/include/asm-ppc/5xx_immap.h
index 8e57057..72cbab4 100644
--- a/include/asm-ppc/5xx_immap.h
+++ b/include/asm-ppc/5xx_immap.h
@@ -408,31 +408,31 @@
 /* Internal Memory Map MPC555
 */
 typedef struct immap {
-	char               res1[262144];       	/* CMF Flash A 256 Kbytes */
-	char               res2[196608];       	/* CMF Flash B 192 Kbytes */
-	char               res3[2670592];      	/* Reserved for Flash */
-	sysconf5xx_t       im_siu_conf;        	/* SIU Configuration */
+	char               res1[262144];	/* CMF Flash A 256 Kbytes */
+	char               res2[196608];	/* CMF Flash B 192 Kbytes */
+	char               res3[2670592];	/* Reserved for Flash */
+	sysconf5xx_t       im_siu_conf;		/* SIU Configuration */
 	memctl5xx_t	   im_memctl;		/* Memory Controller */
 	sit5xx_t           im_sit;		/* System Integration Timers */
 	car5xx_t	   im_clkrst;		/* Clocks and Reset */
-	sitk5xx_t          im_sitk;            	/* System Integration Timer Keys*/
-	cark8xx_t          im_clkrstk;         	/* Clocks and Resert Keys */
+	sitk5xx_t          im_sitk;		/* System Integration Timer Keys*/
+	cark8xx_t          im_clkrstk;		/* Clocks and Resert Keys */
 	fl5xx_t	           im_fla;	        /* Flash Module A */
 	fl5xx_t	           im_flb;	        /* Flash Module B */
-	char               res4[14208];        	/* Reserved for SIU */
-	dprc5xx_t	   im_dprc;            	/* Dpram Control Register */
-	char               res5[8180];         	/* Reserved */
-	char               dptram[6144];       	/* Dptram */
-	char               res6[2048];         	/* Reserved */
+	char               res4[14208];		/* Reserved for SIU */
+	dprc5xx_t	   im_dprc;		/* Dpram Control Register */
+	char               res5[8180];		/* Reserved */
+	char               dptram[6144];	/* Dptram */
+	char               res6[2048];		/* Reserved */
 	tpu5xx_t	   im_tpua;		/* Time Proessing Unit A */
-	tpu5xx_t	   im_tpub;  	      	/* Time Processing Unit B */
-	qadc5xx_t	   im_qadca;           	/* QADC A */
-	qadc5xx_t	   im_qadcb;           	/* QADC B */
+	tpu5xx_t	   im_tpub;		/* Time Processing Unit B */
+	qadc5xx_t	   im_qadca;		/* QADC A */
+	qadc5xx_t	   im_qadcb;		/* QADC B */
 	qsmcm5xx_t	   im_qsmcm;		/* SCI and SPI */
-	mios5xx_t      	   im_mios;		/* MIOS */
-	tcan5xx_t          im_tcana;           	/* Toucan A */
-	tcan5xx_t          im_tcanb;	       	/* Toucan B */
-	char               res7[1792];         	/* Reserved */
+	mios5xx_t	   im_mios;		/* MIOS */
+	tcan5xx_t          im_tcana;		/* Toucan A */
+	tcan5xx_t          im_tcanb;		/* Toucan B */
+	char               res7[1792];		/* Reserved */
 	uimb5xx_t          im_uimb;	        /* UIMB */
 } immap_t;
 
diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h
index de82399..05db0de 100644
--- a/include/asm-ppc/e300.h
+++ b/include/asm-ppc/e300.h
@@ -16,59 +16,59 @@
  */
 
 /* #define HID0 1008 already defined in processor.h */
-#define HID0_MASK_MACHINE_CHECK              0x00000000
-#define HID0_ENABLE_MACHINE_CHECK            0x80000000
+#define HID0_MASK_MACHINE_CHECK		     0x00000000
+#define HID0_ENABLE_MACHINE_CHECK	     0x80000000
 
-#define HID0_DISABLE_CACHE_PARITY            0x00000000
-#define HID0_ENABLE_CACHE_PARITY             0x40000000
+#define HID0_DISABLE_CACHE_PARITY	     0x00000000
+#define HID0_ENABLE_CACHE_PARITY	     0x40000000
 
-#define HID0_DISABLE_ADDRESS_PARITY          0x00000000 /* on mpc8349ads must be disabled */
-#define HID0_ENABLE_ADDRESS_PARITY           0x20000000
+#define HID0_DISABLE_ADDRESS_PARITY	     0x00000000 /* on mpc8349ads must be disabled */
+#define HID0_ENABLE_ADDRESS_PARITY	     0x20000000
 
-#define HID0_DISABLE_DATA_PARITY             0x00000000 /* on mpc8349ads must be disabled */
-#define HID0_ENABLE_DATE_PARITY              0x10000000
+#define HID0_DISABLE_DATA_PARITY	     0x00000000 /* on mpc8349ads must be disabled */
+#define HID0_ENABLE_DATE_PARITY		     0x10000000
 
-#define HID0_CORE_CLK_OUT                    0x00000000
-#define HID0_CORE_CLK_OUT_DIV_2              0x08000000
+#define HID0_CORE_CLK_OUT		     0x00000000
+#define HID0_CORE_CLK_OUT_DIV_2		     0x08000000
 
 #define HID0_ENABLE_ARTRY_OUT_PRECHARGE      0x00000000 /* on mpc8349ads must be enabled */
 #define HID0_DISABLE_ARTRY_OUT_PRECHARGE     0x01000000
 
-#define HID0_DISABLE_DOSE_MODE               0x00000000
-#define HID0_ENABLE_DOSE_MODE                0x00800000
+#define HID0_DISABLE_DOSE_MODE		     0x00000000
+#define HID0_ENABLE_DOSE_MODE		     0x00800000
 
-#define HID0_DISABLE_NAP_MODE                0x00000000
-#define HID0_ENABLE_NAP_MODE                 0x00400000
+#define HID0_DISABLE_NAP_MODE		     0x00000000
+#define HID0_ENABLE_NAP_MODE		     0x00400000
 
-#define HID0_DISABLE_SLEEP_MODE              0x00000000
-#define HID0_ENABLE_SLEEP_MODE               0x00200000
+#define HID0_DISABLE_SLEEP_MODE		     0x00000000
+#define HID0_ENABLE_SLEEP_MODE		     0x00200000
 
 #define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000
 #define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT  0x00100000
 
-#define HID0_SOFT_RESET                      0x00010000
+#define HID0_SOFT_RESET			     0x00010000
 
-#define HID0_DISABLE_INSTRUCTION_CACHE       0x00000000
-#define HID0_ENABLE_INSTRUCTION_CACHE        0x00008000
+#define HID0_DISABLE_INSTRUCTION_CACHE	     0x00000000
+#define HID0_ENABLE_INSTRUCTION_CACHE	     0x00008000
 
-#define HID0_DISABLE_DATA_CACHE              0x00000000
-#define HID0_ENABLE_DATA_CACHE               0x00004000
+#define HID0_DISABLE_DATA_CACHE		     0x00000000
+#define HID0_ENABLE_DATA_CACHE		     0x00004000
 
-#define HID0_LOCK_INSTRUCTION_CACHE          0x00002000
+#define HID0_LOCK_INSTRUCTION_CACHE	     0x00002000
 
-#define HID0_LOCK_DATA_CACHE                 0x00001000
+#define HID0_LOCK_DATA_CACHE		     0x00001000
 
 #define HID0_INVALIDATE_INSTRUCTION_CACHE    0x00000800
 
-#define HID0_INVALIDATE_DATA_CACHE           0x00000400
+#define HID0_INVALIDATE_DATA_CACHE	     0x00000400
 
-#define HID0_DISABLE_M_BIT                   0x00000000
-#define HID0_ENABLE_M_BIT                    0x00000080
+#define HID0_DISABLE_M_BIT		     0x00000000
+#define HID0_ENABLE_M_BIT		     0x00000080
 
-#define HID0_FBIOB                           0x00000010
+#define HID0_FBIOB			     0x00000010
 
-#define HID0_DISABLE_ADDRESS_BROADCAST       0x00000000
-#define HID0_ENABLE_ADDRESS_BROADCAST        0x00000008
+#define HID0_DISABLE_ADDRESS_BROADCAST	     0x00000000
+#define HID0_ENABLE_ADDRESS_BROADCAST	     0x00000008
 
 #define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION  0x00000000
 #define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001
@@ -90,37 +90,37 @@
 
 
 /* BAT (block address translation */
-#define BATU_BEPI_MSK	    0xfffe0000
-#define BATU_BL_MSK         0x00001ffc
+#define BATU_BEPI_MSK		0xfffe0000
+#define BATU_BL_MSK		0x00001ffc
 
-#define BATU_BL_128K        0x00000000
-#define BATU_BL_256K        0x00000004
-#define BATU_BL_512K        0x0000000c
-#define BATU_BL_1M          0x0000001c
-#define BATU_BL_2M          0x0000003c
-#define BATU_BL_4M          0x0000007c
-#define BATU_BL_8M          0x000000fc
-#define BATU_BL_16M         0x000001fc
-#define BATU_BL_32M         0x000003fc
-#define BATU_BL_64M         0x000007fc
-#define BATU_BL_128M        0x00000ffc
-#define BATU_BL_256M        0x00001ffc
+#define BATU_BL_128K		0x00000000
+#define BATU_BL_256K		0x00000004
+#define BATU_BL_512K		0x0000000c
+#define BATU_BL_1M		0x0000001c
+#define BATU_BL_2M		0x0000003c
+#define BATU_BL_4M		0x0000007c
+#define BATU_BL_8M		0x000000fc
+#define BATU_BL_16M		0x000001fc
+#define BATU_BL_32M		0x000003fc
+#define BATU_BL_64M		0x000007fc
+#define BATU_BL_128M		0x00000ffc
+#define BATU_BL_256M		0x00001ffc
 
-#define BATU_VS             0x00000002
-#define BATU_VP             0x00000001
+#define BATU_VS			0x00000002
+#define BATU_VP			0x00000001
 
-#define BATL_BRPN_MSK       0xfffe0000
-#define BATL_WIMG_MSK       0x00000078
+#define BATL_BRPN_MSK		0xfffe0000
+#define BATL_WIMG_MSK		0x00000078
 
-#define BATL_WRITETHROUGH   0x00000040
-#define BATL_CACHEINHIBIT   0x00000020
-#define BATL_MEMCOHERENCE   0x00000010
-#define BATL_GUARDEDSTORAGE 0x00000008
+#define BATL_WRITETHROUGH	0x00000040
+#define BATL_CACHEINHIBIT	0x00000020
+#define BATL_MEMCOHERENCE	0x00000010
+#define BATL_GUARDEDSTORAGE	0x00000008
 
-#define BATL_PP_MSK         0x00000003
-#define BATL_PP_00          0x00000000 /* No access */
-#define BATL_PP_01          0x00000001 /* Read-only */
-#define BATL_PP_10          0x00000002 /* Read-write */
-#define BATL_PP_11        	0x00000003
+#define BATL_PP_MSK		0x00000003
+#define BATL_PP_00		0x00000000 /* No access */
+#define BATL_PP_01		0x00000001 /* Read-only */
+#define BATL_PP_10		0x00000002 /* Read-write */
+#define BATL_PP_11		0x00000003
 
 #endif	/* __E300_H__ */
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 2d07625..113ba48 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1054,7 +1054,7 @@
  * 0x9000-0x90bff: General SIU
  */
 typedef struct ccsr_cpm_siu {
-	char 	res1[80];
+	char	res1[80];
 	uint	smaer;
 	uint	smser;
 	uint	smevr;
@@ -1143,9 +1143,9 @@
 /* 0x91018-0x912ff: SDMA */
 typedef struct ccsr_cpm_sdma {
 	uchar	sdsr;
-	char 	res1[3];
-	uchar 	sdmr;
-	char 	res2[739];
+	char	res1[3];
+	uchar	sdmr;
+	char	res2[739];
 } ccsr_cpm_sdma_t;
 
 /* 0x91300-0x9131f: FCC1 */
@@ -1228,7 +1228,7 @@
 
 /* 0x91400-0x915ef: TC layers */
 typedef struct ccsr_cpm_tmp1 {
-	char 	res[496];
+	char	res[496];
 } ccsr_cpm_tmp1_t;
 
 /* 0x915f0-0x9185f: BRGs:5,6,7,8 */
@@ -1296,7 +1296,7 @@
 
 /* 0x91a80-0x91a9f */
 typedef struct ccsr_cpm_tmp2 {
-	char 	res[32];
+	char	res[32];
 } ccsr_cpm_tmp2_t;
 
 /* 0x91aa0-0x91aff: SPI */
@@ -1338,16 +1338,16 @@
 	/* Some references are into the unique and known dpram spaces,
 	 * others are from the generic base.
 	 */
-#define im_dprambase    	im_dpram1
-	u_char          	im_dpram1[16*1024];
-	char            	res1[16*1024];
-	u_char          	im_dpram2[16*1024];
-	char            	res2[16*1024];
-	ccsr_cpm_siu_t  	im_cpm_siu;     /* SIU Configuration */
-	ccsr_cpm_intctl_t    	im_cpm_intctl;  /* Interrupt Controller */
-	ccsr_cpm_iop_t       	im_cpm_iop;     /* IO Port control/status */
-	ccsr_cpm_timer_t  	im_cpm_timer;   /* CPM timers */
-	ccsr_cpm_sdma_t      	im_cpm_sdma;    /* SDMA control/status */
+#define im_dprambase		im_dpram1
+	u_char			im_dpram1[16*1024];
+	char			res1[16*1024];
+	u_char			im_dpram2[16*1024];
+	char			res2[16*1024];
+	ccsr_cpm_siu_t		im_cpm_siu;     /* SIU Configuration */
+	ccsr_cpm_intctl_t	im_cpm_intctl;  /* Interrupt Controller */
+	ccsr_cpm_iop_t		im_cpm_iop;     /* IO Port control/status */
+	ccsr_cpm_timer_t	im_cpm_timer;   /* CPM timers */
+	ccsr_cpm_sdma_t		im_cpm_sdma;    /* SDMA control/status */
 	ccsr_cpm_fcc1_t		im_cpm_fcc1;
 	ccsr_cpm_fcc2_t		im_cpm_fcc2;
 	ccsr_cpm_fcc3_t		im_cpm_fcc3;
@@ -1553,7 +1553,7 @@
 typedef struct ccsr_gur {
 	uint	porpllsr;	/* 0xe0000 - POR PLL ratio status register */
 	uint	porbmsr;	/* 0xe0004 - POR boot mode status register */
-#define MPC85xx_PORBMSR_HA 		0x00070000
+#define MPC85xx_PORBMSR_HA		0x00070000
 	uint	porimpscr;	/* 0xe0008 - POR I/O impedance status and control register */
 	uint	pordevsr;	/* 0xe000c - POR I/O device status regsiter */
 #define MPC85xx_PORDEVSR_SGMII1_DIS	0x20000000
@@ -1561,13 +1561,13 @@
 #define MPC85xx_PORDEVSR_SGMII3_DIS	0x08000000
 #define MPC85xx_PORDEVSR_SGMII4_DIS	0x04000000
 #define MPC85xx_PORDEVSR_IO_SEL		0x00380000
-#define MPC85xx_PORDEVSR_PCI2_ARB 	0x00040000
-#define MPC85xx_PORDEVSR_PCI1_ARB 	0x00020000
-#define MPC85xx_PORDEVSR_PCI1_PCI32 	0x00010000
-#define MPC85xx_PORDEVSR_PCI1_SPD 	0x00008000
-#define MPC85xx_PORDEVSR_PCI2_SPD 	0x00004000
+#define MPC85xx_PORDEVSR_PCI2_ARB	0x00040000
+#define MPC85xx_PORDEVSR_PCI1_ARB	0x00020000
+#define MPC85xx_PORDEVSR_PCI1_PCI32	0x00010000
+#define MPC85xx_PORDEVSR_PCI1_SPD	0x00008000
+#define MPC85xx_PORDEVSR_PCI2_SPD	0x00004000
 #define MPC85xx_PORDEVSR_DRAM_RTYPE	0x00000060
-#define MPC85xx_PORDEVSR_RIO_CTLS 	0x00000008
+#define MPC85xx_PORDEVSR_RIO_CTLS	0x00000008
 #define MPC85xx_PORDEVSR_RIO_DEV_ID	0x00000007
 	uint	pordbgmsr;	/* 0xe0010 - POR debug mode status register */
 	uint	pordevsr2;	/* 0xe0014 - POR I/O device status regsiter 2 */
@@ -1593,13 +1593,13 @@
 #define MPC85xx_DEVDISR_SEC		0x01000000
 #define MPC85xx_DEVDISR_SRIO		0x00080000
 #define MPC85xx_DEVDISR_RMSG		0x00040000
-#define MPC85xx_DEVDISR_DDR 		0x00010000
-#define MPC85xx_DEVDISR_CPU 		0x00008000
-#define MPC85xx_DEVDISR_CPU0 		MPC85xx_DEVDISR_CPU
-#define MPC85xx_DEVDISR_TB 		0x00004000
-#define MPC85xx_DEVDISR_TB0 		MPC85xx_DEVDISR_TB
-#define MPC85xx_DEVDISR_CPU1 		0x00002000
-#define MPC85xx_DEVDISR_TB1 		0x00001000
+#define MPC85xx_DEVDISR_DDR		0x00010000
+#define MPC85xx_DEVDISR_CPU		0x00008000
+#define MPC85xx_DEVDISR_CPU0		MPC85xx_DEVDISR_CPU
+#define MPC85xx_DEVDISR_TB		0x00004000
+#define MPC85xx_DEVDISR_TB0		MPC85xx_DEVDISR_TB
+#define MPC85xx_DEVDISR_CPU1		0x00002000
+#define MPC85xx_DEVDISR_TB1		0x00001000
 #define MPC85xx_DEVDISR_DMA		0x00000400
 #define MPC85xx_DEVDISR_TSEC1		0x00000080
 #define MPC85xx_DEVDISR_TSEC2		0x00000040
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index 0b78c94..c03b4b8 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -119,7 +119,7 @@
 	uint    sdram_mode_2;		/* 0x211c - DDR SDRAM Mode Configuration 2 */
 	uint    sdram_mode_cntl;        /* 0x2120 - DDR SDRAM Mode Control */
 	uint	sdram_interval;		/* 0x2124 - DDR SDRAM Interval Configuration */
-	uint    sdram_data_init; 	/* 0x2128 - DDR SDRAM Data Initialization */
+	uint    sdram_data_init;	/* 0x2128 - DDR SDRAM Data Initialization */
 	char	res8[4];
 	uint	sdram_clk_cntl;		/* 0x2130 - DDR SDRAM Clock Control */
 	char    res9[12];
@@ -464,7 +464,7 @@
 
 /* tsec1-4: 24000-28000 */
 typedef struct ccsr_tsec {
-	uint    id; 		/* 0x24000 - Controller ID Register */
+	uint    id;		/* 0x24000 - Controller ID Register */
 	char	res1[12];
 	uint	ievent;		/* 0x24010 - Interrupt Event Register */
 	uint	imask;		/* 0x24014 - Interrupt Mask Register */
@@ -538,7 +538,7 @@
 	uint    rbifx;		/* 0x24330 - Receive bit field extract control Register */
 	uint    rqfar;		/* 0x24334 - Receive queue filing table address Register */
 	uint    rqfcr;		/* 0x24338 - Receive queue filing table control Register */
-	uint    rqfpr;      	/* 0x2433c - Receive queue filing table property Register */
+	uint    rqfpr;		/* 0x2433c - Receive queue filing table property Register */
 	uint	mrblr;		/* 0x24340 - Maximum Receive Buffer Length Register */
 	char	res28[56];
 	uint    rbdbph;		/* 0x2437C - Receive Data Buffer Pointer High */
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 49d6860..4f78ca7 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -343,7 +343,7 @@
 #define MAS0_ESEL(x)	((x << 16) & 0x0FFF0000)
 #define MAS0_NV(x)	((x) & 0x00000FFF)
 
-#define MAS1_VALID 	0x80000000
+#define MAS1_VALID	0x80000000
 #define MAS1_IPROT	0x40000000
 #define MAS1_TID(x)	((x << 16) & 0x3FFF0000)
 #define MAS1_TS		0x00001000
@@ -685,7 +685,7 @@
 #define MSYNC				.long 0x7c000000|\
 					(598<<1)
 
-#define MBAR_INST 				.long 0x7c000000|\
+#define MBAR_INST				.long 0x7c000000|\
 					(854<<1)
 
 #ifndef __ASSEMBLY__
diff --git a/include/asm-ppc/ppc4xx-intvec.h b/include/asm-ppc/ppc4xx-intvec.h
index e218119..5b45de4 100644
--- a/include/asm-ppc/ppc4xx-intvec.h
+++ b/include/asm-ppc/ppc4xx-intvec.h
@@ -323,9 +323,9 @@
 #define VECNUM_EWU0		17	/* Ethernet wakeup sequence detected */
 
 #define VECNUM_MADMAL		18	/* Logical OR of following MadMAL int */
-#define VECNUM_MS		18	/*	MAL_SERR_INT 		*/
-#define VECNUM_TXDE		18	/* 	MAL_TXDE_INT 		*/
-#define VECNUM_RXDE		18	/*	MAL_RXDE_INT 		*/
+#define VECNUM_MS		18	/*	MAL_SERR_INT		*/
+#define VECNUM_TXDE		18	/*	MAL_TXDE_INT		*/
+#define VECNUM_RXDE		18	/*	MAL_RXDE_INT		*/
 
 #define VECNUM_MTE		19	/* MAL TXEOB			*/
 #define VECNUM_MTE1		20	/* MAL TXEOB1			*/
diff --git a/include/asm-ppc/ptrace.h b/include/asm-ppc/ptrace.h
index 3c2f4e6..196613b 100644
--- a/include/asm-ppc/ptrace.h
+++ b/include/asm-ppc/ptrace.h
@@ -39,7 +39,7 @@
 	PPC_REG trap;		/* Reason for being here */
 	PPC_REG dar;		/* Fault registers */
 	PPC_REG dsisr;
-	PPC_REG result; 	/* Result of a system call */
+	PPC_REG result;		/* Result of a system call */
 };
 #endif
 
diff --git a/include/asm-ppc/sigcontext.h b/include/asm-ppc/sigcontext.h
index 4bd66a7..715c868 100644
--- a/include/asm-ppc/sigcontext.h
+++ b/include/asm-ppc/sigcontext.h
@@ -9,7 +9,7 @@
 	int		signal;
 	unsigned long	handler;
 	unsigned long	oldmask;
-	struct pt_regs 	*regs;
+	struct pt_regs	*regs;
 };
 
 #endif
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index 786ba03..83af2f5 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -126,14 +126,14 @@
 #if defined(CONFIG_4xx)
 #if defined(CONFIG_440GX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
-	int 		bi_phynum[4];           /* Determines phy mapping */
-	int 		bi_phymode[4];          /* Determines phy mode */
+	int		bi_phynum[4];           /* Determines phy mapping */
+	int		bi_phymode[4];          /* Determines phy mode */
 #elif defined(CONFIG_405EP) || defined(CONFIG_440)
-	int 		bi_phynum[2];           /* Determines phy mapping */
-	int 		bi_phymode[2];          /* Determines phy mode */
+	int		bi_phynum[2];           /* Determines phy mapping */
+	int		bi_phymode[2];          /* Determines phy mode */
 #else
-	int 		bi_phynum[1];           /* Determines phy mapping */
-	int 		bi_phymode[1];          /* Determines phy mode */
+	int		bi_phynum[1];           /* Determines phy mapping */
+	int		bi_phymode[1];          /* Determines phy mode */
 #endif
 #endif /* defined(CONFIG_4xx) */
 } bd_t;