| commit | a1763ba8b11dcfdae09bf3ed627410aa29df532d | [log] [tgz] |
|---|---|---|
| author | Nava kishore Manne <nava.manne@xilinx.com> | Mon May 22 12:05:17 2017 +0530 |
| committer | Michal Simek <michal.simek@xilinx.com> | Tue Nov 28 16:09:08 2017 +0100 |
| tree | 154a70d63f6cdda98c1afea5b53ed18886ec6193 | |
| parent | 2155a6014ca5299585feb9a48c6eeb666b7512b1 [diff] |
arm64: zynqmp: Label whole PL part as fpga_full region This will simplify dt overlay structure for the whole PL. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>