diff --git a/drivers/clk/qcom/clock-sm8250.c b/drivers/clk/qcom/clock-sm8250.c
index af10fc1..e322a92 100644
--- a/drivers/clk/qcom/clock-sm8250.c
+++ b/drivers/clk/qcom/clock-sm8250.c
@@ -253,6 +253,115 @@
 	[USB30_SEC_GDSC] = { 0x10004 },
 };
 
+static const phys_addr_t sm8250_gpll_addrs[] = {
+	0x00100000, // GCC_GPLL0_MODE
+	0x00101000, // GCC_GPLL1_MODE
+	0x00102000, // GCC_GPLL2_MODE
+	0x00103000, // GCC_GPLL3_MODE
+	0x00176000, // GCC_GPLL4_MODE
+	0x00174000, // GCC_GPLL5_MODE
+	0x00113000, // GCC_GPLL6_MODE
+	0x0011a000, // GCC_GPLL7_MODE
+	0x0011b000, // GCC_GPLL8_MODE
+	0x0011c000, // GCC_GPLL9_MODE
+	0x0011d000, // GCC_GPLL10_MODE
+	0x0014a000, // GCC_GPLL11_MODE
+};
+
+static const phys_addr_t sm8250_rcg_addrs[] = {
+	0x0010f020, // GCC_USB30_PRIM_MASTER_CMD_RCGR
+	0x0010f038, // GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR
+	0x0010f064, // GCC_USB3_PRIM_PHY_AUX_CMD_RCGR
+	0x00110020, // GCC_USB30_SEC_MASTER_CMD_RCGR
+	0x00110038, // GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR
+	0x00110064, // GCC_USB3_SEC_PHY_AUX_CMD_RCGR
+	0x0011400c, // GCC_SDCC2_APPS_CMD_RCGR
+	0x0011600c, // GCC_SDCC4_APPS_CMD_RCGR
+	0x0012300c, // GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR
+	0x00117010, // GCC_QUPV3_WRAP0_S0_CMD_RCGR
+	0x00117140, // GCC_QUPV3_WRAP0_S1_CMD_RCGR
+	0x00117270, // GCC_QUPV3_WRAP0_S2_CMD_RCGR
+	0x001173a0, // GCC_QUPV3_WRAP0_S3_CMD_RCGR
+	0x001174d0, // GCC_QUPV3_WRAP0_S4_CMD_RCGR
+	0x00117600, // GCC_QUPV3_WRAP0_S5_CMD_RCGR
+	0x00117730, // GCC_QUPV3_WRAP0_S6_CMD_RCGR
+	0x00117860, // GCC_QUPV3_WRAP0_S7_CMD_RCGR
+	0x00123144, // GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR
+	0x00118010, // GCC_QUPV3_WRAP1_S0_CMD_RCGR
+	0x00118140, // GCC_QUPV3_WRAP1_S1_CMD_RCGR
+	0x00118270, // GCC_QUPV3_WRAP1_S2_CMD_RCGR
+	0x001183a0, // GCC_QUPV3_WRAP1_S3_CMD_RCGR
+	0x001184d0, // GCC_QUPV3_WRAP1_S4_CMD_RCGR
+	0x00118600, // GCC_QUPV3_WRAP1_S5_CMD_RCGR
+	0x0016b038, // GCC_PCIE_0_AUX_CMD_RCGR
+	0x0018d038, // GCC_PCIE_1_AUX_CMD_RCGR
+	0x0016f014, // GCC_PCIE_PHY_REFGEN_CMD_RCGR
+	0x00175024, // GCC_UFS_CARD_AXI_CMD_RCGR
+	0x0017506c, // GCC_UFS_CARD_ICE_CORE_CMD_RCGR
+	0x00175084, // GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR
+	0x001750a0, // GCC_UFS_CARD_PHY_AUX_CMD_RCGR
+	0x00177024, // GCC_UFS_PHY_AXI_CMD_RCGR
+	0x0017706c, // GCC_UFS_PHY_ICE_CORE_CMD_RCGR
+	0x00177084, // GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR
+	0x001770a0, // GCC_UFS_PHY_PHY_AUX_CMD_RCGR
+	0x0012327c, // GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR
+	0x0011e010, // GCC_QUPV3_WRAP2_S0_CMD_RCGR
+	0x0011e140, // GCC_QUPV3_WRAP2_S1_CMD_RCGR
+	0x0011e270, // GCC_QUPV3_WRAP2_S2_CMD_RCGR
+	0x0011e3a0, // GCC_QUPV3_WRAP2_S3_CMD_RCGR
+	0x0011e4d0, // GCC_QUPV3_WRAP2_S4_CMD_RCGR
+	0x0011e600, // GCC_QUPV3_WRAP2_S5_CMD_RCGR
+	0x0010d00c, // GCC_RBCPR_MMCX_CMD_RCGR
+	0x00106038, // GCC_PCIE_2_AUX_CMD_RCGR
+};
+
+static const char *const sm8250_rcg_names[] = {
+	"GCC_USB30_PRIM_MASTER_CMD_RCGR",
+	"GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR",
+	"GCC_USB3_PRIM_PHY_AUX_CMD_RCGR",
+	"GCC_USB30_SEC_MASTER_CMD_RCGR",
+	"GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR",
+	"GCC_USB3_SEC_PHY_AUX_CMD_RCGR",
+	"GCC_SDCC2_APPS_CMD_RCGR",
+	"GCC_SDCC4_APPS_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S0_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S1_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S2_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S3_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S4_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S5_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S6_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S7_CMD_RCGR",
+	"GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR",
+	"GCC_QUPV3_WRAP1_S0_CMD_RCGR",
+	"GCC_QUPV3_WRAP1_S1_CMD_RCGR",
+	"GCC_QUPV3_WRAP1_S2_CMD_RCGR",
+	"GCC_QUPV3_WRAP1_S3_CMD_RCGR",
+	"GCC_QUPV3_WRAP1_S4_CMD_RCGR",
+	"GCC_QUPV3_WRAP1_S5_CMD_RCGR",
+	"GCC_PCIE_0_AUX_CMD_RCGR",
+	"GCC_PCIE_1_AUX_CMD_RCGR",
+	"GCC_PCIE_PHY_REFGEN_CMD_RCGR",
+	"GCC_UFS_CARD_AXI_CMD_RCGR",
+	"GCC_UFS_CARD_ICE_CORE_CMD_RCGR",
+	"GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR",
+	"GCC_UFS_CARD_PHY_AUX_CMD_RCGR",
+	"GCC_UFS_PHY_AXI_CMD_RCGR",
+	"GCC_UFS_PHY_ICE_CORE_CMD_RCGR",
+	"GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR",
+	"GCC_UFS_PHY_PHY_AUX_CMD_RCGR",
+	"GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR",
+	"GCC_QUPV3_WRAP2_S0_CMD_RCGR",
+	"GCC_QUPV3_WRAP2_S1_CMD_RCGR",
+	"GCC_QUPV3_WRAP2_S2_CMD_RCGR",
+	"GCC_QUPV3_WRAP2_S3_CMD_RCGR",
+	"GCC_QUPV3_WRAP2_S4_CMD_RCGR",
+	"GCC_QUPV3_WRAP2_S5_CMD_RCGR",
+	"GCC_RBCPR_MMCX_CMD_RCGR",
+	"GCC_PCIE_2_AUX_CMD_RCGR",
+};
+
 static struct msm_clk_data qcs404_gcc_data = {
 	.resets = sm8250_gcc_resets,
 	.num_resets = ARRAY_SIZE(sm8250_gcc_resets),
@@ -263,6 +372,12 @@
 
 	.enable = sm8250_enable,
 	.set_rate = sm8250_set_rate,
+
+	.dbg_pll_addrs = sm8250_gpll_addrs,
+	.num_plls = ARRAY_SIZE(sm8250_gpll_addrs),
+	.dbg_rcg_addrs = sm8250_rcg_addrs,
+	.num_rcgs = ARRAY_SIZE(sm8250_rcg_addrs),
+	.dbg_rcg_names = sm8250_rcg_names,
 };
 
 static const struct udevice_id gcc_sm8250_of_match[] = {