Merge tag 'next-20230307' of https://source.denx.de/u-boot/custodians/u-boot-video into next
- video console refactoring and optimization
- support for fonts wider than 1 byte
- use named header for 8x16 font data
- support multiple fonts configuration
- move get_font_size() to truetype driver ops
- support font size configuration at runtime
- add 16x32 Terminus font from linux
- add 12x22 Sun font from linux
- add 12x22 console simple font test
diff --git a/MAINTAINERS b/MAINTAINERS
index 41c9f26..e29c16c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1460,12 +1460,8 @@
F: configs/k2l_hs_evm_defconfig
F: configs/am65x_hs_evm_r5_defconfig
F: configs/am65x_hs_evm_a53_defconfig
-F: configs/j7200_hs_evm_a72_defconfig
-F: configs/j7200_hs_evm_r5_defconfig
F: configs/j721e_hs_evm_a72_defconfig
F: configs/j721e_hs_evm_r5_defconfig
-F: configs/j721s2_hs_evm_a72_defconfig
-F: configs/j721s2_hs_evm_r5_defconfig
TPM DRIVERS
M: Ilias Apalodimas <ilias.apalodimas@linaro.org>
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 7e7ad4f..8cfe3f0 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -13,7 +13,6 @@
endif
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
-obj-$(if $(filter spear,$(SOC)),y) += spear/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
# some files can only build in ARM or THUMB2, not THUMB1
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 1305238..7d5cf15 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -1,5 +1,9 @@
if ARM64
+config CMO_BY_VA_ONLY
+ bool "Force cache maintenance to be exclusively by VA"
+ depends on !SYS_DISABLE_DCACHE_OPS
+
config ARMV8_SPL_EXCEPTION_VECTORS
bool "Install crash dump exception vectors"
depends on SPL
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index d1cee23..3fe935c 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -12,6 +12,7 @@
#include <asm/system.h>
#include <linux/linkage.h>
+#ifndef CONFIG_CMO_BY_VA_ONLY
/*
* void __asm_dcache_level(level)
*
@@ -116,6 +117,41 @@
ENDPROC(__asm_invalidate_dcache_all)
.popsection
+.pushsection .text.__asm_flush_l3_dcache, "ax"
+WEAK(__asm_flush_l3_dcache)
+ mov x0, #0 /* return status as success */
+ ret
+ENDPROC(__asm_flush_l3_dcache)
+.popsection
+
+.pushsection .text.__asm_invalidate_l3_icache, "ax"
+WEAK(__asm_invalidate_l3_icache)
+ mov x0, #0 /* return status as success */
+ ret
+ENDPROC(__asm_invalidate_l3_icache)
+.popsection
+
+#else /* CONFIG_CMO_BY_VA */
+
+/*
+ * Define these so that they actively clash with in implementation
+ * accidentally selecting CONFIG_CMO_BY_VA
+ */
+
+.pushsection .text.__asm_invalidate_l3_icache, "ax"
+ENTRY(__asm_invalidate_l3_icache)
+ mov x0, xzr
+ ret
+ENDPROC(__asm_invalidate_l3_icache)
+.popsection
+.pushsection .text.__asm_flush_l3_dcache, "ax"
+ENTRY(__asm_flush_l3_dcache)
+ mov x0, xzr
+ ret
+ENDPROC(__asm_flush_l3_dcache)
+.popsection
+#endif /* CONFIG_CMO_BY_VA */
+
/*
* void __asm_flush_dcache_range(start, end)
*
@@ -189,20 +225,6 @@
ENDPROC(__asm_invalidate_l3_dcache)
.popsection
-.pushsection .text.__asm_flush_l3_dcache, "ax"
-WEAK(__asm_flush_l3_dcache)
- mov x0, #0 /* return status as success */
- ret
-ENDPROC(__asm_flush_l3_dcache)
-.popsection
-
-.pushsection .text.__asm_invalidate_l3_icache, "ax"
-WEAK(__asm_invalidate_l3_icache)
- mov x0, #0 /* return status as success */
- ret
-ENDPROC(__asm_invalidate_l3_icache)
-.popsection
-
/*
* void __asm_switch_ttbr(ulong new_ttbr)
*
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 2a226fd..6973340 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -163,6 +163,83 @@
return NULL;
}
+#ifdef CONFIG_CMO_BY_VA_ONLY
+static void __cmo_on_leaves(void (*cmo_fn)(unsigned long, unsigned long),
+ u64 pte, int level, u64 base)
+{
+ u64 *ptep;
+ int i;
+
+ ptep = (u64 *)(pte & GENMASK_ULL(47, PAGE_SHIFT));
+ for (i = 0; i < PAGE_SIZE / sizeof(u64); i++) {
+ u64 end, va = base + i * BIT(level2shift(level));
+ u64 type, attrs;
+
+ pte = ptep[i];
+ type = pte & PTE_TYPE_MASK;
+ attrs = pte & PMD_ATTRINDX_MASK;
+ debug("PTE %llx at level %d VA %llx\n", pte, level, va);
+
+ /* Not valid? next! */
+ if (!(type & PTE_TYPE_VALID))
+ continue;
+
+ /* Not a leaf? Recurse on the next level */
+ if (!(type == PTE_TYPE_BLOCK ||
+ (level == 3 && type == PTE_TYPE_PAGE))) {
+ __cmo_on_leaves(cmo_fn, pte, level + 1, va);
+ continue;
+ }
+
+ /*
+ * From this point, this must be a leaf.
+ *
+ * Start excluding non memory mappings
+ */
+ if (attrs != PTE_BLOCK_MEMTYPE(MT_NORMAL) &&
+ attrs != PTE_BLOCK_MEMTYPE(MT_NORMAL_NC))
+ continue;
+
+ end = va + BIT(level2shift(level)) - 1;
+
+ /* No intersection with RAM? */
+ if (end < gd->ram_base ||
+ va >= (gd->ram_base + gd->ram_size))
+ continue;
+
+ /*
+ * OK, we have a partial RAM mapping. However, this
+ * can cover *more* than the RAM. Yes, u-boot is
+ * *that* braindead. Compute the intersection we care
+ * about, and not a byte more.
+ */
+ va = max(va, (u64)gd->ram_base);
+ end = min(end, gd->ram_base + gd->ram_size);
+
+ debug("Flush PTE %llx at level %d: %llx-%llx\n",
+ pte, level, va, end);
+ cmo_fn(va, end);
+ }
+}
+
+static void apply_cmo_to_mappings(void (*cmo_fn)(unsigned long, unsigned long))
+{
+ u64 va_bits;
+ int sl = 0;
+
+ if (!gd->arch.tlb_addr)
+ return;
+
+ get_tcr(NULL, &va_bits);
+ if (va_bits < 39)
+ sl = 1;
+
+ __cmo_on_leaves(cmo_fn, gd->arch.tlb_addr, sl, 0);
+}
+#else
+static inline void apply_cmo_to_mappings(void *dummy) {}
+#endif
+
/* Returns and creates a new full table (512 entries) */
static u64 *create_table(void)
{
@@ -222,153 +299,110 @@
set_pte_table(pte, new_table);
}
-/* Add one mm_region map entry to the page tables */
-static void add_map(struct mm_region *map)
+static void map_range(u64 virt, u64 phys, u64 size, int level,
+ u64 *table, u64 attrs)
{
- u64 *pte;
- u64 virt = map->virt;
- u64 phys = map->phys;
- u64 size = map->size;
- u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
- u64 blocksize;
- int level;
- u64 *new_table;
+ u64 map_size = BIT_ULL(level2shift(level));
+ int i, idx;
- while (size) {
- pte = find_pte(virt, 0);
- if (pte && (pte_type(pte) == PTE_TYPE_FAULT)) {
- debug("Creating table for virt 0x%llx\n", virt);
- new_table = create_table();
- set_pte_table(pte, new_table);
- }
+ idx = (virt >> level2shift(level)) & (MAX_PTE_ENTRIES - 1);
+ for (i = idx; size; i++) {
+ u64 next_size, *next_table;
+
+ if (level >= 1 &&
+ size >= map_size && !(virt & (map_size - 1))) {
+ if (level == 3)
+ table[i] = phys | attrs | PTE_TYPE_PAGE;
+ else
+ table[i] = phys | attrs;
- for (level = 1; level < 4; level++) {
- pte = find_pte(virt, level);
- if (!pte)
- panic("pte not found\n");
+ virt += map_size;
+ phys += map_size;
+ size -= map_size;
- blocksize = 1ULL << level2shift(level);
- debug("Checking if pte fits for virt=%llx size=%llx blocksize=%llx\n",
- virt, size, blocksize);
- if (size >= blocksize && !(virt & (blocksize - 1))) {
- /* Page fits, create block PTE */
- debug("Setting PTE %p to block virt=%llx\n",
- pte, virt);
- if (level == 3)
- *pte = phys | attrs | PTE_TYPE_PAGE;
- else
- *pte = phys | attrs;
- virt += blocksize;
- phys += blocksize;
- size -= blocksize;
- break;
- } else if (pte_type(pte) == PTE_TYPE_FAULT) {
- /* Page doesn't fit, create subpages */
- debug("Creating subtable for virt 0x%llx blksize=%llx\n",
- virt, blocksize);
- new_table = create_table();
- set_pte_table(pte, new_table);
- } else if (pte_type(pte) == PTE_TYPE_BLOCK) {
- debug("Split block into subtable for virt 0x%llx blksize=0x%llx\n",
- virt, blocksize);
- split_block(pte, level);
- }
+ continue;
}
+
+ /* Going one level down */
+ if (pte_type(&table[i]) == PTE_TYPE_FAULT)
+ set_pte_table(&table[i], create_table());
+
+ next_table = (u64 *)(table[i] & GENMASK_ULL(47, PAGE_SHIFT));
+ next_size = min(map_size - (virt & (map_size - 1)), size);
+
+ map_range(virt, phys, next_size, level + 1, next_table, attrs);
+
+ virt += next_size;
+ phys += next_size;
+ size -= next_size;
}
}
-enum pte_type {
- PTE_INVAL,
- PTE_BLOCK,
- PTE_LEVEL,
-};
-
-/*
- * This is a recursively called function to count the number of
- * page tables we need to cover a particular PTE range. If you
- * call this with level = -1 you basically get the full 48 bit
- * coverage.
- */
-static int count_required_pts(u64 addr, int level, u64 maxaddr)
+static void add_map(struct mm_region *map)
{
- int levelshift = level2shift(level);
- u64 levelsize = 1ULL << levelshift;
- u64 levelmask = levelsize - 1;
- u64 levelend = addr + levelsize;
- int r = 0;
- int i;
- enum pte_type pte_type = PTE_INVAL;
+ u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
+ u64 va_bits;
+ int level = 0;
+
+ get_tcr(NULL, &va_bits);
+ if (va_bits < 39)
+ level = 1;
- for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) {
- struct mm_region *map = &mem_map[i];
- u64 start = map->virt;
- u64 end = start + map->size;
+ map_range(map->virt, map->phys, map->size, level,
+ (u64 *)gd->arch.tlb_addr, attrs);
+}
- /* Check if the PTE would overlap with the map */
- if (max(addr, start) <= min(levelend, end)) {
- start = max(addr, start);
- end = min(levelend, end);
+static void count_range(u64 virt, u64 size, int level, int *cntp)
+{
+ u64 map_size = BIT_ULL(level2shift(level));
+ int i, idx;
- /* We need a sub-pt for this level */
- if ((start & levelmask) || (end & levelmask)) {
- pte_type = PTE_LEVEL;
- break;
- }
+ idx = (virt >> level2shift(level)) & (MAX_PTE_ENTRIES - 1);
+ for (i = idx; size; i++) {
+ u64 next_size;
- /* Lv0 can not do block PTEs, so do levels here too */
- if (level <= 0) {
- pte_type = PTE_LEVEL;
- break;
- }
+ if (level >= 1 &&
+ size >= map_size && !(virt & (map_size - 1))) {
+ virt += map_size;
+ size -= map_size;
- /* PTE is active, but fits into a block */
- pte_type = PTE_BLOCK;
+ continue;
}
- }
- /*
- * Block PTEs at this level are already covered by the parent page
- * table, so we only need to count sub page tables.
- */
- if (pte_type == PTE_LEVEL) {
- int sublevel = level + 1;
- u64 sublevelsize = 1ULL << level2shift(sublevel);
-
- /* Account for the new sub page table ... */
- r = 1;
+ /* Going one level down */
+ (*cntp)++;
+ next_size = min(map_size - (virt & (map_size - 1)), size);
- /* ... and for all child page tables that one might have */
- for (i = 0; i < MAX_PTE_ENTRIES; i++) {
- r += count_required_pts(addr, sublevel, maxaddr);
- addr += sublevelsize;
+ count_range(virt, next_size, level + 1, cntp);
- if (addr >= maxaddr) {
- /*
- * We reached the end of address space, no need
- * to look any further.
- */
- break;
- }
- }
+ virt += next_size;
+ size -= next_size;
}
-
- return r;
}
-/* Returns the estimated required size of all page tables */
-__weak u64 get_page_table_size(void)
+static int count_ranges(void)
{
- u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
- u64 size = 0;
+ int i, count = 0, level = 0;
u64 va_bits;
- int start_level = 0;
get_tcr(NULL, &va_bits);
if (va_bits < 39)
- start_level = 1;
+ level = 1;
+
+ for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
+ count_range(mem_map[i].virt, mem_map[i].size, level, &count);
+
+ return count;
+}
+
+/* Returns the estimated required size of all page tables */
+__weak u64 get_page_table_size(void)
+{
+ u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
+ u64 size;
/* Account for all page tables we would need to cover our memory map */
- size = one_pt * count_required_pts(0, start_level - 1, 1ULL << va_bits);
+ size = one_pt * count_ranges();
/*
* We need to duplicate our page table once to have an emergency pt to
@@ -447,8 +481,12 @@
*/
void invalidate_dcache_all(void)
{
+#ifndef CONFIG_CMO_BY_VA_ONLY
__asm_invalidate_dcache_all();
__asm_invalidate_l3_dcache();
+#else
+ apply_cmo_to_mappings(invalidate_dcache_range);
+#endif
}
/*
@@ -458,6 +496,7 @@
*/
inline void flush_dcache_all(void)
{
+#ifndef CONFIG_CMO_BY_VA_ONLY
int ret;
__asm_flush_dcache_all();
@@ -466,6 +505,9 @@
debug("flushing dcache returns 0x%x\n", ret);
else
debug("flushing dcache successfully.\n");
+#else
+ apply_cmo_to_mappings(flush_dcache_range);
+#endif
}
#ifndef CONFIG_SYS_DISABLE_DCACHE_OPS
@@ -520,9 +562,19 @@
if (!(sctlr & CR_C))
return;
+ if (IS_ENABLED(CONFIG_CMO_BY_VA_ONLY)) {
+ /*
+ * When invalidating by VA, do it *before* turning the MMU
+ * off, so that at least our stack is coherent.
+ */
+ flush_dcache_all();
+ }
+
set_sctlr(sctlr & ~(CR_C|CR_M));
- flush_dcache_all();
+ if (!IS_ENABLED(CONFIG_CMO_BY_VA_ONLY))
+ flush_dcache_all();
+
__asm_invalidate_tlb_all();
}
diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
index db5d460..3c7f36a 100644
--- a/arch/arm/cpu/armv8/cpu.c
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -48,18 +48,26 @@
disable_interrupts();
- /*
- * Turn off I-cache and invalidate it
- */
- icache_disable();
- invalidate_icache_all();
+ if (IS_ENABLED(CONFIG_CMO_BY_VA_ONLY)) {
+ /*
+ * Disable D-cache.
+ */
+ dcache_disable();
+ } else {
+ /*
+ * Turn off I-cache and invalidate it
+ */
+ icache_disable();
+ invalidate_icache_all();
- /*
- * turn off D-cache
- * dcache_disable() in turn flushes the d-cache and disables MMU
- */
- dcache_disable();
- invalidate_dcache_all();
+ /*
+ * turn off D-cache
+ * dcache_disable() in turn flushes the d-cache and disables
+ * MMU
+ */
+ dcache_disable();
+ invalidate_dcache_all();
+ }
return 0;
}
diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts
index 7a15b44..c953a82 100644
--- a/arch/arm/dts/k3-am62a7-r5-sk.dts
+++ b/arch/arm/dts/k3-am62a7-r5-sk.dts
@@ -25,7 +25,9 @@
memory@80000000 {
device_type = "memory";
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>; /* 2G RAM */
+ /* 4G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000000 0x80000000>;
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts
index 576dbce..b08a083 100644
--- a/arch/arm/dts/k3-am62a7-sk.dts
+++ b/arch/arm/dts/k3-am62a7-sk.dts
@@ -26,8 +26,9 @@
memory@80000000 {
device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+ /* 4G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
diff --git a/arch/arm/dts/uniphier-ld11-global.dts b/arch/arm/dts/uniphier-ld11-global.dts
index 644ffb9..da44a15 100644
--- a/arch/arm/dts/uniphier-ld11-global.dts
+++ b/arch/arm/dts/uniphier-ld11-global.dts
@@ -164,4 +164,8 @@
&nand {
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ };
};
diff --git a/arch/arm/dts/uniphier-ld11-ref.dts b/arch/arm/dts/uniphier-ld11-ref.dts
index 617d2b1..414aeb9 100644
--- a/arch/arm/dts/uniphier-ld11-ref.dts
+++ b/arch/arm/dts/uniphier-ld11-ref.dts
@@ -39,11 +39,11 @@
};
ðsc {
- interrupts = <0 8>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
- interrupts = <0 8>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&serial0 {
@@ -51,7 +51,7 @@
};
&gpio {
- xirq0 {
+ xirq0-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
input;
diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi
index 104d56d..7bb36b0 100644
--- a/arch/arm/dts/uniphier-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "socionext,uniphier-ld11";
@@ -35,6 +36,7 @@
reg = <0 0x000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
+ next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
};
@@ -44,8 +46,13 @@
reg = <0 0x001>;
clocks = <&sys_clk 33>;
enable-method = "psci";
+ next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
};
+
+ l2: l2-cache {
+ compatible = "cache";
+ };
};
cluster0_opp: opp-table {
@@ -102,10 +109,10 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 4>,
- <1 14 4>,
- <1 11 4>,
- <1 10 4>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
reserved-memory {
@@ -131,7 +138,7 @@
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 39 4>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
@@ -144,7 +151,7 @@
reg = <0x54006100 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 216 4>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 12>;
@@ -155,7 +162,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
@@ -166,7 +173,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
@@ -177,7 +184,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
@@ -188,7 +195,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
- interrupts = <0 177 4>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
@@ -223,7 +230,7 @@
audio@56000000 {
compatible = "socionext,uniphier-ld11-aio";
reg = <0x56000000 0x80000>;
- interrupts = <0 144 4>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_aout1>,
<&pinctrl_aoutiec1>;
@@ -306,12 +313,12 @@
};
};
- adamv@57920000 {
+ syscon@57920000 {
compatible = "socionext,uniphier-ld11-adamv",
"simple-mfd", "syscon";
reg = <0x57920000 0x1000>;
- adamv_rst: reset {
+ adamv_rst: reset-controller {
compatible = "socionext,uniphier-ld11-adamv-reset";
#reset-cells = <1>;
};
@@ -323,7 +330,7 @@
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 41 4>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
@@ -337,7 +344,7 @@
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 42 4>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
@@ -350,7 +357,7 @@
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 43 4>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 6>;
resets = <&peri_rst 6>;
clock-frequency = <400000>;
@@ -362,7 +369,7 @@
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 44 4>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
@@ -376,7 +383,7 @@
reg = <0x58784000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 45 4>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clocks = <&peri_clk 8>;
@@ -389,7 +396,7 @@
reg = <0x58785000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 25 4>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 9>;
resets = <&peri_rst 9>;
clock-frequency = <400000>;
@@ -410,28 +417,28 @@
reg = <0x59801000 0x400>;
};
- sdctrl@59810000 {
+ syscon@59810000 {
compatible = "socionext,uniphier-ld11-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
- sd_rst: reset {
+ sd_rst: reset-controller {
compatible = "socionext,uniphier-ld11-sd-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-ld11-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-ld11-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-ld11-peri-reset";
#reset-cells = <1>;
};
@@ -440,7 +447,7 @@
emmc: mmc@5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
reg = <0x5a000000 0x400>;
- interrupts = <0 78 4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&sys_clk 4>;
@@ -460,7 +467,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
- interrupts = <0 243 4>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
@@ -476,7 +483,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
- interrupts = <0 244 4>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
@@ -492,7 +499,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
- interrupts = <0 245 4>;
+ interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
@@ -504,24 +511,24 @@
has-transaction-translator;
};
- mioctrl@5b3e0000 {
+ syscon@5b3e0000 {
compatible = "socionext,uniphier-ld11-mioctrl",
"simple-mfd", "syscon";
reg = <0x5b3e0000 0x800>;
- mio_clk: clock {
+ mio_clk: clock-controller {
compatible = "socionext,uniphier-ld11-mio-clock";
#clock-cells = <1>;
};
- mio_rst: reset {
+ mio_rst: reset-controller {
compatible = "socionext,uniphier-ld11-mio-reset";
#reset-cells = <1>;
resets = <&sys_rst 7>;
};
};
- soc_glue: soc-glue@5f800000 {
+ soc_glue: syscon@5f800000 {
compatible = "socionext,uniphier-ld11-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -530,7 +537,7 @@
compatible = "socionext,uniphier-ld11-pinctrl";
};
- usb-phy {
+ usb-hub {
compatible = "socionext,uniphier-ld11-usb2-phy";
#address-cells = <1>;
#size-cells = <0>;
@@ -552,9 +559,10 @@
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-ld11-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
@@ -573,7 +581,7 @@
xdmac: dma-controller@5fc10000 {
compatible = "socionext,uniphier-xdmac";
reg = <0x5fc10000 0x5300>;
- interrupts = <0 188 4>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <2>;
};
@@ -591,20 +599,20 @@
<0x5fe40000 0x80000>; /* GICR */
interrupt-controller;
#interrupt-cells = <3>;
- interrupts = <1 9 4>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-ld11-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-ld11-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-ld11-reset";
#reset-cells = <1>;
};
@@ -618,7 +626,7 @@
compatible = "socionext,uniphier-ld11-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
- interrupts = <0 66 4>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ether";
clocks = <&sys_clk 6>;
reset-names = "ether";
@@ -638,7 +646,9 @@
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
- interrupts = <0 65 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi
index 4549935..4e21716 100644
--- a/arch/arm/dts/uniphier-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -45,6 +46,7 @@
reg = <0 0x000>;
clocks = <&sys_clk 32>;
enable-method = "psci";
+ next-level-cache = <&a72_l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@@ -55,6 +57,7 @@
reg = <0 0x001>;
clocks = <&sys_clk 32>;
enable-method = "psci";
+ next-level-cache = <&a72_l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@@ -65,6 +68,7 @@
reg = <0 0x100>;
clocks = <&sys_clk 33>;
enable-method = "psci";
+ next-level-cache = <&a53_l2>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
};
@@ -75,12 +79,21 @@
reg = <0 0x101>;
clocks = <&sys_clk 33>;
enable-method = "psci";
+ next-level-cache = <&a53_l2>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
};
+
+ a72_l2: l2-cache0 {
+ compatible = "cache";
+ };
+
+ a53_l2: l2-cache1 {
+ compatible = "cache";
+ };
};
- cluster0_opp: opp-table0 {
+ cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -118,7 +131,7 @@
};
};
- cluster1_opp: opp-table1 {
+ cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
@@ -176,10 +189,10 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 4>,
- <1 14 4>,
- <1 11 4>,
- <1 10 4>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
thermal-zones {
@@ -236,7 +249,7 @@
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 39 4>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
@@ -249,7 +262,7 @@
reg = <0x54006100 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 216 4>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 12>;
@@ -262,7 +275,7 @@
reg = <0x54006200 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 229 4>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
clocks = <&peri_clk 13>;
@@ -275,7 +288,7 @@
reg = <0x54006300 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 230 4>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi3>;
clocks = <&peri_clk 14>;
@@ -286,7 +299,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
@@ -297,7 +310,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
@@ -308,7 +321,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
@@ -319,7 +332,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
- interrupts = <0 177 4>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
@@ -348,7 +361,7 @@
audio@56000000 {
compatible = "socionext,uniphier-ld20-aio";
reg = <0x56000000 0x80000>;
- interrupts = <0 144 4>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_aout1>,
<&pinctrl_aoutiec1>;
@@ -431,12 +444,12 @@
};
};
- adamv@57920000 {
+ syscon@57920000 {
compatible = "socionext,uniphier-ld20-adamv",
"simple-mfd", "syscon";
reg = <0x57920000 0x1000>;
- adamv_rst: reset {
+ adamv_rst: reset-controller {
compatible = "socionext,uniphier-ld20-adamv-reset";
#reset-cells = <1>;
};
@@ -448,7 +461,7 @@
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 41 4>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
@@ -462,7 +475,7 @@
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 42 4>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
@@ -475,7 +488,7 @@
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 43 4>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 6>;
resets = <&peri_rst 6>;
clock-frequency = <400000>;
@@ -487,7 +500,7 @@
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 44 4>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
@@ -501,7 +514,7 @@
reg = <0x58784000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 45 4>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clocks = <&peri_clk 8>;
@@ -514,7 +527,7 @@
reg = <0x58785000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 25 4>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 9>;
resets = <&peri_rst 9>;
clock-frequency = <400000>;
@@ -535,33 +548,33 @@
reg = <0x59801000 0x400>;
};
- sdctrl@59810000 {
+ sdctrl: syscon@59810000 {
compatible = "socionext,uniphier-ld20-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
- sd_clk: clock {
+ sd_clk: clock-controller {
compatible = "socionext,uniphier-ld20-sd-clock";
#clock-cells = <1>;
};
- sd_rst: reset {
+ sd_rst: reset-controller {
compatible = "socionext,uniphier-ld20-sd-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-ld20-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-ld20-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-ld20-peri-reset";
#reset-cells = <1>;
};
@@ -570,7 +583,7 @@
emmc: mmc@5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
reg = <0x5a000000 0x400>;
- interrupts = <0 78 4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&sys_clk 4>;
@@ -590,7 +603,7 @@
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a400000 0x800>;
- interrupts = <0 76 4>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd>;
clocks = <&sd_clk 0>;
@@ -598,9 +611,10 @@
resets = <&sd_rst 0>;
bus-width = <4>;
cap-sd-highspeed;
+ socionext,syscon-uhs-mode = <&sdctrl 0>;
};
- soc_glue: soc-glue@5f800000 {
+ soc_glue: syscon@5f800000 {
compatible = "socionext,uniphier-ld20-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -610,9 +624,10 @@
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-ld20-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
@@ -675,7 +690,7 @@
xdmac: dma-controller@5fc10000 {
compatible = "socionext,uniphier-xdmac";
reg = <0x5fc10000 0x5300>;
- interrupts = <0 188 4>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <2>;
};
@@ -693,20 +708,20 @@
<0x5fe80000 0x80000>; /* GICR */
interrupt-controller;
#interrupt-cells = <3>;
- interrupts = <1 9 4>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-ld20-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-ld20-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-ld20-reset";
#reset-cells = <1>;
};
@@ -715,9 +730,9 @@
compatible = "socionext,uniphier-wdt";
};
- pvtctl: pvtctl {
+ pvtctl: thermal-sensor {
compatible = "socionext,uniphier-ld20-thermal";
- interrupts = <0 3 4>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <0>;
socionext,tmod-calibration = <0x0f22 0x68ee>;
};
@@ -727,7 +742,7 @@
compatible = "socionext,uniphier-ld20-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
- interrupts = <0 66 4>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
clock-names = "ether";
@@ -744,12 +759,12 @@
};
};
- _usb: usb@65a00000 {
+ usb: usb@65a00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
reg = <0x65a00000 0xcd00>;
interrupt-names = "host";
- interrupts = <0 134 4>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
<&pinctrl_usb2>, <&pinctrl_usb3>;
@@ -762,14 +777,15 @@
dr_mode = "host";
};
- usb-glue@65b00000 {
+ usb-controller@65b00000 {
compatible = "socionext,uniphier-ld20-dwc3-glue",
"simple-mfd";
+ reg = <0x65b00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
- usb_rst: reset@0 {
+ usb_rst: reset-controller@0 {
compatible = "socionext,uniphier-ld20-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -815,7 +831,7 @@
resets = <&sys_rst 14>;
};
- usb_hsphy0: hs-phy@200 {
+ usb_hsphy0: phy@200 {
compatible = "socionext,uniphier-ld20-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
@@ -829,7 +845,7 @@
<&usb_hs_i0>;
};
- usb_hsphy1: hs-phy@210 {
+ usb_hsphy1: phy@210 {
compatible = "socionext,uniphier-ld20-usb3-hsphy";
reg = <0x210 0x10>;
#phy-cells = <0>;
@@ -843,7 +859,7 @@
<&usb_hs_i0>;
};
- usb_hsphy2: hs-phy@220 {
+ usb_hsphy2: phy@220 {
compatible = "socionext,uniphier-ld20-usb3-hsphy";
reg = <0x220 0x10>;
#phy-cells = <0>;
@@ -857,7 +873,7 @@
<&usb_hs_i2>;
};
- usb_hsphy3: hs-phy@230 {
+ usb_hsphy3: phy@230 {
compatible = "socionext,uniphier-ld20-usb3-hsphy";
reg = <0x230 0x10>;
#phy-cells = <0>;
@@ -871,7 +887,7 @@
<&usb_hs_i2>;
};
- usb_ssphy0: ss-phy@300 {
+ usb_ssphy0: phy@300 {
compatible = "socionext,uniphier-ld20-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
@@ -882,7 +898,7 @@
vbus-supply = <&usb_vbus0>;
};
- usb_ssphy1: ss-phy@310 {
+ usb_ssphy1: phy@310 {
compatible = "socionext,uniphier-ld20-usb3-ssphy";
reg = <0x310 0x10>;
#phy-cells = <0>;
@@ -894,27 +910,8 @@
};
};
- /* FIXME: U-Boot own node */
- usb: usb@65b00000 {
- compatible = "socionext,uniphier-ld20-dwc3";
- reg = <0x65b00000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
- <&pinctrl_usb2>, <&pinctrl_usb3>;
- dwc3@65a00000 {
- compatible = "snps,dwc3";
- reg = <0x65a00000 0x10000>;
- interrupts = <0 134 4>;
- dr_mode = "host";
- tx-fifo-resize;
- };
- };
-
pcie: pcie@66000000 {
- compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
+ compatible = "socionext,uniphier-pcie";
status = "disabled";
reg-names = "dbi", "link", "config";
reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
@@ -934,7 +931,8 @@
<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
#interrupt-cells = <1>;
interrupt-names = "dma", "msi";
- interrupts = <0 224 4>, <0 225 4>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
<0 0 0 2 &pcie_intc 1>, /* INTB */
@@ -947,7 +945,7 @@
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
- interrupts = <0 226 4>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -967,7 +965,9 @@
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
- interrupts = <0 65 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
diff --git a/arch/arm/dts/uniphier-ld4-ref.dts b/arch/arm/dts/uniphier-ld4-ref.dts
index 03fe696..e007db0 100644
--- a/arch/arm/dts/uniphier-ld4-ref.dts
+++ b/arch/arm/dts/uniphier-ld4-ref.dts
@@ -36,11 +36,11 @@
};
ðsc {
- interrupts = <1 8>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
- interrupts = <1 8>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
};
&serial0 {
@@ -56,7 +56,7 @@
};
&gpio {
- xirq1 {
+ xirq1-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(1) 0>;
input;
@@ -81,4 +81,8 @@
&nand {
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ };
};
diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi
index 897162d..1baf590 100644
--- a/arch/arm/dts/uniphier-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ld4.dtsi
@@ -6,6 +6,7 @@
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "socionext,uniphier-ld4";
@@ -55,7 +56,8 @@
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-size = <(512 * 1024)>;
cache-sets = <256>;
@@ -69,7 +71,7 @@
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 39 4>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
@@ -80,7 +82,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
@@ -91,7 +93,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
@@ -102,7 +104,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
@@ -113,7 +115,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
- interrupts = <0 29 4>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
@@ -140,7 +142,7 @@
reg = <0x58400000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 41 1>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
@@ -154,7 +156,7 @@
reg = <0x58480000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 42 1>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
@@ -168,7 +170,7 @@
reg = <0x58500000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 43 1>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
@@ -182,7 +184,7 @@
reg = <0x58580000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 44 1>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
@@ -205,33 +207,33 @@
reg = <0x59801000 0x400>;
};
- mioctrl@59810000 {
+ syscon@59810000 {
compatible = "socionext,uniphier-ld4-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
- mio_clk: clock {
+ mio_clk: clock-controller {
compatible = "socionext,uniphier-ld4-mio-clock";
#clock-cells = <1>;
};
- mio_rst: reset {
+ mio_rst: reset-controller {
compatible = "socionext,uniphier-ld4-mio-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-ld4-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-ld4-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-ld4-peri-reset";
#reset-cells = <1>;
};
@@ -240,8 +242,13 @@
dmac: dma-controller@5a000000 {
compatible = "socionext,uniphier-mio-dmac";
reg = <0x5a000000 0x1000>;
- interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
- <0 71 4>, <0 72 4>, <0 73 4>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mio_clk 7>;
resets = <&mio_rst 7>;
#dma-cells = <1>;
@@ -251,7 +258,7 @@
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a400000 0x200>;
- interrupts = <0 76 4>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "uhs";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_uhs>;
@@ -271,7 +278,7 @@
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a500000 0x200>;
- interrupts = <0 78 4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&mio_clk 1>;
@@ -289,7 +296,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
@@ -303,7 +310,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
@@ -317,7 +324,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
- interrupts = <0 82 4>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
@@ -327,7 +334,7 @@
has-transaction-translator;
};
- soc-glue@5f800000 {
+ syscon@5f800000 {
compatible = "socionext,uniphier-ld4-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -337,9 +344,10 @@
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-ld4-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
@@ -358,14 +366,16 @@
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
- interrupts = <1 11 0x104>;
+ interrupts = <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
- interrupts = <1 13 0x104>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
@@ -384,17 +394,17 @@
#interrupt-cells = <2>;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-ld4-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-ld4-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-ld4-reset";
#reset-cells = <1>;
};
@@ -405,7 +415,9 @@
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
- interrupts = <0 65 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand2cs>;
clock-names = "nand", "nand_x", "ecc";
diff --git a/arch/arm/dts/uniphier-pro4-ace.dts b/arch/arm/dts/uniphier-pro4-ace.dts
index 27ff2b7..6baee44 100644
--- a/arch/arm/dts/uniphier-pro4-ace.dts
+++ b/arch/arm/dts/uniphier-pro4-ace.dts
@@ -99,3 +99,11 @@
&usb1 {
status = "okay";
};
+
+&ahci0 {
+ status = "okay";
+};
+
+&ahci1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/uniphier-pro4-ref.dts b/arch/arm/dts/uniphier-pro4-ref.dts
index 3e1bc12..202ca84 100644
--- a/arch/arm/dts/uniphier-pro4-ref.dts
+++ b/arch/arm/dts/uniphier-pro4-ref.dts
@@ -40,11 +40,11 @@
};
ðsc {
- interrupts = <2 8>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
- interrupts = <2 8>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
};
&serial0 {
@@ -60,7 +60,7 @@
};
&gpio {
- xirq2 {
+ xirq2-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(2) 0>;
input;
@@ -104,4 +104,16 @@
&nand {
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ };
+};
+
+&ahci0 {
+ status = "okay";
+};
+
+&ahci1 {
+ status = "okay";
};
diff --git a/arch/arm/dts/uniphier-pro4-sanji.dts b/arch/arm/dts/uniphier-pro4-sanji.dts
index e7c122d..7b6faf2 100644
--- a/arch/arm/dts/uniphier-pro4-sanji.dts
+++ b/arch/arm/dts/uniphier-pro4-sanji.dts
@@ -64,15 +64,15 @@
status = "okay";
};
-&emmc {
+&usb2 {
status = "okay";
};
-&usb2 {
+&usb3 {
status = "okay";
};
-&usb3 {
+&emmc {
status = "okay";
};
diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi
index 9dae4e9..ba55af3 100644
--- a/arch/arm/dts/uniphier-pro4.dtsi
+++ b/arch/arm/dts/uniphier-pro4.dtsi
@@ -6,6 +6,7 @@
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "socionext,uniphier-pro4";
@@ -63,7 +64,8 @@
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-size = <(768 * 1024)>;
cache-sets = <256>;
@@ -77,7 +79,7 @@
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 39 4>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
@@ -88,7 +90,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
@@ -99,7 +101,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
@@ -110,7 +112,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
@@ -121,7 +123,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
- interrupts = <0 177 4>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
@@ -148,7 +150,7 @@
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 41 4>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
@@ -162,7 +164,7 @@
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 42 4>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
@@ -176,7 +178,7 @@
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 43 4>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
@@ -190,7 +192,7 @@
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 44 4>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
@@ -206,7 +208,7 @@
reg = <0x58785000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 25 4>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 9>;
resets = <&peri_rst 9>;
clock-frequency = <400000>;
@@ -218,7 +220,7 @@
reg = <0x58786000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 26 4>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 10>;
resets = <&peri_rst 10>;
clock-frequency = <400000>;
@@ -239,33 +241,33 @@
reg = <0x59801000 0x400>;
};
- mioctrl@59810000 {
+ mioctrl: syscon@59810000 {
compatible = "socionext,uniphier-pro4-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
- mio_clk: clock {
+ mio_clk: clock-controller {
compatible = "socionext,uniphier-pro4-mio-clock";
#clock-cells = <1>;
};
- mio_rst: reset {
+ mio_rst: reset-controller {
compatible = "socionext,uniphier-pro4-mio-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-pro4-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-pro4-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-pro4-peri-reset";
#reset-cells = <1>;
};
@@ -274,8 +276,14 @@
dmac: dma-controller@5a000000 {
compatible = "socionext,uniphier-mio-dmac";
reg = <0x5a000000 0x1000>;
- interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
- <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mio_clk 7>;
resets = <&mio_rst 7>;
#dma-cells = <1>;
@@ -285,7 +293,7 @@
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a400000 0x200>;
- interrupts = <0 76 4>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "uhs";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_uhs>;
@@ -299,13 +307,14 @@
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&mioctrl 0>;
};
emmc: mmc@5a500000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a500000 0x200>;
- interrupts = <0 78 4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&mio_clk 1>;
@@ -323,7 +332,7 @@
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a600000 0x200>;
- interrupts = <0 85 4>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd1>;
clocks = <&mio_clk 2>;
@@ -339,7 +348,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
@@ -355,7 +364,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
@@ -367,7 +376,7 @@
has-transaction-translator;
};
- soc_glue: soc-glue@5f800000 {
+ soc_glue: syscon@5f800000 {
compatible = "socionext,uniphier-pro4-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -376,7 +385,7 @@
compatible = "socionext,uniphier-pro4-pinctrl";
};
- usb-phy {
+ usb-hub {
compatible = "socionext,uniphier-pro4-usb2-phy";
#address-cells = <1>;
#size-cells = <0>;
@@ -403,11 +412,17 @@
vbus-supply = <&usb1_vbus>;
};
};
+
+ sg_clk: clock-controller {
+ compatible = "socionext,uniphier-pro4-sg-clock";
+ #clock-cells = <1>;
+ };
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-pro4-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
@@ -431,7 +446,7 @@
xdmac: dma-controller@5fc10000 {
compatible = "socionext,uniphier-xdmac";
reg = <0x5fc10000 0x5300>;
- interrupts = <0 188 4>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <2>;
};
@@ -446,14 +461,16 @@
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
- interrupts = <1 11 0x304>;
+ interrupts = <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
- interrupts = <1 13 0x304>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
@@ -465,17 +482,17 @@
interrupt-controller;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-pro4-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-pro4-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-pro4-reset";
#reset-cells = <1>;
};
@@ -485,7 +502,7 @@
compatible = "socionext,uniphier-pro4-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
- interrupts = <0 66 4>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
clock-names = "gio", "ether", "ether-gb", "ether-phy";
@@ -503,12 +520,107 @@
};
};
+ ahci0: sata@65600000 {
+ compatible = "socionext,uniphier-pro4-ahci",
+ "generic-ahci";
+ status = "disabled";
+ reg = <0x65600000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sys_clk 12>, <&sys_clk 28>;
+ resets = <&sys_rst 12>, <&sys_rst 28>, <&ahci0_rst 3>;
+ ports-implemented = <1>;
+ phys = <&ahci0_phy>;
+ assigned-clocks = <&sg_clk 0>;
+ assigned-clock-rates = <25000000>;
+ };
+
+ sata-controller@65700000 {
+ compatible = "socionext,uniphier-pxs2-ahci-glue",
+ "simple-mfd";
+ reg = <0x65700000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65700000 0x100>;
+
+ ahci0_rst: reset-controller@0 {
+ compatible = "socionext,uniphier-pro4-ahci-reset";
+ reg = <0x0 0x4>;
+ clock-names = "gio", "link";
+ clocks = <&sys_clk 12>, <&sys_clk 28>;
+ reset-names = "gio", "link";
+ resets = <&sys_rst 12>, <&sys_rst 28>;
+ #reset-cells = <1>;
+ };
+
+ ahci0_phy: phy@10 {
+ compatible = "socionext,uniphier-pro4-ahci-phy";
+ reg = <0x10 0x40>;
+ clock-names = "link", "gio";
+ clocks = <&sys_clk 28>, <&sys_clk 12>;
+ reset-names = "link", "gio", "phy",
+ "pm", "tx", "rx";
+ resets = <&sys_rst 28>, <&sys_rst 12>,
+ <&sys_rst 30>,
+ <&ahci0_rst 0>, <&ahci0_rst 1>,
+ <&ahci0_rst 2>;
+ #phy-cells = <0>;
+ };
+ };
+
- _usb0: usb@65a00000 {
+ ahci1: sata@65800000 {
+ compatible = "socionext,uniphier-pro4-ahci",
+ "generic-ahci";
+ status = "disabled";
+ reg = <0x65800000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sys_clk 12>, <&sys_clk 29>;
+ resets = <&sys_rst 12>, <&sys_rst 29>, <&ahci1_rst 3>;
+ ports-implemented = <1>;
+ phys = <&ahci1_phy>;
+ assigned-clocks = <&sg_clk 0>;
+ assigned-clock-rates = <25000000>;
+ };
+
+ sata-controller@65900000 {
+ compatible = "socionext,uniphier-pro4-ahci-glue",
+ "simple-mfd";
+ reg = <0x65900000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65900000 0x100>;
+
+ ahci1_rst: reset-controller@0 {
+ compatible = "socionext,uniphier-pro4-ahci-reset";
+ reg = <0x0 0x4>;
+ clock-names = "gio", "link";
+ clocks = <&sys_clk 12>, <&sys_clk 29>;
+ reset-names = "gio", "link";
+ resets = <&sys_rst 12>, <&sys_rst 29>;
+ #reset-cells = <1>;
+ };
+
+ ahci1_phy: phy@10 {
+ compatible = "socionext,uniphier-pro4-ahci-phy";
+ reg = <0x10 0x40>;
+ clock-names = "link", "gio";
+ clocks = <&sys_clk 29>, <&sys_clk 12>;
+ reset-names = "link", "gio", "phy",
+ "pm", "tx", "rx";
+ resets = <&sys_rst 29>, <&sys_rst 12>,
+ <&sys_rst 30>,
+ <&ahci1_rst 0>, <&ahci1_rst 1>,
+ <&ahci1_rst 2>;
+ #phy-cells = <0>;
+ };
+ };
+
+ usb0: usb@65a00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
reg = <0x65a00000 0xcd00>;
interrupt-names = "host", "peripheral";
- interrupts = <0 134 4>, <0 135 4>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clock-names = "ref", "bus_early", "suspend";
@@ -518,9 +630,10 @@
dr_mode = "host";
};
- usb-glue@65b00000 {
+ usb-controller@65b00000 {
compatible = "socionext,uniphier-pro4-dwc3-glue",
"simple-mfd";
+ reg = <0x65b00000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x100>;
@@ -534,7 +647,7 @@
resets = <&sys_rst 12>, <&sys_rst 14>;
};
- usb0_ssphy: ss-phy@10 {
+ usb0_ssphy: phy@10 {
compatible = "socionext,uniphier-pro4-usb3-ssphy";
reg = <0x10 0x10>;
#phy-cells = <0>;
@@ -545,7 +658,7 @@
vbus-supply = <&usb0_vbus>;
};
- usb0_rst: reset@40 {
+ usb0_rst: reset-controller@40 {
compatible = "socionext,uniphier-pro4-usb3-reset";
reg = <0x40 0x4>;
#reset-cells = <1>;
@@ -556,31 +669,13 @@
};
};
- /* FIXME: U-Boot own node */
- usb0: usb@65b00000 {
- compatible = "socionext,uniphier-pro4-dwc3";
- status = "disabled";
- reg = <0x65b00000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- dwc3@65a00000 {
- compatible = "snps,dwc3";
- reg = <0x65a00000 0x10000>;
- interrupts = <0 134 4>;
- dr_mode = "host";
- tx-fifo-resize;
- };
- };
-
- _usb1: usb@65c00000 {
+ usb1: usb@65c00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
reg = <0x65c00000 0xcd00>;
interrupt-names = "host", "peripheral";
- interrupts = <0 137 4>, <0 138 4>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clock-names = "ref", "bus_early", "suspend";
@@ -590,9 +685,10 @@
dr_mode = "host";
};
- usb-glue@65d00000 {
+ usb-controller@65d00000 {
compatible = "socionext,uniphier-pro4-dwc3-glue",
"simple-mfd";
+ reg = <0x65d00000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65d00000 0x100>;
@@ -606,7 +702,7 @@
resets = <&sys_rst 12>, <&sys_rst 15>;
};
- usb1_rst: reset@40 {
+ usb1_rst: reset-controller@40 {
compatible = "socionext,uniphier-pro4-usb3-reset";
reg = <0x40 0x4>;
#reset-cells = <1>;
@@ -617,31 +713,14 @@
};
};
- /* FIXME: U-Boot own node */
- usb1: usb@65d00000 {
- compatible = "socionext,uniphier-pro4-dwc3";
- status = "disabled";
- reg = <0x65d00000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- dwc3@65c00000 {
- compatible = "snps,dwc3";
- reg = <0x65c00000 0x10000>;
- interrupts = <0 137 4>;
- dr_mode = "host";
- tx-fifo-resize;
- };
- };
-
nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5a";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
- interrupts = <0 65 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi
index 19848e3..c039378 100644
--- a/arch/arm/dts/uniphier-pro5.dtsi
+++ b/arch/arm/dts/uniphier-pro5.dtsi
@@ -5,6 +5,8 @@
// Copyright (C) 2015-2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
/ {
compatible = "socionext,uniphier-pro5";
#address-cells = <1>;
@@ -135,7 +137,8 @@
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
- interrupts = <0 190 4>, <0 191 4>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-size = <(2 * 1024 * 1024)>;
cache-sets = <512>;
@@ -148,7 +151,8 @@
compatible = "socionext,uniphier-system-cache";
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
<0x506c8000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-size = <(2 * 1024 * 1024)>;
cache-sets = <512>;
@@ -162,7 +166,7 @@
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 39 4>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
@@ -175,7 +179,7 @@
reg = <0x54006100 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 216 4>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 11>; /* common with spi0 */
@@ -186,7 +190,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
@@ -197,7 +201,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
@@ -208,7 +212,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
@@ -219,7 +223,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
- interrupts = <0 177 4>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
@@ -246,7 +250,7 @@
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 41 4>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
@@ -260,7 +264,7 @@
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 42 4>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
@@ -274,7 +278,7 @@
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 43 4>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
@@ -288,7 +292,7 @@
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 44 4>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
@@ -304,7 +308,7 @@
reg = <0x58785000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 25 4>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 9>;
resets = <&peri_rst 9>;
clock-frequency = <400000>;
@@ -316,7 +320,7 @@
reg = <0x58786000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 26 4>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 10>;
resets = <&peri_rst 10>;
clock-frequency = <400000>;
@@ -337,39 +341,39 @@
reg = <0x59801000 0x400>;
};
- sdctrl@59810000 {
+ sdctrl: syscon@59810000 {
compatible = "socionext,uniphier-pro5-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
- sd_clk: clock {
+ sd_clk: clock-controller {
compatible = "socionext,uniphier-pro5-sd-clock";
#clock-cells = <1>;
};
- sd_rst: reset {
+ sd_rst: reset-controller {
compatible = "socionext,uniphier-pro5-sd-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-pro5-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-pro5-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-pro5-peri-reset";
#reset-cells = <1>;
};
};
- soc-glue@5f800000 {
+ syscon@5f800000 {
compatible = "socionext,uniphier-pro5-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -379,9 +383,10 @@
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-pro5-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
@@ -415,7 +420,7 @@
xdmac: dma-controller@5fc10000 {
compatible = "socionext,uniphier-xdmac";
reg = <0x5fc10000 0x5300>;
- interrupts = <0 188 4>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <2>;
};
@@ -430,14 +435,16 @@
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
- interrupts = <1 11 0x304>;
+ interrupts = <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
- interrupts = <1 13 0x304>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
@@ -449,17 +456,17 @@
interrupt-controller;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-pro5-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-pro5-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-pro5-reset";
#reset-cells = <1>;
};
@@ -470,7 +477,7 @@
status = "disabled";
reg = <0x65a00000 0xcd00>;
interrupt-names = "host";
- interrupts = <0 134 4>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clock-names = "ref", "bus_early", "suspend";
@@ -480,14 +487,15 @@
dr_mode = "host";
};
- usb-glue@65b00000 {
+ usb-controller@65b00000 {
compatible = "socionext,uniphier-pro5-dwc3-glue",
"simple-mfd";
+ reg = <0x65b00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
- usb0_rst: reset@0 {
+ usb0_rst: reset-controller@0 {
compatible = "socionext,uniphier-pro5-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -506,7 +514,7 @@
resets = <&sys_rst 12>, <&sys_rst 14>;
};
- usb0_hsphy0: hs-phy@280 {
+ usb0_hsphy0: phy@280 {
compatible = "socionext,uniphier-pro5-usb3-hsphy";
reg = <0x280 0x10>;
#phy-cells = <0>;
@@ -517,7 +525,7 @@
vbus-supply = <&usb0_vbus0>;
};
- usb0_ssphy0: ss-phy@380 {
+ usb0_ssphy0: phy@380 {
compatible = "socionext,uniphier-pro5-usb3-ssphy";
reg = <0x380 0x10>;
#phy-cells = <0>;
@@ -534,7 +542,7 @@
status = "disabled";
reg = <0x65c00000 0xcd00>;
interrupt-names = "host";
- interrupts = <0 137 4>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
clock-names = "ref", "bus_early", "suspend";
@@ -544,14 +552,15 @@
dr_mode = "host";
};
- usb-glue@65d00000 {
+ usb-controller@65d00000 {
compatible = "socionext,uniphier-pro5-dwc3-glue",
"simple-mfd";
+ reg = <0x65d00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65d00000 0x400>;
- usb1_rst: reset@0 {
+ usb1_rst: reset-controller@0 {
compatible = "socionext,uniphier-pro5-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -579,7 +588,7 @@
resets = <&sys_rst 12>, <&sys_rst 15>;
};
- usb1_hsphy0: hs-phy@280 {
+ usb1_hsphy0: phy@280 {
compatible = "socionext,uniphier-pro5-usb3-hsphy";
reg = <0x280 0x10>;
#phy-cells = <0>;
@@ -590,7 +599,7 @@
vbus-supply = <&usb1_vbus0>;
};
- usb1_hsphy1: hs-phy@290 {
+ usb1_hsphy1: phy@290 {
compatible = "socionext,uniphier-pro5-usb3-hsphy";
reg = <0x290 0x10>;
#phy-cells = <0>;
@@ -601,7 +610,7 @@
vbus-supply = <&usb1_vbus1>;
};
- usb1_ssphy0: ss-phy@380 {
+ usb1_ssphy0: phy@380 {
compatible = "socionext,uniphier-pro5-usb3-ssphy";
reg = <0x380 0x10>;
#phy-cells = <0>;
@@ -614,8 +623,7 @@
};
pcie_ep: pcie-ep@66000000 {
- compatible = "socionext,uniphier-pro5-pcie-ep",
- "snps,dw-pcie-ep";
+ compatible = "socionext,uniphier-pro5-pcie-ep";
status = "disabled";
reg-names = "dbi", "dbi2", "link", "addr_space";
reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
@@ -648,7 +656,9 @@
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
- interrupts = <0 65 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand2cs>;
clock-names = "nand", "nand_x", "ecc";
@@ -661,7 +671,7 @@
compatible = "socionext,uniphier-sd-v3.1";
status = "disabled";
reg = <0x68400000 0x800>;
- interrupts = <0 78 4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&sd_clk 1>;
@@ -677,7 +687,7 @@
compatible = "socionext,uniphier-sd-v3.1";
status = "disabled";
reg = <0x68800000 0x800>;
- interrupts = <0 76 4>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "uhs";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_uhs>;
@@ -689,6 +699,7 @@
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&sdctrl 0>;
};
};
};
diff --git a/arch/arm/dts/uniphier-pxs2-gentil.dts b/arch/arm/dts/uniphier-pxs2-gentil.dts
index 759384b..5f18b92 100644
--- a/arch/arm/dts/uniphier-pxs2-gentil.dts
+++ b/arch/arm/dts/uniphier-pxs2-gentil.dts
@@ -99,3 +99,7 @@
&usb1 {
status = "okay";
};
+
+&ahci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi
index 7a8b6c1..e3a4b6a 100644
--- a/arch/arm/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/dts/uniphier-pxs2.dtsi
@@ -6,6 +6,7 @@
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -161,7 +162,10 @@
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-size = <(1280 * 1024)>;
cache-sets = <512>;
@@ -175,7 +179,7 @@
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 39 4>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
@@ -188,7 +192,7 @@
reg = <0x54006100 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 216 4>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 12>;
@@ -199,7 +203,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
@@ -210,7 +214,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
@@ -221,7 +225,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
@@ -232,7 +236,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
- interrupts = <0 177 4>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
@@ -259,7 +263,7 @@
audio@56000000 {
compatible = "socionext,uniphier-pxs2-aio";
reg = <0x56000000 0x80000>;
- interrupts = <0 144 4>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ain1>,
<&pinctrl_ain2>,
@@ -317,7 +321,7 @@
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 41 4>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
@@ -331,7 +335,7 @@
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 42 4>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
@@ -345,7 +349,7 @@
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 43 4>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
@@ -359,7 +363,7 @@
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 44 4>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
@@ -373,7 +377,7 @@
reg = <0x58784000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 45 4>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 8>;
resets = <&peri_rst 8>;
clock-frequency = <400000>;
@@ -385,7 +389,7 @@
reg = <0x58785000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 25 4>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 9>;
resets = <&peri_rst 9>;
clock-frequency = <400000>;
@@ -397,7 +401,7 @@
reg = <0x58786000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 26 4>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 10>;
resets = <&peri_rst 10>;
clock-frequency = <400000>;
@@ -418,33 +422,33 @@
reg = <0x59801000 0x400>;
};
- sdctrl@59810000 {
+ sdctrl: syscon@59810000 {
compatible = "socionext,uniphier-pxs2-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
- sd_clk: clock {
+ sd_clk: clock-controller {
compatible = "socionext,uniphier-pxs2-sd-clock";
#clock-cells = <1>;
};
- sd_rst: reset {
+ sd_rst: reset-controller {
compatible = "socionext,uniphier-pxs2-sd-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-pxs2-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-pxs2-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-pxs2-peri-reset";
#reset-cells = <1>;
};
@@ -454,7 +458,7 @@
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a000000 0x800>;
- interrupts = <0 78 4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&sd_clk 1>;
@@ -470,7 +474,7 @@
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a400000 0x800>;
- interrupts = <0 76 4>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "uhs";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_uhs>;
@@ -482,9 +486,10 @@
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&sdctrl 0>;
};
- soc_glue: soc-glue@5f800000 {
+ soc_glue: syscon@5f800000 {
compatible = "socionext,uniphier-pxs2-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -494,9 +499,10 @@
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-pxs2-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
@@ -515,7 +521,7 @@
xdmac: dma-controller@5fc10000 {
compatible = "socionext,uniphier-xdmac";
reg = <0x5fc10000 0x5300>;
- interrupts = <0 188 4>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <2>;
};
@@ -530,14 +536,16 @@
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
- interrupts = <1 11 0xf04>;
+ interrupts = <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
- interrupts = <1 13 0xf04>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
@@ -549,24 +557,24 @@
interrupt-controller;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-pxs2-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-pxs2-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-pxs2-reset";
#reset-cells = <1>;
};
- pvtctl: pvtctl {
+ pvtctl: thermal-sensor {
compatible = "socionext,uniphier-pxs2-thermal";
- interrupts = <0 3 4>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <0>;
socionext,tmod-calibration = <0x0f86 0x6844>;
};
@@ -576,7 +584,7 @@
compatible = "socionext,uniphier-pxs2-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
- interrupts = <0 66 4>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
clock-names = "ether";
@@ -593,12 +601,53 @@
};
};
+ ahci: sata@65600000 {
+ compatible = "socionext,uniphier-pxs2-ahci",
+ "generic-ahci";
+ status = "disabled";
+ reg = <0x65600000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sys_clk 28>;
+ resets = <&sys_rst 28>, <&ahci_rst 0>;
+ ports-implemented = <1>;
+ phys = <&ahci_phy>;
+ };
+
+ sata-controller@65700000 {
+ compatible = "socionext,uniphier-pxs2-ahci-glue",
+ "simple-mfd";
+ reg = <0x65700000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65700000 0x100>;
+
+ ahci_rst: reset-controller@0 {
+ compatible = "socionext,uniphier-pxs2-ahci-reset";
+ reg = <0x0 0x4>;
+ clock-names = "link";
+ clocks = <&sys_clk 28>;
+ reset-names = "link";
+ resets = <&sys_rst 28>;
+ #reset-cells = <1>;
+ };
+
- _usb0: usb@65a00000 {
+ ahci_phy: phy@10 {
+ compatible = "socionext,uniphier-pxs2-ahci-phy";
+ reg = <0x10 0x10>;
+ clock-names = "link";
+ clocks = <&sys_clk 28>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 28>, <&sys_rst 30>;
+ #phy-cells = <0>;
+ };
+ };
+
+ usb0: usb@65a00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
reg = <0x65a00000 0xcd00>;
- interrupt-names = "host", "peripheral";
- interrupts = <0 134 4>, <0 135 4>;
+ interrupt-names = "dwc_usb3";
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
clock-names = "ref", "bus_early", "suspend";
@@ -609,14 +658,15 @@
dr_mode = "host";
};
- usb-glue@65b00000 {
+ usb-controller@65b00000 {
compatible = "socionext,uniphier-pxs2-dwc3-glue",
"simple-mfd";
+ reg = <0x65b00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
- usb0_rst: reset@0 {
+ usb0_rst: reset-controller@0 {
compatible = "socionext,uniphier-pxs2-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -644,7 +694,7 @@
resets = <&sys_rst 14>;
};
- usb0_hsphy0: hs-phy@200 {
+ usb0_hsphy0: phy@200 {
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
@@ -655,7 +705,7 @@
vbus-supply = <&usb0_vbus0>;
};
- usb0_hsphy1: hs-phy@210 {
+ usb0_hsphy1: phy@210 {
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
reg = <0x210 0x10>;
#phy-cells = <0>;
@@ -666,7 +716,7 @@
vbus-supply = <&usb0_vbus1>;
};
- usb0_ssphy0: ss-phy@300 {
+ usb0_ssphy0: phy@300 {
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
@@ -677,7 +727,7 @@
vbus-supply = <&usb0_vbus0>;
};
- usb0_ssphy1: ss-phy@310 {
+ usb0_ssphy1: phy@310 {
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
reg = <0x310 0x10>;
#phy-cells = <0>;
@@ -689,31 +739,12 @@
};
};
- /* FIXME: U-Boot own node */
- usb0: usb@65b00000 {
- compatible = "socionext,uniphier-pxs2-dwc3";
- status = "disabled";
- reg = <0x65b00000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
- dwc3@65a00000 {
- compatible = "snps,dwc3";
- reg = <0x65a00000 0x10000>;
- interrupts = <0 134 4>;
- dr_mode = "host";
- tx-fifo-resize;
- };
- };
-
- _usb1: usb@65c00000 {
+ usb1: usb@65c00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
reg = <0x65c00000 0xcd00>;
- interrupt-names = "host", "peripheral";
- interrupts = <0 137 4>, <0 138 4>;
+ interrupt-names = "dwc_usb3";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
clock-names = "ref", "bus_early", "suspend";
@@ -723,14 +754,15 @@
dr_mode = "host";
};
- usb-glue@65d00000 {
+ usb-controller@65d00000 {
compatible = "socionext,uniphier-pxs2-dwc3-glue",
"simple-mfd";
+ reg = <0x65d00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65d00000 0x400>;
- usb1_rst: reset@0 {
+ usb1_rst: reset-controller@0 {
compatible = "socionext,uniphier-pxs2-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -758,7 +790,7 @@
resets = <&sys_rst 15>;
};
- usb1_hsphy0: hs-phy@200 {
+ usb1_hsphy0: phy@200 {
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
@@ -769,7 +801,7 @@
vbus-supply = <&usb1_vbus0>;
};
- usb1_hsphy1: hs-phy@210 {
+ usb1_hsphy1: phy@210 {
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
reg = <0x210 0x10>;
#phy-cells = <0>;
@@ -780,7 +812,7 @@
vbus-supply = <&usb1_vbus1>;
};
- usb1_ssphy0: ss-phy@300 {
+ usb1_ssphy0: phy@300 {
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
@@ -792,31 +824,14 @@
};
};
- /* FIXME: U-Boot own node */
- usb1: usb@65d00000 {
- compatible = "socionext,uniphier-pxs2-dwc3";
- status = "disabled";
- reg = <0x65d00000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
- dwc3@65c00000 {
- compatible = "snps,dwc3";
- reg = <0x65c00000 0x10000>;
- interrupts = <0 137 4>;
- dr_mode = "host";
- tx-fifo-resize;
- };
- };
-
nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
- interrupts = <0 65 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand2cs>;
clock-names = "nand", "nand_x", "ecc";
diff --git a/arch/arm/dts/uniphier-pxs3-ref.dts b/arch/arm/dts/uniphier-pxs3-ref.dts
index 1a80cd9..1ced619 100644
--- a/arch/arm/dts/uniphier-pxs3-ref.dts
+++ b/arch/arm/dts/uniphier-pxs3-ref.dts
@@ -40,11 +40,11 @@
};
ðsc {
- interrupts = <4 8>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
- interrupts = <4 8>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
};
&spi0 {
@@ -68,7 +68,7 @@
};
&gpio {
- xirq4 {
+ xirq4-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
input;
@@ -131,6 +131,18 @@
&nand {
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ };
+};
+
+&ahci0 {
+ status = "okay";
+};
+
+&ahci1 {
+ status = "okay";
};
&pinctrl_ether_rgmii {
diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi
index 004656c..91d6dde 100644
--- a/arch/arm/dts/uniphier-pxs3.dtsi
+++ b/arch/arm/dts/uniphier-pxs3.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -42,6 +43,7 @@
reg = <0 0x000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
+ next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@@ -52,6 +54,7 @@
reg = <0 0x001>;
clocks = <&sys_clk 33>;
enable-method = "psci";
+ next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@@ -62,6 +65,7 @@
reg = <0 0x002>;
clocks = <&sys_clk 33>;
enable-method = "psci";
+ next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@@ -72,9 +76,14 @@
reg = <0 0x003>;
clocks = <&sys_clk 33>;
enable-method = "psci";
+ next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
+
+ l2: l2-cache {
+ compatible = "cache";
+ };
};
cluster0_opp: opp-table {
@@ -135,10 +144,10 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 4>,
- <1 14 4>,
- <1 11 4>,
- <1 10 4>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
thermal-zones {
@@ -195,7 +204,7 @@
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 39 4>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
@@ -208,7 +217,7 @@
reg = <0x54006100 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 216 4>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 12>;
@@ -219,7 +228,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
@@ -230,7 +239,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
@@ -241,7 +250,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
@@ -252,7 +261,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
- interrupts = <0 177 4>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
@@ -284,7 +293,7 @@
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 41 4>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
@@ -298,7 +307,7 @@
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 42 4>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
@@ -312,7 +321,7 @@
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 43 4>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
@@ -326,7 +335,7 @@
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 44 4>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
@@ -340,7 +349,7 @@
reg = <0x58786000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 26 4>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 10>;
resets = <&peri_rst 10>;
clock-frequency = <400000>;
@@ -361,33 +370,33 @@
reg = <0x59801000 0x400>;
};
- sdctrl@59810000 {
+ sdctrl: syscon@59810000 {
compatible = "socionext,uniphier-pxs3-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
- sd_clk: clock {
+ sd_clk: clock-controller {
compatible = "socionext,uniphier-pxs3-sd-clock";
#clock-cells = <1>;
};
- sd_rst: reset {
+ sd_rst: reset-controller {
compatible = "socionext,uniphier-pxs3-sd-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-pxs3-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-pxs3-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-pxs3-peri-reset";
#reset-cells = <1>;
};
@@ -396,7 +405,7 @@
emmc: mmc@5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
reg = <0x5a000000 0x400>;
- interrupts = <0 78 4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&sys_clk 4>;
@@ -416,7 +425,7 @@
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a400000 0x800>;
- interrupts = <0 76 4>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "uhs";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_uhs>;
@@ -428,9 +437,10 @@
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&sdctrl 0>;
};
- soc_glue: soc-glue@5f800000 {
+ soc_glue: syscon@5f800000 {
compatible = "socionext,uniphier-pxs3-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -440,9 +450,10 @@
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-pxs3-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
@@ -505,7 +516,7 @@
xdmac: dma-controller@5fc10000 {
compatible = "socionext,uniphier-xdmac";
reg = <0x5fc10000 0x5300>;
- interrupts = <0 188 4>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <2>;
};
@@ -523,20 +534,20 @@
<0x5fe80000 0x80000>; /* GICR */
interrupt-controller;
#interrupt-cells = <3>;
- interrupts = <1 9 4>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-pxs3-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-pxs3-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-pxs3-reset";
#reset-cells = <1>;
};
@@ -545,9 +556,9 @@
compatible = "socionext,uniphier-wdt";
};
- pvtctl: pvtctl {
+ pvtctl: thermal-sensor {
compatible = "socionext,uniphier-pxs3-thermal";
- interrupts = <0 3 4>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <0>;
socionext,tmod-calibration = <0x0f22 0x68ee>;
};
@@ -557,7 +568,7 @@
compatible = "socionext,uniphier-pxs3-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
- interrupts = <0 66 4>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
clock-names = "ether";
@@ -578,7 +589,7 @@
compatible = "socionext,uniphier-pxs3-ave4";
status = "disabled";
reg = <0x65200000 0x8500>;
- interrupts = <0 67 4>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether1_rgmii>;
clock-names = "ether";
@@ -595,12 +606,94 @@
};
};
+ ahci0: sata@65600000 {
+ compatible = "socionext,uniphier-pxs3-ahci",
+ "generic-ahci";
+ status = "disabled";
+ reg = <0x65600000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sys_clk 28>;
+ resets = <&sys_rst 28>, <&ahci0_rst 0>;
+ ports-implemented = <1>;
+ phys = <&ahci0_phy>;
+ };
+
+ sata-controller@65700000 {
+ compatible = "socionext,uniphier-pxs3-ahci-glue",
+ "simple-mfd";
+ reg = <0x65700000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65700000 0x100>;
+
+ ahci0_rst: reset-controller@0 {
+ compatible = "socionext,uniphier-pxs3-ahci-reset";
+ reg = <0x0 0x4>;
+ clock-names = "link";
+ clocks = <&sys_clk 28>;
+ reset-names = "link";
+ resets = <&sys_rst 28>;
+ #reset-cells = <1>;
+ };
+
+ ahci0_phy: phy@10 {
+ compatible = "socionext,uniphier-pxs3-ahci-phy";
+ reg = <0x10 0x10>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 28>, <&sys_clk 30>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 28>, <&sys_rst 30>;
+ #phy-cells = <0>;
+ };
+ };
+
+ ahci1: sata@65800000 {
+ compatible = "socionext,uniphier-pxs3-ahci",
+ "generic-ahci";
+ status = "disabled";
+ reg = <0x65800000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sys_clk 29>;
+ resets = <&sys_rst 29>, <&ahci1_rst 0>;
+ ports-implemented = <1>;
+ phys = <&ahci1_phy>;
+ };
+
+ sata-controller@65900000 {
+ compatible = "socionext,uniphier-pxs3-ahci-glue",
+ "simple-mfd";
+ reg = <0x65900000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65900000 0x100>;
+
+ ahci1_rst: reset-controller@0 {
+ compatible = "socionext,uniphier-pxs3-ahci-reset";
+ reg = <0x0 0x4>;
+ clock-names = "link";
+ clocks = <&sys_clk 29>;
+ reset-names = "link";
+ resets = <&sys_rst 29>;
+ #reset-cells = <1>;
+ };
+
+ ahci1_phy: phy@10 {
+ compatible = "socionext,uniphier-pxs3-ahci-phy";
+ reg = <0x10 0x10>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 29>, <&sys_clk 30>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 29>, <&sys_rst 30>;
+ #phy-cells = <0>;
+ };
+ };
+
- _usb0: usb@65a00000 {
+ usb0: usb@65a00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
reg = <0x65a00000 0xcd00>;
- interrupt-names = "host", "peripheral";
- interrupts = <0 134 4>, <0 135 4>;
+ interrupt-names = "dwc_usb3";
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
clock-names = "ref", "bus_early", "suspend";
@@ -611,14 +704,15 @@
dr_mode = "host";
};
- usb-glue@65b00000 {
+ usb-controller@65b00000 {
compatible = "socionext,uniphier-pxs3-dwc3-glue",
"simple-mfd";
+ reg = <0x65b00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
- usb0_rst: reset@0 {
+ usb0_rst: reset-controller@0 {
compatible = "socionext,uniphier-pxs3-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -646,7 +740,7 @@
resets = <&sys_rst 12>;
};
- usb0_hsphy0: hs-phy@200 {
+ usb0_hsphy0: phy@200 {
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
@@ -660,7 +754,7 @@
<&usb_hs_i0>;
};
- usb0_hsphy1: hs-phy@210 {
+ usb0_hsphy1: phy@210 {
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
reg = <0x210 0x10>;
#phy-cells = <0>;
@@ -674,7 +768,7 @@
<&usb_hs_i0>;
};
- usb0_ssphy0: ss-phy@300 {
+ usb0_ssphy0: phy@300 {
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
@@ -685,7 +779,7 @@
vbus-supply = <&usb0_vbus0>;
};
- usb0_ssphy1: ss-phy@310 {
+ usb0_ssphy1: phy@310 {
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
reg = <0x310 0x10>;
#phy-cells = <0>;
@@ -697,31 +791,12 @@
};
};
- /* FIXME: U-Boot own node */
- usb0: usb@65b00000 {
- compatible = "socionext,uniphier-pxs3-dwc3";
- status = "disabled";
- reg = <0x65b00000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
- dwc3@65a00000 {
- compatible = "snps,dwc3";
- reg = <0x65a00000 0x10000>;
- interrupts = <0 134 4>;
- dr_mode = "host";
- tx-fifo-resize;
- };
- };
-
- _usb1: usb@65c00000 {
+ usb1: usb@65c00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
reg = <0x65c00000 0xcd00>;
- interrupt-names = "host", "peripheral";
- interrupts = <0 137 4>, <0 138 4>;
+ interrupt-names = "dwc_usb3";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
clock-names = "ref", "bus_early", "suspend";
@@ -732,14 +807,15 @@
dr_mode = "host";
};
- usb-glue@65d00000 {
+ usb-controller@65d00000 {
compatible = "socionext,uniphier-pxs3-dwc3-glue",
"simple-mfd";
+ reg = <0x65d00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65d00000 0x400>;
- usb1_rst: reset@0 {
+ usb1_rst: reset-controller@0 {
compatible = "socionext,uniphier-pxs3-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -767,7 +843,7 @@
resets = <&sys_rst 13>;
};
- usb1_hsphy0: hs-phy@200 {
+ usb1_hsphy0: phy@200 {
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
@@ -782,7 +858,7 @@
<&usb_hs_i2>;
};
- usb1_hsphy1: hs-phy@210 {
+ usb1_hsphy1: phy@210 {
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
reg = <0x210 0x10>;
#phy-cells = <0>;
@@ -797,7 +873,7 @@
<&usb_hs_i2>;
};
- usb1_ssphy0: ss-phy@300 {
+ usb1_ssphy0: phy@300 {
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
@@ -810,27 +886,8 @@
};
};
- /* FIXME: U-Boot own node */
- usb1: usb@65d00000 {
- compatible = "socionext,uniphier-pxs3-dwc3";
- status = "disabled";
- reg = <0x65d00000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
- dwc3@65c00000 {
- compatible = "snps,dwc3";
- reg = <0x65c00000 0x10000>;
- interrupts = <0 137 4>;
- dr_mode = "host";
- tx-fifo-resize;
- };
- };
-
pcie: pcie@66000000 {
- compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
+ compatible = "socionext,uniphier-pcie";
status = "disabled";
reg-names = "dbi", "link", "config";
reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
@@ -850,7 +907,8 @@
<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
#interrupt-cells = <1>;
interrupt-names = "dma", "msi";
- interrupts = <0 224 4>, <0 225 4>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
<0 0 0 2 &pcie_intc 1>, /* INTB */
@@ -863,7 +921,7 @@
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
- interrupts = <0 226 4>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -883,7 +941,9 @@
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
- interrupts = <0 65 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
diff --git a/arch/arm/dts/uniphier-sld8-ref.dts b/arch/arm/dts/uniphier-sld8-ref.dts
index 22898df..2446f9e 100644
--- a/arch/arm/dts/uniphier-sld8-ref.dts
+++ b/arch/arm/dts/uniphier-sld8-ref.dts
@@ -36,11 +36,11 @@
};
ðsc {
- interrupts = <0 8>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
- interrupts = <0 8>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&serial0 {
@@ -56,7 +56,7 @@
};
&gpio {
- xirq0 {
+ xirq0-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
input;
@@ -85,4 +85,8 @@
&nand {
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ };
};
diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi
index 93ddebb..4708b2d 100644
--- a/arch/arm/dts/uniphier-sld8.dtsi
+++ b/arch/arm/dts/uniphier-sld8.dtsi
@@ -6,6 +6,7 @@
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "socionext,uniphier-sld8";
@@ -55,7 +56,8 @@
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-size = <(256 * 1024)>;
cache-sets = <256>;
@@ -69,7 +71,7 @@
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 39 4>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
@@ -80,7 +82,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
@@ -91,7 +93,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
@@ -102,7 +104,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
@@ -113,7 +115,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
- interrupts = <0 29 4>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
@@ -144,7 +146,7 @@
reg = <0x58400000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 41 1>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
@@ -158,7 +160,7 @@
reg = <0x58480000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 42 1>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
@@ -172,7 +174,7 @@
reg = <0x58500000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 43 1>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
@@ -186,7 +188,7 @@
reg = <0x58580000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 44 1>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
@@ -209,33 +211,33 @@
reg = <0x59801000 0x400>;
};
- mioctrl@59810000 {
+ mioctrl: syscon@59810000 {
compatible = "socionext,uniphier-sld8-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
- mio_clk: clock {
+ mio_clk: clock-controller {
compatible = "socionext,uniphier-sld8-mio-clock";
#clock-cells = <1>;
};
- mio_rst: reset {
+ mio_rst: reset-controller {
compatible = "socionext,uniphier-sld8-mio-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-sld8-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-sld8-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-sld8-peri-reset";
#reset-cells = <1>;
};
@@ -244,8 +246,13 @@
dmac: dma-controller@5a000000 {
compatible = "socionext,uniphier-mio-dmac";
reg = <0x5a000000 0x1000>;
- interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
- <0 71 4>, <0 72 4>, <0 73 4>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mio_clk 7>;
resets = <&mio_rst 7>;
#dma-cells = <1>;
@@ -255,7 +262,7 @@
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a400000 0x200>;
- interrupts = <0 76 4>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "uhs";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_uhs>;
@@ -269,13 +276,14 @@
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&mioctrl 0>;
};
emmc: mmc@5a500000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a500000 0x200>;
- interrupts = <0 78 4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&mio_clk 1>;
@@ -293,7 +301,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
@@ -307,7 +315,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
@@ -321,7 +329,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
- interrupts = <0 82 4>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
@@ -331,7 +339,7 @@
has-transaction-translator;
};
- soc-glue@5f800000 {
+ syscon@5f800000 {
compatible = "socionext,uniphier-sld8-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -341,9 +349,10 @@
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-sld8-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
@@ -362,14 +371,16 @@
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
- interrupts = <1 11 0x104>;
+ interrupts = <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
- interrupts = <1 13 0x104>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
@@ -388,17 +399,17 @@
#interrupt-cells = <2>;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-sld8-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-sld8-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-sld8-reset";
#reset-cells = <1>;
};
@@ -409,7 +420,9 @@
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
- interrupts = <0 65 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand2cs>;
clock-names = "nand", "nand_x", "ecc";
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 1a589c7..7a16015 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -159,6 +159,15 @@
*/
gd->arch.tlb_allocated = gd->arch.tlb_addr;
#endif
+
+ if (IS_ENABLED(CONFIG_CMO_BY_VA_ONLY)) {
+ /*
+ * As invalidate_dcache_all() will be called before
+ * mmu_setup(), we should make sure that the PTs are
+ * already in a valid state.
+ */
+ memset((void *)gd->arch.tlb_addr, 0, gd->arch.tlb_size);
+ }
#endif
return 0;
diff --git a/arch/arm/lib/semihosting.S b/arch/arm/lib/semihosting.S
new file mode 100644
index 0000000..393aade
--- /dev/null
+++ b/arch/arm/lib/semihosting.S
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) 2022 Arm Ltd.
+ */
+
+#include <config.h>
+#include <asm/macro.h>
+#include <linux/linkage.h>
+
+.pushsection .text.smh_trap, "ax"
+/* long smh_trap(unsigned int sysnum, void *addr); */
+ENTRY(smh_trap)
+
+#if defined(CONFIG_ARM64)
+ hlt #0xf000
+#elif defined(CONFIG_CPU_V7M)
+ bkpt #0xab
+#elif defined(CONFIG_SYS_THUMB_BUILD)
+ svc #0xab
+#else
+ svc #0x123456
+#endif
+
+#if defined(CONFIG_ARM64)
+ ret
+#else
+ bx lr
+#endif
+
+ENDPROC(smh_trap)
+.popsection
diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c
deleted file mode 100644
index 7b7669b..0000000
--- a/arch/arm/lib/semihosting.c
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2022 Sean Anderson <sean.anderson@seco.com>
- * Copyright 2014 Broadcom Corporation
- */
-
-#include <common.h>
-
-/*
- * Macro to force the compiler to *populate* memory (for an array or struct)
- * before passing the pointer to an inline assembly call.
- */
-#define USE_PTR(ptr) *(const char (*)[]) (ptr)
-
-#if defined(CONFIG_ARM64)
- #define SMH_TRAP "hlt #0xf000"
-#elif defined(CONFIG_CPU_V7M)
- #define SMH_TRAP "bkpt #0xAB"
-#elif defined(CONFIG_SYS_THUMB_BUILD)
- #define SMH_TRAP "svc #0xab"
-#else
- #define SMH_TRAP "svc #0x123456"
-#endif
-
-/*
- * Call the handler
- */
-long smh_trap(unsigned int sysnum, void *addr)
-{
- register long result asm("r0");
- register void *_addr asm("r1") = addr;
-
- /*
- * We need a memory clobber (aka compiler barrier) for two reasons:
- * - The compiler needs to populate any data structures pointed to
- * by "addr" *before* the trap instruction is called.
- * - At least the SYSREAD function puts the result into memory pointed
- * to by "addr", so the compiler must not use a cached version of
- * the previous content, after the call has finished.
- */
- asm volatile (SMH_TRAP
- : "=r" (result)
- : "0"(sysnum), "r"(USE_PTR(_addr))
- : "memory");
-
- return result;
-}
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig
index 74c4ff3..0684152 100644
--- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig
@@ -23,10 +23,4 @@
endchoice
-source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0"
-source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1"
-source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2"
-source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3"
-source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4"
-
endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0
deleted file mode 100644
index 208eed0..0000000
--- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0
+++ /dev/null
@@ -1,733 +0,0 @@
-menuconfig ELBC_BR0_OR0
- bool "ELBC BR0/OR0"
-
-if ELBC_BR0_OR0
-
-config BR0_OR0_NAME
- string "Identifier"
-
-config BR0_OR0_BASE
- hex "Port base"
-
-choice
- prompt "Port size"
-
-config BR0_PORTSIZE_8BIT
- bool "8-bit"
-
-config BR0_PORTSIZE_16BIT
- depends on !BR0_MACHINE_FCM
- bool "16-bit"
-
-
-config BR0_PORTSIZE_32BIT
- depends on !BR0_MACHINE_FCM
- depends on ARCH_MPC8360 || ARCH_MPC8379
- bool "32-bit"
-
-endchoice
-
-if BR0_MACHINE_FCM
-
-choice
- prompt "Data Error Checking"
-
-config BR0_ERRORCHECKING_DISABLED
- bool "Disabled"
-
-config BR0_ERRORCHECKING_ECC_CHECKING
- bool "ECC checking / No ECC generation"
-
-config BR0_ERRORCHECKING_BOTH
- bool "ECC checking and generation"
-
-endchoice
-
-endif
-
-config BR0_WRITE_PROTECT
- bool "Write-protect"
-
-config BR0_MACHINE_UPM
- bool
-
-choice
- prompt "Machine select"
-
-config BR0_MACHINE_GPCM
- bool "GPCM"
-
-config BR0_MACHINE_FCM
- depends on !ARCH_MPC832X && !ARCH_MPC8360
- bool "FCM"
-
-config BR0_MACHINE_SDRAM
- depends on ARCH_MPC8360
- bool "SDRAM"
-
-config BR0_MACHINE_UPMA
- select BR0_MACHINE_UPM
- bool "UPM (A)"
-
-config BR0_MACHINE_UPMB
- select BR0_MACHINE_UPM
- bool "UPM (B)"
-
-config BR0_MACHINE_UPMC
- select BR0_MACHINE_UPM
- bool "UPM (C)"
-
-endchoice
-
-if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
-
-choice
- prompt "Atomic operations"
-
-config BR0_ATOMIC_NONE
- bool "No atomic operations"
-
-config BR0_ATOMIC_RAWA
- bool "Read-after-write-atomic"
-
-config BR0_ATOMIC_WARA
- bool "Write-after-read-atomic"
-
-endchoice
-
-endif
-
-if BR0_MACHINE_GPCM || BR0_MACHINE_FCM || BR0_MACHINE_UPM || BR0_MACHINE_SDRAM
-
-choice
- prompt "Address mask"
-
-config OR0_AM_32_KBYTES
- depends on !BR0_MACHINE_SDRAM
- bool "32 kb"
-
-config OR0_AM_64_KBYTES
- bool "64 kb"
-
-config OR0_AM_128_KBYTES
- bool "128 kb"
-
-config OR0_AM_256_KBYTES
- bool "256 kb"
-
-config OR0_AM_512_KBYTES
- bool "512 kb"
-
-config OR0_AM_1_MBYTES
- bool "1 mb"
-
-config OR0_AM_2_MBYTES
- bool "2 mb"
-
-config OR0_AM_4_MBYTES
- bool "4 mb"
-
-config OR0_AM_8_MBYTES
- bool "8 mb"
-
-config OR0_AM_16_MBYTES
- bool "16 mb"
-
-config OR0_AM_32_MBYTES
- bool "32 mb"
-
-config OR0_AM_64_MBYTES
- bool "64 mb"
-
-# XXX: Some boards define 128MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR0_AM_128_MBYTES
- bool "128 mb"
-
-# XXX: Some boards define 256MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR0_AM_256_MBYTES
- bool "256 mb"
-
-config OR0_AM_512_MBYTES
- depends on BR0_MACHINE_FCM
- bool "512 mb"
-
-# XXX: Some boards define 1GB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR0_AM_1_GBYTES
- bool "1 gb"
-
-config OR0_AM_2_GBYTES
- depends on BR0_MACHINE_FCM
- bool "2 gb"
-
-config OR0_AM_4_GBYTES
- depends on BR0_MACHINE_FCM
- bool "4 gb"
-
-endchoice
-
-config OR0_XAM_SET
- bool "Set unused bytes after address mask"
-choice
- prompt "Buffer control disable"
-
-config OR0_BCTLD_ASSERTED
- bool "Asserted"
-
-config OR0_BCTLD_NOT_ASSERTED
- bool "Not asserted"
-
-endchoice
-
-endif
-
-if BR0_MACHINE_GPCM || BR0_MACHINE_FCM
-
-choice
- prompt "Cycle length in bus clocks"
-
-config OR0_SCY_0
- bool "No wait states"
-
-config OR0_SCY_1
- bool "1 wait state"
-
-config OR0_SCY_2
- bool "2 wait states"
-
-config OR0_SCY_3
- bool "3 wait states"
-
-config OR0_SCY_4
- bool "4 wait states"
-
-config OR0_SCY_5
- bool "5 wait states"
-
-config OR0_SCY_6
- bool "6 wait states"
-
-config OR0_SCY_7
- bool "7 wait states"
-
-config OR0_SCY_8
- depends on BR0_MACHINE_GPCM
- bool "8 wait states"
-
-config OR0_SCY_9
- depends on BR0_MACHINE_GPCM
- bool "9 wait states"
-
-config OR0_SCY_10
- depends on BR0_MACHINE_GPCM
- bool "10 wait states"
-
-config OR0_SCY_11
- depends on BR0_MACHINE_GPCM
- bool "11 wait states"
-
-config OR0_SCY_12
- depends on BR0_MACHINE_GPCM
- bool "12 wait states"
-
-config OR0_SCY_13
- depends on BR0_MACHINE_GPCM
- bool "13 wait states"
-
-config OR0_SCY_14
- depends on BR0_MACHINE_GPCM
- bool "14 wait states"
-
-config OR0_SCY_15
- depends on BR0_MACHINE_GPCM
- bool "15 wait states"
-
-endchoice
-
-endif # BR0_MACHINE_GPCM || BR0_MACHINE_FCM
-
-if BR0_MACHINE_GPCM
-
-choice
- prompt "Chip select negotiation time"
-
-config OR0_CSNT_NORMAL
- bool "Normal"
-
-config OR0_CSNT_EARLIER
- bool "Earlier"
-
-endchoice
-
-choice
- prompt "Address to chip-select setup"
-
-config OR0_ACS_SAME_TIME
- bool "At the same time"
-
-config OR0_ACS_HALF_CYCLE_EARLIER
- bool "Half of a bus clock cycle earlier"
-
-config OR0_ACS_QUARTER_CYCLE_EARLIER
- bool "Half/Quarter of a bus clock cycle earlier"
-
-endchoice
-
-choice
- prompt "Extra address to check-select setup"
-
-config OR0_XACS_NORMAL
- bool "Normal"
-
-config OR0_XACS_EXTENDED
- bool "Extended"
-
-endchoice
-
-choice
- prompt "External address termination"
-
-config OR0_SETA_INTERNAL
- bool "Access is terminated internally"
-
-config OR0_SETA_EXTERNAL
- bool "Access is terminated externally"
-
-endchoice
-
-endif # BR0_MACHINE_GPCM
-
-if BR0_MACHINE_FCM
-
-choice
- prompt "NAND Flash EEPROM page size"
-
-config OR0_PGS_SMALL
- bool "Small page device"
-
-config OR0_PGS_LARGE
- bool "Large page device"
-
-endchoice
-
-choice
- prompt "Chip select to command time"
-
-config OR0_CSCT_1_CYCLE
- depends on OR0_TRLX_NORMAL
- bool "1 cycle"
-
-config OR0_CSCT_2_CYCLE
- depends on OR0_TRLX_RELAXED
- bool "2 cycles"
-
-config OR0_CSCT_4_CYCLE
- depends on OR0_TRLX_NORMAL
- bool "4 cycles"
-
-config OR0_CSCT_8_CYCLE
- depends on OR0_TRLX_RELAXED
- bool "8 cycles"
-
-endchoice
-
-choice
- prompt "Command setup time"
-
-config OR0_CST_COINCIDENT
- depends on OR0_TRLX_NORMAL
- bool "Coincident with any command"
-
-config OR0_CST_QUARTER_CLOCK
- depends on OR0_TRLX_NORMAL
- bool "0.25 clocks after"
-
-config OR0_CST_HALF_CLOCK
- depends on OR0_TRLX_RELAXED
- bool "0.5 clocks after"
-
-config OR0_CST_ONE_CLOCK
- depends on OR0_TRLX_RELAXED
- bool "1 clock after"
-
-endchoice
-
-choice
- prompt "Command hold time"
-
-config OR0_CHT_HALF_CLOCK
- depends on OR0_TRLX_NORMAL
- bool "0.5 clocks before"
-
-config OR0_CHT_ONE_CLOCK
- depends on OR0_TRLX_NORMAL
- bool "1 clock before"
-
-config OR0_CHT_ONE_HALF_CLOCK
- depends on OR0_TRLX_RELAXED
- bool "1.5 clocks before"
-
-config OR0_CHT_TWO_CLOCK
- depends on OR0_TRLX_RELAXED
- bool "2 clocks before"
-
-endchoice
-
-choice
- prompt "Reset setup time"
-
-config OR0_RST_THREE_QUARTER_CLOCK
- depends on OR0_TRLX_NORMAL
- bool "0.75 clocks prior"
-
-config OR0_RST_ONE_HALF_CLOCK
- depends on OR0_TRLX_RELAXED
- bool "0.5 clocks prior"
-
-config OR0_RST_ONE_CLOCK
- bool "1 clock prior"
-
-endchoice
-
-endif # BR0_MACHINE_FCM
-
-if BR0_MACHINE_UPM
-
-choice
- prompt "Burst inhibit"
-
-config OR0_BI_BURSTSUPPORT
- bool "Support burst access"
-
-config OR0_BI_BURSTINHIBIT
- bool "Inhibit burst access"
-
-endchoice
-
-endif # BR0_MACHINE_UPM
-
-if BR0_MACHINE_SDRAM
-
-choice
- prompt "Number of column address lines"
-
-config OR0_COLS_7
- bool "7"
-
-config OR0_COLS_8
- bool "8"
-
-config OR0_COLS_9
- bool "9"
-
-config OR0_COLS_10
- bool "10"
-
-config OR0_COLS_11
- bool "11"
-
-config OR0_COLS_12
- bool "12"
-
-config OR0_COLS_13
- bool "13"
-
-config OR0_COLS_14
- bool "14"
-
-endchoice
-
-choice
- prompt "Number of rows address lines"
-
-config OR0_ROWS_9
- bool "9"
-
-config OR0_ROWS_10
- bool "10"
-
-config OR0_ROWS_11
- bool "11"
-
-config OR0_ROWS_12
- bool "12"
-
-config OR0_ROWS_13
- bool "13"
-
-config OR0_ROWS_14
- bool "14"
-
-config OR0_ROWS_15
- bool "15"
-
-endchoice
-
-choice
- prompt "Page mode select"
-
-config OR0_PMSEL_BTB
- bool "Back-to-back"
-
-config OR0_PMSEL_KEPT_OPEN
- bool "Page kept open until page miss or refresh"
-
-endchoice
-
-endif # BR0_MACHINE_SDRAM
-
-choice
- prompt "Relaxed timing"
-
-config OR0_TRLX_NORMAL
- bool "Normal"
-
-config OR0_TRLX_RELAXED
- bool "Relaxed"
-
-endchoice
-
-choice
- prompt "Extended hold time"
-
-config OR0_EHTR_NORMAL
- depends on OR0_TRLX_NORMAL
- bool "Normal"
-
-config OR0_EHTR_1_CYCLE
- depends on OR0_TRLX_NORMAL
- bool "1 idle clock cycle inserted"
-
-config OR0_EHTR_4_CYCLE
- depends on OR0_TRLX_RELAXED
- bool "4 idle clock cycles inserted"
-
-config OR0_EHTR_8_CYCLE
- depends on OR0_TRLX_RELAXED
- bool "8 idle clock cycles inserted"
-
-endchoice
-
-if !ARCH_MPC8308
-
-choice
- prompt "External address latch delay"
-
-config OR0_EAD_NONE
- bool "None"
-
-config OR0_EAD_EXTRA
- bool "Extra"
-
-endchoice
-
-endif # !ARCH_MPC8308
-
-endif # ELBC_BR0_OR0
-
-config BR0_PORTSIZE
- hex
- default 0x800 if BR0_PORTSIZE_8BIT
- default 0x1000 if BR0_PORTSIZE_16BIT
- default 0x1800 if BR0_PORTSIZE_32BIT
-
-config BR0_ERRORCHECKING
- hex
- default 0x0 if !BR0_MACHINE_FCM
- default 0x0 if BR0_ERRORCHECKING_DISABLED
- default 0x200 if BR0_ERRORCHECKING_ECC_CHECKING
- default 0x400 if BR0_ERRORCHECKING_BOTH
-
-config BR0_WRITE_PROTECT_BIT
- hex
- default 0x0 if !BR0_WRITE_PROTECT
- default 0x100 if BR0_WRITE_PROTECT
-
-config BR0_MACHINE
- hex
- default 0x0 if BR0_MACHINE_GPCM
- default 0x20 if BR0_MACHINE_FCM
- default 0x60 if BR0_MACHINE_SDRAM
- default 0x80 if BR0_MACHINE_UPMA
- default 0xa0 if BR0_MACHINE_UPMB
- default 0xc0 if BR0_MACHINE_UPMC
-
-config BR0_ATOMIC
- hex
- default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
- default 0x0 if BR0_ATOMIC_NONE
- default 0x4 if BR0_ATOMIC_RAWA
- default 0x8 if BR0_ATOMIC_WARA
-
-config BR0_VALID_BIT
- hex
- default 0x0 if !ELBC_BR0_OR0
- default 0x1 if ELBC_BR0_OR0
-
-config OR0_AM
- hex
- default 0xffff8000 if OR0_AM_32_KBYTES && !BR0_MACHINE_SDRAM
- default 0xffff0000 if OR0_AM_64_KBYTES
- default 0xfffe0000 if OR0_AM_128_KBYTES
- default 0xfffc0000 if OR0_AM_256_KBYTES
- default 0xfff80000 if OR0_AM_512_KBYTES
- default 0xfff00000 if OR0_AM_1_MBYTES
- default 0xffe00000 if OR0_AM_2_MBYTES
- default 0xffc00000 if OR0_AM_4_MBYTES
- default 0xff800000 if OR0_AM_8_MBYTES
- default 0xff000000 if OR0_AM_16_MBYTES
- default 0xfe000000 if OR0_AM_32_MBYTES
- default 0xfc000000 if OR0_AM_64_MBYTES
- default 0xf8000000 if OR0_AM_128_MBYTES
- default 0xf0000000 if OR0_AM_256_MBYTES
- default 0xe0000000 if OR0_AM_512_MBYTES
- default 0xc0000000 if OR0_AM_1_GBYTES
- default 0x80000000 if OR0_AM_2_GBYTES
- default 0x00000000 if OR0_AM_4_GBYTES
-
-config OR0_XAM
- hex
- default 0x0 if !OR0_XAM_SET
- default 0x6000 if OR0_XAM_SET
-
-config OR0_BCTLD
- hex
- default 0x0 if OR0_BCTLD_ASSERTED
- default 0x1000 if OR0_BCTLD_NOT_ASSERTED
-
-config OR0_BI
- hex
- default 0x0 if !BR0_MACHINE_UPM
- default 0x0 if OR0_BI_BURSTSUPPORT
- default 0x100 if OR0_BI_BURSTINHIBIT
-
-config OR0_COLS
- hex
- default 0x0 if !BR0_MACHINE_SDRAM
- default 0x0 if OR0_COLS_7
- default 0x400 if OR0_COLS_8
- default 0x800 if OR0_COLS_9
- default 0xc00 if OR0_COLS_10
- default 0x1000 if OR0_COLS_11
- default 0x1400 if OR0_COLS_12
- default 0x1800 if OR0_COLS_13
- default 0x1c00 if OR0_COLS_14
-
-config OR0_ROWS
- hex
- default 0x0 if !BR0_MACHINE_SDRAM
- default 0x0 if OR0_ROWS_9
- default 0x40 if OR0_ROWS_10
- default 0x80 if OR0_ROWS_11
- default 0xc0 if OR0_ROWS_12
- default 0x100 if OR0_ROWS_13
- default 0x140 if OR0_ROWS_14
- default 0x180 if OR0_ROWS_15
-
-config OR0_PMSEL
- hex
- default 0x0 if !BR0_MACHINE_SDRAM
- default 0x0 if OR0_PMSEL_BTB
- default 0x20 if OR0_PMSEL_KEPT_OPEN
-
-config OR0_SCY
- hex
- default 0x0 if !BR0_MACHINE_GPCM && !BR0_MACHINE_FCM
- default 0x0 if OR0_SCY_0
- default 0x10 if OR0_SCY_1
- default 0x20 if OR0_SCY_2
- default 0x30 if OR0_SCY_3
- default 0x40 if OR0_SCY_4
- default 0x50 if OR0_SCY_5
- default 0x60 if OR0_SCY_6
- default 0x70 if OR0_SCY_7
- default 0x80 if OR0_SCY_8
- default 0x90 if OR0_SCY_9
- default 0xa0 if OR0_SCY_10
- default 0xb0 if OR0_SCY_11
- default 0xc0 if OR0_SCY_12
- default 0xd0 if OR0_SCY_13
- default 0xe0 if OR0_SCY_14
- default 0xf0 if OR0_SCY_15
-
-config OR0_PGS
- hex
- default 0x0 if !BR0_MACHINE_FCM
- default 0x0 if OR0_PGS_SMALL
- default 0x400 if OR0_PGS_LARGE
-
-config OR0_CSCT
- hex
- default 0x0 if !BR0_MACHINE_FCM
- default 0x0 if OR0_CSCT_1_CYCLE
- default 0x0 if OR0_CSCT_2_CYCLE
- default 0x200 if OR0_CSCT_4_CYCLE
- default 0x200 if OR0_CSCT_8_CYCLE
-
-config OR0_CST
- hex
- default 0x0 if !BR0_MACHINE_FCM
- default 0x0 if OR0_CST_COINCIDENT
- default 0x100 if OR0_CST_QUARTER_CLOCK
- default 0x0 if OR0_CST_HALF_CLOCK
- default 0x100 if OR0_CST_ONE_CLOCK
-
-config OR0_CHT
- hex
- default 0x0 if !BR0_MACHINE_FCM
- default 0x0 if OR0_CHT_HALF_CLOCK
- default 0x80 if OR0_CHT_ONE_CLOCK
- default 0x0 if OR0_CHT_ONE_HALF_CLOCK
- default 0x80 if OR0_CHT_TWO_CLOCK
-
-config OR0_RST
- hex
- default 0x0 if !BR0_MACHINE_FCM
- default 0x0 if OR0_RST_THREE_QUARTER_CLOCK
- default 0x8 if OR0_RST_ONE_CLOCK
- default 0x0 if OR0_RST_ONE_HALF_CLOCK
-
-config OR0_CSNT
- hex
- default 0x0 if !BR0_MACHINE_GPCM
- default 0x0 if OR0_CSNT_NORMAL
- default 0x800 if OR0_CSNT_EARLIER
-
-config OR0_ACS
- hex
- default 0x0 if !BR0_MACHINE_GPCM
- default 0x0 if OR0_ACS_SAME_TIME
- default 0x400 if OR0_ACS_QUARTER_CYCLE_EARLIER
- default 0x600 if OR0_ACS_HALF_CYCLE_EARLIER
-
-config OR0_XACS
- hex
- default 0x0 if !BR0_MACHINE_GPCM
- default 0x0 if OR0_XACS_NORMAL
- default 0x100 if OR0_XACS_EXTENDED
-
-config OR0_SETA
- hex
- default 0x0 if !BR0_MACHINE_GPCM
- default 0x0 if OR0_SETA_INTERNAL
- default 0x8 if OR0_SETA_EXTERNAL
-
-config OR0_TRLX
- hex
- default 0x0 if OR0_TRLX_NORMAL
- default 0x4 if OR0_TRLX_RELAXED
-
-config OR0_EHTR
- hex
- default 0x0 if OR0_EHTR_NORMAL
- default 0x2 if OR0_EHTR_1_CYCLE
- default 0x0 if OR0_EHTR_4_CYCLE
- default 0x2 if OR0_EHTR_8_CYCLE
-
-config OR0_EAD
- hex
- default 0x0 if ARCH_MPC8308
- default 0x0 if OR0_EAD_NONE
- default 0x1 if OR0_EAD_EXTRA
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1
deleted file mode 100644
index 1dc3e75..0000000
--- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1
+++ /dev/null
@@ -1,733 +0,0 @@
-menuconfig ELBC_BR1_OR1
- bool "ELBC BR1/OR1"
-
-if ELBC_BR1_OR1
-
-config BR1_OR1_NAME
- string "Identifier"
-
-config BR1_OR1_BASE
- hex "Port base"
-
-choice
- prompt "Port size"
-
-config BR1_PORTSIZE_8BIT
- bool "8-bit"
-
-config BR1_PORTSIZE_16BIT
- depends on !BR1_MACHINE_FCM
- bool "16-bit"
-
-
-config BR1_PORTSIZE_32BIT
- depends on !BR1_MACHINE_FCM
- depends on ARCH_MPC8360 || ARCH_MPC8379
- bool "32-bit"
-
-endchoice
-
-if BR1_MACHINE_FCM
-
-choice
- prompt "Data Error Checking"
-
-config BR1_ERRORCHECKING_DISABLED
- bool "Disabled"
-
-config BR1_ERRORCHECKING_ECC_CHECKING
- bool "ECC checking / No ECC generation"
-
-config BR1_ERRORCHECKING_BOTH
- bool "ECC checking and generation"
-
-endchoice
-
-endif
-
-config BR1_WRITE_PROTECT
- bool "Write-protect"
-
-config BR1_MACHINE_UPM
- bool
-
-choice
- prompt "Machine select"
-
-config BR1_MACHINE_GPCM
- bool "GPCM"
-
-config BR1_MACHINE_FCM
- depends on !ARCH_MPC832X && !ARCH_MPC8360
- bool "FCM"
-
-config BR1_MACHINE_SDRAM
- depends on ARCH_MPC8360
- bool "SDRAM"
-
-config BR1_MACHINE_UPMA
- select BR1_MACHINE_UPM
- bool "UPM (A)"
-
-config BR1_MACHINE_UPMB
- select BR1_MACHINE_UPM
- bool "UPM (B)"
-
-config BR1_MACHINE_UPMC
- select BR1_MACHINE_UPM
- bool "UPM (C)"
-
-endchoice
-
-if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
-
-choice
- prompt "Atomic operations"
-
-config BR1_ATOMIC_NONE
- bool "No atomic operations"
-
-config BR1_ATOMIC_RAWA
- bool "Read-after-write-atomic"
-
-config BR1_ATOMIC_WARA
- bool "Write-after-read-atomic"
-
-endchoice
-
-endif
-
-if BR1_MACHINE_GPCM || BR1_MACHINE_FCM || BR1_MACHINE_UPM || BR1_MACHINE_SDRAM
-
-choice
- prompt "Address mask"
-
-config OR1_AM_32_KBYTES
- depends on !BR1_MACHINE_SDRAM
- bool "32 kb"
-
-config OR1_AM_64_KBYTES
- bool "64 kb"
-
-config OR1_AM_128_KBYTES
- bool "128 kb"
-
-config OR1_AM_256_KBYTES
- bool "256 kb"
-
-config OR1_AM_512_KBYTES
- bool "512 kb"
-
-config OR1_AM_1_MBYTES
- bool "1 mb"
-
-config OR1_AM_2_MBYTES
- bool "2 mb"
-
-config OR1_AM_4_MBYTES
- bool "4 mb"
-
-config OR1_AM_8_MBYTES
- bool "8 mb"
-
-config OR1_AM_16_MBYTES
- bool "16 mb"
-
-config OR1_AM_32_MBYTES
- bool "32 mb"
-
-config OR1_AM_64_MBYTES
- bool "64 mb"
-
-# XXX: Some boards define 128MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR1_AM_128_MBYTES
- bool "128 mb"
-
-# XXX: Some boards define 256MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR1_AM_256_MBYTES
- bool "256 mb"
-
-config OR1_AM_512_MBYTES
- depends on BR1_MACHINE_FCM
- bool "512 mb"
-
-# XXX: Some boards define 1GB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR1_AM_1_GBYTES
- bool "1 gb"
-
-config OR1_AM_2_GBYTES
- depends on BR1_MACHINE_FCM
- bool "2 gb"
-
-config OR1_AM_4_GBYTES
- depends on BR1_MACHINE_FCM
- bool "4 gb"
-
-endchoice
-
-config OR1_XAM_SET
- bool "Set unused bytes after address mask"
-choice
- prompt "Buffer control disable"
-
-config OR1_BCTLD_ASSERTED
- bool "Asserted"
-
-config OR1_BCTLD_NOT_ASSERTED
- bool "Not asserted"
-
-endchoice
-
-endif
-
-if BR1_MACHINE_GPCM || BR1_MACHINE_FCM
-
-choice
- prompt "Cycle length in bus clocks"
-
-config OR1_SCY_0
- bool "No wait states"
-
-config OR1_SCY_1
- bool "1 wait state"
-
-config OR1_SCY_2
- bool "2 wait states"
-
-config OR1_SCY_3
- bool "3 wait states"
-
-config OR1_SCY_4
- bool "4 wait states"
-
-config OR1_SCY_5
- bool "5 wait states"
-
-config OR1_SCY_6
- bool "6 wait states"
-
-config OR1_SCY_7
- bool "7 wait states"
-
-config OR1_SCY_8
- depends on BR1_MACHINE_GPCM
- bool "8 wait states"
-
-config OR1_SCY_9
- depends on BR1_MACHINE_GPCM
- bool "9 wait states"
-
-config OR1_SCY_10
- depends on BR1_MACHINE_GPCM
- bool "10 wait states"
-
-config OR1_SCY_11
- depends on BR1_MACHINE_GPCM
- bool "11 wait states"
-
-config OR1_SCY_12
- depends on BR1_MACHINE_GPCM
- bool "12 wait states"
-
-config OR1_SCY_13
- depends on BR1_MACHINE_GPCM
- bool "13 wait states"
-
-config OR1_SCY_14
- depends on BR1_MACHINE_GPCM
- bool "14 wait states"
-
-config OR1_SCY_15
- depends on BR1_MACHINE_GPCM
- bool "15 wait states"
-
-endchoice
-
-endif # BR1_MACHINE_GPCM || BR1_MACHINE_FCM
-
-if BR1_MACHINE_GPCM
-
-choice
- prompt "Chip select negotiation time"
-
-config OR1_CSNT_NORMAL
- bool "Normal"
-
-config OR1_CSNT_EARLIER
- bool "Earlier"
-
-endchoice
-
-choice
- prompt "Address to chip-select setup"
-
-config OR1_ACS_SAME_TIME
- bool "At the same time"
-
-config OR1_ACS_HALF_CYCLE_EARLIER
- bool "Half of a bus clock cycle earlier"
-
-config OR1_ACS_QUARTER_CYCLE_EARLIER
- bool "Half/Quarter of a bus clock cycle earlier"
-
-endchoice
-
-choice
- prompt "Extra address to check-select setup"
-
-config OR1_XACS_NORMAL
- bool "Normal"
-
-config OR1_XACS_EXTENDED
- bool "Extended"
-
-endchoice
-
-choice
- prompt "External address termination"
-
-config OR1_SETA_INTERNAL
- bool "Access is terminated internally"
-
-config OR1_SETA_EXTERNAL
- bool "Access is terminated externally"
-
-endchoice
-
-endif # BR1_MACHINE_GPCM
-
-if BR1_MACHINE_FCM
-
-choice
- prompt "NAND Flash EEPROM page size"
-
-config OR1_PGS_SMALL
- bool "Small page device"
-
-config OR1_PGS_LARGE
- bool "Large page device"
-
-endchoice
-
-choice
- prompt "Chip select to command time"
-
-config OR1_CSCT_1_CYCLE
- depends on OR1_TRLX_NORMAL
- bool "1 cycle"
-
-config OR1_CSCT_2_CYCLE
- depends on OR1_TRLX_RELAXED
- bool "2 cycles"
-
-config OR1_CSCT_4_CYCLE
- depends on OR1_TRLX_NORMAL
- bool "4 cycles"
-
-config OR1_CSCT_8_CYCLE
- depends on OR1_TRLX_RELAXED
- bool "8 cycles"
-
-endchoice
-
-choice
- prompt "Command setup time"
-
-config OR1_CST_COINCIDENT
- depends on OR1_TRLX_NORMAL
- bool "Coincident with any command"
-
-config OR1_CST_QUARTER_CLOCK
- depends on OR1_TRLX_NORMAL
- bool "0.25 clocks after"
-
-config OR1_CST_HALF_CLOCK
- depends on OR1_TRLX_RELAXED
- bool "0.5 clocks after"
-
-config OR1_CST_ONE_CLOCK
- depends on OR1_TRLX_RELAXED
- bool "1 clock after"
-
-endchoice
-
-choice
- prompt "Command hold time"
-
-config OR1_CHT_HALF_CLOCK
- depends on OR1_TRLX_NORMAL
- bool "0.5 clocks before"
-
-config OR1_CHT_ONE_CLOCK
- depends on OR1_TRLX_NORMAL
- bool "1 clock before"
-
-config OR1_CHT_ONE_HALF_CLOCK
- depends on OR1_TRLX_RELAXED
- bool "1.5 clocks before"
-
-config OR1_CHT_TWO_CLOCK
- depends on OR1_TRLX_RELAXED
- bool "2 clocks before"
-
-endchoice
-
-choice
- prompt "Reset setup time"
-
-config OR1_RST_THREE_QUARTER_CLOCK
- depends on OR1_TRLX_NORMAL
- bool "0.75 clocks prior"
-
-config OR1_RST_ONE_HALF_CLOCK
- depends on OR1_TRLX_RELAXED
- bool "0.5 clocks prior"
-
-config OR1_RST_ONE_CLOCK
- bool "1 clock prior"
-
-endchoice
-
-endif # BR1_MACHINE_FCM
-
-if BR1_MACHINE_UPM
-
-choice
- prompt "Burst inhibit"
-
-config OR1_BI_BURSTSUPPORT
- bool "Support burst access"
-
-config OR1_BI_BURSTINHIBIT
- bool "Inhibit burst access"
-
-endchoice
-
-endif # BR1_MACHINE_UPM
-
-if BR1_MACHINE_SDRAM
-
-choice
- prompt "Number of column address lines"
-
-config OR1_COLS_7
- bool "7"
-
-config OR1_COLS_8
- bool "8"
-
-config OR1_COLS_9
- bool "9"
-
-config OR1_COLS_10
- bool "10"
-
-config OR1_COLS_11
- bool "11"
-
-config OR1_COLS_12
- bool "12"
-
-config OR1_COLS_13
- bool "13"
-
-config OR1_COLS_14
- bool "14"
-
-endchoice
-
-choice
- prompt "Number of rows address lines"
-
-config OR1_ROWS_9
- bool "9"
-
-config OR1_ROWS_10
- bool "10"
-
-config OR1_ROWS_11
- bool "11"
-
-config OR1_ROWS_12
- bool "12"
-
-config OR1_ROWS_13
- bool "13"
-
-config OR1_ROWS_14
- bool "14"
-
-config OR1_ROWS_15
- bool "15"
-
-endchoice
-
-choice
- prompt "Page mode select"
-
-config OR1_PMSEL_BTB
- bool "Back-to-back"
-
-config OR1_PMSEL_KEPT_OPEN
- bool "Page kept open until page miss or refresh"
-
-endchoice
-
-endif # BR1_MACHINE_SDRAM
-
-choice
- prompt "Relaxed timing"
-
-config OR1_TRLX_NORMAL
- bool "Normal"
-
-config OR1_TRLX_RELAXED
- bool "Relaxed"
-
-endchoice
-
-choice
- prompt "Extended hold time"
-
-config OR1_EHTR_NORMAL
- depends on OR1_TRLX_NORMAL
- bool "Normal"
-
-config OR1_EHTR_1_CYCLE
- depends on OR1_TRLX_NORMAL
- bool "1 idle clock cycle inserted"
-
-config OR1_EHTR_4_CYCLE
- depends on OR1_TRLX_RELAXED
- bool "4 idle clock cycles inserted"
-
-config OR1_EHTR_8_CYCLE
- depends on OR1_TRLX_RELAXED
- bool "8 idle clock cycles inserted"
-
-endchoice
-
-if !ARCH_MPC8308
-
-choice
- prompt "External address latch delay"
-
-config OR1_EAD_NONE
- bool "None"
-
-config OR1_EAD_EXTRA
- bool "Extra"
-
-endchoice
-
-endif # !ARCH_MPC8308
-
-endif # ELBC_BR1_OR1
-
-config BR1_PORTSIZE
- hex
- default 0x800 if BR1_PORTSIZE_8BIT
- default 0x1000 if BR1_PORTSIZE_16BIT
- default 0x1800 if BR1_PORTSIZE_32BIT
-
-config BR1_ERRORCHECKING
- hex
- default 0x0 if !BR1_MACHINE_FCM
- default 0x0 if BR1_ERRORCHECKING_DISABLED
- default 0x200 if BR1_ERRORCHECKING_ECC_CHECKING
- default 0x400 if BR1_ERRORCHECKING_BOTH
-
-config BR1_WRITE_PROTECT_BIT
- hex
- default 0x0 if !BR1_WRITE_PROTECT
- default 0x100 if BR1_WRITE_PROTECT
-
-config BR1_MACHINE
- hex
- default 0x0 if BR1_MACHINE_GPCM
- default 0x20 if BR1_MACHINE_FCM
- default 0x60 if BR1_MACHINE_SDRAM
- default 0x80 if BR1_MACHINE_UPMA
- default 0xa0 if BR1_MACHINE_UPMB
- default 0xc0 if BR1_MACHINE_UPMC
-
-config BR1_ATOMIC
- hex
- default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
- default 0x0 if BR1_ATOMIC_NONE
- default 0x4 if BR1_ATOMIC_RAWA
- default 0x8 if BR1_ATOMIC_WARA
-
-config BR1_VALID_BIT
- hex
- default 0x0 if !ELBC_BR1_OR1
- default 0x1 if ELBC_BR1_OR1
-
-config OR1_AM
- hex
- default 0xffff8000 if OR1_AM_32_KBYTES && !BR1_MACHINE_SDRAM
- default 0xffff0000 if OR1_AM_64_KBYTES
- default 0xfffe0000 if OR1_AM_128_KBYTES
- default 0xfffc0000 if OR1_AM_256_KBYTES
- default 0xfff80000 if OR1_AM_512_KBYTES
- default 0xfff00000 if OR1_AM_1_MBYTES
- default 0xffe00000 if OR1_AM_2_MBYTES
- default 0xffc00000 if OR1_AM_4_MBYTES
- default 0xff800000 if OR1_AM_8_MBYTES
- default 0xff000000 if OR1_AM_16_MBYTES
- default 0xfe000000 if OR1_AM_32_MBYTES
- default 0xfc000000 if OR1_AM_64_MBYTES
- default 0xf8000000 if OR1_AM_128_MBYTES
- default 0xf0000000 if OR1_AM_256_MBYTES
- default 0xe0000000 if OR1_AM_512_MBYTES
- default 0xc0000000 if OR1_AM_1_GBYTES
- default 0x80000000 if OR1_AM_2_GBYTES
- default 0x00000000 if OR1_AM_4_GBYTES
-
-config OR1_XAM
- hex
- default 0x0 if !OR1_XAM_SET
- default 0x6000 if OR1_XAM_SET
-
-config OR1_BCTLD
- hex
- default 0x0 if OR1_BCTLD_ASSERTED
- default 0x1000 if OR1_BCTLD_NOT_ASSERTED
-
-config OR1_BI
- hex
- default 0x0 if !BR1_MACHINE_UPM
- default 0x0 if OR1_BI_BURSTSUPPORT
- default 0x100 if OR1_BI_BURSTINHIBIT
-
-config OR1_COLS
- hex
- default 0x0 if !BR1_MACHINE_SDRAM
- default 0x0 if OR1_COLS_7
- default 0x400 if OR1_COLS_8
- default 0x800 if OR1_COLS_9
- default 0xc00 if OR1_COLS_10
- default 0x1000 if OR1_COLS_11
- default 0x1400 if OR1_COLS_12
- default 0x1800 if OR1_COLS_13
- default 0x1c00 if OR1_COLS_14
-
-config OR1_ROWS
- hex
- default 0x0 if !BR1_MACHINE_SDRAM
- default 0x0 if OR1_ROWS_9
- default 0x40 if OR1_ROWS_10
- default 0x80 if OR1_ROWS_11
- default 0xc0 if OR1_ROWS_12
- default 0x100 if OR1_ROWS_13
- default 0x140 if OR1_ROWS_14
- default 0x180 if OR1_ROWS_15
-
-config OR1_PMSEL
- hex
- default 0x0 if !BR1_MACHINE_SDRAM
- default 0x0 if OR1_PMSEL_BTB
- default 0x20 if OR1_PMSEL_KEPT_OPEN
-
-config OR1_SCY
- hex
- default 0x0 if !BR1_MACHINE_GPCM && !BR1_MACHINE_FCM
- default 0x0 if OR1_SCY_0
- default 0x10 if OR1_SCY_1
- default 0x20 if OR1_SCY_2
- default 0x30 if OR1_SCY_3
- default 0x40 if OR1_SCY_4
- default 0x50 if OR1_SCY_5
- default 0x60 if OR1_SCY_6
- default 0x70 if OR1_SCY_7
- default 0x80 if OR1_SCY_8
- default 0x90 if OR1_SCY_9
- default 0xa0 if OR1_SCY_10
- default 0xb0 if OR1_SCY_11
- default 0xc0 if OR1_SCY_12
- default 0xd0 if OR1_SCY_13
- default 0xe0 if OR1_SCY_14
- default 0xf0 if OR1_SCY_15
-
-config OR1_PGS
- hex
- default 0x0 if !BR1_MACHINE_FCM
- default 0x0 if OR1_PGS_SMALL
- default 0x400 if OR1_PGS_LARGE
-
-config OR1_CSCT
- hex
- default 0x0 if !BR1_MACHINE_FCM
- default 0x0 if OR1_CSCT_1_CYCLE
- default 0x0 if OR1_CSCT_2_CYCLE
- default 0x200 if OR1_CSCT_4_CYCLE
- default 0x200 if OR1_CSCT_8_CYCLE
-
-config OR1_CST
- hex
- default 0x0 if !BR1_MACHINE_FCM
- default 0x0 if OR1_CST_COINCIDENT
- default 0x100 if OR1_CST_QUARTER_CLOCK
- default 0x0 if OR1_CST_HALF_CLOCK
- default 0x100 if OR1_CST_ONE_CLOCK
-
-config OR1_CHT
- hex
- default 0x0 if !BR1_MACHINE_FCM
- default 0x0 if OR1_CHT_HALF_CLOCK
- default 0x80 if OR1_CHT_ONE_CLOCK
- default 0x0 if OR1_CHT_ONE_HALF_CLOCK
- default 0x80 if OR1_CHT_TWO_CLOCK
-
-config OR1_RST
- hex
- default 0x0 if !BR1_MACHINE_FCM
- default 0x0 if OR1_RST_THREE_QUARTER_CLOCK
- default 0x8 if OR1_RST_ONE_CLOCK
- default 0x0 if OR1_RST_ONE_HALF_CLOCK
-
-config OR1_CSNT
- hex
- default 0x0 if !BR1_MACHINE_GPCM
- default 0x0 if OR1_CSNT_NORMAL
- default 0x800 if OR1_CSNT_EARLIER
-
-config OR1_ACS
- hex
- default 0x0 if !BR1_MACHINE_GPCM
- default 0x0 if OR1_ACS_SAME_TIME
- default 0x400 if OR1_ACS_QUARTER_CYCLE_EARLIER
- default 0x600 if OR1_ACS_HALF_CYCLE_EARLIER
-
-config OR1_XACS
- hex
- default 0x0 if !BR1_MACHINE_GPCM
- default 0x0 if OR1_XACS_NORMAL
- default 0x100 if OR1_XACS_EXTENDED
-
-config OR1_SETA
- hex
- default 0x0 if !BR1_MACHINE_GPCM
- default 0x0 if OR1_SETA_INTERNAL
- default 0x8 if OR1_SETA_EXTERNAL
-
-config OR1_TRLX
- hex
- default 0x0 if OR1_TRLX_NORMAL
- default 0x4 if OR1_TRLX_RELAXED
-
-config OR1_EHTR
- hex
- default 0x0 if OR1_EHTR_NORMAL
- default 0x2 if OR1_EHTR_1_CYCLE
- default 0x0 if OR1_EHTR_4_CYCLE
- default 0x2 if OR1_EHTR_8_CYCLE
-
-config OR1_EAD
- hex
- default 0x0 if ARCH_MPC8308
- default 0x0 if OR1_EAD_NONE
- default 0x1 if OR1_EAD_EXTRA
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2
deleted file mode 100644
index a9b2546..0000000
--- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2
+++ /dev/null
@@ -1,733 +0,0 @@
-menuconfig ELBC_BR2_OR2
- bool "ELBC BR2/OR2"
-
-if ELBC_BR2_OR2
-
-config BR2_OR2_NAME
- string "Identifier"
-
-config BR2_OR2_BASE
- hex "Port base"
-
-choice
- prompt "Port size"
-
-config BR2_PORTSIZE_8BIT
- bool "8-bit"
-
-config BR2_PORTSIZE_16BIT
- depends on !BR2_MACHINE_FCM
- bool "16-bit"
-
-
-config BR2_PORTSIZE_32BIT
- depends on !BR2_MACHINE_FCM
- depends on ARCH_MPC8360 || ARCH_MPC8379
- bool "32-bit"
-
-endchoice
-
-if BR2_MACHINE_FCM
-
-choice
- prompt "Data Error Checking"
-
-config BR2_ERRORCHECKING_DISABLED
- bool "Disabled"
-
-config BR2_ERRORCHECKING_ECC_CHECKING
- bool "ECC checking / No ECC generation"
-
-config BR2_ERRORCHECKING_BOTH
- bool "ECC checking and generation"
-
-endchoice
-
-endif
-
-config BR2_WRITE_PROTECT
- bool "Write-protect"
-
-config BR2_MACHINE_UPM
- bool
-
-choice
- prompt "Machine select"
-
-config BR2_MACHINE_GPCM
- bool "GPCM"
-
-config BR2_MACHINE_FCM
- depends on !ARCH_MPC832X && !ARCH_MPC8360
- bool "FCM"
-
-config BR2_MACHINE_SDRAM
- depends on ARCH_MPC8360
- bool "SDRAM"
-
-config BR2_MACHINE_UPMA
- select BR2_MACHINE_UPM
- bool "UPM (A)"
-
-config BR2_MACHINE_UPMB
- select BR2_MACHINE_UPM
- bool "UPM (B)"
-
-config BR2_MACHINE_UPMC
- select BR2_MACHINE_UPM
- bool "UPM (C)"
-
-endchoice
-
-if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
-
-choice
- prompt "Atomic operations"
-
-config BR2_ATOMIC_NONE
- bool "No atomic operations"
-
-config BR2_ATOMIC_RAWA
- bool "Read-after-write-atomic"
-
-config BR2_ATOMIC_WARA
- bool "Write-after-read-atomic"
-
-endchoice
-
-endif
-
-if BR2_MACHINE_GPCM || BR2_MACHINE_FCM || BR2_MACHINE_UPM || BR2_MACHINE_SDRAM
-
-choice
- prompt "Address mask"
-
-config OR2_AM_32_KBYTES
- depends on !BR2_MACHINE_SDRAM
- bool "32 kb"
-
-config OR2_AM_64_KBYTES
- bool "64 kb"
-
-config OR2_AM_128_KBYTES
- bool "128 kb"
-
-config OR2_AM_256_KBYTES
- bool "256 kb"
-
-config OR2_AM_512_KBYTES
- bool "512 kb"
-
-config OR2_AM_1_MBYTES
- bool "1 mb"
-
-config OR2_AM_2_MBYTES
- bool "2 mb"
-
-config OR2_AM_4_MBYTES
- bool "4 mb"
-
-config OR2_AM_8_MBYTES
- bool "8 mb"
-
-config OR2_AM_16_MBYTES
- bool "16 mb"
-
-config OR2_AM_32_MBYTES
- bool "32 mb"
-
-config OR2_AM_64_MBYTES
- bool "64 mb"
-
-# XXX: Some boards define 128MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR2_AM_128_MBYTES
- bool "128 mb"
-
-# XXX: Some boards define 256MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR2_AM_256_MBYTES
- bool "256 mb"
-
-config OR2_AM_512_MBYTES
- depends on BR2_MACHINE_FCM
- bool "512 mb"
-
-# XXX: Some boards define 1GB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR2_AM_1_GBYTES
- bool "1 gb"
-
-config OR2_AM_2_GBYTES
- depends on BR2_MACHINE_FCM
- bool "2 gb"
-
-config OR2_AM_4_GBYTES
- depends on BR2_MACHINE_FCM
- bool "4 gb"
-
-endchoice
-
-config OR2_XAM_SET
- bool "Set unused bytes after address mask"
-choice
- prompt "Buffer control disable"
-
-config OR2_BCTLD_ASSERTED
- bool "Asserted"
-
-config OR2_BCTLD_NOT_ASSERTED
- bool "Not asserted"
-
-endchoice
-
-endif
-
-if BR2_MACHINE_GPCM || BR2_MACHINE_FCM
-
-choice
- prompt "Cycle length in bus clocks"
-
-config OR2_SCY_0
- bool "No wait states"
-
-config OR2_SCY_1
- bool "1 wait state"
-
-config OR2_SCY_2
- bool "2 wait states"
-
-config OR2_SCY_3
- bool "3 wait states"
-
-config OR2_SCY_4
- bool "4 wait states"
-
-config OR2_SCY_5
- bool "5 wait states"
-
-config OR2_SCY_6
- bool "6 wait states"
-
-config OR2_SCY_7
- bool "7 wait states"
-
-config OR2_SCY_8
- depends on BR2_MACHINE_GPCM
- bool "8 wait states"
-
-config OR2_SCY_9
- depends on BR2_MACHINE_GPCM
- bool "9 wait states"
-
-config OR2_SCY_10
- depends on BR2_MACHINE_GPCM
- bool "10 wait states"
-
-config OR2_SCY_11
- depends on BR2_MACHINE_GPCM
- bool "11 wait states"
-
-config OR2_SCY_12
- depends on BR2_MACHINE_GPCM
- bool "12 wait states"
-
-config OR2_SCY_13
- depends on BR2_MACHINE_GPCM
- bool "13 wait states"
-
-config OR2_SCY_14
- depends on BR2_MACHINE_GPCM
- bool "14 wait states"
-
-config OR2_SCY_15
- depends on BR2_MACHINE_GPCM
- bool "15 wait states"
-
-endchoice
-
-endif # BR2_MACHINE_GPCM || BR2_MACHINE_FCM
-
-if BR2_MACHINE_GPCM
-
-choice
- prompt "Chip select negotiation time"
-
-config OR2_CSNT_NORMAL
- bool "Normal"
-
-config OR2_CSNT_EARLIER
- bool "Earlier"
-
-endchoice
-
-choice
- prompt "Address to chip-select setup"
-
-config OR2_ACS_SAME_TIME
- bool "At the same time"
-
-config OR2_ACS_HALF_CYCLE_EARLIER
- bool "Half of a bus clock cycle earlier"
-
-config OR2_ACS_QUARTER_CYCLE_EARLIER
- bool "Half/Quarter of a bus clock cycle earlier"
-
-endchoice
-
-choice
- prompt "Extra address to check-select setup"
-
-config OR2_XACS_NORMAL
- bool "Normal"
-
-config OR2_XACS_EXTENDED
- bool "Extended"
-
-endchoice
-
-choice
- prompt "External address termination"
-
-config OR2_SETA_INTERNAL
- bool "Access is terminated internally"
-
-config OR2_SETA_EXTERNAL
- bool "Access is terminated externally"
-
-endchoice
-
-endif # BR2_MACHINE_GPCM
-
-if BR2_MACHINE_FCM
-
-choice
- prompt "NAND Flash EEPROM page size"
-
-config OR2_PGS_SMALL
- bool "Small page device"
-
-config OR2_PGS_LARGE
- bool "Large page device"
-
-endchoice
-
-choice
- prompt "Chip select to command time"
-
-config OR2_CSCT_1_CYCLE
- depends on OR2_TRLX_NORMAL
- bool "1 cycle"
-
-config OR2_CSCT_2_CYCLE
- depends on OR2_TRLX_RELAXED
- bool "2 cycles"
-
-config OR2_CSCT_4_CYCLE
- depends on OR2_TRLX_NORMAL
- bool "4 cycles"
-
-config OR2_CSCT_8_CYCLE
- depends on OR2_TRLX_RELAXED
- bool "8 cycles"
-
-endchoice
-
-choice
- prompt "Command setup time"
-
-config OR2_CST_COINCIDENT
- depends on OR2_TRLX_NORMAL
- bool "Coincident with any command"
-
-config OR2_CST_QUARTER_CLOCK
- depends on OR2_TRLX_NORMAL
- bool "0.25 clocks after"
-
-config OR2_CST_HALF_CLOCK
- depends on OR2_TRLX_RELAXED
- bool "0.5 clocks after"
-
-config OR2_CST_ONE_CLOCK
- depends on OR2_TRLX_RELAXED
- bool "1 clock after"
-
-endchoice
-
-choice
- prompt "Command hold time"
-
-config OR2_CHT_HALF_CLOCK
- depends on OR2_TRLX_NORMAL
- bool "0.5 clocks before"
-
-config OR2_CHT_ONE_CLOCK
- depends on OR2_TRLX_NORMAL
- bool "1 clock before"
-
-config OR2_CHT_ONE_HALF_CLOCK
- depends on OR2_TRLX_RELAXED
- bool "1.5 clocks before"
-
-config OR2_CHT_TWO_CLOCK
- depends on OR2_TRLX_RELAXED
- bool "2 clocks before"
-
-endchoice
-
-choice
- prompt "Reset setup time"
-
-config OR2_RST_THREE_QUARTER_CLOCK
- depends on OR2_TRLX_NORMAL
- bool "0.75 clocks prior"
-
-config OR2_RST_ONE_HALF_CLOCK
- depends on OR2_TRLX_RELAXED
- bool "0.5 clocks prior"
-
-config OR2_RST_ONE_CLOCK
- bool "1 clock prior"
-
-endchoice
-
-endif # BR2_MACHINE_FCM
-
-if BR2_MACHINE_UPM
-
-choice
- prompt "Burst inhibit"
-
-config OR2_BI_BURSTSUPPORT
- bool "Support burst access"
-
-config OR2_BI_BURSTINHIBIT
- bool "Inhibit burst access"
-
-endchoice
-
-endif # BR2_MACHINE_UPM
-
-if BR2_MACHINE_SDRAM
-
-choice
- prompt "Number of column address lines"
-
-config OR2_COLS_7
- bool "7"
-
-config OR2_COLS_8
- bool "8"
-
-config OR2_COLS_9
- bool "9"
-
-config OR2_COLS_10
- bool "10"
-
-config OR2_COLS_11
- bool "11"
-
-config OR2_COLS_12
- bool "12"
-
-config OR2_COLS_13
- bool "13"
-
-config OR2_COLS_14
- bool "14"
-
-endchoice
-
-choice
- prompt "Number of rows address lines"
-
-config OR2_ROWS_9
- bool "9"
-
-config OR2_ROWS_10
- bool "10"
-
-config OR2_ROWS_11
- bool "11"
-
-config OR2_ROWS_12
- bool "12"
-
-config OR2_ROWS_13
- bool "13"
-
-config OR2_ROWS_14
- bool "14"
-
-config OR2_ROWS_15
- bool "15"
-
-endchoice
-
-choice
- prompt "Page mode select"
-
-config OR2_PMSEL_BTB
- bool "Back-to-back"
-
-config OR2_PMSEL_KEPT_OPEN
- bool "Page kept open until page miss or refresh"
-
-endchoice
-
-endif # BR2_MACHINE_SDRAM
-
-choice
- prompt "Relaxed timing"
-
-config OR2_TRLX_NORMAL
- bool "Normal"
-
-config OR2_TRLX_RELAXED
- bool "Relaxed"
-
-endchoice
-
-choice
- prompt "Extended hold time"
-
-config OR2_EHTR_NORMAL
- depends on OR2_TRLX_NORMAL
- bool "Normal"
-
-config OR2_EHTR_1_CYCLE
- depends on OR2_TRLX_NORMAL
- bool "1 idle clock cycle inserted"
-
-config OR2_EHTR_4_CYCLE
- depends on OR2_TRLX_RELAXED
- bool "4 idle clock cycles inserted"
-
-config OR2_EHTR_8_CYCLE
- depends on OR2_TRLX_RELAXED
- bool "8 idle clock cycles inserted"
-
-endchoice
-
-if !ARCH_MPC8308
-
-choice
- prompt "External address latch delay"
-
-config OR2_EAD_NONE
- bool "None"
-
-config OR2_EAD_EXTRA
- bool "Extra"
-
-endchoice
-
-endif # !ARCH_MPC8308
-
-endif # ELBC_BR2_OR2
-
-config BR2_PORTSIZE
- hex
- default 0x800 if BR2_PORTSIZE_8BIT
- default 0x1000 if BR2_PORTSIZE_16BIT
- default 0x1800 if BR2_PORTSIZE_32BIT
-
-config BR2_ERRORCHECKING
- hex
- default 0x0 if !BR2_MACHINE_FCM
- default 0x0 if BR2_ERRORCHECKING_DISABLED
- default 0x200 if BR2_ERRORCHECKING_ECC_CHECKING
- default 0x400 if BR2_ERRORCHECKING_BOTH
-
-config BR2_WRITE_PROTECT_BIT
- hex
- default 0x0 if !BR2_WRITE_PROTECT
- default 0x100 if BR2_WRITE_PROTECT
-
-config BR2_MACHINE
- hex
- default 0x0 if BR2_MACHINE_GPCM
- default 0x20 if BR2_MACHINE_FCM
- default 0x60 if BR2_MACHINE_SDRAM
- default 0x80 if BR2_MACHINE_UPMA
- default 0xa0 if BR2_MACHINE_UPMB
- default 0xc0 if BR2_MACHINE_UPMC
-
-config BR2_ATOMIC
- hex
- default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
- default 0x0 if BR2_ATOMIC_NONE
- default 0x4 if BR2_ATOMIC_RAWA
- default 0x8 if BR2_ATOMIC_WARA
-
-config BR2_VALID_BIT
- hex
- default 0x0 if !ELBC_BR2_OR2
- default 0x1 if ELBC_BR2_OR2
-
-config OR2_AM
- hex
- default 0xffff8000 if OR2_AM_32_KBYTES && !BR2_MACHINE_SDRAM
- default 0xffff0000 if OR2_AM_64_KBYTES
- default 0xfffe0000 if OR2_AM_128_KBYTES
- default 0xfffc0000 if OR2_AM_256_KBYTES
- default 0xfff80000 if OR2_AM_512_KBYTES
- default 0xfff00000 if OR2_AM_1_MBYTES
- default 0xffe00000 if OR2_AM_2_MBYTES
- default 0xffc00000 if OR2_AM_4_MBYTES
- default 0xff800000 if OR2_AM_8_MBYTES
- default 0xff000000 if OR2_AM_16_MBYTES
- default 0xfe000000 if OR2_AM_32_MBYTES
- default 0xfc000000 if OR2_AM_64_MBYTES
- default 0xf8000000 if OR2_AM_128_MBYTES
- default 0xf0000000 if OR2_AM_256_MBYTES
- default 0xe0000000 if OR2_AM_512_MBYTES
- default 0xc0000000 if OR2_AM_1_GBYTES
- default 0x80000000 if OR2_AM_2_GBYTES
- default 0x00000000 if OR2_AM_4_GBYTES
-
-config OR2_XAM
- hex
- default 0x0 if !OR2_XAM_SET
- default 0x6000 if OR2_XAM_SET
-
-config OR2_BCTLD
- hex
- default 0x0 if OR2_BCTLD_ASSERTED
- default 0x1000 if OR2_BCTLD_NOT_ASSERTED
-
-config OR2_BI
- hex
- default 0x0 if !BR2_MACHINE_UPM
- default 0x0 if OR2_BI_BURSTSUPPORT
- default 0x100 if OR2_BI_BURSTINHIBIT
-
-config OR2_COLS
- hex
- default 0x0 if !BR2_MACHINE_SDRAM
- default 0x0 if OR2_COLS_7
- default 0x400 if OR2_COLS_8
- default 0x800 if OR2_COLS_9
- default 0xc00 if OR2_COLS_10
- default 0x1000 if OR2_COLS_11
- default 0x1400 if OR2_COLS_12
- default 0x1800 if OR2_COLS_13
- default 0x1c00 if OR2_COLS_14
-
-config OR2_ROWS
- hex
- default 0x0 if !BR2_MACHINE_SDRAM
- default 0x0 if OR2_ROWS_9
- default 0x40 if OR2_ROWS_10
- default 0x80 if OR2_ROWS_11
- default 0xc0 if OR2_ROWS_12
- default 0x100 if OR2_ROWS_13
- default 0x140 if OR2_ROWS_14
- default 0x180 if OR2_ROWS_15
-
-config OR2_PMSEL
- hex
- default 0x0 if !BR2_MACHINE_SDRAM
- default 0x0 if OR2_PMSEL_BTB
- default 0x20 if OR2_PMSEL_KEPT_OPEN
-
-config OR2_SCY
- hex
- default 0x0 if !BR2_MACHINE_GPCM && !BR2_MACHINE_FCM
- default 0x0 if OR2_SCY_0
- default 0x10 if OR2_SCY_1
- default 0x20 if OR2_SCY_2
- default 0x30 if OR2_SCY_3
- default 0x40 if OR2_SCY_4
- default 0x50 if OR2_SCY_5
- default 0x60 if OR2_SCY_6
- default 0x70 if OR2_SCY_7
- default 0x80 if OR2_SCY_8
- default 0x90 if OR2_SCY_9
- default 0xa0 if OR2_SCY_10
- default 0xb0 if OR2_SCY_11
- default 0xc0 if OR2_SCY_12
- default 0xd0 if OR2_SCY_13
- default 0xe0 if OR2_SCY_14
- default 0xf0 if OR2_SCY_15
-
-config OR2_PGS
- hex
- default 0x0 if !BR2_MACHINE_FCM
- default 0x0 if OR2_PGS_SMALL
- default 0x400 if OR2_PGS_LARGE
-
-config OR2_CSCT
- hex
- default 0x0 if !BR2_MACHINE_FCM
- default 0x0 if OR2_CSCT_1_CYCLE
- default 0x0 if OR2_CSCT_2_CYCLE
- default 0x200 if OR2_CSCT_4_CYCLE
- default 0x200 if OR2_CSCT_8_CYCLE
-
-config OR2_CST
- hex
- default 0x0 if !BR2_MACHINE_FCM
- default 0x0 if OR2_CST_COINCIDENT
- default 0x100 if OR2_CST_QUARTER_CLOCK
- default 0x0 if OR2_CST_HALF_CLOCK
- default 0x100 if OR2_CST_ONE_CLOCK
-
-config OR2_CHT
- hex
- default 0x0 if !BR2_MACHINE_FCM
- default 0x0 if OR2_CHT_HALF_CLOCK
- default 0x80 if OR2_CHT_ONE_CLOCK
- default 0x0 if OR2_CHT_ONE_HALF_CLOCK
- default 0x80 if OR2_CHT_TWO_CLOCK
-
-config OR2_RST
- hex
- default 0x0 if !BR2_MACHINE_FCM
- default 0x0 if OR2_RST_THREE_QUARTER_CLOCK
- default 0x8 if OR2_RST_ONE_CLOCK
- default 0x0 if OR2_RST_ONE_HALF_CLOCK
-
-config OR2_CSNT
- hex
- default 0x0 if !BR2_MACHINE_GPCM
- default 0x0 if OR2_CSNT_NORMAL
- default 0x800 if OR2_CSNT_EARLIER
-
-config OR2_ACS
- hex
- default 0x0 if !BR2_MACHINE_GPCM
- default 0x0 if OR2_ACS_SAME_TIME
- default 0x400 if OR2_ACS_QUARTER_CYCLE_EARLIER
- default 0x600 if OR2_ACS_HALF_CYCLE_EARLIER
-
-config OR2_XACS
- hex
- default 0x0 if !BR2_MACHINE_GPCM
- default 0x0 if OR2_XACS_NORMAL
- default 0x100 if OR2_XACS_EXTENDED
-
-config OR2_SETA
- hex
- default 0x0 if !BR2_MACHINE_GPCM
- default 0x0 if OR2_SETA_INTERNAL
- default 0x8 if OR2_SETA_EXTERNAL
-
-config OR2_TRLX
- hex
- default 0x0 if OR2_TRLX_NORMAL
- default 0x4 if OR2_TRLX_RELAXED
-
-config OR2_EHTR
- hex
- default 0x0 if OR2_EHTR_NORMAL
- default 0x2 if OR2_EHTR_1_CYCLE
- default 0x0 if OR2_EHTR_4_CYCLE
- default 0x2 if OR2_EHTR_8_CYCLE
-
-config OR2_EAD
- hex
- default 0x0 if ARCH_MPC8308
- default 0x0 if OR2_EAD_NONE
- default 0x1 if OR2_EAD_EXTRA
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3
deleted file mode 100644
index 94442cd..0000000
--- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3
+++ /dev/null
@@ -1,733 +0,0 @@
-menuconfig ELBC_BR3_OR3
- bool "ELBC BR3/OR3"
-
-if ELBC_BR3_OR3
-
-config BR3_OR3_NAME
- string "Identifier"
-
-config BR3_OR3_BASE
- hex "Port base"
-
-choice
- prompt "Port size"
-
-config BR3_PORTSIZE_8BIT
- bool "8-bit"
-
-config BR3_PORTSIZE_16BIT
- depends on !BR3_MACHINE_FCM
- bool "16-bit"
-
-
-config BR3_PORTSIZE_32BIT
- depends on !BR3_MACHINE_FCM
- depends on ARCH_MPC8360 || ARCH_MPC8379
- bool "32-bit"
-
-endchoice
-
-if BR3_MACHINE_FCM
-
-choice
- prompt "Data Error Checking"
-
-config BR3_ERRORCHECKING_DISABLED
- bool "Disabled"
-
-config BR3_ERRORCHECKING_ECC_CHECKING
- bool "ECC checking / No ECC generation"
-
-config BR3_ERRORCHECKING_BOTH
- bool "ECC checking and generation"
-
-endchoice
-
-endif
-
-config BR3_WRITE_PROTECT
- bool "Write-protect"
-
-config BR3_MACHINE_UPM
- bool
-
-choice
- prompt "Machine select"
-
-config BR3_MACHINE_GPCM
- bool "GPCM"
-
-config BR3_MACHINE_FCM
- depends on !ARCH_MPC832X && !ARCH_MPC8360
- bool "FCM"
-
-config BR3_MACHINE_SDRAM
- depends on ARCH_MPC8360
- bool "SDRAM"
-
-config BR3_MACHINE_UPMA
- select BR3_MACHINE_UPM
- bool "UPM (A)"
-
-config BR3_MACHINE_UPMB
- select BR3_MACHINE_UPM
- bool "UPM (B)"
-
-config BR3_MACHINE_UPMC
- select BR3_MACHINE_UPM
- bool "UPM (C)"
-
-endchoice
-
-if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
-
-choice
- prompt "Atomic operations"
-
-config BR3_ATOMIC_NONE
- bool "No atomic operations"
-
-config BR3_ATOMIC_RAWA
- bool "Read-after-write-atomic"
-
-config BR3_ATOMIC_WARA
- bool "Write-after-read-atomic"
-
-endchoice
-
-endif
-
-if BR3_MACHINE_GPCM || BR3_MACHINE_FCM || BR3_MACHINE_UPM || BR3_MACHINE_SDRAM
-
-choice
- prompt "Address mask"
-
-config OR3_AM_32_KBYTES
- depends on !BR3_MACHINE_SDRAM
- bool "32 kb"
-
-config OR3_AM_64_KBYTES
- bool "64 kb"
-
-config OR3_AM_128_KBYTES
- bool "128 kb"
-
-config OR3_AM_256_KBYTES
- bool "256 kb"
-
-config OR3_AM_512_KBYTES
- bool "512 kb"
-
-config OR3_AM_1_MBYTES
- bool "1 mb"
-
-config OR3_AM_2_MBYTES
- bool "2 mb"
-
-config OR3_AM_4_MBYTES
- bool "4 mb"
-
-config OR3_AM_8_MBYTES
- bool "8 mb"
-
-config OR3_AM_16_MBYTES
- bool "16 mb"
-
-config OR3_AM_32_MBYTES
- bool "32 mb"
-
-config OR3_AM_64_MBYTES
- bool "64 mb"
-
-# XXX: Some boards define 128MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR3_AM_128_MBYTES
- bool "128 mb"
-
-# XXX: Some boards define 256MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR3_AM_256_MBYTES
- bool "256 mb"
-
-config OR3_AM_512_MBYTES
- depends on BR3_MACHINE_FCM
- bool "512 mb"
-
-# XXX: Some boards define 1GB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR3_AM_1_GBYTES
- bool "1 gb"
-
-config OR3_AM_2_GBYTES
- depends on BR3_MACHINE_FCM
- bool "2 gb"
-
-config OR3_AM_4_GBYTES
- depends on BR3_MACHINE_FCM
- bool "4 gb"
-
-endchoice
-
-config OR3_XAM_SET
- bool "Set unused bytes after address mask"
-choice
- prompt "Buffer control disable"
-
-config OR3_BCTLD_ASSERTED
- bool "Asserted"
-
-config OR3_BCTLD_NOT_ASSERTED
- bool "Not asserted"
-
-endchoice
-
-endif
-
-if BR3_MACHINE_GPCM || BR3_MACHINE_FCM
-
-choice
- prompt "Cycle length in bus clocks"
-
-config OR3_SCY_0
- bool "No wait states"
-
-config OR3_SCY_1
- bool "1 wait state"
-
-config OR3_SCY_2
- bool "2 wait states"
-
-config OR3_SCY_3
- bool "3 wait states"
-
-config OR3_SCY_4
- bool "4 wait states"
-
-config OR3_SCY_5
- bool "5 wait states"
-
-config OR3_SCY_6
- bool "6 wait states"
-
-config OR3_SCY_7
- bool "7 wait states"
-
-config OR3_SCY_8
- depends on BR3_MACHINE_GPCM
- bool "8 wait states"
-
-config OR3_SCY_9
- depends on BR3_MACHINE_GPCM
- bool "9 wait states"
-
-config OR3_SCY_10
- depends on BR3_MACHINE_GPCM
- bool "10 wait states"
-
-config OR3_SCY_11
- depends on BR3_MACHINE_GPCM
- bool "11 wait states"
-
-config OR3_SCY_12
- depends on BR3_MACHINE_GPCM
- bool "12 wait states"
-
-config OR3_SCY_13
- depends on BR3_MACHINE_GPCM
- bool "13 wait states"
-
-config OR3_SCY_14
- depends on BR3_MACHINE_GPCM
- bool "14 wait states"
-
-config OR3_SCY_15
- depends on BR3_MACHINE_GPCM
- bool "15 wait states"
-
-endchoice
-
-endif # BR3_MACHINE_GPCM || BR3_MACHINE_FCM
-
-if BR3_MACHINE_GPCM
-
-choice
- prompt "Chip select negotiation time"
-
-config OR3_CSNT_NORMAL
- bool "Normal"
-
-config OR3_CSNT_EARLIER
- bool "Earlier"
-
-endchoice
-
-choice
- prompt "Address to chip-select setup"
-
-config OR3_ACS_SAME_TIME
- bool "At the same time"
-
-config OR3_ACS_HALF_CYCLE_EARLIER
- bool "Half of a bus clock cycle earlier"
-
-config OR3_ACS_QUARTER_CYCLE_EARLIER
- bool "Half/Quarter of a bus clock cycle earlier"
-
-endchoice
-
-choice
- prompt "Extra address to check-select setup"
-
-config OR3_XACS_NORMAL
- bool "Normal"
-
-config OR3_XACS_EXTENDED
- bool "Extended"
-
-endchoice
-
-choice
- prompt "External address termination"
-
-config OR3_SETA_INTERNAL
- bool "Access is terminated internally"
-
-config OR3_SETA_EXTERNAL
- bool "Access is terminated externally"
-
-endchoice
-
-endif # BR3_MACHINE_GPCM
-
-if BR3_MACHINE_FCM
-
-choice
- prompt "NAND Flash EEPROM page size"
-
-config OR3_PGS_SMALL
- bool "Small page device"
-
-config OR3_PGS_LARGE
- bool "Large page device"
-
-endchoice
-
-choice
- prompt "Chip select to command time"
-
-config OR3_CSCT_1_CYCLE
- depends on OR3_TRLX_NORMAL
- bool "1 cycle"
-
-config OR3_CSCT_2_CYCLE
- depends on OR3_TRLX_RELAXED
- bool "2 cycles"
-
-config OR3_CSCT_4_CYCLE
- depends on OR3_TRLX_NORMAL
- bool "4 cycles"
-
-config OR3_CSCT_8_CYCLE
- depends on OR3_TRLX_RELAXED
- bool "8 cycles"
-
-endchoice
-
-choice
- prompt "Command setup time"
-
-config OR3_CST_COINCIDENT
- depends on OR3_TRLX_NORMAL
- bool "Coincident with any command"
-
-config OR3_CST_QUARTER_CLOCK
- depends on OR3_TRLX_NORMAL
- bool "0.25 clocks after"
-
-config OR3_CST_HALF_CLOCK
- depends on OR3_TRLX_RELAXED
- bool "0.5 clocks after"
-
-config OR3_CST_ONE_CLOCK
- depends on OR3_TRLX_RELAXED
- bool "1 clock after"
-
-endchoice
-
-choice
- prompt "Command hold time"
-
-config OR3_CHT_HALF_CLOCK
- depends on OR3_TRLX_NORMAL
- bool "0.5 clocks before"
-
-config OR3_CHT_ONE_CLOCK
- depends on OR3_TRLX_NORMAL
- bool "1 clock before"
-
-config OR3_CHT_ONE_HALF_CLOCK
- depends on OR3_TRLX_RELAXED
- bool "1.5 clocks before"
-
-config OR3_CHT_TWO_CLOCK
- depends on OR3_TRLX_RELAXED
- bool "2 clocks before"
-
-endchoice
-
-choice
- prompt "Reset setup time"
-
-config OR3_RST_THREE_QUARTER_CLOCK
- depends on OR3_TRLX_NORMAL
- bool "0.75 clocks prior"
-
-config OR3_RST_ONE_HALF_CLOCK
- depends on OR3_TRLX_RELAXED
- bool "0.5 clocks prior"
-
-config OR3_RST_ONE_CLOCK
- bool "1 clock prior"
-
-endchoice
-
-endif # BR3_MACHINE_FCM
-
-if BR3_MACHINE_UPM
-
-choice
- prompt "Burst inhibit"
-
-config OR3_BI_BURSTSUPPORT
- bool "Support burst access"
-
-config OR3_BI_BURSTINHIBIT
- bool "Inhibit burst access"
-
-endchoice
-
-endif # BR3_MACHINE_UPM
-
-if BR3_MACHINE_SDRAM
-
-choice
- prompt "Number of column address lines"
-
-config OR3_COLS_7
- bool "7"
-
-config OR3_COLS_8
- bool "8"
-
-config OR3_COLS_9
- bool "9"
-
-config OR3_COLS_10
- bool "10"
-
-config OR3_COLS_11
- bool "11"
-
-config OR3_COLS_12
- bool "12"
-
-config OR3_COLS_13
- bool "13"
-
-config OR3_COLS_14
- bool "14"
-
-endchoice
-
-choice
- prompt "Number of rows address lines"
-
-config OR3_ROWS_9
- bool "9"
-
-config OR3_ROWS_10
- bool "10"
-
-config OR3_ROWS_11
- bool "11"
-
-config OR3_ROWS_12
- bool "12"
-
-config OR3_ROWS_13
- bool "13"
-
-config OR3_ROWS_14
- bool "14"
-
-config OR3_ROWS_15
- bool "15"
-
-endchoice
-
-choice
- prompt "Page mode select"
-
-config OR3_PMSEL_BTB
- bool "Back-to-back"
-
-config OR3_PMSEL_KEPT_OPEN
- bool "Page kept open until page miss or refresh"
-
-endchoice
-
-endif # BR3_MACHINE_SDRAM
-
-choice
- prompt "Relaxed timing"
-
-config OR3_TRLX_NORMAL
- bool "Normal"
-
-config OR3_TRLX_RELAXED
- bool "Relaxed"
-
-endchoice
-
-choice
- prompt "Extended hold time"
-
-config OR3_EHTR_NORMAL
- depends on OR3_TRLX_NORMAL
- bool "Normal"
-
-config OR3_EHTR_1_CYCLE
- depends on OR3_TRLX_NORMAL
- bool "1 idle clock cycle inserted"
-
-config OR3_EHTR_4_CYCLE
- depends on OR3_TRLX_RELAXED
- bool "4 idle clock cycles inserted"
-
-config OR3_EHTR_8_CYCLE
- depends on OR3_TRLX_RELAXED
- bool "8 idle clock cycles inserted"
-
-endchoice
-
-if !ARCH_MPC8308
-
-choice
- prompt "External address latch delay"
-
-config OR3_EAD_NONE
- bool "None"
-
-config OR3_EAD_EXTRA
- bool "Extra"
-
-endchoice
-
-endif # !ARCH_MPC8308
-
-endif # ELBC_BR3_OR3
-
-config BR3_PORTSIZE
- hex
- default 0x800 if BR3_PORTSIZE_8BIT
- default 0x1000 if BR3_PORTSIZE_16BIT
- default 0x1800 if BR3_PORTSIZE_32BIT
-
-config BR3_ERRORCHECKING
- hex
- default 0x0 if !BR3_MACHINE_FCM
- default 0x0 if BR3_ERRORCHECKING_DISABLED
- default 0x200 if BR3_ERRORCHECKING_ECC_CHECKING
- default 0x400 if BR3_ERRORCHECKING_BOTH
-
-config BR3_WRITE_PROTECT_BIT
- hex
- default 0x0 if !BR3_WRITE_PROTECT
- default 0x100 if BR3_WRITE_PROTECT
-
-config BR3_MACHINE
- hex
- default 0x0 if BR3_MACHINE_GPCM
- default 0x20 if BR3_MACHINE_FCM
- default 0x60 if BR3_MACHINE_SDRAM
- default 0x80 if BR3_MACHINE_UPMA
- default 0xa0 if BR3_MACHINE_UPMB
- default 0xc0 if BR3_MACHINE_UPMC
-
-config BR3_ATOMIC
- hex
- default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
- default 0x0 if BR3_ATOMIC_NONE
- default 0x4 if BR3_ATOMIC_RAWA
- default 0x8 if BR3_ATOMIC_WARA
-
-config BR3_VALID_BIT
- hex
- default 0x0 if !ELBC_BR3_OR3
- default 0x1 if ELBC_BR3_OR3
-
-config OR3_AM
- hex
- default 0xffff8000 if OR3_AM_32_KBYTES && !BR3_MACHINE_SDRAM
- default 0xffff0000 if OR3_AM_64_KBYTES
- default 0xfffe0000 if OR3_AM_128_KBYTES
- default 0xfffc0000 if OR3_AM_256_KBYTES
- default 0xfff80000 if OR3_AM_512_KBYTES
- default 0xfff00000 if OR3_AM_1_MBYTES
- default 0xffe00000 if OR3_AM_2_MBYTES
- default 0xffc00000 if OR3_AM_4_MBYTES
- default 0xff800000 if OR3_AM_8_MBYTES
- default 0xff000000 if OR3_AM_16_MBYTES
- default 0xfe000000 if OR3_AM_32_MBYTES
- default 0xfc000000 if OR3_AM_64_MBYTES
- default 0xf8000000 if OR3_AM_128_MBYTES
- default 0xf0000000 if OR3_AM_256_MBYTES
- default 0xe0000000 if OR3_AM_512_MBYTES
- default 0xc0000000 if OR3_AM_1_GBYTES
- default 0x80000000 if OR3_AM_2_GBYTES
- default 0x00000000 if OR3_AM_4_GBYTES
-
-config OR3_XAM
- hex
- default 0x0 if !OR3_XAM_SET
- default 0x6000 if OR3_XAM_SET
-
-config OR3_BCTLD
- hex
- default 0x0 if OR3_BCTLD_ASSERTED
- default 0x1000 if OR3_BCTLD_NOT_ASSERTED
-
-config OR3_BI
- hex
- default 0x0 if !BR3_MACHINE_UPM
- default 0x0 if OR3_BI_BURSTSUPPORT
- default 0x100 if OR3_BI_BURSTINHIBIT
-
-config OR3_COLS
- hex
- default 0x0 if !BR3_MACHINE_SDRAM
- default 0x0 if OR3_COLS_7
- default 0x400 if OR3_COLS_8
- default 0x800 if OR3_COLS_9
- default 0xc00 if OR3_COLS_10
- default 0x1000 if OR3_COLS_11
- default 0x1400 if OR3_COLS_12
- default 0x1800 if OR3_COLS_13
- default 0x1c00 if OR3_COLS_14
-
-config OR3_ROWS
- hex
- default 0x0 if !BR3_MACHINE_SDRAM
- default 0x0 if OR3_ROWS_9
- default 0x40 if OR3_ROWS_10
- default 0x80 if OR3_ROWS_11
- default 0xc0 if OR3_ROWS_12
- default 0x100 if OR3_ROWS_13
- default 0x140 if OR3_ROWS_14
- default 0x180 if OR3_ROWS_15
-
-config OR3_PMSEL
- hex
- default 0x0 if !BR3_MACHINE_SDRAM
- default 0x0 if OR3_PMSEL_BTB
- default 0x20 if OR3_PMSEL_KEPT_OPEN
-
-config OR3_SCY
- hex
- default 0x0 if !BR3_MACHINE_GPCM && !BR3_MACHINE_FCM
- default 0x0 if OR3_SCY_0
- default 0x10 if OR3_SCY_1
- default 0x20 if OR3_SCY_2
- default 0x30 if OR3_SCY_3
- default 0x40 if OR3_SCY_4
- default 0x50 if OR3_SCY_5
- default 0x60 if OR3_SCY_6
- default 0x70 if OR3_SCY_7
- default 0x80 if OR3_SCY_8
- default 0x90 if OR3_SCY_9
- default 0xa0 if OR3_SCY_10
- default 0xb0 if OR3_SCY_11
- default 0xc0 if OR3_SCY_12
- default 0xd0 if OR3_SCY_13
- default 0xe0 if OR3_SCY_14
- default 0xf0 if OR3_SCY_15
-
-config OR3_PGS
- hex
- default 0x0 if !BR3_MACHINE_FCM
- default 0x0 if OR3_PGS_SMALL
- default 0x400 if OR3_PGS_LARGE
-
-config OR3_CSCT
- hex
- default 0x0 if !BR3_MACHINE_FCM
- default 0x0 if OR3_CSCT_1_CYCLE
- default 0x0 if OR3_CSCT_2_CYCLE
- default 0x200 if OR3_CSCT_4_CYCLE
- default 0x200 if OR3_CSCT_8_CYCLE
-
-config OR3_CST
- hex
- default 0x0 if !BR3_MACHINE_FCM
- default 0x0 if OR3_CST_COINCIDENT
- default 0x100 if OR3_CST_QUARTER_CLOCK
- default 0x0 if OR3_CST_HALF_CLOCK
- default 0x100 if OR3_CST_ONE_CLOCK
-
-config OR3_CHT
- hex
- default 0x0 if !BR3_MACHINE_FCM
- default 0x0 if OR3_CHT_HALF_CLOCK
- default 0x80 if OR3_CHT_ONE_CLOCK
- default 0x0 if OR3_CHT_ONE_HALF_CLOCK
- default 0x80 if OR3_CHT_TWO_CLOCK
-
-config OR3_RST
- hex
- default 0x0 if !BR3_MACHINE_FCM
- default 0x0 if OR3_RST_THREE_QUARTER_CLOCK
- default 0x8 if OR3_RST_ONE_CLOCK
- default 0x0 if OR3_RST_ONE_HALF_CLOCK
-
-config OR3_CSNT
- hex
- default 0x0 if !BR3_MACHINE_GPCM
- default 0x0 if OR3_CSNT_NORMAL
- default 0x800 if OR3_CSNT_EARLIER
-
-config OR3_ACS
- hex
- default 0x0 if !BR3_MACHINE_GPCM
- default 0x0 if OR3_ACS_SAME_TIME
- default 0x400 if OR3_ACS_QUARTER_CYCLE_EARLIER
- default 0x600 if OR3_ACS_HALF_CYCLE_EARLIER
-
-config OR3_XACS
- hex
- default 0x0 if !BR3_MACHINE_GPCM
- default 0x0 if OR3_XACS_NORMAL
- default 0x100 if OR3_XACS_EXTENDED
-
-config OR3_SETA
- hex
- default 0x0 if !BR3_MACHINE_GPCM
- default 0x0 if OR3_SETA_INTERNAL
- default 0x8 if OR3_SETA_EXTERNAL
-
-config OR3_TRLX
- hex
- default 0x0 if OR3_TRLX_NORMAL
- default 0x4 if OR3_TRLX_RELAXED
-
-config OR3_EHTR
- hex
- default 0x0 if OR3_EHTR_NORMAL
- default 0x2 if OR3_EHTR_1_CYCLE
- default 0x0 if OR3_EHTR_4_CYCLE
- default 0x2 if OR3_EHTR_8_CYCLE
-
-config OR3_EAD
- hex
- default 0x0 if ARCH_MPC8308
- default 0x0 if OR3_EAD_NONE
- default 0x1 if OR3_EAD_EXTRA
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4
deleted file mode 100644
index 5d69385..0000000
--- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4
+++ /dev/null
@@ -1,733 +0,0 @@
-menuconfig ELBC_BR4_OR4
- bool "ELBC BR4/OR4"
-
-if ELBC_BR4_OR4
-
-config BR4_OR4_NAME
- string "Identifier"
-
-config BR4_OR4_BASE
- hex "Port base"
-
-choice
- prompt "Port size"
-
-config BR4_PORTSIZE_8BIT
- bool "8-bit"
-
-config BR4_PORTSIZE_16BIT
- depends on !BR4_MACHINE_FCM
- bool "16-bit"
-
-
-config BR4_PORTSIZE_32BIT
- depends on !BR4_MACHINE_FCM
- depends on ARCH_MPC8360 || ARCH_MPC8379
- bool "32-bit"
-
-endchoice
-
-if BR4_MACHINE_FCM
-
-choice
- prompt "Data Error Checking"
-
-config BR4_ERRORCHECKING_DISABLED
- bool "Disabled"
-
-config BR4_ERRORCHECKING_ECC_CHECKING
- bool "ECC checking / No ECC generation"
-
-config BR4_ERRORCHECKING_BOTH
- bool "ECC checking and generation"
-
-endchoice
-
-endif
-
-config BR4_WRITE_PROTECT
- bool "Write-protect"
-
-config BR4_MACHINE_UPM
- bool
-
-choice
- prompt "Machine select"
-
-config BR4_MACHINE_GPCM
- bool "GPCM"
-
-config BR4_MACHINE_FCM
- depends on !ARCH_MPC832X && !ARCH_MPC8360
- bool "FCM"
-
-config BR4_MACHINE_SDRAM
- depends on ARCH_MPC8360
- bool "SDRAM"
-
-config BR4_MACHINE_UPMA
- select BR4_MACHINE_UPM
- bool "UPM (A)"
-
-config BR4_MACHINE_UPMB
- select BR4_MACHINE_UPM
- bool "UPM (B)"
-
-config BR4_MACHINE_UPMC
- select BR4_MACHINE_UPM
- bool "UPM (C)"
-
-endchoice
-
-if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
-
-choice
- prompt "Atomic operations"
-
-config BR4_ATOMIC_NONE
- bool "No atomic operations"
-
-config BR4_ATOMIC_RAWA
- bool "Read-after-write-atomic"
-
-config BR4_ATOMIC_WARA
- bool "Write-after-read-atomic"
-
-endchoice
-
-endif
-
-if BR4_MACHINE_GPCM || BR4_MACHINE_FCM || BR4_MACHINE_UPM || BR4_MACHINE_SDRAM
-
-choice
- prompt "Address mask"
-
-config OR4_AM_32_KBYTES
- depends on !BR4_MACHINE_SDRAM
- bool "32 kb"
-
-config OR4_AM_64_KBYTES
- bool "64 kb"
-
-config OR4_AM_128_KBYTES
- bool "128 kb"
-
-config OR4_AM_256_KBYTES
- bool "256 kb"
-
-config OR4_AM_512_KBYTES
- bool "512 kb"
-
-config OR4_AM_1_MBYTES
- bool "1 mb"
-
-config OR4_AM_2_MBYTES
- bool "2 mb"
-
-config OR4_AM_4_MBYTES
- bool "4 mb"
-
-config OR4_AM_8_MBYTES
- bool "8 mb"
-
-config OR4_AM_16_MBYTES
- bool "16 mb"
-
-config OR4_AM_32_MBYTES
- bool "32 mb"
-
-config OR4_AM_64_MBYTES
- bool "64 mb"
-
-# XXX: Some boards define 128MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR4_AM_128_MBYTES
- bool "128 mb"
-
-# XXX: Some boards define 256MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR4_AM_256_MBYTES
- bool "256 mb"
-
-config OR4_AM_512_MBYTES
- depends on BR4_MACHINE_FCM
- bool "512 mb"
-
-# XXX: Some boards define 1GB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR4_AM_1_GBYTES
- bool "1 gb"
-
-config OR4_AM_2_GBYTES
- depends on BR4_MACHINE_FCM
- bool "2 gb"
-
-config OR4_AM_4_GBYTES
- depends on BR4_MACHINE_FCM
- bool "4 gb"
-
-endchoice
-
-config OR4_XAM_SET
- bool "Set unused bytes after address mask"
-choice
- prompt "Buffer control disable"
-
-config OR4_BCTLD_ASSERTED
- bool "Asserted"
-
-config OR4_BCTLD_NOT_ASSERTED
- bool "Not asserted"
-
-endchoice
-
-endif
-
-if BR4_MACHINE_GPCM || BR4_MACHINE_FCM
-
-choice
- prompt "Cycle length in bus clocks"
-
-config OR4_SCY_0
- bool "No wait states"
-
-config OR4_SCY_1
- bool "1 wait state"
-
-config OR4_SCY_2
- bool "2 wait states"
-
-config OR4_SCY_3
- bool "3 wait states"
-
-config OR4_SCY_4
- bool "4 wait states"
-
-config OR4_SCY_5
- bool "5 wait states"
-
-config OR4_SCY_6
- bool "6 wait states"
-
-config OR4_SCY_7
- bool "7 wait states"
-
-config OR4_SCY_8
- depends on BR4_MACHINE_GPCM
- bool "8 wait states"
-
-config OR4_SCY_9
- depends on BR4_MACHINE_GPCM
- bool "9 wait states"
-
-config OR4_SCY_10
- depends on BR4_MACHINE_GPCM
- bool "10 wait states"
-
-config OR4_SCY_11
- depends on BR4_MACHINE_GPCM
- bool "11 wait states"
-
-config OR4_SCY_12
- depends on BR4_MACHINE_GPCM
- bool "12 wait states"
-
-config OR4_SCY_13
- depends on BR4_MACHINE_GPCM
- bool "13 wait states"
-
-config OR4_SCY_14
- depends on BR4_MACHINE_GPCM
- bool "14 wait states"
-
-config OR4_SCY_15
- depends on BR4_MACHINE_GPCM
- bool "15 wait states"
-
-endchoice
-
-endif # BR4_MACHINE_GPCM || BR4_MACHINE_FCM
-
-if BR4_MACHINE_GPCM
-
-choice
- prompt "Chip select negotiation time"
-
-config OR4_CSNT_NORMAL
- bool "Normal"
-
-config OR4_CSNT_EARLIER
- bool "Earlier"
-
-endchoice
-
-choice
- prompt "Address to chip-select setup"
-
-config OR4_ACS_SAME_TIME
- bool "At the same time"
-
-config OR4_ACS_HALF_CYCLE_EARLIER
- bool "Half of a bus clock cycle earlier"
-
-config OR4_ACS_QUARTER_CYCLE_EARLIER
- bool "Half/Quarter of a bus clock cycle earlier"
-
-endchoice
-
-choice
- prompt "Extra address to check-select setup"
-
-config OR4_XACS_NORMAL
- bool "Normal"
-
-config OR4_XACS_EXTENDED
- bool "Extended"
-
-endchoice
-
-choice
- prompt "External address termination"
-
-config OR4_SETA_INTERNAL
- bool "Access is terminated internally"
-
-config OR4_SETA_EXTERNAL
- bool "Access is terminated externally"
-
-endchoice
-
-endif # BR4_MACHINE_GPCM
-
-if BR4_MACHINE_FCM
-
-choice
- prompt "NAND Flash EEPROM page size"
-
-config OR4_PGS_SMALL
- bool "Small page device"
-
-config OR4_PGS_LARGE
- bool "Large page device"
-
-endchoice
-
-choice
- prompt "Chip select to command time"
-
-config OR4_CSCT_1_CYCLE
- depends on OR4_TRLX_NORMAL
- bool "1 cycle"
-
-config OR4_CSCT_2_CYCLE
- depends on OR4_TRLX_RELAXED
- bool "2 cycles"
-
-config OR4_CSCT_4_CYCLE
- depends on OR4_TRLX_NORMAL
- bool "4 cycles"
-
-config OR4_CSCT_8_CYCLE
- depends on OR4_TRLX_RELAXED
- bool "8 cycles"
-
-endchoice
-
-choice
- prompt "Command setup time"
-
-config OR4_CST_COINCIDENT
- depends on OR4_TRLX_NORMAL
- bool "Coincident with any command"
-
-config OR4_CST_QUARTER_CLOCK
- depends on OR4_TRLX_NORMAL
- bool "0.25 clocks after"
-
-config OR4_CST_HALF_CLOCK
- depends on OR4_TRLX_RELAXED
- bool "0.5 clocks after"
-
-config OR4_CST_ONE_CLOCK
- depends on OR4_TRLX_RELAXED
- bool "1 clock after"
-
-endchoice
-
-choice
- prompt "Command hold time"
-
-config OR4_CHT_HALF_CLOCK
- depends on OR4_TRLX_NORMAL
- bool "0.5 clocks before"
-
-config OR4_CHT_ONE_CLOCK
- depends on OR4_TRLX_NORMAL
- bool "1 clock before"
-
-config OR4_CHT_ONE_HALF_CLOCK
- depends on OR4_TRLX_RELAXED
- bool "1.5 clocks before"
-
-config OR4_CHT_TWO_CLOCK
- depends on OR4_TRLX_RELAXED
- bool "2 clocks before"
-
-endchoice
-
-choice
- prompt "Reset setup time"
-
-config OR4_RST_THREE_QUARTER_CLOCK
- depends on OR4_TRLX_NORMAL
- bool "0.75 clocks prior"
-
-config OR4_RST_ONE_HALF_CLOCK
- depends on OR4_TRLX_RELAXED
- bool "0.5 clocks prior"
-
-config OR4_RST_ONE_CLOCK
- bool "1 clock prior"
-
-endchoice
-
-endif # BR4_MACHINE_FCM
-
-if BR4_MACHINE_UPM
-
-choice
- prompt "Burst inhibit"
-
-config OR4_BI_BURSTSUPPORT
- bool "Support burst access"
-
-config OR4_BI_BURSTINHIBIT
- bool "Inhibit burst access"
-
-endchoice
-
-endif # BR4_MACHINE_UPM
-
-if BR4_MACHINE_SDRAM
-
-choice
- prompt "Number of column address lines"
-
-config OR4_COLS_7
- bool "7"
-
-config OR4_COLS_8
- bool "8"
-
-config OR4_COLS_9
- bool "9"
-
-config OR4_COLS_10
- bool "10"
-
-config OR4_COLS_11
- bool "11"
-
-config OR4_COLS_12
- bool "12"
-
-config OR4_COLS_13
- bool "13"
-
-config OR4_COLS_14
- bool "14"
-
-endchoice
-
-choice
- prompt "Number of rows address lines"
-
-config OR4_ROWS_9
- bool "9"
-
-config OR4_ROWS_10
- bool "10"
-
-config OR4_ROWS_11
- bool "11"
-
-config OR4_ROWS_12
- bool "12"
-
-config OR4_ROWS_13
- bool "13"
-
-config OR4_ROWS_14
- bool "14"
-
-config OR4_ROWS_15
- bool "15"
-
-endchoice
-
-choice
- prompt "Page mode select"
-
-config OR4_PMSEL_BTB
- bool "Back-to-back"
-
-config OR4_PMSEL_KEPT_OPEN
- bool "Page kept open until page miss or refresh"
-
-endchoice
-
-endif # BR4_MACHINE_SDRAM
-
-choice
- prompt "Relaxed timing"
-
-config OR4_TRLX_NORMAL
- bool "Normal"
-
-config OR4_TRLX_RELAXED
- bool "Relaxed"
-
-endchoice
-
-choice
- prompt "Extended hold time"
-
-config OR4_EHTR_NORMAL
- depends on OR4_TRLX_NORMAL
- bool "Normal"
-
-config OR4_EHTR_1_CYCLE
- depends on OR4_TRLX_NORMAL
- bool "1 idle clock cycle inserted"
-
-config OR4_EHTR_4_CYCLE
- depends on OR4_TRLX_RELAXED
- bool "4 idle clock cycles inserted"
-
-config OR4_EHTR_8_CYCLE
- depends on OR4_TRLX_RELAXED
- bool "8 idle clock cycles inserted"
-
-endchoice
-
-if !ARCH_MPC8308
-
-choice
- prompt "External address latch delay"
-
-config OR4_EAD_NONE
- bool "None"
-
-config OR4_EAD_EXTRA
- bool "Extra"
-
-endchoice
-
-endif # !ARCH_MPC8308
-
-endif # ELBC_BR4_OR4
-
-config BR4_PORTSIZE
- hex
- default 0x800 if BR4_PORTSIZE_8BIT
- default 0x1000 if BR4_PORTSIZE_16BIT
- default 0x1800 if BR4_PORTSIZE_32BIT
-
-config BR4_ERRORCHECKING
- hex
- default 0x0 if !BR4_MACHINE_FCM
- default 0x0 if BR4_ERRORCHECKING_DISABLED
- default 0x200 if BR4_ERRORCHECKING_ECC_CHECKING
- default 0x400 if BR4_ERRORCHECKING_BOTH
-
-config BR4_WRITE_PROTECT_BIT
- hex
- default 0x0 if !BR4_WRITE_PROTECT
- default 0x100 if BR4_WRITE_PROTECT
-
-config BR4_MACHINE
- hex
- default 0x0 if BR4_MACHINE_GPCM
- default 0x20 if BR4_MACHINE_FCM
- default 0x60 if BR4_MACHINE_SDRAM
- default 0x80 if BR4_MACHINE_UPMA
- default 0xa0 if BR4_MACHINE_UPMB
- default 0xc0 if BR4_MACHINE_UPMC
-
-config BR4_ATOMIC
- hex
- default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
- default 0x0 if BR4_ATOMIC_NONE
- default 0x4 if BR4_ATOMIC_RAWA
- default 0x8 if BR4_ATOMIC_WARA
-
-config BR4_VALID_BIT
- hex
- default 0x0 if !ELBC_BR4_OR4
- default 0x1 if ELBC_BR4_OR4
-
-config OR4_AM
- hex
- default 0xffff8000 if OR4_AM_32_KBYTES && !BR4_MACHINE_SDRAM
- default 0xffff0000 if OR4_AM_64_KBYTES
- default 0xfffe0000 if OR4_AM_128_KBYTES
- default 0xfffc0000 if OR4_AM_256_KBYTES
- default 0xfff80000 if OR4_AM_512_KBYTES
- default 0xfff00000 if OR4_AM_1_MBYTES
- default 0xffe00000 if OR4_AM_2_MBYTES
- default 0xffc00000 if OR4_AM_4_MBYTES
- default 0xff800000 if OR4_AM_8_MBYTES
- default 0xff000000 if OR4_AM_16_MBYTES
- default 0xfe000000 if OR4_AM_32_MBYTES
- default 0xfc000000 if OR4_AM_64_MBYTES
- default 0xf8000000 if OR4_AM_128_MBYTES
- default 0xf0000000 if OR4_AM_256_MBYTES
- default 0xe0000000 if OR4_AM_512_MBYTES
- default 0xc0000000 if OR4_AM_1_GBYTES
- default 0x80000000 if OR4_AM_2_GBYTES
- default 0x00000000 if OR4_AM_4_GBYTES
-
-config OR4_XAM
- hex
- default 0x0 if !OR4_XAM_SET
- default 0x6000 if OR4_XAM_SET
-
-config OR4_BCTLD
- hex
- default 0x0 if OR4_BCTLD_ASSERTED
- default 0x1000 if OR4_BCTLD_NOT_ASSERTED
-
-config OR4_BI
- hex
- default 0x0 if !BR4_MACHINE_UPM
- default 0x0 if OR4_BI_BURSTSUPPORT
- default 0x100 if OR4_BI_BURSTINHIBIT
-
-config OR4_COLS
- hex
- default 0x0 if !BR4_MACHINE_SDRAM
- default 0x0 if OR4_COLS_7
- default 0x400 if OR4_COLS_8
- default 0x800 if OR4_COLS_9
- default 0xc00 if OR4_COLS_10
- default 0x1000 if OR4_COLS_11
- default 0x1400 if OR4_COLS_12
- default 0x1800 if OR4_COLS_13
- default 0x1c00 if OR4_COLS_14
-
-config OR4_ROWS
- hex
- default 0x0 if !BR4_MACHINE_SDRAM
- default 0x0 if OR4_ROWS_9
- default 0x40 if OR4_ROWS_10
- default 0x80 if OR4_ROWS_11
- default 0xc0 if OR4_ROWS_12
- default 0x100 if OR4_ROWS_13
- default 0x140 if OR4_ROWS_14
- default 0x180 if OR4_ROWS_15
-
-config OR4_PMSEL
- hex
- default 0x0 if !BR4_MACHINE_SDRAM
- default 0x0 if OR4_PMSEL_BTB
- default 0x20 if OR4_PMSEL_KEPT_OPEN
-
-config OR4_SCY
- hex
- default 0x0 if !BR4_MACHINE_GPCM && !BR4_MACHINE_FCM
- default 0x0 if OR4_SCY_0
- default 0x10 if OR4_SCY_1
- default 0x20 if OR4_SCY_2
- default 0x30 if OR4_SCY_3
- default 0x40 if OR4_SCY_4
- default 0x50 if OR4_SCY_5
- default 0x60 if OR4_SCY_6
- default 0x70 if OR4_SCY_7
- default 0x80 if OR4_SCY_8
- default 0x90 if OR4_SCY_9
- default 0xa0 if OR4_SCY_10
- default 0xb0 if OR4_SCY_11
- default 0xc0 if OR4_SCY_12
- default 0xd0 if OR4_SCY_13
- default 0xe0 if OR4_SCY_14
- default 0xf0 if OR4_SCY_15
-
-config OR4_PGS
- hex
- default 0x0 if !BR4_MACHINE_FCM
- default 0x0 if OR4_PGS_SMALL
- default 0x400 if OR4_PGS_LARGE
-
-config OR4_CSCT
- hex
- default 0x0 if !BR4_MACHINE_FCM
- default 0x0 if OR4_CSCT_1_CYCLE
- default 0x0 if OR4_CSCT_2_CYCLE
- default 0x200 if OR4_CSCT_4_CYCLE
- default 0x200 if OR4_CSCT_8_CYCLE
-
-config OR4_CST
- hex
- default 0x0 if !BR4_MACHINE_FCM
- default 0x0 if OR4_CST_COINCIDENT
- default 0x100 if OR4_CST_QUARTER_CLOCK
- default 0x0 if OR4_CST_HALF_CLOCK
- default 0x100 if OR4_CST_ONE_CLOCK
-
-config OR4_CHT
- hex
- default 0x0 if !BR4_MACHINE_FCM
- default 0x0 if OR4_CHT_HALF_CLOCK
- default 0x80 if OR4_CHT_ONE_CLOCK
- default 0x0 if OR4_CHT_ONE_HALF_CLOCK
- default 0x80 if OR4_CHT_TWO_CLOCK
-
-config OR4_RST
- hex
- default 0x0 if !BR4_MACHINE_FCM
- default 0x0 if OR4_RST_THREE_QUARTER_CLOCK
- default 0x8 if OR4_RST_ONE_CLOCK
- default 0x0 if OR4_RST_ONE_HALF_CLOCK
-
-config OR4_CSNT
- hex
- default 0x0 if !BR4_MACHINE_GPCM
- default 0x0 if OR4_CSNT_NORMAL
- default 0x800 if OR4_CSNT_EARLIER
-
-config OR4_ACS
- hex
- default 0x0 if !BR4_MACHINE_GPCM
- default 0x0 if OR4_ACS_SAME_TIME
- default 0x400 if OR4_ACS_QUARTER_CYCLE_EARLIER
- default 0x600 if OR4_ACS_HALF_CYCLE_EARLIER
-
-config OR4_XACS
- hex
- default 0x0 if !BR4_MACHINE_GPCM
- default 0x0 if OR4_XACS_NORMAL
- default 0x100 if OR4_XACS_EXTENDED
-
-config OR4_SETA
- hex
- default 0x0 if !BR4_MACHINE_GPCM
- default 0x0 if OR4_SETA_INTERNAL
- default 0x8 if OR4_SETA_EXTERNAL
-
-config OR4_TRLX
- hex
- default 0x0 if OR4_TRLX_NORMAL
- default 0x4 if OR4_TRLX_RELAXED
-
-config OR4_EHTR
- hex
- default 0x0 if OR4_EHTR_NORMAL
- default 0x2 if OR4_EHTR_1_CYCLE
- default 0x0 if OR4_EHTR_4_CYCLE
- default 0x2 if OR4_EHTR_8_CYCLE
-
-config OR4_EAD
- hex
- default 0x0 if ARCH_MPC8308
- default 0x0 if OR4_EAD_NONE
- default 0x1 if OR4_EAD_EXTRA
diff --git a/arch/riscv/lib/semihosting.S b/arch/riscv/lib/semihosting.S
new file mode 100644
index 0000000..c0c571b
--- /dev/null
+++ b/arch/riscv/lib/semihosting.S
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 Ventana Micro Systems Inc.
+ */
+
+#include <asm/asm.h>
+#include <linux/linkage.h>
+
+.pushsection .text.smh_trap, "ax"
+ENTRY(smh_trap)
+ .align 2
+ .option push
+ .option norvc /* semihosting sequence must be 32-bit wide */
+
+ slli zero, zero, 0x1f /* Entry NOP to identify semihosting */
+ ebreak
+ srai zero, zero, 7 /* NOP encoding of semihosting call number */
+ .option pop
+
+ ret
+ENDPROC(smh_trap)
+.popsection
diff --git a/arch/riscv/lib/semihosting.c b/arch/riscv/lib/semihosting.c
deleted file mode 100644
index d6593b0..0000000
--- a/arch/riscv/lib/semihosting.c
+++ /dev/null
@@ -1,24 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2022 Ventana Micro Systems Inc.
- */
-
-#include <common.h>
-
-long smh_trap(int sysnum, void *addr)
-{
- register int ret asm ("a0") = sysnum;
- register void *param0 asm ("a1") = addr;
-
- asm volatile (".align 4\n"
- ".option push\n"
- ".option norvc\n"
-
- "slli zero, zero, 0x1f\n"
- "ebreak\n"
- "srai zero, zero, 7\n"
- ".option pop\n"
- : "+r" (ret) : "r" (param0) : "memory");
-
- return ret;
-}
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 7287ca6..8f3f54c 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -108,37 +108,6 @@
CONFIG_LBLAW2_BASE=0xF0000000
CONFIG_LBLAW2_NAME="VSC7385"
CONFIG_LBLAW2_LENGTH_128_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_SCY_9=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_EHTR_1_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="NAND"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_ERRORCHECKING_BOTH=y
-CONFIG_BR1_MACHINE_FCM=y
-CONFIG_OR1_SCY_1=y
-CONFIG_OR1_CSCT_8_CYCLE=y
-CONFIG_OR1_CST_ONE_CLOCK=y
-CONFIG_OR1_CHT_TWO_CLOCK=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="VSC7385"
-CONFIG_BR2_OR2_BASE=0xF0000000
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_SETA_EXTERNAL=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 597b771..32e022f 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -13,6 +13,8 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_LDSCRIPT="arch/arm/mach-aspeed/ast2600/u-boot-spl.lds"
CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ast2600-evb"
CONFIG_DM_RESET=y
@@ -74,6 +76,8 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE_AUTO=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig
index 63051af..63488da 100644
--- a/configs/gazerbeam_defconfig
+++ b/configs/gazerbeam_defconfig
@@ -67,31 +67,6 @@
CONFIG_LBLAW2_BASE=0xE0700000
CONFIG_LBLAW2_NAME="FPGA1"
CONFIG_LBLAW2_LENGTH_1_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="FPGA0"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_PORTSIZE_16BIT=y
-CONFIG_OR1_AM_1_MBYTES=y
-CONFIG_OR1_SCY_5=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="FPGA1"
-CONFIG_BR2_OR2_BASE=0xE0700000
-CONFIG_BR2_PORTSIZE_16BIT=y
-CONFIG_OR2_AM_1_MBYTES=y
-CONFIG_OR2_SCY_5=y
-CONFIG_OR2_CSNT_EARLIER=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_DPM=y
CONFIG_HID0_FINAL_ICE=y
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 7490313..e33b3f1 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
@@ -32,7 +33,7 @@
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 00ec48b..94a6523 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x70000
CONFIG_SPL_GPIO=y
@@ -27,7 +28,6 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
-CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0xc0000
diff --git a/configs/j7200_hs_evm_a72_defconfig b/configs/j7200_hs_evm_a72_defconfig
deleted file mode 100644
index e4f3c46..0000000
--- a/configs/j7200_hs_evm_a72_defconfig
+++ /dev/null
@@ -1,204 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SOC_K3_J721E=y
-CONFIG_TARGET_J7200_A72_EVM=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x680000
-CONFIG_DM_GPIO=y
-CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-common-proc-board"
-CONFIG_SPL_TEXT_BASE=0x80080000
-CONFIG_DM_RESET=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_ENV_OFFSET_REDUND=0x6A0000
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-# CONFIG_PSCI_RESET is not set
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
-CONFIG_LOGLEVEL=7
-CONFIG_SPL_MAX_SIZE=0xc0000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x80a00000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
-CONFIG_SPL_DMA=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_I2C=y
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-# CONFIG_SPL_SPI_FLASH_TINY is not set
-CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_REMOTEPROC=y
-CONFIG_CMD_UFS=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)"
-CONFIG_CMD_UBI=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
-CONFIG_CLK_CCF=y
-CONFIG_CLK_TI_SCI=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_DFU_SF=y
-CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
-CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
-CONFIG_DMA_CHANNELS=y
-CONFIG_TI_K3_NAVSS_UDMA=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_TI_SCI_PROTOCOL=y
-CONFIG_DA8XX_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_DM_I2C_GPIO=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_DM_MAILBOX=y
-CONFIG_K3_SEC_PROXY=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_SPL_MMC_HS400_SUPPORT=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ADMA=y
-CONFIG_SPL_MMC_SDHCI_ADMA=y
-CONFIG_MMC_SDHCI_AM654=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_SHOW_PROGRESS=0
-CONFIG_CFI_FLASH=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_HBMC_AM654=y
-CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_MULTIPLEXER=y
-CONFIG_MUX_MMIO=y
-CONFIG_PHY_FIXED=y
-CONFIG_TI_AM65_CPSW_NUSS=y
-CONFIG_PHY=y
-CONFIG_SPL_PHY=y
-CONFIG_PHY_CADENCE_TORRENT=y
-CONFIG_PHY_J721E_WIZ=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_GENERIC is not set
-CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_GENERIC is not set
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_RAM=y
-CONFIG_SPL_RAM=y
-CONFIG_REMOTEPROC_TI_K3_R5F=y
-CONFIG_RESET_TI_SCI=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SOC_DEVICE=y
-CONFIG_SOC_DEVICE_TI_K3=y
-CONFIG_SOC_TI=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_HAS_CQSPI_REF_CLK=y
-CONFIG_CQSPI_REF_CLK=133333333
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_TI_SCI=y
-CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
-CONFIG_SPL_DM_USB_GADGET=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_CDNS3=y
-CONFIG_USB_CDNS3_GADGET=y
-CONFIG_USB_CDNS3_HOST=y
-CONFIG_SPL_USB_CDNS3_GADGET=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
-CONFIG_UFS=y
-CONFIG_CADENCE_UFS=y
-CONFIG_TI_J721E_UFS=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/j7200_hs_evm_r5_defconfig b/configs/j7200_hs_evm_r5_defconfig
deleted file mode 100644
index 94a6523..0000000
--- a/configs/j7200_hs_evm_r5_defconfig
+++ /dev/null
@@ -1,170 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x70000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SOC_K3_J721E=y
-CONFIG_K3_EARLY_CONS=y
-CONFIG_TARGET_J7200_R5_EVM=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf5bfc
-CONFIG_ENV_SIZE=0x20000
-CONFIG_DM_GPIO=y
-CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-r5-common-proc-board"
-CONFIG_SPL_TEXT_BASE=0x41c00000
-CONFIG_DM_RESET=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
-CONFIG_USE_BOOTCOMMAND=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_MAX_SIZE=0xc0000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x41cf5bfc
-CONFIG_SPL_BSS_MAX_SIZE=0xa000
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
-CONFIG_SPL_EARLY_BSS=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
-CONFIG_SPL_DMA=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_FS_EXT4=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
-# CONFIG_SPL_SPI_FLASH_TINY is not set
-CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x4000000
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
-CONFIG_SPL_CLK_CCF=y
-CONFIG_SPL_CLK_K3_PLL=y
-CONFIG_SPL_CLK_K3=y
-CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
-CONFIG_DMA_CHANNELS=y
-CONFIG_TI_K3_NAVSS_UDMA=y
-CONFIG_TI_SCI_PROTOCOL=y
-CONFIG_DA8XX_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_DM_MAILBOX=y
-CONFIG_K3_SEC_PROXY=y
-CONFIG_FS_LOADER=y
-CONFIG_SPL_FS_LOADER=y
-CONFIG_K3_AVS0=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_SPL_MMC_HS400_SUPPORT=y
-CONFIG_MMC_SDHCI=y
-CONFIG_SPL_MMC_SDHCI_ADMA=y
-CONFIG_MMC_SDHCI_AM654=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_SHOW_PROGRESS=0
-CONFIG_CFI_FLASH=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_HBMC_AM654=y
-CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_GENERIC is not set
-CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_GENERIC is not set
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_TI_POWER_DOMAIN=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_TPS65941=y
-CONFIG_DM_REGULATOR=y
-CONFIG_SPL_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_TPS65941=y
-CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
-CONFIG_RESET_TI_SCI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SOC_DEVICE=y
-CONFIG_SOC_DEVICE_TI_K3=y
-CONFIG_SOC_TI=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_HAS_CQSPI_REF_CLK=y
-CONFIG_CQSPI_REF_CLK=133333333
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_TI_SCI=y
-CONFIG_TIMER=y
-CONFIG_SPL_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
-CONFIG_SPL_DM_USB_GADGET=y
-CONFIG_USB_CDNS3=y
-CONFIG_USB_CDNS3_GADGET=y
-CONFIG_SPL_USB_CDNS3_GADGET=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_FS_EXT4=y
-CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
-CONFIG_LIB_RATIONAL=y
-CONFIG_SPL_LIB_RATIONAL=y
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index eae4c10..44f22d5 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
@@ -30,7 +31,7 @@
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index 343e3c1..4ddbe8f 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
@@ -29,7 +30,6 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
-CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
diff --git a/configs/j721s2_hs_evm_a72_defconfig b/configs/j721s2_hs_evm_a72_defconfig
deleted file mode 100644
index dff12ab..0000000
--- a/configs/j721s2_hs_evm_a72_defconfig
+++ /dev/null
@@ -1,212 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SOC_K3_J721S2=y
-CONFIG_TARGET_J721S2_A72_EVM=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x680000
-CONFIG_DM_GPIO=y
-CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-common-proc-board"
-CONFIG_SPL_TEXT_BASE=0x80080000
-CONFIG_DM_RESET=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_ENV_OFFSET_REDUND=0x6A0000
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-# CONFIG_PSCI_RESET is not set
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
-CONFIG_LOGLEVEL=7
-CONFIG_SPL_MAX_SIZE=0xc0000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x80a00000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
-CONFIG_SPL_DMA=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_I2C=y
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-# CONFIG_SPL_SPI_FLASH_TINY is not set
-CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
-CONFIG_SPL_THERMAL=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_REMOTEPROC=y
-CONFIG_CMD_UFS=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),-@8m(hbmc.rootfs)"
-CONFIG_CMD_UBI=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
-CONFIG_CLK_CCF=y
-CONFIG_CLK_TI_SCI=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_DFU_SF=y
-CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
-CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
-CONFIG_DMA_CHANNELS=y
-CONFIG_TI_K3_NAVSS_UDMA=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_TI_SCI_PROTOCOL=y
-CONFIG_DA8XX_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_DM_I2C_GPIO=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_DM_MAILBOX=y
-CONFIG_K3_SEC_PROXY=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_SPL_MMC_HS400_SUPPORT=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ADMA=y
-CONFIG_SPL_MMC_SDHCI_ADMA=y
-CONFIG_MMC_SDHCI_AM654=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_SHOW_PROGRESS=0
-CONFIG_CFI_FLASH=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPI_FLASH_SOFT_RESET=y
-CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_MT35XU=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_MULTIPLEXER=y
-CONFIG_MUX_MMIO=y
-CONFIG_PHY_TI_DP83867=y
-CONFIG_PHY_FIXED=y
-CONFIG_TI_AM65_CPSW_NUSS=y
-CONFIG_PHY=y
-CONFIG_SPL_PHY=y
-CONFIG_PHY_CADENCE_TORRENT=y
-CONFIG_PHY_J721E_WIZ=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_GENERIC is not set
-CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_GENERIC is not set
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_RAM=y
-CONFIG_SPL_RAM=y
-CONFIG_REMOTEPROC_TI_K3_DSP=y
-CONFIG_REMOTEPROC_TI_K3_R5F=y
-CONFIG_RESET_TI_SCI=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SOC_DEVICE=y
-CONFIG_SOC_DEVICE_TI_K3=y
-CONFIG_SOC_TI=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_HAS_CQSPI_REF_CLK=y
-CONFIG_CQSPI_REF_CLK=133333333
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_TI_SCI=y
-CONFIG_DM_THERMAL=y
-CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
-CONFIG_SPL_DM_USB_GADGET=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_CDNS3=y
-CONFIG_USB_CDNS3_GADGET=y
-CONFIG_USB_CDNS3_HOST=y
-CONFIG_SPL_USB_CDNS3_GADGET=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
-CONFIG_UFS=y
-CONFIG_CADENCE_UFS=y
-CONFIG_TI_J721E_UFS=y
-CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/j721s2_hs_evm_r5_defconfig b/configs/j721s2_hs_evm_r5_defconfig
deleted file mode 100644
index c8433a1..0000000
--- a/configs/j721s2_hs_evm_r5_defconfig
+++ /dev/null
@@ -1,175 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x10000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SOC_K3_J721S2=y
-CONFIG_K3_EARLY_CONS=y
-CONFIG_TARGET_J721S2_R5_EVM=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_DM_GPIO=y
-CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-r5-common-proc-board"
-CONFIG_SPL_TEXT_BASE=0x41c00000
-CONFIG_DM_RESET=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_SIZE_LIMIT=0x80000
-CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
-CONFIG_USE_BOOTCOMMAND=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
-CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
-CONFIG_SPL_MAX_SIZE=0xc0000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x41c76000
-CONFIG_SPL_BSS_MAX_SIZE=0xa000
-CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
-CONFIG_SPL_EARLY_BSS=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
-CONFIG_SPL_DMA=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_FS_EXT4=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
-# CONFIG_SPL_SPI_FLASH_TINY is not set
-CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_THERMAL=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x4000000
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
-CONFIG_SPL_CLK_CCF=y
-CONFIG_SPL_CLK_K3_PLL=y
-CONFIG_SPL_CLK_K3=y
-CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
-CONFIG_DMA_CHANNELS=y
-CONFIG_TI_K3_NAVSS_UDMA=y
-CONFIG_TI_SCI_PROTOCOL=y
-CONFIG_DA8XX_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_DM_MAILBOX=y
-CONFIG_K3_SEC_PROXY=y
-CONFIG_FS_LOADER=y
-CONFIG_SPL_FS_LOADER=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_SPL_MMC_HS400_SUPPORT=y
-CONFIG_MMC_SDHCI=y
-CONFIG_SPL_MMC_SDHCI_ADMA=y
-CONFIG_MMC_SDHCI_AM654=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_SHOW_PROGRESS=0
-CONFIG_CFI_FLASH=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPI_FLASH_SOFT_RESET=y
-CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_MT35XU=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_GENERIC is not set
-CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_GENERIC is not set
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_TI_POWER_DOMAIN=y
-CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
-CONFIG_RESET_TI_SCI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SOC_DEVICE=y
-CONFIG_SOC_DEVICE_TI_K3=y
-CONFIG_SOC_TI=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_HAS_CQSPI_REF_CLK=y
-CONFIG_CQSPI_REF_CLK=133333333
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_TI_SCI=y
-CONFIG_DM_THERMAL=y
-CONFIG_TIMER=y
-CONFIG_SPL_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
-CONFIG_SPL_DM_USB_GADGET=y
-CONFIG_USB_CDNS3=y
-CONFIG_USB_CDNS3_GADGET=y
-CONFIG_SPL_USB_CDNS3_GADGET=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_FS_EXT4=y
-CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
-CONFIG_PANIC_HANG=y
-CONFIG_LIB_RATIONAL=y
-CONFIG_SPL_LIB_RATIONAL=y
diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index 4ea7da8..40e2b22 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig
@@ -111,43 +111,6 @@
CONFIG_LBLAW3_BASE=0xA0000000
CONFIG_LBLAW3_NAME="PAXE"
CONFIG_LBLAW3_LENGTH_512_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_OR1_AM_64_MBYTES=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PAXE"
-CONFIG_BR3_OR3_BASE=0xA0000000
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_SCY_2=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_ELBC_BR4_OR4=y
-CONFIG_BR4_OR4_NAME="BFTIC3"
-CONFIG_BR4_OR4_BASE=0xB0000000
-CONFIG_OR4_AM_256_MBYTES=y
-CONFIG_OR4_SCY_2=y
-CONFIG_OR4_CSNT_EARLIER=y
-CONFIG_OR4_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR4_TRLX_RELAXED=y
-CONFIG_OR4_EAD_EXTRA=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index 96298ed..f493675 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig
@@ -91,34 +91,6 @@
CONFIG_LBLAW3_BASE=0xA0000000
CONFIG_LBLAW3_NAME="PAXE"
CONFIG_LBLAW3_LENGTH_512_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_OR1_AM_64_MBYTES=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PAXE"
-CONFIG_BR3_OR3_BASE=0xA0000000
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_SCY_2=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EAD_EXTRA=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index db717e4..9a1b6b8 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig
@@ -99,40 +99,6 @@
CONFIG_LBLAW3_BASE=0xB0000000
CONFIG_LBLAW3_NAME="APP2"
CONFIG_LBLAW3_LENGTH_256_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_OR2_SCY_2=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="APP2"
-CONFIG_BR3_OR3_BASE=0xB0000000
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_SCY_4=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index 69de685..cafe39a 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig
@@ -85,34 +85,6 @@
CONFIG_LBLAW2_BASE=0xA0000000
CONFIG_LBLAW2_NAME="APP1"
CONFIG_LBLAW2_LENGTH_256_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_OR2_SCY_2=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EAD_EXTRA=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index 92f2b0a..0b88ebd 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig
@@ -99,40 +99,6 @@
CONFIG_LBLAW3_BASE=0xB0000000
CONFIG_LBLAW3_NAME="APP2"
CONFIG_LBLAW3_LENGTH_256_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_OR2_SCY_2=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="APP2"
-CONFIG_BR3_OR3_BASE=0xB0000000
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_SCY_4=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index 0c33814..6df74b5 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig
@@ -85,34 +85,6 @@
CONFIG_LBLAW2_BASE=0xA0000000
CONFIG_LBLAW2_NAME="APP1"
CONFIG_LBLAW2_LENGTH_256_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_OR2_SCY_2=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EAD_EXTRA=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index 4f192ad..837098f 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig
@@ -99,42 +99,6 @@
CONFIG_LBLAW3_BASE=0xB0000000
CONFIG_LBLAW3_NAME="APP2"
CONFIG_LBLAW3_LENGTH_256_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_OR2_SCY_2=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="APP2"
-CONFIG_BR3_OR3_BASE=0xB0000000
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_SCY_2=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR3_TRLX_RELAXED=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
index 0df1dc3..e5ada5b 100644
--- a/drivers/clk/aspeed/clk_ast2600.c
+++ b/drivers/clk/aspeed/clk_ast2600.c
@@ -538,7 +538,7 @@
}
p_cfg->reg.b.bypass = 0;
- p_cfg->reg.b.off = 1;
+ p_cfg->reg.b.off = 0;
p_cfg->reg.b.reset = 1;
reg = readl(addr);
@@ -549,7 +549,6 @@
/* write extend parameter */
writel(p_cfg->ext_reg, addr_ext);
udelay(100);
- p_cfg->reg.b.off = 0;
p_cfg->reg.b.reset = 0;
reg &= ~GENMASK(25, 0);
reg |= p_cfg->reg.w;
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 878f867..80641e1 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -667,18 +667,6 @@
If unsure, say N.
-config MMC_SDHCI_SPEAR
- bool "SDHCI support on ST SPEAr platform"
- depends on MMC_SDHCI
- help
- This selects the Secure Digital Host Controller Interface (SDHCI)
- often referrered to as the HSMMC block in some of the ST SPEAR range
- of SoC
-
- If you have a controller with this interface, say Y here.
-
- If unsure, say N.
-
config MMC_SDHCI_STI
bool "SDHCI support for STMicroelectronics SoC"
depends on MMC_SDHCI && OF_CONTROL
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 3dc7571..2c65c47 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -70,7 +70,6 @@
obj-$(CONFIG_MMC_SDHCI_PIC32) += pic32_sdhci.o
obj-$(CONFIG_MMC_SDHCI_ROCKCHIP) += rockchip_sdhci.o
obj-$(CONFIG_MMC_SDHCI_S5P) += s5p_sdhci.o
-obj-$(CONFIG_MMC_SDHCI_SPEAR) += spear_sdhci.o
obj-$(CONFIG_MMC_SDHCI_STI) += sti_sdhci.o
obj-$(CONFIG_MMC_SDHCI_TANGIER) += tangier_sdhci.o
obj-$(CONFIG_MMC_SDHCI_TEGRA) += tegra_mmc.o
diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c
index 1876755..d463933 100644
--- a/drivers/ram/aspeed/sdram_ast2600.c
+++ b/drivers/ram/aspeed/sdram_ast2600.c
@@ -1089,13 +1089,13 @@
}
reg = readl(&priv->scu->mpll);
- reg &= ~(SCU_PLL_BYPASS | SCU_PLL_DIV_MASK |
+ reg &= ~(SCU_PLL_BYPASS | SCU_PLL_OFF | SCU_PLL_DIV_MASK |
SCU_PLL_DENUM_MASK | SCU_PLL_NUM_MASK);
- reg |= (SCU_PLL_RST | SCU_PLL_OFF | SCU_MPLL_FREQ_CFG);
+ reg |= (SCU_PLL_RST | SCU_MPLL_FREQ_CFG);
writel(reg, &priv->scu->mpll);
writel(SCU_MPLL_EXT_CFG, &priv->scu->mpll_ext);
udelay(100);
- reg &= ~(SCU_PLL_RST | SCU_PLL_OFF);
+ reg &= ~SCU_PLL_RST;
writel(reg, &priv->scu->mpll);
while ((readl(&priv->scu->mpll_ext) & BIT(31)) == 0)
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index f32bd16..915b2af 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -145,6 +145,13 @@
Enables support for the Designware APB Timer driver. This timer is
present on Altera SoCFPGA SoCs.
+config FTTMR010_TIMER
+ bool "Faraday Technology timer support"
+ depends on TIMER
+ help
+ Select this to enable support for the timer found on
+ devices using Faraday Technology's IP.
+
config GXP_TIMER
bool "HPE GXP Timer"
depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 3c92113..cdc20f5 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -13,6 +13,7 @@
obj-$(CONFIG_$(SPL_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o
obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
+obj-$(CONFIG_FTTMR010_TIMER) += fttmr010_timer.o
obj-$(CONFIG_GXP_TIMER) += gxp-timer.o
obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
obj-$(CONFIG_NOMADIK_MTU_TIMER) += nomadik-mtu-timer.o
diff --git a/drivers/timer/fttmr010_timer.c b/drivers/timer/fttmr010_timer.c
new file mode 100644
index 0000000..b6289e6
--- /dev/null
+++ b/drivers/timer/fttmr010_timer.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * 23/08/2022 Port to DM
+ */
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <timer.h>
+#include <asm/io.h>
+#include <dm/ofnode.h>
+#include <faraday/fttmr010.h>
+#include <asm/global_data.h>
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+struct fttmr010_timer_priv {
+ struct fttmr010 __iomem *regs;
+};
+
+static u64 fttmr010_timer_get_count(struct udevice *dev)
+{
+ struct fttmr010_timer_priv *priv = dev_get_priv(dev);
+ struct fttmr010 *tmr = priv->regs;
+ u32 now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
+
+ /* increment tbu if tbl has rolled over */
+ if (now < gd->arch.tbl)
+ gd->arch.tbu++;
+ gd->arch.tbl = now;
+
+ return ((u64)gd->arch.tbu << 32) | gd->arch.tbl;
+}
+
+static int fttmr010_timer_probe(struct udevice *dev)
+{
+ struct fttmr010_timer_priv *priv = dev_get_priv(dev);
+ struct fttmr010 *tmr;
+ unsigned int cr;
+
+ priv->regs = dev_read_addr_ptr(dev);
+ if (!priv->regs)
+ return -EINVAL;
+ tmr = priv->regs;
+
+ debug("Faraday FTTMR010 timer revision 0x%08X\n", readl(&tmr->revision));
+
+ /* disable timers */
+ writel(0, &tmr->cr);
+
+ /* setup timer */
+ writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+ writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+ writel(0, &tmr->timer3_match1);
+ writel(0, &tmr->timer3_match2);
+
+ /* we don't want timer to issue interrupts */
+ writel(FTTMR010_TM3_MATCH1 |
+ FTTMR010_TM3_MATCH2 |
+ FTTMR010_TM3_OVERFLOW,
+ &tmr->interrupt_mask);
+
+ cr = readl(&tmr->cr);
+ cr |= FTTMR010_TM3_CLOCK; /* use external clock */
+ cr |= FTTMR010_TM3_ENABLE;
+ writel(cr, &tmr->cr);
+
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+
+ return 0;
+}
+
+static const struct timer_ops fttmr010_timer_ops = {
+ .get_count = fttmr010_timer_get_count,
+};
+
+static const struct udevice_id fttmr010_timer_ids[] = {
+ { .compatible = "faraday,fttmr010-timer" },
+ {}
+};
+
+U_BOOT_DRIVER(fttmr010_timer) = {
+ .name = "fttmr010_timer",
+ .id = UCLASS_TIMER,
+ .of_match = fttmr010_timer_ids,
+ .priv_auto = sizeof(struct fttmr010_timer_priv),
+ .probe = fttmr010_timer_probe,
+ .ops = &fttmr010_timer_ops,
+};
diff --git a/include/faraday/fttmr010.h b/include/faraday/fttmr010.h
index ec1c989..5b1bef3 100644
--- a/include/faraday/fttmr010.h
+++ b/include/faraday/fttmr010.h
@@ -26,6 +26,7 @@
unsigned int cr; /* 0x30 */
unsigned int interrupt_state; /* 0x34 */
unsigned int interrupt_mask; /* 0x38 */
+ unsigned int revision; /* 0x3c */
};
/*