diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 935b2f1..35f50f4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -449,7 +449,6 @@
 	am4372-generic.dtb \
 	am437x-cm-t43.dtb
 dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb
-dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
 dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
diff --git a/arch/arm/dts/dm8168-evm-u-boot.dtsi b/arch/arm/dts/dm8168-evm-u-boot.dtsi
deleted file mode 100644
index f939df2..0000000
--- a/arch/arm/dts/dm8168-evm-u-boot.dtsi
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * dm8168-evm U-Boot Additions
- *
- * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
- */
-
-/ {
-	ocp {
-		bootph-all;
-	};
-};
diff --git a/arch/arm/dts/dm8168-evm.dts b/arch/arm/dts/dm8168-evm.dts
deleted file mode 100644
index 70255ab..0000000
--- a/arch/arm/dts/dm8168-evm.dts
+++ /dev/null
@@ -1,171 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/dts-v1/;
-
-#include "dm816x.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	model = "DM8168 EVM";
-	compatible = "ti,dm8168-evm", "ti,dm8168";
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x80000000 0x40000000	/* 1 GB */
-		       0xc0000000 0x40000000>;	/* 1 GB */
-	};
-
-	/* FDC6331L controlled by SD_POW pin */
-	vmmcsd_fixed: fixedregulator0 {
-		compatible = "regulator-fixed";
-		regulator-name = "vmmcsd_fixed";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-};
-
-&dm816x_pinmux {
-	mcspi1_pins: pinmux_mcspi1_pins {
-		pinctrl-single,pins = <
-			DM816X_IOPAD(0x0a94, MUX_MODE0)			/* SPI_SCLK */
-			DM816X_IOPAD(0x0a98, MUX_MODE0)			/* SPI_SCS0 */
-			DM816X_IOPAD(0x0aa8, MUX_MODE0)			/* SPI_D0 */
-			DM816X_IOPAD(0x0aac, MUX_MODE0)			/* SPI_D1 */
-		>;
-	};
-
-	mmc_pins: pinmux_mmc_pins {
-		pinctrl-single,pins = <
-			DM816X_IOPAD(0x0a70, MUX_MODE0)			/* SD_POW */
-			DM816X_IOPAD(0x0a74, MUX_MODE0)			/* SD_CLK */
-			DM816X_IOPAD(0x0a78, MUX_MODE0)			/* SD_CMD */
-			DM816X_IOPAD(0x0a7C, MUX_MODE0)			/* SD_DAT0 */
-			DM816X_IOPAD(0x0a80, MUX_MODE0)			/* SD_DAT1 */
-			DM816X_IOPAD(0x0a84, MUX_MODE0)			/* SD_DAT2 */
-			DM816X_IOPAD(0x0a88, MUX_MODE0)			/* SD_DAT2 */
-			DM816X_IOPAD(0x0a8c, MUX_MODE2)			/* GP1[7] */
-			DM816X_IOPAD(0x0a90, MUX_MODE2)			/* GP1[8] */
-		>;
-	};
-
-	usb0_pins: pinmux_usb0_pins {
-		pinctrl-single,pins = <
-			DM816X_IOPAD(0x0d04, MUX_MODE0)			/* USB0_DRVVBUS */
-		>;
-	};
-
-	usb1_pins: pinmux_usb1_pins {
-		pinctrl-single,pins = <
-			DM816X_IOPAD(0x0d08, MUX_MODE0)			/* USB1_DRVVBUS */
-		>;
-	};
-};
-
-&i2c1 {
-	extgpio0: pcf8575@20 {
-		compatible = "nxp,pcf8575";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-};
-
-&i2c2 {
-	extgpio1: pcf8575@20 {
-		compatible = "nxp,pcf8575";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-};
-
-&gpmc {
-	ranges = <0 0 0x04000000 0x01000000>;	/* CS0: 16MB for NAND */
-
-	nand@0,0 {
-		compatible = "ti,omap2-nand";
-		linux,mtd-name= "micron,mt29f2g16aadwp";
-		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
-		interrupt-parent = <&gpmc>;
-		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
-			     <1 IRQ_TYPE_NONE>; /* termcount */
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ti,nand-ecc-opt = "bch8";
-		nand-bus-width = <16>;
-		gpmc,device-width = <2>;
-		gpmc,sync-clk-ps = <0>;
-		gpmc,cs-on-ns = <0>;
-		gpmc,cs-rd-off-ns = <44>;
-		gpmc,cs-wr-off-ns = <44>;
-		gpmc,adv-on-ns = <6>;
-		gpmc,adv-rd-off-ns = <34>;
-		gpmc,adv-wr-off-ns = <44>;
-		gpmc,we-on-ns = <0>;
-		gpmc,we-off-ns = <40>;
-		gpmc,oe-on-ns = <0>;
-		gpmc,oe-off-ns = <54>;
-		gpmc,access-ns = <64>;
-		gpmc,rd-cycle-ns = <82>;
-		gpmc,wr-cycle-ns = <82>;
-		gpmc,bus-turnaround-ns = <0>;
-		gpmc,cycle2cycle-delay-ns = <0>;
-		gpmc,clk-activation-ns = <0>;
-		gpmc,wr-access-ns = <40>;
-		gpmc,wr-data-mux-bus-ns = <0>;
-		partition@0 {
-			label = "X-Loader";
-			reg = <0 0x80000>;
-		};
-		partition@80000 {
-			label = "U-Boot";
-			reg = <0x80000 0x1c0000>;
-		};
-		partition@1c0000 {
-			label = "Environment";
-			reg = <0x240000 0x40000>;
-		};
-		partition@280000 {
-			label = "Kernel";
-			reg = <0x280000 0x500000>;
-		};
-		partition@780000 {
-			label = "Filesystem";
-			reg = <0x780000 0xf880000>;
-		};
-	};
-};
-
-&mcspi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcspi1_pins>;
-
-	flash@0 {
-		compatible = "w25x32";
-		spi-max-frequency = <48000000>;
-		reg = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-};
-
-&mmc1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc_pins>;
-	vmmc-supply = <&vmmcsd_fixed>;
-	bus-width = <4>;
-	cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
-	wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
-};
-
-/* At least dm8168-evm rev c won't support multipoint, later may */
-&usb0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb0_pins>;
-	mentor,multipoint = <0>;
-};
-
-&usb1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb1_pins>;
-	mentor,multipoint = <0>;
-};
diff --git a/arch/arm/dts/dm816x-clocks.dtsi b/arch/arm/dts/dm816x-clocks.dtsi
deleted file mode 100644
index f7a839d..0000000
--- a/arch/arm/dts/dm816x-clocks.dtsi
+++ /dev/null
@@ -1,246 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-&scrm {
-	main_fapll: main_fapll {
-		#clock-cells = <1>;
-		compatible = "ti,dm816-fapll-clock";
-		reg = <0x400 0x40>;
-		clocks = <&sys_clkin_ck &sys_clkin_ck>;
-		clock-indices = <1>, <2>, <3>, <4>, <5>,
-				<6>, <7>;
-		clock-output-names = "main_pll_clk1",
-				     "main_pll_clk2",
-				     "main_pll_clk3",
-				     "main_pll_clk4",
-				     "main_pll_clk5",
-				     "main_pll_clk6",
-				     "main_pll_clk7";
-	};
-
-	ddr_fapll: ddr_fapll {
-		#clock-cells = <1>;
-		compatible = "ti,dm816-fapll-clock";
-		reg = <0x440 0x30>;
-		clocks = <&sys_clkin_ck &sys_clkin_ck>;
-		clock-indices = <1>, <2>, <3>, <4>;
-		clock-output-names = "ddr_pll_clk1",
-				     "ddr_pll_clk2",
-				     "ddr_pll_clk3",
-				     "ddr_pll_clk4";
-	};
-
-	video_fapll: video_fapll {
-		#clock-cells = <1>;
-		compatible = "ti,dm816-fapll-clock";
-		reg = <0x470 0x30>;
-		clocks = <&sys_clkin_ck &sys_clkin_ck>;
-		clock-indices = <1>, <2>, <3>;
-		clock-output-names = "video_pll_clk1",
-				     "video_pll_clk2",
-				     "video_pll_clk3";
-	};
-
-	audio_fapll: audio_fapll {
-		#clock-cells = <1>;
-		compatible = "ti,dm816-fapll-clock";
-		reg = <0x4a0 0x30>;
-		clocks = <&main_fapll 7>, < &sys_clkin_ck>;
-		clock-indices = <1>, <2>, <3>, <4>, <5>;
-		clock-output-names = "audio_pll_clk1",
-				     "audio_pll_clk2",
-				     "audio_pll_clk3",
-				     "audio_pll_clk4",
-				     "audio_pll_clk5";
-	};
-};
-
-&scrm_clocks {
-	secure_32k_ck: secure_32k_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <32768>;
-	};
-
-	sys_32k_ck: sys_32k_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <32768>;
-	};
-
-	tclkin_ck: tclkin_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <32768>;
-	};
-
-	sys_clkin_ck: sys_clkin_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <27000000>;
-	};
-};
-
-/* 0x48180000 */
-&prcm_clocks {
-	clkout_pre_ck: clkout_pre_ck@100 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
-			  &audio_fapll 1>;
-		reg = <0x100>;
-	};
-
-	clkout_div_ck: clkout_div_ck@100 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&clkout_pre_ck>;
-		ti,bit-shift = <3>;
-		ti,max-div = <8>;
-		reg = <0x100>;
-	};
-
-	clkout_ck: clkout_ck@100 {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&clkout_div_ck>;
-		ti,bit-shift = <7>;
-		reg = <0x100>;
-	};
-
-	/* CM_DPLL clocks p1795 */
-	sysclk1_ck: sysclk1_ck@300 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&main_fapll 1>;
-		ti,max-div = <7>;
-		reg = <0x0300>;
-	};
-
-	sysclk2_ck: sysclk2_ck@304 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&main_fapll 2>;
-		ti,max-div = <7>;
-		reg = <0x0304>;
-	};
-
-	sysclk3_ck: sysclk3_ck@308 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&main_fapll 3>;
-		ti,max-div = <7>;
-		reg = <0x0308>;
-	};
-
-	sysclk4_ck: sysclk4_ck@30c {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&main_fapll 4>;
-		ti,max-div = <1>;
-		reg = <0x030c>;
-	};
-
-	sysclk5_ck: sysclk5_ck@310 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&sysclk4_ck>;
-		ti,max-div = <1>;
-		reg = <0x0310>;
-	};
-
-	sysclk6_ck: sysclk6_ck@314 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&main_fapll 4>;
-		ti,dividers = <2>, <4>;
-		reg = <0x0314>;
-	};
-
-	sysclk10_ck: sysclk10_ck@324 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&ddr_fapll 2>;
-		ti,max-div = <7>;
-		reg = <0x0324>;
-	};
-
-	sysclk24_ck: sysclk24_ck@3b4 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&main_fapll 5>;
-		ti,max-div = <7>;
-		reg = <0x03b4>;
-	};
-
-	mpu_ck: mpu_ck@15dc {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&sysclk2_ck>;
-		ti,bit-shift = <1>;
-                reg = <0x15dc>;
-	};
-
-	audio_pll_a_ck: audio_pll_a_ck@35c {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&audio_fapll 1>;
-		ti,max-div = <7>;
-		reg = <0x035c>;
-	};
-
-	sysclk18_ck: sysclk18_ck@378 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&sys_32k_ck>, <&audio_pll_a_ck>;
-		reg = <0x0378>;
-	};
-
-	timer1_fck: timer1_fck@390 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
-		reg = <0x0390>;
-	};
-
-	timer2_fck: timer2_fck@394 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
-		reg = <0x0394>;
-	};
-
-	timer3_fck: timer3_fck@398 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
-		reg = <0x0398>;
-	};
-
-	timer4_fck: timer4_fck@39c {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
-		reg = <0x039c>;
-	};
-
-	timer5_fck: timer5_fck@3a0 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
-		reg = <0x03a0>;
-	};
-
-	timer6_fck: timer6_fck@3a4 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
-		reg = <0x03a4>;
-	};
-
-	timer7_fck: timer7_fck@3a8 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
-		reg = <0x03a8>;
-	};
-};
diff --git a/arch/arm/dts/dm816x.dtsi b/arch/arm/dts/dm816x.dtsi
deleted file mode 100644
index c4a8653..0000000
--- a/arch/arm/dts/dm816x.dtsi
+++ /dev/null
@@ -1,517 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/omap.h>
-
-/ {
-	compatible = "ti,dm816";
-	interrupt-parent = <&intc>;
-	#address-cells = <1>;
-	#size-cells = <1>;
-	chosen { };
-
-	aliases {
-		i2c0 = &i2c1;
-		i2c1 = &i2c2;
-		serial0 = &uart1;
-		serial1 = &uart2;
-		serial2 = &uart3;
-		ethernet0 = &eth0;
-		ethernet1 = &eth1;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		cpu@0 {
-			compatible = "arm,cortex-a8";
-			device_type = "cpu";
-			reg = <0>;
-		};
-	};
-
-	pmu {
-		compatible = "arm,cortex-a8-pmu";
-		interrupts = <3>;
-	};
-
-	/*
-	 * The soc node represents the soc top level view. It is used for IPs
-	 * that are not memory mapped in the MPU view or for the MPU itself.
-	 */
-	soc {
-		compatible = "ti,omap-infra";
-		mpu {
-			compatible = "ti,omap3-mpu";
-			ti,hwmods = "mpu";
-		};
-	};
-
-	/*
-	 * XXX: Use a flat representation of the dm816x interconnect.
-	 * The real dm816x interconnect network is quite complex. Since
-	 * it will not bring real advantage to represent that in DT
-	 * for the moment, just use a fake OCP bus entry to represent
-	 * the whole bus hierarchy.
-	 */
-	ocp {
-		compatible = "simple-bus";
-		reg = <0x44000000 0x10000>;
-		interrupts = <9 10>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		prcm: prcm@48180000 {
-			compatible = "ti,dm816-prcm", "simple-bus";
-			reg = <0x48180000 0x4000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x48180000 0x4000>;
-
-			prcm_clocks: clocks {
-				#address-cells = <1>;
-				#size-cells = <0>;
-			};
-
-			prcm_clockdomains: clockdomains {
-			};
-		};
-
-		scrm: scrm@48140000 {
-			compatible = "ti,dm816-scrm", "simple-bus";
-			reg = <0x48140000 0x21000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			#pinctrl-cells = <1>;
-			ranges = <0 0x48140000 0x21000>;
-
-			dm816x_pinmux: pinmux@800 {
-				compatible = "pinctrl-single";
-				reg = <0x800 0x50a>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				#pinctrl-cells = <1>;
-				pinctrl-single,register-width = <16>;
-				pinctrl-single,function-mask = <0xf>;
-			};
-
-			/* Device Configuration Registers */
-			scm_conf: syscon@600 {
-				compatible = "syscon", "simple-bus";
-				reg = <0x600 0x110>;
-				#address-cells = <1>;
-				#size-cells = <1>;
-				ranges = <0 0x600 0x110>;
-
-				usb_phy0: usb-phy@20 {
-					compatible = "ti,dm8168-usb-phy";
-					reg = <0x20 0x8>;
-					reg-names = "phy";
-					clocks = <&main_fapll 6>;
-					clock-names = "refclk";
-					#phy-cells = <0>;
-					syscon = <&scm_conf>;
-				};
-
-				usb_phy1: usb-phy@28 {
-					compatible = "ti,dm8168-usb-phy";
-					reg = <0x28 0x8>;
-					reg-names = "phy";
-					clocks = <&main_fapll 6>;
-					clock-names = "refclk";
-					#phy-cells = <0>;
-					syscon = <&scm_conf>;
-				};
-			};
-
-			scrm_clocks: clocks {
-				#address-cells = <1>;
-				#size-cells = <0>;
-			};
-
-			scrm_clockdomains: clockdomains {
-			};
-		};
-
-		edma: edma@49000000 {
-			compatible = "ti,edma3";
-			ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
-			reg =   <0x49000000 0x10000>,
-			        <0x44e10f90 0x40>;
-			interrupts = <12 13 14>;
-			#dma-cells = <1>;
-		};
-
-		elm: elm@48080000 {
-			compatible = "ti,816-elm";
-			ti,hwmods = "elm";
-			reg = <0x48080000 0x2000>;
-			interrupts = <4>;
-		};
-
-		gpio1: gpio@48032000 {
-			compatible = "ti,omap4-gpio";
-			ti,hwmods = "gpio1";
-			ti,gpio-always-on;
-			reg = <0x48032000 0x1000>;
-			interrupts = <96>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio2: gpio@4804c000 {
-			compatible = "ti,omap4-gpio";
-			ti,hwmods = "gpio2";
-			ti,gpio-always-on;
-			reg = <0x4804c000 0x1000>;
-			interrupts = <98>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpmc: gpmc@50000000 {
-			compatible = "ti,am3352-gpmc";
-			ti,hwmods = "gpmc";
-			reg = <0x50000000 0x2000>;
-			#address-cells = <2>;
-			#size-cells = <1>;
-			interrupts = <100>;
-			dmas = <&edma 52>;
-			dma-names = "rxtx";
-			gpmc,num-cs = <6>;
-			gpmc,num-waitpins = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		i2c1: i2c@48028000 {
-			compatible = "ti,omap4-i2c";
-			ti,hwmods = "i2c1";
-			reg = <0x48028000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <70>;
-			dmas = <&edma 58 &edma 59>;
-			dma-names = "tx", "rx";
-		};
-
-		i2c2: i2c@4802a000 {
-			compatible = "ti,omap4-i2c";
-			ti,hwmods = "i2c2";
-			reg = <0x4802a000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <71>;
-			dmas = <&edma 60 &edma 61>;
-			dma-names = "tx", "rx";
-		};
-
-		intc: interrupt-controller@48200000 {
-			compatible = "ti,dm816-intc";
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			reg = <0x48200000 0x1000>;
-		};
-
-		rtc: rtc@480c0000 {
-			compatible = "ti,am3352-rtc", "ti,da830-rtc";
-			reg = <0x480c0000 0x1000>;
-			interrupts = <75 76>;
-			ti,hwmods = "rtc";
-		};
-
-		mailbox: mailbox@480c8000 {
-			compatible = "ti,omap4-mailbox";
-			reg = <0x480c8000 0x2000>;
-			interrupts = <77>;
-			ti,hwmods = "mailbox";
-			#mbox-cells = <1>;
-			ti,mbox-num-users = <4>;
-			ti,mbox-num-fifos = <12>;
-			mbox_dsp: mbox-dsp {
-				ti,mbox-tx = <3 0 0>;
-				ti,mbox-rx = <0 0 0>;
-			};
-		};
-
-		spinbox: spinbox@480ca000 {
-			compatible = "ti,omap4-hwspinlock";
-			reg = <0x480ca000 0x2000>;
-			ti,hwmods = "spinbox";
-			#hwlock-cells = <1>;
-		};
-
-		mdio: mdio@4a100800 {
-			compatible = "ti,davinci_mdio";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x4a100800 0x100>;
-			ti,hwmods = "davinci_mdio";
-			bus_freq = <1000000>;
-			phy0: ethernet-phy@0 {
-				reg = <1>;
-			};
-			phy1: ethernet-phy@1 {
-				reg = <2>;
-			};
-		};
-
-		eth0: ethernet@4a100000 {
-			compatible = "ti,dm816-emac";
-			ti,hwmods = "emac0";
-			reg = <0x4a100000 0x800
-			       0x4a100900 0x3700>;
-			clocks = <&sysclk24_ck>;
-			syscon = <&scm_conf>;
-			ti,davinci-ctrl-reg-offset = <0>;
-			ti,davinci-ctrl-mod-reg-offset = <0x900>;
-			ti,davinci-ctrl-ram-offset = <0x2000>;
-			ti,davinci-ctrl-ram-size = <0x2000>;
-			interrupts = <40 41 42 43>;
-			phy-handle = <&phy0>;
-		};
-
-		eth1: ethernet@4a120000 {
-			compatible = "ti,dm816-emac";
-			ti,hwmods = "emac1";
-			reg = <0x4a120000 0x4000>;
-			clocks = <&sysclk24_ck>;
-			syscon = <&scm_conf>;
-			ti,davinci-ctrl-reg-offset = <0>;
-			ti,davinci-ctrl-mod-reg-offset = <0x900>;
-			ti,davinci-ctrl-ram-offset = <0x2000>;
-			ti,davinci-ctrl-ram-size = <0x2000>;
-			interrupts = <44 45 46 47>;
-			phy-handle = <&phy1>;
-		};
-
-		mcspi1: spi@48030000 {
-			compatible = "ti,omap4-mcspi";
-			reg = <0x48030000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <65>;
-			ti,spi-num-cs = <4>;
-			ti,hwmods = "mcspi1";
-			dmas = <&edma 16 &edma 17
-				&edma 18 &edma 19
-				&edma 20 &edma 21
-				&edma 22 &edma 23>;
-			dma-names = "tx0", "rx0", "tx1", "rx1",
-				    "tx2", "rx2", "tx3", "rx3";
-		};
-
-		mmc1: mmc@48060000 {
-			compatible = "ti,omap4-hsmmc";
-			reg = <0x48060000 0x11000>;
-			ti,hwmods = "mmc1";
-			interrupts = <64>;
-			dmas = <&edma 24 &edma 25>;
-			dma-names = "tx", "rx";
-		};
-
-		timer1: timer@4802e000 {
-			compatible = "ti,dm816-timer";
-			reg = <0x4802e000 0x2000>;
-			interrupts = <67>;
-			ti,hwmods = "timer1";
-			ti,timer-alwon;
-		};
-
-		timer2: timer@48040000 {
-			compatible = "ti,dm816-timer";
-			reg = <0x48040000 0x2000>;
-			interrupts = <68>;
-			ti,hwmods = "timer2";
-		};
-
-		timer3: timer@48042000 {
-			compatible = "ti,dm816-timer";
-			reg = <0x48042000 0x2000>;
-			interrupts = <69>;
-			ti,hwmods = "timer3";
-		};
-
-		timer4: timer@48044000 {
-			compatible = "ti,dm816-timer";
-			reg = <0x48044000 0x2000>;
-			interrupts = <92>;
-			ti,hwmods = "timer4";
-			ti,timer-pwm;
-		};
-
-		timer5: timer@48046000 {
-			compatible = "ti,dm816-timer";
-			reg = <0x48046000 0x2000>;
-			interrupts = <93>;
-			ti,hwmods = "timer5";
-			ti,timer-pwm;
-		};
-
-		timer6: timer@48048000 {
-			compatible = "ti,dm816-timer";
-			reg = <0x48048000 0x2000>;
-			interrupts = <94>;
-			ti,hwmods = "timer6";
-			ti,timer-pwm;
-		};
-
-		timer7: timer@4804a000 {
-			compatible = "ti,dm816-timer";
-			reg = <0x4804a000 0x2000>;
-			interrupts = <95>;
-			ti,hwmods = "timer7";
-			ti,timer-pwm;
-		};
-
-		uart1: serial@48020000 {
-			compatible = "ti,am3352-uart", "ti,omap3-uart";
-			ti,hwmods = "uart1";
-			reg = <0x48020000 0x2000>;
-			clock-frequency = <48000000>;
-			interrupts = <72>;
-			dmas = <&edma 26 &edma 27>;
-			dma-names = "tx", "rx";
-		};
-
-		uart2: serial@48022000 {
-			compatible = "ti,am3352-uart", "ti,omap3-uart";
-			ti,hwmods = "uart2";
-			reg = <0x48022000 0x2000>;
-			clock-frequency = <48000000>;
-			interrupts = <73>;
-			dmas = <&edma 28 &edma 29>;
-			dma-names = "tx", "rx";
-		};
-
-		uart3: serial@48024000 {
-			compatible = "ti,am3352-uart", "ti,omap3-uart";
-			ti,hwmods = "uart3";
-			reg = <0x48024000 0x2000>;
-			clock-frequency = <48000000>;
-			interrupts = <74>;
-			dmas = <&edma 30 &edma 31>;
-			dma-names = "tx", "rx";
-		};
-
-		/* NOTE: USB needs a transceiver driver for phys to work */
-		usb: usb_otg_hs@47401000 {
-			compatible = "ti,am33xx-usb";
-			reg = <0x47401000 0x400000>;
-			ranges;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ti,hwmods = "usb_otg_hs";
-
-			usb0: usb@47401000 {
-				compatible = "ti,musb-dm816";
-				reg = <0x47401400 0x400
-				       0x47401000 0x200>;
-				reg-names = "mc", "control";
-				interrupts = <18>;
-				interrupt-names = "mc";
-				dr_mode = "host";
-				interface-type = <0>;
-				phys = <&usb_phy0>;
-				phy-names = "usb2-phy";
-				mentor,multipoint = <1>;
-				mentor,num-eps = <16>;
-				mentor,ram-bits = <12>;
-				mentor,power = <500>;
-
-				dmas = <&cppi41dma  0 0 &cppi41dma  1 0
-					&cppi41dma  2 0 &cppi41dma  3 0
-					&cppi41dma  4 0 &cppi41dma  5 0
-					&cppi41dma  6 0 &cppi41dma  7 0
-					&cppi41dma  8 0 &cppi41dma  9 0
-					&cppi41dma 10 0 &cppi41dma 11 0
-					&cppi41dma 12 0 &cppi41dma 13 0
-					&cppi41dma 14 0 &cppi41dma  0 1
-					&cppi41dma  1 1 &cppi41dma  2 1
-					&cppi41dma  3 1 &cppi41dma  4 1
-					&cppi41dma  5 1 &cppi41dma  6 1
-					&cppi41dma  7 1 &cppi41dma  8 1
-					&cppi41dma  9 1 &cppi41dma 10 1
-					&cppi41dma 11 1 &cppi41dma 12 1
-					&cppi41dma 13 1 &cppi41dma 14 1>;
-				dma-names =
-					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
-					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
-					"rx14", "rx15",
-					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
-					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
-					"tx14", "tx15";
-			};
-
-			usb1: usb@47401800 {
-				compatible = "ti,musb-dm816";
-				reg = <0x47401c00 0x400
-				       0x47401800 0x200>;
-				reg-names = "mc", "control";
-				interrupts = <19>;
-				interrupt-names = "mc";
-				dr_mode = "host";
-				interface-type = <0>;
-				phys = <&usb_phy1>;
-				phy-names = "usb2-phy";
-				mentor,multipoint = <1>;
-				mentor,num-eps = <16>;
-				mentor,ram-bits = <12>;
-				mentor,power = <500>;
-
-				dmas = <&cppi41dma 15 0 &cppi41dma 16 0
-					&cppi41dma 17 0 &cppi41dma 18 0
-					&cppi41dma 19 0 &cppi41dma 20 0
-					&cppi41dma 21 0 &cppi41dma 22 0
-					&cppi41dma 23 0 &cppi41dma 24 0
-					&cppi41dma 25 0 &cppi41dma 26 0
-					&cppi41dma 27 0 &cppi41dma 28 0
-					&cppi41dma 29 0 &cppi41dma 15 1
-					&cppi41dma 16 1 &cppi41dma 17 1
-					&cppi41dma 18 1 &cppi41dma 19 1
-					&cppi41dma 20 1 &cppi41dma 21 1
-					&cppi41dma 22 1 &cppi41dma 23 1
-					&cppi41dma 24 1 &cppi41dma 25 1
-					&cppi41dma 26 1 &cppi41dma 27 1
-					&cppi41dma 28 1 &cppi41dma 29 1>;
-				dma-names =
-					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
-					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
-					"rx14", "rx15",
-					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
-					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
-					"tx14", "tx15";
-			};
-
-			cppi41dma: dma-controller@47402000 {
-				compatible = "ti,am3359-cppi41";
-				reg =  <0x47400000 0x1000
-					0x47402000 0x1000
-					0x47403000 0x1000
-					0x47404000 0x4000>;
-				reg-names = "glue", "controller", "scheduler", "queuemgr";
-				interrupts = <17>;
-				interrupt-names = "glue";
-				#dma-cells = <2>;
-				#dma-channels = <30>;
-				#dma-requests = <256>;
-			};
-		};
-
-		wd_timer2: wd_timer@480c2000 {
-			compatible = "ti,omap3-wdt";
-			ti,hwmods = "wd_timer";
-			reg = <0x480c2000 0x1000>;
-			interrupts = <0>;
-		};
-	};
-};
-
-#include "dm816x-clocks.dtsi"
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index ad25b3e..67400c2 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -13,10 +13,6 @@
 #include <asm/arch/clocks_am33xx.h>
 #include <asm/arch/hardware.h>
 
-#if defined(CONFIG_TI816X)
-#include <asm/arch/clock_ti81xx.h>
-#endif
-
 #define LDELAY 1000000
 
 /*CM_<clock_domain>__CLKCTRL */
diff --git a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
deleted file mode 100644
index d22d958..0000000
--- a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * ti81xx.h
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- *
- * This file is released under the terms of GPL v2 and any later version.
- * See the file COPYING in the root directory of the source tree for details.
- */
-
-#ifndef _CLOCK_TI81XX_H_
-#define _CLOCK_TI81XX_H_
-
-#define PRCM_MOD_EN     0x2
-
-#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500)
-#define CM_ALWON_BASE   (PRCM_BASE + 0x1400)
-
-struct cm_def {
-	unsigned int resv0[2];
-	unsigned int l3fastclkstctrl;
-	unsigned int resv1[1];
-	unsigned int pciclkstctrl;
-	unsigned int resv2[1];
-	unsigned int ducaticlkstctrl;
-	unsigned int resv3[1];
-	unsigned int emif0clkctrl;
-	unsigned int emif1clkctrl;
-	unsigned int dmmclkctrl;
-	unsigned int fwclkctrl;
-	unsigned int resv4[10];
-	unsigned int usbclkctrl;
-	unsigned int resv5[1];
-	unsigned int sataclkctrl;
-	unsigned int resv6[4];
-	unsigned int ducaticlkctrl;
-	unsigned int pciclkctrl;
-};
-
-struct cm_alwon {
-	unsigned int l3slowclkstctrl;
-	unsigned int ethclkstctrl;
-	unsigned int l3medclkstctrl;
-	unsigned int mmu_clkstctrl;
-	unsigned int mmucfg_clkstctrl;
-	unsigned int ocmc0clkstctrl;
-#if defined(CONFIG_TI816X)
-	unsigned int ocmc1clkstctrl;
-#endif
-	unsigned int mpuclkstctrl;
-	unsigned int sysclk4clkstctrl;
-	unsigned int sysclk5clkstctrl;
-	unsigned int sysclk6clkstctrl;
-	unsigned int rtcclkstctrl;
-	unsigned int l3fastclkstctrl;
-	unsigned int resv0[67];
-	unsigned int mcasp0clkctrl;
-	unsigned int mcasp1clkctrl;
-	unsigned int mcasp2clkctrl;
-	unsigned int mcbspclkctrl;
-	unsigned int uart0clkctrl;
-	unsigned int uart1clkctrl;
-	unsigned int uart2clkctrl;
-	unsigned int gpio0clkctrl;
-	unsigned int gpio1clkctrl;
-	unsigned int i2c0clkctrl;
-	unsigned int i2c1clkctrl;
-#if defined(CONFIG_TI816X)
-	unsigned int resv1[1];
-	unsigned int timer1clkctrl;
-	unsigned int timer2clkctrl;
-	unsigned int timer3clkctrl;
-	unsigned int timer4clkctrl;
-	unsigned int timer5clkctrl;
-	unsigned int timer6clkctrl;
-	unsigned int timer7clkctrl;
-#endif
-	unsigned int wdtimerclkctrl;
-	unsigned int spiclkctrl;
-	unsigned int mailboxclkctrl;
-	unsigned int spinboxclkctrl;
-	unsigned int mmudataclkctrl;
-	unsigned int resv2[2];
-	unsigned int mmucfgclkctrl;
-#if defined(CONFIG_TI816X)
-	unsigned int resv3[1];
-	unsigned int sdioclkctrl;
-#endif
-	unsigned int ocmc0clkctrl;
-#if defined(CONFIG_TI816X)
-	unsigned int ocmc1clkctrl;
-#endif
-	unsigned int resv4[2];
-	unsigned int controlclkctrl;
-	unsigned int resv5[2];
-	unsigned int gpmcclkctrl;
-	unsigned int ethernet0clkctrl;
-	unsigned int ethernet1clkctrl;
-	unsigned int mpuclkctrl;
-#if defined(CONFIG_TI816X)
-	unsigned int resv6[1];
-#endif
-	unsigned int l3clkctrl;
-	unsigned int l4hsclkctrl;
-	unsigned int l4lsclkctrl;
-	unsigned int rtcclkctrl;
-	unsigned int tpccclkctrl;
-	unsigned int tptc0clkctrl;
-	unsigned int tptc1clkctrl;
-	unsigned int tptc2clkctrl;
-	unsigned int tptc3clkctrl;
-#if defined(CONFIG_TI816X)
-	unsigned int sr0clkctrl;
-	unsigned int sr1clkctrl;
-#endif
-};
-
-#endif /* _CLOCK_TI81XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 15a5b64..1a03107 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -369,15 +369,9 @@
 	unsigned int ddrckectrl;
 };
 
-#ifdef CONFIG_TI816X
-void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl,
-		const struct emif_regs *regs,
-		const struct dmm_lisa_map_regs *lisa_regs, int nrs);
-#else
 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
 		const struct ddr_data *data, const struct cmd_control *ctrl,
 		const struct emif_regs *regs, int nr);
-#endif
 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
 
 #endif  /* _DDR_DEFS_H */
diff --git a/arch/arm/include/asm/arch-am33xx/emac_defs.h b/arch/arm/include/asm/arch-am33xx/emac_defs.h
deleted file mode 100644
index eb6516d..0000000
--- a/arch/arm/include/asm/arch-am33xx/emac_defs.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010 Texas Instruments
- *
- * Based on:
- *
- * ----------------------------------------------------------------------------
- *
- * dm644x_emac.h
- *
- * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
- *
- * Copyright (C) 2005 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- *
- */
-
-#ifndef _EMAC_DEFS_H_
-#define _EMAC_DEFS_H_
-
-#ifdef CONFIG_TI816X
-#define EMAC_BASE_ADDR			(0x4A100000)
-#define EMAC_WRAPPER_BASE_ADDR		(0x4A100900)
-#define EMAC_WRAPPER_RAM_ADDR		(0x4A102000)
-#define EMAC_MDIO_BASE_ADDR		(0x4A100800)
-#define EMAC_MDIO_BUS_FREQ		(250000000UL)
-#define EMAC_MDIO_CLOCK_FREQ		(2000000UL)
-
-typedef volatile unsigned int	dv_reg;
-typedef volatile unsigned int	*dv_reg_p;
-
-#define DAVINCI_EMAC_VERSION2
-#define DAVINCI_EMAC_GIG_ENABLE
-#endif
-
-#endif  /* _EMAC_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 2d7f9da..387f053 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -14,8 +14,6 @@
 #include <asm/arch/omap.h>
 #ifdef CONFIG_AM33XX
 #include <asm/arch/hardware_am33xx.h>
-#elif defined(CONFIG_TI816X)
-#include <asm/arch/hardware_ti816x.h>
 #elif defined(CONFIG_AM43XX)
 #include <asm/arch/hardware_am43xx.h>
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
deleted file mode 100644
index 78b7948..0000000
--- a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * hardware_ti816x.h
- *
- * TI816x hardware specific header
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- * Based on TI-PSP-04.00.02.14
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __AM33XX_HARDWARE_TI816X_H
-#define __AM33XX_HARDWARE_TI816X_H
-
-/* UART */
-#define UART0_BASE		0x48020000
-#define UART1_BASE		0x48022000
-#define UART2_BASE		0x48024000
-
-/* Watchdog Timer */
-#define WDT_BASE		0x480C2000
-
-/* Control Module Base Address */
-#define CTRL_BASE		0x48140000
-#define CTRL_DEVICE_BASE	0x48140600
-
-/* PRCM Base Address */
-#define PRCM_BASE		0x48180000
-
-#define PRM_RSTCTRL		(PRCM_BASE + 0x00A0)
-#define PRM_RSTST		(PRM_RSTCTRL + 8)
-
-/* VTP Base address */
-#define VTP0_CTRL_ADDR		0x48198358
-#define VTP1_CTRL_ADDR		0x4819A358
-
-/* DDR Base address */
-#define DDR_PHY_CMD_ADDR	0x48198000
-#define DDR_PHY_DATA_ADDR	0x481980C8
-#define DDR_PHY_CMD_ADDR2	0x4819A000
-#define DDR_PHY_DATA_ADDR2	0x4819A0C8
-#define DDR_DATA_REGS_NR	4
-
-
-#define DDRPHY_0_CONFIG_BASE	0x48198000
-#define DDRPHY_1_CONFIG_BASE	0x4819A000
-#define DDRPHY_CONFIG_BASE	((emif == 0) ? \
-	DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE)
-
-/* RTC base address */
-#define RTC_BASE		0x480C0000
-
-#endif /* __AM33XX_HARDWARE_TI816X_H */
diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
index ed15d15..b1b1896 100644
--- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -24,9 +24,4 @@
 #define OMAP_HSMMC1_BASE		0x48060000
 #define OMAP_HSMMC2_BASE		0x481D8000
 
-#if defined(CONFIG_TI816X)
-#undef MMC_CLOCK_REFERENCE
-#define MMC_CLOCK_REFERENCE	48 /* MHz */
-#endif
-
 #endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h
index 7cf9737..ebb2d30 100644
--- a/arch/arm/include/asm/arch-am33xx/mux.h
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -20,8 +20,6 @@
 
 #ifdef CONFIG_AM33XX
 #include <asm/arch/mux_am33xx.h>
-#elif defined(CONFIG_TI816X)
-#include <asm/arch/mux_ti816x.h>
 #elif defined(CONFIG_AM43XX)
 #include <asm/arch/mux_am43xx.h>
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
deleted file mode 100644
index a6a8a98..0000000
--- a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
+++ /dev/null
@@ -1,362 +0,0 @@
-/*
- * mux_ti816x.h
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _MUX_TI816X_H_
-#define _MUX_TI816X_H_
-
-#include <asm/io.h>
-
-#define MUX_CFG(value, offset)  \
-	__raw_writel(value, (CTRL_BASE + offset));
-
-#define PULLDOWN_EN	(0x0 << 4)	/* Pull Down Selection */
-#define PULLUP_EN	(0x1 << 4)	/* Pull Up Selection */
-#define PULLUDEN	(0x0 << 3)	/* Pull up enabled */
-#define PULLUDDIS	(0x1 << 3)	/* Pull up disabled */
-#define MODE(val)	(val)		/* used for Readability */
-
-
-/*
- * PAD CONTROL OFFSETS
- * Field names corresponds to the pad signal name
- */
-struct pad_signals {
-	int pincntl1;
-	int pincntl2;
-	int pincntl3;
-	int pincntl4;
-	int pincntl5;
-	int pincntl6;
-	int pincntl7;
-	int pincntl8;
-	int pincntl9;
-	int pincntl10;
-	int pincntl11;
-	int pincntl12;
-	int pincntl13;
-	int pincntl14;
-	int pincntl15;
-	int pincntl16;
-	int pincntl17;
-	int pincntl18;
-	int pincntl19;
-	int pincntl20;
-	int pincntl21;
-	int pincntl22;
-	int pincntl23;
-	int pincntl24;
-	int pincntl25;
-	int pincntl26;
-	int pincntl27;
-	int pincntl28;
-	int pincntl29;
-	int pincntl30;
-	int pincntl31;
-	int pincntl32;
-	int pincntl33;
-	int pincntl34;
-	int pincntl35;
-	int pincntl36;
-	int pincntl37;
-	int pincntl38;
-	int pincntl39;
-	int pincntl40;
-	int pincntl41;
-	int pincntl42;
-	int pincntl43;
-	int pincntl44;
-	int pincntl45;
-	int pincntl46;
-	int pincntl47;
-	int pincntl48;
-	int pincntl49;
-	int pincntl50;
-	int pincntl51;
-	int pincntl52;
-	int pincntl53;
-	int pincntl54;
-	int pincntl55;
-	int pincntl56;
-	int pincntl57;
-	int pincntl58;
-	int pincntl59;
-	int pincntl60;
-	int pincntl61;
-	int pincntl62;
-	int pincntl63;
-	int pincntl64;
-	int pincntl65;
-	int pincntl66;
-	int pincntl67;
-	int pincntl68;
-	int pincntl69;
-	int pincntl70;
-	int pincntl71;
-	int pincntl72;
-	int pincntl73;
-	int pincntl74;
-	int pincntl75;
-	int pincntl76;
-	int pincntl77;
-	int pincntl78;
-	int pincntl79;
-	int pincntl80;
-	int pincntl81;
-	int pincntl82;
-	int pincntl83;
-	int pincntl84;
-	int pincntl85;
-	int pincntl86;
-	int pincntl87;
-	int pincntl88;
-	int pincntl89;
-	int pincntl90;
-	int pincntl91;
-	int pincntl92;
-	int pincntl93;
-	int pincntl94;
-	int pincntl95;
-	int pincntl96;
-	int pincntl97;
-	int pincntl98;
-	int pincntl99;
-	int pincntl100;
-	int pincntl101;
-	int pincntl102;
-	int pincntl103;
-	int pincntl104;
-	int pincntl105;
-	int pincntl106;
-	int pincntl107;
-	int pincntl108;
-	int pincntl109;
-	int pincntl110;
-	int pincntl111;
-	int pincntl112;
-	int pincntl113;
-	int pincntl114;
-	int pincntl115;
-	int pincntl116;
-	int pincntl117;
-	int pincntl118;
-	int pincntl119;
-	int pincntl120;
-	int pincntl121;
-	int pincntl122;
-	int pincntl123;
-	int pincntl124;
-	int pincntl125;
-	int pincntl126;
-	int pincntl127;
-	int pincntl128;
-	int pincntl129;
-	int pincntl130;
-	int pincntl131;
-	int pincntl132;
-	int pincntl133;
-	int pincntl134;
-	int pincntl135;
-	int pincntl136;
-	int pincntl137;
-	int pincntl138;
-	int pincntl139;
-	int pincntl140;
-	int pincntl141;
-	int pincntl142;
-	int pincntl143;
-	int pincntl144;
-	int pincntl145;
-	int pincntl146;
-	int pincntl147;
-	int pincntl148;
-	int pincntl149;
-	int pincntl150;
-	int pincntl151;
-	int pincntl152;
-	int pincntl153;
-	int pincntl154;
-	int pincntl155;
-	int pincntl156;
-	int pincntl157;
-	int pincntl158;
-	int pincntl159;
-	int pincntl160;
-	int pincntl161;
-	int pincntl162;
-	int pincntl163;
-	int pincntl164;
-	int pincntl165;
-	int pincntl166;
-	int pincntl167;
-	int pincntl168;
-	int pincntl169;
-	int pincntl170;
-	int pincntl171;
-	int pincntl172;
-	int pincntl173;
-	int pincntl174;
-	int pincntl175;
-	int pincntl176;
-	int pincntl177;
-	int pincntl178;
-	int pincntl179;
-	int pincntl180;
-	int pincntl181;
-	int pincntl182;
-	int pincntl183;
-	int pincntl184;
-	int pincntl185;
-	int pincntl186;
-	int pincntl187;
-	int pincntl188;
-	int pincntl189;
-	int pincntl190;
-	int pincntl191;
-	int pincntl192;
-	int pincntl193;
-	int pincntl194;
-	int pincntl195;
-	int pincntl196;
-	int pincntl197;
-	int pincntl198;
-	int pincntl199;
-	int pincntl200;
-	int pincntl201;
-	int pincntl202;
-	int pincntl203;
-	int pincntl204;
-	int pincntl205;
-	int pincntl206;
-	int pincntl207;
-	int pincntl208;
-	int pincntl209;
-	int pincntl210;
-	int pincntl211;
-	int pincntl212;
-	int pincntl213;
-	int pincntl214;
-	int pincntl215;
-	int pincntl216;
-	int pincntl217;
-	int pincntl218;
-	int pincntl219;
-	int pincntl220;
-	int pincntl221;
-	int pincntl222;
-	int pincntl223;
-	int pincntl224;
-	int pincntl225;
-	int pincntl226;
-	int pincntl227;
-	int pincntl228;
-	int pincntl229;
-	int pincntl230;
-	int pincntl231;
-	int pincntl232;
-	int pincntl233;
-	int pincntl234;
-	int pincntl235;
-	int pincntl236;
-	int pincntl237;
-	int pincntl238;
-	int pincntl239;
-	int pincntl240;
-	int pincntl241;
-	int pincntl242;
-	int pincntl243;
-	int pincntl244;
-	int pincntl245;
-	int pincntl246;
-	int pincntl247;
-	int pincntl248;
-	int pincntl249;
-	int pincntl250;
-	int pincntl251;
-	int pincntl252;
-	int pincntl253;
-	int pincntl254;
-	int pincntl255;
-	int pincntl256;
-	int pincntl257;
-	int pincntl258;
-	int pincntl259;
-	int pincntl260;
-	int pincntl261;
-	int pincntl262;
-	int pincntl263;
-	int pincntl264;
-	int pincntl265;
-	int pincntl266;
-	int pincntl267;
-	int pincntl268;
-	int pincntl269;
-	int pincntl270;
-	int pincntl271;
-	int pincntl272;
-	int pincntl273;
-	int pincntl274;
-	int pincntl275;
-	int pincntl276;
-	int pincntl277;
-	int pincntl278;
-	int pincntl279;
-	int pincntl280;
-	int pincntl281;
-	int pincntl282;
-	int pincntl283;
-	int pincntl284;
-	int pincntl285;
-	int pincntl286;
-	int pincntl287;
-	int pincntl288;
-	int pincntl289;
-	int pincntl290;
-	int pincntl291;
-	int pincntl292;
-	int pincntl293;
-	int pincntl294;
-	int pincntl295;
-	int pincntl296;
-	int pincntl297;
-	int pincntl298;
-	int pincntl299;
-	int pincntl300;
-	int pincntl301;
-	int pincntl302;
-	int pincntl303;
-	int pincntl304;
-	int pincntl305;
-	int pincntl306;
-	int pincntl307;
-	int pincntl308;
-	int pincntl309;
-	int pincntl310;
-	int pincntl311;
-	int pincntl312;
-	int pincntl313;
-	int pincntl314;
-	int pincntl315;
-	int pincntl316;
-	int pincntl317;
-	int pincntl318;
-	int pincntl319;
-	int pincntl320;
-	int pincntl321;
-	int pincntl322;
-	int pincntl323;
-};
-
-#endif /* endif _MUX_TI816X_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
index 4c71dbf..53046de 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -20,10 +20,6 @@
 #define NON_SECURE_SRAM_START	0x402F0400
 #define NON_SECURE_SRAM_END	0x40310000
 #define NON_SECURE_SRAM_IMG_END	0x4030B800
-#elif defined(CONFIG_TI816X)
-#define NON_SECURE_SRAM_START	0x40300000
-#define NON_SECURE_SRAM_END	0x40320000
-#define NON_SECURE_SRAM_IMG_END	0x4031B800
 #elif defined(CONFIG_AM43XX)
 #define NON_SECURE_SRAM_START	0x402F0400
 #define NON_SECURE_SRAM_END	0x40340000
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 6bd3ca0..9ddb346 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -9,19 +9,7 @@
 #define BOOT_DEVICE_NONE	0x00
 #define BOOT_DEVICE_MMC2_2	0xFF
 
-#if defined(CONFIG_TI816X)
-#define BOOT_DEVICE_XIP		0x01
-#define BOOT_DEVICE_XIPWAIT	0x02
-#define BOOT_DEVICE_NAND	0x03
-#define BOOT_DEVICE_ONENAND	0x04
-#define BOOT_DEVICE_MMC2	0x05 /* ROM only supports 2nd instance. */
-#define BOOT_DEVICE_MMC1	0x06
-#define BOOT_DEVICE_UART	0x43
-#define BOOT_DEVICE_USB		0x45
-
-#define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC2
-#define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC1
-#elif defined(CONFIG_AM33XX)
+#if defined(CONFIG_AM33XX)
 #define BOOT_DEVICE_XIP		0x01
 #define BOOT_DEVICE_XIPWAIT	0x02
 #define BOOT_DEVICE_NAND	0x05
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 309b967..8465b54 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -77,16 +77,6 @@
 	imply SPL_SERIAL
 	imply SYS_I2C_OMAP24XX
 
-config TI816X
-	bool "TI816X SoC"
-	select SPECIFY_CONSOLE_INDEX
-	imply NAND_OMAP_ELM
-	imply NAND_OMAP_GPMC
-	help
-	  Support for AM335x SOC from Texas Instruments.
-	  The AM335x high performance SOC features a Cortex-A8
-	  ARM core and more.
-
 config AM43XX
 	bool "AM43XX SoC"
 	select SPECIFY_CONSOLE_INDEX
@@ -203,7 +193,6 @@
 source "board/siemens/draco/Kconfig"
 source "board/siemens/pxm2/Kconfig"
 source "board/siemens/rut/Kconfig"
-source "board/ti/ti816x/Kconfig"
 source "board/ti/am43xx/Kconfig"
 source "board/ti/am335x/Kconfig"
 source "board/compulab/cm_t43/Kconfig"
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index 1299aec..8cb0c57 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -1,13 +1,3 @@
-if TI816X
-
-config TARGET_TI816X_EVM
-	bool "Support ti816x_evm"
-	help
-	  This option specifies support for the TI8168 EVM development platform
-	  with PG2.0 silicon and DDR3 DRAM.
-
-endif
-
 if AM33XX
 
 config AM33XX_CHILISOM
diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile
index bf94d34..2aa8013 100644
--- a/arch/arm/mach-omap2/am33xx/Makefile
+++ b/arch/arm/mach-omap2/am33xx/Makefile
@@ -9,13 +9,11 @@
 obj-y	+= clock.o
 endif
 
-obj-$(CONFIG_TI816X)	+= clock_ti816x.o
 obj-y	+= sys_info.o
 obj-y	+= ddr.o
-ifeq ($(CONFIG_TI816X)$(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
+ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
 obj-y	+= emif4.o
 endif
-obj-$(CONFIG_TI816X)	+= ti816x_emif4.o
 obj-y	+= board.o
 obj-y	+= mux.o
 obj-y	+= prcm-regs.o
diff --git a/arch/arm/mach-omap2/am33xx/clock_ti816x.c b/arch/arm/mach-omap2/am33xx/clock_ti816x.c
deleted file mode 100644
index ec4cc75..0000000
--- a/arch/arm/mach-omap2/am33xx/clock_ti816x.c
+++ /dev/null
@@ -1,407 +0,0 @@
-/*
- * clock_ti816x.c
- *
- * Clocks for TI816X based boards
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- *
- * Based on TI-PSP-04.00.02.14 :
- *
- * Copyright (C) 2009, Texas Instruments, Incorporated
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-
-#include <asm/emif.h>
-
-#define CM_PLL_BASE		(CTRL_BASE + 0x0400)
-
-/* Main PLL */
-#define MAIN_N			64
-#define MAIN_P			0x1
-#define MAIN_INTFREQ1		0x8
-#define MAIN_FRACFREQ1		0x800000
-#define MAIN_MDIV1		0x2
-#define MAIN_INTFREQ2		0xE
-#define MAIN_FRACFREQ2		0x0
-#define MAIN_MDIV2		0x1
-#define MAIN_INTFREQ3		0x8
-#define MAIN_FRACFREQ3		0xAAAAB0
-#define MAIN_MDIV3		0x3
-#define MAIN_INTFREQ4		0x9
-#define MAIN_FRACFREQ4		0x55554F
-#define MAIN_MDIV4		0x3
-#define MAIN_INTFREQ5		0x9
-#define MAIN_FRACFREQ5		0x374BC6
-#define MAIN_MDIV5		0xC
-#define MAIN_MDIV6		0x48
-#define MAIN_MDIV7		0x4
-
-/* DDR PLL */
-#define DDR_N			59
-#define DDR_P			0x1
-#define DDR_MDIV1		0x2
-#define DDR_INTFREQ2		0x8
-#define DDR_FRACFREQ2		0xD99999
-#define DDR_MDIV2		0x1E
-#define DDR_INTFREQ3		0x8
-#define DDR_FRACFREQ3		0x0
-#define DDR_MDIV3		0x4
-#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ4		0x0
-#define DDR_MDIV4		0x4
-#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ5		0x0
-#define DDR_MDIV5		0x4
-
-#define CONTROL_STATUS			(CTRL_BASE + 0x40)
-#define DDR_RCD				(CTRL_BASE + 0x070C)
-#define CM_TIMER1_CLKSEL		(PRCM_BASE + 0x390)
-#define CM_ALWON_CUST_EFUSE_CLKCTRL	(PRCM_BASE + 0x1628)
-
-#define INTCPS_SYSCONFIG	0x48200010
-#define CM_SYSCLK10_CLKSEL	0x48180324
-
-struct cm_pll {
-	unsigned int mainpll_ctrl;	/* offset 0x400 */
-	unsigned int mainpll_pwd;
-	unsigned int mainpll_freq1;
-	unsigned int mainpll_div1;
-	unsigned int mainpll_freq2;
-	unsigned int mainpll_div2;
-	unsigned int mainpll_freq3;
-	unsigned int mainpll_div3;
-	unsigned int mainpll_freq4;
-	unsigned int mainpll_div4;
-	unsigned int mainpll_freq5;
-	unsigned int mainpll_div5;
-	unsigned int resv0[1];
-	unsigned int mainpll_div6;
-	unsigned int resv1[1];
-	unsigned int mainpll_div7;
-	unsigned int ddrpll_ctrl;	/* offset 0x440 */
-	unsigned int ddrpll_pwd;
-	unsigned int resv2[1];
-	unsigned int ddrpll_div1;
-	unsigned int ddrpll_freq2;
-	unsigned int ddrpll_div2;
-	unsigned int ddrpll_freq3;
-	unsigned int ddrpll_div3;
-	unsigned int ddrpll_freq4;
-	unsigned int ddrpll_div4;
-	unsigned int ddrpll_freq5;
-	unsigned int ddrpll_div5;
-	unsigned int videopll_ctrl;	/* offset 0x470 */
-	unsigned int videopll_pwd;
-	unsigned int videopll_freq1;
-	unsigned int videopll_div1;
-	unsigned int videopll_freq2;
-	unsigned int videopll_div2;
-	unsigned int videopll_freq3;
-	unsigned int videopll_div3;
-	unsigned int resv3[4];
-	unsigned int audiopll_ctrl;	/* offset 0x4A0 */
-	unsigned int audiopll_pwd;
-	unsigned int resv4[2];
-	unsigned int audiopll_freq2;
-	unsigned int audiopll_div2;
-	unsigned int audiopll_freq3;
-	unsigned int audiopll_div3;
-	unsigned int audiopll_freq4;
-	unsigned int audiopll_div4;
-	unsigned int audiopll_freq5;
-	unsigned int audiopll_div5;
-};
-
-const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
-const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
-const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE;
-const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-
-void enable_dmm_clocks(void)
-{
-	writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
-	/* Wait for dmm to be fully functional, including OCP */
-	while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0)
-		;
-}
-
-void enable_emif_clocks(void)
-{
-	writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
-	writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
-	writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
-	writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
-
-	/* Wait for clocks to be active */
-	while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
-		;
-	/* Wait for emif0 to be fully functional, including OCP */
-	while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0)
-		;
-	/* Wait for emif1 to be fully functional, including OCP */
-	while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0)
-		;
-}
-
-/* assume delay is aprox at least 1us */
-static void ddr_delay(int d)
-{
-	int i;
-
-	/*
-	 * read a control register.
-	 * this is a bit more delay and cannot be optimized by the compiler
-	 * assuming one read takes 200 cycles and A8 is runing 1 GHz
-	 * somewhat conservative setting
-	 */
-	for (i = 0; i < 50*d; i++)
-		readl(CONTROL_STATUS);
-}
-
-static void main_pll_init_ti816x(void)
-{
-	u32 main_pll_ctrl = 0;
-
-	/* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
-	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
-	main_pll_ctrl &= 0xFFFFFFFB;
-	main_pll_ctrl |= BIT(2);
-	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-
-	/* Enable PLL by setting BIT3 in its ctrl reg */
-	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
-	main_pll_ctrl &= 0xFFFFFFF7;
-	main_pll_ctrl |= BIT(3);
-	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-
-	/* Write the values of N,P in the CTRL reg  */
-	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
-	main_pll_ctrl &= 0xFF;
-	main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8);
-	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-
-	/* Power up clock1-7 */
-	writel(0x0, &cmpll->mainpll_pwd);
-
-	/* Program the freq and divider values for clock1-7 */
-	writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1),
-		&cmpll->mainpll_freq1);
-	writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1);
-
-	writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2),
-		&cmpll->mainpll_freq2);
-	writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2);
-
-	writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3),
-		&cmpll->mainpll_freq3);
-	writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3);
-
-	writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4),
-		&cmpll->mainpll_freq4);
-	writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4);
-
-	writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5),
-		&cmpll->mainpll_freq5);
-	writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5);
-
-	writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6);
-
-	writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7);
-
-	/* Wait for PLL to lock */
-	while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7))
-		;
-
-	/* Put the PLL in normal mode, disable bypass */
-	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
-	main_pll_ctrl &= 0xFFFFFFFB;
-	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-}
-
-static void ddr_pll_bypass_ti816x(void)
-{
-	u32 ddr_pll_ctrl = 0;
-
-	/* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
-	ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
-	ddr_pll_ctrl &= 0xFFFFFFFB;
-	ddr_pll_ctrl |= BIT(2);
-	writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
-}
-
-static void ddr_pll_init_ti816x(void)
-{
-	u32 ddr_pll_ctrl = 0;
-	/* Enable PLL by setting BIT3 in its ctrl reg */
-	ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
-	ddr_pll_ctrl &= 0xFFFFFFF7;
-	ddr_pll_ctrl |= BIT(3);
-	writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
-
-	/* Write the values of N,P in the CTRL reg  */
-	ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
-	ddr_pll_ctrl &= 0xFF;
-	ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8);
-	writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
-
-	ddr_delay(10);
-
-	/* Power up clock1-5 */
-	writel(0x0, &cmpll->ddrpll_pwd);
-
-	/* Program the freq and divider values for clock1-3 */
-	writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
-	ddr_delay(1);
-	writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
-	writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2),
-		&cmpll->ddrpll_freq2);
-	writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2);
-	writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
-	ddr_delay(1);
-	writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
-	ddr_delay(1);
-	writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
-		&cmpll->ddrpll_freq3);
-	ddr_delay(1);
-	writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
-		&cmpll->ddrpll_freq3);
-
-	ddr_delay(5);
-
-	/* Wait for PLL to lock */
-	while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7))
-		;
-
-	/* Power up RCD */
-	writel(BIT(0), DDR_RCD);
-}
-
-static void peripheral_enable(void)
-{
-	/* Wake-up the l3_slow clock */
-	writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
-
-	/*
-	 * Note on Timers:
-	 * There are 8 timers(0-7) out of which timer 0 is a secure timer.
-	 * Timer 0 mux should not be changed
-	 *
-	 * To access the timer registers we need the to be
-	 * enabled which is what we do in the first step
-	 */
-
-	/* Enable timer1 */
-	writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl);
-	/* Select timer1 clock to be CLKIN (27MHz) */
-	writel(BIT(1), CM_TIMER1_CLKSEL);
-
-	/* Wait for timer1 to be ON-ACTIVE */
-	while (((readl(&cmalwon->l3slowclkstctrl)
-					& (0x80000<<1))>>20) != 1)
-		;
-	/* Wait for timer1 to be enabled */
-	while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0)
-		;
-	/* Active posted mode */
-	writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54));
-	while (readl(DM_TIMER1_BASE + 0x10) & BIT(0))
-		;
-	/* Start timer1  */
-	writel(BIT(0), (DM_TIMER1_BASE + 0x38));
-
-	/* eFuse */
-	writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL);
-	while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN)
-		;
-
-	/* Enable gpio0 */
-	writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl);
-	while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN)
-		;
-	writel((BIT(1) | BIT(8)), &cmalwon->gpio0clkctrl);
-
-	/* Enable gpio1 */
-	writel(PRCM_MOD_EN, &cmalwon->gpio1clkctrl);
-	while (readl(&cmalwon->gpio1clkctrl) != PRCM_MOD_EN)
-		;
-	writel((BIT(1) | BIT(8)), &cmalwon->gpio1clkctrl);
-
-	/* Enable spi */
-	writel(PRCM_MOD_EN, &cmalwon->spiclkctrl);
-	while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN)
-		;
-
-	/* Enable i2c0 */
-	writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl);
-	while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* Enable ethernet0 */
-	writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
-	writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
-	writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
-
-	/* Enable hsmmc */
-	writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl);
-	while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN)
-		;
-}
-
-void setup_clocks_for_console(void)
-{
-	/* Fix ROM code bug - from TI-PSP-04.00.02.14 */
-	writel(0x0, CM_SYSCLK10_CLKSEL);
-
-	ddr_pll_bypass_ti816x();
-
-	/* Enable uart0-2 */
-	writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
-	while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
-		;
-	writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl);
-	while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN)
-		;
-	writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl);
-	while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN)
-		;
-	while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
-		;
-}
-
-void setup_early_clocks(void)
-{
-	setup_clocks_for_console();
-}
-
-void prcm_init(void)
-{
-	/* Enable the control */
-	writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
-
-	main_pll_init_ti816x();
-	ddr_pll_init_ti816x();
-
-	/*
-	 * With clk freqs setup to desired values,
-	 * enable the required peripherals
-	 */
-	peripheral_enable();
-}
diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c
index f8434ec..5f970d9 100644
--- a/arch/arm/mach-omap2/am33xx/ddr.c
+++ b/arch/arm/mach-omap2/am33xx/ddr.c
@@ -182,14 +182,6 @@
  */
 void config_sdram(const struct emif_regs *regs, int nr)
 {
-#ifdef CONFIG_TI816X
-	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
-	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1);
-	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
-	writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl);   /* initially a large refresh period */
-	writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl);   /* trigger initialization           */
-	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
-#else
 	if (regs->zq_config) {
 		writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
 		writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
@@ -211,7 +203,6 @@
 	/* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
 	if (regs->ocp_config)
 		writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
-#endif
 }
 
 /**
diff --git a/arch/arm/mach-omap2/am33xx/ti816x_emif4.c b/arch/arm/mach-omap2/am33xx/ti816x_emif4.c
deleted file mode 100644
index 707ea80..0000000
--- a/arch/arm/mach-omap2/am33xx/ti816x_emif4.c
+++ /dev/null
@@ -1,165 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * ti816x_emif4.c
- *
- * TI816x emif4 configuration file
- *
- * Copyright (C) 2017, Konsulko Group
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <linux/delay.h>
-
-/*********************************************************************
- * Init DDR3 on TI816X EVM
- *********************************************************************/
-static void ddr_init_settings(const struct cmd_control *ctrl, int emif)
-{
-	/*
-	 * setup use_rank_delays to 1.  This is only necessary when
-	 * multiple ranks are in use.  Though the EVM does not have
-	 * multiple ranks, this is a good value to set.
-	 */
-	writel(1, DDRPHY_CONFIG_BASE + 0x134); // DATA0_REG_PHY_USE_RANK0_DELAYS
-	writel(1, DDRPHY_CONFIG_BASE + 0x1d8); // DATA1_REG_PHY_USE_RANK0_DELAYS
-	writel(1, DDRPHY_CONFIG_BASE + 0x27c); // DATA2_REG_PHY_USE_RANK0_DELAYS
-	writel(1, DDRPHY_CONFIG_BASE + 0x320); // DATA3_REG_PHY_USE_RANK0_DELAYS
-
-	config_cmd_ctrl(ctrl, emif);
-
-	/* for ddr3 this needs to be set to 1 */
-	writel(0x1, DDRPHY_CONFIG_BASE + 0x0F8); /* init mode */
-	writel(0x1, DDRPHY_CONFIG_BASE + 0x104);
-	writel(0x1, DDRPHY_CONFIG_BASE + 0x19C);
-	writel(0x1, DDRPHY_CONFIG_BASE + 0x1A8);
-	writel(0x1, DDRPHY_CONFIG_BASE + 0x240);
-	writel(0x1, DDRPHY_CONFIG_BASE + 0x24C);
-	writel(0x1, DDRPHY_CONFIG_BASE + 0x2E4);
-	writel(0x1, DDRPHY_CONFIG_BASE + 0x2F0);
-
-	/*
-	 * This represents the initial value for the leveling process.  The
-	 * value is a ratio - so 0x100 represents one cycle.  The real delay
-	 * is determined through the leveling process.
-	 *
-	 * During the leveling process, 0x20 is subtracted from the value, so
-	 * we have added that to the value we want to set.  We also set the
-	 * values such that byte3 completes leveling after byte2 and byte1
-	 * after byte0.
-	 */
-	writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0F0); /*  data0 writelvl init ratio */
-	writel(0x0, DDRPHY_CONFIG_BASE + 0x0F4);   /*   */
-	writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x194); /*  data1 writelvl init ratio */
-	writel(0x0, DDRPHY_CONFIG_BASE + 0x198);   /*   */
-	writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x238); /*  data2 writelvl init ratio */
-	writel(0x0, DDRPHY_CONFIG_BASE + 0x23c);   /*   */
-	writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2dc); /*  data3 writelvl init ratio */
-	writel(0x0, DDRPHY_CONFIG_BASE + 0x2e0);   /*   */
-
-
-	writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0FC); /*  data0 gatelvl init ratio */
-	writel(0x0, DDRPHY_CONFIG_BASE + 0x100);
-	writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x1A0); /*  data1 gatelvl init ratio */
-	writel(0x0, DDRPHY_CONFIG_BASE + 0x1A4);
-	writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x244); /*  data2 gatelvl init ratio */
-	writel(0x0, DDRPHY_CONFIG_BASE + 0x248);
-	writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2E8); /*  data3 gatelvl init ratio */
-	writel(0x0, DDRPHY_CONFIG_BASE + 0x2EC);
-
-	writel(0x5, DDRPHY_CONFIG_BASE + 0x00C);     /* cmd0 io config - output impedance of pad */
-	writel(0x5, DDRPHY_CONFIG_BASE + 0x010);     /* cmd0 io clk config - output impedance of pad */
-	writel(0x5, DDRPHY_CONFIG_BASE + 0x040);     /* cmd1 io config - output impedance of pad */
-	writel(0x5, DDRPHY_CONFIG_BASE + 0x044);     /* cmd1 io clk config - output impedance of pad */
-	writel(0x5, DDRPHY_CONFIG_BASE + 0x074);     /* cmd2 io config - output impedance of pad */
-	writel(0x5, DDRPHY_CONFIG_BASE + 0x078);     /* cmd2 io clk config - output impedance of pad */
-	writel(0x4, DDRPHY_CONFIG_BASE + 0x0A8);     /* data0 io config - output impedance of pad */
-	writel(0x4, DDRPHY_CONFIG_BASE + 0x0AC);     /* data0 io clk config - output impedance of pad */
-	writel(0x4, DDRPHY_CONFIG_BASE + 0x14C);     /* data1 io config - output impedance of pa     */
-	writel(0x4, DDRPHY_CONFIG_BASE + 0x150);     /* data1 io clk config - output impedance of pad */
-	writel(0x4, DDRPHY_CONFIG_BASE + 0x1F0);     /* data2 io config - output impedance of pa */
-	writel(0x4, DDRPHY_CONFIG_BASE + 0x1F4);     /* data2 io clk config - output impedance of pad */
-	writel(0x4, DDRPHY_CONFIG_BASE + 0x294);     /* data3 io config - output impedance of pa */
-	writel(0x4, DDRPHY_CONFIG_BASE + 0x298);     /* data3 io clk config - output impedance of pad */
-}
-
-static void ddr3_sw_levelling(const struct ddr_data *data, int emif)
-{
-	/* Set the correct value to DDR_VTP_CTRL_0 */
-	writel(0x6, (DDRPHY_CONFIG_BASE + 0x358));
-
-	writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x108));
-	writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x1AC));
-	writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x250));
-	writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x2F4));
-
-	writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x0DC));
-	writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x180));
-	writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x224));
-	writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x2C8));
-
-	writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x120));
-	writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x1C4));
-	writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x268));
-	writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x30C));
-
-	writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x0C8));
-	writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x16C));
-	writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x210));
-	writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x2B4));
-}
-
-static struct dmm_lisa_map_regs *hw_lisa_map_regs =
-				(struct dmm_lisa_map_regs *)DMM_BASE;
-
-#define DMM_PAT_BASE_ADDR		(DMM_BASE + 0x420)
-void config_dmm(const struct dmm_lisa_map_regs *regs)
-{
-	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
-	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
-	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
-	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
-
-	writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
-	writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
-	writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
-	writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
-
-	/* Enable Tiled Access */
-	writel(0x80000000, DMM_PAT_BASE_ADDR);
-}
-
-void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl,
-		const struct emif_regs *regs,
-		const struct dmm_lisa_map_regs *lisa_regs, int nrs)
-{
-	int i;
-
-	enable_emif_clocks();
-
-	for (i = 0; i < nrs; i++)
-		ddr_init_settings(ctrl, i);
-
-	enable_dmm_clocks();
-
-	/* Program the DMM to for non-interleaved configuration */
-	config_dmm(lisa_regs);
-
-	/* Program EMIF CFG Registers */
-	for (i = 0; i < nrs; i++) {
-		set_sdram_timings(regs, i);
-		config_sdram(regs, i);
-	}
-
-	udelay(1000);
-	for (i = 0; i < nrs; i++)
-		ddr3_sw_levelling(data, i);
-
-	udelay(50000);	/* Some delay needed */
-}
diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c
index 9a342a1..a2dd5f6 100644
--- a/arch/arm/mach-omap2/boot-common.c
+++ b/arch/arm/mach-omap2/boot-common.c
@@ -75,23 +75,6 @@
 	if (boot_device == BOOT_DEVICE_QSPI_4)
 		boot_device = BOOT_DEVICE_SPI;
 #endif
-#ifdef CONFIG_TI816X
-	/*
-	 * On PG2.0 and later TI816x the values we get when booting are not the
-	 * same as on PG1.0, which is what the defines are based on.  Update
-	 * them as needed.
-	 */
-	if (get_cpu_rev() != 1) {
-		if (boot_device == 0x05) {
-			omap_boot_params->boot_device = BOOT_DEVICE_NAND;
-			boot_device = BOOT_DEVICE_NAND;
-		}
-		if (boot_device == 0x08) {
-			omap_boot_params->boot_device = BOOT_DEVICE_MMC1;
-			boot_device = BOOT_DEVICE_MMC1;
-		}
-	}
-#endif
 	/*
 	 * When booting from peripheral booting, the boot device is not usable
 	 * as-is (unless there is support for it), so the boot device is instead
@@ -183,8 +166,7 @@
 
 	gd->arch.omap_boot_mode = boot_mode;
 
-#if !defined(CONFIG_TI816X) && \
-    !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX)
+#if !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX)
 
 	/* CH flags */
 
diff --git a/board/ti/ti816x/Kconfig b/board/ti/ti816x/Kconfig
deleted file mode 100644
index 95973b4..0000000
--- a/board/ti/ti816x/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_TI816X_EVM
-
-config SYS_BOARD
-	default "ti816x"
-
-config SYS_VENDOR
-	default "ti"
-
-config SYS_SOC
-	default "am33xx"
-
-config SYS_CONFIG_NAME
-	default "ti816x_evm"
-
-endif
diff --git a/board/ti/ti816x/MAINTAINERS b/board/ti/ti816x/MAINTAINERS
deleted file mode 100644
index fd9a98f..0000000
--- a/board/ti/ti816x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TI816X BOARD
-M:	Tom Rini <trini@konsulko.com>
-S:	Maintained
-F:	board/ti/ti816x/
-F:	include/configs/ti816x_evm.h
-F:	configs/ti816x_evm_defconfig
diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile
deleted file mode 100644
index f12712a..0000000
--- a/board/ti/ti816x/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
-# Antoine Tenart, <atenart@adeneo-embedded.com>
-#
-# Based on TI-PSP-04.00.02.14 :
-#
-# Copyright (C) 2009, Texas Instruments, Incorporated
-
-obj-y	:= evm.o
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
deleted file mode 100644
index 8c70835..0000000
--- a/board/ti/ti816x/evm.c
+++ /dev/null
@@ -1,140 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * evm.c
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- */
-
-#include <common.h>
-#include <env.h>
-#include <init.h>
-#include <net.h>
-#include <spl.h>
-#include <asm/cache.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
-#if defined(CONFIG_MTD_RAW_NAND)
-	gpmc_init();
-#endif
-	return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	uint8_t mac_addr[6];
-	uint32_t mac_hi, mac_lo;
-	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
-		printf("<ethaddr> not set. Reading from E-fuse\n");
-		/* try reading mac address from efuse */
-		mac_lo = readl(&cdev->macid0l);
-		mac_hi = readl(&cdev->macid0h);
-		mac_addr[0] = mac_hi & 0xFF;
-		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
-		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
-		mac_addr[4] = mac_lo & 0xFF;
-		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
-		if (is_valid_ethaddr(mac_addr))
-			eth_env_set_enetaddr("ethaddr", mac_addr);
-		else
-			printf("Unable to read MAC address. Set <ethaddr>\n");
-	}
-
-	return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-static struct module_pin_mux mmc_pin_mux[] = {
-	{ OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
-	{ OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
-	{ OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
-	{ OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
-	{ OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
-	{ OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
-	{ OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
-	{ -1 },
-};
-
-void set_uart_mux_conf(void) {}
-
-void set_mux_conf_regs(void)
-{
-	configure_module_pin_mux(mmc_pin_mux);
-}
-
-/*
- * EMIF Paramters.  Refer the EMIF register documentation and the
- * memory datasheet for details.  This is for 796 MHz.
- */
-#define EMIF_TIM1   0x1779C9FE
-#define EMIF_TIM2   0x50608074
-#define EMIF_TIM3   0x009F857F
-#define EMIF_SDREF  0x10001841
-#define EMIF_SDCFG  0x62A73832
-#define EMIF_PHYCFG 0x00000110
-static const struct emif_regs ddr3_emif_regs = {
-	.sdram_config		= EMIF_SDCFG,
-	.ref_ctrl		= EMIF_SDREF,
-	.sdram_tim1		= EMIF_TIM1,
-	.sdram_tim2		= EMIF_TIM2,
-	.sdram_tim3		= EMIF_TIM3,
-	.emif_ddr_phy_ctlr_1	= EMIF_PHYCFG,
-};
-
-static const struct cmd_control ddr3_ctrl = {
-	.cmd0csratio	= 0x100,
-	.cmd0iclkout	= 0x001,
-	.cmd1csratio	= 0x100,
-	.cmd1iclkout	= 0x001,
-	.cmd2csratio	= 0x100,
-	.cmd2iclkout	= 0x001,
-};
-
-/* These values are obtained from the CCS app */
-#define RD_DQS_GATE	(0x1B3)
-#define RD_DQS		(0x35)
-#define WR_DQS		(0x93)
-static struct ddr_data ddr3_data = {
-	.datardsratio0		= ((RD_DQS<<10) | (RD_DQS<<0)),
-	.datawdsratio0		= ((WR_DQS<<10) | (WR_DQS<<0)),
-	.datawiratio0		= ((0x20<<10) | 0x20<<0),
-	.datagiratio0		= ((0x20<<10) | 0x20<<0),
-	.datafwsratio0		= ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
-	.datawrsratio0		= (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
-};
-
-static const struct dmm_lisa_map_regs evm_lisa_map_regs = {
-	.dmm_lisa_map_0 = 0x00000000,
-	.dmm_lisa_map_1 = 0x00000000,
-	.dmm_lisa_map_2 = 0x80640300,
-	.dmm_lisa_map_3 = 0xC0640320,
-};
-
-void sdram_init(void)
-{
-	/*
-	 * Pass in our DDR3 config information and that we have 2 EMIFs to
-	 * configure.
-	 */
-	config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs,
-			&evm_lisa_map_regs, 2);
-}
-#endif /* CONFIG_SPL_BUILD */
diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
deleted file mode 100644
index a4bc993..0000000
--- a/configs/ti816x_evm_defconfig
+++ /dev/null
@@ -1,82 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4031ff00
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x1C0000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="dm8168-evm"
-CONFIG_SPL_TEXT_BASE=0x40400000
-CONFIG_TI816X=y
-CONFIG_TARGET_TI816X_EVM=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x1E0000
-CONFIG_SYS_CLK_FREQ=27000000
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyO2,115200n8 noinitrd earlyprintk"
-CONFIG_BOOTCOMMAND="mmc rescan;fatload mmc 0 ${loadaddr} uImage;bootm ${loadaddr}"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_MISC_INIT_R is not set
-CONFIG_SPL_MAX_SIZE=0xfff1b400
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_NAND_DRIVERS=y
-CONFIG_SPL_NAND_ECC=y
-CONFIG_SPL_NAND_BASE=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_BOOTP_DNS2=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RETRY_COUNT=10
-CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
-CONFIG_SYS_NAND_PAGE_SIZE=0x800
-CONFIG_SYS_NAND_OOBSIZE=0x40
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
-CONFIG_MII=y
-CONFIG_DRIVER_TI_EMAC=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-# CONFIG_USE_PRIVATE_LIBGCC is not set
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 05b14d2..5e81698 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -744,7 +744,6 @@
 config SYS_I2C_BUS_MAX
 	int "Max I2C busses"
 	depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA
-	default 2 if TI816X
 	default 3 if OMAP34XX || AM33XX || AM43XX
 	default 4 if ARCH_SOCFPGA || OMAP44XX
 	default 5 if OMAP54XX
diff --git a/drivers/net/ti/davinci_emac.c b/drivers/net/ti/davinci_emac.c
index 29d2fc9..034877a 100644
--- a/drivers/net/ti/davinci_emac.c
+++ b/drivers/net/ti/davinci_emac.c
@@ -833,9 +833,9 @@
 #endif
 	}
 
-#if defined(CONFIG_TI816X) || (defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
 		defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
-			!defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE))
+			!defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE)
 	for (i = 0; i < num_phy; i++) {
 		if (phy[i].is_phy_connected(i))
 			phy[i].auto_negotiate(i);
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
deleted file mode 100644
index ac6d46f..0000000
--- a/include/configs/ti816x_evm.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * ti816x_evm.h
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- */
-
-#ifndef __CONFIG_TI816X_EVM_H
-#define __CONFIG_TI816X_EVM_H
-
-#include <configs/ti_armv7_omap.h>
-#include <asm/arch/omap.h>
-
-#define CFG_EXTRA_ENV_SETTINGS	\
-	DEFAULT_LINUX_BOOT_ENV
-
-/* Clock Defines */
-#define V_OSCK          24000000    /* Clock output from T2 */
-#define V_SCLK          (V_OSCK >> 1)
-
-#define CFG_MAX_RAM_BANK_SIZE	(2048 << 20)	/* 2048MB */
-#define CFG_SYS_SDRAM_BASE		0x80000000
-
-/**
- * Platform/Board specific defs
- */
-#define CFG_SYS_TIMERBASE    0x4802E000
-
-/*
- * NS16550 Configuration
- */
-#define CFG_SYS_NS16550_CLK      (48000000)
-#define CFG_SYS_NS16550_COM1     0x48024000  /* Base EVM has UART2 */
-
-/* allow overwriting serial config and ethaddr */
-
-
-/*
- * GPMC NAND block.  We support 1 device and the physical address to
- * access CS0 at is 0x8000000.
- */
-#define CFG_SYS_NAND_BASE		0x8000000
-
-/* NAND: SPL related configs */
-
-/* NAND: device related configs */
-/* NAND: driver related configs */
-#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
-					 10, 11, 12, 13, 14, 15, 16, 17, \
-					 18, 19, 20, 21, 22, 23, 24, 25, \
-					 26, 27, 28, 29, 30, 31, 32, 33, \
-					 34, 35, 36, 37, 38, 39, 40, 41, \
-					 42, 43, 44, 45, 46, 47, 48, 49, \
-					 50, 51, 52, 53, 54, 55, 56, 57, }
-
-#define CFG_SYS_NAND_ECCSIZE		512
-#define CFG_SYS_NAND_ECCBYTES	14
-
-/* SPL */
-/* Defines for SPL */
-
-#endif