diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 7b38e83..fe34755 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -73,6 +73,12 @@
 	help
 	  ODT EN value from vendor DRAM settings.
 
+config DRAM_SUN50I_H616_TPR0
+	hex "H616 DRAM TPR0 parameter"
+	default 0x0
+	help
+	  TPR0 value from vendor DRAM settings.
+
 config DRAM_SUN50I_H616_TPR10
 	hex "H616 DRAM TPR10 parameter"
 	help
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index f5d8718..44bb153 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -773,6 +773,39 @@
 	}
 }
 
+static void mctl_phy_ca_bit_delay_compensation(struct dram_para *para)
+{
+	u32 val, *ptr;
+	int i;
+
+	if (para->tpr0 & BIT(30))
+		val = (para->tpr0 >> 7) & 0x3e;
+	else
+		val = (para->tpr10 >> 3) & 0x1e;
+
+	ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x780);
+	for (i = 0; i < 32; i++)
+		writel(val, &ptr[i]);
+
+	val = (para->tpr10 << 1) & 0x1e;
+	writel(val, SUNXI_DRAM_PHY0_BASE + 0x7dc);
+	writel(val, SUNXI_DRAM_PHY0_BASE + 0x7e0);
+
+	/* following configuration is DDR3 specific */
+	val = (para->tpr10 >> 7) & 0x1e;
+	writel(val, SUNXI_DRAM_PHY0_BASE + 0x7d4);
+	if (para->ranks == 2) {
+		val = (para->tpr10 >> 11) & 0x1e;
+		writel(val, SUNXI_DRAM_PHY0_BASE + 0x79c);
+	}
+	if (para->tpr0 & BIT(31)) {
+		val = (para->tpr0 << 1) & 0x3e;
+		writel(val, SUNXI_DRAM_PHY0_BASE + 0x78c);
+		writel(val, SUNXI_DRAM_PHY0_BASE + 0x7a4);
+		writel(val, SUNXI_DRAM_PHY0_BASE + 0x7b8);
+	}
+}
+
 static bool mctl_phy_init(struct dram_para *para)
 {
 	struct sunxi_mctl_com_reg * const mctl_com =
@@ -807,17 +840,8 @@
 	for (i = 0; i < ARRAY_SIZE(phy_init); i++)
 		writel(phy_init[i], &ptr[i]);
 
-	if (para->tpr10 & TPR10_CA_BIT_DELAY) {
-		ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x780);
-		for (i = 0; i < 32; i++)
-			writel(0x16, &ptr[i]);
-		writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x78c);
-		writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7a4);
-		writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7b8);
-		writel(0x8, SUNXI_DRAM_PHY0_BASE + 0x7d4);
-		writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7dc);
-		writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7e0);
-	}
+	if (para->tpr10 & TPR10_CA_BIT_DELAY)
+		mctl_phy_ca_bit_delay_compensation(para);
 
 	writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x3dc);
 	writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x45c);
@@ -1110,6 +1134,7 @@
 		.dx_dri = CONFIG_DRAM_SUN50I_H616_DX_DRI,
 		.ca_dri = CONFIG_DRAM_SUN50I_H616_CA_DRI,
 		.odt_en = CONFIG_DRAM_SUN50I_H616_ODT_EN,
+		.tpr0 = CONFIG_DRAM_SUN50I_H616_TPR0,
 		.tpr10 = CONFIG_DRAM_SUN50I_H616_TPR10,
 		.tpr11 = CONFIG_DRAM_SUN50I_H616_TPR11,
 		.tpr12 = CONFIG_DRAM_SUN50I_H616_TPR12,