commit 9e1ba0afd33018559c49a38e4a84ece2a9553eaf
author Svyatoslav Ryhel <clamor95@gmail.com> Tue Feb 14 19:35:33 2023 +0200
committer Tom <twarren@nvidia.com> Thu Feb 23 12:55:37 2023 -0700
tree c79c8fdf09fa539ef57db0507c3d25451b30fd14
parent 018e737ca70b45584ddb775a457380ec940fa3c4

board: tegra124: switch to updated pre-dm i2c write

Configure PMIC for early stages using updated i2c write.

Tested-by: Thierry Reding <treding@nvidia.com> # Jetson TK1 T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>

board/nvidia/venice2/as3722_init.c

diff --git a/board/nvidia/venice2/as3722_init.c b/board/nvidia/venice2/as3722_init.c
index ba67654..395bdd9 100644
--- a/board/nvidia/venice2/as3722_init.c
+++ b/board/nvidia/venice2/as3722_init.c
@@ -9,25 +9,42 @@
 #include <asm/io.h>
 #include <asm/arch-tegra/tegra_i2c.h>
 #include <linux/delay.h>
-#include "as3722_init.h"
 
-/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
+/* AS3722-PMIC-specific early init regs */
 
-void tegra_i2c_ll_write_addr(uint addr, uint config)
-{
-	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+#define AS3722_I2C_ADDR		0x80
 
-	writel(addr, &reg->cmd_addr0);
-	writel(config, &reg->cnfg);
-}
+#define AS3722_SD0VOLTAGE_REG	0x00	/* CPU */
+#define AS3722_SD1VOLTAGE_REG	0x01	/* CORE, already set by OTP */
+#define AS3722_SD6VOLTAGE_REG	0x06	/* GPU */
+#define AS3722_SDCONTROL_REG	0x4D
 
-void tegra_i2c_ll_write_data(uint data, uint config)
-{
-	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+#define AS3722_LDO2VOLTAGE_REG	0x12	/* VPP_FUSE */
+#define AS3722_LDO6VOLTAGE_REG	0x16	/* VDD_SDMMC */
+#define AS3722_LDCONTROL_REG	0x4E
 
-	writel(data, &reg->cmd_data1);
-	writel(config, &reg->cnfg);
-}
+#if defined(CONFIG_TARGET_VENICE2)
+#define AS3722_SD0VOLTAGE_DATA	(0x2800 | AS3722_SD0VOLTAGE_REG)
+#else /* TK1 or Nyan-Big */
+#define AS3722_SD0VOLTAGE_DATA	(0x3C00 | AS3722_SD0VOLTAGE_REG)
+#endif
+#define AS3722_SD0CONTROL_DATA	(0x0100 | AS3722_SDCONTROL_REG)
+
+#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_CEI_TK1_SOM)
+#define AS3722_SD1VOLTAGE_DATA	(0x2800 | AS3722_SD1VOLTAGE_REG)
+#define AS3722_SD1CONTROL_DATA	(0x0200 | AS3722_SDCONTROL_REG)
+#endif
+
+#define AS3722_SD6CONTROL_DATA	(0x4000 | AS3722_SDCONTROL_REG)
+#define AS3722_SD6VOLTAGE_DATA	(0x2800 | AS3722_SD6VOLTAGE_REG)
+
+#define AS3722_LDO2CONTROL_DATA	(0x0400 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO2VOLTAGE_DATA	(0x1000 | AS3722_LDO2VOLTAGE_REG)
+
+#define AS3722_LDO6CONTROL_DATA	(0x4000 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO6VOLTAGE_DATA	(0x3F00 | AS3722_LDO6VOLTAGE_REG)
+
+/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
 
 void pmic_enable_cpu_vdd(void)
 {
@@ -37,8 +54,8 @@
 	/* Set up VDD_CORE, for boards where OTP is incorrect*/
 	debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
 	/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
-	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
-	tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	tegra_i2c_ll_write(AS3722_I2C_ADDR,
+			   AS3722_SD1VOLTAGE_DATA);
 	/*
 	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
 	 * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
@@ -51,8 +68,8 @@
 	 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
 	 * First set VDD to 1.0V, then enable the VDD regulator.
 	 */
-	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
-	tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	tegra_i2c_ll_write(AS3722_I2C_ADDR,
+			   AS3722_SD0VOLTAGE_DATA);
 	/*
 	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
 	 * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
@@ -64,8 +81,8 @@
 	 * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
 	 * First set VDD to 1.0V, then enable the VDD regulator.
 	 */
-	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
-	tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	tegra_i2c_ll_write(AS3722_I2C_ADDR,
+			   AS3722_SD6VOLTAGE_DATA);
 	/*
 	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
 	 * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
@@ -77,8 +94,8 @@
 	 * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
 	 * First set VDD to 1.2V, then enable the VDD regulator.
 	 */
-	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
-	tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	tegra_i2c_ll_write(AS3722_I2C_ADDR,
+			   AS3722_LDO2VOLTAGE_DATA);
 	/*
 	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
 	 * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
@@ -93,8 +110,8 @@
 	 * NOTE: We do this early because doing it later seems to hose the CPU
 	 * power rail/partition startup. Need to debug.
 	 */
-	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
-	tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	tegra_i2c_ll_write(AS3722_I2C_ADDR,
+			   AS3722_LDO6VOLTAGE_DATA);
 	/*
 	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
 	 * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);