tree 6fac1fbe6edbeef3aeda7e874b28ca30829118d6
parent ad6cca1a73f2df54c182c9de8703dc4bf7507471
author Gabor Juhos <juhosg@openwrt.org> 1358305501 +0000
committer Daniel Schwierzeck <daniel.schwierzeck@gmail.com> 1358885374 +0100

MIPS: start{, 64}.S: fill branch delay slots with NOP instructions

The romReserved and romExcHandle handlers are
accessed by a branch instruction however the
delay slots of those instructions are not filled.

Because the start.S uses the 'noreorder' directive,
the assembler will not fill the delay slots either,
and leads to the following assembly code:

  0000056c <romReserved>:
   56c:   1000ffff        b       56c <romReserved>

  00000570 <romExcHandle>:
   570:   1000ffff        b       570 <romExcHandle>

In the resulting code, the second branch instruction
is placed into the delay slot of the first branch
instruction, which is not allowed on the MIPS
architecture.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>