tree 27a3b69531fc9a55d833ff44a42d14b669feda29
parent c23ad846e99df4175e048af87625fc061ac6d5c9
author Paweł Anikiel <pan@semihalf.com> 1655462846 +0200
committer Tien Fong Chee <tien.fong.chee@intel.com> 1656658635 +0800

socfpga: arria10: Allow dcache_enable before relocation

Before relocating to SDRAM, the ECC is initialized by clearing the
whole SDRAM. In order to speed this up, dcache_enable is used (see
sdram_init_ecc_bits).

Since commit 503eea451903 ("arm: cp15: update DACR value to activate
access control"), this no longer works, because running code in OCRAM
with the XN bit set causes a page fault. Override dram_bank_mmu_setup
to disable XN in the OCRAM and setup DRAM dcache before relocation.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>