commit 9d3bfc3342d5a0f89c5a6023c55b160a717a9b1c
author Johan Jonker <jbx6244@gmail.com> Fri Sep 09 22:18:45 2022 +0200
committer Kever Yang <kever.yang@rock-chips.com> Mon Dec 19 10:56:12 2022 +0800
tree a2f7eebdcdea43d2534ffef27c114700f8a6d4c0
parent 32cb5bc2e68e7360e1564acd81e31fd87b4110e6

rockchip: rk3128-cru: sync the clock dt-binding header from Linux

In order to update the DT for rk3128
sync the clock dt-binding header.
This is the state as of v6.0 in Linux.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

drivers/clk/rockchip/clk_rk3128.c

diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c
index d5b2b63..13e176c 100644
--- a/drivers/clk/rockchip/clk_rk3128.c
+++ b/drivers/clk/rockchip/clk_rk3128.c
@@ -438,7 +438,7 @@
 			     VIO1_SEL_GPLL << VIO1_PLL_SHIFT |
 			     (src_clk_div - 1) << VIO1_DIV_SHIFT);
 		break;
-	case DCLK_LCDC:
+	case DCLK_VOP:
 		if (pll_para_config(hz, &cpll_config))
 			return -1;
 		rkclk_set_pll(cru, CLK_CODEC, &cpll_config);
@@ -471,7 +471,7 @@
 		div = (con >> 8) & 0x1f;
 		parent = GPLL_HZ;
 		break;
-	case DCLK_LCDC:
+	case DCLK_VOP:
 		con = readl(&cru->cru_clksel_con[27]);
 		div = (con >> 8) & 0xfff;
 		parent = rkclk_pll_get_rate(cru, CLK_CODEC);
@@ -497,7 +497,7 @@
 		return rk3128_peri_get_pclk(priv->cru, clk->id);
 	case SCLK_SARADC:
 		return rk3128_saradc_get_clk(priv->cru);
-	case DCLK_LCDC:
+	case DCLK_VOP:
 	case ACLK_VIO0:
 	case ACLK_VIO1:
 		return rk3128_vop_get_rate(priv->cru, clk->id);
@@ -515,7 +515,7 @@
 	switch (clk->id) {
 	case 0 ... 63:
 		return 0;
-	case DCLK_LCDC:
+	case DCLK_VOP:
 	case ACLK_VIO0:
 	case ACLK_VIO1:
 		new_rate = rk3128_vop_set_clk(priv->cru,