diff --git a/board/renesas/blanche/Kconfig b/board/renesas/blanche/Kconfig
new file mode 100644
index 0000000..ac4730a
--- /dev/null
+++ b/board/renesas/blanche/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_BLANCHE
+
+config SYS_BOARD
+	default "blanche"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "blanche"
+
+endif
diff --git a/board/renesas/blanche/Makefile b/board/renesas/blanche/Makefile
new file mode 100644
index 0000000..bdbfb29
--- /dev/null
+++ b/board/renesas/blanche/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/blanche/Makefile
+#
+# Copyright (C) 2016 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y	:= blanche.o qos.o ../rcar-common/common.o
diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c
new file mode 100644
index 0000000..717c169
--- /dev/null
+++ b/board/renesas/blanche/blanche.c
@@ -0,0 +1,458 @@
+/*
+ * board/renesas/blanche/blanche.c
+ *     This file is blanche board support.
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/sh_sdhi.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <mmc.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pin_db {
+	u32	addr;	/* register address */
+	u32	mask;	/* mask value */
+	u32	val;	/* setting value */
+};
+
+#define	PMMR		0xE6060000
+#define	GPSR10		0xE606002C
+#define	PUPR3		0xE606010C
+#define	PUPR10		0xE6060128
+#define	PUPR11		0xE606012C
+
+#define	CPG_PLL1CR	0xE6150028
+#define	CPG_PLL3CR	0xE61500DC
+
+#define	SetREG(x) \
+	writel((readl((x)->addr) & ~((x)->mask)) | ((x)->val), (x)->addr)
+
+#define	SetGuardREG(x)				\
+{ \
+	u32	val; \
+	val = (readl((x)->addr) & ~((x)->mask)) | ((x)->val); \
+	writel(~val, PMMR); \
+	writel(val, (x)->addr); \
+}
+
+struct pin_db	pin_guard[] = {
+	{ GPSR10,	0xFFFFFFFF,	0x04006000 },
+};
+
+struct pin_db	pin_tbl[] = {
+	{ PUPR3,	0xFFFFFFFF,	0x0803FF40 },
+	{ PUPR10,	0xFFFFFFFF,	0xC0438001 },
+	{ PUPR11,	0xFFFFFFFF,	0x0FC00007 },
+};
+
+void pin_init(void)
+{
+	struct pin_db	*db;
+
+	for (db = pin_guard; db < &pin_guard[sizeof(pin_guard)/sizeof(struct pin_db)]; db++) {
+		SetGuardREG(db);
+	}
+	for (db = pin_tbl; db < &pin_tbl[sizeof(pin_tbl) /sizeof(struct pin_db)]; db++) {
+		SetREG(db);
+	}
+}
+
+#define s_init_wait(cnt) \
+		({	\
+			volatile u32 i = 0x10000 * cnt;	\
+			while (i > 0)	\
+				i--;	\
+		})
+
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+	u32 cpu_type;
+
+	cpu_type = rmobile_get_cpu_type();
+	if (cpu_type == 0x4A) {
+		writel(0x4D000000, CPG_PLL1CR);
+		writel(0x4F000000, CPG_PLL3CR);
+	}
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* QoS(Quality-of-Service) Init */
+	qos_init();
+
+	/* SCIF Init */
+	pin_init();
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+	struct rcar_lbsc *lbsc = (struct rcar_lbsc *)LBSC_BASE;
+	struct rcar_dbsc3 *dbsc3_0 = (struct rcar_dbsc3 *)DBSC3_0_BASE;
+
+	/* LBSC */
+	writel(0x00000020, &lbsc->cs0ctrl);
+	writel(0x00000020, &lbsc->cs1ctrl);
+	writel(0x00002020, &lbsc->ecs0ctrl);
+	writel(0x00002020, &lbsc->ecs1ctrl);
+
+	writel(0x2A103320, &lbsc->cswcr0);
+	writel(0x2A103320, &lbsc->cswcr1);
+	writel(0x19102110, &lbsc->ecswcr0);
+	writel(0x19102110, &lbsc->ecswcr1);
+
+	/* DBSC3 */
+	s_init_wait(10);
+
+	writel(0x0000A55A, &dbsc3_0->dbpdlck);
+
+	writel(0x21000000, &dbsc3_0->dbcmd);		/* opc=RstH (RESET => H) */
+	writel(0x11000000, &dbsc3_0->dbcmd);		/* opc=PDXt(CKE=H) */
+	writel(0x10000000, &dbsc3_0->dbcmd);		/* opc=PDEn(CKE=L) */
+
+	/* Stop Auto-Calibration */
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x80000000, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
+
+	/* PLLCR: PLL Control Register */
+	writel(0x00000006, &dbsc3_0->dbpdrga);
+	writel(0x0001C000, &dbsc3_0->dbpdrgd);	// > DDR1440
+
+	/* DXCCR: DATX8 Common Configuration Register */
+	writel(0x0000000F, &dbsc3_0->dbpdrga);
+	writel(0x00181EE4, &dbsc3_0->dbpdrgd);
+
+	/* DSGCR	:DDR System General Configuration Register */
+	writel(0x00000010, &dbsc3_0->dbpdrga);
+	writel(0xF00464DB, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000061, &dbsc3_0->dbpdrga);
+	writel(0x0000008D, &dbsc3_0->dbpdrgd);
+
+	/* Re-Execute ZQ calibration */
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x00000073, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000007, &dbsc3_0->dbkind);
+	writel(0x0F030A02, &dbsc3_0->dbconf0);
+	writel(0x00000001, &dbsc3_0->dbphytype);
+	writel(0x00000000, &dbsc3_0->dbbl);
+
+	writel(0x0000000B, &dbsc3_0->dbtr0);	// tCL=11
+	writel(0x00000008, &dbsc3_0->dbtr1);	// tCWL=8
+	writel(0x00000000, &dbsc3_0->dbtr2);	// tAL=0
+	writel(0x0000000B, &dbsc3_0->dbtr3);	// tRCD=11
+	writel(0x000C000B, &dbsc3_0->dbtr4);	// tRPA=12,tRP=11
+	writel(0x00000027, &dbsc3_0->dbtr5);	// tRC = 39
+	writel(0x0000001C, &dbsc3_0->dbtr6);	// tRAS = 28
+	writel(0x00000006, &dbsc3_0->dbtr7);	// tRRD = 6
+	writel(0x00000020, &dbsc3_0->dbtr8);	// tRFAW = 32
+	writel(0x00000008, &dbsc3_0->dbtr9);	// tRDPR = 8
+	writel(0x0000000C, &dbsc3_0->dbtr10);	// tWR = 12
+	writel(0x00000009, &dbsc3_0->dbtr11);	// tRDWR = 9
+	writel(0x00000012, &dbsc3_0->dbtr12);	// tWRRD = 18
+	writel(0x000000D0, &dbsc3_0->dbtr13);	// tRFC = 208
+	writel(0x00140005, &dbsc3_0->dbtr14);
+	writel(0x00050004, &dbsc3_0->dbtr15);
+	writel(0x70233005, &dbsc3_0->dbtr16);		/* DQL = 35, WDQL = 5 */
+	writel(0x000C0000, &dbsc3_0->dbtr17);
+	writel(0x00000300, &dbsc3_0->dbtr18);
+	writel(0x00000040, &dbsc3_0->dbtr19);
+	writel(0x00000001, &dbsc3_0->dbrnk0);
+	writel(0x00020001, &dbsc3_0->dbadj0);
+	writel(0x20082004, &dbsc3_0->dbadj2);		/* blanche QoS rev0.1 */
+	writel(0x00020002, &dbsc3_0->dbwt0cnf0);	/* 1600 */
+	writel(0x0000001F, &dbsc3_0->dbwt0cnf4);
+
+	while ((readl(&dbsc3_0->dbdfistat) & 0x00000001) != 0x00000001);
+	writel(0x00000011, &dbsc3_0->dbdficnt);
+
+	/* PGCR1	:PHY General Configuration Register 1 */
+	writel(0x00000003, &dbsc3_0->dbpdrga);
+	writel(0x0300C4E1, &dbsc3_0->dbpdrgd);		/* DDR3 */
+
+	/* PGCR2: PHY General Configuration Registers 2 */
+	writel(0x00000023, &dbsc3_0->dbpdrga);
+	writel(0x00FCDB60, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000011, &dbsc3_0->dbpdrga);
+	writel(0x1000040B, &dbsc3_0->dbpdrgd);
+
+	/* DTPR0	:DRAM Timing Parameters Register 0 */
+	writel(0x00000012, &dbsc3_0->dbpdrga);
+	writel(0x9D9CBB66, &dbsc3_0->dbpdrgd);
+
+	/* DTPR1	:DRAM Timing Parameters Register 1 */
+	writel(0x00000013, &dbsc3_0->dbpdrga);
+	writel(0x1A868400, &dbsc3_0->dbpdrgd);
+
+	/* DTPR2	::DRAM Timing Parameters Register 2 */
+	writel(0x00000014, &dbsc3_0->dbpdrga);
+	writel(0x300214D8, &dbsc3_0->dbpdrgd);
+
+	/* MR0	:Mode Register 0 */
+	writel(0x00000015, &dbsc3_0->dbpdrga);
+	writel(0x00000D70, &dbsc3_0->dbpdrgd);
+
+	/* MR1	:Mode Register 1 */
+	writel(0x00000016, &dbsc3_0->dbpdrga);
+	writel(0x00000004, &dbsc3_0->dbpdrgd);	/* DRAM Drv 40ohm */
+
+	/* MR2	:Mode Register 2 */
+	writel(0x00000017, &dbsc3_0->dbpdrga);
+	writel(0x00000018, &dbsc3_0->dbpdrgd);	/* CWL=8 */
+
+	/* VREF(ZQCAL) */
+	writel(0x0000001A, &dbsc3_0->dbpdrga);
+	writel(0x910035C7, &dbsc3_0->dbpdrgd);
+
+	/* PGSR0	:PHY General Status Registers 0 */
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
+
+	/* DRAM Init (set MRx etc) */
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x00000181, &dbsc3_0->dbpdrgd);
+
+	/* CKE  = H */
+	writel(0x11000000, &dbsc3_0->dbcmd);		/* opc=PDXt(CKE=H) */
+
+	/* PGSR0	:PHY General Status Registers 0 */
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
+
+	/* RAM ACC Training */
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x0000FE01, &dbsc3_0->dbpdrgd);
+
+	/* Bus control 0 */
+	writel(0x00000000, &dbsc3_0->dbbs0cnt1);
+	/* DDR3 Calibration set */
+	writel(0x01004C20, &dbsc3_0->dbcalcnf);
+	/* DDR3 Calibration timing */
+	writel(0x014000AA, &dbsc3_0->dbcaltr);
+	/* Refresh */
+	writel(0x00000140, &dbsc3_0->dbrfcnf0);
+	writel(0x00081860, &dbsc3_0->dbrfcnf1);
+	writel(0x00010000, &dbsc3_0->dbrfcnf2);
+
+	/* PGSR0	:PHY General Status Registers 0 */
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
+
+	/* Enable Auto-Refresh */
+	writel(0x00000001, &dbsc3_0->dbrfen);
+	/* Permit DDR-Access */
+	writel(0x00000001, &dbsc3_0->dbacen);
+
+	/* This locks the access to the PHY unit registers */
+	writel(0x00000000, &dbsc3_0->dbpdlck);
+#endif /* CONFIG_SYS_NO_FLASH */
+
+}
+
+#define TMU0_MSTP125	(1 << 25)
+#define SCIF0_MSTP721	(1 << 21)
+#define SDHI0_MSTP314	(1 << 14)
+#define QSPI_MSTP917	(1 << 17)
+
+int board_early_init_f(void)
+{
+	/* TMU0 */
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+	/* SCIF0 */
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+	/* SDHI0 */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314);
+	/* QSPI */
+	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+	return 0;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	/* Init PFC controller */
+	r8a7792_pinmux_init();
+
+	gpio_request(GPIO_FN_D0, NULL);
+	gpio_request(GPIO_FN_D1, NULL);
+	gpio_request(GPIO_FN_D2, NULL);
+	gpio_request(GPIO_FN_D3, NULL);
+	gpio_request(GPIO_FN_D4, NULL);
+	gpio_request(GPIO_FN_D5, NULL);
+	gpio_request(GPIO_FN_D6, NULL);
+	gpio_request(GPIO_FN_D7, NULL);
+	gpio_request(GPIO_FN_D8, NULL);
+	gpio_request(GPIO_FN_D9, NULL);
+	gpio_request(GPIO_FN_D10, NULL);
+	gpio_request(GPIO_FN_D11, NULL);
+	gpio_request(GPIO_FN_D12, NULL);
+	gpio_request(GPIO_FN_D13, NULL);
+	gpio_request(GPIO_FN_D14, NULL);
+	gpio_request(GPIO_FN_D15, NULL);
+	gpio_request(GPIO_FN_A0, NULL);
+	gpio_request(GPIO_FN_A1, NULL);
+	gpio_request(GPIO_FN_A2, NULL);
+	gpio_request(GPIO_FN_A3, NULL);
+	gpio_request(GPIO_FN_A4, NULL);
+	gpio_request(GPIO_FN_A5, NULL);
+	gpio_request(GPIO_FN_A6, NULL);
+	gpio_request(GPIO_FN_A7, NULL);
+	gpio_request(GPIO_FN_A8, NULL);
+	gpio_request(GPIO_FN_A9, NULL);
+	gpio_request(GPIO_FN_A10, NULL);
+	gpio_request(GPIO_FN_A11, NULL);
+	gpio_request(GPIO_FN_A12, NULL);
+	gpio_request(GPIO_FN_A13, NULL);
+	gpio_request(GPIO_FN_A14, NULL);
+	gpio_request(GPIO_FN_A15, NULL);
+	gpio_request(GPIO_FN_A16, NULL);
+	gpio_request(GPIO_FN_A17, NULL);
+	gpio_request(GPIO_FN_A18, NULL);
+	gpio_request(GPIO_FN_A19, NULL);
+#if defined(CONFIG_SYS_NO_FLASH)
+	gpio_request(GPIO_FN_MOSI_IO0, NULL);
+	gpio_request(GPIO_FN_MISO_IO1, NULL);
+	gpio_request(GPIO_FN_IO2, NULL);
+	gpio_request(GPIO_FN_IO3, NULL);
+	gpio_request(GPIO_FN_SPCLK, NULL);
+	gpio_request(GPIO_FN_SSL, NULL);
+#else	/* CONFIG_SYS_NO_FLASH */
+	gpio_request(GPIO_FN_A20, NULL);
+	gpio_request(GPIO_FN_A21, NULL);
+	gpio_request(GPIO_FN_A22, NULL);
+	gpio_request(GPIO_FN_A23, NULL);
+	gpio_request(GPIO_FN_A24, NULL);
+	gpio_request(GPIO_FN_A25, NULL);
+#endif	/* CONFIG_SYS_NO_FLASH */
+
+	gpio_request(GPIO_FN_CS1_A26, NULL);
+	gpio_request(GPIO_FN_EX_CS0, NULL);
+	gpio_request(GPIO_FN_EX_CS1, NULL);
+	gpio_request(GPIO_FN_BS, NULL);
+	gpio_request(GPIO_FN_RD, NULL);
+	gpio_request(GPIO_FN_WE0, NULL);
+	gpio_request(GPIO_FN_WE1, NULL);
+	gpio_request(GPIO_FN_EX_WAIT0, NULL);
+	gpio_request(GPIO_FN_IRQ0, NULL);
+	gpio_request(GPIO_FN_IRQ2, NULL);
+	gpio_request(GPIO_FN_IRQ3, NULL);
+	gpio_request(GPIO_FN_CS0, NULL);
+
+	/* Init timer */
+	timer_init();
+
+	return 0;
+}
+
+/*
+ Added for BLANCHE(R-CarV2H board)
+*/
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_SMC911X
+#define STR_ENV_ETHADDR	"ethaddr"
+
+	struct eth_device *dev;
+	uchar eth_addr[6];
+
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+
+	if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
+		dev = eth_get_dev_by_index(0);
+		if (dev) {
+			eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
+		} else {
+			printf("blanche: Couldn't get eth device\n");
+			rc = -1;
+		}
+	}
+
+#endif
+
+	return rc;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret = -ENODEV;
+
+#ifdef CONFIG_SH_SDHI
+	gpio_request(GPIO_FN_SD0_DAT0, NULL);
+	gpio_request(GPIO_FN_SD0_DAT1, NULL);
+	gpio_request(GPIO_FN_SD0_DAT2, NULL);
+	gpio_request(GPIO_FN_SD0_DAT3, NULL);
+	gpio_request(GPIO_FN_SD0_CLK, NULL);
+	gpio_request(GPIO_FN_SD0_CMD, NULL);
+	gpio_request(GPIO_FN_SD0_CD, NULL);
+
+	gpio_request(GPIO_GP_11_12, NULL);
+	gpio_direction_output(GPIO_GP_11_12, 1);	/* power on */
+
+
+	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
+			   SH_SDHI_QUIRK_16BIT_BUF);
+
+	if (ret)
+		return ret;
+#endif
+	return ret;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RMOBILE_BOARD_STRING
+};
+
+void reset_cpu(ulong addr)
+{
+}
+
+static const struct sh_serial_platdata serial_platdata = {
+	.base = SCIF0_BASE,
+	.type = PORT_SCIF,
+	.clk = 14745600,
+	.clk_mode = EXT_CLK,
+};
+
+U_BOOT_DEVICE(blanche_serials) = {
+	.name = "serial_sh",
+	.platdata = &serial_platdata,
+};
diff --git a/board/renesas/blanche/qos.c b/board/renesas/blanche/qos.c
new file mode 100644
index 0000000..f1327f6
--- /dev/null
+++ b/board/renesas/blanche/qos.c
@@ -0,0 +1,1366 @@
+/*
+ * board/renesas/blanche/qos.c
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+enum {
+	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+	DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+	DBSC3_15,
+	DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+	int i;
+	struct rcar_s3c *s3c;
+	struct rcar_s3c_qos *s3c_qos;
+	struct rcar_dbsc3_qos *qos_addr;
+	struct rcar_mxi *mxi;
+	struct rcar_mxi_qos *mxi_qos;
+	struct rcar_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20082004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct rcar_s3c *)S3C_BASE;
+	// writel(0x00000000, &s3c->s3cadsplcr);
+	writel(0x1F0D0C0C, &s3c->s3crorr);
+	writel(0x1F1F0C0C, &s3c->s3cworr);
+
+	/* QoS Control Registers */
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x00820082, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20DC, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20DC, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+	writel(0x80918099, &s3c_qos->s3cqos0);
+	writel(0x20410010, &s3c_qos->s3cqos1);
+	writel(0x200A2023, &s3c_qos->s3cqos2);
+	writel(0x20502001, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20410FFF, &s3c_qos->s3cqos5);
+	writel(0x200A2023, &s3c_qos->s3cqos6);
+	writel(0x20502001, &s3c_qos->s3cqos7);
+	writel(0x20142032, &s3c_qos->s3cqos8);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00001FB0, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x0000204B, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x00001FC4, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC0 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x0000206E, &qos_addr->dbtmval1);
+		writel(0x00002050, &qos_addr->dbtmval2);
+		writel(0x0000203A, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x0000205A, &qos_addr->dbthres0);
+		writel(0x0000205A, &qos_addr->dbthres1);
+		writel(0x0000203C, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct rcar_mxi *)MXI_BASE;
+	writel(0x00000100, &mxi->mxaxirtcr);
+	writel(0xFF530100, &mxi->mxaxiwtcr);
+	writel(0x00000100, &mxi->mxs3crtcr);
+	writel(0xFF530100, &mxi->mxs3cwtcr);
+	writel(0x004000C0, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->du0);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADM_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADS_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX_BASE;
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AXI64TO128W_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVBW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCIW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCSW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2DW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0W_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1W_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2W_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBSW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTXBW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRABW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADMW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADSW_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYXW_BASE;
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_IMP0_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000211B, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SY2_BASE;
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256W_AXI128TO256_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXMW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXIW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_IMP0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SY2W_BASE;
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002055, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002055, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RT_BASE;
+	writel(0x00002001, &axi_qos->qosctset1);
+	writel(0x00002001, &axi_qos->qosctset2);
+	writel(0x00002001, &axi_qos->qosctset3);
+	writel(0x00000000, &axi_qos->qosthres0);
+	writel(0x00000000, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHXW_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002055, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_DBGW_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002055, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTW_BASE;
+	writel(0x00002001, &axi_qos->qosctset1);
+	writel(0x00002001, &axi_qos->qosctset2);
+	writel(0x00002001, &axi_qos->qosctset3);
+	writel(0x00000000, &axi_qos->qosthres0);
+	writel(0x00000000, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000000A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002018, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002259, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCTU0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCTU0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU1R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU1W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002046, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN1W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002046, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_RDRW_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x000020D0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS01R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x0000000C, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS01W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000200D, &axi_qos->qosctset0);
+	writel(0x000000C0, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS23R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x0000000C, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS23W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000200D, &axi_qos->qosctset0);
+	writel(0x000000C0, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS45R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x0000000C, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS45W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000200D, &axi_qos->qosctset0);
+	writel(0x000000C0, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002069, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002069, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE4R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE4W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC4R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC4W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x00000008, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x000020D3, &axi_qos->qosctset0);
+	writel(0x00000008, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x00000008, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x000020D3, &axi_qos->qosctset0);
+	writel(0x00000008, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000201A, &axi_qos->qosctset0);
+	writel(0x00000018, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002006, &axi_qos->qosctset0);
+	writel(0x00000018, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000201A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002042, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE1R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE1W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC1R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC1W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE2R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE2W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC2R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC2W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE3R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE3W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC3R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC3W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* DMS Register(SYS-AXI) */
+	writel(0x00000000, SYS_AXI_AVBDMSCR);
+	writel(0x00000000, SYS_AXI_AX2MDMSCR);
+	writel(0x00000000, SYS_AXI_CC50DMSCR);
+	writel(0x00000000, SYS_AXI_CCIDMSCR);
+	writel(0x00000000, SYS_AXI_CSDMSCR);
+	writel(0x00000000, SYS_AXI_G2DDMSCR);
+	writel(0x00000000, SYS_AXI_IMP1DMSCR);
+	writel(0x00000000, SYS_AXI_LBSMDMSCR);
+	writel(0x00000000, SYS_AXI_MMUDSDMSCR);
+	writel(0x00000000, SYS_AXI_MMUMXDMSCR);
+	writel(0x00000000, SYS_AXI_MMUS0DMSCR);
+	writel(0x00000000, SYS_AXI_MMUS1DMSCR);
+	writel(0x00000000, SYS_AXI_RTMXDMSCR);
+	writel(0x00000000, SYS_AXI_SDM0DMSCR);
+	writel(0x00000000, SYS_AXI_SDM1DMSCR);
+	writel(0x00000000, SYS_AXI_SDS0DMSCR);
+	writel(0x00000000, SYS_AXI_SDS1DMSCR);
+	writel(0x00000000, SYS_AXI_TRABDMSCR);
+	writel(0x00000000, SYS_AXI_X128TO64SLVDMSCR);
+	writel(0x00000000, SYS_AXI_X64TO128SLVDMSCR);
+	writel(0x00000000, SYS_AXI_AVBSLVDMSCR);
+	writel(0x00000000, SYS_AXI_AX2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_GICSLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMPSLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMPSLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMX0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMX1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMX2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_LBSSLVDMSCR);
+	writel(0x00000000, SYS_AXI_MXTSLVDMSCR);
+	writel(0x00000000, SYS_AXI_SYAPBSLVDMSCR);
+	writel(0x00000000, SYS_AXI_QSAPBSLVDMSCR);
+	writel(0x00000000, SYS_AXI_RTXSLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC3SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC65SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC8SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SDAP0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SGXSLV1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STMSLVDMSCR);
+	writel(0x00000000, SYS_AXI_SYXXDEFAULTSLAVESLVDMSCR);
+	writel(0x00000000, SYS_AXI_TSPL0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_TSPL1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_TSPL2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_UTLBDSSLVDMSCR);
+	writel(0x00000000, SYS_AXI_UTLBS0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_UTLBS1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_ROT0DMSCR);
+	writel(0x00000000, SYS_AXI_ROT1DMSCR);
+	writel(0x00000000, SYS_AXI_ROT2DMSCR);
+	writel(0x00000000, SYS_AXI_ROT3DMSCR);
+	writel(0x00000000, SYS_AXI_ROT4DMSCR);
+	writel(0x00000000, SYS_AXI_IMUX3SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR0PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR0XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR1PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR1XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR2PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR2XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR3SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR3PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR3XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR4SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR4PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR4XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_ADM_DMSCR);
+	writel(0x00000000, SYS_AXI_ADS_DMSCR);
+
+	/* DMS Register(RT-AXI) */
+	writel(0x00000000, DM_AXI_DMAXICONF);
+	writel(0x00000019, DM_AXI_DMAPBCONF);
+	writel(0x00000000, DM_AXI_DMADMCONF);
+	writel(0x00000000, DM_AXI_DMSDM0CONF);
+	writel(0x00000000, DM_AXI_DMSDM1CONF);
+	writel(0x00000004, DM_AXI_DMQSPAPSLVCONF);
+	writel(0x00000004, DM_AXI_RAPD4SLVCONF);
+	writel(0x00000004, DM_AXI_SAPD4SLVCONF);
+	writel(0x00000004, DM_AXI_SAPD5SLVCONF);
+	writel(0x00000004, DM_AXI_SAPD6SLVCONF);
+	writel(0x00000004, DM_AXI_SAPD65DSLVCONF);
+	writel(0x00000004, DM_AXI_SDAP0SLVCONF);
+	writel(0x00000004, DM_AXI_MAPD2SLVCONF);
+	writel(0x00000004, DM_AXI_MAPD3SLVCONF);
+	writel(0x00000000, DM_AXI_DMXXDEFAULTSLAVESLVCONF);
+	writel(0x00000100, DM_AXI_DMADMRQOSCONF);
+	writel(0x0000214C, DM_AXI_DMADMRQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMADMRQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMADMRQOSQON);
+	writel(0x00000005, DM_AXI_DMADMRQOSIN);
+	writel(0x00000000, DM_AXI_DMADMRQOSSTAT);
+	writel(0x00000000, DM_AXI_DMSDM0RQOSCONF);
+	writel(0x0000214C, DM_AXI_DMSDM0RQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMSDM0RQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMSDM0RQOSQON);
+	writel(0x00000005, DM_AXI_DMSDM0RQOSIN);
+	writel(0x00000000, DM_AXI_DMSDM0RQOSSTAT);
+	writel(0x00000000, DM_AXI_DMSDM1RQOSCONF);
+	writel(0x0000214C, DM_AXI_DMSDM1RQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMSDM1RQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMSDM1RQOSQON);
+	writel(0x00000005, DM_AXI_DMSDM1RQOSIN);
+	writel(0x00000000, DM_AXI_DMSDM1RQOSSTAT);
+	writel(0x00002041, DM_AXI_DMRQOSCTSET1);
+	writel(0x00002023, DM_AXI_DMRQOSCTSET2);
+	writel(0x0000200A, DM_AXI_DMRQOSCTSET3);
+	writel(0x00002050, DM_AXI_DMRQOSTHRES0);
+	writel(0x00002032, DM_AXI_DMRQOSTHRES1);
+	writel(0x00002014, DM_AXI_DMRQOSTHRES2);
+	writel(0x00000100, DM_AXI_DMADMWQOSCONF);
+	writel(0x0000214C, DM_AXI_DMADMWQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMADMWQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMADMWQOSQON);
+	writel(0x00000005, DM_AXI_DMADMWQOSIN);
+	writel(0x00000000, DM_AXI_DMADMWQOSSTAT);
+	writel(0x00000000, DM_AXI_DMSDM0WQOSCONF);
+	writel(0x0000214C, DM_AXI_DMSDM0WQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMSDM0WQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMSDM0WQOSQON);
+	writel(0x00000005, DM_AXI_DMSDM0WQOSIN);
+	writel(0x00000000, DM_AXI_DMSDM0WQOSSTAT);
+	writel(0x00000000, DM_AXI_DMSDM1WQOSCONF);
+	writel(0x0000214C, DM_AXI_DMSDM1WQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMSDM1WQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMSDM1WQOSQON);
+	writel(0x00000005, DM_AXI_DMSDM1WQOSIN);
+	writel(0x00000000, DM_AXI_DMSDM1WQOSSTAT);
+	writel(0x00002041, DM_AXI_DMWQOSCTSET1);
+	writel(0x00002023, DM_AXI_DMWQOSCTSET2);
+	writel(0x0000200A, DM_AXI_DMWQOSCTSET3);
+	writel(0x00002050, DM_AXI_DMWQOSTHRES0);
+	writel(0x00002032, DM_AXI_DMWQOSTHRES1);
+	writel(0x00002014, DM_AXI_DMWQOSTHRES2);
+	writel(0x00000000, DM_AXI_RDMDMSCR);
+	writel(0x00000000, DM_AXI_SDM0DMSCR);
+	writel(0x00000000, DM_AXI_SDM1DMSCR);
+	writel(0x00000000, DM_AXI_DMQSPAPSLVDMSCR);
+	writel(0x00000000, DM_AXI_RAPD4SLVDMSCR);
+	writel(0x00000000, DM_AXI_SAPD4SLVDMSCR);
+	writel(0x00000000, DM_AXI_SAPD5SLVDMSCR);
+	writel(0x00000000, DM_AXI_SAPD6SLVDMSCR);
+	writel(0x00000000, DM_AXI_SAPD65DSLVDMSCR);
+	writel(0x00000000, DM_AXI_SDAP0SLVDMSCR);
+	writel(0x00000000, DM_AXI_MAPD2SLVDMSCR);
+	writel(0x00000000, DM_AXI_MAPD3SLVDMSCR);
+	writel(0x00000000, DM_AXI_DMXXDEFAULTSLAVESLVDMSCR);
+	writel(0x00000001, DM_AXI_DMXREGDMSENN);
+
+	/* DMS Register(SYS-AXI256) */
+	writel(0x00000000, SYS_AXI256_SYXDMSCR);
+	writel(0x00000000, SYS_AXI256_MXIDMSCR);
+	writel(0x00000000, SYS_AXI256_X128TO256SLVDMSCR);
+	writel(0x00000000, SYS_AXI256_X256TO128SLVDMSCR);
+	writel(0x00000000, SYS_AXI256_SYXSLVDMSCR);
+	writel(0x00000000, SYS_AXI256_CCXSLVDMSCR);
+	writel(0x00000000, SYS_AXI256_S3CSLVDMSCR);
+
+	/* DMS Register(MXT) */
+	writel(0x00000000, MXT_SYXDMSCR);
+	writel(0x00000000, MXT_IMRSLVDMSCR);
+	writel(0x00000000, MXT_VINSLVDMSCR);
+	writel(0x00000000, MXT_VPC1SLVDMSCR);
+	writel(0x00000000, MXT_VSPD0SLVDMSCR);
+	writel(0x00000000, MXT_VSPD1SLVDMSCR);
+	writel(0x00000000, MXT_MAP1SLVDMSCR);
+	writel(0x00000000, MXT_MAP2SLVDMSCR);
+	writel(0x00000000, MXT_MAP2BSLVDMSCR);
+
+	/* DMS Register(MXI) */
+	writel(0x00000002, MXI_JPURDMSCR);
+	writel(0x00000002, MXI_JPUWDMSCR);
+	writel(0x00000002, MXI_VCTU0RDMSCR);
+	writel(0x00000002, MXI_VCTU0WDMSCR);
+	writel(0x00000002, MXI_VDCTU0RDMSCR);
+	writel(0x00000002, MXI_VDCTU0WDMSCR);
+	writel(0x00000002, MXI_VDCTU1RDMSCR);
+	writel(0x00000002, MXI_VDCTU1WDMSCR);
+	writel(0x00000002, MXI_VIN0WDMSCR);
+	writel(0x00000002, MXI_VIN1WDMSCR);
+	writel(0x00000002, MXI_RDRWDMSCR);
+	writel(0x00000002, MXI_IMS01RDMSCR);
+	writel(0x00000002, MXI_IMS01WDMSCR);
+	writel(0x00000002, MXI_IMS23RDMSCR);
+	writel(0x00000002, MXI_IMS23WDMSCR);
+	writel(0x00000002, MXI_IMS45RDMSCR);
+	writel(0x00000002, MXI_IMS45WDMSCR);
+	writel(0x00000002, MXI_IMRRDMSCR);
+	writel(0x00000002, MXI_IMRWDMSCR);
+	writel(0x00000002, MXI_ROTCE4RDMSCR);
+	writel(0x00000002, MXI_ROTCE4WDMSCR);
+	writel(0x00000002, MXI_ROTVLC4RDMSCR);
+	writel(0x00000002, MXI_ROTVLC4WDMSCR);
+	writel(0x00000002, MXI_VSPD0RDMSCR);
+	writel(0x00000002, MXI_VSPD0WDMSCR);
+	writel(0x00000002, MXI_VSPD1RDMSCR);
+	writel(0x00000002, MXI_VSPD1WDMSCR);
+	writel(0x00000002, MXI_DU0RDMSCR);
+	writel(0x00000002, MXI_DU0WDMSCR);
+	writel(0x00000002, MXI_VSP0RDMSCR);
+	writel(0x00000002, MXI_VSP0WDMSCR);
+	writel(0x00000002, MXI_ROTCE0RDMSCR);
+	writel(0x00000002, MXI_ROTCE0WDMSCR);
+	writel(0x00000002, MXI_ROTVLC0RDMSCR);
+	writel(0x00000002, MXI_ROTVLC0WDMSCR);
+	writel(0x00000002, MXI_ROTCE1RDMSCR);
+	writel(0x00000002, MXI_ROTCE1WDMSCR);
+	writel(0x00000002, MXI_ROTVLC1RDMSCR);
+	writel(0x00000002, MXI_ROTVLC1WDMSCR);
+	writel(0x00000002, MXI_ROTCE2RDMSCR);
+	writel(0x00000002, MXI_ROTCE2WDMSCR);
+	writel(0x00000002, MXI_ROTVLC2RDMSCR);
+	writel(0x00000002, MXI_ROTVLC2WDMSCR);
+	writel(0x00000002, MXI_ROTCE3RDMSCR);
+	writel(0x00000002, MXI_ROTCE3WDMSCR);
+	writel(0x00000002, MXI_ROTVLC3RDMSCR);
+	writel(0x00000002, MXI_ROTVLC3WDMSCR);
+
+	/* DMS Register(CCI-AXI) */
+	writel(0x00000000, CCI_AXI_MMUS0DMSCR);
+	writel(0x00000000, CCI_AXI_SYX2DMSCR);
+	writel(0x00000000, CCI_AXI_MMURDMSCR);
+	writel(0x00000000, CCI_AXI_MMUDSDMSCR);
+	writel(0x00000000, CCI_AXI_MMUMDMSCR);
+	writel(0x00000000, CCI_AXI_MXIDMSCR);
+	writel(0x00000000, CCI_AXI_MMUS1DMSCR);
+	writel(0x00000000, CCI_AXI_MMUMPDMSCR);
+	writel(0x00000000, CCI_AXI_DVMDMSCR);
+	writel(0x00000000, CCI_AXI_CCISLVDMSCR);
+
+	/* CC-AXI Function Register */
+	writel(0x00000011, CCI_AXI_IPMMUIDVMCR);
+	writel(0x00000011, CCI_AXI_IPMMURDVMCR);
+	writel(0x00000011, CCI_AXI_IPMMUS0DVMCR);
+	writel(0x00000011, CCI_AXI_IPMMUS1DVMCR);
+	writel(0x00000011, CCI_AXI_IPMMUMPDVMCR);
+	writel(0x00000011, CCI_AXI_IPMMUDSDVMCR);
+	writel(0x0000F700, CCI_AXI_AX2ADDRMASK);
+
+}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
diff --git a/board/renesas/blanche/qos.h b/board/renesas/blanche/qos.h
new file mode 100644
index 0000000..e3ecddf
--- /dev/null
+++ b/board/renesas/blanche/qos.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif