arm: rmobile: Add BLANCHE board support
BLANCHE is development board based on R-Car V2H SoC (R8A7792)
This commit supports the following periherals:
- SCIF, Ethernet, QSPI, MMC
Signed-off-by: Masakazu Mochizuki <masakazu.mochizuki.wd@hitachi.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
diff --git a/arch/arm/mach-rmobile/include/mach/rcar-base.h b/arch/arm/mach-rmobile/include/mach/rcar-base.h
index 53ead26..709bc75 100644
--- a/arch/arm/mach-rmobile/include/mach/rcar-base.h
+++ b/arch/arm/mach-rmobile/include/mach/rcar-base.h
@@ -10,7 +10,7 @@
#define __ASM_ARCH_RCAR_BASE_H
/*
- * R-Car (R8A7790/R8A7791/R8A7793/R8A7794) I/O Addresses
+ * R-Car (R8A7790/R8A7791/R8A7792/R8A7793/R8A7794) I/O Addresses
*/
#define RWDT_BASE 0xE6020000
#define SWDT_BASE 0xE6030000
@@ -142,6 +142,12 @@
#define SYS_AXI_SYX64TO128_BASE 0xFF800300
#define SYS_AXI_AVB_BASE 0xFF800340
+#define SYS_AXI_AX2M_BASE 0xFF800380
+#define SYS_AXI_CC50_BASE 0xFF8003C0
+#define SYS_AXI_CCI_BASE 0xFF800440
+#define SYS_AXI_CS_BASE 0xFF800480
+#define SYS_AXI_DDM_BASE 0xFF8004C0
+#define SYS_AXI_ETH_BASE 0xFF800500
#define SYS_AXI_G2D_BASE 0xFF800540
#define SYS_AXI_IMP0_BASE 0xFF800580
#define SYS_AXI_IMP1_BASE 0xFF8005C0
@@ -154,30 +160,49 @@
#define SYS_AXI_MMUR_BASE 0xFF800780
#define SYS_AXI_MMUS0_BASE 0xFF8007C0
#define SYS_AXI_MMUS1_BASE 0xFF800800
+#define SYS_AXI_MPXM_BASE 0xFF800840
#define SYS_AXI_MTSB0_BASE 0xFF800880
#define SYS_AXI_MTSB1_BASE 0xFF8008C0
#define SYS_AXI_PCI_BASE 0xFF800900
#define SYS_AXI_RTX_BASE 0xFF800940
-#define SYS_AXI_SDS0_BASE 0xFF800A80
-#define SYS_AXI_SDS1_BASE 0xFF800AC0
-#define SYS_AXI_USB20_BASE 0xFF800C00
-#define SYS_AXI_USB21_BASE 0xFF800C40
-#define SYS_AXI_USB22_BASE 0xFF800C80
-#define SYS_AXI_USB30_BASE 0xFF800CC0
-#define SYS_AXI_AX2M_BASE 0xFF800380
-#define SYS_AXI_CC50_BASE 0xFF8003C0
-#define SYS_AXI_CCI_BASE 0xFF800440
-#define SYS_AXI_CS_BASE 0xFF800480
-#define SYS_AXI_DDM_BASE 0xFF8004C0
-#define SYS_AXI_ETH_BASE 0xFF800500
-#define SYS_AXI_MPXM_BASE 0xFF800840
#define SYS_AXI_SAT0_BASE 0xFF800980
#define SYS_AXI_SAT1_BASE 0xFF8009C0
#define SYS_AXI_SDM0_BASE 0xFF800A00
#define SYS_AXI_SDM1_BASE 0xFF800A40
+#define SYS_AXI_SDS0_BASE 0xFF800A80
+#define SYS_AXI_SDS1_BASE 0xFF800AC0
#define SYS_AXI_TRAB_BASE 0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
#define SYS_AXI_UDM0_BASE 0xFF800B80
#define SYS_AXI_UDM1_BASE 0xFF800BC0
+#define SYS_AXI_USB20_BASE 0xFF800C00
+#define SYS_AXI_USB21_BASE 0xFF800C40
+#define SYS_AXI_USB22_BASE 0xFF800C80
+#define SYS_AXI_USB30_BASE 0xFF800CC0
+#define SYS_AXI_ADM_BASE 0xFF800D00
+#define SYS_AXI_ADS_BASE 0xFF800D40
+#define SYS_AXI_SYX_BASE 0xFF800FB8
+
+#define SYS_AXI_AXI64TO128W_BASE 0xFF801300
+#define SYS_AXI_AVBW_BASE 0xFF801340
+#define SYS_AXI_CC50W_BASE 0xFF8013C0
+#define SYS_AXI_CCIW_BASE 0xFF801440
+#define SYS_AXI_CSW_BASE 0xFF801480
+#define SYS_AXI_G2DW_BASE 0xFF801540
+#define SYS_AXI_IMUX0W_BASE 0xFF801600
+#define SYS_AXI_IMUX1W_BASE 0xFF801640
+#define SYS_AXI_IMUX2W_BASE 0xFF801680
+#define SYS_AXI_LBSW_BASE 0xFF8016C0
+#define SYS_AXI_RTXW_BASE 0xFF801940
+#define SYS_AXI_SDM0W_BASE 0xFF801A00
+#define SYS_AXI_SDM1W_BASE 0xFF801A40
+#define SYS_AXI_SDS0W_BASE 0xFF801A80
+#define SYS_AXI_SDS1W_BASE 0xFF801AC0
+#define SYS_AXI_TRABW_BASE 0xFF801B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
+#define SYS_AXI_UDM0W_BASE 0xFF801B80
+#define SYS_AXI_UDM1W_BASE 0xFF801BC0
+#define SYS_AXI_ADMW_BASE 0xFF801D00
+#define SYS_AXI_ADSW_BASE 0xFF801D40
+#define SYS_AXI_SYXW_BASE 0xFF801FB8
#define RT_AXI_SHX_BASE 0xFF810100
#define RT_AXI_DBG_BASE 0xFF810140 /* R8A7791 only */
@@ -186,6 +211,11 @@
#define RT_AXI_RTX64TO128_BASE 0xFF810200
#define RT_AXI_STPRO_BASE 0xFF810240
#define RT_AXI_SY2RT_BASE 0xFF810280 /* R8A7791 only */
+#define RT_AXI_RT_BASE 0xFF810FC0
+#define RT_AXI_SHXW_BASE 0xFF811100
+#define RT_AXI_DBGW_BASE 0xFF811140
+#define RT_AXI_RTX64TO128W_BASE 0xFF811200
+#define RT_AXI_RTW_BASE 0xFF811FC0
#define MP_AXI_ADSP_BASE 0xFF820100
#define MP_AXI_ASDS0_BASE 0xFF8201C0
@@ -197,8 +227,16 @@
#define SYS_AXI256_AXI128TO256_BASE 0xFF860100
#define SYS_AXI256_SYX_BASE 0xFF860140
+#define SYS_AXI256_AXM_BASE 0xFF860140
#define SYS_AXI256_MPX_BASE 0xFF860180
#define SYS_AXI256_MXI_BASE 0xFF8601C0
+#define SYS_AXI256_IMP0_BASE 0xFF860580
+#define SYS_AXI256_SY2_BASE 0xFF860FC0
+#define SYS_AXI256_AXI128TO256W_BASE 0xFF861100
+#define SYS_AXI256_AXMW_BASE 0xFF861140
+#define SYS_AXI256_MXIW_BASE 0xFF8611C0
+#define SYS_AXI256_IMP0W_BASE 0xFF861580
+#define SYS_AXI256_SY2W_BASE 0xFF861FC0
#define CCI_AXI_MMUS0_BASE 0xFF880100
#define CCI_AXI_SYX2_BASE 0xFF880140
@@ -227,9 +265,6 @@
#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
-#define MEDIA_AXI_VIN0W_BASE 0xFE966900
-#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
-#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
#define MEDIA_AXI_FDP0R_BASE 0xFE964D40
#define MEDIA_AXI_FDP0W_BASE 0xFE966D40
#define MEDIA_AXI_IMSR_BASE 0xFE964D80
@@ -242,12 +277,6 @@
#define MEDIA_AXI_IMRW_BASE 0xFE967180
#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
-#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
-#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
-#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
-#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
-#define MEDIA_AXI_DU0R_BASE 0xFE965580
-#define MEDIA_AXI_DU0W_BASE 0xFE967580
#define MEDIA_AXI_DU1R_BASE 0xFE9655C0
#define MEDIA_AXI_DU1W_BASE 0xFE9675C0
#define MEDIA_AXI_VCP0CR_BASE 0xFE965900
@@ -261,8 +290,66 @@
#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
#define MEDIA_AXI_VPC1R_BASE 0xFE965D80
+#if defined (CONFIG_R8A7792)
+#define MEDIA_AXI_VCTU0R_BASE 0xFE964500 /* R8A7792 */
+#define MEDIA_AXI_VCTU0W_BASE 0xFE966500
+#define MEDIA_AXI_VDCTU0R_BASE 0xFE964540
+#define MEDIA_AXI_VDCTU0W_BASE 0xFE966540
+#define MEDIA_AXI_VDCTU1R_BASE 0xFE964580
+#define MEDIA_AXI_VDCTU1W_BASE 0xFE966580
+#define MEDIA_AXI_VIN0W_BASE 0xFE967580
+#define MEDIA_AXI_VIN1W_BASE 0xFE966D80
+#define MEDIA_AXI_RDRW_BASE 0xFE9675C0
+#define MEDIA_AXI_IMS01R_BASE 0xFE965500
+#define MEDIA_AXI_IMS01W_BASE 0xFE967500
+#define MEDIA_AXI_IMS23R_BASE 0xFE965540 /* FIXME */
+#define MEDIA_AXI_IMS23W_BASE 0xFE967540
+#define MEDIA_AXI_IMS45R_BASE 0xFE964D00
+#define MEDIA_AXI_IMS45W_BASE 0xFE966D00
+#define MEDIA_AXI_ROTCE4R_BASE 0xFE965100
+#define MEDIA_AXI_ROTCE4W_BASE 0xFE967100
+#define MEDIA_AXI_ROTVLC4R_BASE 0xFE965140
+#define MEDIA_AXI_ROTVLC4W_BASE 0xFE965140
+#define MEDIA_AXI_VSPD0R_BASE 0xFE964900
+#define MEDIA_AXI_VSPD0W_BASE 0xFE966900
+#define MEDIA_AXI_VSPD1R_BASE 0xFE964940
+#define MEDIA_AXI_VSPD1W_BASE 0xFE966940
+#define MEDIA_AXI_DU0R_BASE 0xFE964980
+#define MEDIA_AXI_DU0W_BASE 0xFE966980
+#define MEDIA_AXI_VSP0R_BASE 0xFE9649C0
+#define MEDIA_AXI_VSP0W_BASE 0xFE9669C0
+#define MEDIA_AXI_ROTCE0R_BASE 0xFE965900
+#define MEDIA_AXI_ROTCE0W_BASE 0xFE967900
+#define MEDIA_AXI_ROTVLC0R_BASE 0xFE965940
+#define MEDIA_AXI_ROTVLC0W_BASE 0xFE967940
+#define MEDIA_AXI_ROTCE1R_BASE 0xFE965980
+#define MEDIA_AXI_ROTCE1W_BASE 0xFE967980
+#define MEDIA_AXI_ROTVLC1R_BASE 0xFE9659C0
+#define MEDIA_AXI_ROTVLC1W_BASE 0xFE9679C0
+#define MEDIA_AXI_ROTCE2R_BASE 0xFE965D00
+#define MEDIA_AXI_ROTCE2W_BASE 0xFE967D00
+#define MEDIA_AXI_ROTVLC2R_BASE 0xFE965D40
+#define MEDIA_AXI_ROTVLC2W_BASE 0xFE967D40
+#define MEDIA_AXI_ROTCE3R_BASE 0xFE965D80
+#define MEDIA_AXI_ROTCE3W_BASE 0xFE967D80
+#define MEDIA_AXI_ROTVLC3R_BASE 0xFE965DC0
+#define MEDIA_AXI_ROTVLC3W_BASE 0xFE967DC0
+#else /* R8A7792 */
+#define MEDIA_AXI_VIN0W_BASE 0xFE966900
+#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
+#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
+#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
+#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
+#define MEDIA_AXI_DU0R_BASE 0xFE965580
+#define MEDIA_AXI_DU0W_BASE 0xFE967580
+#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
+#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
+#endif /* R8A7792 */
+
+
#define SYS_AXI_AVBDMSCR 0xFF802000
#define SYS_AXI_SYX2DMSCR 0xFF802004
+#define SYS_AXI_AX2MDMSCR 0xFF802004
#define SYS_AXI_CC50DMSCR 0xFF802008
#define SYS_AXI_CC51DMSCR 0xFF80200C
#define SYS_AXI_CCIDMSCR 0xFF802010
@@ -301,6 +388,7 @@
#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
#define SYS_AXI_AVBSLVDMSCR 0xFF802108
#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
+#define SYS_AXI_AX2SLVDMSCR 0xFF80210C
#define SYS_AXI_ETHSLVDMSCR 0xFF802110
#define SYS_AXI_GICSLVDMSCR 0xFF802114
#define SYS_AXI_IMPSLVDMSCR 0xFF802118
@@ -318,6 +406,11 @@
#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
#define SYS_AXI_RTXSLVDMSCR 0xFF802150
+#define SYS_AXI_SAPC1SLVDMSCR 0xFF802154
+#define SYS_AXI_SAPC2SLVDMSCR 0xFF802158
+#define SYS_AXI_SAPC3SLVDMSCR 0xFF80215C
+#define SYS_AXI_SAPC65SLVDMSCR 0xFF802160
+#define SYS_AXI_SAPC8SLVDMSCR 0xFF802164
#define SYS_AXI_SAT0SLVDMSCR 0xFF802168
#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
@@ -325,8 +418,10 @@
#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
#define SYS_AXI_SGXSLVDMSCR 0xFF802180
+#define SYS_AXI_SGXSLV1SLVDMSCR 0xFF802184
#define SYS_AXI_STBSLVDMSCR 0xFF802188
#define SYS_AXI_STMSLVDMSCR 0xFF80218C
+#define SYS_AXI_SYXXDEFAULTSLAVESLVDMSCR 0xFF802190
#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
@@ -334,6 +429,32 @@
#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
+#define SYS_AXI_UTLBDSSLVDMSCR 0xFF8021B0
+#define SYS_AXI_UTLBS0SLVDMSCR 0xFF8021B4
+#define SYS_AXI_UTLBS1SLVDMSCR 0xFF8021B8
+#define SYS_AXI_ROT0DMSCR 0xFF802320
+#define SYS_AXI_ROT1DMSCR 0xFF802324
+#define SYS_AXI_ROT2DMSCR 0xFF802328
+#define SYS_AXI_ROT3DMSCR 0xFF80232C
+#define SYS_AXI_ROT4DMSCR 0xFF802330
+#define SYS_AXI_IMUX3SLVDMSCR 0xFF802334
+#define SYS_AXI_STBR0SLVDMSCR 0xFF803200
+#define SYS_AXI_STBR0PSLVDMSCR 0xFF803204
+#define SYS_AXI_STBR0XSLVDMSCR 0xFF803208
+#define SYS_AXI_STBR1SLVDMSCR 0xFF803210
+#define SYS_AXI_STBR1PSLVDMSCR 0xFF803214
+#define SYS_AXI_STBR1XSLVDMSCR 0xFF803218
+#define SYS_AXI_STBR2SLVDMSCR 0xFF803220
+#define SYS_AXI_STBR2PSLVDMSCR 0xFF803224
+#define SYS_AXI_STBR2XSLVDMSCR 0xFF803228
+#define SYS_AXI_STBR3SLVDMSCR 0xFF803230
+#define SYS_AXI_STBR3PSLVDMSCR 0xFF803234
+#define SYS_AXI_STBR3XSLVDMSCR 0xFF803238
+#define SYS_AXI_STBR4SLVDMSCR 0xFF803240
+#define SYS_AXI_STBR4PSLVDMSCR 0xFF803244
+#define SYS_AXI_STBR4XSLVDMSCR 0xFF803248
+#define SYS_AXI_ADM_DMSCR 0xFF803260
+#define SYS_AXI_ADS_DMSCR 0xFF803264
#define RT_AXI_CBMDMSCR 0xFF812000
#define RT_AXI_DBDMSCR 0xFF812004
@@ -380,9 +501,86 @@
#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
+#define DM_AXI_DMAXICONF 0xFF850000
+#define DM_AXI_DMAPBCONF 0xFF850004
+#define DM_AXI_DMADMCONF 0xFF850020
+#define DM_AXI_DMSDM0CONF 0xFF850024
+#define DM_AXI_DMSDM1CONF 0xFF850028
+#define DM_AXI_DMQSPAPSLVCONF 0xFF850030
+#define DM_AXI_RAPD4SLVCONF 0xFF850034
+#define DM_AXI_SAPD4SLVCONF 0xFF85003C
+#define DM_AXI_SAPD5SLVCONF 0xFF850040
+#define DM_AXI_SAPD6SLVCONF 0xFF850044
+#define DM_AXI_SAPD65DSLVCONF 0xFF850048
+#define DM_AXI_SDAP0SLVCONF 0xFF85004C
+#define DM_AXI_MAPD2SLVCONF 0xFF850050
+#define DM_AXI_MAPD3SLVCONF 0xFF850054
+#define DM_AXI_DMXXDEFAULTSLAVESLVCONF 0xFF850058
+#define DM_AXI_DMADMRQOSCONF 0xFF850100
+#define DM_AXI_DMADMRQOSCTSET0 0xFF850104
+#define DM_AXI_DMADMRQOSREQCTR 0xFF850114
+#define DM_AXI_DMADMRQOSQON 0xFF850124
+#define DM_AXI_DMADMRQOSIN 0xFF850128
+#define DM_AXI_DMADMRQOSSTAT 0xFF85012C
+#define DM_AXI_DMSDM0RQOSCONF 0xFF850140
+#define DM_AXI_DMSDM0RQOSCTSET0 0xFF850144
+#define DM_AXI_DMSDM0RQOSREQCTR 0xFF850154
+#define DM_AXI_DMSDM0RQOSQON 0xFF850164
+#define DM_AXI_DMSDM0RQOSIN 0xFF850168
+#define DM_AXI_DMSDM0RQOSSTAT 0xFF85016C
+#define DM_AXI_DMSDM1RQOSCONF 0xFF850180
+#define DM_AXI_DMSDM1RQOSCTSET0 0xFF850184
+#define DM_AXI_DMSDM1RQOSREQCTR 0xFF850194
+#define DM_AXI_DMSDM1RQOSQON 0xFF8501A4
+#define DM_AXI_DMSDM1RQOSIN 0xFF8501A8
+#define DM_AXI_DMSDM1RQOSSTAT 0xFF8501AC
+#define DM_AXI_DMRQOSCTSET1 0xFF850FC0
+#define DM_AXI_DMRQOSCTSET2 0xFF850FC4
+#define DM_AXI_DMRQOSCTSET3 0xFF850FC8
+#define DM_AXI_DMRQOSTHRES0 0xFF850FCC
+#define DM_AXI_DMRQOSTHRES1 0xFF850FD0
+#define DM_AXI_DMRQOSTHRES2 0xFF850FD4
+#define DM_AXI_DMADMWQOSCONF 0xFF851100
+#define DM_AXI_DMADMWQOSCTSET0 0xFF851104
+#define DM_AXI_DMADMWQOSREQCTR 0xFF851114
+#define DM_AXI_DMADMWQOSQON 0xFF851124
+#define DM_AXI_DMADMWQOSIN 0xFF851128
+#define DM_AXI_DMADMWQOSSTAT 0xFF85112C
+#define DM_AXI_DMSDM0WQOSCONF 0xFF851140
+#define DM_AXI_DMSDM0WQOSCTSET0 0xFF851144
+#define DM_AXI_DMSDM0WQOSREQCTR 0xFF851154
+#define DM_AXI_DMSDM0WQOSQON 0xFF851164
+#define DM_AXI_DMSDM0WQOSIN 0xFF851168
+#define DM_AXI_DMSDM0WQOSSTAT 0xFF85116C
+#define DM_AXI_DMSDM1WQOSCONF 0xFF851180
+#define DM_AXI_DMSDM1WQOSCTSET0 0xFF851184
+#define DM_AXI_DMSDM1WQOSREQCTR 0xFF851194
+#define DM_AXI_DMSDM1WQOSQON 0xFF8511A4
+#define DM_AXI_DMSDM1WQOSIN 0xFF8511A8
+#define DM_AXI_DMSDM1WQOSSTAT 0xFF8511AC
+#define DM_AXI_DMWQOSCTSET1 0xFF851FC0
+#define DM_AXI_DMWQOSCTSET2 0xFF851FC4
+#define DM_AXI_DMWQOSCTSET3 0xFF851FC8
+#define DM_AXI_DMWQOSTHRES0 0xFF851FCC
+#define DM_AXI_DMWQOSTHRES1 0xFF851FD0
+#define DM_AXI_DMWQOSTHRES2 0xFF851FD4
+
#define DM_AXI_RDMDMSCR 0xFF852000
#define DM_AXI_SDM0DMSCR 0xFF852004
#define DM_AXI_SDM1DMSCR 0xFF852008
+#if defined(CONFIG_R8A7792)
+#define DM_AXI_DMQSPAPSLVDMSCR 0xFF852104
+#define DM_AXI_RAPD4SLVDMSCR 0xFF852108
+#define DM_AXI_SAPD4SLVDMSCR 0xFF852110
+#define DM_AXI_SAPD5SLVDMSCR 0xFF852114
+#define DM_AXI_SAPD6SLVDMSCR 0xFF852118
+#define DM_AXI_SAPD65DSLVDMSCR 0xFF85211C
+#define DM_AXI_SDAP0SLVDMSCR 0xFF852120
+#define DM_AXI_MAPD2SLVDMSCR 0xFF852124
+#define DM_AXI_MAPD3SLVDMSCR 0xFF852128
+#define DM_AXI_DMXXDEFAULTSLAVESLVDMSCR 0xFF85212C
+#define DM_AXI_DMXREGDMSENN 0xFF852200
+#else
#define DM_AXI_MMAP0SLVDMSCR 0xFF852100
#define DM_AXI_MMAP1SLVDMSCR 0xFF852104
#define DM_AXI_QSPAPSLVDMSCR 0xFF852108
@@ -396,6 +594,7 @@
#define DM_AXI_SDAP1SLVDMSCR 0xFF852128
#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
#define DM_AXI_SDAP3SLVDMSCR 0xFF852130
+#endif
#define SYS_AXI256_SYXDMSCR 0xFF862000
#define SYS_AXI256_MPXDMSCR 0xFF862004
@@ -407,6 +606,16 @@
#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
#define MXT_SYXDMSCR 0xFF872000
+#if defined(CONFIG_R8A7792)
+#define MXT_IMRSLVDMSCR 0xFF872110
+#define MXT_VINSLVDMSCR 0xFF872114
+#define MXT_VSP1SLVDMSCR 0xFF87211C
+#define MXT_VSPD0SLVDMSCR 0xFF872120
+#define MXT_VSPD1SLVDMSCR 0xFF872124
+#define MXT_MAP1SLVDMSCR 0xFF872128
+#define MXT_MAP2SLVDMSCR 0xFF87212C
+#define MXT_MAP2BSLVDMSCR 0xFF872134
+#else /* R8A7792 */
#define MXT_CMM0SLVDMSCR 0xFF872100
#define MXT_CMM1SLVDMSCR 0xFF872104
#define MXT_CMM2SLVDMSCR 0xFF872108
@@ -421,6 +630,58 @@
#define MXT_VSPD1SLVDMSCR 0xFF87212C
#define MXT_MAP1SLVDMSCR 0xFF872130
#define MXT_MAP2SLVDMSCR 0xFF872134
+#endif /* R8A7792 */
+
+/* DMS Register (MXI) */
+#if defined(CONFIG_R8A7792)
+#define MXI_JPURDMSCR 0xFE964200
+#define MXI_JPUWDMSCR 0xFE966200
+#define MXI_VCTU0RDMSCR 0xFE964600
+#define MXI_VCTU0WDMSCR 0xFE966600
+#define MXI_VDCTU0RDMSCR 0xFE964604
+#define MXI_VDCTU0WDMSCR 0xFE966604
+#define MXI_VDCTU1RDMSCR 0xFE964608
+#define MXI_VDCTU1WDMSCR 0xFE966608
+#define MXI_VIN0WDMSCR 0xFE967608
+#define MXI_VIN1WDMSCR 0xFE966E08
+#define MXI_RDRWDMSCR 0xFE96760C
+#define MXI_IMS01RDMSCR 0xFE965600
+#define MXI_IMS01WDMSCR 0xFE967600
+#define MXI_IMS23RDMSCR 0xFE965604
+#define MXI_IMS23WDMSCR 0xFE967604
+#define MXI_IMS45RDMSCR 0xFE964E00
+#define MXI_IMS45WDMSCR 0xFE966E00
+#define MXI_IMRRDMSCR 0xFE964E04
+#define MXI_IMRWDMSCR 0xFE966E04
+#define MXI_ROTCE4RDMSCR 0xFE965200
+#define MXI_ROTCE4WDMSCR 0xFE967200
+#define MXI_ROTVLC4RDMSCR 0xFE965204
+#define MXI_ROTVLC4WDMSCR 0xFE967204
+#define MXI_VSPD0RDMSCR 0xFE964A00
+#define MXI_VSPD0WDMSCR 0xFE966A00
+#define MXI_VSPD1RDMSCR 0xFE964A04
+#define MXI_VSPD1WDMSCR 0xFE966A04
+#define MXI_DU0RDMSCR 0xFE964A08
+#define MXI_DU0WDMSCR 0xFE966A08
+#define MXI_VSP0RDMSCR 0xFE964A0C
+#define MXI_VSP0WDMSCR 0xFE966A0C
+#define MXI_ROTCE0RDMSCR 0xFE965A00
+#define MXI_ROTCE0WDMSCR 0xFE967A00
+#define MXI_ROTVLC0RDMSCR 0xFE965A04
+#define MXI_ROTVLC0WDMSCR 0xFE967A04
+#define MXI_ROTCE1RDMSCR 0xFE965A08
+#define MXI_ROTCE1WDMSCR 0xFE967A08
+#define MXI_ROTVLC1RDMSCR 0xFE965A0C
+#define MXI_ROTVLC1WDMSCR 0xFE967A0C
+#define MXI_ROTCE2RDMSCR 0xFE965E00
+#define MXI_ROTCE2WDMSCR 0xFE967E00
+#define MXI_ROTVLC2RDMSCR 0xFE965E04
+#define MXI_ROTVLC2WDMSCR 0xFE967E04
+#define MXI_ROTCE3RDMSCR 0xFE965E08
+#define MXI_ROTCE3WDMSCR 0xFE967E08
+#define MXI_ROTVLC3RDMSCR 0xFE965E0C
+#define MXI_ROTVLC3WDMSCR 0xFE967E0C
+#endif /* R8A7792 */
#define CCI_AXI_MMUS0DMSCR 0xFF882000
#define CCI_AXI_SYX2DMSCR 0xFF882004
@@ -597,6 +858,81 @@
u32 dbwt0cnf2;
u32 dbwt0cnf3;
u32 dbwt0cnf4;
+ u32 dummy17[27]; /* 0x394 .. 0x3FC */
+ u32 dbeccmode;
+ u32 dummy18[3]; /* 0x404 .. 0x40C */
+ u32 dbeccarea0;
+ u32 dbeccarea1;
+ u32 dbeccarea2;
+ u32 dbeccarea3;
+ u32 dummy19[4]; /* 0x420 .. 0x42C */
+ u32 dbeccintenable;
+ u32 dbeccintdetect;
+ u32 dummy20[22]; /* 0x438 .. 0x48C */
+ u32 dbeccmodulcnt;
+ u32 dummy21[27]; /* 0x494 .. 0x4FC */
+ u32 dbschecnt0;
+ u32 dummy22[63]; /* 0x504 .. 0x5FC */
+ u32 dbreradr0;
+ u32 dbreblane0;
+ u32 dbrerid0;
+ u32 dbrerinfo0;
+ u32 dbureradr0;
+ u32 dbureblane0;
+ u32 dburerid0;
+ u32 dburerinfo0;
+ u32 dbreradr1;
+ u32 dbreblane1;
+ u32 dbrerid1;
+ u32 dbrerinfo1;
+ u32 dbureradr1;
+ u32 dbureblane1;
+ u32 dburerid1;
+ u32 dburerinfo1;
+ u32 dbreradr2;
+ u32 dbreblane2;
+ u32 dbrerid2;
+ u32 dbrerinfo2;
+ u32 dbureradr2;
+ u32 dbureblane2;
+ u32 dburerid2;
+ u32 dburerinfo2;
+ u32 dbreradr3;
+ u32 dbreblane3;
+ u32 dbrerid3;
+ u32 dbrerinfo3;
+ u32 dbureradr3;
+ u32 dbureblane3;
+ u32 dburerid3;
+ u32 dburerinfo3;
+ u32 dummy23[160]; /* 0x680 .. 0x8FC */
+ u32 dbpccr;
+ u32 dbpeier;
+ u32 dbpeisr;
+ u32 dummy24;
+ u32 dbwdpesr0;
+ u32 dbwspesr0;
+ u32 dbpwear0;
+ u32 dbpweid0;
+ u32 dbpweinfo0;
+ u32 dummy25[3]; /* 0x924 .. 0x92C */
+ u32 dbwdpesr1;
+ u32 dbwspesr1;
+ u32 dbpwear1;
+ u32 dbpweid1;
+ u32 dbpweinfo1;
+ u32 dummy26[3]; /* 0x944 .. 0x94C */
+ u32 dbwdpesr2;
+ u32 dbwspesr2;
+ u32 dbpwear2;
+ u32 dbpweid2;
+ u32 dbpweinfo2;
+ u32 dummy27[3]; /* 0x964 .. 0x96C */
+ u32 dbwdpesr3;
+ u32 dbwspesr3;
+ u32 dbpwear3;
+ u32 dbpweid3;
+ u32 dbpweinfo3;
};
/* GPIO */
@@ -678,6 +1014,10 @@
u32 dummy2; /* 0x3C */
u32 mxrtcr;
u32 mxwtcr;
+ u32 mxaxirtcr; /* R8a7792 only */
+ u32 mxaxiwtcr;
+ u32 mxs3crtcr;
+ u32 mxs3cwtcr;
};
struct rcar_mxi_qos {
@@ -699,6 +1039,7 @@
u32 qosthres1;
u32 qosthres2;
u32 qosqon;
+ u32 qosin;
};
#endif