commit 9cd9e13475a30ae34882b6ae42373b7ba7ec02d6
author Poonam Aggrwal <poonam.aggrwal@freescale.com> Wed Jun 23 19:32:28 2010 +0530
committer Wolfgang Denk <wd@denx.de> Tue Jun 29 21:01:07 2010 +0200
tree 4a029912084daeb20457c7007cbeec4af881d498
parent 625e7f186df919d5710daf9f9cc1e87561c0514e

85xx/p1_p2_rdb: Modify the CLK_CTRL value for DDR at 667MHz

Use a slighly larger value of CLK_CTRL for DDR at 667MHz
which fixes random crashes while linux booting.

Applicable for both NAND and NOR boot.

Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

board/freescale/p1_p2_rdb/ddr.c

diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index fccc4f8..15b46b0 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -76,7 +76,7 @@
 #define CONFIG_SYS_DDR_TIMING_0_667	0x55770802
 #define CONFIG_SYS_DDR_TIMING_1_667	0x5f599543
 #define CONFIG_SYS_DDR_TIMING_2_667	0x0fa074d1
-#define CONFIG_SYS_DDR_CLK_CTRL_667	0x02800000
+#define CONFIG_SYS_DDR_CLK_CTRL_667	0x03000000
 #define CONFIG_SYS_DDR_MODE_1_667	0x00040852
 #define CONFIG_SYS_DDR_MODE_2_667	0x00000000
 #define CONFIG_SYS_DDR_INTERVAL_667	0x0a280100