Merge tag 'efi-2023-04-rc1-3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2023-04-rc1-3
Documentation:
* Improve the sl-mx8mm documenation
* Clean up README, move some section to HTML
* Man-pages for the mtime and sleep command
* Description of reducible builds
* Document dynamic event handlers
UEFI:
* Support scrolling in eficonfig command
Other:
* fix mtest on 64 bit systems
diff --git a/MAINTAINERS b/MAINTAINERS
index 8dcce88..eb6289d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1245,6 +1245,7 @@
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-pmic.git
F: drivers/power/
+F: include/power/
POWERPC
M: Wolfgang Denk <wd@denx.de>
diff --git a/Makefile b/Makefile
index eb354c0..9c38cc2 100644
--- a/Makefile
+++ b/Makefile
@@ -1441,6 +1441,7 @@
ifdef U_BOOT_ITS
u-boot.itb: u-boot-nodtb.bin \
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SANDBOX),dts/dt.dtb) \
+ $(if $(CONFIG_MULTI_DTB_FIT),$(FINAL_DTB_CONTAINER)) \
$(U_BOOT_ITS) FORCE
$(call if_changed,mkfitimage)
$(BOARD_SIZE_CHECK)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 44256d9..3ecd6a8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -340,7 +340,6 @@
zynq-zybo-z7.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
avnet-ultra96-rev1.dtb \
- avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \
zynqmp-a2197-revA.dtb \
zynqmp-dlc21-revA.dtb \
zynqmp-e-a2197-00-revA.dtb \
@@ -354,6 +353,8 @@
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb \
zynqmp-mini-qspi.dtb \
+ zynqmp-sm-k24-revA.dtb \
+ zynqmp-smk-k24-revA.dtb \
zynqmp-sm-k26-revA.dtb \
zynqmp-smk-k26-revA.dtb \
zynqmp-sck-kr-g-revA.dtbo \
@@ -1253,7 +1254,9 @@
k3-j7200-r5-common-proc-board.dtb \
k3-j721e-sk.dtb \
k3-j721e-r5-sk.dtb
-dtb-$(CONFIG_SOC_K3_J721S2) += k3-j721s2-common-proc-board.dtb\
+dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\
+ k3-am68-sk-r5-base-board.dtb\
+ k3-j721s2-common-proc-board.dtb\
k3-j721s2-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
k3-am642-r5-evm.dtb \
diff --git a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts
deleted file mode 100644
index 6d1448e..0000000
--- a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-
-/*
- * UltraZed-EV Carrier Card v1 (based on the UltraZed-EV SoM)
- * http://ultrazed.org/product/ultrazed-ev-carrier-card
- */
-
-/dts-v1/;
-
-#include "avnet-ultrazedev-som-v1.0.dtsi"
-
-/ {
- model = "Avnet UltraZed EV Carrier Card v1.0";
- compatible = "avnet,ultrazedev-cc-v1.0-ultrazedev-som-v1.0",
- "xlnx,zynqmp";
- chosen {
- stdout-path = "serial0:115200n8";
- };
- aliases {
- ethernet0 = &gem3;
- nvmem0 = &eeprom;
- serial0 = &uart0;
- };
-};
-
-&uart0 {
- device_type = "serial";
- status = "okay";
-};
-
-&i2c_cc {
- /* Microchip 24AA025E48T-I/OT: 2K I2C Serial EEPROM with EUI-48 */
- eeprom: eeprom@51 {
- compatible = "atmel,24c02";
- reg = <0x51>;
- };
-
- /* IDT Versa Clock 5P49V5935B */
- vc5: clock-generator@6a {
- compatible = "idt,5p49v5935";
- reg = <0x6a>;
- #clock-cells = <1>;
- };
-};
-
-/* Ethernet RJ-45 */
-&gem3 {
- status = "okay";
-};
-
-/* microSD card slot */
-&sdhci1 {
- status = "okay";
- xlnx,mio-bank = <1>;
- clock-frequency = <199998000>;
- max-frequency = <50000000>;
- no-1-8-v;
- disable-wp;
-};
diff --git a/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi b/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi
deleted file mode 100644
index cbcb290..0000000
--- a/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi
+++ /dev/null
@@ -1,56 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-
-/*
- * UltraZed-EV SoM v1
- * http://ultrazed.org/product/ultrazed-ev
- */
-
-/dts-v1/;
-
-#include "zynqmp.dtsi"
-#include "zynqmp-clk-ccf.dtsi"
-
-/ {
- model = "Avnet UltraZed EV SoM v1.0";
- compatible = "avnet,ultrazedev-som-v1.0", "xlnx,zynqmp";
- memory {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>, /* 2 GB @ offset 0 */
- <0x8 0x0 0x0 0x80000000>; /* 2 GB @ offset 32GB */
- };
-};
-
-&i2c1 {
- clock-frequency = <400000>;
- status = "okay";
-
- i2cswitch@70 {
- compatible = "nxp,pca9543";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x70>;
-
- /* I2C connected to Carrier Card via JX3A1/JX3C1 */
- i2c_cc: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-};
-
-/* Marvell 88E1512-A0-NNP2I000 Ethernet PHY */
-&gem3 {
- phy-mode = "rgmii-id";
- phy-handle = <&gem3phy>;
- gem3phy: ethernet-phy@0 {
- reg = <0>;
- };
-};
-
-/* Micron MTFC8GAKAJCN-4M 8 GB eMMC */
-&sdhci0 {
- status = "okay";
- xlnx,mio-bank = <0>;
- clock-frequency = <199998000>;
-};
diff --git a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
new file mode 100644
index 0000000..12faaae
--- /dev/null
+++ b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &timer1;
+ };
+
+ aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
+ serial2 = &main_uart8;
+ i2c0 = &wkup_i2c0;
+ i2c1 = &mcu_i2c0;
+ i2c2 = &mcu_i2c1;
+ i2c3 = &main_i2c0;
+ ethernet0 = &cpsw_port1;
+ mmc1 = &main_sdhci1;
+ };
+};
+
+&wkup_i2c0 {
+ u-boot,dm-spl;
+};
+
+&cbass_main {
+ u-boot,dm-spl;
+};
+
+&main_navss {
+ u-boot,dm-spl;
+};
+
+&cbass_mcu_wakeup {
+ u-boot,dm-spl;
+
+ timer1: timer@40400000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x40400000 0x0 0x80>;
+ ti,timer-alwon;
+ clock-frequency = <250000000>;
+ u-boot,dm-spl;
+ };
+
+ chipid@43000014 {
+ u-boot,dm-spl;
+ };
+};
+
+&mcu_navss {
+ u-boot,dm-spl;
+};
+
+&mcu_ringacc {
+ reg = <0x0 0x2b800000 0x0 0x400000>,
+ <0x0 0x2b000000 0x0 0x400000>,
+ <0x0 0x28590000 0x0 0x100>,
+ <0x0 0x2a500000 0x0 0x40000>,
+ <0x0 0x28440000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
+ u-boot,dm-spl;
+};
+
+&mcu_udmap {
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ u-boot,dm-spl;
+};
+
+&secure_proxy_main {
+ u-boot,dm-spl;
+};
+
+&sms {
+ u-boot,dm-spl;
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ u-boot,dm-spl;
+ };
+};
+
+&main_pmx0 {
+ u-boot,dm-spl;
+};
+
+&main_uart8_pins_default {
+ u-boot,dm-spl;
+};
+
+&main_mmc1_pins_default {
+ u-boot,dm-spl;
+};
+
+&wkup_pmx0 {
+ u-boot,dm-spl;
+};
+
+&k3_pds {
+ u-boot,dm-spl;
+};
+
+&k3_clks {
+ u-boot,dm-spl;
+};
+
+&k3_reset {
+ u-boot,dm-spl;
+};
+
+&main_uart8 {
+ u-boot,dm-spl;
+};
+
+&mcu_uart0 {
+ u-boot,dm-spl;
+};
+
+&wkup_uart0 {
+ u-boot,dm-spl;
+};
+
+&mcu_cpsw {
+ reg = <0x0 0x46000000 0x0 0x200000>,
+ <0x0 0x40f00200 0x0 0x8>;
+ reg-names = "cpsw_nuss", "mac_efuse";
+ /delete-property/ ranges;
+
+ cpsw-phy-sel@40f04040 {
+ compatible = "ti,am654-cpsw-phy-sel";
+ reg= <0x0 0x40f04040 0x0 0x4>;
+ reg-names = "gmii-sel";
+ };
+};
+
+&main_sdhci0 {
+ status = "disabled";
+};
+
+&main_sdhci1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/k3-am68-sk-base-board.dts b/arch/arm/dts/k3-am68-sk-base-board.dts
new file mode 100644
index 0000000..8fc0332
--- /dev/null
+++ b/arch/arm/dts/k3-am68-sk-base-board.dts
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Base Board: **Yet to Add**
+ */
+
+/dts-v1/;
+
+#include "k3-am68-sk-som.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ compatible = "ti,am68-sk", "ti,j721s2";
+ model = "Texas Instruments AM68 SK";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2880000";
+ };
+
+ aliases {
+ serial2 = &main_uart8;
+ mmc1 = &main_sdhci1;
+ };
+
+ vusb_main: fixedregulator-vusb-main5v0 {
+ /* USB MAIN INPUT 5V DC */
+ compatible = "regulator-fixed";
+ regulator-name = "vusb-main5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: fixedregulator-vsys3v3 {
+ /* Output of LM5141 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vusb_main>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_mmc1: fixedregulator-sd {
+ /* Output of TPS22918 */
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vsys_3v3>;
+ gpio = <&exp1 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_sd_dv: gpio-regulator-TLV71033 {
+ /* Output of TLV71033 */
+ compatible = "regulator-gpio";
+ regulator-name = "tlv71033";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_pins_default>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ vin-supply = <&vsys_3v3>;
+ gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
+ };
+};
+
+&main_pmx0 {
+ main_uart8_pins_default: main-uart8-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */
+ J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
+ J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
+ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
+ >;
+ };
+
+ main_i2c0_pins_default: i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
+ J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
+ J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
+ J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
+ J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
+ J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
+ J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
+ J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
+ >;
+ };
+
+ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */
+ >;
+ };
+};
+
+&wkup_pmx0 {
+ mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
+ J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
+ J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
+ J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
+ J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
+ J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
+ J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
+ J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
+ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
+ J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
+ J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
+ J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
+ >;
+ };
+
+ mcu_mdio_pins_default: mcu-mdio-pins-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
+ J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
+ >;
+ };
+};
+
+&main_gpio2 {
+ status = "disabled";
+};
+
+&main_gpio4 {
+ status = "disabled";
+};
+
+&main_gpio6 {
+ status = "disabled";
+};
+
+&wkup_gpio1 {
+ status = "disabled";
+};
+
+&wkup_uart0 {
+ status = "reserved";
+};
+
+&main_uart0 {
+ status = "disabled";
+};
+
+&main_uart1 {
+ status = "disabled";
+};
+
+&main_uart2 {
+ status = "disabled";
+};
+
+&main_uart3 {
+ status = "disabled";
+};
+
+&main_uart4 {
+ status = "disabled";
+};
+
+&main_uart5 {
+ status = "disabled";
+};
+
+&main_uart6 {
+ status = "disabled";
+};
+
+&main_uart7 {
+ status = "disabled";
+};
+
+&main_uart8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart8_pins_default>;
+ /* Shared with TFA on this platform */
+ power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
+};
+
+&main_uart9 {
+ status = "disabled";
+};
+
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ exp1: gpio@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPN", "HDMI_PDN",
+ "HDMI_LS_OE", "DP0_3V3_EN", "BOARDID_EEPROM_WP",
+ "CAN_STB", "","GPIO_uSD_PWR_EN", "EDP_ENABLE",
+ "IO_EXP_PCIE1_M2_RSTZ", "IO_EXP_MCU_RGMII_RSTZ",
+ "IO_EXP_CSI1_EXP_RSTZ", "","CSI0_B_GPIO1",
+ "CSI1_B_GPIO1";
+ };
+};
+
+&main_i2c1 {
+ status = "disabled";
+};
+
+&main_i2c2 {
+ status = "disabled";
+};
+
+&main_i2c3 {
+ status = "disabled";
+};
+
+&main_i2c4 {
+ status = "disabled";
+};
+
+&main_i2c5 {
+ status = "disabled";
+};
+
+&main_i2c6 {
+ status = "disabled";
+};
+
+&main_sdhci0 {
+ status = "disabled";
+};
+
+&main_sdhci1 {
+ /* SD card */
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ pinctrl-names = "default";
+ disable-wp;
+ vmmc-supply = <&vdd_mmc1>;
+ vqmmc-supply = <&vdd_sd_dv>;
+};
+
+&mcu_cpsw {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+};
+
+&davinci_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&phy0>;
+};
+
+&mcu_mcan0 {
+ status = "disabled";
+};
+
+&mcu_mcan1 {
+ status = "disabled";
+};
+
+&main_mcan0 {
+ status = "disabled";
+};
+
+&main_mcan1 {
+ status = "disabled";
+};
+
+&main_mcan2 {
+ status = "disabled";
+};
+
+&main_mcan3 {
+ status = "disabled";
+};
+
+&main_mcan4 {
+ status = "disabled";
+};
+
+&main_mcan5 {
+ status = "disabled";
+};
+
+&main_mcan6 {
+ status = "disabled";
+};
+
+&main_mcan7 {
+ status = "disabled";
+};
+
+&main_mcan8 {
+ status = "disabled";
+};
+
+&main_mcan9 {
+ status = "disabled";
+};
+
+&main_mcan10 {
+ status = "disabled";
+};
+
+&main_mcan11 {
+ status = "disabled";
+};
+
+&main_mcan12 {
+ status = "disabled";
+};
+
+&main_mcan13 {
+ status = "disabled";
+};
+
+&main_mcan14 {
+ status = "disabled";
+};
+
+&main_mcan15 {
+ status = "disabled";
+};
+
+&main_mcan17 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/k3-am68-sk-r5-base-board.dts b/arch/arm/dts/k3-am68-sk-r5-base-board.dts
new file mode 100644
index 0000000..46ee6c442
--- /dev/null
+++ b/arch/arm/dts/k3-am68-sk-r5-base-board.dts
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am68-sk-som.dtsi"
+#include "k3-j721s2-ddr-evm-lp4-4266.dtsi"
+#include "k3-j721s2-ddr.dtsi"
+
+/ {
+ chosen {
+ firmware-loader = &fs_loader0;
+ stdout-path = &main_uart8;
+ tick-timer = &timer1;
+ };
+
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a72_0;
+ };
+
+ fs_loader0: fs_loader@0 {
+ compatible = "u-boot,fs-loader";
+ u-boot,dm-pre-reloc;
+ };
+
+ a72_0: a72@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x0 0x00a90000 0x0 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 202 0>;
+ clocks = <&k3_clks 61 1>;
+ assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;
+ assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-rates = <200000000>, <2000000000>;
+ ti,sci = <&sms>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ u-boot,dm-spl;
+ };
+
+ clk_200mhz: dummy_clock_200mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ u-boot,dm-spl;
+ };
+
+ clk_19_2mhz: dummy_clock_19_2mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_mcu_wakeup {
+ sa3_secproxy: secproxy@44880000 {
+ u-boot,dm-spl;
+ compatible = "ti,am654-secure-proxy";
+ reg = <0x0 0x44880000 0x0 0x20000>,
+ <0x0 0x44860000 0x0 0x20000>,
+ <0x0 0x43600000 0x0 0x10000>;
+ reg-names = "rt", "scfg", "target_data";
+ #mbox-cells = <1>;
+ };
+
+ mcu_secproxy: secproxy@2a380000 {
+ compatible = "ti,am654-secure-proxy";
+ reg = <0x0 0x2a380000 0x0 0x80000>,
+ <0x0 0x2a400000 0x0 0x80000>,
+ <0x0 0x2a480000 0x0 0x80000>;
+ reg-names = "rt", "scfg", "target_data";
+ #mbox-cells = <1>;
+ u-boot,dm-spl;
+ };
+
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>;
+ mbox-names = "tx", "rx", "boot_notify";
+ u-boot,dm-spl;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&mcu_secproxy 21>,
+ <&mcu_secproxy 23>;
+ u-boot,dm-spl;
+ };
+};
+
+&main_pmx0 {
+ main_uart8_pins_default: main-uart8-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
+ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
+ J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
+ J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
+ J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
+ J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
+ J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
+ J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
+ >;
+ };
+
+ main_usbss0_pins_default: main-usbss0-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
+ >;
+ };
+};
+
+&wkup_pmx0 {
+ mcu_uart0_pins_default: mcu-uart0-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /*(C24) WKUP_GPIO0_13.MCU_UART0_RXD*/
+ J721S2_WKUP_IOPAD(0x0f0, PIN_OUTPUT, 0) /*(C25) WKUP_GPIO0_12.MCU_UART0_TXD*/
+ >;
+ };
+
+ wkup_uart0_pins_default: wkup-uart0-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /*(E25) WKUP_GPIO0_6.WKUP_UART0_CTSn*/
+ J721S2_WKUP_IOPAD(0x0dc, PIN_OUTPUT, 0) /*(F28) WKUP_GPIO0_7.WKUP_UART0_RTSn*/
+ J721S2_WKUP_IOPAD(0x0b0, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
+ J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
+ >;
+ };
+
+};
+
+&sms {
+ mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+ mbox-names = "tx", "rx", "notify";
+ ti,host-id = <4>;
+ ti,secure-host;
+ u-boot,dm-spl;
+};
+
+&wkup_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+};
+
+&mcu_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_uart0_pins_default>;
+};
+
+&main_uart8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart8_pins_default>;
+};
+
+&main_sdhci0 {
+ status = "disabled";
+};
+
+&main_sdhci1 {
+ /delete-property/ power-domains;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ pinctrl-names = "default";
+ clock-names = "clk_xin";
+ clocks = <&clk_200mhz>;
+ ti,driver-strength-ohm = <50>;
+};
+
+&mcu_ringacc {
+ ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+ ti,sci = <&dm_tifs>;
+};
+
+#include "k3-am68-sk-base-board-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am68-sk-som.dtsi b/arch/arm/dts/k3-am68-sk-som.dtsi
new file mode 100644
index 0000000..cb1c58f
--- /dev/null
+++ b/arch/arm/dts/k3-am68-sk-som.dtsi
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j721s2.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ /* 16 GB RAM */
+ reg = <0x00 0x80000000 0x00 0x80000000>,
+ <0x08 0x80000000 0x03 0x80000000>;
+ };
+
+ /* Reserving memory regions still pending */
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+};
+
+&mailbox0_cluster0 {
+ status = "disabled";
+};
+
+&mailbox0_cluster1 {
+ status = "disabled";
+};
+
+&mailbox0_cluster2 {
+ status = "disabled";
+};
+
+&mailbox0_cluster3 {
+ status = "disabled";
+};
+
+&mailbox0_cluster4 {
+ status = "disabled";
+};
+
+&mailbox0_cluster5 {
+ status = "disabled";
+};
+
+&mailbox0_cluster6 {
+ status = "disabled";
+};
+
+&mailbox0_cluster7 {
+ status = "disabled";
+};
+
+&mailbox0_cluster8 {
+ status = "disabled";
+};
+
+&mailbox0_cluster9 {
+ status = "disabled";
+};
+
+&mailbox0_cluster10 {
+ status = "disabled";
+};
+
+&mailbox0_cluster11 {
+ status = "disabled";
+};
+
+&mailbox1_cluster0 {
+ status = "disabled";
+};
+
+&mailbox1_cluster1 {
+ status = "disabled";
+};
+
+&mailbox1_cluster2 {
+ status = "disabled";
+};
+
+&mailbox1_cluster3 {
+ status = "disabled";
+};
+
+&mailbox1_cluster4 {
+ status = "disabled";
+};
+
+&mailbox1_cluster5 {
+ status = "disabled";
+};
+
+&mailbox1_cluster6 {
+ status = "disabled";
+};
+
+&mailbox1_cluster7 {
+ status = "disabled";
+};
+
+&mailbox1_cluster8 {
+ status = "disabled";
+};
+
+&mailbox1_cluster9 {
+ status = "disabled";
+};
+
+&mailbox1_cluster10 {
+ status = "disabled";
+};
+
+&mailbox1_cluster11 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
index 4538345..fabe592 100644
--- a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
+++ b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
@@ -257,6 +257,364 @@
syscon = <&gcr>;
status = "disabled";
};
+
+ i2c1: i2c@81000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x81000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb1_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@82000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x82000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb2_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@83000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x83000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb3_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@84000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x84000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb4_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@85000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x85000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb5_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@86000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x86000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb6_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@87000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x87000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb7_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@88000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x88000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb8_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c9: i2c@89000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x89000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb9_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c10: i2c@8a000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x8a000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb10_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c11: i2c@8b000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x8b000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb11_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c12: i2c@8c000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x8c000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb12_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c13: i2c@8d000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x8d000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb13_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c14: i2c@8e000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x8e000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb14_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c15: i2c@8f000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x8f000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb15_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c16: i2c@fff00000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb16_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c17: i2c@fff01000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff01000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb17_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c18: i2c@fff02000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff02000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb18_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c19: i2c@fff03000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff03000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb19_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c20: i2c@fff04000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff04000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb20_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c21: i2c@fff05000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff05000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb21_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c22: i2c@fff06000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff06000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb22_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c23: i2c@fff07000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff07000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb23_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c24: i2c@fff08000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff08000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c25: i2c@fff09000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff09000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c26: i2c@fff0a000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff0a000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
};
};
};
diff --git a/arch/arm/dts/nuvoton-npcm845-evb.dts b/arch/arm/dts/nuvoton-npcm845-evb.dts
index 53f4c6a..3cab780 100644
--- a/arch/arm/dts/nuvoton-npcm845-evb.dts
+++ b/arch/arm/dts/nuvoton-npcm845-evb.dts
@@ -11,7 +11,37 @@
aliases {
serial0 = &serial0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ ethernet2 = &gmac2;
+ ethernet3 = &gmac3;
i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ i2c10 = &i2c10;
+ i2c11 = &i2c11;
+ i2c12 = &i2c12;
+ i2c13 = &i2c13;
+ i2c14 = &i2c14;
+ i2c15 = &i2c15;
+ i2c16 = &i2c16;
+ i2c17 = &i2c17;
+ i2c18 = &i2c18;
+ i2c19 = &i2c19;
+ i2c20 = &i2c20;
+ i2c21 = &i2c21;
+ i2c22 = &i2c22;
+ i2c23 = &i2c23;
+ i2c24 = &i2c24;
+ i2c25 = &i2c25;
+ i2c26 = &i2c26;
spi0 = &fiu0;
spi1 = &fiu1;
spi3 = &fiu3;
@@ -106,6 +136,49 @@
status = "okay";
};
+&gmac0 {
+ phy-mode = "sgmii";
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-gpio = <&gpio5 30 GPIO_ACTIVE_LOW>; /* gpio190 */
+ status = "okay";
+};
+
+&gmac1 {
+ phy-mode = "rgmii-id";
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; /* gpio162 */
+ status = "okay";
+};
+
+&gmac2 {
+ phy-mode = "NC-SI";
+ max-speed = <100>;
+ use-ncsi;
+ pinctrl-0 = <&r1_pins
+ &r1en_pins
+ &r1oen_pins>;
+ status = "disabled";
+};
+
+&gmac3 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&r2_pins
+ &r2oen_pins
+ &r2en_pins
+ &gpio91o_pins
+ &gpio92o_pins>;
+ snps,bitbang-mii;
+ snps,mdc-gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio91 */
+ snps,mdio-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* gpio92 */
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; /* gpio93 */
+ status = "okay";
+};
+
&spi1 {
status = "okay";
};
@@ -142,10 +215,135 @@
phys = <&usbphy3 4>;
};
+&rng {
+ status = "okay";
+};
+
+&aes {
+ status = "okay";
+};
+
+&sha {
+ status = "okay";
+};
+
+&otp {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
};
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+ tmp100@48 {
+ compatible = "tmp100";
+ reg = <0x48>;
+ status = "okay";
+ };
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&i2c14 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
+
+&i2c16 {
+ status = "okay";
+};
+
+&i2c17 {
+ status = "okay";
+};
+
+&i2c18 {
+ status = "okay";
+};
+
+&i2c19 {
+ status = "okay";
+};
+
+&i2c20 {
+ status = "okay";
+};
+
+&i2c21 {
+ status = "okay";
+};
+
+&i2c22 {
+ status = "okay";
+};
+
+&i2c23 {
+ status = "okay";
+};
+
+&i2c24 {
+ status = "okay";
+};
+
+&i2c25 {
+ status = "okay";
+};
+
+&i2c26 {
+ status = "okay";
+};
+
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <
diff --git a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
index d21e504..be2ad0c 100644
--- a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
+++ b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
@@ -59,6 +59,68 @@
clocks = <&clk_refclk>;
};
+ gmac0: eth@f0802000 {
+ device_type = "network";
+ compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
+ reg = <0x0 0xf0802000 0x0 0x2000>,
+ <0x0 0xf0780000 0x0 0x200>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clk NPCM8XX_CLK_AHB>;
+ clock-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rg1mdio_pins>;
+ resets = <&rstc2 NPCM8XX_RESET_GMAC1>;
+ status = "disabled";
+ };
+
+ gmac1: eth@f0804000 {
+ device_type = "network";
+ compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
+ reg = <0x0 0xf0804000 0x0 0x2000>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clk NPCM8XX_CLK_AHB>;
+ clock-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rg2_pins
+ &rg2mdio_pins>;
+ resets = <&rstc2 NPCM8XX_RESET_GMAC2>;
+ status = "disabled";
+ };
+
+ gmac2: eth@f0806000 {
+ device_type = "network";
+ compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
+ reg = <0x0 0xf0806000 0x0 0x2000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clk NPCM8XX_CLK_AHB>;
+ clock-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&r1_pins
+ &r1err_pins
+ &r1md_pins>;
+ resets = <&rstc1 NPCM8XX_RESET_GMAC3>;
+ status = "disabled";
+ };
+
+ gmac3: eth@f0808000 {
+ device_type = "network";
+ compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
+ reg = <0x0 0xf0808000 0x0 0x2000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clk NPCM8XX_CLK_AHB>;
+ clock-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&r2_pins
+ &r2err_pins
+ &r2md_pins>;
+ resets = <&rstc1 NPCM8XX_RESET_GMAC4>;
+ status = "disabled";
+ };
+
ehci1: usb@f0828100 {
compatible = "nuvoton,npcm845-ehci";
reg = <0x0 0xf0828100 0x0 0x1000>;
@@ -236,6 +298,49 @@
status = "disabled";
};
+ serial1: serial@1000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x1000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
+ status = "disabled";
+ };
+
+ serial2: serial@2000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x2000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
+ status = "disabled";
+ };
+
+ serial3: serial@3000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x3000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
+ status = "disabled";
+ };
+
+ serial4: serial@4000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x4000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART2>, <&clk NPCM8XX_CLK_PLL2DIV2>;
+ status = "disabled";
+ };
+
+ serial5: serial@5000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x5000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART2>, <&clk NPCM8XX_CLK_PLL2DIV2>;
+ status = "disabled";
+ };
+
+ serial6: serial@6000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x6000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART2>, <&clk NPCM8XX_CLK_PLL2DIV2>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
gpio0: gpio0@10000 {
compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
reg = <0x10000 0xB0>;
@@ -299,6 +404,35 @@
gpio-controller;
gpio-bank-name = "gpio7";
};
+
+ rng: rng@b000 {
+ compatible = "nuvoton,npcm845-rng";
+ reg = <0xb000 0x8>;
+ status = "disabled";
+ };
+
+ otp: otp@189000 {
+ compatible = "nuvoton,npcm845-otp";
+ reg = <0x189000 0x1000>;
+ status = "disabled";
+ };
+
+ aes: aes@f0858000 {
+ compatible = "nuvoton,npcm845-aes";
+ reg = <0x0 0xf0858000 0x0 0x1000>,
+ <0x0 0xf0851000 0x0 0x1000>;
+ status = "disabled";
+ clocks = <&clk NPCM8XX_CLK_AHB>;
+ clock-names = "clk_ahb";
+ };
+
+ sha:sha@f085a000 {
+ compatible = "nuvoton,npcm845-sha";
+ reg = <0x0 0xf085a000 0x0 0x1000>;
+ status = "disabled";
+ clocks = <&clk NPCM8XX_CLK_AHB>;
+ clock-names = "clk_ahb";
+ };
};
};
pinctrl: pinctrl@f0800000 {
diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts
index 0461219..bf0d89a 100644
--- a/arch/arm/dts/zynqmp-dlc21-revA.dts
+++ b/arch/arm/dts/zynqmp-dlc21-revA.dts
@@ -154,8 +154,6 @@
&usb0 {
status = "okay";
- xlnx,usb-polarity = <0>;
- xlnx,usb-reset-mode = <0>;
};
&dwc3_0 {
@@ -170,8 +168,6 @@
&usb1 {
status = "disabled"; /* Any unknown issue with USB-C */
- xlnx,usb-polarity = <0>;
- xlnx,usb-reset-mode = <0>;
};
&dwc3_1 {
diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
index e004283..02d2427 100644
--- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
@@ -303,8 +303,6 @@
&usb0 { /* USB0 MIO52-63 */
status = "okay";
- xlnx,usb-polarity = <0>;
- xlnx,usb-reset-mode = <0>;
};
&dwc3_0 {
diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
index 1fa023f..2d7fe59 100644
--- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@@ -461,8 +461,6 @@
&usb0 {
status = "okay";
- xlnx,usb-polarity = <0>;
- xlnx,usb-reset-mode = <0>;
};
&dwc3_0 {
@@ -474,8 +472,6 @@
&usb1 {
status = "disabled"; /* not at mem board */
- xlnx,usb-polarity = <0>;
- xlnx,usb-reset-mode = <0>;
};
&dwc3_1 {
diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
index 2271a6a..e46748d 100644
--- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
@@ -463,8 +463,6 @@
&usb0 {
status = "okay";
- xlnx,usb-polarity = <0>;
- xlnx,usb-reset-mode = <0>;
};
&dwc3_0 {
@@ -476,8 +474,6 @@
&usb1 {
status = "disabled"; /* not at mem board */
- xlnx,usb-polarity = <0>;
- xlnx,usb-reset-mode = <0>;
};
&dwc3_1 {
diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
index a89046a..f564817 100644
--- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
@@ -457,8 +457,6 @@
&usb0 {
status = "okay";
- xlnx,usb-polarity = <0>;
- xlnx,usb-reset-mode = <0>;
};
&dwc3_0 {
@@ -470,8 +468,6 @@
&usb1 {
status = "disabled"; /* not at mem board */
- xlnx,usb-polarity = <0>;
- xlnx,usb-reset-mode = <0>;
};
&dwc3_1 {
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
index b3fe42f..d63deb8 100644
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
@@ -543,8 +543,6 @@
&usb0 {
status = "okay";
- xlnx,usb-polarity = <0>;
- xlnx,usb-reset-mode = <0>;
phy-names = "usb3-phy";
phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
};
@@ -559,8 +557,6 @@
&usb1 {
status = "okay";
- xlnx,usb-polarity = <0>;
- xlnx,usb-reset-mode = <0>;
};
&dwc3_1 {
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
index 735c1e3..83c6502 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
@@ -18,6 +18,7 @@
&{/} {
compatible = "xlnx,zynqmp-sk-kr260-revA",
"xlnx,zynqmp-sk-kr260", "xlnx,zynqmp";
+ model = "ZynqMP KR260 revA";
ina260-u14 {
compatible = "iio-hwmon";
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
index 6359061..f41a2f8 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
@@ -18,6 +18,7 @@
&{/} {
compatible = "xlnx,zynqmp-sk-kr260-revB",
"xlnx,zynqmp-sk-kr260", "xlnx,zynqmp";
+ model = "ZynqMP KR260 revB";
ina260-u14 {
compatible = "iio-hwmon";
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
index b714bd3..0be5b29 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -25,6 +25,7 @@
"xlnx,zynqmp-sk-kv260-revY",
"xlnx,zynqmp-sk-kv260-revZ",
"xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
+ model = "ZynqMP KV260 revA";
};
&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index a1d8f9f..fca57a6 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -19,6 +19,7 @@
compatible = "xlnx,zynqmp-sk-kv260-rev1",
"xlnx,zynqmp-sk-kv260-revB",
"xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
+ model = "ZynqMP KV260 revB";
};
&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
diff --git a/arch/arm/dts/zynqmp-sm-k24-revA.dts b/arch/arm/dts/zynqmp-sm-k24-revA.dts
new file mode 100644
index 0000000..2451440
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sm-k24-revA.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP SM-K24 RevA
+ *
+ * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2022, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include "zynqmp-sm-k26-revA.dts"
+
+/ {
+ model = "ZynqMP SM-K24 RevA";
+ compatible = "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24",
+ "xlnx,zynqmp";
+
+ memory@0 {
+ device_type = "memory"; /* 2GB */
+ reg = <0 0 0 0x80000000>;
+ };
+};
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index bae24aa..aafaaec 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -53,7 +53,7 @@
gpio-keys {
compatible = "gpio-keys";
autorepeat;
- fwuen {
+ key-fwuen {
label = "fwuen";
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
linux,code = <BTN_MISC>;
diff --git a/arch/arm/dts/zynqmp-smk-k24-revA.dts b/arch/arm/dts/zynqmp-smk-k24-revA.dts
new file mode 100644
index 0000000..7308983
--- /dev/null
+++ b/arch/arm/dts/zynqmp-smk-k24-revA.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP SMK-K24 RevA
+ *
+ * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2022, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include "zynqmp-sm-k24-revA.dts"
+
+/ {
+ model = "ZynqMP SMK-K24 RevA";
+ compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24",
+ "xlnx,zynqmp";
+};
+
+&sdhci0 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index 5e7bc73..eea703a 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -49,7 +49,7 @@
gpio-keys {
compatible = "gpio-keys";
autorepeat;
- sw4 {
+ switch-4 {
label = "sw4";
gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 9d8e551..d78bfb8 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -47,7 +47,7 @@
gpio-keys {
compatible = "gpio-keys";
autorepeat;
- sw19 {
+ switch-19 {
label = "sw19";
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_DOWN>;
diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts
index 2422558..de3b5ab 100644
--- a/arch/arm/dts/zynqmp-zcu102-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revB.dts
@@ -16,16 +16,20 @@
&gem3 {
phy-handle = <&phyc>;
- phyc: ethernet-phy@c {
- reg = <0xc>;
- ti,rx-internal-delay = <0x8>;
- ti,tx-internal-delay = <0xa>;
- ti,fifo-depth = <0x1>;
- ti,dp83867-rxctrl-strap-quirk;
- /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
+ mdio: mdio {
+ phyc: ethernet-phy@c {
+ #phy-cells = <0x1>;
+ compatible = "ethernet-phy-id2000.a231";
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+ };
+ /* Cleanup from RevA */
+ /delete-node/ ethernet-phy@21;
};
- /* Cleanup from RevA */
- /delete-node/ ethernet-phy@21;
};
/* Fix collision with u61 */
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 4858b4d..266c24e 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -47,7 +47,7 @@
gpio-keys {
compatible = "gpio-keys";
autorepeat;
- sw19 {
+ switch-19 {
label = "sw19";
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_DOWN>;
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index 2e95f22..8535cc0 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -47,7 +47,7 @@
gpio-keys {
compatible = "gpio-keys";
autorepeat;
- sw19 {
+ switch-19 {
label = "sw19";
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_DOWN>;
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index b210bc4..0a06c73 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -280,10 +280,10 @@
interrupt-parent = <&gic>;
interrupts = <0 124 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14e8>;
power-domains = <&zynqmp_firmware PD_GDMA>;
- #dma-cells = <1>;
};
fpd_dma_chan2: dma-controller@fd510000 {
@@ -293,10 +293,10 @@
interrupt-parent = <&gic>;
interrupts = <0 125 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14e9>;
power-domains = <&zynqmp_firmware PD_GDMA>;
- #dma-cells = <1>;
};
fpd_dma_chan3: dma-controller@fd520000 {
@@ -306,10 +306,10 @@
interrupt-parent = <&gic>;
interrupts = <0 126 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ea>;
power-domains = <&zynqmp_firmware PD_GDMA>;
- #dma-cells = <1>;
};
fpd_dma_chan4: dma-controller@fd530000 {
@@ -319,10 +319,10 @@
interrupt-parent = <&gic>;
interrupts = <0 127 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14eb>;
power-domains = <&zynqmp_firmware PD_GDMA>;
- #dma-cells = <1>;
};
fpd_dma_chan5: dma-controller@fd540000 {
@@ -332,10 +332,10 @@
interrupt-parent = <&gic>;
interrupts = <0 128 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ec>;
power-domains = <&zynqmp_firmware PD_GDMA>;
- #dma-cells = <1>;
};
fpd_dma_chan6: dma-controller@fd550000 {
@@ -345,10 +345,10 @@
interrupt-parent = <&gic>;
interrupts = <0 129 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ed>;
power-domains = <&zynqmp_firmware PD_GDMA>;
- #dma-cells = <1>;
};
fpd_dma_chan7: dma-controller@fd560000 {
@@ -358,10 +358,10 @@
interrupt-parent = <&gic>;
interrupts = <0 130 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ee>;
power-domains = <&zynqmp_firmware PD_GDMA>;
- #dma-cells = <1>;
};
fpd_dma_chan8: dma-controller@fd570000 {
@@ -371,10 +371,10 @@
interrupt-parent = <&gic>;
interrupts = <0 131 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ef>;
power-domains = <&zynqmp_firmware PD_GDMA>;
- #dma-cells = <1>;
};
gic: interrupt-controller@f9010000 {
@@ -411,10 +411,10 @@
interrupt-parent = <&gic>;
interrupts = <0 77 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x868>;
power-domains = <&zynqmp_firmware PD_ADMA>;
- #dma-cells = <1>;
};
lpd_dma_chan2: dma-controller@ffa90000 {
@@ -424,10 +424,10 @@
interrupt-parent = <&gic>;
interrupts = <0 78 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x869>;
power-domains = <&zynqmp_firmware PD_ADMA>;
- #dma-cells = <1>;
};
lpd_dma_chan3: dma-controller@ffaa0000 {
@@ -437,10 +437,10 @@
interrupt-parent = <&gic>;
interrupts = <0 79 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86a>;
power-domains = <&zynqmp_firmware PD_ADMA>;
- #dma-cells = <1>;
};
lpd_dma_chan4: dma-controller@ffab0000 {
@@ -450,10 +450,10 @@
interrupt-parent = <&gic>;
interrupts = <0 80 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86b>;
power-domains = <&zynqmp_firmware PD_ADMA>;
- #dma-cells = <1>;
};
lpd_dma_chan5: dma-controller@ffac0000 {
@@ -463,10 +463,10 @@
interrupt-parent = <&gic>;
interrupts = <0 81 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86c>;
power-domains = <&zynqmp_firmware PD_ADMA>;
- #dma-cells = <1>;
};
lpd_dma_chan6: dma-controller@ffad0000 {
@@ -476,10 +476,10 @@
interrupt-parent = <&gic>;
interrupts = <0 82 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86d>;
power-domains = <&zynqmp_firmware PD_ADMA>;
- #dma-cells = <1>;
};
lpd_dma_chan7: dma-controller@ffae0000 {
@@ -489,10 +489,10 @@
interrupt-parent = <&gic>;
interrupts = <0 83 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86e>;
power-domains = <&zynqmp_firmware PD_ADMA>;
- #dma-cells = <1>;
};
lpd_dma_chan8: dma-controller@ffaf0000 {
@@ -502,10 +502,10 @@
interrupt-parent = <&gic>;
interrupts = <0 84 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86f>;
power-domains = <&zynqmp_firmware PD_ADMA>;
- #dma-cells = <1>;
};
mc: memory-controller@fd070000 {
@@ -540,6 +540,7 @@
iommus = <&smmu 0x874>;
power-domains = <&zynqmp_firmware PD_ETH_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
+ reset-names = "gem0_rst";
};
gem1: ethernet@ff0c0000 {
@@ -554,6 +555,7 @@
iommus = <&smmu 0x875>;
power-domains = <&zynqmp_firmware PD_ETH_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
+ reset-names = "gem1_rst";
};
gem2: ethernet@ff0d0000 {
@@ -568,6 +570,7 @@
iommus = <&smmu 0x876>;
power-domains = <&zynqmp_firmware PD_ETH_2>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
+ reset-names = "gem2_rst";
};
gem3: ethernet@ff0e0000 {
@@ -582,6 +585,7 @@
iommus = <&smmu 0x877>;
power-domains = <&zynqmp_firmware PD_ETH_3>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
+ reset-names = "gem3_rst";
};
gpio: gpio@ff0a0000 {
@@ -842,7 +846,7 @@
power-domains = <&zynqmp_firmware PD_UART_1>;
};
- usb0: usb0@ff9d0000 {
+ usb0: usb@ff9d0000 {
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
@@ -866,7 +870,6 @@
interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
iommus = <&smmu 0x860>;
snps,quirk-frame-length-adjustment = <0x20>;
- snps,refclk_fladj;
clock-names = "ref";
snps,enable_guctl1_resume_quirk;
snps,enable_guctl1_ipd_quirk;
@@ -875,7 +878,7 @@
};
};
- usb1: usb1@ff9e0000 {
+ usb1: usb@ff9e0000 {
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
@@ -898,7 +901,6 @@
interrupts = <0 70 4>, <0 74 4>, <0 76 4>;
iommus = <&smmu 0x861>;
snps,quirk-frame-length-adjustment = <0x20>;
- snps,refclk_fladj;
clock-names = "ref";
snps,enable_guctl1_resume_quirk;
snps,enable_guctl1_ipd_quirk;
@@ -934,21 +936,23 @@
interrupt-names = "ams-irq";
reg = <0x0 0xffa50000 0x0 0x800>;
reg-names = "ams-base";
- #address-cells = <2>;
- #size-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
#io-channel-cells = <1>;
- ranges;
+ ranges = <0 0 0xffa50800 0x800>;
- ams_ps: ams_ps@ffa50800 {
+ ams_ps: ams_ps@0 {
compatible = "xlnx,zynqmp-ams-ps";
status = "disabled";
- reg = <0x0 0xffa50800 0x0 0x400>;
+ reg = <0x0 0x400>;
};
- ams_pl: ams_pl@ffa50c00 {
+ ams_pl: ams_pl@400 {
compatible = "xlnx,zynqmp-ams-pl";
status = "disabled";
- reg = <0x0 0xffa50c00 0x0 0x400>;
+ reg = <0x400 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
diff --git a/arch/arm/include/asm/arch-npcm8xx/aes.h b/arch/arm/include/asm/arch-npcm8xx/aes.h
new file mode 100644
index 0000000..255efcb
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/aes.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _NPCM_AES_H_
+#define _NPCM_AES_H_
+
+#define AES_OP_ENCRYPT 0
+#define AES_OP_DECRYPT 1
+#define SIZE_AES_BLOCK (AES128_KEY_LENGTH)
+
+struct npcm_aes_regs {
+ unsigned char reserved_0[0x400]; // 0x000
+ unsigned int aes_key_0; // 0x400
+ unsigned int aes_key_1; // 0x404
+ unsigned int aes_key_2; // 0x408
+ unsigned int aes_key_3; // 0x40c
+ unsigned char reserved_1[0x30]; // 0x410
+ unsigned int aes_iv_0; // 0x440
+ unsigned char reserved_2[0x1c]; // 0x444
+ unsigned int aes_ctr_0; // 0x460
+ unsigned char reserved_3[0x0c]; // 0x464
+ unsigned int aes_busy; // 0x470
+ unsigned char reserved_4[0x04]; // 0x474
+ unsigned int aes_sk; // 0x478
+ unsigned char reserved_5[0x14]; // 0x47c
+ unsigned int aes_prev_iv_0; // 0x490
+ unsigned char reserved_6[0x0c]; // 0x494
+ unsigned int aes_din_dout; // 0x4a0
+ unsigned char reserved_7[0x1c]; // 0x4a4
+ unsigned int aes_control; // 0x4c0
+ unsigned int aes_version; // 0x4c4
+ unsigned int aes_hw_flags; // 0x4c8
+ unsigned char reserved_8[0x28]; // 0x4cc
+ unsigned int aes_sw_reset; // 0x4f4
+ unsigned char reserved_9[0x08]; // 0x4f8
+ unsigned int aes_fifo_data; // 0x500
+ unsigned char reserved_10[0xfc]; // 0x504
+ unsigned int aes_fifo_status; // 0x600
+};
+
+#define AES_BUSY_BIT BIT(0)
+#define SW_RESET_BIT BIT(0)
+#define AES_SK_BIT BIT(0)
+
+#define DIN_FIFO_FULL BIT(0)
+#define DIN_FIFO_EMPTY BIT(1)
+#define DOUT_FIFO_FULL BIT(2)
+#define DOUT_FIFO_EMPTY BIT(3)
+#define DIN_FIFO_OVERFLOW BIT(4)
+#define DOUT_FIFO_UNDERFLOW BIT(5)
+
+int npcm_aes_select_key(u8 fkeyind);
+
+#endif
diff --git a/arch/arm/include/asm/arch-npcm8xx/otp.h b/arch/arm/include/asm/arch-npcm8xx/otp.h
new file mode 100644
index 0000000..c8d50fb
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/otp.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _NPCM_OTP_H_
+#define _NPCM_OTP_H_
+
+#ifdef CONFIG_ARCH_NPCM8XX
+enum {
+ NPCM_KEY_SA = 0,
+ NPCM_FUSE_SA = 0,
+ NPCM_NUM_OF_SA = 1
+};
+#else
+enum {
+ NPCM_KEY_SA = 0,
+ NPCM_FUSE_SA = 1,
+ NPCM_NUM_OF_SA = 2
+};
+#endif
+
+/* arrray images in flash, to program during fisrt boot (offsets in sector) */
+#define SA_KEYS_FLASH_IMAGE_OFFSET (0x000)
+#define SA_FUSE_FLASH_IMAGE_OFFSET (0x400)
+#define SA_TAG_FLASH_IMAGE_OFFSET (0x800)
+/* F U S E I M G S */
+#define SA_TAG_FLASH_IMAGE_VAL {0x46, 0x55, 0x53, 0x45, 0x49, 0x4d, 0x47, 0x53}
+#define SA_TAG_FLASH_IMAGE_SIZE (8)
+
+#define SA_FUSE_FUSTRAP_OFFSET (0x00)
+#define SA_FUSE_FUSTRAP_OSECBOOT_MASK (0x00800000)
+
+struct npcm_otp_regs {
+ unsigned int fst;
+ unsigned int faddr;
+ unsigned int fdata;
+ unsigned int fcfg;
+ unsigned int fustrap_fkeyind;
+ unsigned int fctl;
+};
+
+#define FST_RDY BIT(0)
+#define FST_RDST BIT(1)
+#define FST_RIEN BIT(2)
+
+#ifdef CONFIG_ARCH_NPCM8XX
+#define FADDR_BYTEADDR(addr) ((addr) << 3)
+#define FADDR_BITPOS(pos) ((pos) << 0)
+#define FADDR_VAL(addr, pos) (FADDR_BITPOS(pos) | FADDR_BYTEADDR(addr))
+#define FADDR_IN_PROG BIT(16)
+#else
+#define FADDR_BYTEADDR(addr) ((addr) << 0)
+#define FADDR_BITPOS(pos) ((pos) << 10)
+#define FADDR_VAL(addr, pos) (FADDR_BYTEADDR(addr) | FADDR_BITPOS(pos))
+#endif
+
+#define FDATA_MASK (0xff)
+
+#define FUSTRAP_O_SECBOOT BIT(23)
+#define FCFG_FDIS BIT(31)
+#define FKEYIND_KVAL BIT(0)
+#define FKEYIND_KSIZE_MASK (0x00000070)
+#define FKEYIND_KSIZE_128 (0x4 << 4)
+#define FKEYIND_KSIZE_192 (0x5 << 4)
+#define FKEYIND_KSIZE_256 (0x6 << 4)
+#define FKEYIND_KIND_MASK (0x000c0000)
+#define FKEYIND_KIND_KEY(indx) ((indx) << 18)
+
+/* Program cycle initiation values (sequence of two adjacent writes) */
+#define PROGRAM_ARM 0x1
+#define PROGRAM_INIT 0xBF79E5D0
+
+/* Read cycle initiation value */
+#define READ_INIT 0x02
+
+/* Value to clean FDATA contents */
+#define FDATA_CLEAN_VALUE 0x01
+
+#ifdef CONFIG_ARCH_NPCM8XX
+#define NPCM_OTP_ARR_BYTE_SIZE 8192
+#else
+#define NPCM_OTP_ARR_BYTE_SIZE 1024
+#endif
+
+#define MIN_PROGRAM_PULSES 4
+#define MAX_PROGRAM_PULSES 20
+
+int fuse_prog_image(u32 bank, uintptr_t address);
+int fuse_program_data(u32 bank, u32 word, u8 *data, u32 size);
+int npcm_otp_select_key(u8 key_index);
+bool npcm_otp_is_fuse_array_disabled(u32 arr);
+void npcm_otp_nibble_parity_ecc_encode(u8 *datain, u8 *dataout, u32 size);
+void npcm_otp_majority_rule_ecc_encode(u8 *datain, u8 *dataout, u32 size);
+
+#endif
diff --git a/arch/arm/include/asm/arch-npcm8xx/rng.h b/arch/arm/include/asm/arch-npcm8xx/rng.h
new file mode 100644
index 0000000..897e8fe
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/rng.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _NPCM_RNG_H_
+#define _NPCM_RNG_H_
+
+struct npcm_rng_regs {
+ unsigned int rngcs;
+ unsigned int rngd;
+ unsigned int rngmode;
+};
+
+#define RNGCS_RNGE (1 << 0)
+#define RNGCS_DVALID (1 << 1)
+#define RNGCS_CLKP(range) ((0x0f & (range)) << 2)
+#define RNGMODE_M1ROSEL_VAL (0x02) /* Ring Oscillator Select for Method I */
+
+/*----------------------------------------------------------------------------*/
+/* Core Domain Clock Frequency Range for the selected value is higher */
+/* than or equal to the actual Core domain clock frequency */
+/*----------------------------------------------------------------------------*/
+enum {
+ RNG_CLKP_80_100_MHZ = 0x00, /*default */
+ RNG_CLKP_60_80_MHZ = 0x01,
+ RNG_CLKP_50_60_MHZ = 0x02,
+ RNG_CLKP_40_50_MHZ = 0x03,
+ RNG_CLKP_30_40_MHZ = 0x04,
+ RNG_CLKP_25_30_MHZ = 0x05,
+ RNG_CLKP_20_25_MHZ = 0x06,
+ RNG_CLKP_5_20_MHZ = 0x07,
+ RNG_CLKP_2_15_MHZ = 0x08,
+ RNG_CLKP_9_12_MHZ = 0x09,
+ RNG_CLKP_7_9_MHZ = 0x0A,
+ RNG_CLKP_6_7_MHZ = 0x0B,
+ RNG_CLKP_5_6_MHZ = 0x0C,
+ RNG_CLKP_4_5_MHZ = 0x0D,
+ RNG_CLKP_3_4_MHZ = 0x0E,
+ RNG_NUM_OF_CLKP
+};
+
+void npcm_rng_init(void);
+void npcm_rng_disable(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-npcm8xx/sha.h b/arch/arm/include/asm/arch-npcm8xx/sha.h
new file mode 100644
index 0000000..ec0ec9c
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/sha.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _NPCM_SHA_H_
+#define _NPCM_SHA_H_
+
+#define HASH_DIG_H_NUM 8
+
+/* SHA type */
+enum npcm_sha_type {
+ npcm_sha_type_sha2 = 0,
+ npcm_sha_type_sha1,
+ npcm_sha_type_num
+};
+
+struct npcm_sha_regs {
+ unsigned int hash_data_in;
+ unsigned char hash_ctr_sts;
+ unsigned char reserved_0[0x03];
+ unsigned char hash_cfg;
+ unsigned char reserved_1[0x03];
+ unsigned char hash_ver;
+ unsigned char reserved_2[0x13];
+ unsigned int hash_dig[HASH_DIG_H_NUM];
+};
+
+#define HASH_CTR_STS_SHA_EN BIT(0)
+#define HASH_CTR_STS_SHA_BUSY BIT(1)
+#define HASH_CTR_STS_SHA_RST BIT(2)
+#define HASH_CFG_SHA1_SHA2 BIT(0)
+
+int npcm_sha_calc(u8 type, const u8 *buf, u32 len, u8 *digest);
+int npcm_sha_selftest(u8 type);
+
+#endif
diff --git a/arch/arm/mach-k3/include/mach/sys_proto.h b/arch/arm/mach-k3/include/mach/sys_proto.h
index 60287b2..3d3d90d 100644
--- a/arch/arm/mach-k3/include/mach/sys_proto.h
+++ b/arch/arm/mach-k3/include/mach/sys_proto.h
@@ -19,4 +19,7 @@
bool soc_is_j721e(void);
bool soc_is_j7200(void);
+void k3_spl_init(void);
+void k3_mem_init(void);
+bool check_rom_loaded_sysfw(void);
#endif
diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c
index 0206b01..09e55ed 100644
--- a/arch/arm/mach-k3/j721s2_init.c
+++ b/arch/arm/mach-k3/j721s2_init.c
@@ -93,7 +93,7 @@
sizeof(struct rom_extended_boot_data));
}
-void board_init_f(ulong dummy)
+void k3_spl_init(void)
{
struct udevice *dev;
int ret;
@@ -154,6 +154,17 @@
/* Output System Firmware version info */
k3_sysfw_print_ver();
+}
+
+bool check_rom_loaded_sysfw(void)
+{
+ return is_rom_loaded_sysfw(&bootdata);
+}
+
+void k3_mem_init(void)
+{
+ struct udevice *dev;
+ int ret;
if (IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM)) {
ret = uclass_get_device_by_name(UCLASS_MISC, "msmc", &dev);
diff --git a/arch/arm/mach-versal-net/Kconfig b/arch/arm/mach-versal-net/Kconfig
index 62825e1..edff5b0 100644
--- a/arch/arm/mach-versal-net/Kconfig
+++ b/arch/arm/mach-versal-net/Kconfig
@@ -21,6 +21,18 @@
Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
will be used for board configuration.
+config COUNTER_FREQUENCY
+ int "Timer clock frequency"
+ default 0
+ help
+ Setup time clock frequency for certain platform
+
+config IOU_SWITCH_DIVISOR0
+ hex "IOU switch divisor0"
+ default 0x20
+ help
+ Setup time clock divisor for input clock.
+
config SYS_MEM_RSVD_FOR_MMU
bool "Reserve memory for MMU Table"
help
diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h b/arch/arm/mach-versal-net/include/mach/hardware.h
index 808ce48..c5e4e22 100644
--- a/arch/arm/mach-versal-net/include/mach/hardware.h
+++ b/arch/arm/mach-versal-net/include/mach/hardware.h
@@ -8,6 +8,36 @@
#include <linux/bitops.h>
#endif
+struct crlapb_regs {
+ u32 reserved0[67];
+ u32 cpu_r5_ctrl;
+ u32 reserved;
+ u32 iou_switch_ctrl; /* 0x114 */
+ u32 reserved1[13];
+ u32 timestamp_ref_ctrl; /* 0x14c */
+ u32 reserved3[108];
+ u32 rst_cpu_r5;
+ u32 reserved2[17];
+ u32 rst_timestamp; /* 0x348 */
+};
+
+struct iou_scntrs_regs {
+ u32 counter_control_register; /* 0x0 */
+ u32 reserved0[7];
+ u32 base_frequency_id_register; /* 0x20 */
+};
+
+#define VERSAL_NET_CRL_APB_BASEADDR 0xEB5E0000
+#define VERSAL_NET_IOU_SCNTR_SECURE 0xEC920000
+
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25)
+#define IOU_SWITCH_CTRL_CLKACT_BIT BIT(25)
+#define IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8
+#define IOU_SCNTRS_CONTROL_EN 1
+
+#define crlapb_base ((struct crlapb_regs *)VERSAL_NET_CRL_APB_BASEADDR)
+#define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_NET_IOU_SCNTR_SECURE)
+
#define PMC_TAP 0xF11A0000
#define PMC_TAP_IDCODE (PMC_TAP + 0)
diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c
index cea6d56..eaa095b 100644
--- a/arch/microblaze/cpu/spl.c
+++ b/arch/microblaze/cpu/spl.c
@@ -14,8 +14,6 @@
#include <asm/u-boot.h>
#include <linux/stringify.h>
-bool boot_linux;
-
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = BOOT_DEVICE_NOR;
@@ -41,17 +39,12 @@
image_entry(NULL, 0, (ulong)spl_image->arg);
}
-#endif /* CONFIG_SPL_OS_BOOT */
int spl_start_uboot(void)
{
-#ifdef CONFIG_SPL_OS_BOOT
- if (boot_linux)
- return 0;
-#endif
-
- return 1;
+ return 0;
}
+#endif /* CONFIG_SPL_OS_BOOT */
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
diff --git a/board/cortina/presidio-asic/lowlevel_init.S b/board/cortina/presidio-asic/lowlevel_init.S
index 8d8842e..220ec79 100644
--- a/board/cortina/presidio-asic/lowlevel_init.S
+++ b/board/cortina/presidio-asic/lowlevel_init.S
@@ -34,10 +34,8 @@
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
branch_if_slave x0, 1f
-#ifndef CONFIG_TARGET_VENUS
ldr x0, =GICD_BASE
bl gic_init_secure
-#endif
1:
#if defined(CONFIG_GICV3)
ldr x0, =GICR_BASE
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index 4d28582..c86715f 100644
--- a/board/ti/j721s2/evm.c
+++ b/board/ti/j721s2/evm.c
@@ -23,11 +23,10 @@
#include <asm/arch/sys_proto.h>
#include <dm.h>
#include <dm/uclass-internal.h>
+#include <dm/root.h>
#include "../common/board_detect.h"
-#define board_is_j721s2_som() board_ti_k3_is("J721S2X-PM1-SOM")
-
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
@@ -73,16 +72,6 @@
return 0;
}
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
- if (!strcmp(name, "k3-j721s2-common-proc-board"))
- return 0;
-
- return -1;
-}
-#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
@@ -101,15 +90,32 @@
#endif
#ifdef CONFIG_TI_I2C_BOARD_DETECT
+/*
+ * Functions specific to EVM and SK designs of J721S2/AM68 family.
+ */
+
+#define board_is_j721s2_som() board_ti_k3_is("J721S2X-PM1-SOM")
+
+#define board_is_am68_sk_som() board_ti_k3_is("AM68-SK-SOM")
+
int do_board_detect(void)
{
int ret;
+ if (board_ti_was_eeprom_read())
+ return 0;
+
ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
CONFIG_EEPROM_CHIP_ADDRESS);
- if (ret)
- pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
- CONFIG_EEPROM_CHIP_ADDRESS, ret);
+ if (ret) {
+ printf("EEPROM not available at 0x%02x, trying to read at 0x%02x\n",
+ CONFIG_EEPROM_CHIP_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS + 1);
+ ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
+ CONFIG_EEPROM_CHIP_ADDRESS + 1);
+ if (ret)
+ pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
+ CONFIG_EEPROM_CHIP_ADDRESS + 1, ret);
+ }
return ret;
}
@@ -136,6 +142,8 @@
if (board_is_j721s2_som())
name = "j721s2";
+ else if (board_is_am68_sk_som())
+ name = "am68-sk";
else
printf("Unidentified board claims %s in eeprom header\n",
board_ti_get_name());
@@ -165,6 +173,28 @@
}
#endif
+/*
+ * This function chooses the right dtb based on the board name read from
+ * EEPROM if the EEPROM is programmed. Also, by default the boot chooses
+ * the EVM DTB if there is no EEPROM is programmed or not detected.
+ */
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ bool eeprom_read = board_ti_was_eeprom_read();
+
+ if (!eeprom_read || board_is_j721s2_som()) {
+ if (!strcmp(name, "k3-j721s2-common-proc-board"))
+ return 0;
+ } else if (!eeprom_read || board_is_am68_sk_som()) {
+ if (!strcmp(name, "k3-am68-sk-base-board"))
+ return 0;
+ }
+
+ return -1;
+}
+#endif
+
int board_late_init(void)
{
if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
@@ -177,4 +207,67 @@
void spl_board_init(void)
{
+}
+
+/* Support for the various EVM / SK families */
+#if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT)
+void do_dt_magic(void)
+{
+ int ret, rescan, mmc_dev = -1;
+ static struct mmc *mmc;
+
+ do_board_detect();
+
+ /*
+ * Board detection has been done.
+ * Let us see if another dtb wouldn't be a better match
+ * for our board
+ */
+ if (IS_ENABLED(CONFIG_CPU_V7R)) {
+ ret = fdtdec_resetup(&rescan);
+ if (!ret && rescan) {
+ dm_uninit();
+ dm_init_and_scan(true);
+ }
+ }
+
+ /*
+ * Because of multi DTB configuration, the MMC device has
+ * to be re-initialized after reconfiguring FDT inorder to
+ * boot from MMC. Do this when boot mode is MMC and ROM has
+ * not loaded SYSFW.
+ */
+ switch (spl_boot_device()) {
+ case BOOT_DEVICE_MMC1:
+ mmc_dev = 0;
+ break;
+ case BOOT_DEVICE_MMC2:
+ case BOOT_DEVICE_MMC2_2:
+ mmc_dev = 1;
+ break;
+ }
+
+ if (mmc_dev > 0 && !check_rom_loaded_sysfw()) {
+ ret = mmc_init_device(mmc_dev);
+ if (!ret) {
+ mmc = find_mmc_device(mmc_dev);
+ if (mmc) {
+ ret = mmc_init(mmc);
+ if (ret)
+ printf("mmc init failed with error: %d\n", ret);
+ }
+ }
+ }
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ k3_spl_init();
+#if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT)
+ do_dt_magic();
+#endif
+ k3_mem_init();
}
+#endif
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 59d87f2..fbc76ee 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -1,7 +1,9 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2014 - 2020 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * (C) Copyright 2014 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
*/
#include <common.h>
@@ -9,6 +11,7 @@
#include <efi_loader.h>
#include <env.h>
#include <image.h>
+#include <init.h>
#include <lmb.h>
#include <log.h>
#include <asm/global_data.h>
@@ -22,6 +25,7 @@
#include <i2c_eeprom.h>
#include <net.h>
#include <generated/dt.h>
+#include <slre.h>
#include <soc.h>
#include <linux/ctype.h>
#include <linux/kernel.h>
@@ -82,7 +86,7 @@
struct xilinx_legacy_format {
char board_sn[18]; /* 0x0 */
char unused0[14]; /* 0x12 */
- char eth_mac[6]; /* 0x20 */
+ char eth_mac[ETH_ALEN]; /* 0x20 */
char unused1[170]; /* 0x26 */
char board_name[11]; /* 0xd0 */
char unused2[5]; /* 0xdc */
@@ -98,9 +102,13 @@
for (i = 0; i < size; i++) {
byte = eeprom[i];
- /* Remove all ffs and spaces */
- if (byte == 0xff || byte == ' ')
+ /* Remove all non printable chars but ignore MAC address */
+ if ((i < offsetof(struct xilinx_legacy_format, eth_mac) ||
+ i >= offsetof(struct xilinx_legacy_format, unused1)) &&
+ (byte < '!' || byte > '~')) {
eeprom[i] = 0;
+ continue;
+ }
/* Convert strings to lower case */
if (byte >= 'A' && byte <= 'Z')
@@ -133,21 +141,25 @@
xilinx_eeprom_legacy_cleanup((char *)eeprom_content, size);
- printf("Xilinx I2C Legacy format at %s:\n", name);
- printf(" Board name:\t%s\n", eeprom_content->board_name);
- printf(" Board rev:\t%s\n", eeprom_content->board_revision);
- printf(" Board SN:\t%s\n", eeprom_content->board_sn);
+ /* Terminating \0 chars are the part of desc fields already */
+ strlcpy(desc->name, eeprom_content->board_name,
+ sizeof(eeprom_content->board_name) + 1);
+ strlcpy(desc->revision, eeprom_content->board_revision,
+ sizeof(eeprom_content->board_revision) + 1);
+ strlcpy(desc->serial, eeprom_content->board_sn,
+ sizeof(eeprom_content->board_sn) + 1);
eth_valid = is_valid_ethaddr((const u8 *)eeprom_content->eth_mac);
if (eth_valid)
- printf(" Ethernet mac:\t%pM\n", eeprom_content->eth_mac);
+ memcpy(desc->mac_addr[0], eeprom_content->eth_mac, ETH_ALEN);
- /* Terminating \0 chars ensure end of string */
- strcpy(desc->name, eeprom_content->board_name);
- strcpy(desc->revision, eeprom_content->board_revision);
- strcpy(desc->serial, eeprom_content->board_sn);
+ printf("Xilinx I2C Legacy format at %s:\n", name);
+ printf(" Board name:\t%s\n", desc->name);
+ printf(" Board rev:\t%s\n", desc->revision);
+ printf(" Board SN:\t%s\n", desc->serial);
+
if (eth_valid)
- memcpy(desc->mac_addr[0], eeprom_content->eth_mac, ETH_ALEN);
+ printf(" Ethernet mac:\t%pM\n", desc->mac_addr);
desc->header = EEPROM_HEADER_MAGIC;
@@ -468,6 +480,21 @@
{
debug("%s: Check %s, default %s\n", __func__, name, board_name);
+#if !defined(CONFIG_SPL_BUILD)
+ if (CONFIG_IS_ENABLED(REGEX)) {
+ struct slre slre;
+ int ret;
+
+ ret = slre_compile(&slre, name);
+ if (ret) {
+ ret = slre_match(&slre, board_name, strlen(board_name),
+ NULL);
+ debug("%s: name match ret = %d\n", __func__, ret);
+ return !ret;
+ }
+ }
+#endif
+
if (!strcmp(name, board_name))
return 0;
diff --git a/board/xilinx/common/fru_ops.c b/board/xilinx/common/fru_ops.c
index c4f009a..167252c 100644
--- a/board/xilinx/common/fru_ops.c
+++ b/board/xilinx/common/fru_ops.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * (C) Copyright 2019 - 2020 Xilinx, Inc.
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*/
#include <common.h>
@@ -61,9 +62,6 @@
{
int len;
- if (type_len == FRU_TYPELEN_EOF)
- return -EINVAL;
-
*type = (type_len & FRU_TYPELEN_CODE_MASK) >> FRU_TYPELEN_TYPE_SHIFT;
len = type_len & FRU_TYPELEN_LEN_MASK;
@@ -172,9 +170,16 @@
{
u8 i, type;
int len;
- u8 *data, *term, *limit;
+ u8 *data, *term, *limit, *next_addr, *eof;
memcpy(&fru_data.brd.ver, (void *)addr, 6);
+
+ /*
+ * eof marks the last data byte (without checksum). That's why checksum
+ * is address length - 1 and last data byte is length - 2.
+ */
+ eof = (u8 *)(fru_data.brd.len * 8 + addr - 2);
+
addr += 6;
data = (u8 *)&fru_data.brd.manufacturer_type_len;
@@ -184,10 +189,21 @@
for (i = 0; ; i++, data += FRU_BOARD_MAX_LEN) {
len = fru_check_type_len(*(u8 *)addr, fru_data.brd.lang_code,
&type);
+ next_addr = (u8 *)addr + 1;
+
+ if ((u8 *)addr >= eof) {
+ debug("Reach EOF record: addr %lx, eof %lx\n", addr,
+ (unsigned long)eof);
+ break;
+ }
+
/*
- * Stop cature if it end of fields
+ * Stop capture if the type is ASCII and valid field length
+ * is 1 (0xc1) and next FRU data is less than 0x20 (space " ")
+ * or it is 0x7f (delete 'DEL').
*/
- if (len == -EINVAL)
+ if (type == FRU_TYPELEN_TYPE_ASCII8 && len == 1 &&
+ (*next_addr < 0x20 || *next_addr == 0x7F))
break;
/* Stop when amount of chars is more then fields to record */
@@ -332,9 +348,11 @@
for (u8 i = 0; i < (sizeof(boardinfo) / sizeof(*boardinfo)); i++) {
len = fru_check_type_len(*data++, brd->lang_code,
&type);
- if (len == -EINVAL) {
- printf("**** EOF for Board Area ****\n");
- break;
+
+ /* Empty record has no len/type filled */
+ if (!len) {
+ debug("%s not found\n", boardinfo[i]);
+ continue;
}
if (type <= FRU_TYPELEN_TYPE_ASCII8 &&
@@ -344,11 +362,6 @@
else
debug("Type code: %s\n", typecode[type + 1]);
- if (!len) {
- debug("%s not found\n", boardinfo[i]);
- continue;
- }
-
switch (type) {
case FRU_TYPELEN_TYPE_BINARY:
debug("Length: %d\n", len);
diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c
index 7600319..5fb7110 100644
--- a/board/xilinx/versal-net/board.c
+++ b/board/xilinx/versal-net/board.c
@@ -121,6 +121,47 @@
int board_early_init_r(void)
{
+ u32 val;
+
+ if (current_el() != 3)
+ return 0;
+
+ debug("iou_switch ctrl div0 %x\n",
+ readl(&crlapb_base->iou_switch_ctrl));
+
+ writel(IOU_SWITCH_CTRL_CLKACT_BIT |
+ (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
+ &crlapb_base->iou_switch_ctrl);
+
+ /* Global timer init - Program time stamp reference clk */
+ val = readl(&crlapb_base->timestamp_ref_ctrl);
+ val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
+ writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+ debug("ref ctrl 0x%x\n",
+ readl(&crlapb_base->timestamp_ref_ctrl));
+
+ /* Clear reset of timestamp reg */
+ writel(0, &crlapb_base->rst_timestamp);
+
+ /*
+ * Program freq register in System counter and
+ * enable system counter.
+ */
+ writel(CONFIG_COUNTER_FREQUENCY,
+ &iou_scntr_secure->base_frequency_id_register);
+
+ debug("counter val 0x%x\n",
+ readl(&iou_scntr_secure->base_frequency_id_register));
+
+ writel(IOU_SCNTRS_CONTROL_EN,
+ &iou_scntr_secure->counter_control_register);
+
+ debug("scntrs control 0x%x\n",
+ readl(&iou_scntr_secure->counter_control_register));
+ debug("timer 0x%llx\n", get_ticks());
+ debug("timer 0x%llx\n", get_ticks());
+
return 0;
}
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index f9f5457..4cdc2ec 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -4,6 +4,7 @@
* Michal Simek <michal.simek@xilinx.com>
*/
+#include <command.h>
#include <common.h>
#include <cpu_func.h>
#include <env.h>
diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS
index 07b91b8..a4527f8 100644
--- a/board/xilinx/zynqmp/MAINTAINERS
+++ b/board/xilinx/zynqmp/MAINTAINERS
@@ -9,9 +9,3 @@
F: include/configs/xilinx_zynqmp*
F: configs/xilinx_zynqmp*
F: configs/avnet_ultra96_rev1_defconfig
-
-ARM ZYNQMP AVNET ULTRAZED EV BOARD
-M: Luca Ceresoli <luca.ceresoli@bootlin.com>
-S: Maintained
-F: arch/arm/dts/avnet-ultrazedev-*
-F: configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
diff --git a/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c b/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c
deleted file mode 100644
index d030e79..0000000
--- a/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c
+++ /dev/null
@@ -1,655 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
- */
-
-#include <asm/arch/psu_init_gpl.h>
-#include <xil_io.h>
-
-static unsigned long psu_pll_init_data(void)
-{
- psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
- psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U);
- psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
- psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
- mask_poll(0xFF5E0040, 0x00000002U);
- psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
- psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
- psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
- psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
- psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
- psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
- psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
- mask_poll(0xFF5E0040, 0x00000001U);
- psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
- psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
- psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
- psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014200U);
- psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
- psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
- mask_poll(0xFD1A0044, 0x00000001U);
- psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
- psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
- psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
- psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014800U);
- psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
- psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
- mask_poll(0xFD1A0044, 0x00000002U);
- psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
- psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
- psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
- psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
- psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
- psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
- mask_poll(0xFD1A0044, 0x00000004U);
- psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
- psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
-
- return 1;
-}
-
-static unsigned long psu_clock_init_data(void)
-{
- psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
- psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
- psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
- psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
- psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
- psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010602U);
- psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010602U);
- psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
- psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
- psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
- psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
- psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
- psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
- psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
- psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
- psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
- psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
- psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
- psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
- psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
- psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
- psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
- psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
- psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
- psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
- psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
- psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
- psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
- psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
- psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
- psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
- psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
- psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
- psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000303U);
- psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
- psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
- psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
- psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
- psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
- psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
-
- return 1;
-}
-
-static unsigned long psu_ddr_init_data(void)
-{
- psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
- psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
- psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
- psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U);
- psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
- psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
- psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00409410U);
- psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
- psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
- psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
- psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x009280D2U);
- psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
- psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
- psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
- psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0048051FU);
- psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020126U);
- psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
- psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002705U);
- psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09340301U);
- psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280200U);
- psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
- psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
- psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
- psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
- psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
- psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x131C2813U);
- psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041CU);
- psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0808050FU);
- psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
- psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
- psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
- psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
- psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
- psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x05050D08U);
- psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002040CU);
- psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1308010EU);
- psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
- psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
- psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201C9C2U);
- psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048C820DU);
- psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
- psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
- psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
- psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
- psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
- psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
- psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000A0BU);
- psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
- psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
- psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
- psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
- psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
- psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
- psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
- psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
- psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
- psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F08U);
- psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
- psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
- psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
- psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
- psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
- psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
- psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
- psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
- psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
- psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
- psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
- psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
- psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
- psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
- psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
- psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
- psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
- psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
- psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
- psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
- psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
- psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
- psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
- psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
- psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
- psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
- psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
- psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
- psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
- psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
- psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
- psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
- psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
- psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
- psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
- psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
- psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
- psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
- psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
- psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
- psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
- psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
- psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
- psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
- psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
- psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
- psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
- psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
- psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
- psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
- psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F12090U);
- psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
- psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
- psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x4B025810U);
- psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xEA601518U);
- psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x000E0000U);
- psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
- psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DDU);
- psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
- psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08261009U);
- psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28380008U);
- psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
- psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
- psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01A42B08U);
- psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00371009U);
- psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00001010U);
- psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
- psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
- psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000300U);
- psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000834U);
- psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
- psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U);
- psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
- psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
- psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
- psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
- psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
- psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
- psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
- psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
- psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
- psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
- psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
- psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
- psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
- psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
- psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
- psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
- psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
- psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
- psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
- psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AEA58U);
- psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
- psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
- psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
- psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
- psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
- psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
- psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
- psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
- psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
- psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
- psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
- psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
- psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
- psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
- psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
- psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
- psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
- psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
- psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
- psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
- psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
- psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
- psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
- psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
- psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
- psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
- psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
- psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
- psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
- psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
- psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
- psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
- psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
- psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
- psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
- psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
- psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
- psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
- psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
- psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
- psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
- psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
- psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
- psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
- psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
- psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
- psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
- psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
- psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
- psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
- psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
- psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
- psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
- psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
- psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
- psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
- psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
- psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
- psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
- psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
- psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
- psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x000E0000U);
- psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
- psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
- psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
- psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
- psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x000E0000U);
- psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
- psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
- psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
- psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
- psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x000E0000U);
- psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
- psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
- psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
- psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
- psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x000E0000U);
- psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
- psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
- psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
- psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
- psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x200E0000U);
- psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
- psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
- psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
- psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x000E0000U);
- psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
-
- return 1;
-}
-
-static unsigned long psu_ddr_qos_init_data(void)
-{
- return 1;
-}
-
-static unsigned long psu_mio_init_data(void)
-{
- psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
- psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
- psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
- psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
- psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
- psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
- psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
- psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
- psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
- psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
- psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
- psu_mask_write(0xFF180060, 0x000000FEU, 0x00000040U);
- psu_mask_write(0xFF180064, 0x000000FEU, 0x00000040U);
- psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
- psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
- psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
- psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
- psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
- psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
- psu_mask_write(0xFF180080, 0x000000FEU, 0x000000C0U);
- psu_mask_write(0xFF180084, 0x000000FEU, 0x000000C0U);
- psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
- psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
- psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
- psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
- psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
- psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U);
- psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
- psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
- psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
- psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
- psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
- psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
- psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
- psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
- psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
- psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
- psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
- psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
- psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
- psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
- psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
- psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
- psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
- psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
- psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
- psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
- psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
- psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
- psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
- psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
- psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
- psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
- psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50000000U);
- psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02006U);
- psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
- psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
- psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
- psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
- psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
- psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
- psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
- psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
- psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
- psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
- psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
- psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
- psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
- psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
- psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
- psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
- psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
- psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
- psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
- psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
-
- return 1;
-}
-
-static unsigned long psu_peripherals_pre_init_data(void)
-{
- psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
-
- return 1;
-}
-
-static unsigned long psu_peripherals_init_data(void)
-{
- psu_mask_write(0xFD1A0100, 0x000F807EU, 0x00000000U);
- psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
- psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
- psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
- psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
- psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
- psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
- psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
- psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
- psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U);
- psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
- psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
- psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
- psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
- psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
- psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
- psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
- psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
- psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
- psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
- psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
- psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
- psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
- psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
- psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
- psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
- psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
-
- mask_delay(1);
- psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
-
- mask_delay(5);
- psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
- psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U);
- psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U);
- psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U);
- mask_delay(1);
- psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U);
- mask_delay(5);
-
- return 1;
-}
-
-static unsigned long psu_afi_config(void)
-{
- psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
- psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
- psu_mask_write(0xFD615000, 0x00000F00U, 0x00000A00U);
-
- return 1;
-}
-
-static unsigned long psu_ddr_phybringup_data(void)
-{
- unsigned int regval = 0;
- unsigned int pll_retry = 10;
- unsigned int pll_locked = 0;
-
- while ((pll_retry > 0) && (!pll_locked)) {
- Xil_Out32(0xFD080004, 0x00040010);
- Xil_Out32(0xFD080004, 0x00040011);
-
- while ((Xil_In32(0xFD080030) & 0x1) != 1)
- ;
- pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
- >> 31;
- pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
- >> 16;
- pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
- >> 16;
- pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
- >> 16;
- pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
- >> 16;
- pll_retry--;
- }
- Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
- if (!pll_locked)
- return 0;
-
- Xil_Out32(0xFD080004U, 0x00040063U);
-
- while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
- ;
- prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
-
- while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
- ;
- Xil_Out32(0xFD0701B0U, 0x00000001U);
- Xil_Out32(0xFD070320U, 0x00000001U);
- while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
- ;
- prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
- Xil_Out32(0xFD080004, 0x0004FE01);
- regval = Xil_In32(0xFD080030);
- while (regval != 0x80000FFF)
- regval = Xil_In32(0xFD080030);
- regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
- if (regval != 0)
- return 0;
-
- Xil_Out32(0xFD080200U, 0x100091C7U);
- int cur_R006_tREFPRD;
-
- cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
- prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
-
- prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
- prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
- prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
- prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
- prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
- prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
-
- Xil_Out32(0xFD080004, 0x00060001);
- regval = Xil_In32(0xFD080030);
- while ((regval & 0x80004001) != 0x80004001)
- regval = Xil_In32(0xFD080030);
-
- prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
- prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
- prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
- prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
- prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
- prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
-
- Xil_Out32(0xFD080200U, 0x800091C7U);
- prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
-
- Xil_Out32(0xFD080004, 0x0000C001);
- regval = Xil_In32(0xFD080030);
- while ((regval & 0x80000C01) != 0x80000C01)
- regval = Xil_In32(0xFD080030);
-
- Xil_Out32(0xFD070180U, 0x01000040U);
- Xil_Out32(0xFD070060U, 0x00000000U);
- prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
-
- return 1;
-}
-
-static void init_peripheral(void)
-{
- psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
-}
-
-int psu_init(void)
-{
- int status = 1;
-
- status &= psu_mio_init_data();
- status &= psu_peripherals_pre_init_data();
- status &= psu_pll_init_data();
- status &= psu_clock_init_data();
- status &= psu_ddr_init_data();
- status &= psu_ddr_phybringup_data();
- status &= psu_peripherals_init_data();
- init_peripheral();
-
- status &= psu_afi_config();
- psu_ddr_qos_init_data();
-
- if (status == 0)
- return 1;
- return 0;
-}
diff --git a/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c
new file mode 100644
index 0000000..4510230
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c
@@ -0,0 +1,1061 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly,
+ int d_lock_cnt, int d_lfhf, int d_cp, int d_res)
+{
+ unsigned int pll_ctrl_regval;
+ unsigned int pll_status_regval;
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00010000U);
+ pll_ctrl_regval = pll_ctrl_regval | (div2 << 16);
+ Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+ pll_ctrl_regval = pll_ctrl_regval & (~0xFE000000U);
+ pll_ctrl_regval = pll_ctrl_regval | (d_lock_dly << 25);
+ Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x007FE000U);
+ pll_ctrl_regval = pll_ctrl_regval | (d_lock_cnt << 13);
+ Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00000C00U);
+ pll_ctrl_regval = pll_ctrl_regval | (d_lfhf << 10);
+ Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x000001E0U);
+ pll_ctrl_regval = pll_ctrl_regval | (d_cp << 5);
+ Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x0000000FU);
+ pll_ctrl_regval = pll_ctrl_regval | (d_res << 0);
+ Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00007F00U);
+ pll_ctrl_regval = pll_ctrl_regval | (ddr_pll_fbdiv << 8);
+ Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U);
+ pll_ctrl_regval = pll_ctrl_regval | (1 << 3);
+ Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U);
+ pll_ctrl_regval = pll_ctrl_regval | (1 << 0);
+ Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U);
+ pll_ctrl_regval = pll_ctrl_regval | (0 << 0);
+ Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+ pll_status_regval = 0x00000000;
+ while ((pll_status_regval & 0x00000002U) != 0x00000002U)
+ pll_status_regval = Xil_In32(((0xFD1A0000U) + 0x00000044));
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U);
+ pll_ctrl_regval = pll_ctrl_regval | (0 << 3);
+ Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+}
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014F00U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x8000FB15U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+ psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+ psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+ psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+ psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+ psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+ psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011603U);
+ psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011403U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000203U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000300U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00501B9BU);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00408093U);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030403U);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00680000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x0034001BU);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x13151117U);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x050A170FU);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x820D0010U);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B64228U);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x04918208U);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000F06U);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07C30U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U);
+ psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+ psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E5U);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282A0711U);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F012EU);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01262B0BU);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0043260BU);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000A14U);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000034U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x0000001BU);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000056U);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8C58U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F504U);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F504U);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU);
+ psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU);
+ psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+ psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+ psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180018, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180024, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180028, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180038, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180040, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180060, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180064, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180090, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180094, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50000000U);
+ psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02020U);
+ psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x00080814U);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x03F7F7EBU);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x00FC000BU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF18017C, 0x0357FFFFU, 0x0357FFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x0357FFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x0303FFF4U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+ psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFD1A0100, 0x0001807CU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+ psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+ psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
+ psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+ psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000010U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000004U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+ mask_delay(1);
+ psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+ mask_delay(5);
+ psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+ return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+ psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
+ psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+ psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+ psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U);
+ psu_mask_write(0xFD402868, 0x00000082U, 0x00000002U);
+ psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+ psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
+ psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+ psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
+ psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
+ psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+ psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+ psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+ psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+ psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+ psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+
+ serdes_illcalib(0, 0, 3, 0, 4, 0, 4, 0);
+ psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
+ psu_mask_write(0xFD410014, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
+ psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+ psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+ psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
+ psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+ psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+ psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+ psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+ psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+ mask_poll(0xFD4063E4, 0x00000010U);
+ mask_poll(0xFD40A3E4, 0x00000010U);
+
+ return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+ return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+ psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+
+ for (int tp = 0; tp < 20; tp++)
+ regval = Xil_In32(0xFD070018);
+ int cur_PLLCR0;
+
+ cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U;
+ int cur_DX8SL0PLLCR0;
+
+ cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U;
+ int cur_DX8SL1PLLCR0;
+
+ cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U;
+ int cur_DX8SL2PLLCR0;
+
+ cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U;
+ int cur_DX8SL3PLLCR0;
+
+ cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U;
+ int cur_DX8SL4PLLCR0;
+
+ cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U;
+ int cur_DX8SLBPLLCR0;
+
+ cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U;
+ Xil_Out32(0xFD080068, 0x02120000);
+ Xil_Out32(0xFD081404, 0x02120000);
+ Xil_Out32(0xFD081444, 0x02120000);
+ Xil_Out32(0xFD081484, 0x02120000);
+ Xil_Out32(0xFD0814C4, 0x02120000);
+ Xil_Out32(0xFD081504, 0x02120000);
+ Xil_Out32(0xFD0817C4, 0x02120000);
+ int cur_div2;
+
+ cur_div2 = (Xil_In32(0xFD1A002CU) & 0x00010000U) >> 0x00000010U;
+ int cur_fbdiv;
+
+ cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U;
+ dpll_prog(1, 49, 63, 625, 3, 3, 2);
+ for (int tp = 0; tp < 20; tp++)
+ regval = Xil_In32(0xFD070018);
+ unsigned int pll_retry = 10;
+ unsigned int pll_locked = 0;
+
+ while ((pll_retry > 0) && (!pll_locked)) {
+ Xil_Out32(0xFD080004, 0x00040010);
+ Xil_Out32(0xFD080004, 0x00040011);
+
+ while ((Xil_In32(0xFD080030) & 0x1) != 1)
+ ;
+ pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+ >> 31;
+ pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+ >> 16;
+ pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+ pll_retry--;
+ }
+ Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+ if (!pll_locked)
+ return 0;
+
+ Xil_Out32(0xFD080004U, 0x00040063U);
+ Xil_Out32(0xFD0800C0U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ Xil_Out32(0xFD070010U, 0x80000018U);
+ Xil_Out32(0xFD0701B0U, 0x00000005U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00000331U);
+ Xil_Out32(0xFD070010U, 0x80000018U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00000B36U);
+ Xil_Out32(0xFD070010U, 0x80000018U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00000C56U);
+ Xil_Out32(0xFD070010U, 0x80000018U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00000E19U);
+ Xil_Out32(0xFD070010U, 0x80000018U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00001616U);
+ Xil_Out32(0xFD070010U, 0x80000018U);
+ Xil_Out32(0xFD070010U, 0x80000010U);
+ Xil_Out32(0xFD0701B0U, 0x00000005U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+ prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
+ prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U);
+ prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
+ prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
+ prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U);
+ prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
+ for (int tp = 0; tp < 20; tp++)
+ regval = Xil_In32(0xFD070018);
+
+ Xil_Out32(0xFD080068, cur_PLLCR0);
+ Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0);
+ Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0);
+ Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0);
+ Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0);
+ Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0);
+ Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0);
+ for (int tp = 0; tp < 20; tp++)
+ regval = Xil_In32(0xFD070018);
+
+ dpll_prog(cur_div2, cur_fbdiv, 63, 625, 3, 3, 2);
+ for (int tp = 0; tp < 2000; tp++)
+ regval = Xil_In32(0xFD070018);
+
+ prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U);
+ prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U);
+ prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U);
+ prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U);
+ prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U);
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ for (int tp = 0; tp < 2000; tp++)
+ regval = Xil_In32(0xFD070018);
+
+ prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U);
+ prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
+ prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
+ prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U);
+ prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
+ for (int tp = 0; tp < 2000; tp++)
+ regval = Xil_In32(0xFD070018);
+
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0014FE01);
+
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x8000007E)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD080200U, 0x000091C7U);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80008FFF)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+ if (regval != 0)
+ return 0;
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ int cur_R006_tREFPRD;
+
+ cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+ prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+ Xil_Out32(0xFD080004, 0x00060001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80004001) != 0x80004001)
+ regval = Xil_In32(0xFD080030);
+
+ regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+ if (regval != 0)
+ return 0;
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+ Xil_Out32(0xFD080004, 0x0000C001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80000C01) != 0x80000C01)
+ regval = Xil_In32(0xFD080030);
+
+ prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U);
+ prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U);
+ prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U);
+ prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U);
+ Xil_Out32(0xFD070180U, 0x020D0010U);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+ for (int tp = 0; tp < 4000; tp++)
+ regval = Xil_In32(0xFD070018);
+
+ prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U);
+ prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U);
+ prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U);
+ prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U);
+ prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U);
+ prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U);
+ prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U);
+ prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U);
+ prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U);
+ prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U);
+ prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U);
+ prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U);
+ prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U);
+ prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU);
+ prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ return 1;
+}
+
+static void init_peripheral(void)
+{
+ psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_peripherals_pre_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+ init_peripheral();
+
+ status &= psu_afi_config();
+ psu_ddr_qos_init_data();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
diff --git a/board/xilinx/zynqmp/zynqmp-smk-k24-revA b/board/xilinx/zynqmp/zynqmp-smk-k24-revA
new file mode 120000
index 0000000..89e45cd
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-smk-k24-revA
@@ -0,0 +1 @@
+zynqmp-sm-k24-revA
\ No newline at end of file
diff --git a/common/bouncebuf.c b/common/bouncebuf.c
index 6d98920..93a3566 100644
--- a/common/bouncebuf.c
+++ b/common/bouncebuf.c
@@ -12,6 +12,7 @@
#include <errno.h>
#include <bouncebuf.h>
#include <asm/cache.h>
+#include <linux/dma-mapping.h>
static int addr_aligned(struct bounce_buffer *state)
{
@@ -59,9 +60,9 @@
* Flush data to RAM so DMA reads can pick it up,
* and any CPU writebacks don't race with DMA writes
*/
- flush_dcache_range((unsigned long)state->bounce_buffer,
- (unsigned long)(state->bounce_buffer) +
- state->len_aligned);
+ dma_map_single(state->bounce_buffer,
+ state->len_aligned,
+ DMA_BIDIRECTIONAL);
return 0;
}
@@ -78,9 +79,9 @@
{
if (state->flags & GEN_BB_WRITE) {
/* Invalidate cache so that CPU can see any newly DMA'd data */
- invalidate_dcache_range((unsigned long)state->bounce_buffer,
- (unsigned long)(state->bounce_buffer) +
- state->len_aligned);
+ dma_unmap_single((dma_addr_t)state->bounce_buffer,
+ state->len_aligned,
+ DMA_BIDIRECTIONAL);
}
if (state->bounce_buffer == state->user_buffer)
diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig
index aa85766..8f8a603 100644
--- a/configs/arbel_evb_defconfig
+++ b/configs/arbel_evb_defconfig
@@ -38,6 +38,7 @@
CONFIG_CLK=y
CONFIG_NPCM_GPIO=y
CONFIG_DM_I2C=y
+CONFIG_NPCM_I2C=y
# CONFIG_INPUT is not set
CONFIG_NPCM_HOST=y
CONFIG_MMC_SDHCI=y
@@ -46,7 +47,6 @@
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_BROADCOM=y
-CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
@@ -75,3 +75,20 @@
CONFIG_USB_OHCI_NPCM=y
CONFIG_USB_STORAGE=y
# CONFIG_EFI_LOADER is not set
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_DM_ETH=y
+CONFIG_MISC=y
+CONFIG_SHA_HW_ACCEL=y
+CONFIG_NPCM_SHA=y
+CONFIG_RNG_NPCM=y
+CONFIG_LIB_HW_RAND=y
+CONFIG_DM_RNG=y
+# CONFIG_AES is not set
+CONFIG_CMD_RNG=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_HASH=y
+CONFIG_NPCM_AES=y
+CONFIG_NPCM_OTP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_NPCM8XX=y
diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
deleted file mode 100644
index 0a3d710..0000000
--- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
+++ /dev/null
@@ -1,83 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_LEN=0x4008000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0"
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-CONFIG_SYS_LOAD_ADDR=0x8000000
-CONFIG_DEBUG_UART=y
-CONFIG_SYS_MEMTEST_START=0x00000000
-CONFIG_SYS_MEMTEST_END=0x00001000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8000000
-CONFIG_REMAKE_ELF=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
-CONFIG_BOOTDELAY=0
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_CLOCKS=y
-CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_BSS_MAX_SIZE=0x80000
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK=0xfffffffc
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20000000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
-CONFIG_SPL_FS_LOAD_KERNEL_NAME="atf-uboot.ub"
-CONFIG_SPL_FS_LOAD_ARGS_NAME="u-boot.bin"
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x8000000
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2073
-CONFIG_SYS_BOOTM_LEN=0x6400000
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_BOOTP_MAY_FAIL=y
-CONFIG_BOOTP_BOOTFILESIZE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_ZYNQ_GEM=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ARM_DCC=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_PANIC_HANG=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 99a0eee..84b4fb0 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -89,9 +89,11 @@
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_OF_LIST="k3-j721s2-common-proc-board k3-am68-sk-base-board"
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index cd25016..1f2102a 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -84,7 +84,11 @@
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_OF_LIST="k3-j721s2-r5-common-proc-board k3-am68-sk-r5-base-board"
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_OVERWRITE=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index be34941..438540f 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -33,9 +33,6 @@
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK=0x100000
CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x2a000000
-CONFIG_SYS_OS_BASE=0x2c060000
CONFIG_SYS_MAXARGS=15
CONFIG_SYS_CBSIZE=512
CONFIG_SYS_PBSIZE=544
diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig
index 3c5ab01..463aee4 100644
--- a/configs/xilinx_versal_mini_defconfig
+++ b/configs/xilinx_versal_mini_defconfig
@@ -1,5 +1,5 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini_qspi"
+CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini"
CONFIG_SYS_ICACHE_OFF=y
CONFIG_COUNTER_FREQUENCY=100000000
CONFIG_ARCH_VERSAL=y
diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig
index abcd20b..f9fdf61 100644
--- a/configs/xilinx_versal_mini_ospi_defconfig
+++ b/configs/xilinx_versal_mini_ospi_defconfig
@@ -1,5 +1,5 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini_qspi"
+CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini"
CONFIG_COUNTER_FREQUENCY=100000000
CONFIG_ARCH_VERSAL=y
CONFIG_TEXT_BASE=0xFFFC0000
diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig
index 9ca9b7e..9fc3eb6 100644
--- a/configs/xilinx_versal_mini_qspi_defconfig
+++ b/configs/xilinx_versal_mini_qspi_defconfig
@@ -1,5 +1,5 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini_qspi"
+CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini"
CONFIG_COUNTER_FREQUENCY=100000000
CONFIG_ARCH_VERSAL=y
CONFIG_TEXT_BASE=0xFFFC0000
@@ -62,6 +62,7 @@
CONFIG_SF_DEFAULT_SPEED=30000000
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
+CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig
index c5fa431..0ff5268 100644
--- a/configs/xilinx_versal_net_mini_defconfig
+++ b/configs/xilinx_versal_net_mini_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_CONFIG_NAME="xilinx_versal_net_mini"
CONFIG_SYS_ICACHE_OFF=y
# CONFIG_ARM64_CRC32 is not set
+CONFIG_COUNTER_FREQUENCY=100000000
# CONFIG_ARM64_SUPPORT_AARCH32 is not set
CONFIG_ARCH_VERSAL_NET=y
CONFIG_TEXT_BASE=0xBBF10000
@@ -19,6 +20,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF10000
# CONFIG_EXPERT is not set
+CONFIG_REMAKE_ELF=y
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
# CONFIG_AUTOBOOT is not set
diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig
index 2fdf99f..729c6ad 100644
--- a/configs/xilinx_versal_net_virt_defconfig
+++ b/configs/xilinx_versal_net_virt_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=100000000
CONFIG_POSITION_INDEPENDENT=y
CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864
CONFIG_ARCH_VERSAL_NET=y
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index 610d9de..0ae771d 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -119,6 +119,7 @@
CONFIG_NAND_ZYNQ=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_SPEED=30000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig
index d8b3aab..9680d9b 100644
--- a/configs/xilinx_zynqmp_mini_defconfig
+++ b/configs/xilinx_zynqmp_mini_defconfig
@@ -1,5 +1,5 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_qspi"
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini"
CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_TEXT_BASE=0xFFFC0000
diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig
index a1ee98d..93aaa93 100644
--- a/configs/xilinx_zynqmp_mini_emmc0_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig
@@ -1,5 +1,5 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini"
CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_TEXT_BASE=0x10000
diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig
index 88c95d4..81ea67a 100644
--- a/configs/xilinx_zynqmp_mini_emmc1_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig
@@ -1,5 +1,5 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini"
CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_TEXT_BASE=0x10000
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index 6861f73..046cbcf 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -1,5 +1,5 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_qspi"
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini"
CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_TEXT_BASE=0xFFFC0000
@@ -79,6 +79,7 @@
# CONFIG_MMC is not set
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
+CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index ab2a542..c40490a 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -159,6 +159,7 @@
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_MAX_CHIPS=2
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index c623caf..bebbb34 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -82,6 +82,7 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_MMC is not set
CONFIG_SF_DEFAULT_SPEED=30000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/doc/mkimage.1 b/doc/mkimage.1
index 353ea8b..d8727ec 100644
--- a/doc/mkimage.1
+++ b/doc/mkimage.1
@@ -22,7 +22,8 @@
.SY mkimage
.RI [ option\~ .\|.\|.\&]
.BI \-f\~ image-tree-source-file\c
-.RB | auto
+.RB | auto\c
+.RB | auto-conf
.I image-file-name
.YS
.
@@ -296,9 +297,9 @@
for details on using external data.
.
.TP
-\fB\-f \fIimage-tree-source-file\fR | \fBauto
+\fB\-f \fIimage-tree-source-file\fR | \fBauto\fR | \fBauto-conf
.TQ
-\fB\-\-fit \fIimage-tree-source-file\fR | \fBauto
+\fB\-\-fit \fIimage-tree-source-file\fR | \fBauto\fR | \fBauto-conf
Image tree source file that describes the structure and contents of the
FIT image.
.IP
@@ -317,7 +318,25 @@
options may be used to specify the image to include in the FIT and its
attributes. No
.I image-tree-source-file
-is required.
+is required. The
+.BR \-g ,
+.BR \-o ,
+and
+.B \-k
+or
+.B \-G
+options may be used to get \(oqimages\(cq signed subnodes in the generated
+auto FIT. Instead, to get \(oqconfigurations\(cq signed subnodes and
+\(oqimages\(cq hashed subnodes, pass
+.BR "\-f auto-conf".
+In this case
+.BR \-g ,
+.BR \-o ,
+and
+.B \-k
+or
+.B \-G
+are mandatory options.
.
.TP
.B \-F
@@ -348,16 +367,16 @@
necessary when embedding it into another device tree using
.BR \-K .
.I name
-defaults to the value of the signature node's \(oqkey-name-hint\(cq property,
-but may be overridden using
-.BR \-g .
+is the value of the signature node's \(oqkey-name-hint\(cq property.
.
.TP
.BI \-G " key-file"
.TQ
.BI \-\-key\-file " key-file"
Specifies the private key file to use when signing. This option may be used
-instead of \-k.
+instead of \-k. Useful when the private key file basename does not match
+\(oqkey-name-hint\(cq value. But note that it may lead to unexpected results
+when used together with -K and/or -k options.
.
.TP
.BI \-K " key-destination"
@@ -373,49 +392,50 @@
.BI \-g " key-name-hint"
.TQ
.BI \-\-key\-name\-hint " key-name-hint"
-Overrides the signature node's \(oqkey-name-hint\(cq property. This is
-especially useful when signing an image with
-.BR "\-f auto" .
-This is the
-.I name
-part of the key. The directory part is set by
-.BR \-k .
-This option also indicates that the images included in the FIT should be signed.
-If this option is specified, then
+Specifies the value of signature node \(oqkey-name-hint\(cq property for
+an automatically generated FIT image. It makes sense only when used with
+.B "\-f auto"
+or
+.BR "\-f auto-conf".
+This option also indicates that the images or configurations included in
+the FIT should be signed. If this option is specified, then
.B \-o
must be specified as well.
.
.TP
-.BI \-o " crypto" , checksum
+.BI \-o " checksum" , crypto
.TQ
-.BI \-\-algo " crypto" , checksum
-Specifies the algorithm to be used for signing a FIT image. The default is
-taken from the signature node's \(oqalgo\(cq property.
+.BI \-\-algo " checksum" , crypto
+Specifies the algorithm to be used for signing a FIT image, overriding value
+taken from the signature node \(oqalgo\(cq property in the
+.IR image-tree-source-file .
+It is mandatory for automatically generated FIT.
+.IP
The valid values for
-.I crypto
+.I checksum
are:
.RS
.IP
.TS
lb.
-rsa2048
-rsa3072
-rsa4096
-ecdsa256
+sha1
+sha256
+sha384
+sha512
.TE
.RE
.IP
The valid values for
-.I checksum
-are
+.I crypto
+are:
.RS
.IP
.TS
lb.
-sha1
-sha256
-sha384
-sha512
+rsa2048
+rsa3072
+rsa4096
+ecdsa256
.TE
.RE
.
@@ -423,9 +443,13 @@
.B \-r
.TQ
.B \-\-key\-required
-Specifies that keys used to sign the FIT are required. This means that they
-must be verified for the image to boot. Without this option, the verification
-will be optional (useful for testing but not for release).
+Specifies that keys used to sign the FIT are required. This means that images
+or configurations signatures must be verified before using them (i.e. to
+boot). Without this option, the verification will be optional (useful for
+testing but not for release). It makes sense only when used with
+.BR \-K.
+When both, images and configurations, are signed, \(oqrequired\(cq property
+value will be "conf".
.
.TP
.BI \-N " engine"
@@ -716,7 +740,7 @@
.EE
.RE
.P
-Add public keys to u\-boot.dtb without needing a FIT to sign. This will also
+Add public key to u\-boot.dtb without needing a FIT to sign. This will also
create a FIT containing an images node with no data named unused.itb.
.RS
.P
@@ -726,6 +750,16 @@
.EE
.RE
.P
+Add public key with required = "conf" property to u\-boot.dtb without needing
+a FIT to sign. This will also create a useless FIT named unused.itb.
+.RS
+.P
+.EX
+\fBmkimage \-f auto-conf \-d /dev/null \-k /public/signing\-keys \-g dev \\
+ \-o sha256,rsa2048 \-K u\-boot.dtb -r unused.itb
+.EE
+.RE
+.P
Update an existing FIT image, signing it with additional keys.
Add corresponding public keys into u\-boot.dtb. This will resign all images
with keys that are available in the new directory. Images that request signing
@@ -768,6 +802,19 @@
\-d vmlinuz \-k /secret/signing\-keys \-g dev \-o sha256,rsa2048 kernel.itb
.EE
.RE
+.P
+Create a FIT image containing a kernel and some device tree files, signing
+each configuration, using automatic mode. Moreover, the public key needed to
+verify signatures is added to u\-boot.dtb with required = "conf" property.
+.RS
+.P
+.EX
+\fBmkimage \-f auto-conf \-A arm \-O linux \-T kernel \-C none \-a 43e00000 \\
+ \-e 0 \-d vmlinuz \-b /path/to/file\-1.dtb \-b /path/to/file\-2.dtb \\
+ \-k /folder/with/signing\-keys \-g dev \-o sha256,rsa2048 \\
+ \-K u\-boot.dtb -r kernel.itb
+.EE
+.RE
.
.SH SEE ALSO
.BR dtc (1),
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index 76fde00..faebbab 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -657,7 +657,9 @@
if (ret < 0)
return -EINVAL;
- versal_clock_setup();
+ ret = versal_clock_setup();
+ if (ret < 0)
+ return ret;
priv->clk = clock;
diff --git a/drivers/gpio/zynqmp_gpio_modepin.c b/drivers/gpio/zynqmp_gpio_modepin.c
index 078fd83..e9565ff 100644
--- a/drivers/gpio/zynqmp_gpio_modepin.c
+++ b/drivers/gpio/zynqmp_gpio_modepin.c
@@ -48,6 +48,9 @@
int ret;
ret = get_gpio_modepin(ret_payload);
+ if (ret)
+ return ret;
+
if (value)
out_val = OUTVAL(offset) | ret_payload[1];
else
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 7dcf6ad..be4075c 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -249,7 +249,7 @@
u32 ctrl;
struct sdhci_host *host;
struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
- char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
+ int tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
dev_dbg(mmc->dev, "%s\n", __func__);
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index a862fbd..3f8b796 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -118,6 +118,36 @@
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ /* adding these 3V QSPI flash parts */
+ {INFO("gd25b256", 0xc84019, 0, 64 * 1024, 512, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES) },
+ {INFO("gd25b512", 0xc8471A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55b01g", 0xc8471B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55b02g", 0xc8471C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25f64", 0xc84317, 0, 64 * 1024, 128, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+ {INFO("gd25f128", 0xc84318, 0, 64 * 1024, 256, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+ {INFO("gd25f256", 0xc84319, 0, 64 * 1024, 512, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55f512", 0xc8431A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25t512", 0xc8461A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55t01g", 0xc8461B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55t02g", 0xc8461C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ /* adding these 3V OSPI flash parts */
+ {INFO("gd25x512", 0xc8481A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55x01g", 0xc8481B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
{
INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
@@ -128,10 +158,48 @@
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ /* adding these 1.8V QSPI flash parts */
+ {INFO("gd25lb256", 0xc86719, 0, 64 * 1024, 512, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lb512", 0xc8671A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lb01g", 0xc8671B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lb02g", 0xc8671C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lf80", 0xc86314, 0, 64 * 1024, 16, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+ {INFO("gd25lf16", 0xc86315, 0, 64 * 1024, 32, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+ {INFO("gd25lf32", 0xc86316, 0, 64 * 1024, 64, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
+ {INFO("gd25lf64", 0xc86317, 0, 64 * 1024, 128, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
+ {INFO("gd25lf128", 0xc86318, 0, 64 * 1024, 256, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
+ {INFO("gd25lf255", 0xc86319, 0, 64 * 1024, 512, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lf511", 0xc8631A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lt256", 0xc86619, 0, 64 * 1024, 512, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lt512", 0xc8661A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lt01g", 0xc8661B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lt02g", 0xc8661C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
},
+ /* adding these 1.8V OSPI flash parts */
+ {INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lx01g", 0xc8681B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lx02g", 0xc8681C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
#endif
#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
/* ISSI */
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 507b19b..cc49788 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -125,6 +125,10 @@
*/
#define PHY_DETECT_MASK 0x1808
+/* PCS (SGMII) Link Status */
+#define ZYNQ_GEM_PCSSTATUS_LINK BIT(2)
+#define ZYNQ_GEM_PCSSTATUS_ANEG_COMPL BIT(5)
+
/* TX BD status masks */
#define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
@@ -164,7 +168,8 @@
u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
u32 reserved9[20];
u32 pcscntrl;
- u32 rserved12[36];
+ u32 pcsstatus;
+ u32 rserved12[35];
u32 dcfg6; /* 0x294 Design config reg6 */
u32 reserved7[106];
u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
@@ -491,12 +496,37 @@
* Must be written after PCS_SEL is set in nwconfig,
* otherwise writes will not take effect.
*/
- if (priv->phydev->phy_id != PHY_FIXED_ID)
+ if (priv->phydev->phy_id != PHY_FIXED_ID) {
writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
®s->pcscntrl);
- else
+ /*
+ * When the PHY link is already up, the PCS link needs
+ * to get re-checked
+ */
+ if (priv->phydev->link) {
+ u32 pcsstatus;
+
+ pcsstatus = ZYNQ_GEM_PCSSTATUS_LINK |
+ ZYNQ_GEM_PCSSTATUS_ANEG_COMPL;
+ ret = wait_for_bit_le32(®s->pcsstatus,
+ pcsstatus,
+ true, 5000, true);
+ if (ret) {
+ dev_warn(dev,
+ "no PCS (SGMII) link\n");
+ } else {
+ /*
+ * Some additional minimal delay seems
+ * to be needed so that the first
+ * packet will be sent correctly
+ */
+ mdelay(1);
+ }
+ }
+ } else {
writel(readl(®s->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
®s->pcscntrl);
+ }
}
#endif
@@ -821,7 +851,8 @@
if (priv->interface == PHY_INTERFACE_MODE_SGMII && phy.dev) {
if (IS_ENABLED(CONFIG_DM_ETH_PHY)) {
- if (device_is_compatible(dev, "cdns,zynqmp-gem")) {
+ if (device_is_compatible(dev, "cdns,zynqmp-gem") ||
+ device_is_compatible(dev, "xlnx,zynqmp-gem")) {
ret = gem_zynqmp_set_dynamic_config(dev);
if (ret) {
dev_err
@@ -922,8 +953,11 @@
}
static const struct udevice_id zynq_gem_ids[] = {
+ { .compatible = "xlnx,versal-gem", .data = RXCLK_EN },
{ .compatible = "cdns,versal-gem", .data = RXCLK_EN },
+ { .compatible = "xlnx,zynqmp-gem" },
{ .compatible = "cdns,zynqmp-gem" },
+ { .compatible = "xlnx,zynq-gem" },
{ .compatible = "cdns,zynq-gem" },
{ .compatible = "cdns,gem" },
{ }
diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c
index a1b85ca..8837726 100644
--- a/drivers/pinctrl/pinctrl-uclass.c
+++ b/drivers/pinctrl/pinctrl-uclass.c
@@ -20,7 +20,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#if CONFIG_IS_ENABLED(PINCTRL_FULL)
/**
* pinctrl_config_one() - apply pinctrl settings for a single node
*
@@ -71,13 +70,13 @@
*/
state = dectoul(statename, &end);
if (*end)
- return -EINVAL;
+ return -ENOSYS;
}
snprintf(propname, sizeof(propname), "pinctrl-%d", state);
list = dev_read_prop(dev, propname, &size);
if (!list)
- return -EINVAL;
+ return -ENOSYS;
size /= sizeof(*list);
for (i = 0; i < size; i++) {
@@ -148,6 +147,7 @@
return 0;
}
+#if CONFIG_IS_ENABLED(PINCTRL_FULL)
UCLASS_DRIVER(pinconfig) = {
.id = UCLASS_PINCONFIG,
#if CONFIG_IS_ENABLED(PINCONF_RECURSIVE)
@@ -160,17 +160,6 @@
.name = "pinconfig",
.id = UCLASS_PINCONFIG,
};
-
-#else
-static int pinctrl_select_state_full(struct udevice *dev, const char *statename)
-{
- return -ENODEV;
-}
-
-static int pinconfig_post_bind(struct udevice *dev)
-{
- return 0;
-}
#endif
static int
@@ -317,10 +306,10 @@
* Try full-implemented pinctrl first.
* If it fails or is not implemented, try simple one.
*/
- if (pinctrl_select_state_full(dev, statename))
- return pinctrl_select_state_simple(dev);
+ if (CONFIG_IS_ENABLED(PINCTRL_FULL))
+ return pinctrl_select_state_full(dev, statename);
- return 0;
+ return pinctrl_select_state_simple(dev);
}
int pinctrl_request(struct udevice *dev, int func, int flags)
@@ -393,7 +382,7 @@
}
/**
- * pinconfig_post_bind() - post binding for PINCTRL uclass
+ * pinctrl_post_bind() - post binding for PINCTRL uclass
* Recursively bind child nodes as pinconfig devices in case of full pinctrl.
*
* @dev: pinctrl device
@@ -409,12 +398,11 @@
}
/*
- * If set_state callback is set, we assume this pinctrl driver is the
- * full implementation. In this case, its child nodes should be bound
- * so that peripheral devices can easily search in parent devices
- * during later DT-parsing.
+ * If the pinctrl driver has the full implementation, its child nodes
+ * should be bound so that peripheral devices can easily search in
+ * parent devices during later DT-parsing.
*/
- if (ops->set_state)
+ if (CONFIG_IS_ENABLED(PINCTRL_FULL))
return pinconfig_post_bind(dev);
return 0;
diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c
index a51bcdb..afa277f 100644
--- a/drivers/soc/soc_xilinx_zynqmp.c
+++ b/drivers/soc/soc_xilinx_zynqmp.c
@@ -186,7 +186,7 @@
.variants = ZYNQMP_VARIANT_DR,
},
{
- .id = 0x04714093,
+ .id = 0x04712093,
.device = 24,
.variants = 0,
},
diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h
index 54dfea6..bfada9e 100644
--- a/include/configs/j721s2_evm.h
+++ b/include/configs/j721s2_evm.h
@@ -32,6 +32,10 @@
"default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"findfdt=" \
"setenv name_fdt ${default_device_tree};" \
+ "if test $board_name = j721s2; then " \
+ "setenv name_fdt k3-j721s2-common-proc-board.dtb; fi;" \
+ "if test $board_name = am68-sk; then " \
+ "setenv name_fdt k3-am68-sk-base-board.dtb; fi;"\
"setenv fdtfile ${name_fdt}\0" \
"name_kern=Image\0" \
"console=ttyS2,115200n8\0" \
diff --git a/include/configs/xilinx_versal_mini_qspi.h b/include/configs/xilinx_versal_mini_qspi.h
deleted file mode 100644
index e2f2df2..0000000
--- a/include/configs/xilinx_versal_mini_qspi.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Configuration for Xilinx Versal QSPI Flash utility
- *
- * (C) Copyright 2018-2019 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
- */
-
-#ifndef __CONFIG_VERSAL_MINI_QSPI_H
-#define __CONFIG_VERSAL_MINI_QSPI_H
-
-#include <configs/xilinx_versal_mini.h>
-
-#endif /* __CONFIG_VERSAL_MINI_QSPI_H */
diff --git a/include/configs/xilinx_zynqmp_mini_emmc.h b/include/configs/xilinx_zynqmp_mini_emmc.h
deleted file mode 100644
index f423ddd..0000000
--- a/include/configs/xilinx_zynqmp_mini_emmc.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for Xilinx ZynqMP eMMC Flash utility
- *
- * (C) Copyright 2018 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
- */
-
-#ifndef __CONFIG_ZYNQMP_MINI_EMMC_H
-#define __CONFIG_ZYNQMP_MINI_EMMC_H
-
-#include <configs/xilinx_zynqmp_mini.h>
-
-#endif /* __CONFIG_ZYNQMP_MINI_EMMC_H */
diff --git a/include/configs/xilinx_zynqmp_mini_qspi.h b/include/configs/xilinx_zynqmp_mini_qspi.h
deleted file mode 100644
index 5bea1c9..0000000
--- a/include/configs/xilinx_zynqmp_mini_qspi.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for Xilinx ZynqMP QSPI Flash utility
- *
- * (C) Copyright 2018 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
- */
-
-#ifndef __CONFIG_ZYNQMP_MINI_QSPI_H
-#define __CONFIG_ZYNQMP_MINI_QSPI_H
-
-#include <configs/xilinx_zynqmp_mini.h>
-
-#endif /* __CONFIG_ZYNQMP_MINI_QSPI_H */
diff --git a/test/py/tests/test_fit_auto_signed.py b/test/py/tests/test_fit_auto_signed.py
new file mode 100644
index 0000000..9ea3351
--- /dev/null
+++ b/test/py/tests/test_fit_auto_signed.py
@@ -0,0 +1,195 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2022 Massimo Pegorer
+
+"""
+Test that mkimage generates auto-FIT with signatures and/or hashes as expected.
+
+The mkimage tool can create auto generated (i.e. without an ITS file
+provided as input) FIT in three different flavours: with crc32 checksums
+of 'images' subnodes; with signatures of 'images' subnodes; with sha1
+hashes of 'images' subnodes and signatures of 'configurations' subnodes.
+This test verifies that auto-FIT are generated as expected, in all of
+the three flavours, including check of hashes and signatures (except for
+configurations ones).
+
+The test does not run the sandbox. It only checks the host tool mkimage.
+"""
+
+import os
+import pytest
+import u_boot_utils as util
+import binascii
+from Cryptodome.Hash import SHA1
+from Cryptodome.Hash import SHA256
+from Cryptodome.PublicKey import RSA
+from Cryptodome.Signature import pkcs1_15
+
+class SignedFitHelper(object):
+ """Helper to manipulate a FIT with signed/hashed images/configs."""
+ def __init__(self, cons, file_name):
+ self.fit = file_name
+ self.cons = cons
+ self.images_nodes = set()
+ self.confgs_nodes = set()
+
+ def __fdt_list(self, path):
+ return util.run_and_log(self.cons,
+ f'fdtget -l {self.fit} {path}')
+
+ def __fdt_get_string(self, node, prop):
+ return util.run_and_log(self.cons,
+ f'fdtget -ts {self.fit} {node} {prop}')
+
+ def __fdt_get_binary(self, node, prop):
+ numbers = util.run_and_log(self.cons,
+ f'fdtget -tbi {self.fit} {node} {prop}')
+
+ bignum = bytearray()
+ for little_num in numbers.split():
+ bignum.append(int(little_num))
+
+ return bignum
+
+ def build_nodes_sets(self):
+ """Fill sets with FIT images and configurations subnodes."""
+ for node in self.__fdt_list('/images').split():
+ subnode = f'/images/{node}'
+ self.images_nodes.add(subnode)
+
+ for node in self.__fdt_list('/configurations').split():
+ subnode = f'/configurations/{node}'
+ self.confgs_nodes.add(subnode)
+
+ return len(self.images_nodes) + len(self.confgs_nodes)
+
+ def check_fit_crc32_images(self):
+ """Test that all images in the set are hashed as expected.
+
+ Each image must have an hash with algo=crc32 and hash value must match
+ the one calculated over image data.
+ """
+ for node in self.images_nodes:
+ algo = self.__fdt_get_string(f'{node}/hash', 'algo')
+ assert algo == "crc32\n", "Missing expected crc32 image hash!"
+
+ raw_crc32 = self.__fdt_get_binary(f'{node}/hash', 'value')
+ raw_bin = self.__fdt_get_binary(node, 'data')
+ assert raw_crc32 == (binascii.crc32(raw_bin) &
+ 0xffffffff).to_bytes(4, 'big'), "Wrong crc32 hash!"
+
+ def check_fit_signed_images(self, key_name, sign_algo, verifier):
+ """Test that all images in the set are signed as expected.
+
+ Each image must have a signature with: key-name-hint matching key_name
+ argument; algo matching sign_algo argument; value matching the one
+ calculated over image data using verifier argument.
+ """
+ for node in self.images_nodes:
+ hint = self.__fdt_get_string(f'{node}/signature', 'key-name-hint')
+ assert hint == key_name + "\n", "Missing expected key name hint!"
+ algo = self.__fdt_get_string(f'{node}/signature', 'algo')
+ assert algo == sign_algo + "\n", "Missing expected signature algo!"
+
+ raw_sig = self.__fdt_get_binary(f'{node}/signature', 'value')
+ raw_bin = self.__fdt_get_binary(node, 'data')
+ verifier.verify(SHA256.new(raw_bin), bytes(raw_sig))
+
+ def check_fit_signed_confgs(self, key_name, sign_algo):
+ """Test that all configs are signed, and images hashed, as expected.
+
+ Each image must have an hash with algo=sha1 and hash value must match
+ the one calculated over image data. Each configuration must have a
+ signature with key-name-hint matching key_name argument and algo
+ matching sign_algo argument.
+ TODO: configurations signature checking.
+ """
+ for node in self.images_nodes:
+ algo = self.__fdt_get_string(f'{node}/hash', 'algo')
+ assert algo == "sha1\n", "Missing expected sha1 image hash!"
+
+ raw_hash = self.__fdt_get_binary(f'{node}/hash', 'value')
+ raw_bin = self.__fdt_get_binary(node, 'data')
+ assert raw_hash == SHA1.new(raw_bin).digest(), "Wrong sha1 hash!"
+
+ for node in self.confgs_nodes:
+ hint = self.__fdt_get_string(f'{node}/signature', 'key-name-hint')
+ assert hint == key_name + "\n", "Missing expected key name hint!"
+ algo = self.__fdt_get_string(f'{node}/signature', 'algo')
+ assert algo == sign_algo + "\n", "Missing expected signature algo!"
+
+
+@pytest.mark.buildconfigspec('fit_signature')
+@pytest.mark.requiredtool('fdtget')
+def test_fit_auto_signed(u_boot_console):
+ """Test that mkimage generates auto-FIT with signatures/hashes as expected.
+
+ The mkimage tool can create auto generated (i.e. without an ITS file
+ provided as input) FIT in three different flavours: with crc32 checksums
+ of 'images' subnodes; with signatures of 'images' subnodes; with sha1
+ hashes of 'images' subnodes and signatures of 'configurations' subnodes.
+ This test verifies that auto-FIT are generated as expected, in all of
+ the three flavours, including check of hashes and signatures (except for
+ configurations ones).
+
+ The test does not run the sandbox. It only checks the host tool mkimage.
+ """
+ cons = u_boot_console
+ mkimage = cons.config.build_dir + '/tools/mkimage'
+ tempdir = os.path.join(cons.config.result_dir, 'auto_fit')
+ os.makedirs(tempdir, exist_ok=True)
+ kernel_file = f'{tempdir}/vmlinuz'
+ dt1_file = f'{tempdir}/dt-1.dtb'
+ dt2_file = f'{tempdir}/dt-2.dtb'
+ key_name = 'sign-key'
+ sign_algo = 'sha256,rsa4096'
+ key_file = f'{tempdir}/{key_name}.key'
+ fit_file = f'{tempdir}/test.fit'
+
+ # Create a fake kernel image and two dtb files with random data
+ with open(kernel_file, 'wb') as fd:
+ fd.write(os.urandom(512))
+
+ with open(dt1_file, 'wb') as fd:
+ fd.write(os.urandom(256))
+
+ with open(dt2_file, 'wb') as fd:
+ fd.write(os.urandom(256))
+
+ # Create 4096 RSA key and write to file to be read by mkimage
+ key = RSA.generate(bits=4096)
+ verifier = pkcs1_15.new(key)
+
+ with open(key_file, 'w') as fd:
+ fd.write(str(key.export_key(format='PEM').decode('ascii')))
+
+ b_args = " -d" + kernel_file + " -b" + dt1_file + " -b" + dt2_file
+ s_args = " -k" + tempdir + " -g" + key_name + " -o" + sign_algo
+
+ # 1 - Create auto FIT with images crc32 checksum, and verify it
+ util.run_and_log(cons, mkimage + ' -fauto' + b_args + " " + fit_file)
+
+ fit = SignedFitHelper(cons, fit_file)
+ if fit.build_nodes_sets() == 0:
+ raise ValueError('FIT-1 has no "/image" nor "/configuration" nodes')
+
+ fit.check_fit_crc32_images()
+
+ # 2 - Create auto FIT with signed images, and verify it
+ util.run_and_log(cons, mkimage + ' -fauto' + b_args + s_args + " " +
+ fit_file)
+
+ fit = SignedFitHelper(cons, fit_file)
+ if fit.build_nodes_sets() == 0:
+ raise ValueError('FIT-2 has no "/image" nor "/configuration" nodes')
+
+ fit.check_fit_signed_images(key_name, sign_algo, verifier)
+
+ # 3 - Create auto FIT with signed configs and hashed images, and verify it
+ util.run_and_log(cons, mkimage + ' -fauto-conf' + b_args + s_args + " " +
+ fit_file)
+
+ fit = SignedFitHelper(cons, fit_file)
+ if fit.build_nodes_sets() == 0:
+ raise ValueError('FIT-3 has no "/image" nor "/configuration" nodes')
+
+ fit.check_fit_signed_confgs(key_name, sign_algo)
diff --git a/tools/fit_image.c b/tools/fit_image.c
index 8a18b1b..8763a36 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -201,36 +201,59 @@
}
/**
- * add_hash_node() - Add a hash or signature node
+ * fit_add_hash_or_sign() - Add a hash or signature node
*
* @params: Image parameters
* @fdt: Device tree to add to (in sequential-write mode)
+ * @is_images_subnode: true to add hash even if key name hint is provided
*
- * If there is a key name hint, try to sign the images. Otherwise, just add a
- * CRC.
- *
- * Return: 0 on success, or -1 on failure
+ * If do_add_hash is false (default) and there is a key name hint, try to add
+ * a sign node to parent. Otherwise, just add a CRC. Rationale: if conf have
+ * to be signed, image/dt have to be hashed even if there is a key name hint.
*/
-static int add_hash_node(struct image_tool_params *params, void *fdt)
+static void fit_add_hash_or_sign(struct image_tool_params *params, void *fdt,
+ bool is_images_subnode)
{
- if (params->keyname) {
- if (!params->algo_name) {
- fprintf(stderr,
- "%s: Algorithm name must be specified\n",
- params->cmdname);
- return -1;
+ const char *hash_algo = "crc32";
+ bool do_hash = false;
+ bool do_sign = false;
+
+ switch (params->auto_fit) {
+ case AF_OFF:
+ break;
+ case AF_HASHED_IMG:
+ do_hash = is_images_subnode;
+ break;
+ case AF_SIGNED_IMG:
+ do_sign = is_images_subnode;
+ break;
+ case AF_SIGNED_CONF:
+ if (is_images_subnode) {
+ do_hash = true;
+ hash_algo = "sha1";
+ } else {
+ do_sign = true;
}
+ break;
+ default:
+ fprintf(stderr,
+ "%s: Unsupported auto FIT mode %u\n",
+ params->cmdname, params->auto_fit);
+ break;
+ }
+
+ if (do_hash) {
+ fdt_begin_node(fdt, FIT_HASH_NODENAME);
+ fdt_property_string(fdt, FIT_ALGO_PROP, hash_algo);
+ fdt_end_node(fdt);
+ }
- fdt_begin_node(fdt, "signature-1");
+ if (do_sign) {
+ fdt_begin_node(fdt, FIT_SIG_NODENAME);
fdt_property_string(fdt, FIT_ALGO_PROP, params->algo_name);
fdt_property_string(fdt, FIT_KEY_HINT, params->keyname);
- } else {
- fdt_begin_node(fdt, "hash-1");
- fdt_property_string(fdt, FIT_ALGO_PROP, "crc32");
+ fdt_end_node(fdt);
}
-
- fdt_end_node(fdt);
- return 0;
}
/**
@@ -271,9 +294,7 @@
ret = fdt_property_file(params, fdt, FIT_DATA_PROP, params->datafile);
if (ret)
return ret;
- ret = add_hash_node(params, fdt);
- if (ret)
- return ret;
+ fit_add_hash_or_sign(params, fdt, true);
fdt_end_node(fdt);
/* Now the device tree files if available */
@@ -296,7 +317,7 @@
genimg_get_arch_short_name(params->arch));
fdt_property_string(fdt, FIT_COMP_PROP,
genimg_get_comp_short_name(IH_COMP_NONE));
- ret = add_hash_node(params, fdt);
+ fit_add_hash_or_sign(params, fdt, true);
if (ret)
return ret;
fdt_end_node(fdt);
@@ -316,7 +337,7 @@
params->fit_ramdisk);
if (ret)
return ret;
- ret = add_hash_node(params, fdt);
+ fit_add_hash_or_sign(params, fdt, true);
if (ret)
return ret;
fdt_end_node(fdt);
@@ -368,6 +389,7 @@
snprintf(str, sizeof(str), FIT_FDT_PROP "-%d", upto);
fdt_property_string(fdt, FIT_FDT_PROP, str);
+ fit_add_hash_or_sign(params, fdt, false);
fdt_end_node(fdt);
}
@@ -380,6 +402,7 @@
if (params->fit_ramdisk)
fdt_property_string(fdt, FIT_RAMDISK_PROP,
FIT_RAMDISK_PROP "-1");
+ fit_add_hash_or_sign(params, fdt, false);
fdt_end_node(fdt);
}
@@ -723,7 +746,7 @@
sprintf (tmpfile, "%s%s", params->imagefile, MKIMAGE_TMPFILE_SUFFIX);
/* We either compile the source file, or use the existing FIT image */
- if (params->auto_its) {
+ if (params->auto_fit) {
if (fit_build(params, tmpfile)) {
fprintf(stderr, "%s: failed to build FIT\n",
params->cmdname);
@@ -907,7 +930,7 @@
static int fit_check_params(struct image_tool_params *params)
{
- if (params->auto_its)
+ if (params->auto_fit)
return 0;
return ((params->dflag && params->fflag) ||
(params->fflag && params->lflag) ||
diff --git a/tools/ifwitool.c b/tools/ifwitool.c
index 3159186..c1defe5 100644
--- a/tools/ifwitool.c
+++ b/tools/ifwitool.c
@@ -721,7 +721,7 @@
*/
static size_t fix_member(void *data, size_t offset, size_t size_bytes)
{
- uint8_t *src = (uint8_t *)data + offset;
+ void *src = (uint8_t *)data + offset;
switch (size_bytes) {
case 1:
@@ -1441,20 +1441,20 @@
size_t offset = 0;
- offset = fix_member(&s, offset, sizeof(h->signature));
- offset = fix_member(&s, offset, sizeof(h->descriptor_count));
- offset = fix_member(&s, offset, sizeof(h->bpdt_version));
- offset = fix_member(&s, offset, sizeof(h->xor_redundant_block));
- offset = fix_member(&s, offset, sizeof(h->ifwi_version));
- offset = fix_member(&s, offset, sizeof(h->fit_tool_version));
+ offset = fix_member(s, offset, sizeof(h->signature));
+ offset = fix_member(s, offset, sizeof(h->descriptor_count));
+ offset = fix_member(s, offset, sizeof(h->bpdt_version));
+ offset = fix_member(s, offset, sizeof(h->xor_redundant_block));
+ offset = fix_member(s, offset, sizeof(h->ifwi_version));
+ offset = fix_member(s, offset, sizeof(h->fit_tool_version));
uint32_t i;
for (i = 0; i < count; i++) {
- offset = fix_member(&s, offset, sizeof(e[i].type));
- offset = fix_member(&s, offset, sizeof(e[i].flags));
- offset = fix_member(&s, offset, sizeof(e[i].offset));
- offset = fix_member(&s, offset, sizeof(e[i].size));
+ offset = fix_member(s, offset, sizeof(e[i].type));
+ offset = fix_member(s, offset, sizeof(e[i].flags));
+ offset = fix_member(s, offset, sizeof(e[i].offset));
+ offset = fix_member(s, offset, sizeof(e[i].size));
}
}
@@ -1654,21 +1654,21 @@
size_t count = h->num_entries;
size_t offset = 0;
- offset = fix_member(&s, offset, sizeof(h->marker));
- offset = fix_member(&s, offset, sizeof(h->num_entries));
- offset = fix_member(&s, offset, sizeof(h->header_version));
- offset = fix_member(&s, offset, sizeof(h->entry_version));
- offset = fix_member(&s, offset, sizeof(h->header_length));
- offset = fix_member(&s, offset, sizeof(h->checksum));
+ offset = fix_member(s, offset, sizeof(h->marker));
+ offset = fix_member(s, offset, sizeof(h->num_entries));
+ offset = fix_member(s, offset, sizeof(h->header_version));
+ offset = fix_member(s, offset, sizeof(h->entry_version));
+ offset = fix_member(s, offset, sizeof(h->header_length));
+ offset = fix_member(s, offset, sizeof(h->checksum));
offset += sizeof(h->name);
uint32_t i;
for (i = 0; i < count; i++) {
offset += sizeof(e[i].name);
- offset = fix_member(&s, offset, sizeof(e[i].offset));
- offset = fix_member(&s, offset, sizeof(e[i].length));
- offset = fix_member(&s, offset, sizeof(e[i].rsvd));
+ offset = fix_member(s, offset, sizeof(e[i].offset));
+ offset = fix_member(s, offset, sizeof(e[i].length));
+ offset = fix_member(s, offset, sizeof(e[i].rsvd));
}
}
diff --git a/tools/imagetool.h b/tools/imagetool.h
index ca7c2e4..fdceea4 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -39,6 +39,14 @@
const char *fname;
};
+/* FIT auto generation modes */
+enum af_mode {
+ AF_OFF = 0, /* Needs .its or existing FIT to be provided */
+ AF_HASHED_IMG, /* Auto FIT with crc32 hashed images subnodes */
+ AF_SIGNED_IMG, /* Auto FIT with signed images subnodes */
+ AF_SIGNED_CONF, /* Auto FIT with sha1 images and signed configs */
+};
+
/*
* This structure defines all such variables those are initialized by
* mkimage and dumpimage main core and need to be referred by image
@@ -79,7 +87,7 @@
int require_keys; /* 1 to mark signing keys as 'required' */
int file_size; /* Total size of output file */
int orig_file_size; /* Original size for file before padding */
- bool auto_its; /* Automatically create the .its file */
+ enum af_mode auto_fit; /* Automatically create the FIT */
int fit_image_type; /* Image type to put into the FIT */
char *fit_ramdisk; /* Ramdisk file to include */
struct content_info *content_head; /* List of files to include */
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 8306861..af7b0e0 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -104,7 +104,7 @@
" -v ==> verbose\n",
params.cmdname);
fprintf(stderr,
- " %s [-D dtc_options] [-f fit-image.its|-f auto|-F] [-b <dtb> [-b <dtb>]] [-E] [-B size] [-i <ramdisk.cpio.gz>] fit-image\n"
+ " %s [-D dtc_options] [-f fit-image.its|-f auto|-f auto-conf|-F] [-b <dtb> [-b <dtb>]] [-E] [-B size] [-i <ramdisk.cpio.gz>] fit-image\n"
" <dtb> file is used with -f auto, it may occur multiple times.\n",
params.cmdname);
fprintf(stderr,
@@ -271,7 +271,10 @@
break;
case 'f':
datafile = optarg;
- params.auto_its = !strcmp(datafile, "auto");
+ if (!strcmp(datafile, "auto"))
+ params.auto_fit = AF_HASHED_IMG;
+ else if (!strcmp(datafile, "auto-conf"))
+ params.auto_fit = AF_SIGNED_CONF;
/* fallthrough */
case 'F':
/*
@@ -283,6 +286,7 @@
break;
case 'g':
params.keyname = optarg;
+ break;
case 'G':
params.keyfile = optarg;
break;
@@ -370,6 +374,15 @@
if (optind < argc)
params.imagefile = argv[optind];
+ if (params.auto_fit == AF_SIGNED_CONF) {
+ if (!params.keyname || !params.algo_name)
+ usage("Missing key/algo for auto-FIT with signed configs (use -g -o)");
+ } else if (params.auto_fit == AF_HASHED_IMG && params.keyname) {
+ params.auto_fit = AF_SIGNED_IMG;
+ if (!params.algo_name)
+ usage("Missing algorithm for auto-FIT with signed images (use -g)");
+ }
+
/*
* For auto-generated FIT images we need to know the image type to put
* in the FIT, which is separate from the file's image type (which
@@ -377,8 +390,8 @@
*/
if (params.type == IH_TYPE_FLATDT) {
params.fit_image_type = type ? type : IH_TYPE_KERNEL;
- /* For auto_its, datafile is always 'auto' */
- if (!params.auto_its)
+ /* For auto-FIT, datafile has to be provided with -d */
+ if (!params.auto_fit)
params.datafile = datafile;
else if (!params.datafile)
usage("Missing data file for auto-FIT (use -d)");