imx8ulp:ddr: saving the dram config timing data into sram
On i.MX8ULP, The dram config timing need to be saved into sram for
ddr retention when APD enter PD mode, so add this support on i.MX8ULP.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
diff --git a/drivers/ddr/imx/imx8ulp/Kconfig b/drivers/ddr/imx/imx8ulp/Kconfig
index e56062a..4284886 100644
--- a/drivers/ddr/imx/imx8ulp/Kconfig
+++ b/drivers/ddr/imx/imx8ulp/Kconfig
@@ -8,4 +8,11 @@
bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK "
depends on IMX8ULP_DRAM
+config SAVED_DRAM_TIMING_BASE
+ hex "Define the base address for saved dram timing"
+ help
+ The DRAM config timing data need to be saved into sram
+ for low power use.
+ default 0x2006c000
+
endmenu