board: starfive: spl: Support jtag for VisionFive2 board
JTAG pins are mapped as below. To access the JTAG pins, we need to
control the GPIO pins from SPL which seems to be the earliest stage for
JTAG.
- JTAG nTRST: GPIO36 / Input
- JTAG TDI: GPIO61 / Input
- JTAG TMS: GPIO63 / Input
- JTAG TCK: GPIO60 / Input
- JTAG TDO: GPIO44 / Output
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index ad5f71a..336f0cd 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <asm/arch/eeprom.h>
+#include <asm/arch/gpio.h>
#include <asm/arch/regs.h>
#include <asm/arch/spl.h>
#include <asm/io.h>
@@ -172,10 +173,32 @@
/* Update the memory size which read form eeprom or DT */
fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size);
}
+
+static void jh7110_jtag_init(void)
+{
+ /* nTRST: GPIO36 */
+ SYS_IOMUX_DOEN(36, HIGH);
+ SYS_IOMUX_DIN(36, 4);
+ /* TDI: GPIO61 */
+ SYS_IOMUX_DOEN(61, HIGH);
+ SYS_IOMUX_DIN(61, 19);
+ /* TMS: GPIO63 */
+ SYS_IOMUX_DOEN(63, HIGH);
+ SYS_IOMUX_DIN(63, 20);
+ /* TCK: GPIO60 */
+ SYS_IOMUX_DOEN(60, HIGH);
+ SYS_IOMUX_DIN(60, 29);
+ /* TDO: GPIO44 */
+ SYS_IOMUX_DOEN(44, 8);
+ SYS_IOMUX_DOUT(44, 22);
+}
+
int spl_board_init_f(void)
{
int ret;
+ jh7110_jtag_init();
+
ret = spl_soc_init();
if (ret) {
debug("JH7110 SPL init failed: %d\n", ret);