x86: Move common PCH code into a common place
The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile
index 1918ca3..74b097a 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -11,4 +11,5 @@
ifndef CONFIG_TARGET_EFI
obj-y += microcode.o
endif
+obj-y += pch.o
obj-$(CONFIG_HAVE_MRC) += report_platform.o
diff --git a/arch/x86/cpu/intel_common/pch.c b/arch/x86/cpu/intel_common/pch.c
new file mode 100644
index 0000000..1f05b44
--- /dev/null
+++ b/arch/x86/cpu/intel_common/pch.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/pch_common.h>
+
+u32 pch_common_sir_read(struct udevice *dev, int idx)
+{
+ u32 data;
+
+ dm_pci_write_config32(dev, SATA_SIRI, idx);
+ dm_pci_read_config32(dev, SATA_SIRD, &data);
+
+ return data;
+}
+
+void pch_common_sir_write(struct udevice *dev, int idx, u32 value)
+{
+ dm_pci_write_config32(dev, SATA_SIRI, idx);
+ dm_pci_write_config32(dev, SATA_SIRD, value);
+}
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index bb720ba..0f93905 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -21,6 +21,7 @@
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/lapic.h>
+#include <asm/lpc_common.h>
#include <asm/microcode.h>
#include <asm/msr.h>
#include <asm/mtrr.h>
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
index da6455b..c3d1057 100644
--- a/arch/x86/cpu/ivybridge/sata.c
+++ b/arch/x86/cpu/ivybridge/sata.c
@@ -9,28 +9,13 @@
#include <dm.h>
#include <fdtdec.h>
#include <asm/io.h>
+#include <asm/pch_common.h>
#include <asm/pci.h>
#include <asm/arch/pch.h>
#include <asm/arch/bd82x6x.h>
DECLARE_GLOBAL_DATA_PTR;
-static inline u32 sir_read(struct udevice *dev, int idx)
-{
- u32 data;
-
- dm_pci_write_config32(dev, SATA_SIRI, idx);
- dm_pci_read_config32(dev, SATA_SIRD, &data);
-
- return data;
-}
-
-static inline void sir_write(struct udevice *dev, int idx, u32 value)
-{
- dm_pci_write_config32(dev, SATA_SIRI, idx);
- dm_pci_write_config32(dev, SATA_SIRD, value);
-}
-
static void common_sata_init(struct udevice *dev, unsigned int port_map)
{
u32 reg32;
@@ -177,27 +162,27 @@
pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);
/* Additional Programming Requirements */
- sir_write(dev, 0x04, 0x00001600);
- sir_write(dev, 0x28, 0xa0000033);
- reg32 = sir_read(dev, 0x54);
+ pch_common_sir_write(dev, 0x04, 0x00001600);
+ pch_common_sir_write(dev, 0x28, 0xa0000033);
+ reg32 = pch_common_sir_read(dev, 0x54);
reg32 &= 0xff000000;
reg32 |= 0x5555aa;
- sir_write(dev, 0x54, reg32);
- sir_write(dev, 0x64, 0xcccc8484);
- reg32 = sir_read(dev, 0x68);
+ pch_common_sir_write(dev, 0x54, reg32);
+ pch_common_sir_write(dev, 0x64, 0xcccc8484);
+ reg32 = pch_common_sir_read(dev, 0x68);
reg32 &= 0xffff0000;
reg32 |= 0xcccc;
- sir_write(dev, 0x68, reg32);
- reg32 = sir_read(dev, 0x78);
+ pch_common_sir_write(dev, 0x68, reg32);
+ reg32 = pch_common_sir_read(dev, 0x78);
reg32 &= 0x0000ffff;
reg32 |= 0x88880000;
- sir_write(dev, 0x78, reg32);
- sir_write(dev, 0x84, 0x001c7000);
- sir_write(dev, 0x88, 0x88338822);
- sir_write(dev, 0xa0, 0x001c7000);
- sir_write(dev, 0xc4, 0x0c0c0c0c);
- sir_write(dev, 0xc8, 0x0c0c0c0c);
- sir_write(dev, 0xd4, 0x10000000);
+ pch_common_sir_write(dev, 0x78, reg32);
+ pch_common_sir_write(dev, 0x84, 0x001c7000);
+ pch_common_sir_write(dev, 0x88, 0x88338822);
+ pch_common_sir_write(dev, 0xa0, 0x001c7000);
+ pch_common_sir_write(dev, 0xc4, 0x0c0c0c0c);
+ pch_common_sir_write(dev, 0xc8, 0x0c0c0c0c);
+ pch_common_sir_write(dev, 0xd4, 0x10000000);
pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000);
pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100);