tree 3d4befb85e4653fc8e6dcc760584b0d08efbd9c3
parent 3673f2c1b270a20384286b7f17d93abd9325dfde
author York Sun <yorksun@freescale.com> 1295480253 -0800
committer Kumar Gala <galak@kernel.crashing.org> 1299341630 -0600

corenet_ds: pick the middle value for all tested timing parameters

For DDR3 controller, the clk_adjust and wrlvl_start are platform-dependent.
The best values should be picked up from the middle of all working
combinations. This patch updates the table with confirmed values tested on
Hynix dual-rank UDIMMs (HMT125U7BFR8C-H9) at 1300MT/s, 1200MT/s, 1000MT/s,
900MT/s, 800MT/s and Kingston quad-rank RDIMMs (KVR1333D3Q8R9S/4G) at 1300MT/s,
1200MT/s, 1000MT/s.

Signed-off-by: York Sun <yorksun@freescale.com>