| commit | 9c43c140bc3a5a46ac3299e337a52d4c41722df2 | [log] [tgz] |
|---|---|---|
| author | Tom Rini <trini@konsulko.com> | Tue Sep 10 07:50:05 2024 -0600 |
| committer | Tom Rini <trini@konsulko.com> | Tue Sep 10 07:50:05 2024 -0600 |
| tree | 84b20693c9f3dd5d5cc831d0b999bd5523523c35 | |
| parent | c95c17bc2dfa23ffb89165d7a03ddfc30ee902e6 [diff] | |
| parent | d46dc184c913d7d92146df8f0fa00df8eb7eb710 [diff] |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/22292 - Add rdcycle to RISC-V exception command - Some fixes and refactoring
diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index e1cd6f8..9b895a6 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi
@@ -111,6 +111,8 @@ #endif #address-cells = <1>; + offset = <0x57c00>; + images { uboot { arch = "arm64";