diff --git a/Makefile b/Makefile
index 94c21cc..86e44d0 100644
--- a/Makefile
+++ b/Makefile
@@ -240,18 +240,10 @@
 LIBS += drivers/serial/libserial.a
 LIBS += drivers/usb/libusb.a
 LIBS += drivers/video/libvideo.a
-LIBS += post/libpost.a post/drivers/libpostdrivers.a
-LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
-	"post/lib_$(ARCH)/libpost$(ARCH).a"; fi)
-LIBS += $(shell if [ -d post/lib_$(ARCH)/fpu ]; then echo \
-	"post/lib_$(ARCH)/fpu/libpost$(ARCH)fpu.a"; fi)
-LIBS += $(shell if [ -d post/cpu/$(CPU) ]; then echo \
-	"post/cpu/$(CPU)/libpost$(CPU).a"; fi)
-LIBS += $(shell if [ -d post/board/$(BOARDDIR) ]; then echo \
-	"post/board/$(BOARDDIR)/libpost$(BOARD).a"; fi)
 LIBS += common/libcommon.a
 LIBS += libfdt/libfdt.a
 LIBS += api/libapi.a
+LIBS += post/libpost.a
 
 LIBS := $(addprefix $(obj),$(LIBS))
 .PHONY : $(LIBS) $(VERSION_FILE)
@@ -2992,7 +2984,7 @@
 		$(obj)cscope.* $(obj)*.*~
 	@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
 	@rm -f $(obj)tools/{crc32.c,environment.c,env/crc32.c,md5.c,sha1.c,inca-swap-bytes}
-	@rm -f $(obj)tools/{image.c,fdt.c,fdt_ro.c,fdt_rw.c,fdt_strerror.c}
+	@rm -f $(obj)tools/{image.c,fdt.c,fdt_ro.c,fdt_rw.c,fdt_strerror.c,zlib.h}
 	@rm -f $(obj)tools/{fdt_wip.c,libfdt_internal.h}
 	@rm -f $(obj)cpu/mpc824x/bedbug_603e.c
 	@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
diff --git a/board/imx31_litekit/imx31_litekit.c b/board/imx31_litekit/imx31_litekit.c
index 5ba60e9..e0fbf25 100644
--- a/board/imx31_litekit/imx31_litekit.c
+++ b/board/imx31_litekit/imx31_litekit.c
@@ -52,7 +52,7 @@
 	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
 	mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
 
-	gd->bd->bi_arch_number = 447;		/* board id for linux */
+	gd->bd->bi_arch_number = MACH_TYPE_MX31LITE; /* board id for linux */
 	gd->bd->bi_boot_params = (0x80000100);	/* adress of boot parameters */
 
 	return 0;
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index e5fa259..b63fbdc 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -476,6 +476,24 @@
 void hw_watchdog_reset(void)
 {
 	int val;
+#if defined(CONFIG_WD_MAX_RATE)
+	unsigned long long ct = get_ticks();
+
+	/*
+	 * Don't allow watch-dog triggering more frequently than
+	 * the predefined value CONFIG_WD_MAX_RATE [ticks].
+	 */
+	if (ct >= gd->wdt_last) {
+		if ((ct - gd->wdt_last) < CONFIG_WD_MAX_RATE)
+			return;
+	} else {
+		/* Time base counter had been reset */
+		if (((unsigned long long)(-1) - gd->wdt_last + ct) <
+		    CONFIG_WD_MAX_RATE)
+			return;
+	}
+	gd->wdt_last = get_ticks();
+#endif
 
 	/*
 	 * Toggle watchdog output
diff --git a/board/mx31ads/mx31ads.c b/board/mx31ads/mx31ads.c
index 5a7d8c9..dd0e150 100644
--- a/board/mx31ads/mx31ads.c
+++ b/board/mx31ads/mx31ads.c
@@ -57,6 +57,18 @@
 	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
 	mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
 
+	/* SPI2 */
+	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2);
+	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SCLK);
+	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SPI_RDY);
+	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MOSI);
+	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MISO);
+	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS0);
+	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS1);
+
+	/* start SPI2 clock */
+	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
+
 	/* PBC setup */
 	/* Enable UART transceivers also reset the Ethernet/external UART */
 	readw(CS4_BASE + 4);
@@ -81,7 +93,7 @@
 	readb(CS4_BASE + 8);
 	readb(CS4_BASE + 7);
 
-	gd->bd->bi_arch_number = 447;		/* board id for linux */
+	gd->bd->bi_arch_number = MACH_TYPE_MX31ADS;	/* board id for linux */
 	gd->bd->bi_boot_params = 0x80000100;	/* adress of boot parameters */
 
 	return 0;
diff --git a/board/siemens/common/fpga.c b/board/siemens/common/fpga.c
index 48c1850..ac0022e 100644
--- a/board/siemens/common/fpga.c
+++ b/board/siemens/common/fpga.c
@@ -160,7 +160,7 @@
     data = (uchar*)image_get_data (hdr);
     len  = image_get_data_size (hdr);
 
-    verify = getenv_verify ();
+    verify = getenv_yesno ("verify");
     if (verify) {
 	if (!image_check_dcrc (hdr)) {
 	    strcpy (msg, "Bad Image Data CRC");
diff --git a/common/cmd_autoscript.c b/common/cmd_autoscript.c
index 1a37b90..932f638 100644
--- a/common/cmd_autoscript.c
+++ b/common/cmd_autoscript.c
@@ -65,7 +65,7 @@
 	size_t		fit_len;
 #endif
 
-	verify = getenv_verify ();
+	verify = getenv_yesno ("verify");
 
 	switch (genimg_get_format ((void *)addr)) {
 	case IMAGE_FORMAT_LEGACY:
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index ae9c21b..44f6b9f 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -132,8 +132,8 @@
 	struct lmb lmb;
 
 	memset ((void *)&images, 0, sizeof (images));
-	images.verify = getenv_verify();
-	images.autostart = getenv_autostart();
+	images.verify = getenv_yesno ("verify");
+	images.autostart = getenv_yesno ("autostart");
 	images.lmb = &lmb;
 
 	lmb_init(&lmb);
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index d6d7a5b..51aa71f 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -35,6 +35,7 @@
 #ifdef CONFIG_HAS_DATAFLASH
 #include <dataflash.h>
 #endif
+#include <watchdog.h>
 
 #if defined(CONFIG_CMD_MEMORY)		\
     || defined(CONFIG_CMD_I2C)		\
@@ -872,6 +873,7 @@
 		    }
 		}
 		start[test_offset] = pattern;
+		WATCHDOG_RESET();
 
 		/*
 		 * Check for addr bits stuck low or shorted.
@@ -909,6 +911,7 @@
 		 * Fill memory with a known pattern.
 		 */
 		for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) {
+			WATCHDOG_RESET();
 			start[offset] = pattern;
 		}
 
@@ -916,6 +919,7 @@
 		 * Check each location and invert it for the second pass.
 		 */
 		for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) {
+		    WATCHDOG_RESET();
 		    temp = start[offset];
 		    if (temp != pattern) {
 			printf ("\nFAILURE (read/write) @ 0x%.8lx:"
@@ -932,6 +936,7 @@
 		 * Check each location for the inverted pattern and zero it.
 		 */
 		for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) {
+		    WATCHDOG_RESET();
 		    anti_pattern = ~pattern;
 		    temp = start[offset];
 		    if (temp != anti_pattern) {
@@ -958,6 +963,7 @@
 			pattern, "");
 
 		for (addr=start,val=pattern; addr<end; addr++) {
+			WATCHDOG_RESET();
 			*addr = val;
 			val  += incr;
 		}
@@ -965,6 +971,7 @@
 		puts ("Reading...");
 
 		for (addr=start,val=pattern; addr<end; addr++) {
+			WATCHDOG_RESET();
 			readback = *addr;
 			if (readback != val) {
 				printf ("\nMem error @ 0x%08X: "
diff --git a/common/cmd_ximg.c b/common/cmd_ximg.c
index 7916fc1..2753389 100644
--- a/common/cmd_ximg.c
+++ b/common/cmd_ximg.c
@@ -51,7 +51,7 @@
 	size_t		fit_len;
 #endif
 
-	verify = getenv_verify ();
+	verify = getenv_yesno ("verify");
 
 	if (argc > 1) {
 		addr = simple_strtoul(argv[1], NULL, 16);
diff --git a/common/image.c b/common/image.c
index d218f2f..4a024d4 100644
--- a/common/image.c
+++ b/common/image.c
@@ -155,7 +155,8 @@
 	{	-1,		"",		"",			},
 };
 
-unsigned long crc32 (unsigned long, const unsigned char *, unsigned int);
+uint32_t crc32 (uint32_t, const unsigned char *, uint);
+uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint);
 static void genimg_print_size (uint32_t size);
 #if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
 static void genimg_print_time (time_t timestamp);
@@ -183,39 +184,11 @@
 {
 	ulong data = image_get_data (hdr);
 	ulong len = image_get_data_size (hdr);
-	ulong dcrc = crc32 (0, (unsigned char *)data, len);
+	ulong dcrc = crc32_wd (0, (unsigned char *)data, len, CHUNKSZ_CRC32);
 
 	return (dcrc == image_get_dcrc (hdr));
 }
 
-#ifndef USE_HOSTCC
-int image_check_dcrc_wd (image_header_t *hdr, ulong chunksz)
-{
-	ulong dcrc = 0;
-	ulong len = image_get_data_size (hdr);
-	ulong data = image_get_data (hdr);
-
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
-	ulong cdata = data;
-	ulong edata = cdata + len;
-
-	while (cdata < edata) {
-		ulong chunk = edata - cdata;
-
-		if (chunk > chunksz)
-			chunk = chunksz;
-		dcrc = crc32 (dcrc, (unsigned char *)cdata, chunk);
-		cdata += chunk;
-
-		WATCHDOG_RESET ();
-	}
-#else
-	dcrc = crc32 (0, (unsigned char *)data, len);
-#endif
-
-	return (dcrc == image_get_dcrc (hdr));
-}
-#endif /* !USE_HOSTCC */
 
 /**
  * image_multi_count - get component (sub-image) count
@@ -316,19 +289,27 @@
 }
 
 /**
- * __image_print_contents - prints out the contents of the legacy format image
+ * image_print_contents - prints out the contents of the legacy format image
  * @hdr: pointer to the legacy format image header
  * @p: pointer to prefix string
  *
- * __image_print_contents() formats a multi line legacy image contents description.
+ * image_print_contents() formats a multi line legacy image contents description.
  * The routine prints out all header fields followed by the size/offset data
  * for MULTI/SCRIPT images.
  *
  * returns:
  *     no returned results
  */
-static void __image_print_contents (image_header_t *hdr, const char *p)
+void image_print_contents (image_header_t *hdr)
 {
+	const char *p;
+
+#ifdef USE_HOSTCC
+	p = "";
+#else
+	p = "   ";
+#endif
+
 	printf ("%sImage Name:   %.*s\n", p, IH_NMLEN, image_get_name (hdr));
 #if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
 	printf ("%sCreated:      ", p);
@@ -366,15 +347,6 @@
 	}
 }
 
-inline void image_print_contents (image_header_t *hdr)
-{
-	__image_print_contents (hdr, "   ");
-}
-
-inline void image_print_contents_noindent (image_header_t *hdr)
-{
-	__image_print_contents (hdr, "");
-}
 
 #ifndef USE_HOSTCC
 /**
@@ -417,7 +389,7 @@
 
 	if (verify) {
 		puts("   Verifying Checksum ... ");
-		if (!image_check_dcrc_wd (rd_hdr, CHUNKSZ)) {
+		if (!image_check_dcrc (rd_hdr)) {
 			puts ("Bad Data CRC\n");
 			show_boot_progress (-12);
 			return NULL;
@@ -444,15 +416,9 @@
 /* Shared dual-format routines */
 /*****************************************************************************/
 #ifndef USE_HOSTCC
-int getenv_verify (void)
-{
-	char *s = getenv ("verify");
-	return (s && (*s == 'n')) ? 0 : 1;
-}
-
-int getenv_autostart (void)
+int getenv_yesno (char *var)
 {
-	char *s = getenv ("autostart");
+	char *s = getenv (var);
 	return (s && (*s == 'n')) ? 0 : 1;
 }
 
@@ -1265,18 +1231,18 @@
 }
 
 /**
- * __fit_print_contents - prints out the contents of the FIT format image
+ * fit_print_contents - prints out the contents of the FIT format image
  * @fit: pointer to the FIT format image header
  * @p: pointer to prefix string
  *
- * __fit_print_contents() formats a multi line FIT image contents description.
+ * fit_print_contents() formats a multi line FIT image contents description.
  * The routine prints out FIT image properties (root node level) follwed by
  * the details of each component image.
  *
  * returns:
  *     no returned results
  */
-static void __fit_print_contents (const void *fit, const char *p)
+void fit_print_contents (const void *fit)
 {
 	char *desc;
 	char *uname;
@@ -1286,10 +1252,17 @@
 	int ndepth;
 	int count = 0;
 	int ret;
+	const char *p;
 #if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
 	time_t timestamp;
 #endif
 
+#ifdef USE_HOSTCC
+	p = "";
+#else
+	p = "   ";
+#endif
+
 	/* Root node properties */
 	ret = fit_get_desc (fit, 0, &desc);
 	printf ("%sFIT description: ", p);
@@ -1361,16 +1334,6 @@
 	}
 }
 
-inline void fit_print_contents (const void *fit)
-{
-	__fit_print_contents (fit, "   ");
-}
-
-inline void fit_print_contents_noindent (const void *fit)
-{
-	__fit_print_contents (fit, "");
-}
-
 /**
  * fit_image_print - prints out the FIT component image details
  * @fit: pointer to the FIT format image header
@@ -1933,15 +1896,16 @@
 			uint8_t *value, int *value_len)
 {
 	if (strcmp (algo, "crc32") == 0 ) {
-		*((uint32_t *)value) = crc32 (0, data, data_len);
+		*((uint32_t *)value) = crc32_wd (0, data, data_len,
+							CHUNKSZ_CRC32);
 		*((uint32_t *)value) = cpu_to_uimage (*((uint32_t *)value));
 		*value_len = 4;
 	} else if (strcmp (algo, "sha1") == 0 ) {
-		sha1_csum ((unsigned char *) data, data_len,
-				(unsigned char *) value);
+		sha1_csum_wd ((unsigned char *) data, data_len,
+				(unsigned char *) value, CHUNKSZ_SHA1);
 		*value_len = 20;
 	} else if (strcmp (algo, "md5") == 0 ) {
-		md5 ((unsigned char *)data, data_len, value);
+		md5_wd ((unsigned char *)data, data_len, value, CHUNKSZ_MD5);
 		*value_len = 16;
 	} else {
 		debug ("Unsupported hash alogrithm\n");
diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c
index 4075f2e..96e43d0 100644
--- a/cpu/arm920t/s3c24x0/usb_ohci.c
+++ b/cpu/arm920t/s3c24x0/usb_ohci.c
@@ -58,8 +58,8 @@
 #define	OHCI_CONTROL_INIT \
 	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
 
-#define readl(a) (*((vu_long *)(a)))
-#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
+#define readl(a) (*((volatile u32 *)(a)))
+#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
 
 #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
 
diff --git a/cpu/arm926ejs/davinci/timer.c b/cpu/arm926ejs/davinci/timer.c
index 8bb8b45..6c670f0 100644
--- a/cpu/arm926ejs/davinci/timer.c
+++ b/cpu/arm926ejs/davinci/timer.c
@@ -42,9 +42,9 @@
 
 typedef volatile struct {
 	u_int32_t	pid12;
-	u_int32_t	emumgt_clksped;
-	u_int32_t	gpint_en;
-	u_int32_t	gpdir_dat;
+	u_int32_t	emumgt;
+	u_int32_t	na1;
+	u_int32_t	na2;
 	u_int32_t	tim12;
 	u_int32_t	tim34;
 	u_int32_t	prd12;
@@ -52,21 +52,12 @@
 	u_int32_t	tcr;
 	u_int32_t	tgcr;
 	u_int32_t	wdtcr;
-	u_int32_t	tlgc;
-	u_int32_t	tlmr;
 } davinci_timer;
 
 davinci_timer		*timer = (davinci_timer *)CFG_TIMERBASE;
 
 #define TIMER_LOAD_VAL	(CFG_HZ_CLOCK / CFG_HZ)
-#define READ_TIMER	timer->tim34
-
-/*
- * Timer runs with CFG_HZ_CLOCK, currently 27MHz. To avoid wrap
- * around of timestamp already after min ~159s, divide it, e.g. by 16.
- * timestamp will then wrap around all min ~42min
- */
-#define DIV(x)		((x) >> 4)
+#define TIM_CLK_DIV	16
 
 static ulong timestamp;
 static ulong lastinc;
@@ -76,63 +67,51 @@
 	/* We are using timer34 in unchained 32-bit mode, full speed */
 	timer->tcr = 0x0;
 	timer->tgcr = 0x0;
-	timer->tgcr = 0x06;
+	timer->tgcr = 0x06 | ((TIM_CLK_DIV - 1) << 8);
 	timer->tim34 = 0x0;
 	timer->prd34 = TIMER_LOAD_VAL;
 	lastinc = 0;
-	timer->tcr = 0x80 << 16;
 	timestamp = 0;
+	timer->tcr = 2 << 22;
 
 	return(0);
 }
 
 void reset_timer(void)
 {
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	return(get_timer_masked() - base);
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
-void udelay(unsigned long usec)
-{
-	udelay_masked(usec);
-}
-
-void reset_timer_masked(void)
-{
-	lastinc = DIV(READ_TIMER);
+	timer->tcr = 0x0;
+	timer->tim34 = 0;
+	lastinc = 0;
 	timestamp = 0;
+	timer->tcr = 2 << 22;
 }
 
-ulong get_timer_raw(void)
+static ulong get_timer_raw(void)
 {
-	ulong now = DIV(READ_TIMER);
+	ulong now = timer->tim34;
 
 	if (now >= lastinc) {
 		/* normal mode */
 		timestamp += now - lastinc;
 	} else {
 		/* overflow ... */
-		timestamp += now + DIV(TIMER_LOAD_VAL) - lastinc;
+		timestamp += now + TIMER_LOAD_VAL - lastinc;
 	}
 	lastinc = now;
 	return timestamp;
 }
 
+ulong get_timer(ulong base)
+{
+	return((get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base);
+}
+
-ulong get_timer_masked(void)
+void set_timer(ulong t)
 {
-	return(get_timer_raw() / DIV(TIMER_LOAD_VAL));
+	timestamp = t;
 }
 
-void udelay_masked(unsigned long usec)
+void udelay(unsigned long usec)
 {
 	ulong tmo;
 	ulong endtime;
@@ -140,7 +119,7 @@
 
 	tmo = CFG_HZ_CLOCK / 1000;
 	tmo *= usec;
-	tmo /= 1000;
+	tmo /= (1000 * TIM_CLK_DIV);
 
 	endtime = get_timer_raw() + tmo;
 
@@ -165,8 +144,5 @@
  */
 ulong get_tbclk(void)
 {
-	ulong tbclk;
-
-	tbclk = CFG_HZ;
-	return(tbclk);
+	return CFG_HZ;
 }
diff --git a/cpu/mpc5xxx/usb_ohci.c b/cpu/mpc5xxx/usb_ohci.c
index c774da3..2ad12b2 100644
--- a/cpu/mpc5xxx/usb_ohci.c
+++ b/cpu/mpc5xxx/usb_ohci.c
@@ -56,8 +56,8 @@
 #define OHCI_CONTROL_INIT \
 	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
 
-#define readl(a) (*((vu_long *)(a)))
-#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
+#define readl(a) (*((volatile u32 *)(a)))
+#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
 
 #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
 
diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S
index fdf9d35..309eb30 100644
--- a/cpu/mpc83xx/start.S
+++ b/cpu/mpc83xx/start.S
@@ -172,11 +172,8 @@
 	/* there and deflate the flash size back to minimal size      */
 	/*------------------------------------------------------------*/
 	bl map_flash_by_law1
-
-	GET_GOT			/* initialize GOT access	*/
-	lwz r4, GOT(_start)
-	addi r4, r4, -EXC_OFF_SYS_RESET
-
+	lis r4, (CFG_MONITOR_BASE)@h
+	ori r4, r4, (CFG_MONITOR_BASE)@l
 	addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
 	mtlr r5
 	blr
@@ -875,8 +872,8 @@
 	mr	r10, r5		/* Save copy of Destination Address */
 
 	mr	r3,  r5				/* Destination Address */
-	lwz	r4, GOT(_start)
-	addi	r4, r4, -EXC_OFF_SYS_RESET
+	lis	r4, CFG_MONITOR_BASE@h		/* Source      Address */
+	ori	r4, r4, CFG_MONITOR_BASE@l
 	lwz	r5, GOT(__init_end)
 	sub	r5, r5, r4
 	li	r6, CFG_CACHELINE_SIZE		/* Cache Line Size */
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index dcd8817..74b210c 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -116,22 +116,21 @@
 	get_sys_info(&sysinfo);
 
 	puts("Clock Configuration:\n");
-	printf("       CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
-	printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
-
+	printf("       CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
+	printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));
 	ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
 	switch (ddr_ratio) {
 	case 0x0:
 		printf("       DDR:%4lu MHz (%lu MT/s data rate), ",
-		sysinfo.freqDDRBus / 2000000, sysinfo.freqDDRBus / 1000000);
+		DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
 		break;
 	case 0x7:
 		printf("       DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
-		sysinfo.freqDDRBus / 2000000, sysinfo.freqDDRBus / 1000000);
+		DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000));
 		break;
 	default:
 		printf("       DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
-		sysinfo.freqDDRBus / 2000000, sysinfo.freqDDRBus / 1000000);
+		DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
 		break;
 	}
 
@@ -154,7 +153,7 @@
 		 clkdiv *= 2;
 #endif
 		printf("LBC:%4lu MHz\n",
-		       sysinfo.freqSystemBus / 1000000 / clkdiv);
+		       DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv);
 	} else {
 		printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
 	}
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index bde6d1e..bb87740 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -52,7 +52,7 @@
 			if (*reg == id) {
 				fdt_setprop_string(blob, off, "status", "okay");
 			} else {
-				u32 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
+				u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
 				val = cpu_to_fdt32(val);
 				fdt_setprop_string(blob, off, "status",
 								"disabled");
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index d90d397..699441b4 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -65,6 +65,9 @@
 int get_clocks (void)
 {
 	sys_info_t sys_info;
+#ifdef CONFIG_MPC8544
+	volatile ccsr_gur_t *gur = (void *) CFG_MPC85xx_GUTS_ADDR;
+#endif
 #if defined(CONFIG_CPM2)
 	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
 	uint sccr, dfbrg;
@@ -78,8 +81,34 @@
 	gd->cpu_clk = sys_info.freqProcessor;
 	gd->bus_clk = sys_info.freqSystemBus;
 	gd->mem_clk = sys_info.freqDDRBus;
+
+	/*
+	 * The base clock for I2C depends on the actual SOC.  Unfortunately,
+	 * there is no pattern that can be used to determine the frequency, so
+	 * the only choice is to look up the actual SOC number and use the value
+	 * for that SOC. This information is taken from application note
+	 * AN2919.
+	 */
+#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+	defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
 	gd->i2c1_clk = sys_info.freqSystemBus;
-	gd->i2c2_clk = sys_info.freqSystemBus;
+#elif defined(CONFIG_MPC8544)
+	/*
+	 * On the 8544, the I2C clock is the same as the SEC clock.  This can be
+	 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
+	 * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
+	 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
+	 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
+	 */
+	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
+		gd->i2c1_clk = sys_info.freqSystemBus / 3;
+	else
+		gd->i2c1_clk = sys_info.freqSystemBus / 2;
+#else
+	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
+	gd->i2c1_clk = sys_info.freqSystemBus / 2;
+#endif
+	gd->i2c2_clk = gd->i2c1_clk;
 
 #if defined(CONFIG_CPM2)
 	gd->vco_out = 2*sys_info.freqSystemBus;
diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c
index c71a6a9..7dbb288 100644
--- a/cpu/ppc4xx/usb_ohci.c
+++ b/cpu/ppc4xx/usb_ohci.c
@@ -56,8 +56,8 @@
 #define OHCI_CONTROL_INIT \
 	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
 
-#define readl(a) (*((vu_long *)(a)))
-#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
+#define readl(a) (*((volatile u32 *)(a)))
+#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
 
 #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
 
diff --git a/doc/README.mips b/doc/README.mips
new file mode 100644
index 0000000..85dea40
--- /dev/null
+++ b/doc/README.mips
@@ -0,0 +1,57 @@
+
+Notes for the MIPS architecture port of U-Boot
+
+Toolchains
+----------
+
+  http://www.denx.de/wiki/DULG/ELDK
+  ELDK < DULG < DENX
+
+  http://www.emdebian.org/crosstools.html
+  Embedded Debian -- Cross-development toolchains
+
+  http://buildroot.uclibc.org/
+  Buildroot
+
+Known Issues
+------------
+
+  * Little endian build problem
+
+    If use non-ELDK toolchains, -EB will be set to CPPFLAGS. Therefore all
+    objects will be generated in big-endian format.
+
+  * Cache incoherency issue caused by do_bootelf_exec() at cmd_elf.c
+
+    Cache will be disabled before entering the loaded ELF image without
+    writing back and invalidating cache lines. This leads to cache
+    incoherency in most cases, unless the code gets loaded after U-Boot
+    re-initializes the cache. The more common uImage 'bootm' command does
+    not suffer this problem.
+
+    [workaround] To avoid this cache incoherency,
+    1) insert flush_cache(all) before calling dcache_disable(), or
+    2) fix dcache_disable() to do both flushing and disabling cache.
+
+  * Note that Linux users need to kill dcache_disable() in do_bootelf_exec()
+    or override do_bootelf_exec() not to disable I-/D-caches, because most
+    Linux/MIPS ports don't re-enable caches after entering kernel_entry.
+
+TODOs
+-----
+
+  * Probe CPU types, I-/D-cache and TLB size etc. automatically
+
+  * Secondary cache support missing
+
+  * Centralize the link directive files
+
+  * Initialize TLB entries redardless of their use
+
+  * R2000/R3000 class parts are not supported
+
+  * Limited testing across different MIPS variants
+
+  * Due to cache initialization issues, the DRAM on board must be
+    initialized in board specific assembler language before the cache init
+    code is run -- that is, initialize the DRAM in lowlevel_init().
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 151f535..2da1d46 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -931,7 +931,7 @@
 			for (i = 0; i < eccbytes; i++, eccidx++)
 				oob_buf[oob_config[eccidx]] = ecc_code[i];
 			/* If the hardware ecc provides syndromes then
-			 * the ecc code must be written immidiately after
+			 * the ecc code must be written immediately after
 			 * the data bytes (words) */
 			if (this->options & NAND_HWECC_SYNDROME)
 				this->write_buf(mtd, ecc_code, eccbytes);
@@ -1299,7 +1299,7 @@
 				for (i = 0, j = 0; j < mtd->oobavail; i++) {
 					int from = oobsel->oobfree[i][0];
 					int num = oobsel->oobfree[i][1];
-					memcpy(&oob_buf[oob], &oob_data[from], num);
+					memcpy(&oob_buf[oob+j], &oob_data[from], num);
 					j+= num;
 				}
 				oob += mtd->oobavail;
@@ -1644,8 +1644,10 @@
 	this->select_chip(mtd, chipnr);
 
 	/* Check, if it is write protected */
-	if (nand_check_wp(mtd))
+	if (nand_check_wp(mtd)) {
+		printk (KERN_NOTICE "nand_write_ecc: Device is write protected\n");
 		goto out;
+	}
 
 	/* if oobsel is NULL, use chip defaults */
 	if (oobsel == NULL)
@@ -2486,12 +2488,9 @@
 
 	/* The number of bytes available for the filesystem to place fs dependend
 	 * oob data */
-	if (this->options & NAND_BUSWIDTH_16) {
-		mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 2);
-		if (this->autooob->eccbytes & 0x01)
-			mtd->oobavail--;
-	} else
-		mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 1);
+	mtd->oobavail = 0;
+	for (i=0; this->autooob->oobfree[i][1]; i++)
+		mtd->oobavail += this->autooob->oobfree[i][1];
 
 	/*
 	 * check ECC mode, default to software
diff --git a/drivers/net/ax88796.h b/drivers/net/ax88796.h
index 069ae80..0e6f8a2 100644
--- a/drivers/net/ax88796.h
+++ b/drivers/net/ax88796.h
@@ -23,24 +23,24 @@
 #ifndef __DRIVERS_AX88796L_H__
 #define __DRIVERS_AX88796L_H__
 
-#define DP_DATA     (0x10 << 1)
-#define START_PG    0x40    /* First page of TX buffer */
-#define START_PG2   0x48
-#define STOP_PG     0x80    /* Last page +1 of RX ring */
-#define TX_PAGES    12
-#define RX_START    (START_PG+TX_PAGES)
-#define RX_END      STOP_PG
+#define DP_DATA		(0x10 << 1)
+#define START_PG	0x40	/* First page of TX buffer */
+#define START_PG2	0x48
+#define STOP_PG		0x80	/* Last page +1 of RX ring */
+#define TX_PAGES	12
+#define RX_START	(START_PG+TX_PAGES)
+#define RX_END		STOP_PG
 
 #define AX88796L_BASE_ADDRESS	CONFIG_DRIVER_NE2000_BASE
-#define AX88796L_BYTE_ACCESS    0x00001000
-#define AX88796L_OFFSET         0x00000400
-#define AX88796L_ADDRESS_BYTE   AX88796L_BASE_ADDRESS + \
+#define AX88796L_BYTE_ACCESS	0x00001000
+#define AX88796L_OFFSET		0x00000400
+#define AX88796L_ADDRESS_BYTE	AX88796L_BASE_ADDRESS + \
 		AX88796L_BYTE_ACCESS + AX88796L_OFFSET
-#define AX88796L_REG_MEMR       AX88796L_ADDRESS_BYTE + (0x14<<1)
-#define AX88796L_REG_CR         AX88796L_ADDRESS_BYTE + (0x00<<1)
+#define AX88796L_REG_MEMR	AX88796L_ADDRESS_BYTE + (0x14<<1)
+#define AX88796L_REG_CR		AX88796L_ADDRESS_BYTE + (0x00<<1)
 
 #define AX88796L_CR		(*(vu_short *)(AX88796L_REG_CR))
-#define AX88796L_MEMR	(*(vu_short *)(AX88796L_REG_MEMR))
+#define AX88796L_MEMR		(*(vu_short *)(AX88796L_REG_MEMR))
 
 #define EECS_HIGH		(AX88796L_MEMR |= 0x10)
 #define EECS_LOW		(AX88796L_MEMR &= 0xef)
@@ -53,7 +53,7 @@
 #define PAGE0_SET		(AX88796L_CR &= 0x3f)
 #define PAGE1_SET		(AX88796L_CR = (AX88796L_CR & 0x3f) | 0x40)
 
-#define BIT_DUMMY		0
+#define BIT_DUMMY	0
 #define MAC_EEP_READ	1
 #define MAC_EEP_WRITE	2
 #define MAC_EEP_ERACE	3
@@ -62,20 +62,20 @@
 
 /* R7780MP Specific code */
 #if defined(CONFIG_R7780MP)
-#define ISA_OFFSET  0x1400
-#define DP_IN(_b_, _o_, _d_)  (_d_) = \
+#define ISA_OFFSET	0x1400
+#define DP_IN(_b_, _o_, _d_)	(_d_) = \
 	*( (vu_short *) ((_b_) + ((_o_) * 2) + ISA_OFFSET))
 #define DP_OUT(_b_, _o_, _d_) \
 	*((vu_short *)((_b_) + ((_o_) * 2) + ISA_OFFSET)) = (_d_)
-#define DP_IN_DATA(_b_, _d_)  (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET))
-#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
+#define DP_IN_DATA(_b_, _d_)	(_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET))
+#define DP_OUT_DATA(_b_, _d_)	*( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
 #else
 /* Please change for your target boards */
-#define ISA_OFFSET  0x0000
-#define DP_IN(_b_, _o_, _d_)  (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET))
-#define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_)
-#define DP_IN_DATA(_b_, _d_)  (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET))
-#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
+#define ISA_OFFSET	0x0000
+#define DP_IN(_b_, _o_, _d_)	(_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET))
+#define DP_OUT(_b_, _o_, _d_)	*((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_)
+#define DP_IN_DATA(_b_, _d_)	(_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET))
+#define DP_OUT_DATA(_b_, _d_)	*( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
 #endif
 
 
diff --git a/drivers/net/ne2000.c b/drivers/net/ne2000.c
index 99baeea..d09da78 100644
--- a/drivers/net/ne2000.c
+++ b/drivers/net/ne2000.c
@@ -1,5 +1,5 @@
 /*
-Ported to U-Boot  by Christian Pellegrin <chri@ascensit.com>
+Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
 
 Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
 eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
@@ -57,13 +57,13 @@
 ==========================================================================
 #####DESCRIPTIONBEGIN####
 
-Author(s):    gthomas
-Contributors: gthomas, jskov, rsandifo
-Date:	      2001-06-13
+Author(s):	gthomas
+Contributors:	gthomas, jskov, rsandifo
+Date:		2001-06-13
 Purpose:
 Description:
 
-FIXME:	      Will fail if pinged with large packets (1520 bytes)
+FIXME:		Will fail if pinged with large packets (1520 bytes)
 Add promisc config
 Add SNMP
 
@@ -77,24 +77,26 @@
 #include <net.h>
 #include <malloc.h>
 
-#define mdelay(n)       udelay((n)*1000)
+#define mdelay(n)	udelay((n)*1000)
 /* forward definition of function used for the uboot interface */
 void uboot_push_packet_len(int len);
 void uboot_push_tx_done(int key, int val);
 
 /*
-  ------------------------------------------------------------------------
-  Debugging details
-
-  Set to perms of:
-  0 disables all debug output
-  1 for process debug output
-  2 for added data IO output: get_reg, put_reg
-  4 for packet allocation/free output
-  8 for only startup status, so we can tell we're installed OK
-*/
-/*#define DEBUG 0xf*/
+ * Debugging details
+ *
+ * Set to perms of:
+ * 0 disables all debug output
+ * 1 for process debug output
+ * 2 for added data IO output: get_reg, put_reg
+ * 4 for packet allocation/free output
+ * 8 for only startup status, so we can tell we're installed OK
+ */
+#if 0
+#define DEBUG 0xf
+#else
 #define DEBUG 0
+#endif
 
 #if DEBUG & 1
 #define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0)
@@ -128,27 +130,28 @@
 	DEBUG_FUNCTION();
 
 	base = dp->base;
-	if (!base) return false;  /* No device found */
+	if (!base)
+		return false;	/* No device found */
 
 	DEBUG_LINE();
 
 #if defined(NE2000_BASIC_INIT)
 	/* AX88796L doesn't need */
 	/* Prepare ESA */
-	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1);  /* Select page 1 */
+	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1);	/* Select page 1 */
 	/* Use the address from the serial EEPROM */
 	for (i = 0; i < 6; i++)
 		DP_IN(base, DP_P1_PAR0+i, dp->esa[i]);
-	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0);  /* Select page 0 */
+	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0);	/* Select page 0 */
 
 	printf("NE2000 - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n",
-	       "eeprom",
-	       dp->esa[0],
-	       dp->esa[1],
-	       dp->esa[2],
-	       dp->esa[3],
-	       dp->esa[4],
-	       dp->esa[5] );
+		"eeprom",
+		dp->esa[0],
+		dp->esa[1],
+		dp->esa[2],
+		dp->esa[3],
+		dp->esa[4],
+		dp->esa[5] );
 
 #endif	/* NE2000_BASIC_INIT */
 	return true;
@@ -162,7 +165,7 @@
 
 	DEBUG_FUNCTION();
 
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP);  /* Brutal */
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP);	/* Brutal */
 	DP_OUT(base, DP_ISR, 0xFF);		/* Clear any pending interrupts */
 	DP_OUT(base, DP_IMR, 0x00);		/* Disable all interrupts */
 
@@ -170,11 +173,11 @@
 }
 
 /*
-  This function is called to "start up" the interface.  It may be called
-  multiple times, even when the hardware is already running.  It will be
-  called whenever something "hardware oriented" changes and should leave
-  the hardware ready to send/receive packets.
-*/
+ * This function is called to "start up" the interface. It may be called
+ * multiple times, even when the hardware is already running. It will be
+ * called whenever something "hardware oriented" changes and should leave
+ * the hardware ready to send/receive packets.
+ */
 static void
 dp83902a_start(u8 * enaddr)
 {
@@ -196,16 +199,16 @@
 	dp->tx_started = false;
 	dp->running = true;
 	DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */
-	DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); /* Receive ring boundary */
+	DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); /* Receive ring boundary */
 	DP_OUT(base, DP_PSTOP, dp->rx_buf_end);	/* Receive ring end page */
-	dp->rx_next = dp->rx_buf_start-1;
+	dp->rx_next = dp->rx_buf_start - 1;
 	dp->running = true;
 	DP_OUT(base, DP_ISR, 0xFF);		/* Clear any pending interrupts */
 	DP_OUT(base, DP_IMR, DP_IMR_All);	/* Enable all interrupts */
-	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP);  /* Select page 1 */
-	DP_OUT(base, DP_P1_CURP, dp->rx_buf_start);   /* Current page - next free page for Rx */
+	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP);	/* Select page 1 */
+	DP_OUT(base, DP_P1_CURP, dp->rx_buf_start);	/* Current page - next free page for Rx */
 	dp->running = true;
-	for (i = 0;  i < ETHER_ADDR_LEN;  i++) {
+	for (i = 0; i < ETHER_ADDR_LEN; i++) {
 		/* FIXME */
 		/*((vu_short*)( base + ((DP_P1_PAR0 + i) * 2) +
 		 * 0x1400)) = enaddr[i];*/
@@ -214,15 +217,15 @@
 	/* Enable and start device */
 	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
 	DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */
-	DP_OUT(base, DP_RCR, DP_RCR_AB);  /* Accept broadcast, no errors, no multicast */
+	DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */
 	dp->running = true;
 }
 
 /*
-  This routine is called to start the transmitter.  It is split out from the
-  data handling routine so it may be called either when data becomes first
-  available or when an Tx interrupt occurs
-*/
+ * This routine is called to start the transmitter. It is split out from the
+ * data handling routine so it may be called either when data becomes first
+ * available or when an Tx interrupt occurs
+ */
 
 static void
 dp83902a_start_xmit(int start_page, int len)
@@ -249,9 +252,9 @@
 }
 
 /*
-  This routine is called to send data to the hardware.  It is known a-priori
-  that there is free buffer space (dp->tx_next).
-*/
+ * This routine is called to send data to the hardware. It is known a-priori
+ * that there is free buffer space (dp->tx_next).
+ */
 static void
 dp83902a_send(u8 *data, int total_len, u32 key)
 {
@@ -265,7 +268,8 @@
 	DEBUG_FUNCTION();
 
 	len = pkt_len = total_len;
-	if (pkt_len < IEEE_8023_MIN_FRAME) pkt_len = IEEE_8023_MIN_FRAME;
+	if (pkt_len < IEEE_8023_MIN_FRAME)
+		pkt_len = IEEE_8023_MIN_FRAME;
 
 	start_page = dp->tx_next;
 	if (dp->tx_next == dp->tx_buf1) {
@@ -284,17 +288,19 @@
 	printf("TX prep page %d len %d\n", start_page, pkt_len);
 #endif
 
-	DP_OUT(base, DP_ISR, DP_ISR_RDC);  /* Clear end of DMA */
+	DP_OUT(base, DP_ISR, DP_ISR_RDC);	/* Clear end of DMA */
 	{
-		/* Dummy read. The manual sez something slightly different, */
-		/* but the code is extended a bit to do what Hitachi's monitor */
-		/* does (i.e., also read data). */
+		/*
+		 * Dummy read. The manual sez something slightly different,
+		 * but the code is extended a bit to do what Hitachi's monitor
+		 * does (i.e., also read data).
+		 */
 
 		u16 tmp;
 		int len = 1;
 
-		DP_OUT(base, DP_RSAL, 0x100-len);
-		DP_OUT(base, DP_RSAH, (start_page-1) & 0xff);
+		DP_OUT(base, DP_RSAL, 0x100 - len);
+		DP_OUT(base, DP_RSAH, (start_page - 1) & 0xff);
 		DP_OUT(base, DP_RBCL, len);
 		DP_OUT(base, DP_RBCH, 0);
 		DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_RDMA | DP_CR_START);
@@ -302,8 +308,10 @@
 	}
 
 #ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
-	/* Stall for a bit before continuing to work around random data */
-	/* corruption problems on some platforms. */
+	/*
+	 * Stall for a bit before continuing to work around random data
+	 * corruption problems on some platforms.
+	 */
 	CYGACC_CALL_IF_DELAY_US(1);
 #endif
 
@@ -336,16 +344,18 @@
 		printf("  + %d bytes of padding\n", pkt_len - total_len);
 #endif
 		/* Padding to 802.3 length was required */
-		for (i = total_len;  i < pkt_len;) {
+		for (i = total_len; i < pkt_len;) {
 			i++;
 			DP_OUT_DATA(dp->data, 0);
 		}
 	}
 
 #ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
-	/* After last data write, delay for a bit before accessing the */
-	/* device again, or we may get random data corruption in the last */
-	/* datum (on some platforms). */
+	/*
+	 * After last data write, delay for a bit before accessing the
+	 * device again, or we may get random data corruption in the last
+	 * datum (on some platforms).
+	 */
 	CYGACC_CALL_IF_DELAY_US(1);
 #endif
 
@@ -360,21 +370,21 @@
 	/* Start transmit if not already going */
 	if (!dp->tx_started) {
 		if (start_page == dp->tx1) {
-			dp->tx_int = 1;  /* Expecting interrupt from BUF1 */
+			dp->tx_int = 1; /* Expecting interrupt from BUF1 */
 		} else {
-			dp->tx_int = 2;  /* Expecting interrupt from BUF2 */
+			dp->tx_int = 2; /* Expecting interrupt from BUF2 */
 		}
 		dp83902a_start_xmit(start_page, pkt_len);
 	}
 }
 
 /*
-  This function is called when a packet has been received.  It's job is
-  to prepare to unload the packet from the hardware.  Once the length of
-  the packet is known, the upper layer of the driver can be told.  When
-  the upper layer is ready to unload the packet, the internal function
-  'dp83902a_recv' will be called to actually fetch it from the hardware.
-*/
+ * This function is called when a packet has been received. It's job is
+ * to prepare to unload the packet from the hardware. Once the length of
+ * the packet is known, the upper layer of the driver can be told. When
+ * the upper layer is ready to unload the packet, the internal function
+ * 'dp83902a_recv' will be called to actually fetch it from the hardware.
+ */
 static void
 dp83902a_RxEvent(void)
 {
@@ -407,9 +417,9 @@
 		DP_OUT(base, DP_RSAH, pkt);
 		if (dp->rx_next == pkt) {
 			if (cur == dp->rx_buf_start)
-				DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1);
+				DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1);
 			else
-				DP_OUT(base, DP_BNDRY, cur-1); /* Update pointer */
+				DP_OUT(base, DP_BNDRY, cur - 1); /* Update pointer */
 			return;
 		}
 		dp->rx_next = pkt;
@@ -420,13 +430,13 @@
 #endif
 
 		/* read header (get data size)*/
-		for (i = 0;  i < sizeof(rcv_hdr);) {
+		for (i = 0; i < sizeof(rcv_hdr);) {
 			DP_IN_DATA(dp->data, rcv_hdr[i++]);
 		}
 
 #if DEBUG & 5
 		printf("rx hdr %02x %02x %02x %02x\n",
-		       rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]);
+			rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]);
 #endif
 		len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr);
 
@@ -434,19 +444,19 @@
 		uboot_push_packet_len(len);
 
 		if (rcv_hdr[1] == dp->rx_buf_start)
-			DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1);
+			DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1);
 		else
-			DP_OUT(base, DP_BNDRY, rcv_hdr[1]-1); /* Update pointer */
+			DP_OUT(base, DP_BNDRY, rcv_hdr[1] - 1); /* Update pointer */
 	}
 }
 
 /*
-  This function is called as a result of the "eth_drv_recv()" call above.
-  It's job is to actually fetch data for a packet from the hardware once
-  memory buffers have been allocated for the packet.  Note that the buffers
-  may come in pieces, using a scatter-gather list.  This allows for more
-  efficient processing in the upper layers of the stack.
-*/
+ * This function is called as a result of the "eth_drv_recv()" call above.
+ * It's job is to actually fetch data for a packet from the hardware once
+ * memory buffers have been allocated for the packet. Note that the buffers
+ * may come in pieces, using a scatter-gather list. This allows for more
+ * efficient processing in the upper layers of the stack.
+ */
 static void
 dp83902a_recv(u8 *data, int len)
 {
@@ -478,7 +488,7 @@
 #endif
 
 	saved = false;
-	for (i = 0;  i < 1;  i++) {
+	for (i = 0; i < 1; i++) {
 		if (data) {
 			mlen = len;
 #if DEBUG & 4
@@ -545,8 +555,10 @@
 	uboot_push_tx_done(key, 0);
 }
 
-/* Read the tally counters to clear them.  Called in response to a CNT */
-/* interrupt. */
+/*
+ * Read the tally counters to clear them. Called in response to a CNT
+ * interrupt.
+ */
 static void
 dp83902a_ClearCounters(void)
 {
@@ -560,8 +572,10 @@
 	DP_OUT(base, DP_ISR, DP_ISR_CNT);
 }
 
-/* Deal with an overflow condition.  This code follows the procedure set */
-/* out in section 7.0 of the datasheet. */
+/*
+ * Deal with an overflow condition. This code follows the procedure set
+ * out in section 7.0 of the datasheet.
+ */
 static void
 dp83902a_Overflow(void)
 {
@@ -581,9 +595,11 @@
 	DP_OUT(base, DP_TCR, DP_TCR_LOCAL);
 	DP_OUT(base, DP_CR, DP_CR_START | DP_CR_NODMA);
 
-	/* Read in as many packets as we can and acknowledge any and receive */
-	/* interrupts.  Since the buffer has overflowed, a receive event of */
-	/* some kind will have occured. */
+	/*
+	 * Read in as many packets as we can and acknowledge any and receive
+	 * interrupts. Since the buffer has overflowed, a receive event of
+	 * some kind will have occured.
+	 */
 	dp83902a_RxEvent();
 	DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE);
 
@@ -591,8 +607,10 @@
 	DP_OUT(base, DP_ISR, DP_ISR_OFLW);
 	DP_OUT(base, DP_TCR, DP_TCR_NORMAL);
 
-	/* If a transmit command was issued, but no transmit event has occured, */
-	/* restart it here. */
+	/*
+	 * If a transmit command was issued, but no transmit event has occured,
+	 * restart it here.
+	 */
 	DP_IN(base, DP_ISR, isr);
 	if (dp->tx_started && !(isr & (DP_ISR_TxP|DP_ISR_TxE))) {
 		DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START);
@@ -609,25 +627,33 @@
 	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START);
 	DP_IN(base, DP_ISR, isr);
 	while (0 != isr) {
-		/* The CNT interrupt triggers when the MSB of one of the error */
-		/* counters is set.  We don't much care about these counters, but */
-		/* we should read their values to reset them. */
+		/*
+		 * The CNT interrupt triggers when the MSB of one of the error
+		 * counters is set. We don't much care about these counters, but
+		 * we should read their values to reset them.
+		 */
 		if (isr & DP_ISR_CNT) {
 			dp83902a_ClearCounters();
 		}
-		/* Check for overflow.  It's a special case, since there's a */
-		/* particular procedure that must be followed to get back into */
-		/* a running state.a */
+		/*
+		 * Check for overflow. It's a special case, since there's a
+		 * particular procedure that must be followed to get back into
+		 * a running state.a
+		 */
 		if (isr & DP_ISR_OFLW) {
 			dp83902a_Overflow();
 		} else {
-			/* Other kinds of interrupts can be acknowledged simply by */
-			/* clearing the relevant bits of the ISR.  Do that now, then */
-			/* handle the interrupts we care about. */
-			DP_OUT(base, DP_ISR, isr);      /* Clear set bits */
+			/*
+			 * Other kinds of interrupts can be acknowledged simply by
+			 * clearing the relevant bits of the ISR. Do that now, then
+			 * handle the interrupts we care about.
+			 */
+			DP_OUT(base, DP_ISR, isr);	/* Clear set bits */
 			if (!dp->running) break;	/* Is this necessary? */
-			/* Check for tx_started on TX event since these may happen */
-			/* spuriously it seems. */
+			/*
+			 * Check for tx_started on TX event since these may happen
+			 * spuriously it seems.
+			 */
 			if (isr & (DP_ISR_TxP|DP_ISR_TxE) && dp->tx_started) {
 				dp83902a_TxEvent();
 			}
@@ -658,8 +684,8 @@
 #define HAS_MII		0x40
 #define USE_SHMEM	0x80	/* autodetected */
 
-#define AM79C9XX_HOME_PHY	0x00006B90  /* HomePNA PHY */
-#define AM79C9XX_ETH_PHY	0x00006B70  /* 10baseT PHY */
+#define AM79C9XX_HOME_PHY	0x00006B90	/* HomePNA PHY */
+#define AM79C9XX_ETH_PHY	0x00006B70	/* 10baseT PHY */
 #define MII_PHYID_REV_MASK	0xfffffff0
 #define MII_PHYID_REG1		0x02
 #define MII_PHYID_REG2		0x03
@@ -669,7 +695,7 @@
 	{ /* Allied Telesis LA-PCM */ 0x0ff0, 0x00, 0x00, 0xf4, 0 },
 	{ /* APEX MultiCard */ 0x03f4, 0x00, 0x20, 0xe5, 0 },
 	{ /* ASANTE FriendlyNet */ 0x4910, 0x00, 0x00, 0x94,
-	  DELAY_OUTPUT | HAS_IBM_MISC },
+			DELAY_OUTPUT | HAS_IBM_MISC },
 	{ /* Danpex EN-6200P2 */ 0x0110, 0x00, 0x40, 0xc7, 0 },
 	{ /* DataTrek NetCard */ 0x0ff0, 0x00, 0x20, 0xe8, 0 },
 	{ /* Dayna CommuniCard E */ 0x0110, 0x00, 0x80, 0x19, 0 },
@@ -677,48 +703,48 @@
 	{ /* EP-210 Ethernet */ 0x0110, 0x00, 0x40, 0x33, 0 },
 	{ /* EP4000 Ethernet */ 0x01c0, 0x00, 0x00, 0xb4, 0 },
 	{ /* Epson EEN10B */ 0x0ff0, 0x00, 0x00, 0x48,
-	  HAS_MISC_REG | HAS_IBM_MISC },
+			HAS_MISC_REG | HAS_IBM_MISC },
 	{ /* ELECOM Laneed LD-CDWA */ 0xb8, 0x08, 0x00, 0x42, 0 },
 	{ /* Hypertec Ethernet */ 0x01c0, 0x00, 0x40, 0x4c, 0 },
 	{ /* IBM CCAE */ 0x0ff0, 0x08, 0x00, 0x5a,
-	  HAS_MISC_REG | HAS_IBM_MISC },
+			HAS_MISC_REG | HAS_IBM_MISC },
 	{ /* IBM CCAE */ 0x0ff0, 0x00, 0x04, 0xac,
-	  HAS_MISC_REG | HAS_IBM_MISC },
+			HAS_MISC_REG | HAS_IBM_MISC },
 	{ /* IBM CCAE */ 0x0ff0, 0x00, 0x06, 0x29,
-	  HAS_MISC_REG | HAS_IBM_MISC },
+			HAS_MISC_REG | HAS_IBM_MISC },
 	{ /* IBM FME */ 0x0374, 0x08, 0x00, 0x5a,
-	  HAS_MISC_REG | HAS_IBM_MISC },
+			HAS_MISC_REG | HAS_IBM_MISC },
 	{ /* IBM FME */ 0x0374, 0x00, 0x04, 0xac,
-	  HAS_MISC_REG | HAS_IBM_MISC },
+			HAS_MISC_REG | HAS_IBM_MISC },
 	{ /* Kansai KLA-PCM/T */ 0x0ff0, 0x00, 0x60, 0x87,
-	  HAS_MISC_REG | HAS_IBM_MISC },
+			HAS_MISC_REG | HAS_IBM_MISC },
 	{ /* NSC DP83903 */ 0x0374, 0x08, 0x00, 0x17,
-	  HAS_MISC_REG | HAS_IBM_MISC },
+			HAS_MISC_REG | HAS_IBM_MISC },
 	{ /* NSC DP83903 */ 0x0374, 0x00, 0xc0, 0xa8,
-	  HAS_MISC_REG | HAS_IBM_MISC },
+			HAS_MISC_REG | HAS_IBM_MISC },
 	{ /* NSC DP83903 */ 0x0374, 0x00, 0xa0, 0xb0,
-	  HAS_MISC_REG | HAS_IBM_MISC },
+			HAS_MISC_REG | HAS_IBM_MISC },
 	{ /* NSC DP83903 */ 0x0198, 0x00, 0x20, 0xe0,
-	  HAS_MISC_REG | HAS_IBM_MISC },
+			HAS_MISC_REG | HAS_IBM_MISC },
 	{ /* I-O DATA PCLA/T */ 0x0ff0, 0x00, 0xa0, 0xb0, 0 },
 	{ /* Katron PE-520 */ 0x0110, 0x00, 0x40, 0xf6, 0 },
 	{ /* Kingston KNE-PCM/x */ 0x0ff0, 0x00, 0xc0, 0xf0,
-	  HAS_MISC_REG | HAS_IBM_MISC },
+			HAS_MISC_REG | HAS_IBM_MISC },
 	{ /* Kingston KNE-PCM/x */ 0x0ff0, 0xe2, 0x0c, 0x0f,
-	  HAS_MISC_REG | HAS_IBM_MISC },
+			HAS_MISC_REG | HAS_IBM_MISC },
 	{ /* Kingston KNE-PC2 */ 0x0180, 0x00, 0xc0, 0xf0, 0 },
 	{ /* Maxtech PCN2000 */ 0x5000, 0x00, 0x00, 0xe8, 0 },
 	{ /* NDC Instant-Link */ 0x003a, 0x00, 0x80, 0xc6, 0 },
 	{ /* NE2000 Compatible */ 0x0ff0, 0x00, 0xa0, 0x0c, 0 },
 	{ /* Network General Sniffer */ 0x0ff0, 0x00, 0x00, 0x65,
-	  HAS_MISC_REG | HAS_IBM_MISC },
+			HAS_MISC_REG | HAS_IBM_MISC },
 	{ /* Panasonic VEL211 */ 0x0ff0, 0x00, 0x80, 0x45,
-	  HAS_MISC_REG | HAS_IBM_MISC },
+			HAS_MISC_REG | HAS_IBM_MISC },
 	{ /* PreMax PE-200 */ 0x07f0, 0x00, 0x20, 0xe0, 0 },
 	{ /* RPTI EP400 */ 0x0110, 0x00, 0x40, 0x95, 0 },
 	{ /* SCM Ethernet */ 0x0ff0, 0x00, 0x20, 0xcb, 0 },
 	{ /* Socket EA */ 0x4000, 0x00, 0xc0, 0x1b,
-	  DELAY_OUTPUT | HAS_MISC_REG | USE_BIG_BUF },
+			DELAY_OUTPUT | HAS_MISC_REG | USE_BIG_BUF },
 	{ /* Socket LP-E CF+ */ 0x01c0, 0x00, 0xc0, 0x1b, 0 },
 	{ /* SuperSocket RE450T */ 0x0110, 0x00, 0xe0, 0x98, 0 },
 	{ /* Volktek NPL-402CT */ 0x0060, 0x00, 0x40, 0x05, 0 },
@@ -744,11 +770,11 @@
 static u8 *pbuf = NULL;
 
 static int pkey = -1;
-static int initialized=0;
+static int initialized = 0;
 
 void uboot_push_packet_len(int len) {
 	PRINTK("pushed len = %d\n", len);
-	if (len>=2000) {
+	if (len >= 2000) {
 		printf("NE2000: packet too big\n");
 		return;
 	}
@@ -779,7 +805,7 @@
 
 #ifdef CONFIG_DRIVER_NE2000_CCR
 	{
-		vu_char *p =  (vu_char *) CONFIG_DRIVER_NE2000_CCR;
+		vu_char *p = (vu_char *) CONFIG_DRIVER_NE2000_CCR;
 
 		PRINTK("CCR before is %x\n", *p);
 		*p = CONFIG_DRIVER_NE2000_VAL;
@@ -811,7 +837,7 @@
 		return -1;
 
 	dp83902a_start(dev_addr);
-	initialized=1;
+	initialized = 1;
 
 	return 0;
 }
@@ -821,7 +847,7 @@
 	PRINTK("### eth_halt\n");
 	if(initialized)
 		dp83902a_stop();
-	initialized=0;
+	initialized = 0;
 }
 
 int eth_rx() {
diff --git a/drivers/net/ne2000.h b/drivers/net/ne2000.h
index d324a00..6049482 100644
--- a/drivers/net/ne2000.h
+++ b/drivers/net/ne2000.h
@@ -1,5 +1,5 @@
 /*
-Ported to U-Boot  by Christian Pellegrin <chri@ascensit.com>
+Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
 
 Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
 eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
@@ -7,9 +7,9 @@
 
 ==========================================================================
 
-      dev/dp83902a.h
+	dev/dp83902a.h
 
-      National Semiconductor DP83902a ethernet chip
+	National Semiconductor DP83902a ethernet chip
 
 ==========================================================================
 ####ECOSGPLCOPYRIGHTBEGIN####
@@ -57,9 +57,9 @@
 ==========================================================================
 #####DESCRIPTIONBEGIN####
 
- Author(s):    gthomas
- Contributors: gthomas, jskov
- Date:         2001-06-13
+ Author(s):	gthomas
+ Contributors:	gthomas, jskov
+ Date:		2001-06-13
  Purpose:
  Description:
 
@@ -79,17 +79,17 @@
 /* Enable NE2000 basic init function */
 #define NE2000_BASIC_INIT
 
-#define DP_DATA     0x10
-#define START_PG    0x50    /* First page of TX buffer */
-#define STOP_PG     0x80    /* Last page +1 of RX ring */
+#define DP_DATA		0x10
+#define START_PG	0x50	/* First page of TX buffer */
+#define STOP_PG		0x80	/* Last page +1 of RX ring */
 
-#define RX_START    0x50
-#define RX_END      0x80
+#define RX_START	0x50
+#define RX_END		0x80
 
-#define DP_IN(_b_, _o_, _d_)  (_d_) = *( (vu_char *) ((_b_)+(_o_)))
-#define DP_OUT(_b_, _o_, _d_) *( (vu_char *) ((_b_)+(_o_))) = (_d_)
-#define DP_IN_DATA(_b_, _d_)  (_d_) = *( (vu_char *) ((_b_)))
-#define DP_OUT_DATA(_b_, _d_) *( (vu_char *) ((_b_))) = (_d_)
+#define DP_IN(_b_, _o_, _d_)	(_d_) = *( (vu_char *) ((_b_)+(_o_)))
+#define DP_OUT(_b_, _o_, _d_)	*( (vu_char *) ((_b_)+(_o_))) = (_d_)
+#define DP_IN_DATA(_b_, _d_)	(_d_) = *( (vu_char *) ((_b_)))
+#define DP_OUT_DATA(_b_, _d_)	*( (vu_char *) ((_b_))) = (_d_)
 
 static void pcnet_reset_8390(void)
 {
diff --git a/drivers/net/ne2000_base.h b/drivers/net/ne2000_base.h
index 1badf62..990d748 100644
--- a/drivers/net/ne2000_base.h
+++ b/drivers/net/ne2000_base.h
@@ -1,5 +1,5 @@
 /*
-Ported to U-Boot  by Christian Pellegrin <chri@ascensit.com>
+Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
 
 Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
 eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
@@ -8,9 +8,9 @@
 
 ==========================================================================
 
-      dev/dp83902a.h
+	dev/dp83902a.h
 
-      National Semiconductor DP83902a ethernet chip
+	National Semiconductor DP83902a ethernet chip
 
 ==========================================================================
 ####ECOSGPLCOPYRIGHTBEGIN####
@@ -58,9 +58,9 @@
 ==========================================================================
 #####DESCRIPTIONBEGIN####
 
- Author(s):    gthomas
- Contributors: gthomas, jskov
- Date:         2001-06-13
+ Author(s):	gthomas
+ Contributors:	gthomas, jskov
+ Date:		2001-06-13
  Purpose:
  Description:
 
@@ -76,6 +76,9 @@
  These can be overridden by the platform header
 */
 
+#ifndef __NE2000_BASE_H__
+#define __NE2000_BASE_H__
+
 #define bool int
 
 #define false 0
@@ -92,191 +95,191 @@
 
 /* H/W infomation struct */
 typedef struct hw_info_t {
-    u32   offset;
-    u8  a0, a1, a2;
-    u32   flags;
+	u32 offset;
+	u8 a0, a1, a2;
+	u32 flags;
 } hw_info_t;
 
 typedef struct dp83902a_priv_data {
-    u8* base;
-    u8* data;
-    u8* reset;
-    int tx_next;           /* First free Tx page */
-    int tx_int;            /* Expecting interrupt from this buffer */
-    int rx_next;           /* First free Rx page */
-    int tx1, tx2;          /* Page numbers for Tx buffers */
-    u32 tx1_key, tx2_key;   /* Used to ack when packet sent */
-    int tx1_len, tx2_len;
-    bool tx_started, running, hardwired_esa;
-    u8 esa[6];
-    void* plf_priv;
+	u8* base;
+	u8* data;
+	u8* reset;
+	int tx_next;		/* First free Tx page */
+	int tx_int;		/* Expecting interrupt from this buffer */
+	int rx_next;		/* First free Rx page */
+	int tx1, tx2;		/* Page numbers for Tx buffers */
+	u32 tx1_key, tx2_key;	/* Used to ack when packet sent */
+	int tx1_len, tx2_len;
+	bool tx_started, running, hardwired_esa;
+	u8 esa[6];
+	void* plf_priv;
 
-    /* Buffer allocation */
-    int tx_buf1, tx_buf2;
-    int rx_buf_start, rx_buf_end;
+	/* Buffer allocation */
+	int tx_buf1, tx_buf2;
+	int rx_buf_start, rx_buf_end;
 } dp83902a_priv_data_t;
 
 /*
- ------------------------------------------------------------------------
- Some forward declarations
-*/
+ * Some forward declarations
+ */
 int get_prom( u8* mac_addr);
 static void dp83902a_poll(void);
 
 /* ------------------------------------------------------------------------ */
 /* Register offsets */
 
-#define DP_CR          0x00
-#define DP_CLDA0       0x01
-#define DP_PSTART      0x01             /* write */
-#define DP_CLDA1       0x02
-#define DP_PSTOP       0x02             /* write */
-#define DP_BNDRY       0x03
-#define DP_TSR         0x04
-#define DP_TPSR        0x04             /* write */
-#define DP_NCR         0x05
-#define DP_TBCL        0x05             /* write */
-#define DP_FIFO        0x06
-#define DP_TBCH        0x06             /* write */
-#define DP_ISR         0x07
-#define DP_CRDA0       0x08
-#define DP_RSAL        0x08             /* write */
-#define DP_CRDA1       0x09
-#define DP_RSAH        0x09             /* write */
-#define DP_RBCL        0x0a             /* write */
-#define DP_RBCH        0x0b             /* write */
-#define DP_RSR         0x0c
-#define DP_RCR         0x0c             /* write */
-#define DP_FER         0x0d
-#define DP_TCR         0x0d             /* write */
-#define DP_CER         0x0e
-#define DP_DCR         0x0e             /* write */
-#define DP_MISSED      0x0f
-#define DP_IMR         0x0f             /* write */
-#define DP_DATAPORT    0x10             /* "eprom" data port */
+#define DP_CR		0x00
+#define DP_CLDA0	0x01
+#define DP_PSTART	0x01	/* write */
+#define DP_CLDA1	0x02
+#define DP_PSTOP	0x02	/* write */
+#define DP_BNDRY	0x03
+#define DP_TSR		0x04
+#define DP_TPSR		0x04	/* write */
+#define DP_NCR		0x05
+#define DP_TBCL		0x05	/* write */
+#define DP_FIFO		0x06
+#define DP_TBCH		0x06	/* write */
+#define DP_ISR		0x07
+#define DP_CRDA0	0x08
+#define DP_RSAL		0x08	/* write */
+#define DP_CRDA1	0x09
+#define DP_RSAH		0x09	/* write */
+#define DP_RBCL		0x0a	/* write */
+#define DP_RBCH		0x0b	/* write */
+#define DP_RSR		0x0c
+#define DP_RCR		0x0c	/* write */
+#define DP_FER		0x0d
+#define DP_TCR		0x0d	/* write */
+#define DP_CER		0x0e
+#define DP_DCR		0x0e	/* write */
+#define DP_MISSED	0x0f
+#define DP_IMR		0x0f	/* write */
+#define DP_DATAPORT	0x10	/* "eprom" data port */
 
-#define DP_P1_CR       0x00
-#define DP_P1_PAR0     0x01
-#define DP_P1_PAR1     0x02
-#define DP_P1_PAR2     0x03
-#define DP_P1_PAR3     0x04
-#define DP_P1_PAR4     0x05
-#define DP_P1_PAR5     0x06
-#define DP_P1_CURP     0x07
-#define DP_P1_MAR0     0x08
-#define DP_P1_MAR1     0x09
-#define DP_P1_MAR2     0x0a
-#define DP_P1_MAR3     0x0b
-#define DP_P1_MAR4     0x0c
-#define DP_P1_MAR5     0x0d
-#define DP_P1_MAR6     0x0e
-#define DP_P1_MAR7     0x0f
+#define DP_P1_CR	0x00
+#define DP_P1_PAR0	0x01
+#define DP_P1_PAR1	0x02
+#define DP_P1_PAR2	0x03
+#define DP_P1_PAR3	0x04
+#define DP_P1_PAR4	0x05
+#define DP_P1_PAR5	0x06
+#define DP_P1_CURP	0x07
+#define DP_P1_MAR0	0x08
+#define DP_P1_MAR1	0x09
+#define DP_P1_MAR2	0x0a
+#define DP_P1_MAR3	0x0b
+#define DP_P1_MAR4	0x0c
+#define DP_P1_MAR5	0x0d
+#define DP_P1_MAR6	0x0e
+#define DP_P1_MAR7	0x0f
 
-#define DP_P2_CR       0x00
-#define DP_P2_PSTART   0x01
-#define DP_P2_CLDA0    0x01             /* write */
-#define DP_P2_PSTOP    0x02
-#define DP_P2_CLDA1    0x02             /* write */
-#define DP_P2_RNPP     0x03
-#define DP_P2_TPSR     0x04
-#define DP_P2_LNPP     0x05
-#define DP_P2_ACH      0x06
-#define DP_P2_ACL      0x07
-#define DP_P2_RCR      0x0c
-#define DP_P2_TCR      0x0d
-#define DP_P2_DCR      0x0e
-#define DP_P2_IMR      0x0f
+#define DP_P2_CR	0x00
+#define DP_P2_PSTART	0x01
+#define DP_P2_CLDA0	0x01	/* write */
+#define DP_P2_PSTOP	0x02
+#define DP_P2_CLDA1	0x02	/* write */
+#define DP_P2_RNPP	0x03
+#define DP_P2_TPSR	0x04
+#define DP_P2_LNPP	0x05
+#define DP_P2_ACH	0x06
+#define DP_P2_ACL	0x07
+#define DP_P2_RCR	0x0c
+#define DP_P2_TCR	0x0d
+#define DP_P2_DCR	0x0e
+#define DP_P2_IMR	0x0f
 
 /* Command register - common to all pages */
 
-#define DP_CR_STOP    0x01   /* Stop: software reset */
-#define DP_CR_START   0x02   /* Start: initialize device */
-#define DP_CR_TXPKT   0x04   /* Transmit packet */
-#define DP_CR_RDMA    0x08   /* Read DMA  (recv data from device) */
-#define DP_CR_WDMA    0x10   /* Write DMA (send data to device) */
-#define DP_CR_SEND    0x18   /* Send packet */
-#define DP_CR_NODMA   0x20   /* Remote (or no) DMA */
-#define DP_CR_PAGE0   0x00   /* Page select */
-#define DP_CR_PAGE1   0x40
-#define DP_CR_PAGE2   0x80
-#define DP_CR_PAGEMSK 0x3F   /* Used to mask out page bits */
+#define DP_CR_STOP	0x01	/* Stop: software reset */
+#define DP_CR_START	0x02	/* Start: initialize device */
+#define DP_CR_TXPKT	0x04	/* Transmit packet */
+#define DP_CR_RDMA	0x08	/* Read DMA (recv data from device) */
+#define DP_CR_WDMA	0x10	/* Write DMA (send data to device) */
+#define DP_CR_SEND	0x18	/* Send packet */
+#define DP_CR_NODMA	0x20	/* Remote (or no) DMA */
+#define DP_CR_PAGE0	0x00	/* Page select */
+#define DP_CR_PAGE1	0x40
+#define DP_CR_PAGE2	0x80
+#define DP_CR_PAGEMSK	0x3F	/* Used to mask out page bits */
 
 /* Data configuration register */
 
-#define DP_DCR_WTS    0x01   /* 1=16 bit word transfers */
-#define DP_DCR_BOS    0x02   /* 1=Little Endian */
-#define DP_DCR_LAS    0x04   /* 1=Single 32 bit DMA mode */
-#define DP_DCR_LS     0x08   /* 1=normal mode, 0=loopback */
-#define DP_DCR_ARM    0x10   /* 0=no send command (program I/O) */
-#define DP_DCR_FIFO_1 0x00   /* FIFO threshold */
-#define DP_DCR_FIFO_2 0x20
-#define DP_DCR_FIFO_4 0x40
-#define DP_DCR_FIFO_6 0x60
+#define DP_DCR_WTS	0x01	/* 1=16 bit word transfers */
+#define DP_DCR_BOS	0x02	/* 1=Little Endian */
+#define DP_DCR_LAS	0x04	/* 1=Single 32 bit DMA mode */
+#define DP_DCR_LS	0x08	/* 1=normal mode, 0=loopback */
+#define DP_DCR_ARM	0x10	/* 0=no send command (program I/O) */
+#define DP_DCR_FIFO_1	0x00	/* FIFO threshold */
+#define DP_DCR_FIFO_2	0x20
+#define DP_DCR_FIFO_4	0x40
+#define DP_DCR_FIFO_6	0x60
 
-#define DP_DCR_INIT   (DP_DCR_LS|DP_DCR_FIFO_4)
+#define DP_DCR_INIT	(DP_DCR_LS|DP_DCR_FIFO_4)
 
 /* Interrupt status register */
 
-#define DP_ISR_RxP    0x01   /* Packet received */
-#define DP_ISR_TxP    0x02   /* Packet transmitted */
-#define DP_ISR_RxE    0x04   /* Receive error */
-#define DP_ISR_TxE    0x08   /* Transmit error */
-#define DP_ISR_OFLW   0x10   /* Receive overflow */
-#define DP_ISR_CNT    0x20   /* Tally counters need emptying */
-#define DP_ISR_RDC    0x40   /* Remote DMA complete */
-#define DP_ISR_RESET  0x80   /* Device has reset (shutdown, error) */
+#define DP_ISR_RxP	0x01	/* Packet received */
+#define DP_ISR_TxP	0x02	/* Packet transmitted */
+#define DP_ISR_RxE	0x04	/* Receive error */
+#define DP_ISR_TxE	0x08	/* Transmit error */
+#define DP_ISR_OFLW	0x10	/* Receive overflow */
+#define DP_ISR_CNT	0x20	/* Tally counters need emptying */
+#define DP_ISR_RDC	0x40	/* Remote DMA complete */
+#define DP_ISR_RESET	0x80	/* Device has reset (shutdown, error) */
 
 /* Interrupt mask register */
 
-#define DP_IMR_RxP    0x01   /* Packet received */
-#define DP_IMR_TxP    0x02   /* Packet transmitted */
-#define DP_IMR_RxE    0x04   /* Receive error */
-#define DP_IMR_TxE    0x08   /* Transmit error */
-#define DP_IMR_OFLW   0x10   /* Receive overflow */
-#define DP_IMR_CNT    0x20   /* Tall counters need emptying */
-#define DP_IMR_RDC    0x40   /* Remote DMA complete */
+#define DP_IMR_RxP	0x01	/* Packet received */
+#define DP_IMR_TxP	0x02	/* Packet transmitted */
+#define DP_IMR_RxE	0x04	/* Receive error */
+#define DP_IMR_TxE	0x08	/* Transmit error */
+#define DP_IMR_OFLW	0x10	/* Receive overflow */
+#define DP_IMR_CNT	0x20	/* Tall counters need emptying */
+#define DP_IMR_RDC	0x40	/* Remote DMA complete */
 
-#define DP_IMR_All    0x3F   /* Everything but remote DMA */
+#define DP_IMR_All	0x3F	/* Everything but remote DMA */
 
 /* Receiver control register */
 
-#define DP_RCR_SEP    0x01   /* Save bad(error) packets */
-#define DP_RCR_AR     0x02   /* Accept runt packets */
-#define DP_RCR_AB     0x04   /* Accept broadcast packets */
-#define DP_RCR_AM     0x08   /* Accept multicast packets */
-#define DP_RCR_PROM   0x10   /* Promiscuous mode */
-#define DP_RCR_MON    0x20   /* Monitor mode - 1=accept no packets */
+#define DP_RCR_SEP	0x01	/* Save bad(error) packets */
+#define DP_RCR_AR	0x02	/* Accept runt packets */
+#define DP_RCR_AB	0x04	/* Accept broadcast packets */
+#define DP_RCR_AM	0x08	/* Accept multicast packets */
+#define DP_RCR_PROM	0x10	/* Promiscuous mode */
+#define DP_RCR_MON	0x20	/* Monitor mode - 1=accept no packets */
 
 /* Receiver status register */
 
-#define DP_RSR_RxP    0x01   /* Packet received */
-#define DP_RSR_CRC    0x02   /* CRC error */
-#define DP_RSR_FRAME  0x04   /* Framing error */
-#define DP_RSR_FO     0x08   /* FIFO overrun */
-#define DP_RSR_MISS   0x10   /* Missed packet */
-#define DP_RSR_PHY    0x20   /* 0=pad match, 1=mad match */
-#define DP_RSR_DIS    0x40   /* Receiver disabled */
-#define DP_RSR_DFR    0x80   /* Receiver processing deferred */
+#define DP_RSR_RxP	0x01	/* Packet received */
+#define DP_RSR_CRC	0x02	/* CRC error */
+#define DP_RSR_FRAME	0x04	/* Framing error */
+#define DP_RSR_FO	0x08	/* FIFO overrun */
+#define DP_RSR_MISS	0x10	/* Missed packet */
+#define DP_RSR_PHY	0x20	/* 0=pad match, 1=mad match */
+#define DP_RSR_DIS	0x40	/* Receiver disabled */
+#define DP_RSR_DFR	0x80	/* Receiver processing deferred */
 
 /* Transmitter control register */
 
-#define DP_TCR_NOCRC  0x01   /* 1=inhibit CRC */
-#define DP_TCR_NORMAL 0x00   /* Normal transmitter operation */
-#define DP_TCR_LOCAL  0x02   /* Internal NIC loopback */
-#define DP_TCR_INLOOP 0x04   /* Full internal loopback */
-#define DP_TCR_OUTLOOP 0x08  /* External loopback */
-#define DP_TCR_ATD    0x10   /* Auto transmit disable */
-#define DP_TCR_OFFSET 0x20   /* Collision offset adjust */
+#define DP_TCR_NOCRC	0x01	/* 1=inhibit CRC */
+#define DP_TCR_NORMAL	0x00	/* Normal transmitter operation */
+#define DP_TCR_LOCAL	0x02	/* Internal NIC loopback */
+#define DP_TCR_INLOOP	0x04	/* Full internal loopback */
+#define DP_TCR_OUTLOOP	0x08	/* External loopback */
+#define DP_TCR_ATD	0x10	/* Auto transmit disable */
+#define DP_TCR_OFFSET	0x20	/* Collision offset adjust */
 
 /* Transmit status register */
 
-#define DP_TSR_TxP    0x01   /* Packet transmitted */
-#define DP_TSR_COL    0x04   /* Collision (at least one) */
-#define DP_TSR_ABT    0x08   /* Aborted because of too many collisions */
-#define DP_TSR_CRS    0x10   /* Lost carrier */
-#define DP_TSR_FU     0x20   /* FIFO underrun */
-#define DP_TSR_CDH    0x40   /* Collision Detect Heartbeat */
-#define DP_TSR_OWC    0x80   /* Collision outside normal window */
+#define DP_TSR_TxP	0x01	/* Packet transmitted */
+#define DP_TSR_COL	0x04	/* Collision (at least one) */
+#define DP_TSR_ABT	0x08	/* Aborted because of too many collisions */
+#define DP_TSR_CRS	0x10	/* Lost carrier */
+#define DP_TSR_FU	0x20	/* FIFO underrun */
+#define DP_TSR_CDH	0x40	/* Collision Detect Heartbeat */
+#define DP_TSR_OWC	0x80	/* Collision outside normal window */
 
-#define IEEE_8023_MAX_FRAME         1518    /* Largest possible ethernet frame */
-#define IEEE_8023_MIN_FRAME           64    /* Smallest possible ethernet frame */
+#define IEEE_8023_MAX_FRAME	1518	/* Largest possible ethernet frame */
+#define IEEE_8023_MIN_FRAME	64	/* Smallest possible ethernet frame */
+#endif /* __NE2000_BASE_H__ */
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index 4e270c9..386fa50 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -30,7 +30,7 @@
 #include <pci.h>
 
 #if 0
-#define	PCNET_DEBUG_LEVEL	0 /* 0=off, 1=init, 2=rx/tx */
+#define	PCNET_DEBUG_LEVEL	0	/* 0=off, 1=init, 2=rx/tx */
 #endif
 
 #if PCNET_DEBUG_LEVEL > 0
@@ -70,42 +70,42 @@
 
 /* The PCNET Rx and Tx ring descriptors. */
 struct pcnet_rx_head {
-    u32 base;
-    s16 buf_length;
-    s16 status;
-    u32 msg_length;
-    u32 reserved;
+	u32 base;
+	s16 buf_length;
+	s16 status;
+	u32 msg_length;
+	u32 reserved;
 };
 
 struct pcnet_tx_head {
-    u32 base;
-    s16 length;
-    s16 status;
-    u32 misc;
-    u32 reserved;
+	u32 base;
+	s16 length;
+	s16 status;
+	u32 misc;
+	u32 reserved;
 };
 
 /* The PCNET 32-Bit initialization block, described in databook. */
 struct pcnet_init_block {
-    u16 mode;
-    u16 tlen_rlen;
-    u8	phys_addr[6];
-    u16 reserved;
-    u32 filter[2];
-    /* Receive and transmit ring base, along with extra bits. */
-    u32 rx_ring;
-    u32 tx_ring;
-    u32 reserved2;
+	u16 mode;
+	u16 tlen_rlen;
+	u8 phys_addr[6];
+	u16 reserved;
+	u32 filter[2];
+	/* Receive and transmit ring base, along with extra bits. */
+	u32 rx_ring;
+	u32 tx_ring;
+	u32 reserved2;
 };
 
 typedef struct pcnet_priv {
-    struct pcnet_rx_head    rx_ring[RX_RING_SIZE];
-    struct pcnet_tx_head    tx_ring[TX_RING_SIZE];
-    struct pcnet_init_block init_block;
-    /* Receive Buffer space */
-    unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
-    int cur_rx;
-    int cur_tx;
+	struct pcnet_rx_head rx_ring[RX_RING_SIZE];
+	struct pcnet_tx_head tx_ring[TX_RING_SIZE];
+	struct pcnet_init_block init_block;
+	/* Receive Buffer space */
+	unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
+	int cur_rx;
+	int cur_tx;
 } pcnet_priv_t;
 
 static pcnet_priv_t *lp;
@@ -118,57 +118,121 @@
 
 static u16 pcnet_read_csr (struct eth_device *dev, int index)
 {
-    outw (index, dev->iobase+PCNET_RAP);
-    return inw (dev->iobase+PCNET_RDP);
+	outw (index, dev->iobase + PCNET_RAP);
+	return inw (dev->iobase + PCNET_RDP);
 }
 
 static void pcnet_write_csr (struct eth_device *dev, int index, u16 val)
 {
-    outw (index, dev->iobase+PCNET_RAP);
-    outw (val, dev->iobase+PCNET_RDP);
+	outw (index, dev->iobase + PCNET_RAP);
+	outw (val, dev->iobase + PCNET_RDP);
 }
 
 static u16 pcnet_read_bcr (struct eth_device *dev, int index)
 {
-    outw (index, dev->iobase+PCNET_RAP);
-    return inw (dev->iobase+PCNET_BDP);
+	outw (index, dev->iobase + PCNET_RAP);
+	return inw (dev->iobase + PCNET_BDP);
 }
 
 static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val)
 {
-    outw (index, dev->iobase+PCNET_RAP);
-    outw (val, dev->iobase+PCNET_BDP);
+	outw (index, dev->iobase + PCNET_RAP);
+	outw (val, dev->iobase + PCNET_BDP);
 }
 
 static void pcnet_reset (struct eth_device *dev)
 {
-    inw (dev->iobase+PCNET_RESET);
+	inw (dev->iobase + PCNET_RESET);
 }
 
 static int pcnet_check (struct eth_device *dev)
 {
-    outw (88, dev->iobase+PCNET_RAP);
-    return (inw (dev->iobase+PCNET_RAP) == 88);
+	outw (88, dev->iobase + PCNET_RAP);
+	return (inw (dev->iobase + PCNET_RAP) == 88);
 }
 
-static int  pcnet_init( struct eth_device* dev, bd_t *bis);
-static int  pcnet_send (struct eth_device* dev, volatile void *packet,
-			int length);
-static int  pcnet_recv (struct eth_device* dev);
-static void pcnet_halt (struct eth_device* dev);
-static int  pcnet_probe(struct eth_device* dev, bd_t *bis, int dev_num);
+static int pcnet_init (struct eth_device *dev, bd_t * bis);
+static int pcnet_send (struct eth_device *dev, volatile void *packet,
+		       int length);
+static int pcnet_recv (struct eth_device *dev);
+static void pcnet_halt (struct eth_device *dev);
+static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
 
 #define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a))
 #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))
 
 static struct pci_device_id supported[] = {
-	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE },
-	{ }
+	{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
+	{}
 };
 
 
-int pcnet_initialize(bd_t *bis)
+int pcnet_initialize (bd_t * bis)
 {
+<<<<<<< HEAD:drivers/net/pcnet.c
+	pci_dev_t devbusfn;
+	struct eth_device *dev;
+	u16 command, status;
+	int dev_nr = 0;
+
+	PCNET_DEBUG1 ("\npcnet_initialize...\n");
+
+	for (dev_nr = 0;; dev_nr++) {
+
+		/*
+		 * Find the PCnet PCI device(s).
+		 */
+		if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) {
+			break;
+		}
+
+		/*
+		 * Allocate and pre-fill the device structure.
+		 */
+		dev = (struct eth_device *) malloc (sizeof *dev);
+		dev->priv = (void *) devbusfn;
+		sprintf (dev->name, "pcnet#%d", dev_nr);
+
+		/*
+		 * Setup the PCI device.
+		 */
+		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
+				       (unsigned int *) &dev->iobase);
+		dev->iobase=pci_io_to_phys (devbusfn, dev->iobase);
+		dev->iobase &= ~0xf;
+
+		PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ",
+			      dev->name, devbusfn, dev->iobase);
+
+		command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
+		pci_write_config_word (devbusfn, PCI_COMMAND, command);
+		pci_read_config_word (devbusfn, PCI_COMMAND, &status);
+		if ((status & command) != command) {
+			printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name);
+			free (dev);
+			continue;
+		}
+
+		pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40);
+
+		/*
+		 * Probe the PCnet chip.
+		 */
+		if (pcnet_probe (dev, bis, dev_nr) < 0) {
+			free (dev);
+			continue;
+		}
+
+		/*
+		 * Setup device structure and register the driver.
+		 */
+		dev->init = pcnet_init;
+		dev->halt = pcnet_halt;
+		dev->send = pcnet_send;
+		dev->recv = pcnet_recv;
+
+		eth_register (dev);
+=======
     pci_dev_t devbusfn;
     struct eth_device* dev;
     u16 command, status;
@@ -196,6 +260,7 @@
 	 * Setup the PCI device.
 	 */
 	pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (unsigned int *)&dev->iobase);
+	dev->iobase=pci_io_to_phys(devbusfn,dev->iobase);
 	dev->iobase &= ~0xf;
 
 	PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
@@ -219,308 +284,311 @@
 	if (pcnet_probe(dev, bis, dev_nr) < 0) {
 	    free(dev);
 	    continue;
+>>>>>>> Fixed pcnet io_base:drivers/net/pcnet.c
 	}
 
-	/*
-	 * Setup device structure and register the driver.
-	 */
-	dev->init   = pcnet_init;
-	dev->halt   = pcnet_halt;
-	dev->send   = pcnet_send;
-	dev->recv   = pcnet_recv;
-
-	eth_register(dev);
-    }
+	udelay (10 * 1000);
 
-    udelay(10 * 1000);
-
-    return dev_nr;
+	return dev_nr;
 }
 
-static int pcnet_probe(struct eth_device* dev, bd_t *bis, int dev_nr)
+static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr)
 {
-    int chip_version;
-    char *chipname;
+	int chip_version;
+	char *chipname;
+
 #ifdef PCNET_HAS_PROM
-    int i;
+	int i;
 #endif
 
-    /* Reset the PCnet controller */
-    pcnet_reset(dev);
+	/* Reset the PCnet controller */
+	pcnet_reset (dev);
 
-    /* Check if register access is working */
-    if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
-	printf("%s: CSR register access check failed\n", dev->name);
-	return -1;
-    }
+	/* Check if register access is working */
+	if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) {
+		printf ("%s: CSR register access check failed\n", dev->name);
+		return -1;
+	}
 
-    /* Identify the chip */
-    chip_version = pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev,89) << 16);
-    if ((chip_version & 0xfff) != 0x003)
-       return -1;
-    chip_version = (chip_version >> 12) & 0xffff;
-    switch (chip_version) {
+	/* Identify the chip */
+	chip_version =
+		pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16);
+	if ((chip_version & 0xfff) != 0x003)
+		return -1;
+	chip_version = (chip_version >> 12) & 0xffff;
+	switch (chip_version) {
+	case 0x2621:
+		chipname = "PCnet/PCI II 79C970A";	/* PCI */
+		break;
 #ifdef CONFIG_PCNET_79C973
-    case 0x2625:
-	chipname = "PCnet/FAST III 79C973"; /* PCI */
-	break;
+	case 0x2625:
+		chipname = "PCnet/FAST III 79C973";	/* PCI */
+		break;
 #endif
 #ifdef CONFIG_PCNET_79C975
-    case 0x2627:
-	chipname = "PCnet/FAST III 79C975"; /* PCI */
-	break;
+	case 0x2627:
+		chipname = "PCnet/FAST III 79C975";	/* PCI */
+		break;
 #endif
-    default:
-	printf("%s: PCnet version %#x not supported\n",
-	       dev->name, chip_version);
-	return -1;
-    }
+	default:
+		printf ("%s: PCnet version %#x not supported\n",
+			dev->name, chip_version);
+		return -1;
+	}
 
-    PCNET_DEBUG1("AMD %s\n", chipname);
+	PCNET_DEBUG1 ("AMD %s\n", chipname);
 
 #ifdef PCNET_HAS_PROM
-    /*
-     * In most chips, after a chip reset, the ethernet address is read from
-     * the station address PROM at the base address and programmed into the
-     * "Physical Address Registers" CSR12-14.
-     */
-    for (i = 0; i < 3; i++) {
-	unsigned int val;
-	val = pcnet_read_csr(dev, i+12) & 0x0ffff;
-	/* There may be endianness issues here. */
-	dev->enetaddr[2*i  ] =  val       & 0x0ff;
-	dev->enetaddr[2*i+1] = (val >> 8) & 0x0ff;
-    }
+	/*
+	 * In most chips, after a chip reset, the ethernet address is read from
+	 * the station address PROM at the base address and programmed into the
+	 * "Physical Address Registers" CSR12-14.
+	 */
+	for (i = 0; i < 3; i++) {
+		unsigned int val;
+
+		val = pcnet_read_csr (dev, i + 12) & 0x0ffff;
+		/* There may be endianness issues here. */
+		dev->enetaddr[2 * i] = val & 0x0ff;
+		dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
+	}
 #endif /* PCNET_HAS_PROM */
 
-    return 0;
+	return 0;
 }
 
-static int pcnet_init(struct eth_device* dev, bd_t *bis)
+static int pcnet_init (struct eth_device *dev, bd_t * bis)
 {
-    int i, val;
-    u32 addr;
+	int i, val;
+	u32 addr;
 
-    PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
+	PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name);
 
-    /* Switch pcnet to 32bit mode */
-    pcnet_write_bcr (dev, 20, 2);
+	/* Switch pcnet to 32bit mode */
+	pcnet_write_bcr (dev, 20, 2);
 
 #ifdef CONFIG_PN62
-    /* Setup LED registers */
-    val = pcnet_read_bcr (dev, 2) | 0x1000;
-    pcnet_write_bcr (dev, 2, val);    /* enable LEDPE */
-    pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */
-    pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */
-    pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */
-    pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */
+	/* Setup LED registers */
+	val = pcnet_read_bcr (dev, 2) | 0x1000;
+	pcnet_write_bcr (dev, 2, val);	/* enable LEDPE */
+	pcnet_write_bcr (dev, 4, 0x5080);	/* 100MBit */
+	pcnet_write_bcr (dev, 5, 0x40c0);	/* LNKSE */
+	pcnet_write_bcr (dev, 6, 0x4090);	/* TX Activity */
+	pcnet_write_bcr (dev, 7, 0x4084);	/* RX Activity */
 #endif
 
-    /* Set/reset autoselect bit */
-    val = pcnet_read_bcr (dev, 2) & ~2;
-    val |= 2;
-    pcnet_write_bcr (dev, 2, val);
+	/* Set/reset autoselect bit */
+	val = pcnet_read_bcr (dev, 2) & ~2;
+	val |= 2;
+	pcnet_write_bcr (dev, 2, val);
 
-    /* Enable auto negotiate, setup, disable fd */
-    val = pcnet_read_bcr(dev, 32) & ~0x98;
-    val |= 0x20;
-    pcnet_write_bcr(dev, 32, val);
+	/* Enable auto negotiate, setup, disable fd */
+	val = pcnet_read_bcr (dev, 32) & ~0x98;
+	val |= 0x20;
+	pcnet_write_bcr (dev, 32, val);
 
-    /*
-     * We only maintain one structure because the drivers will never
-     * be used concurrently. In 32bit mode the RX and TX ring entries
-     * must be aligned on 16-byte boundaries.
-     */
-    if (lp == NULL) {
-	addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10);
-	addr = (addr + 0xf) & ~0xf;
-	lp = (pcnet_priv_t *)addr;
-    }
+	/*
+	 * We only maintain one structure because the drivers will never
+	 * be used concurrently. In 32bit mode the RX and TX ring entries
+	 * must be aligned on 16-byte boundaries.
+	 */
+	if (lp == NULL) {
+		addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10);
+		addr = (addr + 0xf) & ~0xf;
+		lp = (pcnet_priv_t *) addr;
+	}
 
-    lp->init_block.mode = cpu_to_le16(0x0000);
-    lp->init_block.filter[0] = 0x00000000;
-    lp->init_block.filter[1] = 0x00000000;
+	lp->init_block.mode = cpu_to_le16 (0x0000);
+	lp->init_block.filter[0] = 0x00000000;
+	lp->init_block.filter[1] = 0x00000000;
 
-    /*
-     * Initialize the Rx ring.
-     */
-    lp->cur_rx = 0;
-    for (i = 0; i < RX_RING_SIZE; i++) {
-	lp->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]);
-	lp->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
-	lp->rx_ring[i].status = cpu_to_le16(0x8000);
-	PCNET_DEBUG1("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n",
-	       i, lp->rx_ring[i].base, lp->rx_ring[i].buf_length,
-	       lp->rx_ring[i].status);
-    }
+	/*
+	 * Initialize the Rx ring.
+	 */
+	lp->cur_rx = 0;
+	for (i = 0; i < RX_RING_SIZE; i++) {
+		lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]);
+		lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ);
+		lp->rx_ring[i].status = cpu_to_le16 (0x8000);
+		PCNET_DEBUG1
+			("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
+			 lp->rx_ring[i].base, lp->rx_ring[i].buf_length,
+			 lp->rx_ring[i].status);
+	}
 
-    /*
-     * Initialize the Tx ring. The Tx buffer address is filled in as
-     * needed, but we do need to clear the upper ownership bit.
-     */
-    lp->cur_tx = 0;
-    for (i = 0; i < TX_RING_SIZE; i++) {
-	lp->tx_ring[i].base = 0;
-	lp->tx_ring[i].status = 0;
-    }
+	/*
+	 * Initialize the Tx ring. The Tx buffer address is filled in as
+	 * needed, but we do need to clear the upper ownership bit.
+	 */
+	lp->cur_tx = 0;
+	for (i = 0; i < TX_RING_SIZE; i++) {
+		lp->tx_ring[i].base = 0;
+		lp->tx_ring[i].status = 0;
+	}
 
-    /*
-     * Setup Init Block.
-     */
-    PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->init_block);
+	/*
+	 * Setup Init Block.
+	 */
+	PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block);
 
-    for (i = 0; i < 6; i++) {
-	lp->init_block.phys_addr[i] = dev->enetaddr[i];
-	PCNET_DEBUG1(" %02x", lp->init_block.phys_addr[i]);
-    }
+	for (i = 0; i < 6; i++) {
+		lp->init_block.phys_addr[i] = dev->enetaddr[i];
+		PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]);
+	}
 
-    lp->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
-					   RX_RING_LEN_BITS);
-    lp->init_block.rx_ring = PCI_TO_MEM_LE(dev, lp->rx_ring);
-    lp->init_block.tx_ring = PCI_TO_MEM_LE(dev, lp->tx_ring);
+	lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS |
+						RX_RING_LEN_BITS);
+	lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring);
+	lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring);
 
-    PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
-	   lp->init_block.tlen_rlen,
-	   lp->init_block.rx_ring, lp->init_block.tx_ring);
+	PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
+		      lp->init_block.tlen_rlen,
+		      lp->init_block.rx_ring, lp->init_block.tx_ring);
 
-    /*
-     * Tell the controller where the Init Block is located.
-     */
-    addr = PCI_TO_MEM(dev, &lp->init_block);
-    pcnet_write_csr(dev, 1, addr & 0xffff);
-    pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
+	/*
+	 * Tell the controller where the Init Block is located.
+	 */
+	addr = PCI_TO_MEM (dev, &lp->init_block);
+	pcnet_write_csr (dev, 1, addr & 0xffff);
+	pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff);
 
-    pcnet_write_csr (dev, 4, 0x0915);
-    pcnet_write_csr (dev, 0, 0x0001); /* start */
+	pcnet_write_csr (dev, 4, 0x0915);
+	pcnet_write_csr (dev, 0, 0x0001);	/* start */
 
-    /* Wait for Init Done bit */
-    for (i = 10000; i > 0; i--) {
-	if (pcnet_read_csr (dev, 0) & 0x0100)
-	    break;
-	udelay(10);
-    }
-    if (i <= 0) {
-	printf("%s: TIMEOUT: controller init failed\n", dev->name);
-	pcnet_reset (dev);
-	return -1;
-    }
+	/* Wait for Init Done bit */
+	for (i = 10000; i > 0; i--) {
+		if (pcnet_read_csr (dev, 0) & 0x0100)
+			break;
+		udelay (10);
+	}
+	if (i <= 0) {
+		printf ("%s: TIMEOUT: controller init failed\n", dev->name);
+		pcnet_reset (dev);
+		return -1;
+	}
 
-    /*
-     * Finally start network controller operation.
-     */
-    pcnet_write_csr (dev, 0, 0x0002);
+	/*
+	 * Finally start network controller operation.
+	 */
+	pcnet_write_csr (dev, 0, 0x0002);
 
-    return 0;
+	return 0;
 }
 
-static int pcnet_send(struct eth_device* dev, volatile void *packet, int pkt_len)
+static int pcnet_send (struct eth_device *dev, volatile void *packet,
+		       int pkt_len)
 {
-    int i, status;
-    struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx];
+	int i, status;
+	struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx];
 
-    PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, packet);
+	PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
+		      packet);
 
-    /* Wait for completion by testing the OWN bit */
-    for (i = 1000; i > 0; i--) {
-	status = le16_to_cpu(entry->status);
-	if ((status & 0x8000) == 0)
-	    break;
-	udelay(100);
-	PCNET_DEBUG2(".");
-    }
-    if (i <= 0) {
-	printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
-	       dev->name, lp->cur_tx, status);
-	pkt_len = 0;
-	goto failure;
-    }
+	/* Wait for completion by testing the OWN bit */
+	for (i = 1000; i > 0; i--) {
+		status = le16_to_cpu (entry->status);
+		if ((status & 0x8000) == 0)
+			break;
+		udelay (100);
+		PCNET_DEBUG2 (".");
+	}
+	if (i <= 0) {
+		printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
+			dev->name, lp->cur_tx, status);
+		pkt_len = 0;
+		goto failure;
+	}
 
-    /*
-     * Setup Tx ring. Caution: the write order is important here,
-     * set the status with the "ownership" bits last.
-     */
-    status = 0x8300;
-    entry->length = le16_to_cpu(-pkt_len);
-    entry->misc   = 0x00000000;
-    entry->base   = PCI_TO_MEM_LE(dev, packet);
-    entry->status = le16_to_cpu(status);
+	/*
+	 * Setup Tx ring. Caution: the write order is important here,
+	 * set the status with the "ownership" bits last.
+	 */
+	status = 0x8300;
+	entry->length = le16_to_cpu (-pkt_len);
+	entry->misc = 0x00000000;
+	entry->base = PCI_TO_MEM_LE (dev, packet);
+	entry->status = le16_to_cpu (status);
 
-    /* Trigger an immediate send poll. */
-    pcnet_write_csr (dev, 0, 0x0008);
+	/* Trigger an immediate send poll. */
+	pcnet_write_csr (dev, 0, 0x0008);
 
- failure:
-    if (++lp->cur_tx >= TX_RING_SIZE)
-	lp->cur_tx = 0;
+      failure:
+	if (++lp->cur_tx >= TX_RING_SIZE)
+		lp->cur_tx = 0;
 
-    PCNET_DEBUG2("done\n");
-    return pkt_len;
+	PCNET_DEBUG2 ("done\n");
+	return pkt_len;
 }
 
-static int pcnet_recv(struct eth_device* dev)
+static int pcnet_recv (struct eth_device *dev)
 {
-    struct pcnet_rx_head *entry;
-    int pkt_len = 0;
-    u16 status;
+	struct pcnet_rx_head *entry;
+	int pkt_len = 0;
+	u16 status;
 
-    while (1) {
-	entry = &lp->rx_ring[lp->cur_rx];
-	/*
-	 * If we own the next entry, it's a new packet. Send it up.
-	 */
-	if (((status = le16_to_cpu(entry->status)) & 0x8000) != 0) {
-	    break;
-	}
-	status >>= 8;
+	while (1) {
+		entry = &lp->rx_ring[lp->cur_rx];
+		/*
+		 * If we own the next entry, it's a new packet. Send it up.
+		 */
+		if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) {
+			break;
+		}
+		status >>= 8;
 
-	if (status != 0x03) {	/* There was an error. */
+		if (status != 0x03) {	/* There was an error. */
 
-	    printf("%s: Rx%d", dev->name, lp->cur_rx);
-	    PCNET_DEBUG1(" (status=0x%x)", status);
-	    if (status & 0x20) printf(" Frame");
-	    if (status & 0x10) printf(" Overflow");
-	    if (status & 0x08) printf(" CRC");
-	    if (status & 0x04) printf(" Fifo");
-	    printf(" Error\n");
-	    entry->status &= le16_to_cpu(0x03ff);
+			printf ("%s: Rx%d", dev->name, lp->cur_rx);
+			PCNET_DEBUG1 (" (status=0x%x)", status);
+			if (status & 0x20)
+				printf (" Frame");
+			if (status & 0x10)
+				printf (" Overflow");
+			if (status & 0x08)
+				printf (" CRC");
+			if (status & 0x04)
+				printf (" Fifo");
+			printf (" Error\n");
+			entry->status &= le16_to_cpu (0x03ff);
 
-	} else {
+		} else {
 
-	    pkt_len = (le32_to_cpu(entry->msg_length) & 0xfff) - 4;
-	    if (pkt_len < 60) {
-		printf("%s: Rx%d: invalid packet length %d\n",
-		       dev->name, lp->cur_rx, pkt_len);
-	    } else {
-		NetReceive(lp->rx_buf[lp->cur_rx], pkt_len);
-		PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
-		       lp->cur_rx, pkt_len, lp->rx_buf[lp->cur_rx]);
-	    }
-	}
-	entry->status |= cpu_to_le16(0x8000);
+			pkt_len =
+				(le32_to_cpu (entry->msg_length) & 0xfff) - 4;
+			if (pkt_len < 60) {
+				printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len);
+			} else {
+				NetReceive (lp->rx_buf[lp->cur_rx], pkt_len);
+				PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n",
+					      lp->cur_rx, pkt_len,
+					      lp->rx_buf[lp->cur_rx]);
+			}
+		}
+		entry->status |= cpu_to_le16 (0x8000);
 
-	if (++lp->cur_rx >= RX_RING_SIZE)
-	    lp->cur_rx = 0;
-    }
-    return pkt_len;
+		if (++lp->cur_rx >= RX_RING_SIZE)
+			lp->cur_rx = 0;
+	}
+	return pkt_len;
 }
 
-static void pcnet_halt(struct eth_device* dev)
+static void pcnet_halt (struct eth_device *dev)
 {
-    int i;
+	int i;
 
-    PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
+	PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name);
 
-    /* Reset the PCnet controller */
-    pcnet_reset (dev);
+	/* Reset the PCnet controller */
+	pcnet_reset (dev);
 
-    /* Wait for Stop bit */
-    for (i = 1000; i > 0; i--) {
-	if (pcnet_read_csr (dev, 0) & 0x4)
-	    break;
-	udelay(10);
-    }
-    if (i <= 0) {
-	printf("%s: TIMEOUT: controller reset failed\n", dev->name);
-    }
+	/* Wait for Stop bit */
+	for (i = 1000; i > 0; i--) {
+		if (pcnet_read_csr (dev, 0) & 0x4)
+			break;
+		udelay (10);
+	}
+	if (i <= 0) {
+		printf ("%s: TIMEOUT: controller reset failed\n", dev->name);
+	}
 }
-
 #endif
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 68e45e1..7dc33be 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -182,7 +182,8 @@
 
 	/* Clear all error indications */
 
-	pci->pme_msg_det = 0xffffffff;
+	if (bridge)
+		pci->pme_msg_det = 0xffffffff;
 	pci->pedr = 0xffffffff;
 
 	pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
diff --git a/drivers/usb/usb_ohci.c b/drivers/usb/usb_ohci.c
index 5c201b3..ee0f2e4 100644
--- a/drivers/usb/usb_ohci.c
+++ b/drivers/usb/usb_ohci.c
@@ -86,11 +86,11 @@
  * e.g. PCI controllers need this
  */
 #ifdef CFG_OHCI_SWAP_REG_ACCESS
-# define readl(a) __swap_32(*((vu_long *)(a)))
-# define writel(a, b) (*((vu_long *)(b)) = __swap_32((vu_long)a))
+# define readl(a) __swap_32(*((volatile u32 *)(a)))
+# define writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a))
 #else
-# define readl(a) (*((vu_long *)(a)))
-# define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
+# define readl(a) (*((volatile u32 *)(a)))
+# define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
 #endif /* CFG_OHCI_SWAP_REG_ACCESS */
 
 #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
@@ -138,28 +138,14 @@
 /* device which was disconnected */
 struct usb_device *devgone;
 
-/*-------------------------------------------------------------------------*/
-
-/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
- * The erratum (#4) description is incorrect.  AMD's workaround waits
- * till some bits (mostly reserved) are clear; ok for all revs.
- */
-#define OHCI_QUIRK_AMD756 0xabcd
-#define read_roothub(hc, register, mask) ({ \
-	u32 temp = readl (&hc->regs->roothub.register); \
-	if (hc->flags & OHCI_QUIRK_AMD756) \
-		while (temp & mask) \
-			temp = readl (&hc->regs->roothub.register); \
-	temp; })
-
-static u32 roothub_a (struct ohci *hc)
-	{ return read_roothub (hc, a, 0xfc0fe000); }
+static inline u32 roothub_a (struct ohci *hc)
+	{ return readl (&hc->regs->roothub.a); }
 static inline u32 roothub_b (struct ohci *hc)
 	{ return readl (&hc->regs->roothub.b); }
 static inline u32 roothub_status (struct ohci *hc)
 	{ return readl (&hc->regs->roothub.status); }
-static u32 roothub_portstatus (struct ohci *hc, int i)
-	{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }
+static inline u32 roothub_portstatus (struct ohci *hc, int i)
+	{ return readl (&hc->regs->roothub.portstatus[i]); }
 
 /* forward declaration */
 static int hc_interrupt (void);
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 4f73067..68b9861 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -849,6 +849,7 @@
 		if (!((bmp->header.signature[0] == 'B') &&
 		      (bmp->header.signature[1] == 'M'))) {
 			printf ("Error: no valid bmp.gz image at %lx\n", bmp_image);
+			free(dst);
 			return 1;
 		}
 #else
@@ -869,6 +870,10 @@
 	if (compression != BMP_BI_RGB) {
 		printf ("Error: compression type %ld not supported\n",
 			compression);
+#ifdef CONFIG_VIDEO_BMP_GZIP
+		if (dst)
+			free(dst);
+#endif
 		return 1;
 	}
 
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 9ccf7d6..202c844 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -155,6 +155,9 @@
 #if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
 	unsigned long kbd_status;
 #endif
+#if defined(CONFIG_WD_MAX_RATE)
+	unsigned long long wdt_last;	/* trace watch-dog triggering rate */
+#endif
 	void		**jt;		/* jump table */
 } gd_t;
 
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 01cb2d7..dc6e278 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1570,7 +1570,9 @@
 #define MPC85xx_PORDEVSR_RIO_CTLS 	0x00000008
 #define MPC85xx_PORDEVSR_RIO_DEV_ID	0x00000007
 	uint	pordbgmsr;	/* 0xe0010 - POR debug mode status register */
-	char	res1[12];
+	uint	pordevsr2;	/* 0xe0014 - POR I/O device status regsiter 2 */
+#define MPC85xx_PORDEVSR2_SEC_CFG	0x00000020
+	char	res1[8];
 	uint	gpporcr;	/* 0xe0020 - General-purpose POR configuration register */
 	char	res2[12];
 	uint	gpiocr;		/* 0xe0030 - GPIO control register */
diff --git a/include/common.h b/include/common.h
index 8630780..f12e3bd 100644
--- a/include/common.h
+++ b/include/common.h
@@ -604,8 +604,9 @@
 int	vsprintf(char *buf, const char *fmt, va_list args);
 
 /* lib_generic/crc32.c */
-ulong crc32 (ulong, const unsigned char *, uint);
-ulong crc32_no_comp (ulong, const unsigned char *, uint);
+uint32_t crc32 (uint32_t, const unsigned char *, uint);
+uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint);
+uint32_t crc32_no_comp (uint32_t, const unsigned char *, uint);
 
 /* common/console.c */
 int	console_init_f(void);	/* Before relocation; uses the serial  stuff	*/
@@ -661,7 +662,7 @@
 /*
  * Board-specific Platform code can reimplement show_boot_progress () if needed
  */
-void inline show_boot_progress (int val);
+void __attribute__((weak)) show_boot_progress (int val);
 
 #ifdef CONFIG_INIT_CRITICAL
 #error CONFIG_INIT_CRITICAL is deprecated!
@@ -670,6 +671,9 @@
 
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 
+#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
+#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
+
 /* Multicore arch functions */
 #ifdef CONFIG_MP
 int cpu_status(int nr);
@@ -677,4 +681,8 @@
 int cpu_release(int nr, int argc, char *argv[]);
 #endif
 
+#ifdef CONFIG_POST
+#define CONFIG_HAS_POST
+#endif
+
 #endif	/* __COMMON_H_ */
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index c147424..81e7c1e 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007 DENX Software Engineering
+ * (C) Copyright 2007, 2008 DENX Software Engineering
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -413,7 +413,7 @@
 	"addtty=setenv bootargs ${bootargs} "				\
 		"console=${consdev},${baudrate}\0"			\
 	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"		\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
 	"flash_self=run ramargs addip addtty;"				\
 		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
 	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
@@ -422,10 +422,10 @@
 		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
 	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
 		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
-		"tftp ${fdt_addr_r} ${fdtfile};"				\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
 		"run ramargs addip addtty;"				\
 		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
-	"load=tftp ${u-boot_addr_r} ${u-boot}\0"				\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
 	"update=protect off ${u-boot_addr} +${filesize};"		\
 		"era ${u-boot_addr} +${filesize};"			\
 		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 605eb40..5e97cfa 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -28,6 +28,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/mx31-regs.h>
+
  /* High Level Configuration Options */
 #define CONFIG_ARM1136		1    /* This is an arm1136 CPU core */
 #define CONFIG_MX31		1    /* in a mx31 */
@@ -91,7 +93,7 @@
 
 
 #define CONFIG_DRIVER_SMC911X		1
-#define CONFIG_DRIVER_SMC911X_BASE	0xb4020000
+#define CONFIG_DRIVER_SMC911X_BASE	(CS4_BASE + 0x00020000)
 #define CONFIG_DRIVER_SMC911X_32_BIT	1
 
 /*
@@ -127,18 +129,18 @@
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS	1
-#define PHYS_SDRAM_1		0x80000000
+#define PHYS_SDRAM_1		CSD0_BASE
 #define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_FLASH_BASE		0xa0000000
+#define CFG_FLASH_BASE		CS0_BASE
 #define CFG_MAX_FLASH_BANKS	1           /* max number of memory banks */
 #define CFG_MAX_FLASH_SECT	128	     /* max number of sectors on one chip */
 #define CFG_MONITOR_BASE	CFG_FLASH_BASE /* Monitor at beginning of flash */
 
-#define CFG_ENV_ADDR		0xa01f0000
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x001f0000)
 #define	CFG_ENV_IS_IN_FLASH	1
 #define CFG_ENV_SECT_SIZE	(64 * 1024)
 #define CFG_ENV_SIZE		(64 * 1024)
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 36adf66..690584a 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -75,8 +75,8 @@
 /*
  * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
  * the POST_WORD from OCM to a 440EPx register that preserves it's
- * content during reset (GPT0_COM6). This way we reserve the OCM (16k)
- * for logbuffer only.
+ * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
+ * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
  */
 #define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
@@ -91,9 +91,9 @@
 
 /* Additional registers for watchdog timer post test */
 
-#define CFG_DSPIC_TEST_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP5)
-#define CFG_WATCHDOG_TIME_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP4)
-#define CFG_WATCHDOG_FLAGS_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP5)
+#define CFG_DSPIC_TEST_ADDR	(CFG_PERIPHERAL_BASE + GPT0_MASK1)
+#define CFG_WATCHDOG_TIME_ADDR	(CFG_PERIPHERAL_BASE + GPT0_MASK2)
+#define CFG_WATCHDOG_FLAGS_ADDR	(CFG_PERIPHERAL_BASE + GPT0_MASK1)
 #define CFG_WATCHDOG_MAGIC	0x12480000
 #define CFG_WATCHDOG_MAGIC_MASK	0xFFFF0000
 #define CFG_DSPIC_TEST_MASK	0x00000001
@@ -242,6 +242,7 @@
 
 #define CFG_POST_CACHE_ADDR	0x7fff0000 /* free virtual address	*/
 #define CONFIG_LOGBUFFER
+/* Reserve GPT0_COMP1-COMP5 for logbuffer header */
 #define CONFIG_ALT_LH_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP1)
 #define CONFIG_ALT_LB_ADDR	(CFG_OCM_BASE)
 #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
@@ -452,6 +453,7 @@
 
 #define CONFIG_HW_WATCHDOG	1	/* Use external HW-Watchdog	*/
 #define CONFIG_WD_PERIOD	40000	/* in usec */
+#define CONFIG_WD_MAX_RATE	66600	/* in ticks */
 
 /*
  * For booting Linux, the board info and command line data
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index a394b4b..a9c86f9 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2008
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -155,8 +155,8 @@
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
 	"addcons=setenv bootargs ${bootargs} "				\
-		"console=${console},${baudrate} "		\
-		"ubootver=${ubootver} board=${board}\0"	\
+		"console=${console},${baudrate} "			\
+		"ubootver=${ubootver} board=${board}\0"			\
 	"flash_nfs=run nfsargs addip addcons;"				\
 		"bootm ${kernel_addr}\0"				\
 	"flash_self=run ramargs addip addcons;"				\
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index 78e2545..5286e1f 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -51,7 +51,7 @@
  * Size of malloc() pool
  */
 #define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
-#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -60,6 +60,12 @@
 #define CONFIG_MX31_UART	1
 #define CFG_MX31_UART1		1
 
+#define CONFIG_HARD_SPI		1
+#define CONFIG_MXC_SPI		1
+#define CONFIG_MXC_SPI_IFACE	1	/* Default SPI interface number */
+
+#define CONFIG_RTC_MC13783	1
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX	1
@@ -73,20 +79,33 @@
 #include <config_cmd_default.h>
 
 #define CONFIG_CMD_PING
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_DATE
 
 #define CONFIG_BOOTDELAY	3
 
 #define CONFIG_NETMASK		255.255.255.0
 #define CONFIG_IPADDR		192.168.23.168
 #define CONFIG_SERVERIP		192.168.23.2
+#define CONFIG_LOADADDR		(CSD0_BASE + 0x800000)	/* loadaddr env var */
 
-#define	CONFIG_EXTRA_ENV_SETTINGS											\
-	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"							\
-	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
-	"bootcmd=run bootcmd_net\0"											\
-	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0"		\
-	"prg_uboot=tftpboot 0x80000000 u-boot-mx31ads.bin; protect off 0xa0000000 0xa001ffff; erase 0xa0000000 0xa001ffff; cp.b 0x80000000 0xa0000000 $(filesize)\0"
-
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"uboot_addr=0xa0000000\0"					\
+	"uboot=mx31ads/u-boot.bin\0"					\
+	"kernel=mx31ads/uImage\0"					\
+	"nfsroot=/opt/eldk/arm\0"					\
+	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"	\
+	"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "	\
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"	\
+	"bootcmd=run bootcmd_net\0"					\
+	"bootcmd_net=run bootargs_base bootargs_nfs; "			\
+		"tftpboot ${loadaddr} ${kernel}; bootm\0"		\
+	"prg_uboot=tftpboot ${loadaddr} ${uboot}; "			\
+		"protect off ${uboot_addr} 0xa003ffff; "		\
+		"erase ${uboot_addr} 0xa003ffff; "			\
+		"cp.b ${loadaddr} ${uboot_addr} ${filesize}; "		\
+		"setenv filesize; saveenv\0"
 
 #define CONFIG_DRIVER_CS8900	1
 #define CS8900_BASE		0xb4020300
@@ -120,7 +139,7 @@
 
 #undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR		CSD0_BASE	/* default load address */
+#define CFG_LOAD_ADDR		CONFIG_LOADADDR
 
 #define CFG_HZ			32000
 
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index ed41b2f..ac72f98 100644
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -173,7 +173,7 @@
 	"upd=run load update\0"						\
 	"ipaddr=10.0.0.233\0"						\
 	"serverip=10.0.0.152\0"						\
-	"netmask=255.255.0.0\0"					\
+	"netmask=255.255.0.0\0"						\
 	"ethaddr=c6:6f:13:36:f3:81\0"					\
 	"eth1addr=c6:6f:13:36:f3:82\0"					\
 	"mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env),"		\
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index e164019..d6bcc8e 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -22,31 +22,31 @@
  */
 
 /*
- * This file contains the configuration parameters for the dbau1x00 board.
+ * This file contains the configuration parameters for qemu-mips target.
  */
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
-#define CONFIG_QEMU_MIPS        1
+#define CONFIG_MIPS32		1	/* MIPS32 CPU core */
+#define CONFIG_QEMU_MIPS	1
 #define CONFIG_MISC_INIT_R
 
 /*IP address is default used by Qemu*/
-#define CONFIG_IPADDR		10.0.2.15    	     /* Our IP address */
-#define CONFIG_SERVERIP		10.0.2.2	     /* Server IP address*/
+#define CONFIG_IPADDR		10.0.2.15	/* Our IP address */
+#define CONFIG_SERVERIP		10.0.2.2	/* Server IP address */
 
-#define CONFIG_BOOTDELAY	10	/* autoboot after 10 seconds	*/
+#define CONFIG_BOOTDELAY	10	/* autoboot after 10 seconds */
 
 #define CONFIG_BAUDRATE		115200
 
 /* valid baudrates */
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-#undef	CONFIG_BOOTARGS
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+#undef CONFIG_BOOTARGS
 
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
+#define CONFIG_EXTRA_ENV_SETTINGS					\
 	"addmisc=setenv bootargs ${bootargs} "				\
 		"console=ttyS0,${baudrate} "				\
 		"panic=1\0"						\
@@ -56,7 +56,6 @@
 
 #define CONFIG_BOOTCOMMAND	"bootp;bootelf"
 
-
 /*
  * BOOTP options
  */
@@ -65,7 +64,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -74,27 +72,24 @@
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_EXT2
-#undef  CONFIG_CMD_IMLS
-#undef  CONFIG_CMD_FLASH
-#undef  CONFIG_CMD_LOADB
-#undef  CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
 #define CONFIG_CMD_DHCP
 
 #define CONFIG_DRIVER_NE2000
 #define CONFIG_DRIVER_NE2000_BASE	(0xb4000300)
 
-#define CFG_NO_FLASH
 #define CFG_NS16550
 #define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
-#define CFG_NS16550_CLK         115200
-#define CFG_NS16550_COM1        (0xb40003f8)
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		115200
+#define CFG_NS16550_COM1	(0xb40003f8)
 #define CONFIG_CONS_INDEX	1
 
 #define CONFIG_CMD_IDE
 #define CONFIG_DOS_PARTITION
 
-#define CFG_IDE_MAXBUS	2
+#define CFG_IDE_MAXBUS		2
 #define CFG_ATA_IDE0_OFFSET	(0x1f0)
 #define CFG_ATA_IDE1_OFFSET	(0x170)
 #define CFG_ATA_DATA_OFFSET	(0)
@@ -106,18 +101,18 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory      */
+#define CFG_LONGHELP				/* undef to save memory */
 
-#define	CFG_PROMPT		"qemu-mips # "	/* Monitor Command Prompt    */
+#define CFG_PROMPT		"qemu-mips # "	/* Monitor Command Prompt */
 
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
 #define CFG_HUSH_PARSER
 #define CFG_PROMPT_HUSH_PS2	"> "
 
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args */
 
 #define CFG_MALLOC_LEN		128*1024
 
@@ -125,11 +120,11 @@
 
 #define CFG_MHZ			132
 
-#define CFG_HZ                  (CFG_MHZ * 1000000)
+#define CFG_HZ			(CFG_MHZ * 1000000)
 
-#define CFG_SDRAM_BASE		0x80000000     /* Cached addr */
+#define CFG_SDRAM_BASE		0x80000000	/* Cached addr */
 
-#define	CFG_LOAD_ADDR		0x81000000     /* default load address	*/
+#define CFG_LOAD_ADDR		0x81000000	/* default load address */
 
 #define CFG_MEMTEST_START	0x80100000
 #define CFG_MEMTEST_END		0x80800000
@@ -139,21 +134,30 @@
  */
 
 /* The following #defines are needed to get flash environment right */
-#define	CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(192 << 10)
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(192 << 10)
 
 #define CFG_INIT_SP_OFFSET	0x400000
 
 /* We boot from this flash, selected with dip switch */
 #define CFG_FLASH_BASE		0xbfc00000
+#define CFG_MAX_FLASH_BANKS	1
+#define CFG_MAX_FLASH_SECT	128
+#define CFG_FLASH_CFI		1	/* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER	1
+#define CFG_FLASH_USE_BUFFER_WRITE	1
 
-#define	CFG_ENV_IS_NOWHERE	1
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x40000)
 
-/* Address and size of Primary Environment Sector	*/
-#define CFG_ENV_SIZE		0x10000
+/* Address and size of Primary Environment Sector */
+#define CFG_ENV_SIZE		0x8000
+
+#define CONFIG_ENV_OVERWRITE	1
+
 #undef CONFIG_NET_MULTI
 
-#define MEM_SIZE 128
+#define MEM_SIZE		128
 
 #undef CONFIG_MEMSIZE_IN_BYTES
 
@@ -164,4 +168,4 @@
 #define CFG_ICACHE_SIZE		16384
 #define CFG_CACHELINE_SIZE	32
 
-#endif	/* __CONFIG_H */
+#endif /* __CONFIG_H */
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index d00c22f..133cbcf 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -671,7 +671,7 @@
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
-	"hostname=sbc8349\0"					\
+	"hostname=sbc8349\0"						\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
@@ -690,7 +690,7 @@
 		"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0"	\
 	"upd=run load update\0"						\
 	"fdtaddr=400000\0"						\
-	"fdtfile=sbc8349.dtb\0"					\
+	"fdtfile=sbc8349.dtb\0"						\
 	""
 
 #define CONFIG_NFSBOOTCOMMAND	                                        \
diff --git a/include/environment.h b/include/environment.h
index af605ab..c4f7c33 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -84,18 +84,23 @@
 # endif
 #endif /* CFG_ENV_IS_IN_NAND */
 
+#ifdef USE_HOSTCC
+# include <stdint.h>
+#else
+# include <linux/types.h>
+#endif
 
 #ifdef CFG_REDUNDAND_ENVIRONMENT
-# define ENV_HEADER_SIZE	(sizeof(unsigned long) + 1)
+# define ENV_HEADER_SIZE	(sizeof(uint32_t) + 1)
 #else
-# define ENV_HEADER_SIZE	(sizeof(unsigned long))
+# define ENV_HEADER_SIZE	(sizeof(uint32_t))
 #endif
 
 
 #define ENV_SIZE (CFG_ENV_SIZE - ENV_HEADER_SIZE)
 
 typedef	struct environment_s {
-	unsigned long	crc;		/* CRC32 over data bytes	*/
+	uint32_t	crc;		/* CRC32 over data bytes	*/
 #ifdef CFG_REDUNDAND_ENVIRONMENT
 	unsigned char	flags;		/* active/obsolete flags	*/
 #endif
diff --git a/include/image.h b/include/image.h
index 60fdb2b..664e51e 100644
--- a/include/image.h
+++ b/include/image.h
@@ -227,9 +227,23 @@
 /*
  * Some systems (for example LWMON) have very short watchdog periods;
  * we must make sure to split long operations like memmove() or
- * crc32() into reasonable chunks.
+ * checksum calculations into reasonable chunks.
  */
+#ifndef CHUNKSZ
 #define CHUNKSZ (64 * 1024)
+#endif
+
+#ifndef CHUNKSZ_CRC32
+#define CHUNKSZ_CRC32 (64 * 1024)
+#endif
+
+#ifndef CHUNKSZ_MD5
+#define CHUNKSZ_MD5 (64 * 1024)
+#endif
+
+#ifndef CHUNKSZ_SHA1
+#define CHUNKSZ_SHA1 (64 * 1024)
+#endif
 
 #define uimage_to_cpu(x)		ntohl(x)
 #define cpu_to_uimage(x)		htonl(x)
@@ -363,9 +377,7 @@
 int image_check_hcrc (image_header_t *hdr);
 int image_check_dcrc (image_header_t *hdr);
 #ifndef USE_HOSTCC
-int image_check_dcrc_wd (image_header_t *hdr, ulong chunksize);
-int getenv_verify (void);
-int getenv_autostart (void);
+int getenv_yesno (char *var);
 ulong getenv_bootm_low(void);
 ulong getenv_bootm_size(void);
 void memmove_wd (void *to, void *from, size_t len, ulong chunksz);
@@ -392,8 +404,7 @@
 void image_multi_getimg (image_header_t *hdr, ulong idx,
 			ulong *data, ulong *len);
 
-inline void image_print_contents (image_header_t *hdr);
-inline void image_print_contents_noindent (image_header_t *hdr);
+void image_print_contents (image_header_t *hdr);
 
 #ifndef USE_HOSTCC
 static inline int image_check_target_arch (image_header_t *hdr)
@@ -469,8 +480,7 @@
 inline int fit_parse_subimage (const char *spec, ulong addr_curr,
 		ulong *addr, const char **image_name);
 
-inline void fit_print_contents (const void *fit);
-inline void fit_print_contents_noindent (const void *fit);
+void fit_print_contents (const void *fit);
 void fit_image_print (const void *fit, int noffset, const char *p);
 void fit_image_print_hash (const void *fit, int noffset, const char *p);
 
diff --git a/include/ppc440.h b/include/ppc440.h
index bb39ad6..2f6ed97 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1437,6 +1437,13 @@
 #define GPT0_COMP2			0x00000088
 #define GPT0_COMP1			0x00000084
 
+#define GPT0_MASK6			0x000000D8
+#define GPT0_MASK5			0x000000D4
+#define GPT0_MASK4			0x000000D0
+#define GPT0_MASK3			0x000000CC
+#define GPT0_MASK2			0x000000C8
+#define GPT0_MASK1			0x000000C4
+
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define SDR0_USB2D0CR                 0x0320
 #define   SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK   0x00000004    /* USB 2.0 Device/EBC Master Selection */
diff --git a/include/sha1.h b/include/sha1.h
index 15ea13c..734d1fb 100644
--- a/include/sha1.h
+++ b/include/sha1.h
@@ -80,6 +80,17 @@
 		unsigned char output[20] );
 
 /**
+ * \brief	   Output = SHA-1( input buffer ), with watchdog triggering
+ *
+ * \param input    buffer holding the  data
+ * \param ilen	   length of the input data
+ * \param output   SHA-1 checksum result
+ * \param chunk_sz watchdog triggering period (in bytes of input processed)
+ */
+void sha1_csum_wd (unsigned char *input, int ilen,
+		unsigned char output[20], unsigned int chunk_sz);
+
+/**
  * \brief	   Output = SHA-1( file contents )
  *
  * \param path	   input file name
diff --git a/include/u-boot/md5.h b/include/u-boot/md5.h
index 046d1ee..8b44a7f 100644
--- a/include/u-boot/md5.h
+++ b/include/u-boot/md5.h
@@ -20,4 +20,12 @@
  */
 void md5 (unsigned char *input, int len, unsigned char output[16]);
 
+/*
+ * Calculate and store in 'output' the MD5 digest of 'len' bytes at 'input'.
+ * 'output' must have enough space to hold 16 bytes. If 'chunk' Trigger the
+ * watchdog every 'chunk_sz' bytes of input processed.
+ */
+void md5_wd (unsigned char *input, int len, unsigned char output[16],
+		unsigned int chunk_sz);
+
 #endif /* _MD5_H */
diff --git a/lib_generic/crc32.c b/lib_generic/crc32.c
index df0dbca..57c6d66 100644
--- a/lib_generic/crc32.c
+++ b/lib_generic/crc32.c
@@ -10,18 +10,20 @@
 
 #ifndef USE_HOSTCC	/* Shut down "ANSI does not permit..." warnings */
 #include <common.h>
+#else
+#include <stdint.h>
 #endif
 
+#include <watchdog.h>
 #include "zlib.h"
 
 #define local static
 #define ZEXPORT	/* empty */
-unsigned long crc32 (unsigned long, const unsigned char *, unsigned int);
 
 #ifdef DYNAMIC_CRC_TABLE
 
 local int crc_table_empty = 1;
-local uLongf crc_table[256];
+local uint32_t crc_table[256];
 local void make_crc_table OF((void));
 
 /*
@@ -50,7 +52,7 @@
 */
 local void make_crc_table()
 {
-  uLong c;
+  uint32_t c;
   int n, k;
   uLong poly;            /* polynomial exclusive-or pattern */
   /* terms of polynomial defining this crc (except x^32): */
@@ -74,7 +76,7 @@
 /* ========================================================================
  * Table of CRC-32's of all single-byte values (made by make_crc_table)
  */
-local const uLongf crc_table[256] = {
+local const uint32_t crc_table[256] = {
   0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L,
   0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L,
   0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L,
@@ -134,12 +136,12 @@
 /* =========================================================================
  * This function can be used by asm versions of crc32()
  */
-const uLongf * ZEXPORT get_crc_table()
+const uint32_t * ZEXPORT get_crc_table()
 {
 #ifdef DYNAMIC_CRC_TABLE
   if (crc_table_empty) make_crc_table();
 #endif
-  return (const uLongf *)crc_table;
+  return (const uint32_t *)crc_table;
 }
 #endif
 
@@ -150,10 +152,7 @@
 #define DO8(buf)  DO4(buf); DO4(buf);
 
 /* ========================================================================= */
-uLong ZEXPORT crc32(crc, buf, len)
-    uLong crc;
-    const Bytef *buf;
-    uInt len;
+uint32_t ZEXPORT crc32 (uint32_t crc, const Bytef *buf, uInt len)
 {
 #ifdef DYNAMIC_CRC_TABLE
     if (crc_table_empty)
@@ -178,7 +177,7 @@
 /* No ones complement version. JFFS2 (and other things ?)
  * don't use ones compliment in their CRC calculations.
  */
-uLong ZEXPORT crc32_no_comp(uLong crc, const Bytef *buf, uInt len)
+uint32_t ZEXPORT crc32_no_comp(uint32_t crc, const Bytef *buf, uInt len)
 {
 #ifdef DYNAMIC_CRC_TABLE
     if (crc_table_empty)
@@ -196,4 +195,33 @@
     return crc;
 }
 
+#endif
+
+/*
+ * Calculate the crc32 checksum triggering the watchdog every 'chunk_sz' bytes
+ * of input.
+ */
+uint32_t ZEXPORT crc32_wd (uint32_t crc,
+			   const unsigned char *buf,
+			   uInt len, uInt chunk_sz)
+{
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+	const unsigned char *end, *curr;
+	int chunk;
+
+	curr = buf;
+	end = buf + len;
+	while (curr < end) {
+		chunk = end - curr;
+		if (chunk > chunk_sz)
+			chunk = chunk_sz;
+		crc = crc32 (crc, curr, chunk);
+		curr += chunk;
+		WATCHDOG_RESET ();
+	}
+#else
+        crc = crc32 (crc, buf, len);
 #endif
+
+	return crc;
+}
diff --git a/lib_generic/md5.c b/lib_generic/md5.c
index 3cee431..78ef475 100644
--- a/lib_generic/md5.c
+++ b/lib_generic/md5.c
@@ -25,6 +25,10 @@
    and to fit the cifs vfs by
    Steve French sfrench@us.ibm.com */
 
+#ifndef USE_HOSTCC
+#include <common.h>
+#endif /* USE_HOSTCC */
+#include <watchdog.h>
 #include <linux/types.h>
 #include <linux/string.h>
 #include <u-boot/md5.h>
@@ -272,3 +276,39 @@
 	MD5Update(&context, input, len);
 	MD5Final(output, &context);
 }
+
+
+/*
+ * Calculate and store in 'output' the MD5 digest of 'len' bytes at 'input'.
+ * 'output' must have enough space to hold 16 bytes. If 'chunk' Trigger the
+ * watchdog every 'chunk_sz' bytes of input processed.
+ */
+void
+md5_wd (unsigned char *input, int len, unsigned char output[16],
+	unsigned int chunk_sz)
+{
+	struct MD5Context context;
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+	unsigned char *end, *curr;
+	int chunk;
+#endif
+
+	MD5Init(&context);
+
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+	curr = input;
+	end = input + len;
+	while (curr < end) {
+		chunk = end - curr;
+		if (chunk > chunk_sz)
+			chunk = chunk_sz;
+		MD5Update(&context, curr, chunk);
+		curr += chunk;
+		WATCHDOG_RESET ();
+	}
+#else
+	MD5Update(&context, input, len);
+#endif
+
+	MD5Final(output, &context);
+}
diff --git a/lib_generic/sha1.c b/lib_generic/sha1.c
index 08ffa6b..c8ef4d2 100644
--- a/lib_generic/sha1.c
+++ b/lib_generic/sha1.c
@@ -29,6 +29,10 @@
 #define _CRT_SECURE_NO_DEPRECATE 1
 #endif
 
+#ifndef USE_HOSTCC
+#include <common.h>
+#endif /* USE_HOSTCC */
+#include <watchdog.h>
 #include <linux/string.h>
 #include "sha1.h"
 
@@ -309,6 +313,39 @@
 }
 
 /*
+ * Output = SHA-1( input buffer ). Trigger the watchdog every 'chunk_sz'
+ * bytes of input processed.
+ */
+void sha1_csum_wd (unsigned char *input, int ilen, unsigned char output[20],
+			unsigned int chunk_sz)
+{
+	sha1_context ctx;
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+	unsigned char *end, *curr;
+	int chunk;
+#endif
+
+	sha1_starts (&ctx);
+
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+	curr = input;
+	end = input + ilen;
+	while (curr < end) {
+		chunk = end - curr;
+		if (chunk > chunk_sz)
+			chunk = chunk_sz;
+		sha1_update (&ctx, curr, chunk);
+		curr += chunk;
+		WATCHDOG_RESET ();
+	}
+#else
+	sha1_update (&ctx, input, ilen);
+#endif
+
+	sha1_finish (&ctx, output);
+}
+
+/*
  * Output = HMAC-SHA-1( input buffer, hmac key )
  */
 void sha1_hmac (unsigned char *key, int keylen,
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index b2bc4eb..1b8a872 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -124,7 +124,6 @@
 #define CFG_MEM_TOP_HIDE	0
 #endif
 
-extern ulong _start;
 extern ulong __init_end;
 extern ulong _end;
 ulong monitor_flash_len;
diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c
index e2147cb..bc57725 100644
--- a/nand_spl/nand_boot.c
+++ b/nand_spl/nand_boot.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2006-2007
+ * (C) Copyright 2006-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * This program is free software; you can redistribute it and/or
@@ -28,6 +28,10 @@
 
 extern void board_nand_init(struct nand_chip *nand);
 
+#if (CFG_NAND_PAGE_SIZE <= 512)
+/*
+ * NAND command for small page NAND devices (512)
+ */
 static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
 {
 	struct nand_chip *this = mtd->priv;
@@ -65,6 +69,64 @@
 
 	return 0;
 }
+#else
+/*
+ * NAND command for large page NAND devices (2k)
+ */
+static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
+{
+	struct nand_chip *this = mtd->priv;
+	int page_offs = offs;
+	int page_addr = page + block * CFG_NAND_PAGE_COUNT;
+
+	if (this->dev_ready)
+		this->dev_ready(mtd);
+	else
+		CFG_NAND_READ_DELAY;
+
+	/* Emulate NAND_CMD_READOOB */
+	if (cmd == NAND_CMD_READOOB) {
+		page_offs += CFG_NAND_PAGE_SIZE;
+		cmd = NAND_CMD_READ0;
+	}
+
+	/* Begin command latch cycle */
+	this->hwcontrol(mtd, NAND_CTL_SETCLE);
+	this->write_byte(mtd, cmd);
+	/* Set ALE and clear CLE to start address cycle */
+	this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+	this->hwcontrol(mtd, NAND_CTL_SETALE);
+	/* Column address */
+	this->write_byte(mtd, page_offs & 0xff);			/* A[7:0] */
+	this->write_byte(mtd, (uchar)((page_offs >> 8) & 0xff));	/* A[11:9] */
+	/* Row address */
+	this->write_byte(mtd, (uchar)(page_addr & 0xff));		/* A[19:12] */
+	this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff));	/* A[27:20] */
+#ifdef CFG_NAND_5_ADDR_CYCLE
+	/* One more address cycle for devices > 128MiB */
+	this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f));	/* A[xx:28] */
+#endif
+	/* Latch in address */
+	this->hwcontrol(mtd, NAND_CTL_CLRALE);
+
+	/* Begin command latch cycle */
+	this->hwcontrol(mtd, NAND_CTL_SETCLE);
+	/* Write out the start read command */
+	this->write_byte(mtd, NAND_CMD_READSTART);
+	/* End command latch cycle */
+	this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+
+	/*
+	 * Wait a while for the data to be ready
+	 */
+	if (this->dev_ready)
+		this->dev_ready(mtd);
+	else
+		CFG_NAND_READ_DELAY;
+
+	return 0;
+}
+#endif
 
 static int nand_is_bad_block(struct mtd_info *mtd, int block)
 {
diff --git a/post/Makefile b/post/Makefile
index f32af95..02b5154 100644
--- a/post/Makefile
+++ b/post/Makefile
@@ -21,11 +21,50 @@
 # MA 02111-1307 USA
 #
 
+include $(TOPDIR)/include/autoconf.mk
 
-SUBDIRS = drivers cpu lib_$(ARCH) board/$(BOARDDIR)
+LIB				= libpost.a
+GPLIB-$(CONFIG_HAS_POST)	+= libgenpost.a
+COBJS-$(CONFIG_HAS_POST)	+= post.o tests.o
 
-LIB	= libpost.a
+SPLIB-$(CONFIG_HAS_POST) = drivers/libpostdrivers.a
+SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d lib_$(ARCH) ]; then echo \
+			    "lib_$(ARCH)/libpost$(ARCH).a"; fi)
+SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d lib_$(ARCH)/fpu ]; then echo \
+			    "lib_$(ARCH)/fpu/libpost$(ARCH)fpu.a"; fi)
+SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d cpu/$(CPU) ]; then echo \
+			    "cpu/$(CPU)/libpost$(CPU).a"; fi)
+SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d board/$(BOARD) ]; then echo \
+			    "board/$(BOARD)/libpost$(BOARD).a"; fi)
 
-COBJS	= post.o tests.o
+GPLIB	:= $(GPLIB-y)
+SPLIB	:= $(SPLIB-y)
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+LIB	:= $(obj)$(LIB)
+
+all:	$(LIB)
+
+# generic POST library
+$(GPLIB): $(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+# specific POST libraries
+$(SPLIB): $(obj).depend
+	$(MAKE) -C $(dir $(subst $(obj),,$@))
+
+# the POST lib archive
+$(LIB): $(GPLIB) $(SPLIB)
+	(echo create $(LIB); for lib in $(GPLIB) $(SPLIB) ; \
+	 do echo addlib $$lib; done; echo save) \
+	| $(AR) -M
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
 
-include $(TOPDIR)/post/rules.mk
+#########################################################################
diff --git a/post/board/lwmon/sysmon.c b/post/board/lwmon/sysmon.c
index f61d598..ea8b5a9 100644
--- a/post/board/lwmon/sysmon.c
+++ b/post/board/lwmon/sysmon.c
@@ -24,8 +24,6 @@
 #include <post.h>
 #include <common.h>
 
-#ifdef CONFIG_POST
-
 /*
  * SYSMON test
  *
@@ -328,4 +326,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_SYSMON */
-#endif /* CONFIG_POST */
diff --git a/post/board/lwmon5/Makefile b/post/board/lwmon5/Makefile
index 5a92d1c..3cb6426 100644
--- a/post/board/lwmon5/Makefile
+++ b/post/board/lwmon5/Makefile
@@ -20,9 +20,10 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
+include $(TOPDIR)/include/autoconf.mk
 
 LIB	= libpostlwmon5.a
 
-COBJS	= sysmon.o watchdog.o dspic.o fpga.o dsp.o gdc.o
+COBJS-$(CONFIG_HAS_POST)	+= sysmon.o watchdog.o dspic.o fpga.o dsp.o gdc.o
 
 include $(TOPDIR)/post/rules.mk
diff --git a/post/board/lwmon5/dsp.c b/post/board/lwmon5/dsp.c
index 1946f09..a96ac7d 100644
--- a/post/board/lwmon5/dsp.c
+++ b/post/board/lwmon5/dsp.c
@@ -24,11 +24,8 @@
 
 #include <common.h>
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
-
 #if CONFIG_POST & CFG_POST_DSP
 #include <asm/io.h>
 
@@ -54,4 +51,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_DSP */
-#endif /* CONFIG_POST */
diff --git a/post/board/lwmon5/dspic.c b/post/board/lwmon5/dspic.c
index fcbbc60..eb1c31c 100644
--- a/post/board/lwmon5/dspic.c
+++ b/post/board/lwmon5/dspic.c
@@ -24,8 +24,6 @@
 
 #include <common.h>
 
-#ifdef CONFIG_POST
-
 /* There are two tests for dsPIC currently implemented:
  * 1. dsPIC ready test. Done in board_early_init_f(). Only result verified here.
  * 2. dsPIC POST result test.  This test gets dsPIC POST codes and version.
@@ -59,27 +57,25 @@
 
 #if CONFIG_POST & CFG_POST_BSPEC2
 /* Read a register from the dsPIC. */
-int dspic_read(ushort reg, ushort *data)
+int dspic_read(ushort reg)
 {
-	uchar buf[sizeof(*data)];
-	int rval;
+	uchar buf[2];
 
-	rval = i2c_read(CFG_I2C_DSPIC_IO_ADDR, reg, sizeof(reg),
-					       buf, sizeof(*data));
+	if (i2c_read(CFG_I2C_DSPIC_IO_ADDR, reg, 2, buf, 2))
+		return -1;
 
-	*data = (buf[0] << 8) | buf[1];
-
-	return rval;
+	return (uint)((buf[0] << 8) | buf[1]);
 }
 
 /* Verify error codes regs, display version */
 int dspic_post_test(int flags)
 {
-	ushort data;
+	int data;
 	int ret = 0;
 
 	post_log("\n");
-	if (dspic_read(DSPIC_VERSION_REG, &data)) {
+	data = dspic_read(DSPIC_VERSION_REG);
+	if (data == -1) {
 		post_log("dsPIC : failed read version\n");
 		ret = 1;
 	} else {
@@ -87,24 +83,23 @@
 			(data >> 8) & 0xFF, data & 0xFF);
 	}
 
-	if (dspic_read(DSPIC_POST_ERROR_REG, &data)) {
+	data = dspic_read(DSPIC_POST_ERROR_REG);
+	if (data != 0) ret = 1;
+	if (data == -1) {
 		post_log("dsPIC : failed read POST code\n");
 	} else {
 		post_log("dsPIC POST code 0x%04X\n", data);
 	}
-	if (data != 0)
-		ret = 1;
 
-	if (dspic_read(DSPIC_SYS_ERROR_REG, &data)) {
+	data = dspic_read(DSPIC_SYS_ERROR_REG);
+	if (data == -1) {
 		post_log("dsPIC : failed read system error\n");
 		ret = 1;
-	} else if (data != 0) {
+	} else {
 		post_log("dsPIC SYS-ERROR code: 0x%04X\n", data);
-		ret = 1;
 	}
 
 	return ret;
 }
 
 #endif /* CONFIG_POST & CFG_POST_BSPEC2 */
-#endif /* CONFIG_POST */
diff --git a/post/board/lwmon5/fpga.c b/post/board/lwmon5/fpga.c
index 2d95b5e..b48390b 100644
--- a/post/board/lwmon5/fpga.c
+++ b/post/board/lwmon5/fpga.c
@@ -23,8 +23,6 @@
  */
 #include <common.h>
 
-#ifdef CONFIG_POST
-
 /* This test performs testing of FPGA SCRATCH register,
  * gets FPGA version and run get_ram_size() on FPGA memory
  */
@@ -94,4 +92,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_BSPEC3 */
-#endif /* CONFIG_POST */
diff --git a/post/board/lwmon5/gdc.c b/post/board/lwmon5/gdc.c
index 4af6a7a..bc16685 100644
--- a/post/board/lwmon5/gdc.c
+++ b/post/board/lwmon5/gdc.c
@@ -23,8 +23,6 @@
  */
 #include <common.h>
 
-#ifdef CONFIG_POST
-
 /* This test attempts to verify board GDC. A scratch register tested, then
  * simple memory test (get_ram_size()) run over GDC memory.
  */
@@ -96,4 +94,3 @@
 	return ret;
 }
 #endif /* CONFIG_POST & CFG_POST_BSPEC4 */
-#endif /* CONFIG_POST */
diff --git a/post/board/lwmon5/sysmon.c b/post/board/lwmon5/sysmon.c
index 0cf1cf2..15661e3 100644
--- a/post/board/lwmon5/sysmon.c
+++ b/post/board/lwmon5/sysmon.c
@@ -25,8 +25,6 @@
 #include <post.h>
 #include <common.h>
 
-#ifdef CONFIG_POST
-
 /*
  * SYSMON test
  *
@@ -34,9 +32,9 @@
  * The test passes when all the following voltages and temperatures
  * are within allowed ranges:
  *
- * Temperature		      -40 .. +85 C
- * +5V			    +4.75 .. +5.25 V
- * +5V standby		    +4.75 .. +5.25 V
+ * Temperature                -40 .. +85 C
+ * +5V                      +4.75 .. +5.25 V
+ * +5V standby              +4.75 .. +5.25 V
  *
  * LCD backlight is not enabled if temperature values are not within
  * allowed ranges (-30 .. + 80). The brightness of backlite can be
@@ -58,7 +56,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* from dspic.c */
-extern int dspic_read(ushort reg, ushort *data);
+extern int dspic_read(ushort reg);
 
 #define	RELOC(x) if (x != NULL) x = (void *) ((ulong) (x) + gd->reloc_off)
 
@@ -67,7 +65,6 @@
 
 static void sysmon_dspic_init (sysmon_t * this);
 static int sysmon_dspic_read (sysmon_t * this, uint addr);
-static int sysmon_dspic_read_sgn (sysmon_t * this, uint addr);
 static void sysmon_backlight_disable (sysmon_table_t * this);
 
 struct sysmon_s
@@ -80,13 +77,9 @@
 static sysmon_t sysmon_dspic =
 	{CFG_I2C_DSPIC_IO_ADDR, sysmon_dspic_init, sysmon_dspic_read};
 
-static sysmon_t sysmon_dspic_sgn =
-	{CFG_I2C_DSPIC_IO_ADDR, sysmon_dspic_init, sysmon_dspic_read_sgn};
-
 static sysmon_t * sysmon_list[] =
 {
 	&sysmon_dspic,
-	&sysmon_dspic_sgn,
 	NULL
 };
 
@@ -114,17 +107,17 @@
 
 static sysmon_table_t sysmon_table[] =
 {
-    {"Temperature", " C", &sysmon_dspic_sgn, NULL, sysmon_backlight_disable,
+    {"Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable,
      1, 1, -32768, 32767, 0xFFFF, 0x8000-40, 0x8000+85, 0,
-				  0x8000-30, 0x8000+80, 0, 0x12BC},
+                                  0x8000-30, 0x8000+80, 0, 0x12BC},
 
     {"+ 5 V", "V", &sysmon_dspic, NULL, NULL,
-     100, 1000, 0, 0xFFFF, 0xFFFF, 4750, 5250, 0,
-				   4750, 5250, 0, 0x12CA},
+     100, 1000, -0x8000, 0x7FFF, 0xFFFF, 0x8000+4750, 0x8000+5250, 0,
+                                         0x8000+4750, 0x8000+5250, 0, 0x12CA},
 
     {"+ 5 V standby", "V", &sysmon_dspic, NULL, NULL,
-     100, 1000, 0, 0xFFFF, 0xFFFF, 4750, 5250, 0,
-				   4750, 5250, 0, 0x12C6},
+     100, 1000, -0x8000, 0x7FFF, 0xFFFF, 0x8000+4750, 0x8000+5250, 0,
+                                         0x8000+4750, 0x8000+5250, 0, 0x12C6},
 };
 static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]);
 
@@ -161,7 +154,9 @@
 	static char buf[32];
 	char *p, sign;
 	int decimal, frac;
-	int unit_val =
+	int unit_val;
+
+	unit_val =
 	    s->unit_min + (s->unit_max - s->unit_min) * val / s->val_mask;
 
 	if (val == -1)
@@ -197,18 +192,10 @@
 
 static int sysmon_dspic_read (sysmon_t * this, uint addr)
 {
-	ushort data;
-
-	return (dspic_read(addr, &data)) ? -1 : data;
-}
-
-static int sysmon_dspic_read_sgn (sysmon_t * this, uint addr)
-{
-	ushort data;
+	int res = dspic_read(addr);
 
 	/* To fit into the table range we should add 0x8000 */
-	return (dspic_read(addr, &data)) ? -1 :
-	       (signed short)data + 0x8000;
+	return (res == -1) ? -1 : (res + 0x8000);
 }
 
 static void sysmon_backlight_disable (sysmon_table_t * this)
@@ -256,4 +243,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_SYSMON */
-#endif /* CONFIG_POST */
diff --git a/post/board/lwmon5/watchdog.c b/post/board/lwmon5/watchdog.c
index 899fbfb..16c01be 100644
--- a/post/board/lwmon5/watchdog.c
+++ b/post/board/lwmon5/watchdog.c
@@ -24,14 +24,11 @@
 
 #include <common.h>
 
-/*
- * This test verifies if the reason of last reset was an abnormal voltage
+/* This test verifies if the reason of last reset was an abnormal voltage
  * condition, than it performs watchdog test, measuing time required to
  * trigger watchdog reset.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_WATCHDOG
@@ -55,9 +52,8 @@
 
 int sysmon1_post_test(int flags)
 {
-	if (gpio_read_in_bit(CFG_GPIO_SYSMON_STATUS) == 0) {
-		/*
-		 * 3.1. GPIO62 is low
+	if (gpio_read_in_bit(CFG_GPIO_SYSMON_STATUS)) {
+		/* 3.1. GPIO62 is low
 		 * Assuming system voltage failure.
 		 */
 		post_log("Abnormal voltage detected (GPIO62)\n");
@@ -69,14 +65,11 @@
 
 int lwmon5_watchdog_post_test(int flags)
 {
-	ulong time;
-
 	/* On each reset scratch register 1 should be tested,
 	 * but first test GPIO62:
 	 */
 	if (!(flags & POST_MANUAL) && sysmon1_post_test(flags)) {
-		/*
-		 * 3.1. GPIO62 is low
+		/* 3.1. GPIO62 is low
 		 * Assuming system voltage failure.
 		 */
 		/* 3.1.1. Set scratch register 1 to 0x0000xxxx */
@@ -86,12 +79,12 @@
 	}
 
 	if (watchdog_magic_read() != CFG_WATCHDOG_MAGIC) {
-		/*
-		 * 3.2. Scratch register 1 differs from magic value 0x1248xxxx
+		/* 3.2. Scratch register 1 differs from magic value 0x1248xxxx
 		 * Assuming PowerOn
 		 */
 		int ints;
 		ulong base;
+		ulong time;
 
 		/* 3.2.1. Set magic value to scratch register */
 		watchdog_magic_write(CFG_WATCHDOG_MAGIC);
@@ -109,28 +102,26 @@
 		if (ints)
 			enable_interrupts ();
 
-		/*
-		 * 3.2.5. Reset didn't happen. - Set 0x0000xxxx
+		/* 3.2.5. Reset didn't happen. - Set 0x0000xxxx
 		 * into scratch register 1
 		 */
 		watchdog_magic_write(0);
 		/* 3.2.6. Mark test as failed. */
 		post_log("hw watchdog time : %u ms, failed ", time);
 		return 2;
+	} else {
+		/* 3.3. Scratch register matches magic value 0x1248xxxx
+		 * Assume this is watchdog-initiated reset
+		 */
+		ulong time;
+		/* 3.3.1. So, the test succeed, save measured time to syslog. */
+		time = in_be32((void *)CFG_WATCHDOG_TIME_ADDR);
+		post_log("hw watchdog time : %u ms, passed ", time);
+		/* 3.3.2. Set scratch register 1 to 0x0000xxxx */
+		watchdog_magic_write(0);
+		return 0;
 	}
-
-	/*
-	 * 3.3. Scratch register matches magic value 0x1248xxxx
-	 * Assume this is watchdog-initiated reset
-	 */
-	/* 3.3.1. So, the test succeed, save measured time to syslog. */
-	time = in_be32((void *)CFG_WATCHDOG_TIME_ADDR);
-	post_log("hw watchdog time : %u ms, passed ", time);
-	/* 3.3.2. Set scratch register 1 to 0x0000xxxx */
-	watchdog_magic_write(0);
-
-	return 0;
+	return -1;
 }
 
 #endif /* CONFIG_POST & CFG_POST_WATCHDOG */
-#endif /* CONFIG_POST */
diff --git a/post/board/netta/codec.c b/post/board/netta/codec.c
index e881752..115e331 100644
--- a/post/board/netta/codec.c
+++ b/post/board/netta/codec.c
@@ -31,8 +31,6 @@
  * in the board specific function.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_CODEC
@@ -45,4 +43,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_CODEC */
-#endif /* CONFIG_POST */
diff --git a/post/board/netta/dsp.c b/post/board/netta/dsp.c
index 63531a2..dcef4e8 100644
--- a/post/board/netta/dsp.c
+++ b/post/board/netta/dsp.c
@@ -31,8 +31,6 @@
  * in the board specific function.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_DSP
@@ -45,4 +43,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_DSP */
-#endif /* CONFIG_POST */
diff --git a/post/cpu/mpc8xx/cache.c b/post/cpu/mpc8xx/cache.c
index 501465c..36965a1 100644
--- a/post/cpu/mpc8xx/cache.c
+++ b/post/cpu/mpc8xx/cache.c
@@ -29,8 +29,6 @@
  * several test scenarios.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include <watchdog.h>
 
@@ -78,4 +76,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_CACHE */
-#endif /* CONFIG_POST */
diff --git a/post/cpu/mpc8xx/cache_8xx.S b/post/cpu/mpc8xx/cache_8xx.S
index 2d41b55..a3fc39b 100644
--- a/post/cpu/mpc8xx/cache_8xx.S
+++ b/post/cpu/mpc8xx/cache_8xx.S
@@ -22,7 +22,6 @@
 
 #include <config.h>
 
-#ifdef CONFIG_POST
 #if defined(CONFIG_MPC823) || \
     defined(CONFIG_MPC850) || \
     defined(CONFIG_MPC855) || \
@@ -492,4 +491,3 @@
 
 #endif /* CONFIG_MPC823 || MPC850 || MPC855 || MPC860 */
 #endif /* CONFIG_POST & CFG_POST_CACHE */
-#endif /* CONFIG_POST */
diff --git a/post/cpu/mpc8xx/ether.c b/post/cpu/mpc8xx/ether.c
index 8c87b59..2fa5cf4 100644
--- a/post/cpu/mpc8xx/ether.c
+++ b/post/cpu/mpc8xx/ether.c
@@ -35,8 +35,6 @@
  *   TEST_NUM - number of tests
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #if CONFIG_POST & CFG_POST_ETHER
 #if defined(CONFIG_8xx)
@@ -627,5 +625,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_ETHER */
-
-#endif /* CONFIG_POST */
diff --git a/post/cpu/mpc8xx/spr.c b/post/cpu/mpc8xx/spr.c
index 330b977..83f04da 100644
--- a/post/cpu/mpc8xx/spr.c
+++ b/post/cpu/mpc8xx/spr.c
@@ -33,8 +33,6 @@
  * corresponding table value.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_SPR
@@ -149,4 +147,3 @@
 	return ret;
 }
 #endif /* CONFIG_POST & CFG_POST_SPR */
-#endif /* CONFIG_POST */
diff --git a/post/cpu/mpc8xx/uart.c b/post/cpu/mpc8xx/uart.c
index fd97e38..635debe 100644
--- a/post/cpu/mpc8xx/uart.c
+++ b/post/cpu/mpc8xx/uart.c
@@ -36,8 +36,6 @@
  *   TEST_NUM - number of tests
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #if CONFIG_POST & CFG_POST_UART
 #if defined(CONFIG_8xx)
@@ -556,5 +554,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_UART */
-
-#endif /* CONFIG_POST */
diff --git a/post/cpu/mpc8xx/usb.c b/post/cpu/mpc8xx/usb.c
index 0c74cfa..5877981 100644
--- a/post/cpu/mpc8xx/usb.c
+++ b/post/cpu/mpc8xx/usb.c
@@ -34,8 +34,6 @@
  * Initialization Example.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_USB
@@ -265,5 +263,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_USB */
-
-#endif /* CONFIG_POST */
diff --git a/post/cpu/mpc8xx/watchdog.c b/post/cpu/mpc8xx/watchdog.c
index 48c4282..f94158a 100644
--- a/post/cpu/mpc8xx/watchdog.c
+++ b/post/cpu/mpc8xx/watchdog.c
@@ -33,8 +33,6 @@
  * reboots, on the second iteration the test routine reports a success.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include <watchdog.h>
 
@@ -75,4 +73,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_WATCHDOG */
-#endif /* CONFIG_POST */
diff --git a/post/cpu/ppc4xx/Makefile b/post/cpu/ppc4xx/Makefile
index e3f44b7..7b13413 100644
--- a/post/cpu/ppc4xx/Makefile
+++ b/post/cpu/ppc4xx/Makefile
@@ -20,10 +20,11 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
+include $(TOPDIR)/include/autoconf.mk
 
 LIB	= libpostppc4xx.a
 
-AOBJS   = cache_4xx.o
-COBJS	= cache.o denali_ecc.o ether.o fpu.o spr.o uart.o watchdog.o
+AOBJS-$(CONFIG_HAS_POST)	+= cache_4xx.o
+COBJS-$(CONFIG_HAS_POST)	+= cache.o denali_ecc.o ether.o fpu.o spr.o uart.o watchdog.o
 
 include $(TOPDIR)/post/rules.mk
diff --git a/post/cpu/ppc4xx/cache.c b/post/cpu/ppc4xx/cache.c
index 466ca92..be6a2bf 100644
--- a/post/cpu/ppc4xx/cache.c
+++ b/post/cpu/ppc4xx/cache.c
@@ -31,8 +31,6 @@
  * several test scenarios.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_CACHE
@@ -122,4 +120,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_CACHE */
-#endif /* CONFIG_POST */
diff --git a/post/cpu/ppc4xx/cache_4xx.S b/post/cpu/ppc4xx/cache_4xx.S
index d5cb075..455ffa0 100644
--- a/post/cpu/ppc4xx/cache_4xx.S
+++ b/post/cpu/ppc4xx/cache_4xx.S
@@ -25,8 +25,6 @@
 
 #include <config.h>
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
@@ -489,4 +487,3 @@
 	blr
 
 #endif /* CONFIG_POST & CFG_POST_CACHE */
-#endif /* CONFIG_POST */
diff --git a/post/cpu/ppc4xx/denali_ecc.c b/post/cpu/ppc4xx/denali_ecc.c
index 439f80d..12a1bbf 100644
--- a/post/cpu/ppc4xx/denali_ecc.c
+++ b/post/cpu/ppc4xx/denali_ecc.c
@@ -31,7 +31,7 @@
 #include <common.h>
 #include <watchdog.h>
 
-#if defined(CONFIG_POST) && (defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
 #include <post.h>
 
@@ -268,4 +268,4 @@
 	return ret;
 }
 #endif /* CONFIG_POST & CFG_POST_ECC */
-#endif /* defined(CONFIG_POST) && ... */
+#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c
index 4ac7491..ccbfcf9 100644
--- a/post/cpu/ppc4xx/ether.c
+++ b/post/cpu/ppc4xx/ether.c
@@ -37,8 +37,6 @@
  *   TEST_NUM - number of tests
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_ETHER
@@ -430,4 +428,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_ETHER */
-#endif /* CONFIG_POST */
diff --git a/post/cpu/ppc4xx/fpu.c b/post/cpu/ppc4xx/fpu.c
index 0c26fe0..fff4169 100644
--- a/post/cpu/ppc4xx/fpu.c
+++ b/post/cpu/ppc4xx/fpu.c
@@ -25,7 +25,6 @@
 
 #include <config.h>
 
-#ifdef CONFIG_POST
 #if defined(CONFIG_440EP) || \
     defined(CONFIG_440EPX)
 
@@ -56,4 +55,3 @@
 }
 
 #endif
-#endif /* CONFIG_POST */
diff --git a/post/cpu/ppc4xx/spr.c b/post/cpu/ppc4xx/spr.c
index 37c9559..6152eb2 100644
--- a/post/cpu/ppc4xx/spr.c
+++ b/post/cpu/ppc4xx/spr.c
@@ -35,8 +35,6 @@
  * corresponding table value.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_SPR
@@ -199,4 +197,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_SPR */
-#endif /* CONFIG_POST */
diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c
index f47b48e..27cfb91 100644
--- a/post/cpu/ppc4xx/uart.c
+++ b/post/cpu/ppc4xx/uart.c
@@ -32,8 +32,6 @@
  * characters are transmitted.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_UART
@@ -389,4 +387,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_UART */
-#endif /* CONFIG_POST */
diff --git a/post/cpu/ppc4xx/watchdog.c b/post/cpu/ppc4xx/watchdog.c
index bd4f4c9..7fdecb4 100644
--- a/post/cpu/ppc4xx/watchdog.c
+++ b/post/cpu/ppc4xx/watchdog.c
@@ -35,8 +35,6 @@
  * reboots, on the second iteration the test routine reports a success.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_WATCHDOG
@@ -68,4 +66,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_WATCHDOG */
-#endif /* CONFIG_POST */
diff --git a/post/drivers/Makefile b/post/drivers/Makefile
index cb2f1de..0b6cdf5 100644
--- a/post/drivers/Makefile
+++ b/post/drivers/Makefile
@@ -20,12 +20,10 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-
-
-SUBDIRS =
+include $(TOPDIR)/config.mk
 
 LIB	= libpostdrivers.a
 
-COBJS	= i2c.o memory.o rtc.o
+COBJS-$(CONFIG_HAS_POST)	+= i2c.o memory.o rtc.o
 
 include $(TOPDIR)/post/rules.mk
diff --git a/post/drivers/i2c.c b/post/drivers/i2c.c
index 1b2e644..f54fe99 100644
--- a/post/drivers/i2c.c
+++ b/post/drivers/i2c.c
@@ -23,8 +23,6 @@
 
 #include <common.h>
 
-#ifdef CONFIG_POST
-
 /*
  * I2C test
  *
@@ -91,4 +89,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_I2C */
-#endif /* CONFIG_POST */
diff --git a/post/drivers/memory.c b/post/drivers/memory.c
index fb96985..e94d92c 100644
--- a/post/drivers/memory.c
+++ b/post/drivers/memory.c
@@ -150,8 +150,6 @@
  * the whole RAM.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include <watchdog.h>
 
@@ -483,4 +481,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_MEMORY */
-#endif /* CONFIG_POST */
diff --git a/post/drivers/rtc.c b/post/drivers/rtc.c
index e3da5e6..66e5265 100644
--- a/post/drivers/rtc.c
+++ b/post/drivers/rtc.c
@@ -40,8 +40,6 @@
  *      nonleap-years.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include <rtc.h>
 
@@ -195,4 +193,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_RTC */
-#endif /* CONFIG_POST */
diff --git a/post/lib_ppc/Makefile b/post/lib_ppc/Makefile
index 9f1b329..bd7a232 100644
--- a/post/lib_ppc/Makefile
+++ b/post/lib_ppc/Makefile
@@ -20,14 +20,13 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-
-SUBDIRS = fpu
+include $(TOPDIR)/config.mk
 
 LIB	= libpostppc.a
 
-AOBJS	= asm.o
-COBJS	= cpu.o cmp.o cmpi.o two.o twox.o three.o threex.o
-COBJS   += threei.o andi.o srawi.o rlwnm.o rlwinm.o rlwimi.o
-COBJS	+= store.o load.o cr.o b.o multi.o string.o complex.o
+AOBJS-$(CONFIG_HAS_POST)	+= asm.o
+COBJS-$(CONFIG_HAS_POST)	+= cpu.o cmp.o cmpi.o two.o twox.o three.o threex.o
+COBJS-$(CONFIG_HAS_POST)   += threei.o andi.o srawi.o rlwnm.o rlwinm.o rlwimi.o
+COBJS-$(CONFIG_HAS_POST)	+= store.o load.o cr.o b.o multi.o string.o complex.o
 
 include $(TOPDIR)/post/rules.mk
diff --git a/post/lib_ppc/andi.c b/post/lib_ppc/andi.c
index 7ddf2ab..e3315bf 100644
--- a/post/lib_ppc/andi.c
+++ b/post/lib_ppc/andi.c
@@ -32,8 +32,6 @@
  * different sets of operand registers and result registers.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -120,4 +118,3 @@
 }
 
 #endif
-#endif
diff --git a/post/lib_ppc/asm.S b/post/lib_ppc/asm.S
index 1279176..6220ed2 100644
--- a/post/lib_ppc/asm.S
+++ b/post/lib_ppc/asm.S
@@ -22,8 +22,6 @@
 
 #include <config.h>
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
@@ -358,4 +356,3 @@
 blr
 
 #endif
-#endif
diff --git a/post/lib_ppc/b.c b/post/lib_ppc/b.c
index 6e276c4..45b9ff2 100644
--- a/post/lib_ppc/b.c
+++ b/post/lib_ppc/b.c
@@ -37,8 +37,6 @@
  * linked in U-Boot at build time.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -194,4 +192,3 @@
 }
 
 #endif
-#endif
diff --git a/post/lib_ppc/cmp.c b/post/lib_ppc/cmp.c
index 789a24c..89f754a 100644
--- a/post/lib_ppc/cmp.c
+++ b/post/lib_ppc/cmp.c
@@ -36,8 +36,6 @@
  * the result in and the expected result.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -130,4 +128,3 @@
 }
 
 #endif
-#endif
diff --git a/post/lib_ppc/cmpi.c b/post/lib_ppc/cmpi.c
index e0c2aaf..0afdd71 100644
--- a/post/lib_ppc/cmpi.c
+++ b/post/lib_ppc/cmpi.c
@@ -36,8 +36,6 @@
  * the result in and the expected result.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -130,4 +128,3 @@
 }
 
 #endif
-#endif
diff --git a/post/lib_ppc/complex.c b/post/lib_ppc/complex.c
index 033584b..271392a 100644
--- a/post/lib_ppc/complex.c
+++ b/post/lib_ppc/complex.c
@@ -31,8 +31,6 @@
  * calculations, but probably under different timing conditions, etc.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -123,4 +121,3 @@
 }
 
 #endif
-#endif
diff --git a/post/lib_ppc/cpu.c b/post/lib_ppc/cpu.c
index 4ab6d2d..5c7f761 100644
--- a/post/lib_ppc/cpu.c
+++ b/post/lib_ppc/cpu.c
@@ -32,8 +32,6 @@
  * For more details refer to post/cpu/ *.c files.
  */
 
-#ifdef CONFIG_POST
-
 #include <watchdog.h>
 #include <post.h>
 #include <asm/mmu.h>
@@ -147,4 +145,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_CPU */
-#endif /* CONFIG_POST */
diff --git a/post/lib_ppc/cr.c b/post/lib_ppc/cr.c
index da6ef37..0bd9e74 100644
--- a/post/lib_ppc/cr.c
+++ b/post/lib_ppc/cr.c
@@ -46,8 +46,6 @@
  * expected one.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -353,4 +351,3 @@
 }
 
 #endif
-#endif
diff --git a/post/lib_ppc/fpu/20001122-1.c b/post/lib_ppc/fpu/20001122-1.c
index f689b82..dece614 100644
--- a/post/lib_ppc/fpu/20001122-1.c
+++ b/post/lib_ppc/fpu/20001122-1.c
@@ -26,8 +26,6 @@
 
 #include <common.h>
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_FPU
@@ -59,4 +57,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_FPU */
-#endif /* CONFIG_POST */
diff --git a/post/lib_ppc/fpu/20010114-2.c b/post/lib_ppc/fpu/20010114-2.c
index 6e60507..8a17217 100644
--- a/post/lib_ppc/fpu/20010114-2.c
+++ b/post/lib_ppc/fpu/20010114-2.c
@@ -26,8 +26,6 @@
 
 #include <common.h>
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_FPU
@@ -63,4 +61,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_FPU */
-#endif /* CONFIG_POST */
diff --git a/post/lib_ppc/fpu/20010226-1.c b/post/lib_ppc/fpu/20010226-1.c
index b2c47e3..f366252 100644
--- a/post/lib_ppc/fpu/20010226-1.c
+++ b/post/lib_ppc/fpu/20010226-1.c
@@ -26,8 +26,6 @@
 
 #include <common.h>
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_FPU
@@ -51,4 +49,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_FPU */
-#endif /* CONFIG_POST */
diff --git a/post/lib_ppc/fpu/980619-1.c b/post/lib_ppc/fpu/980619-1.c
index 990aa0c..7f26482 100644
--- a/post/lib_ppc/fpu/980619-1.c
+++ b/post/lib_ppc/fpu/980619-1.c
@@ -26,8 +26,6 @@
 
 #include <common.h>
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_FPU
@@ -57,4 +55,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_FPU */
-#endif /* CONFIG_POST */
diff --git a/post/lib_ppc/fpu/Makefile b/post/lib_ppc/fpu/Makefile
index 82646c8..db43593 100644
--- a/post/lib_ppc/fpu/Makefile
+++ b/post/lib_ppc/fpu/Makefile
@@ -20,12 +20,12 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-
+include $(TOPDIR)/config.mk
 
 LIB	= libpostppcfpu.a
 
-COBJS	+= fpu.o 20001122-1.o 20010114-2.o 20010226-1.o 980619-1.o
-COBJS	+= acc1.o compare-fp-1.o mul-subnormal-single-1.o
+COBJS-$(CONFIG_HAS_POST)	+= fpu.o 20001122-1.o 20010114-2.o 20010226-1.o 980619-1.o
+COBJS-$(CONFIG_HAS_POST)	+= acc1.o compare-fp-1.o mul-subnormal-single-1.o
 
 include $(TOPDIR)/post/rules.mk
 
diff --git a/post/lib_ppc/fpu/acc1.c b/post/lib_ppc/fpu/acc1.c
index 4cecbf6..921282e 100644
--- a/post/lib_ppc/fpu/acc1.c
+++ b/post/lib_ppc/fpu/acc1.c
@@ -26,8 +26,6 @@
 
 #include <common.h>
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_FPU
@@ -54,4 +52,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_FPU */
-#endif /* CONFIG_POST */
diff --git a/post/lib_ppc/fpu/compare-fp-1.c b/post/lib_ppc/fpu/compare-fp-1.c
index d866ad5..be8f620 100644
--- a/post/lib_ppc/fpu/compare-fp-1.c
+++ b/post/lib_ppc/fpu/compare-fp-1.c
@@ -28,8 +28,6 @@
 
 #include <common.h>
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_FPU
@@ -222,4 +220,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_FPU */
-#endif /* CONFIG_POST */
diff --git a/post/lib_ppc/fpu/fpu.c b/post/lib_ppc/fpu/fpu.c
index 07dcba8..9ddb67a 100644
--- a/post/lib_ppc/fpu/fpu.c
+++ b/post/lib_ppc/fpu/fpu.c
@@ -34,8 +34,6 @@
  * For more details refer to post/cpu/ *.c files.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_FPU
@@ -89,4 +87,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_FPU */
-#endif /* CONFIG_POST */
diff --git a/post/lib_ppc/fpu/mul-subnormal-single-1.c b/post/lib_ppc/fpu/mul-subnormal-single-1.c
index 67f48da..7e6fe87 100644
--- a/post/lib_ppc/fpu/mul-subnormal-single-1.c
+++ b/post/lib_ppc/fpu/mul-subnormal-single-1.c
@@ -28,8 +28,6 @@
 
 #include <common.h>
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 #if CONFIG_POST & CFG_POST_FPU
@@ -100,4 +98,3 @@
 }
 
 #endif /* CONFIG_POST & CFG_POST_FPU */
-#endif /* CONFIG_POST */
diff --git a/post/lib_ppc/load.c b/post/lib_ppc/load.c
index 393c568..86bc223 100644
--- a/post/lib_ppc/load.c
+++ b/post/lib_ppc/load.c
@@ -41,8 +41,6 @@
  * register (it must change for "load with update" instructions).
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -252,4 +250,3 @@
 }
 
 #endif
-#endif
diff --git a/post/lib_ppc/multi.c b/post/lib_ppc/multi.c
index 8724384..5d3f584 100644
--- a/post/lib_ppc/multi.c
+++ b/post/lib_ppc/multi.c
@@ -33,8 +33,6 @@
  * of the source and target buffers are then compared.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -78,4 +76,3 @@
 }
 
 #endif
-#endif
diff --git a/post/lib_ppc/rlwimi.c b/post/lib_ppc/rlwimi.c
index f65f79a..1d8e61e 100644
--- a/post/lib_ppc/rlwimi.c
+++ b/post/lib_ppc/rlwimi.c
@@ -32,8 +32,6 @@
  * different sets of operand registers and result registers.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -159,4 +157,3 @@
 }
 
 #endif
-#endif
diff --git a/post/lib_ppc/rlwinm.c b/post/lib_ppc/rlwinm.c
index e240c41..113e79d 100644
--- a/post/lib_ppc/rlwinm.c
+++ b/post/lib_ppc/rlwinm.c
@@ -32,8 +32,6 @@
  * different sets of operand registers and result registers.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -152,4 +150,3 @@
 }
 
 #endif
-#endif
diff --git a/post/lib_ppc/rlwnm.c b/post/lib_ppc/rlwnm.c
index 523cf4d..a6684bf 100644
--- a/post/lib_ppc/rlwnm.c
+++ b/post/lib_ppc/rlwnm.c
@@ -32,8 +32,6 @@
  * different sets of operand registers and result registers.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -162,4 +160,3 @@
 }
 
 #endif
-#endif
diff --git a/post/lib_ppc/srawi.c b/post/lib_ppc/srawi.c
index 91c82c9..8c70007 100644
--- a/post/lib_ppc/srawi.c
+++ b/post/lib_ppc/srawi.c
@@ -32,8 +32,6 @@
  * different sets of operand registers and result registers.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -153,4 +151,3 @@
 }
 
 #endif
-#endif
diff --git a/post/lib_ppc/store.c b/post/lib_ppc/store.c
index f495bf2..09ec485 100644
--- a/post/lib_ppc/store.c
+++ b/post/lib_ppc/store.c
@@ -41,8 +41,6 @@
  * with update" instructions).
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -232,4 +230,3 @@
 }
 
 #endif
-#endif
diff --git a/post/lib_ppc/string.c b/post/lib_ppc/string.c
index bd83bd1..b2daa88 100644
--- a/post/lib_ppc/string.c
+++ b/post/lib_ppc/string.c
@@ -33,8 +33,6 @@
  * of the source and target buffers are then compared.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -103,4 +101,3 @@
 }
 
 #endif
-#endif
diff --git a/post/lib_ppc/three.c b/post/lib_ppc/three.c
index c2d7476..a7f1a86 100644
--- a/post/lib_ppc/three.c
+++ b/post/lib_ppc/three.c
@@ -35,8 +35,6 @@
  * different sets of operand registers and result registers.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -256,4 +254,3 @@
 }
 
 #endif
-#endif
diff --git a/post/lib_ppc/threei.c b/post/lib_ppc/threei.c
index 79f0178..bbb4f50 100644
--- a/post/lib_ppc/threei.c
+++ b/post/lib_ppc/threei.c
@@ -34,8 +34,6 @@
  * different sets of operand registers and result registers.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -134,4 +132,3 @@
 }
 
 #endif
-#endif
diff --git a/post/lib_ppc/threex.c b/post/lib_ppc/threex.c
index 2c72063..6aac937 100644
--- a/post/lib_ppc/threex.c
+++ b/post/lib_ppc/threex.c
@@ -35,8 +35,6 @@
  * different sets of operand registers and result registers.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -226,4 +224,3 @@
 }
 
 #endif
-#endif
diff --git a/post/lib_ppc/two.c b/post/lib_ppc/two.c
index cfbac5e..3d6b3c0 100644
--- a/post/lib_ppc/two.c
+++ b/post/lib_ppc/two.c
@@ -35,8 +35,6 @@
  * different sets of operand registers and result registers.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -173,4 +171,3 @@
 }
 
 #endif
-#endif
diff --git a/post/lib_ppc/twox.c b/post/lib_ppc/twox.c
index 48d9954..7417a36 100644
--- a/post/lib_ppc/twox.c
+++ b/post/lib_ppc/twox.c
@@ -35,8 +35,6 @@
  * different sets of operand registers and result registers.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
@@ -173,4 +171,3 @@
 }
 
 #endif
-#endif
diff --git a/post/post.c b/post/post.c
index 1df0657..c016c3a 100644
--- a/post/post.c
+++ b/post/post.c
@@ -30,8 +30,6 @@
 #include <logbuff.h>
 #endif
 
-#ifdef CONFIG_POST
-
 DECLARE_GLOBAL_DATA_PTR;
 
 #define POST_MAX_NUMBER		32
@@ -442,5 +440,3 @@
 	return 0; /* Not implemented yet */
 #endif
 }
-
-#endif /* CONFIG_POST */
diff --git a/post/rules.mk b/post/rules.mk
index e2c73c6..94e72be 100644
--- a/post/rules.mk
+++ b/post/rules.mk
@@ -23,6 +23,8 @@
 
 include $(TOPDIR)/config.mk
 
+COBJS	:= $(COBJS-y)
+AOBJS	:= $(AOBJS-y)
 SRCS 	:= $(AOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(AOBJS) $(COBJS))
 LIB	:= $(obj)$(LIB)
diff --git a/post/tests.c b/post/tests.c
index 53d01e3..36473e3 100644
--- a/post/tests.c
+++ b/post/tests.c
@@ -27,8 +27,6 @@
 
 #include <common.h>
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
 extern int cache_post_test (int flags);
@@ -278,5 +276,3 @@
 };
 
 unsigned int post_list_size = sizeof (post_list) / sizeof (struct post_test);
-
-#endif /* CONFIG_POST */
diff --git a/tools/Makefile b/tools/Makefile
index 8784a6d..b897923 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -236,7 +236,11 @@
 $(obj)environment.o:	$(obj)environment.c
 		$(CC) -g $(HOST_ENVIRO_CFLAGS) $(CPPFLAGS) -c -o $@ $<
 
-$(obj)crc32.c:
+$(obj)zlib.h:
+		@rm -f $@
+		ln -s $(src)../include/zlib.h $@
+
+$(obj)crc32.c: $(obj)zlib.h
 		@rm -f $(obj)crc32.c
 		ln -s $(src)../lib_generic/crc32.c $(obj)crc32.c
 
diff --git a/tools/envcrc.c b/tools/envcrc.c
index 7b77183..550cf82 100644
--- a/tools/envcrc.c
+++ b/tools/envcrc.c
@@ -22,6 +22,7 @@
  */
 
 #include <stdio.h>
+#include <stdint.h>
 #include <stdlib.h>
 #include <unistd.h>
 
@@ -58,15 +59,15 @@
 #endif	/* CFG_ENV_IS_IN_FLASH */
 
 #ifdef CFG_REDUNDAND_ENVIRONMENT
-# define ENV_HEADER_SIZE	(sizeof(unsigned long) + 1)
+# define ENV_HEADER_SIZE	(sizeof(uint32_t) + 1)
 #else
-# define ENV_HEADER_SIZE	(sizeof(unsigned long))
+# define ENV_HEADER_SIZE	(sizeof(uint32_t))
 #endif
 
 #define ENV_SIZE (CFG_ENV_SIZE - ENV_HEADER_SIZE)
 
 
-extern unsigned long crc32 (unsigned long, const unsigned char *, unsigned int);
+extern uint32_t crc32 (uint32_t, const unsigned char *, unsigned int);
 
 #ifdef	ENV_IS_EMBEDDED
 extern unsigned int env_size;
@@ -76,7 +77,7 @@
 int main (int argc, char **argv)
 {
 #ifdef	ENV_IS_EMBEDDED
-	int crc;
+	uint32_t crc;
 	unsigned char *envptr = &environment,
 		*dataptr = envptr + ENV_HEADER_SIZE;
 	unsigned int datasize = ENV_SIZE;
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 6e1ff2b..ea7a826 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -229,10 +229,10 @@
 		if (fdt_check_header (ptr)) {
 			/* old-style image */
 			image_verify_header ((char *)ptr, sbuf.st_size);
-			image_print_contents_noindent ((image_header_t *)ptr);
+			image_print_contents ((image_header_t *)ptr);
 		} else {
 			/* FIT image */
-			fit_print_contents_noindent (ptr);
+			fit_print_contents (ptr);
 		}
 
 		(void) munmap((void *)ptr, sbuf.st_size);
@@ -363,7 +363,7 @@
 
 	image_set_hcrc (hdr, checksum);
 
-	image_print_contents_noindent (hdr);
+	image_print_contents (hdr);
 
 	(void) munmap((void *)ptr, sbuf.st_size);