mtd: cfi: Add support for status register polling
The status register is optional in the AMD command sets, but it's
presence can be checked by reading out CFI table entry 0xc bit 0.
If the register is present, prefer using it's bit 7 to determine
if the flash is busy over reading the flash ; this is needed ie.
on Hyperflash memories.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index df04a42..8a5babe 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -544,7 +544,16 @@
#ifdef CONFIG_FLASH_CFI_LEGACY
case CFI_CMDSET_AMD_LEGACY:
#endif
- retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
+ if (info->sr_supported) {
+ flash_write_cmd (info, sect, info->addr_unlock1,
+ FLASH_CMD_READ_STATUS);
+ retval = !flash_isset (info, sect, 0,
+ FLASH_STATUS_DONE);
+ } else {
+ retval = flash_toggle (info, sect, 0,
+ AMD_STATUS_TOGGLE);
+ }
+
break;
default:
retval = 0;
@@ -1685,6 +1694,7 @@
{
ushort bankId = 0;
uchar manuId;
+ uchar lsbits;
flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
flash_unlock_seq(info, 0);
@@ -1700,6 +1710,9 @@
}
info->manufacturer_id = manuId;
+ lsbits = flash_read_uchar(info, FLASH_OFFSET_LOWER_SW_BITS);
+ info->sr_supported = lsbits & BIT(0);
+
switch (info->chipwidth){
case FLASH_CFI_8BIT:
info->device_id = flash_read_uchar (info,
diff --git a/include/flash.h b/include/flash.h
index 0eedb1e..dc67cb2 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -42,6 +42,7 @@
ushort cfi_offset; /* offset for cfi query */
ulong addr_unlock1; /* unlock address 1 for AMD flash roms */
ulong addr_unlock2; /* unlock address 2 for AMD flash roms */
+ uchar sr_supported; /* status register supported */
const char *name; /* human-readable name */
#endif
#ifdef CONFIG_MTD
diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h
index eade2b3..095725a 100644
--- a/include/mtd/cfi_flash.h
+++ b/include/mtd/cfi_flash.h
@@ -62,6 +62,7 @@
#define FLASH_OFFSET_MANUFACTURER_ID 0x00
#define FLASH_OFFSET_DEVICE_ID 0x01
+#define FLASH_OFFSET_LOWER_SW_BITS 0x0C
#define FLASH_OFFSET_DEVICE_ID2 0x0E
#define FLASH_OFFSET_DEVICE_ID3 0x0F
#define FLASH_OFFSET_CFI 0x55