diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi
index 7dd2858..8b179ba 100644
--- a/arch/arm/dts/bcm63158.dtsi
+++ b/arch/arm/dts/bcm63158.dtsi
@@ -1,122 +1,167 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
+ * Copyright 2022 Broadcom Ltd.
  */
 
-#include "skeleton64.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
-	compatible = "brcm,bcm63158";
+	compatible = "brcm,bcm63158", "brcm,bcmbca";
 	#address-cells = <2>;
 	#size-cells = <2>;
 
-	aliases {
-		spi0 = &hsspi;
-	};
+	interrupt-parent = <&gic>;
 
 	cpus {
 		#address-cells = <2>;
 		#size-cells = <0>;
-		u-boot,dm-pre-reloc;
 
-		cpu0: cpu@0 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+		B53_0: cpu@0 {
+			compatible = "brcm,brahma-b53";
 			device_type = "cpu";
 			reg = <0x0 0x0>;
-			next-level-cache = <&l2>;
-			u-boot,dm-pre-reloc;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
 		};
 
-		cpu1: cpu@1 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+		B53_1: cpu@1 {
+			compatible = "brcm,brahma-b53";
 			device_type = "cpu";
 			reg = <0x0 0x1>;
-			next-level-cache = <&l2>;
-			u-boot,dm-pre-reloc;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
 		};
 
-		cpu2: cpu@2 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+		B53_2: cpu@2 {
+			compatible = "brcm,brahma-b53";
 			device_type = "cpu";
 			reg = <0x0 0x2>;
-			next-level-cache = <&l2>;
-			u-boot,dm-pre-reloc;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
 		};
 
-		cpu3: cpu@3 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+		B53_3: cpu@3 {
+			compatible = "brcm,brahma-b53";
 			device_type = "cpu";
 			reg = <0x0 0x3>;
-			next-level-cache = <&l2>;
-			u-boot,dm-pre-reloc;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
 		};
 
-		l2: l2-cache0 {
+		L2_0: l2-cache0 {
 			compatible = "cache";
-			u-boot,dm-pre-reloc;
 		};
 	};
 
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	pmu: pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&B53_0>, <&B53_1>,
+			<&B53_2>, <&B53_3>;
+	};
+
 	clocks {
-		compatible = "simple-bus";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
 		u-boot,dm-pre-reloc;
-
-		periph_osc: periph-osc {
+		periph_clk: periph-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <0xbebc200>;
-			u-boot,dm-pre-reloc;
+			clock-frequency = <200000000>;
 		};
 
 		hsspi_pll: hsspi-pll {
 			compatible = "fixed-factor-clock";
 			#clock-cells = <0>;
-			clocks = <&periph_osc>;
+			clocks = <&periph_clk>;
 			clock-mult = <2>;
 			clock-div = <1>;
 		};
 
-		refclk50mhz: refclk50mhz {
-			compatible = "fixed-clock";
+		uart_clk: uart-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_clk>;
+			clock-div = <4>;
+			clock-mult = <1>;
+		};
+
+		wdt_clk: wdt-clk {
+			compatible = "fixed-factor-clock";
 			#clock-cells = <0>;
-			clock-frequency = <50000000>;
+			clocks = <&periph_clk>;
+			clock-div = <4>;
+			clock-mult = <1>;
 		};
 	};
 
-	ubus {
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	axi@81000000 {
 		compatible = "simple-bus";
-		#address-cells = <2>;
-		#size-cells = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x81000000 0x8000>;
+
+		gic: interrupt-controller@1000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			reg = <0x1000 0x1000>,
+				<0x2000 0x2000>,
+				<0x4000 0x2000>,
+				<0x6000 0x2000>;
+		};
+	};
+
+	bus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0xff800000 0x800000>;
 		u-boot,dm-pre-reloc;
 
-		uart0: serial@ff812000 {
+		uart0: serial@12000 {
 			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x0 0xff812000 0x0 0x1000>;
-			clock = <50000000>;
-
+			reg = <0x12000 0x1000>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_clk>, <&uart_clk>;
+			clock-names = "uartclk", "apb_pclk";
 			status = "disabled";
 		};
 
-		leds: led-controller@ff800800 {
+		leds: led-controller@800 {
 			compatible = "brcm,bcm6858-leds";
-			reg = <0x0 0xff800800 0x0 0xe4>;
+			reg = <0x800 0xe4>;
 
 			status = "disabled";
 		};
 
-		wdt1: watchdog@ff800480 {
+		wdt1: watchdog@480 {
 			compatible = "brcm,bcm6345-wdt";
-			reg = <0x0 0xff800480 0x0 0x14>;
-			clocks = <&refclk50mhz>;
+			reg = <0x480 0x14>;
+			clocks = <&wdt_clk>;
 		};
 
-		wdt2: watchdog@ff8004c0 {
+		wdt2: watchdog@4c0 {
 			compatible = "brcm,bcm6345-wdt";
-			reg = <0x0 0xff8004c0 0x0 0x14>;
-			clocks = <&refclk50mhz>;
+			reg = <0x4c0 0x14>;
+			clocks = <&wdt_clk>;
 		};
 
 		wdt-reboot {
@@ -124,91 +169,91 @@
 			wdt = <&wdt1>;
 		};
 
-		gpio0: gpio-controller@0xff800500 {
+		gpio0: gpio-controller@500 {
 			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff800500 0x0 0x4>,
-			      <0x0 0xff800520 0x0 0x4>;
+			reg = <0x500 0x4>,
+			      <0x520 0x4>;
 			gpio-controller;
 			#gpio-cells = <2>;
 
 			status = "disabled";
 		};
 
-		gpio1: gpio-controller@0xff800504 {
+		gpio1: gpio-controller@504 {
 			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff800504 0x0 0x4>,
-			      <0x0 0xff800524 0x0 0x4>;
+			reg = <0x504 0x4>,
+			      <0x524 0x4>;
 			gpio-controller;
 			#gpio-cells = <2>;
 
 			status = "disabled";
 		};
 
-		gpio2: gpio-controller@0xff800508 {
+		gpio2: gpio-controller@508 {
 			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff800508 0x0 0x4>,
-			      <0x0 0xff800528 0x0 0x4>;
+			reg = <0x508 0x4>,
+			      <0x528 0x4>;
 			gpio-controller;
 			#gpio-cells = <2>;
 
 			status = "disabled";
 		};
 
-		gpio3: gpio-controller@0xff80050c {
+		gpio3: gpio-controller@50c {
 			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff80050c 0x0 0x4>,
-			      <0x0 0xff80052c 0x0 0x4>;
+			reg = <0x50c 0x4>,
+			      <0x52c 0x4>;
 			gpio-controller;
 			#gpio-cells = <2>;
 
 			status = "disabled";
 		};
 
-		gpio4: gpio-controller@0xff800510 {
+		gpio4: gpio-controller@510 {
 			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff800510 0x0 0x4>,
-			      <0x0 0xff800530 0x0 0x4>;
+			reg = <0x510 0x4>,
+			      <0x530 0x4>;
 			gpio-controller;
 			#gpio-cells = <2>;
 
 			status = "disabled";
 		};
 
-		gpio5: gpio-controller@0xff800514 {
+		gpio5: gpio-controller@514 {
 			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff800514 0x0 0x4>,
-			      <0x0 0xff800534 0x0 0x4>;
+			reg = <0x514 0x4>,
+			      <0x534 0x4>;
 			gpio-controller;
 			#gpio-cells = <2>;
 
 			status = "disabled";
 		};
 
-		gpio6: gpio-controller@0xff800518 {
+		gpio6: gpio-controller@518 {
 			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff800518 0x0 0x4>,
-			      <0x0 0xff800538 0x0 0x4>;
+			reg = <0x518 0x4>,
+			      <0x538 0x4>;
 			gpio-controller;
 			#gpio-cells = <2>;
 
 			status = "disabled";
 		};
 
-		gpio7: gpio-controller@0xff80051c {
+		gpio7: gpio-controller@51c {
 			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff80051c 0x0 0x4>,
-			      <0x0 0xff80053c 0x0 0x4>;
+			reg = <0x51c 0x4>,
+			      <0x53c 0x4>;
 			gpio-controller;
 			#gpio-cells = <2>;
 
 			status = "disabled";
 		};
 
-		hsspi: spi-controller@ff801000 {
+		hsspi: spi-controller@1000 {
 			compatible = "brcm,bcm6328-hsspi";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <0x0 0xff801000 0x0 0x600>;
+			reg = <0x1000 0x600>;
 			clocks = <&hsspi_pll>, <&hsspi_pll>;
 			clock-names = "hsspi", "pll";
 			spi-max-frequency = <100000000>;
@@ -217,14 +262,14 @@
 			status = "disabled";
 		};
 
-		nand: nand-controller@ff801800 {
+		nand: nand-controller@1800 {
 			compatible = "brcm,nand-bcm63158",
 				     "brcm,brcmnand-v5.0",
 				     "brcm,brcmnand";
 			reg-names = "nand", "nand-int-base", "nand-cache";
-			reg = <0x0 0xff801800 0x0 0x180>,
-			      <0x0 0xff802000 0x0 0x10>,
-			      <0x0 0xff801c00 0x0 0x200>;
+			reg = <0x1800 0x180>,
+			      <0x2000 0x10>,
+			      <0x1c00 0x200>;
 			parameter-page-big-endian = <0>;
 
 			status = "disabled";