| commit | 99b58708bbb03376d74d7aa75ac47f322e82011f | [log] [tgz] |
|---|---|---|
| author | Christoph G. Baumann <c.baumann@ppc-ag.de> | Mon Oct 28 12:29:31 2013 +0100 |
| committer | Stefano Babic <sbabic@denx.de> | Thu Oct 31 17:54:23 2013 +0100 |
| tree | c047693a9974b64722eb83e031a15e1b6209f608 | |
| parent | 4cf9ce45e3ae4995da70f110fa10845589bda959 [diff] |
ARM: mxs: Configure 2 Gbit DDR2 RAM for BG0900 The BG0900 module has 2Gbit DRAM module on it, adjust the DataBahn DRAM controller registers so the DRAM module will be correctly recognised. Signed-off-by: Christoph G. Baumann <c.baumann@ppc-ag.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>