diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 6a4128c..64431ab 100644
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -437,11 +437,11 @@
 	 * The PCI initialization sequence enable bit must be set ... if not abort
 	 * pci setup since updating the bit requires chip reset.
 	 *--------------------------------------------------------------------------*/
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
 	unsigned long strap;
 
 	mfsdr(sdr_sdstp1,strap);
-	if ( (strap & 0x00010000) == 0 ){
+	if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
 		printf("PCI: SDR0_STRP1[PISE] not set.\n");
 		printf("PCI: Configuration aborted.\n");
 		return;
@@ -450,7 +450,7 @@
 	unsigned long strap;
 
 	strap = mfdcr(cpc0_strp1);
-	if( (strap & 0x00040000) == 0 ){
+	if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
 		printf("PCI: CPC0_STRP1[PISE] not set.\n");
 		printf("PCI: Configuration aborted.\n");
 		return;
@@ -466,26 +466,26 @@
 
 	pci_set_region(hose->regions + reg_num++,
 		       0x00000000,
-			   PCIX0_IOBASE,
-			   0x10000,
-			   PCI_REGION_IO);
+		       PCIX0_IOBASE,
+		       0x10000,
+		       PCI_REGION_IO);
 
 	pci_set_region(hose->regions + reg_num++,
 		       CFG_PCI_TARGBASE,
-			   CFG_PCI_MEMBASE,
-			   0x10000000,
-			   PCI_REGION_MEM );
+		       CFG_PCI_MEMBASE,
+		       0x10000000,
+		       PCI_REGION_MEM );
 	hose->region_count = reg_num;
 
 	pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
 
 #if defined(CFG_PCI_PRE_INIT)
-    /* Let board change/modify hose & do initial checks */
-    if( pci_pre_init (hose) == 0 ){
-	printf("PCI: Board-specific initialization failed.\n");
-	printf("PCI: Configuration aborted.\n");
-	return;
-    }
+	/* Let board change/modify hose & do initial checks */
+	if (pci_pre_init (hose) == 0) {
+		printf("PCI: Board-specific initialization failed.\n");
+		printf("PCI: Configuration aborted.\n");
+		return;
+	}
 #endif
 
 	pci_register_hose( hose );
@@ -496,9 +496,9 @@
 #if defined(CFG_PCI_TARGET_INIT)
 	pci_target_init(hose);                /* Let board setup pci target */
 #else
-    out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
-    out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
-    out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
+	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
+	out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
 #endif
 
 #if defined(CONFIG_440GX)
@@ -524,24 +524,24 @@
 	out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
 	out32r( PCIX0_POM0PCIAH, 0x00000000 );
 	out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
-    out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
+	out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
 #endif
 
 	/*--------------------------------------------------------------------------+
 	 * PCI host configuration -- we don't make any assumptions here ... the
-     * _board_must_indicate_ what to do -- there's just too many runtime
-     * scenarios in environments like cPCI, PPMC, etc. to make a determination
-     * based on hard-coded values or state of arbiter enable.
+	 * _board_must_indicate_ what to do -- there's just too many runtime
+	 * scenarios in environments like cPCI, PPMC, etc. to make a determination
+	 * based on hard-coded values or state of arbiter enable.
 	 *--------------------------------------------------------------------------*/
-    if( is_pci_host(hose) ){
+	if (is_pci_host(hose)) {
 #ifdef CONFIG_PCI_SCAN_SHOW
-	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+		printf("PCI:   Bus Dev VenId DevId Class Int\n");
 #endif
 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
-	out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
+		out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
 #endif
-	hose->last_busno = pci_hose_scan(hose);
-    }
+		hose->last_busno = pci_hose_scan(hose);
+	}
 }