| commit | 9954cd15660bec09e1c0bdc6cc2502f094145374 | [log] [tgz] |
|---|---|---|
| author | Shaohui Xie <Shaohui.Xie@freescale.com> | Tue Sep 13 17:51:39 2011 +0800 |
| committer | Kumar Gala <galak@kernel.crashing.org> | Mon Oct 03 08:29:54 2011 -0500 |
| tree | 7a6bd82233c3f92e547ba4a0e87170c57ffaa908 | |
| parent | c3c301e664b0dd17afc5042f81e1671fb3ade2fb [diff] |
powerpc/p2041rdb: update cpld reset command according to CPLD 2.0 CPLD 2.0 provides a new register which bit[0] is set to '1' will reset board with initializing the CPLD registers to default values. And add bit[6] of register at offset 0x5 to use to enable flash bank selection. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>