tree 91218ae8474793be1d2a49b9b8078b1b7486bff7
parent b3022409ffe9670ac8fdb4342103f4f7b0824fbf
author Roy Zang <tie-fei.zang@freescale.com> 1231488155 +0800
committer Andrew Fleming-AFLEMING <afleming@freescale.com> 1231885973 -0600

Change PCIE1&2 deciide logic on MPC8544DS board more readable

The IO port selection for MPC8544DS board:
 Port			cfg_io_ports
 PCIE1		0x2, 0x3, 0x4, 0x5, 0x6, 0x7
 PCIE2		0x4, 0x5, 0x6, 0x7
 PCIE3		0x6, 0x7
 This patch changes the PCIE12 and PCIE2 logic more readable.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>