arch: arm: Agilex5 enablement
This patch is to enable Agilex5 platform for Intel
product. Changes, modification and new files are
created for board, dts, configs and makefile to
create the base for Agilex5.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
diff --git a/include/dt-bindings/clock/agilex5-clock.h b/include/dt-bindings/clock/agilex5-clock.h
new file mode 100644
index 0000000..c84fa51
--- /dev/null
+++ b/include/dt-bindings/clock/agilex5-clock.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024, Intel Corporation
+ */
+
+#ifndef __AGILEX5_CLOCK_H
+#define __AGILEX5_CLOCK_H
+
+/* fixed rate clocks */
+#define AGILEX5_OSC1 0
+#define AGILEX5_CB_INTOSC_HS_DIV2_CLK 1
+#define AGILEX5_CB_INTOSC_LS_CLK 2
+#define AGILEX5_L4_SYS_FREE_CLK 3
+#define AGILEX5_F2S_FREE_CLK 4
+
+/* PLL clocks */
+#define AGILEX5_MAIN_PLL_CLK 5
+#define AGILEX5_MAIN_PLL_C0_CLK 6
+#define AGILEX5_MAIN_PLL_C1_CLK 7
+#define AGILEX5_MAIN_PLL_C2_CLK 8
+#define AGILEX5_MAIN_PLL_C3_CLK 9
+#define AGILEX5_PERIPH_PLL_CLK 10
+#define AGILEX5_PERIPH_PLL_C0_CLK 11
+#define AGILEX5_PERIPH_PLL_C1_CLK 12
+#define AGILEX5_PERIPH_PLL_C2_CLK 13
+#define AGILEX5_PERIPH_PLL_C3_CLK 14
+#define AGILEX5_MPU_FREE_CLK 15
+#define AGILEX5_MPU_CCU_CLK 16
+#define AGILEX5_BOOT_CLK 17
+
+/* fixed factor clocks */
+#define AGILEX5_L3_MAIN_FREE_CLK 18
+#define AGILEX5_NOC_FREE_CLK 19
+#define AGILEX5_S2F_USR0_CLK 20
+#define AGILEX5_NOC_CLK 21
+#define AGILEX5_EMAC_A_FREE_CLK 22
+#define AGILEX5_EMAC_B_FREE_CLK 23
+#define AGILEX5_EMAC_PTP_FREE_CLK 24
+#define AGILEX5_GPIO_DB_FREE_CLK 25
+#define AGILEX5_SDMMC_FREE_CLK 26
+#define AGILEX5_S2F_USER0_FREE_CLK 27
+#define AGILEX5_S2F_USER1_FREE_CLK 28
+#define AGILEX5_PSI_REF_FREE_CLK 29
+
+/* Gate clocks */
+#define AGILEX5_MPU_CLK 30
+#define AGILEX5_MPU_PERIPH_CLK 31
+#define AGILEX5_L4_MAIN_CLK 32
+#define AGILEX5_L4_MP_CLK 33
+#define AGILEX5_L4_SP_CLK 34
+#define AGILEX5_CS_AT_CLK 35
+#define AGILEX5_CS_TRACE_CLK 36
+#define AGILEX5_CS_PDBG_CLK 37
+#define AGILEX5_CS_TIMER_CLK 38
+#define AGILEX5_S2F_USER0_CLK 39
+#define AGILEX5_EMAC0_CLK 40
+#define AGILEX5_EMAC1_CLK 41
+#define AGILEX5_EMAC2_CLK 42
+#define AGILEX5_EMAC_PTP_CLK 43
+#define AGILEX5_GPIO_DB_CLK 44
+#define AGILEX5_NAND_CLK 45
+#define AGILEX5_PSI_REF_CLK 46
+#define AGILEX5_S2F_USER1_CLK 47
+#define AGILEX5_SDMMC_CLK 48
+#define AGILEX5_SPI_M_CLK 49
+#define AGILEX5_USB_CLK 50
+#define AGILEX5_NAND_X_CLK 51
+#define AGILEX5_NAND_ECC_CLK 52
+#define AGILEX5_NUM_CLKS 53
+
+#endif /* __AGILEX5_CLOCK_H */
diff --git a/include/dt-bindings/reset/altr,rst-mgr-agx5.h b/include/dt-bindings/reset/altr,rst-mgr-agx5.h
new file mode 100644
index 0000000..1dba270
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-agx5.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 Intel Corporation. All rights reserved
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H
+
+/* PER0MODRST */
+#define EMAC0_RESET 0
+#define EMAC1_RESET 1
+#define EMAC2_RESET 2
+#define USB0_RESET 3
+#define USB1_RESET 4
+#define NAND_RESET 5
+#define COMBOPHY_RESET 6
+#define SDMMC_RESET 7
+#define EMAC0_OCP_RESET 8
+#define EMAC1_OCP_RESET 9
+#define EMAC2_OCP_RESET 10
+#define USB0_OCP_RESET 11
+#define USB1_OCP_RESET 12
+#define NAND_OCP_RESET 13
+/* 14 is empty */
+#define SDMMC_OCP_RESET 15
+#define DMA_RESET 16
+#define SPIM0_RESET 17
+#define SPIM1_RESET 18
+#define SPIS0_RESET 19
+#define SPIS1_RESET 20
+#define DMA_OCP_RESET 21
+#define EMAC_PTP_RESET 22
+/* 23 is empty*/
+#define DMAIF0_RESET 24
+#define DMAIF1_RESET 25
+#define DMAIF2_RESET 26
+#define DMAIF3_RESET 27
+#define DMAIF4_RESET 28
+#define DMAIF5_RESET 29
+#define DMAIF6_RESET 30
+#define DMAIF7_RESET 31
+
+/* PER1MODRST */
+#define WATCHDOG0_RESET 32
+#define WATCHDOG1_RESET 33
+#define WATCHDOG2_RESET 34
+#define WATCHDOG3_RESET 35
+#define L4SYSTIMER0_RESET 36
+#define L4SYSTIMER1_RESET 37
+#define SPTIMER0_RESET 38
+#define SPTIMER1_RESET 39
+#define I2C0_RESET 40
+#define I2C1_RESET 41
+#define I2C2_RESET 42
+#define I2C3_RESET 43
+#define I2C4_RESET 44
+#define I3C0_RESET 45
+#define I3C1_RESET 46
+/* 47 is empty */
+#define UART0_RESET 48
+#define UART1_RESET 49
+/* 50-55 is empty */
+#define GPIO0_RESET 56
+#define GPIO1_RESET 57
+#define WATCHDOG4_RESET 58
+/* 59-63 is empty */
+
+/* BRGMODRST */
+#define SOC2FPGA_RESET 64
+#define LWHPS2FPGA_RESET 65
+#define FPGA2SOC_RESET 66
+#define F2SSDRAM_RESET 67
+/* 68-69 is empty */
+#define DDRSCH_RESET 70
+/* 71-95 is empty */
+
+/* DBGMODRST */
+#define DBG_RESET 192
+
+#endif