mx5 clocks: Fix get_periph_clk()
In the case periph_clk comes from periph_apm_clk, the latter is selected by the
CCM.CBCMR.periph_apm_sel mux, which can source the lp_apm clock from its
input ♯2. get_periph_clk() returned 0 instead of the lp_apm clock frequency in
this case.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 8c71a51..e6eae7e 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -240,6 +240,26 @@
#endif
/*
+ * This function returns the low power audio clock.
+ */
+static u32 get_lp_apm(void)
+{
+ u32 ret_val = 0;
+ u32 ccsr = readl(&mxc_ccm->ccsr);
+
+ if (ccsr & MXC_CCM_CCSR_LP_APM)
+#if defined(CONFIG_MX51)
+ ret_val = get_fpm();
+#elif defined(CONFIG_MX53)
+ ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
+#endif
+ else
+ ret_val = MXC_HCLK;
+
+ return ret_val;
+}
+
+/*
* Get mcu main rate
*/
u32 get_mcu_main_clk(void)
@@ -267,6 +287,8 @@
return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
case 1:
return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
+ case 2:
+ return get_lp_apm();
default:
return 0;
}
@@ -336,26 +358,6 @@
}
/*
- * This function returns the low power audio clock.
- */
-static u32 get_lp_apm(void)
-{
- u32 ret_val = 0;
- u32 ccsr = readl(&mxc_ccm->ccsr);
-
- if (ccsr & MXC_CCM_CCSR_LP_APM)
-#if defined(CONFIG_MX51)
- ret_val = get_fpm();
-#elif defined(CONFIG_MX53)
- ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
-#endif
- else
- ret_val = MXC_HCLK;
-
- return ret_val;
-}
-
-/*
* get cspi clock rate.
*/
static u32 imx_get_cspiclk(void)