diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 2238c52..3d38d08 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -278,6 +278,25 @@
 	wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
 }
 
+static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
+{
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	dpll_param *ptr = (dpll_param *) get_per2_dpll_param();
+
+	/* Moving it to the right sysclk base */
+	ptr = ptr + clk_index;
+
+	/* PER2 DPLL (DPLL5) */
+	sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
+	wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
+	sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
+	sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
+	sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
+	sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);   /* FREQSEL */
+	sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK);   /* lock mode */
+	wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
+}
+
 static void mpu_init_34xx(u32 sil_index, u32 clk_index)
 {
 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
@@ -587,6 +606,7 @@
 
 		dpll3_init_34xx(sil_index, clk_index);
 		dpll4_init_34xx(sil_index, clk_index);
+		dpll5_init_34xx(sil_index, clk_index);
 		iva_init_34xx(sil_index, clk_index);
 		mpu_init_34xx(sil_index, clk_index);
 
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index 109481e..1458072 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -360,6 +360,28 @@
 	adr	r0, per_dpll_param
 	mov	pc, lr
 
+/* PER2 DPLL values */
+per2_dpll_param:
+/* 12MHz */
+.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
+
+/* 13MHz */
+.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
+
+/* 19.2MHz */
+.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
+
+/* 26MHz */
+.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
+
+/* 38.4MHz */
+.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
+
+.globl get_per2_dpll_param
+get_per2_dpll_param:
+	adr	r0, per2_dpll_param
+	mov	pc, lr
+
 /*
  * Tables for 36XX/37XX devices
  *
diff --git a/arch/arm/include/asm/arch-omap3/clocks.h b/arch/arm/include/asm/arch-omap3/clocks.h
index 40f80ba..bed0002 100644
--- a/arch/arm/include/asm/arch-omap3/clocks.h
+++ b/arch/arm/include/asm/arch-omap3/clocks.h
@@ -68,6 +68,7 @@
 extern dpll_param *get_iva_dpll_param(void);
 extern dpll_param *get_core_dpll_param(void);
 extern dpll_param *get_per_dpll_param(void);
+extern dpll_param *get_per2_dpll_param(void);
 
 extern dpll_param *get_36x_mpu_dpll_param(void);
 extern dpll_param *get_36x_iva_dpll_param(void);
diff --git a/arch/arm/include/asm/arch-omap3/clocks_omap3.h b/arch/arm/include/asm/arch-omap3/clocks_omap3.h
index 30ef690..ef600dd 100644
--- a/arch/arm/include/asm/arch-omap3/clocks_omap3.h
+++ b/arch/arm/include/asm/arch-omap3/clocks_omap3.h
@@ -282,6 +282,32 @@
 #define PER_FSEL_38P4		0x07
 #define PER_M2_38P4		0x09
 
+/* PER2 DPLL */
+#define PER2_M_12		0x78
+#define PER2_N_12		0x0B
+#define PER2_FSEL_12		0x03
+#define PER2_M2_12		0x01
+
+#define PER2_M_13		0x78
+#define PER2_N_13		0x0C
+#define PER2_FSEL_13		0x03
+#define PER2_M2_13		0x01
+
+#define PER2_M_19P2		0x2EE
+#define PER2_N_19P2		0x0B
+#define PER2_FSEL_19P2		0x06
+#define PER2_M2_19P2		0x0A
+
+#define PER2_M_26		0x78
+#define PER2_N_26		0x0C
+#define PER2_FSEL_26		0x03
+#define PER2_M2_26		0x01
+
+#define PER2_M_38P4		0x2EE
+#define PER2_N_38P4		0x0B
+#define PER2_FSEL_38P4		0x06
+#define PER2_M2_38P4		0x0A
+
 /* 36XX PER DPLL */
 
 #define PER_36XX_M_12		0x1B0
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
index 962d6d4..e944de7 100644
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -347,10 +347,13 @@
 	u32 clksel2_pll_mpu;	/* 0x944 */
 	u8 res6[0xb8];
 	u32 fclken1_core;	/* 0xa00 */
-	u8 res7[0xc];
+	u32 res_fclken2_core;
+	u32 fclken3_core;	/* 0xa08 */
+	u8 res7[0x4];
 	u32 iclken1_core;	/* 0xa10 */
 	u32 iclken2_core;	/* 0xa14 */
-	u8 res8[0x28];
+	u32 iclken3_core;	/* 0xa18 */
+	u8 res8[0x24];
 	u32 clksel_core;	/* 0xa40 */
 	u8 res9[0xbc];
 	u32 fclken_gfx;		/* 0xb00 */
@@ -368,13 +371,17 @@
 	u32 clksel_wkup;	/* 0xc40 */
 	u8 res16[0xbc];
 	u32 clken_pll;		/* 0xd00 */
-	u8 res17[0x1c];
+	u32 clken2_pll;	        /* 0xd04 */
+	u8 res17[0x18];
 	u32 idlest_ckgen;	/* 0xd20 */
-	u8 res18[0x1c];
+	u32 idlest2_ckgen;	/* 0xd24 */
+	u8 res18[0x18];
 	u32 clksel1_pll;	/* 0xd40 */
 	u32 clksel2_pll;	/* 0xd44 */
 	u32 clksel3_pll;	/* 0xd48 */
-	u8 res19[0xb4];
+	u32 clksel4_pll;	/* 0xd4c */
+	u32 clksel5_pll;	/* 0xd50 */
+	u8 res19[0xac];
 	u32 fclken_dss;		/* 0xe00 */
 	u8 res20[0xc];
 	u32 iclken_dss;		/* 0xe10 */
@@ -394,6 +401,10 @@
 	u32 clksel_per;		/* 0x1040 */
 	u8 res28[0xfc];
 	u32 clksel1_emu;	/* 0x1140 */
+	u8 res29[0x2bc];
+	u32 fclken_usbhost;	/* 0x1400 */
+	u8 res30[0xc];
+	u32 iclken_usbhost;	/* 0x1410 */
 };
 #else /* __ASSEMBLY__ */
 #define CM_CLKSEL_CORE		0x48004a40