arm: mach: imx: Remove duplicate newlines
Drop all duplicate newlines. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c
index b368db4..7b3eacb 100644
--- a/arch/arm/mach-imx/cache.c
+++ b/arch/arm/mach-imx/cache.c
@@ -86,7 +86,6 @@
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
unsigned int val, cache_id;
-
/*
* Must disable the L2 before changing the latency parameters
* and auxiliary control register.
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 627baa1..accba50 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -519,7 +519,6 @@
board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
&phys_sdram_2_start, &phys_sdram_2_size);
-
end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
for (mr = 0; mr < 64; mr++) {
err = get_owned_memreg(mr, &start, &end);
@@ -699,7 +698,6 @@
board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
&phys_sdram_2_start, &phys_sdram_2_size);
-
end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
index 7e6c374..43e677d 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
@@ -733,7 +733,6 @@
return 0;
}
-
int clock_init(void)
{
u32 grade;
diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c
index ab5de26..03e1214 100644
--- a/arch/arm/mach-imx/mx6/litesom.c
+++ b/arch/arm/mach-imx/mx6/litesom.c
@@ -83,7 +83,6 @@
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
-
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
.grp_addds = 0x00000030,
.grp_ddrmode_ctl = 0x00020000,
diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c
index d4fb538..59da730 100644
--- a/arch/arm/mach-imx/mx7ulp/scg.c
+++ b/arch/arm/mach-imx/mx7ulp/scg.c
@@ -428,7 +428,6 @@
return rate;
}
-
static enum scg_clk scg_scs_array[4] = {
SCG_SOSC_CLK, SCG_SIRC_CLK, SCG_FIRC_CLK, SCG_ROSC_CLK,
};
@@ -807,7 +806,6 @@
return 0;
}
-
/* A7 domain system clock source is SPLL */
#define SCG1_RCCR_SCS_NUM ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT)