// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for KV260 revA Carrier Card
 *
 * (C) Copyright 2020, Xilinx, Inc.
 *
 * SD level shifter:
 * "A" – A01 board un-modified (NXP)
 * "Y" – A01 board modified with legacy interposer (Nexperia)
 * "Z" – A01 board modified with Diode interposer
 *
 * Michal Simek <michal.simek@xilinx.com>
 */

 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/net/ti-dp83867.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>

/dts-v1/;
/plugin/;

/{
	compatible = "xlnx,zynqmp-sk-kv260-revA",
		     "xlnx,zynqmp-sk-kv260-revY",
		     "xlnx,zynqmp-sk-kv260-revZ",
		     "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";

	fragment1 {
		target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */

		__overlay__ {
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default", "gpio";
			pinctrl-0 = <&pinctrl_i2c1_default>;
			pinctrl-1 = <&pinctrl_i2c1_gpio>;
			scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
			sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;

			u14: ina260@40 { /* u14 */
				compatible = "ti,ina260";
				#io-channel-cells = <1>;
				label = "ina260-u14";
				reg = <0x40>;
			};
			/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
		};
	};

	fragment1a {
		target = <&amba>;
		__overlay__ {
			ina260-u14 {
				compatible = "iio-hwmon";
				io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
			};

			si5332_0: si5332_0 { /* u17 */
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <125000000>;
			};

			si5332_1: si5332_1 { /* u17 */
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <25000000>;
			};

			si5332_2: si5332_2 { /* u17 */
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <48000000>;
			};

			si5332_3: si5332_3 { /* u17 */
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <24000000>;
			};

			si5332_4: si5332_4 { /* u17 */
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <26000000>;
			};

			si5332_5: si5332_5 { /* u17 */
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <27000000>;
			};
		};
	};

/* DP/USB 3.0 and SATA */
	fragment2 {
		target = <&psgtr>;
		__overlay__ {
			status = "okay";
			/* pcie, usb3, sata */
			clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
			clock-names = "ref0", "ref1", "ref2";
		};
	};

	fragment3 {
		target = <&sata>;
		__overlay__ {
			status = "okay";
			/* SATA OOB timing settings */
			ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
			ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
			ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
			ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
			ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
			ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
			ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
			ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
			phy-names = "sata-phy";
			phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
		};
	};

	fragment4 {
		target = <&zynqmp_dpsub>;
		__overlay__ {
			status = "disabled";
			phy-names = "dp-phy0", "dp-phy1";
			phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
		};
	};

	fragment9 {
		target = <&zynqmp_dpdma>;
		__overlay__ {
			status = "okay";
		};
	};

	fragment10 {
		target = <&usb0>;
		__overlay__ {
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0_default>;
			usbhub: usb5744 { /* u43 */
				compatible = "microchip,usb5744";
				reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
			};
		};
	};

	fragment11 {
		target = <&dwc3_0>;
		__overlay__ {
			status = "okay";
			dr_mode = "host";
			snps,usb3_lpm_capable;
			phy-names = "usb3-phy";
			phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
			maximum-speed = "super-speed";
		};
	};

	fragment12 {
		target = <&sdhci1>; /* on CC with tuned parameters */
		__overlay__ {
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_sdhci1_default>;
			/*
			 * SD 3.0 requires level shifter and this property
			 * should be removed if the board has level shifter and
			 * need to work in UHS mode
			 */
			no-1-8-v;
			disable-wp;
			xlnx,mio-bank = <1>;
		};
	};

	fragment13 {
		target = <&gem3>; /* required by spec */
		__overlay__ {
			#address-cells = <1>;
			#size-cells = <0>;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_gem3_default>;
			phy-handle = <&phy0>;
			phy-mode = "rgmii-id";

			mdio: mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
				reset-delay-us = <2>;

				phy0: ethernet-phy@1 {
					#phy-cells = <1>;
					reg = <1>;
					ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
					ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
					ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
					ti,dp83867-rxctrl-strap-quirk;
				};
			};
		};
	};

	fragment14 {
		target = <&pinctrl0>; /* required by spec */
		__overlay__ {
			status = "okay";

			pinctrl_uart1_default: uart1-default {
				conf {
					groups = "uart1_9_grp";
					slew-rate = <SLEW_RATE_SLOW>;
					power-source = <IO_STANDARD_LVCMOS18>;
					drive-strength = <12>;
				};

				conf-rx {
					pins = "MIO37";
					bias-high-impedance;
				};

				conf-tx {
					pins = "MIO36";
					bias-disable;
				};

				mux {
					groups = "uart1_9_grp";
					function = "uart1";
				};
			};

			pinctrl_i2c1_default: i2c1-default {
				conf {
					groups = "i2c1_6_grp";
					bias-pull-up;
					slew-rate = <SLEW_RATE_SLOW>;
					power-source = <IO_STANDARD_LVCMOS18>;
				};

				mux {
					groups = "i2c1_6_grp";
					function = "i2c1";
				};
			};

			pinctrl_i2c1_gpio: i2c1-gpio {
				conf {
					groups = "gpio0_24_grp", "gpio0_25_grp";
					slew-rate = <SLEW_RATE_SLOW>;
					power-source = <IO_STANDARD_LVCMOS18>;
				};

				mux {
					groups = "gpio0_24_grp", "gpio0_25_grp";
					function = "gpio0";
				};
			};

			pinctrl_gem3_default: gem3-default {
				conf {
					groups = "ethernet3_0_grp";
					slew-rate = <SLEW_RATE_SLOW>;
					power-source = <IO_STANDARD_LVCMOS18>;
				};

				conf-rx {
					pins = "MIO70", "MIO72", "MIO74";
					bias-high-impedance;
					low-power-disable;
				};

				conf-bootstrap {
					pins = "MIO71", "MIO73", "MIO75";
					bias-disable;
					low-power-disable;
				};

				conf-tx {
					pins = "MIO64", "MIO65", "MIO66",
					       "MIO67", "MIO68", "MIO69";
					bias-disable;
					low-power-enable;
				};

				conf-mdio {
					groups = "mdio3_0_grp";
					slew-rate = <SLEW_RATE_SLOW>;
					power-source = <IO_STANDARD_LVCMOS18>;
					bias-disable;
				};

				mux-mdio {
					function = "mdio3";
					groups = "mdio3_0_grp";
				};

				mux {
					function = "ethernet3";
					groups = "ethernet3_0_grp";
				};
			};

			pinctrl_usb0_default: usb0-default {
				conf {
					groups = "usb0_0_grp";
					slew-rate = <SLEW_RATE_SLOW>;
					power-source = <IO_STANDARD_LVCMOS18>;
				};

				conf-rx {
					pins = "MIO52", "MIO53", "MIO55";
					bias-high-impedance;
				};

				conf-tx {
					pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
					"MIO60", "MIO61", "MIO62", "MIO63";
					bias-disable;
				};

				mux {
					groups = "usb0_0_grp";
					function = "usb0";
				};
			};

			pinctrl_sdhci1_default: sdhci1-default {
				conf {
					groups = "sdio1_0_grp";
					slew-rate = <SLEW_RATE_SLOW>;
					power-source = <IO_STANDARD_LVCMOS18>;
					bias-disable;
				};

				conf-cd {
					groups = "sdio1_cd_0_grp";
					bias-high-impedance;
					bias-pull-up;
					slew-rate = <SLEW_RATE_SLOW>;
					power-source = <IO_STANDARD_LVCMOS18>;
				};

				mux-cd {
					groups = "sdio1_cd_0_grp";
					function = "sdio1_cd";
				};

				mux {
					groups = "sdio1_0_grp";
					function = "sdio1";
				};
			};
		};
	};
	fragment15 {
		target = <&uart1>;
		__overlay__ {
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1_default>;
		};
	};
};