arch/arm/dts/stm32mp131.dtsi - filogic/uboot - Gitiles

 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
 /*
  * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
  */
 #include <dt-bindings/interrupt-controller/arm-gic.h>

 / {
 	#address-cells = <1>;
 	#size-cells = <1>;

 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

 		cpu0: cpu@0 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <0>;
 		};
 	};

 	arm-pmu {
 		compatible = "arm,cortex-a7-pmu";
 		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-affinity = <&cpu0>;
 		interrupt-parent = <&intc>;
 	};

 	scmi_sram: sram@2ffff000 {
 		compatible = "mmio-sram";
 		reg = <0x2ffff000 0x1000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0 0x2ffff000 0x1000>;

 		scmi_shm: scmi_shm@0 {
 			compatible = "arm,scmi-shmem";
 			reg = <0 0x80>;
 		};
 	};

 	firmware {
 		optee: optee {
 			method = "smc";
 			compatible = "linaro,optee-tz";
 		};

 		scmi: scmi {
 			compatible = "linaro,scmi-optee";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			linaro,optee-channel-id = <0>;
 			shmem = <&scmi_shm>;

 			scmi_clk: protocol@14 {
 				reg = <0x14>;
 				#clock-cells = <1>;
 			};

 			scmi_reset: protocol@16 {
 				reg = <0x16>;
 				#reset-cells = <1>;
 			};
 		};
 	};

 	clocks {
 		clk_axi: clk-axi {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <266500000>;
 		};

 		clk_hse: clk-hse {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <24000000>;
 		};

 		clk_hsi: clk-hsi {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <64000000>;
 		};

 		clk_lsi: clk-lsi {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <32000>;
 		};

 		clk_pclk3: clk-pclk3 {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <104438965>;
 		};

 		clk_pclk4: clk-pclk4 {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <133250000>;
 		};

 		clk_pll4_p: clk-pll4_p {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <50000000>;
 		};

 		clk_pll4_r: clk-pll4_r {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <99000000>;
 		};
 	};

 	intc: interrupt-controller@a0021000 {
 		compatible = "arm,cortex-a7-gic";
 		#interrupt-cells = <3>;
 		interrupt-controller;
 		reg = <0xa0021000 0x1000>,
 		      <0xa0022000 0x2000>;
 	};

 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
 	};

 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
 		interrupt-parent = <&intc>;
 		always-on;
 	};

 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		interrupt-parent = <&intc>;
 		ranges;

 		uart4: serial@40010000 {
 			compatible = "st,stm32h7-uart";
 			reg = <0x40010000 0x400>;
 			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk_hsi>;
 			status = "disabled";
 		};

 		dma1: dma-controller@48000000 {
 			compatible = "st,stm32-dma";
 			reg = <0x48000000 0x400>;
 			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk_pclk4>;
 			#dma-cells = <4>;
 			st,mem2mem;
 			dma-requests = <8>;
 		};

 		dma2: dma-controller@48001000 {
 			compatible = "st,stm32-dma";
 			reg = <0x48001000 0x400>;
 			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk_pclk4>;
 			#dma-cells = <4>;
 			st,mem2mem;
 			dma-requests = <8>;
 		};

 		dmamux1: dma-router@48002000 {
 			compatible = "st,stm32h7-dmamux";
 			reg = <0x48002000 0x40>;
 			clocks = <&clk_pclk4>;
 			#dma-cells = <3>;
 			dma-masters = <&dma1 &dma2>;
 			dma-requests = <128>;
 			dma-channels = <16>;
 		};

 		exti: interrupt-controller@5000d000 {
 			compatible = "st,stm32mp13-exti", "syscon";
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			reg = <0x5000d000 0x400>;
 		};

 		syscfg: syscon@50020000 {
 			compatible = "st,stm32mp157-syscfg", "syscon";
 			reg = <0x50020000 0x400>;
 			clocks = <&clk_pclk3>;
 		};

 		mdma: dma-controller@58000000 {
 			compatible = "st,stm32h7-mdma";
 			reg = <0x58000000 0x1000>;
 			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk_pclk4>;
 			#dma-cells = <5>;
 			dma-channels = <32>;
 			dma-requests = <48>;
 		};

 		sdmmc1: mmc@58005000 {
 			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
 			arm,primecell-periphid = <0x20253180>;
 			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
 			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "cmd_irq";
 			clocks = <&clk_pll4_p>;
 			clock-names = "apb_pclk";
 			cap-sd-highspeed;
 			cap-mmc-highspeed;
 			max-frequency = <130000000>;
 			status = "disabled";
 		};

 		sdmmc2: mmc@58007000 {
 			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
 			arm,primecell-periphid = <0x20253180>;
 			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "cmd_irq";
 			clocks = <&clk_pll4_p>;
 			clock-names = "apb_pclk";
 			cap-sd-highspeed;
 			cap-mmc-highspeed;
 			max-frequency = <130000000>;
 			status = "disabled";
 		};

 		iwdg2: watchdog@5a002000 {
 			compatible = "st,stm32mp1-iwdg";
 			reg = <0x5a002000 0x400>;
 			clocks = <&clk_pclk4>, <&clk_lsi>;
 			clock-names = "pclk", "lsi";
 			status = "disabled";
 		};

 		bsec: efuse@5c005000 {
 			compatible = "st,stm32mp13-bsec";
 			reg = <0x5c005000 0x400>;
 			#address-cells = <1>;
 			#size-cells = <1>;

 			part_number_otp: part_number_otp@4 {
 				reg = <0x4 0x2>;
 			};
 			ts_cal1: calib@5c {
 				reg = <0x5c 0x2>;
 			};
 			ts_cal2: calib@5e {
 				reg = <0x5e 0x2>;
 			};
 		};

 		/*
 		 * Break node order to solve dependency probe issue between
 		 * pinctrl and exti.
 		 */
 		pinctrl: pin-controller@50002000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "st,stm32mp135-pinctrl";
 			ranges = <0 0x50002000 0x8400>;
 			pins-are-numbered;

 			gpioa: gpio@50002000 {
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				reg = <0x0 0x400>;
 				clocks = <&clk_pclk4>;
 				st,bank-name = "GPIOA";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 0 16>;
 			};

 			gpiob: gpio@50003000 {
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				reg = <0x1000 0x400>;
 				clocks = <&clk_pclk4>;
 				st,bank-name = "GPIOB";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 16 16>;
 			};

 			gpioc: gpio@50004000 {
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				reg = <0x2000 0x400>;
 				clocks = <&clk_pclk4>;
 				st,bank-name = "GPIOC";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 32 16>;
 			};

 			gpiod: gpio@50005000 {
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				reg = <0x3000 0x400>;
 				clocks = <&clk_pclk4>;
 				st,bank-name = "GPIOD";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 48 16>;
 			};

 			gpioe: gpio@50006000 {
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				reg = <0x4000 0x400>;
 				clocks = <&clk_pclk4>;
 				st,bank-name = "GPIOE";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 64 16>;
 			};

 			gpiof: gpio@50007000 {
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				reg = <0x5000 0x400>;
 				clocks = <&clk_pclk4>;
 				st,bank-name = "GPIOF";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 80 16>;
 			};

 			gpiog: gpio@50008000 {
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				reg = <0x6000 0x400>;
 				clocks = <&clk_pclk4>;
 				st,bank-name = "GPIOG";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 96 16>;
 			};

 			gpioh: gpio@50009000 {
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				reg = <0x7000 0x400>;
 				clocks = <&clk_pclk4>;
 				st,bank-name = "GPIOH";
 				ngpios = <15>;
 				gpio-ranges = <&pinctrl 0 112 15>;
 			};

 			gpioi: gpio@5000a000 {
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				reg = <0x8000 0x400>;
 				clocks = <&clk_pclk4>;
 				st,bank-name = "GPIOI";
 				ngpios = <8>;
 				gpio-ranges = <&pinctrl 0 128 8>;
 			};
 		};
 	};
 };
	// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
	/*
	* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
	* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
	*/
	#include <dt-bindings/interrupt-controller/arm-gic.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <0>;
	};
	};

	arm-pmu {
	compatible = "arm,cortex-a7-pmu";
	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>;
	interrupt-parent = <&intc>;
	};

	scmi_sram: sram@2ffff000 {
	compatible = "mmio-sram";
	reg = <0x2ffff000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x2ffff000 0x1000>;

	scmi_shm: scmi_shm@0 {
	compatible = "arm,scmi-shmem";
	reg = <0 0x80>;
	};
	};

	firmware {
	optee: optee {
	method = "smc";
	compatible = "linaro,optee-tz";
	};

	scmi: scmi {
	compatible = "linaro,scmi-optee";
	#address-cells = <1>;
	#size-cells = <0>;
	linaro,optee-channel-id = <0>;
	shmem = <&scmi_shm>;

	scmi_clk: protocol@14 {
	reg = <0x14>;
	#clock-cells = <1>;
	};

	scmi_reset: protocol@16 {
	reg = <0x16>;
	#reset-cells = <1>;
	};
	};
	};

	clocks {
	clk_axi: clk-axi {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <266500000>;
	};

	clk_hse: clk-hse {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	};

	clk_hsi: clk-hsi {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <64000000>;
	};

	clk_lsi: clk-lsi {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <32000>;
	};

	clk_pclk3: clk-pclk3 {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <104438965>;
	};

	clk_pclk4: clk-pclk4 {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <133250000>;
	};

	clk_pll4_p: clk-pll4_p {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <50000000>;
	};

	clk_pll4_r: clk-pll4_r {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <99000000>;
	};
	};

	intc: interrupt-controller@a0021000 {
	compatible = "arm,cortex-a7-gic";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0xa0021000 0x1000>,
	<0xa0022000 0x2000>;
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>;
	interrupt-parent = <&intc>;
	always-on;
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&intc>;
	ranges;

	uart4: serial@40010000 {
	compatible = "st,stm32h7-uart";
	reg = <0x40010000 0x400>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk_hsi>;
	status = "disabled";
	};

	dma1: dma-controller@48000000 {
	compatible = "st,stm32-dma";
	reg = <0x48000000 0x400>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk_pclk4>;
	#dma-cells = <4>;
	st,mem2mem;
	dma-requests = <8>;
	};

	dma2: dma-controller@48001000 {
	compatible = "st,stm32-dma";
	reg = <0x48001000 0x400>;
	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk_pclk4>;
	#dma-cells = <4>;
	st,mem2mem;
	dma-requests = <8>;
	};

	dmamux1: dma-router@48002000 {
	compatible = "st,stm32h7-dmamux";
	reg = <0x48002000 0x40>;
	clocks = <&clk_pclk4>;
	#dma-cells = <3>;
	dma-masters = <&dma1 &dma2>;
	dma-requests = <128>;
	dma-channels = <16>;
	};

	exti: interrupt-controller@5000d000 {
	compatible = "st,stm32mp13-exti", "syscon";
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x5000d000 0x400>;
	};

	syscfg: syscon@50020000 {
	compatible = "st,stm32mp157-syscfg", "syscon";
	reg = <0x50020000 0x400>;
	clocks = <&clk_pclk3>;
	};

	mdma: dma-controller@58000000 {
	compatible = "st,stm32h7-mdma";
	reg = <0x58000000 0x1000>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk_pclk4>;
	#dma-cells = <5>;
	dma-channels = <32>;
	dma-requests = <48>;
	};

	sdmmc1: mmc@58005000 {
	compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
	arm,primecell-periphid = <0x20253180>;
	reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&clk_pll4_p>;
	clock-names = "apb_pclk";
	cap-sd-highspeed;
	cap-mmc-highspeed;
	max-frequency = <130000000>;
	status = "disabled";
	};

	sdmmc2: mmc@58007000 {
	compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
	arm,primecell-periphid = <0x20253180>;
	reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "cmd_irq";
	clocks = <&clk_pll4_p>;
	clock-names = "apb_pclk";
	cap-sd-highspeed;
	cap-mmc-highspeed;
	max-frequency = <130000000>;
	status = "disabled";
	};

	iwdg2: watchdog@5a002000 {
	compatible = "st,stm32mp1-iwdg";
	reg = <0x5a002000 0x400>;
	clocks = <&clk_pclk4>, <&clk_lsi>;
	clock-names = "pclk", "lsi";
	status = "disabled";
	};

	bsec: efuse@5c005000 {
	compatible = "st,stm32mp13-bsec";
	reg = <0x5c005000 0x400>;
	#address-cells = <1>;
	#size-cells = <1>;

	part_number_otp: part_number_otp@4 {
	reg = <0x4 0x2>;
	};
	ts_cal1: calib@5c {
	reg = <0x5c 0x2>;
	};
	ts_cal2: calib@5e {
	reg = <0x5e 0x2>;
	};
	};

	/*
	* Break node order to solve dependency probe issue between
	* pinctrl and exti.
	*/
	pinctrl: pin-controller@50002000 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "st,stm32mp135-pinctrl";
	ranges = <0 0x50002000 0x8400>;
	pins-are-numbered;

	gpioa: gpio@50002000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x0 0x400>;
	clocks = <&clk_pclk4>;
	st,bank-name = "GPIOA";
	ngpios = <16>;
	gpio-ranges = <&pinctrl 0 0 16>;
	};

	gpiob: gpio@50003000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x1000 0x400>;
	clocks = <&clk_pclk4>;
	st,bank-name = "GPIOB";
	ngpios = <16>;
	gpio-ranges = <&pinctrl 0 16 16>;
	};

	gpioc: gpio@50004000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x2000 0x400>;
	clocks = <&clk_pclk4>;
	st,bank-name = "GPIOC";
	ngpios = <16>;
	gpio-ranges = <&pinctrl 0 32 16>;
	};

	gpiod: gpio@50005000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x3000 0x400>;
	clocks = <&clk_pclk4>;
	st,bank-name = "GPIOD";
	ngpios = <16>;
	gpio-ranges = <&pinctrl 0 48 16>;
	};

	gpioe: gpio@50006000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x4000 0x400>;
	clocks = <&clk_pclk4>;
	st,bank-name = "GPIOE";
	ngpios = <16>;
	gpio-ranges = <&pinctrl 0 64 16>;
	};

	gpiof: gpio@50007000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x5000 0x400>;
	clocks = <&clk_pclk4>;
	st,bank-name = "GPIOF";
	ngpios = <16>;
	gpio-ranges = <&pinctrl 0 80 16>;
	};

	gpiog: gpio@50008000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x6000 0x400>;
	clocks = <&clk_pclk4>;
	st,bank-name = "GPIOG";
	ngpios = <16>;
	gpio-ranges = <&pinctrl 0 96 16>;
	};

	gpioh: gpio@50009000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x7000 0x400>;
	clocks = <&clk_pclk4>;
	st,bank-name = "GPIOH";
	ngpios = <15>;
	gpio-ranges = <&pinctrl 0 112 15>;
	};

	gpioi: gpio@5000a000 {
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x8000 0x400>;
	clocks = <&clk_pclk4>;
	st,bank-name = "GPIOI";
	ngpios = <8>;
	gpio-ranges = <&pinctrl 0 128 8>;
	};
	};
	};
	};