board: Add support for Sielaff i.MX6 Solo board
The Sielaff i.MX6 Solo board is a control and HMI board for vending
machines. Add support for this board.
The devicetree files are taken from pending changes in the Linux
kernel that are available from linux-next and will likely be
part of Linux v6.9.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
diff --git a/board/sielaff/imx6dl-sielaff/Kconfig b/board/sielaff/imx6dl-sielaff/Kconfig
new file mode 100644
index 0000000..1b74a7d
--- /dev/null
+++ b/board/sielaff/imx6dl-sielaff/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX6S_SIELAFF
+
+config SYS_BOARD
+ string
+ default "imx6dl-sielaff"
+
+config SYS_VENDOR
+ string
+ default "sielaff"
+
+config SYS_CONFIG_NAME
+ string
+ default "imx6dl-sielaff"
+
+endif
diff --git a/board/sielaff/imx6dl-sielaff/MAINTAINERS b/board/sielaff/imx6dl-sielaff/MAINTAINERS
new file mode 100644
index 0000000..c0d3a09
--- /dev/null
+++ b/board/sielaff/imx6dl-sielaff/MAINTAINERS
@@ -0,0 +1,9 @@
+Sielaff i.MX6 Solo Board
+M: Frieder Schrempf <frieder.schrempf@kontron.de>
+S: Maintained
+F: arch/arm/dts/imx6dl-sielaff*
+F: board/sielaff/imx6dl-sielaff/
+F: configs/imx6dl_sielaff_defconfig
+F: doc/board/sielaff/imx6dl-sielaff.rst
+F: include/configs/imx6dl-sielaff.h
+F: include/configs/kontron-sl-mx6ul.h
diff --git a/board/sielaff/imx6dl-sielaff/Makefile b/board/sielaff/imx6dl-sielaff/Makefile
new file mode 100644
index 0000000..65cecfe
--- /dev/null
+++ b/board/sielaff/imx6dl-sielaff/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2022 Kontron Electronics GmbH
+
+ifdef CONFIG_SPL_BUILD
+obj-y := spl.o
+else
+obj-y := imx6dl-sielaff.o
+endif
diff --git a/board/sielaff/imx6dl-sielaff/imx6dl-sielaff.c b/board/sielaff/imx6dl-sielaff/imx6dl-sielaff.c
new file mode 100644
index 0000000..4da084ed
--- /dev/null
+++ b/board/sielaff/imx6dl-sielaff/imx6dl-sielaff.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+
+#include <compiler.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/io.h>
+#include <init.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const iomux_v3_cfg_t nfc_pads[] = {
+ MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* config gpmi nand iomux */
+ imx_iomux_v3_setup_multiple_pads(nfc_pads,
+ ARRAY_SIZE(nfc_pads));
+
+ /* gate ENFC_CLK_ROOT clock first,before clk source switch */
+ clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+ /* config gpmi and bch clock to 100 MHz */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+ /* enable ENFC_CLK_ROOT clock */
+ setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+ /* enable gpmi and bch clock gating */
+ setbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+
+int board_init(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ u32 reg;
+
+ setup_gpmi_nand();
+
+ /* Enable SPI2 clock */
+ enable_spi_clk(true, 1);
+
+ /*
+ * Configure clock output for USB hub
+ * 1. Disabling CLK01 and CLK02
+ */
+ clrbits_le32(&mxc_ccm->ccosr, MXC_CCM_CCOSR_CKOL_EN);
+ clrbits_le32(&mxc_ccm->ccosr, MXC_CCM_CCOSR_CKO2_EN_OFFSET);
+
+ /*
+ * 2. Setting ccm timer - osc_clk (24 MHz) divide by 2 -> 12 Mhz
+ * CLK02_DIV: 001b CLK02_SEL: 01110b -> 0010 1110b -> 0x2e
+ */
+ reg = readl(&mxc_ccm->ccosr);
+ reg &= ~MXC_CCM_CCOSR_CKO2_SEL_MASK;
+ reg &= ~MXC_CCM_CCOSR_CKO2_DIV_MASK;
+ reg |= (0x2e << MXC_CCM_CCOSR_CKO2_SEL_OFFSET);
+ writel(reg, &mxc_ccm->ccosr);
+
+ /* 3. Enabling CLK02 on output CCM_CLK01 */
+ setbits_le32(&mxc_ccm->ccosr, MXC_CCM_CCOSR_CLK_OUT_SEL);
+ setbits_le32(&mxc_ccm->ccosr, MXC_CCM_CCOSR_CKO2_EN_OFFSET);
+
+ return 0;
+}
diff --git a/board/sielaff/imx6dl-sielaff/imx6dl-sielaff.env b/board/sielaff/imx6dl-sielaff/imx6dl-sielaff.env
new file mode 100644
index 0000000..9aafa3c
--- /dev/null
+++ b/board/sielaff/imx6dl-sielaff/imx6dl-sielaff.env
@@ -0,0 +1,114 @@
+blkloadfdt=fatload ${device} ${devnum}:${partnum} ${fdt_addr} ${load_fdt_file}
+blkloadimage=fatload ${device} ${devnum}:${partnum} ${loadaddr} ${load_image}
+boot_devices=usb mmc ubi
+bootargs_base=vt.global_cursor_default=0 consoleblank=0 cma=200M fbcon=rotate:1
+bootdelay=3
+bootdir=
+console=ttymxc1,115200
+ethact=FEC0
+fdt_addr=0x18000000
+fdt_file_legacy=imx6dl_sielaff.dtb
+fdt_file=imx6dl-sielaff.dtb
+fdt_high=0xffffffff
+image_legacy=zImage
+image=fitImage
+initrd_high=0xffffffff
+ip_dyn=no
+loadaddr=0x12000000
+mmcargs=setenv bootargs ${bootargs_base} console=${console} root=${mmcroot}
+mmcroot=/dev/mmcblk2p2 rootwait rw
+ramdisk_addr=0x18C00000
+script=boot.scr
+touch_rst_gpio=2
+touch_irq_gpio=146
+ubiargs=setenv bootargs ${bootargs_base} console=${console} rootfstype=ubifs ubi.mtd=0 root=ubi0_0 rw
+ubiloadfdt=ubifsload ${fdt_addr} /boot/${load_fdt_file}
+ubiloadimage=ubifsload ${loadaddr} /boot/${load_image}
+usb_pgood_delay=2000
+usbargs=setenv bootargs ${bootargs_base} console=${console} root=${usbroot}
+usbroot=/dev/sda2 rootwait rw
+
+bootcmd=
+ for b in ${boot_devices}; do
+ if test ${b} = mmc; then
+ run mmcboot;
+ fi;
+ if test ${b} = net; then
+ run netboot;
+ fi;
+ if test ${b} = ubi; then
+ run ubiboot;
+ fi;
+ if test ${b} = usb; then
+ run usbboot;
+ fi;
+ done;
+
+boot=
+ load_image=${image};
+ run loadimagecmd;
+ if test $? = 0; then
+ imxtract ${loadaddr} fdt-${fdt_file} ${fdt_addr};
+ run detect_touch;
+ bootm ${loadaddr} - ${fdt_addr};
+ else
+ load_image=${image_legacy};
+ load_fdt_file=${fdt_file_legacy};
+ run loadimagecmd;
+ run loadfdtcmd;
+ if test $? = 0; then
+ run detect_touch;
+ bootz ${loadaddr} - ${fdt_addr};
+ fi;
+ fi;
+
+detect_touch=
+ gpio clear ${touch_irq_gpio};
+ gpio clear ${touch_rst_gpio};
+ sleep 0.02;
+ gpio set ${touch_rst_gpio};
+ sleep 0.1;
+ gpio input ${touch_irq_gpio};
+ i2c dev 2;
+ fdt addr ${fdt_addr};
+ if i2c probe 0x55; then
+ echo 'Detected Sitronix Touch';
+ fdt set /soc/bus@2100000/i2c@21a8000/touchscreen@55 status okay;
+ else
+ if i2c probe 0x5d; then
+ echo 'Detected Goodix Touch';
+ fdt set /soc/bus@2100000/i2c@21a8000/touchscreen@5d status okay;
+ fi;
+ fi;
+ gpio clear ${touch_rst_gpio};
+
+mmcboot=
+ echo Booting from MMC ...;
+ run mmcargs;
+ device=mmc;
+ devnum=2;
+ partnum=1;
+ setenv loadimagecmd ${blkloadimage};
+ setenv loadfdtcmd ${blkloadfdt};
+ run boot;
+
+ubiboot=
+ echo Booting from NAND (UBI);
+ run ubiargs;
+ ubi part rootfs;
+ ubifsmount ubi0;
+ setenv loadimagecmd ${ubiloadimage};
+ setenv loadfdtcmd ${ubiloadfdt};
+ load_image=${image};
+ run boot;
+
+usbboot=
+ echo Booting from USB Storage ...;
+ run usbargs;
+ usb start;
+ device=usb;
+ devnum=0;
+ partnum=1;
+ setenv loadimagecmd ${blkloadimage};
+ setenv loadfdtcmd ${blkloadfdt};
+ run boot;
diff --git a/board/sielaff/imx6dl-sielaff/spl.c b/board/sielaff/imx6dl-sielaff/spl.c
new file mode 100644
index 0000000..64a84fd
--- /dev/null
+++ b/board/sielaff/imx6dl-sielaff/spl.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/sections.h>
+#include <init.h>
+#include <spl.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define GPIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static const iomux_v3_cfg_t ecspi2_pads[] = {
+ MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static const iomux_v3_cfg_t uart2_pads[] = {
+ MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static const iomux_v3_cfg_t usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* CD */
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 4)
+#define SPI2_CS_GPIO IMX_GPIO_NR(5, 29)
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC3_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ */
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
+ ARRAY_SIZE(usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers \
+ (%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static int mx6ssielaff_dcd_table[] = {
+ 0x020e0774, 0x000C0000,
+ 0x020e0754, 0x00000000,
+ 0x020e04ac, 0x00000030,
+ 0x020e04b0, 0x00000030,
+ 0x020e0464, 0x00000030,
+ 0x020e0490, 0x00000030,
+ 0x020e074c, 0x00000030,
+ 0x020e0494, 0x00000030,
+ 0x020e04a0, 0x00000000,
+ 0x020e04b4, 0x00000030,
+ 0x020e04b8, 0x00000030,
+ 0x020e076c, 0x00000030,
+ 0x020e0750, 0x00020000,
+ 0x020e04bc, 0x00000030,
+ 0x020e04c0, 0x00000030,
+ 0x020e04c4, 0x00000030,
+ 0x020e04c8, 0x00000030,
+ 0x020e0760, 0x00020000,
+ 0x020e0764, 0x00000030,
+ 0x020e0770, 0x00000030,
+ 0x020e0778, 0x00000030,
+ 0x020e077c, 0x00000030,
+ 0x020e0470, 0x00000030,
+ 0x020e0474, 0x00000030,
+ 0x020e0478, 0x00000030,
+ 0x020e047c, 0x00000030,
+ 0x021b001c, 0x00008000,
+ 0x021b0800, 0xA1390003,
+ 0x021b080c, 0x00350035,
+ 0x021b0810, 0x002A0032,
+ 0x021b083c, 0x02340234,
+ 0x021b0840, 0x02200220,
+ 0x021b0848, 0x4650504E,
+ 0x021b0850, 0x3A342E34,
+ 0x021b081c, 0x33333333,
+ 0x021b0820, 0x33333333,
+ 0x021b0824, 0x33333333,
+ 0x021b0828, 0x33333333,
+ 0x021b08b8, 0x00000800,
+ 0x021b0004, 0x0002002D,
+ 0x021b0008, 0x00333040,
+ 0x021b000c, 0x676B52F3,
+ 0x021b0010, 0xB66D8B63,
+ 0x021b0014, 0x01FF00DB,
+ 0x021b0018, 0x00011740,
+ 0x021b001c, 0x00008000,
+ 0x021b002c, 0x000026D2,
+ 0x021b0030, 0x006B1023,
+ 0x021b0040, 0x00000027,
+ 0x021b0000, 0x84190000,
+ 0x021b001c, 0x02008032,
+ 0x021b001c, 0x00008033,
+ 0x021b001c, 0x00048031,
+ 0x021b001c, 0x15208030,
+ 0x021b001c, 0x04008040,
+ 0x021b0020, 0x00007800,
+ 0x021b0818, 0x00022227,
+ 0x021b0004, 0x0002556D,
+ 0x021b0404, 0x00011006,
+ 0x021b001c, 0x00000000,
+ 0x020c4068, 0x00C03F3F,
+ 0x020c406c, 0x0030FC03,
+ 0x020c4070, 0x0FFFC000,
+ 0x020c4074, 0x3FF00000,
+ 0x020c4078, 0xFFFFF300,
+ 0x020c407c, 0x0F0000C3,
+ 0x020c4080, 0x000003FF,
+ 0x020e0010, 0xF00000CF,
+ 0x020e0018, 0x007F007F,
+ 0x020e001c, 0x007F007F,
+};
+
+static void ddr_init(int *table, int size)
+{
+ int i;
+
+ for (i = 0; i < size / 2 ; i++)
+ writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+ ddr_init(mx6ssielaff_dcd_table, ARRAY_SIZE(mx6ssielaff_dcd_table));
+}
+
+int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
+{
+ return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
+ ? SPI2_CS_GPIO : -1;
+}
+
+static void setup_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
+ gpio_request(SPI2_CS_GPIO, "spi2_cs0");
+ gpio_direction_output(SPI2_CS_GPIO, 1);
+ enable_spi_clk(true, 1);
+}
+
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+ gpr_init();
+
+ /* IOMUX UART */
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* SPI */
+ setup_spi();
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ u32 bootdev = spl_boot_device();
+
+ /*
+ * The default boot fuse settings use the SD card (MMC1) as primary
+ * boot device, but allow SPI NOR as a fallback boot device.
+ * We can't detect the fallback case and spl_boot_device() will return
+ * BOOT_DEVICE_MMC1 despite the actual boot device being SPI NOR.
+ * Therefore we try to load U-Boot proper vom SPI NOR after loading
+ * from MMC has failed.
+ */
+ spl_boot_list[0] = bootdev;
+
+ switch (bootdev) {
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+ spl_boot_list[1] = BOOT_DEVICE_SPI;
+ break;
+ }
+}