commit 94e3f0f8d053e69b2da998cb6321d41ce24c7d58
author TsiChung Liew <Tsi-Chung.Liew@freescale.com> Wed Jun 18 19:27:23 2008 -0500
committer John Rigby <jrigby@freescale.com> Fri Jul 11 10:45:58 2008 -0600
tree 689796916df50e0c293e3414c701164fce074d28
parent 7d12938a30292162a1ef53a3aa17624750728dce

ColdFire: Fix power up issue for MCF5235

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>

board/freescale/m5235evb/m5235evb.c

diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
index c2c8fe8..bd8a4e5 100644
--- a/board/freescale/m5235evb/m5235evb.c
+++ b/board/freescale/m5235evb/m5235evb.c
@@ -75,9 +75,11 @@
 		sdram->dacr0 =
 		    SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
 		    SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
+		asm("nop");
 
 		/* Initialize DMR0 */
 		sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
+		asm("nop");
 
 		/* Set IP (bit 3) in DACR */
 		sdram->dacr0 |= SDRAMC_DARCn_IP;
@@ -100,6 +102,7 @@
 
 		/* Finish the configuration by issuing the MRS. */
 		sdram->dacr0 |= SDRAMC_DARCn_IMRS;
+		asm("nop");
 
 		/* Write to the SDRAM Mode Register */
 		*(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696;