commit 94bc0ddab4792ec7e7942e513cf60a41afeb4270
author Fabio Estevam <fabio.estevam@freescale.com> Fri May 03 04:37:13 2013 +0000
committer Stefano Babic <sbabic@denx.de> Sun May 05 17:08:47 2013 +0200
tree 2b8fff77b97276c5b93d580d8eae738e3683b75f
parent 1bd7205c2fcd622f7b928aa6a9ff709296047a11

mxs: spl_mem_init: Change EMI port priority

FSL bootlets code set the PORT_PRIORITY_ORDER field of register HW_EMI_CTRL
as 0x2, which means:

PORT0231 = 0x02 Priority Order: AXI0, AHB2, AHB3, AHB1

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index 5eacd36..41fb803 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -287,7 +287,7 @@
 	early_delay(20000);
 
 	/* Adjust EMI port priority. */
-	clrsetbits_le32(0x80020000, 0x1f << 16, 0x8);
+	clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
 	early_delay(20000);
 
 	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);