rockchip: spl: Support full-speed CPU in SPL
Add a feature which speeds up the CPU to full speed in SPL to minimise
boot time. This is only supported for certain boards (at present only
jerry).
Signed-off-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index a9ea268..d66b26f 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -74,4 +74,9 @@
*/
int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp);
+struct rk3288_cru;
+struct rk3288_grf;
+
+void rkclk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
+
#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index b0dea70..d2690c7 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -109,6 +109,18 @@
SPI0_DIV_MASK = 0x7f,
};
+/* CRU_CLKSEL37_CON */
+enum {
+ PCLK_CORE_DBG_DIV_SHIFT = 9,
+ PCLK_CORE_DBG_DIV_MASK = 0x1f,
+
+ ATCLK_CORE_DIV_CON_SHIFT = 4,
+ ATCLK_CORE_DIV_CON_MASK = 0x1f,
+
+ CLK_L2RAM_DIV_SHIFT = 0,
+ CLK_L2RAM_DIV_MASK = 7,
+};
+
/* CRU_CLKSEL39_CON */
enum {
ACLK_HEVC_PLL_SHIFT = 0xe,