arm: rmobile: Add support Renesas SH73A0
Renesas SH73A0 is CPU with Cortex-A9.
This supports the basic register definition and GPIO.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile
index e7eb90f..77eca4b 100644
--- a/arch/arm/cpu/armv7/rmobile/Makefile
+++ b/arch/arm/cpu/armv7/rmobile/Makefile
@@ -25,11 +25,17 @@
LIB = $(obj)lib$(SOC).o
-COBJS += cpu_info.o
-COBJS += timer.o
+SOBJS = lowlevel_init.o
+COBJS-y += cpu_info.o
+COBJS-y += timer.o
+
+COBJS-$(CONFIG_DISPLAY_BOARDINFO) += board.o
+COBJS-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
-SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y))
+COBJS := $(COBJS-y)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(LIB)
diff --git a/arch/arm/cpu/armv7/rmobile/board.c b/arch/arm/cpu/armv7/rmobile/board.c
new file mode 100644
index 0000000..2622590
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/board.c
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+
+int checkboard(void)
+{
+ printf("Board: %s\n", sysinfo.board_string);
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c b/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
new file mode 100644
index 0000000..3086dd8
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+
+u32 rmobile_get_cpu_type(void)
+{
+ u32 id;
+ u32 type;
+ struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+
+ id = readl(hpb->cccr);
+ type = (id >> 8) & 0xFF;
+
+ return type;
+}
+
+u32 get_cpu_rev(void)
+{
+ u32 id;
+ u32 rev;
+ struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+
+ id = readl(hpb->cccr);
+ rev = (id >> 4) & 0xF;
+
+ return rev;
+}
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c
index 789c2c3..2148958 100644
--- a/arch/arm/cpu/armv7/rmobile/cpu_info.c
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info.c
@@ -22,7 +22,6 @@
*/
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/rmobile.h>
#ifdef CONFIG_ARCH_CPU_INIT
int arch_cpu_init(void)
@@ -40,35 +39,32 @@
#endif
#ifdef CONFIG_DISPLAY_CPUINFO
-static u32 get_cpu_type(void)
+static u32 __rmobile_get_cpu_type(void)
{
- u32 id;
- u32 type;
-
- id = readl(CCCR);
- type = (id >> 8) & 0xFF;
-
- return type;
+ return 0x0;
}
+u32 rmobile_get_cpu_type(void)
+ __attribute__((weak, alias("__rmobile_get_cpu_type")));
-static u32 get_cpu_rev(void)
+static u32 __rmobile_get_cpu_rev(void)
{
- u32 id;
- u32 rev;
-
- id = readl(CCCR);
- rev = (id >> 4) & 0xF;
-
- return rev;
+ return 0;
}
+u32 rmobile_get_cpu_rev(void)
+ __attribute__((weak, alias("__rmobile_get_cpu_rev")));
int print_cpuinfo(void)
{
- switch (get_cpu_type()) {
+ switch (rmobile_get_cpu_type()) {
+ case 0x37:
+ printf("CPU: Renesas Electronics SH73A0 rev %d\n",
+ rmobile_get_cpu_rev());
+ break;
default:
- printf("CPU: Renesas Electronics CPU rev %d\n", get_cpu_rev());
+ printf("CPU: Renesas Electronics CPU rev %d\n",
+ get_cpu_rev());
break;
}
return 0;
}
-#endif
+#endif /* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init.S
new file mode 100644
index 0000000..2cd410b
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init.S
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com>
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+ ldr r0, =MERAM_BASE
+ mov r1, #0x0
+ str r1, [r0]
+
+ mrc p15, 0, r0, c0, c0, 5
+ ands r0, r0, #0xF
+ beq lowlevel_init__
+ b wait_interrupt
+
+ .pool
+ .align 4
+
+wait_interrupt:
+ ldr r1, =ICCICR
+ mov r2, #0x0
+ str r2, [r1]
+ mov r2, #0xF0
+ adds r1, r1, #4 /* ICCPMR */
+ str r2, [r1]
+ ldr r1, =ICCICR
+ mov r2, #0x1
+ str r2, [r1]
+
+wait_loop:
+ wfi
+
+ ldr r2, [r1, #0xC]
+ str r2, [r1, #0x10]
+
+ ldr r0, =MERAM_BASE
+ ldr r2, [r0]
+ cmp r2, #0
+ movne pc, r2
+
+ b wait_loop
+
+wait_loop_end:
+ .pool
+ .align 4
+
+lowlevel_init__:
+
+ mov r0, #0x200000
+
+loop0:
+ subs r0, r0, #1
+ bne loop0
+
+ ldr sp, MERAM_STACK
+
+ str ip, [sp] /* stash old link register */
+ mov ip, lr /* save link reg across call */
+ bl s_init
+
+ ldr ip, [sp] /* restore save ip */
+ mov lr, ip /* restore link reg */
+
+ /* back to arch calling code */
+ mov pc, lr
+
+ .pool
+ .align 4
+
+ENDPROC(lowlevel_init)
+ .ltorg
+
+MERAM_STACK:
+ .word LOW_LEVEL_MERAM_STACK
diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/include/asm/arch-rmobile/rmobile.h
index bf5e22a..a3468e9 100644
--- a/arch/arm/include/asm/arch-rmobile/rmobile.h
+++ b/arch/arm/include/asm/arch-rmobile/rmobile.h
@@ -2,7 +2,11 @@
#define __ASM_ARCH_RMOBILE_H
#if defined(CONFIG_RMOBILE)
+#if defined(CONFIG_SH73A0)
+#include <asm/arch/sh73a0.h>
+#else
#error "SOC Name not defined"
+#endif
#endif /* CONFIG_RMOBILE */
#endif /* __ASM_ARCH_RMOBILE_H */
diff --git a/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h b/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h
new file mode 100644
index 0000000..398e2c1
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h
@@ -0,0 +1,553 @@
+#ifndef __ASM_SH73A0_H__
+#define __ASM_SH73A0_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function and MSEL switch
+ * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+ /* Hardware manual Table 25-1 (GPIO) */
+ GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
+ GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
+
+ GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
+ GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
+
+ GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
+ GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
+
+ GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
+ GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
+
+ GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
+ GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
+
+ GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
+ GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
+
+ GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
+ GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
+
+ GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
+ GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
+
+ GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
+ GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
+
+ GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
+ GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
+
+ GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
+ GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
+
+ GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
+ GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118,
+
+ GPIO_PORT128, GPIO_PORT129,
+
+ GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
+ GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
+
+ GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
+ GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
+
+ GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
+ GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
+
+ GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
+
+ GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
+ GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
+
+ GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
+ GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
+
+ GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
+ GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
+
+ GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
+ GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
+
+ GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
+ GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
+
+ GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
+ GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
+
+ GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
+ GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
+
+ GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
+ GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
+
+ GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274,
+ GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279,
+
+ GPIO_PORT280, GPIO_PORT281, GPIO_PORT282,
+
+ GPIO_PORT288, GPIO_PORT289,
+
+ GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294,
+ GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299,
+
+ GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304,
+ GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
+
+ /* Table 25-1 (Function 0-7) */
+ GPIO_FN_VBUS_0,
+ GPIO_FN_GPI0,
+ GPIO_FN_GPI1,
+ GPIO_FN_GPI2,
+ GPIO_FN_GPI3,
+ GPIO_FN_GPI4,
+ GPIO_FN_GPI5,
+ GPIO_FN_GPI6,
+ GPIO_FN_GPI7,
+ GPIO_FN_SCIFA7_RXD,
+ GPIO_FN_SCIFA7_CTS_,
+ GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
+ GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
+ GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \
+ GPIO_FN_PORT16_VIO_CKOR,
+ GPIO_FN_SCIFA0_TXD,
+ GPIO_FN_SCIFA7_TXD,
+ GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
+ GPIO_FN_GPO0,
+ GPIO_FN_GPO1,
+ GPIO_FN_GPO2, GPIO_FN_STATUS0,
+ GPIO_FN_GPO3, GPIO_FN_STATUS1,
+ GPIO_FN_GPO4, GPIO_FN_STATUS2,
+ GPIO_FN_VINT,
+ GPIO_FN_TCKON,
+ GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \
+ GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
+ GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \
+ GPIO_FN_PORT28_TPU1TO1,
+ GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
+ GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
+ GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
+ GPIO_FN_SCIFA4_TXD,
+ GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
+ GPIO_FN_SCIFA4_RTS_,
+ GPIO_FN_SCIFA4_CTS_,
+ GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
+ GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
+ GPIO_FN_FSIBOSLD,
+ GPIO_FN_FSIBISLD,
+ GPIO_FN_VACK,
+ GPIO_FN_XTAL1L,
+ GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2,
+ GPIO_FN_SCIFA0_RXD,
+ GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1,
+ GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT,
+ GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR,
+ GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF,
+ GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD,
+ GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \
+ GPIO_FN_FSIAOMC,
+ GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
+
+ GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
+ GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
+ GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
+ GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
+ GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
+ GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
+ GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
+ GPIO_FN_A0, GPIO_FN_BS_,
+ GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2,
+ GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1,
+ GPIO_FN_A14, GPIO_FN_KEYOUT5,
+ GPIO_FN_A15, GPIO_FN_KEYOUT4,
+ GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1,
+ GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
+ GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
+ GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD,
+ GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK,
+ GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
+ GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0,
+ GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1,
+ GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD,
+ GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2,
+ GPIO_FN_A26, GPIO_FN_KEYIN6,
+ GPIO_FN_KEYIN7,
+ GPIO_FN_D0_NAF0,
+ GPIO_FN_D1_NAF1,
+ GPIO_FN_D2_NAF2,
+ GPIO_FN_D3_NAF3,
+ GPIO_FN_D4_NAF4,
+ GPIO_FN_D5_NAF5,
+ GPIO_FN_D6_NAF6,
+ GPIO_FN_D7_NAF7,
+ GPIO_FN_D8_NAF8,
+ GPIO_FN_D9_NAF9,
+ GPIO_FN_D10_NAF10,
+ GPIO_FN_D11_NAF11,
+ GPIO_FN_D12_NAF12,
+ GPIO_FN_D13_NAF13,
+ GPIO_FN_D14_NAF14,
+ GPIO_FN_D15_NAF15,
+ GPIO_FN_CS4_,
+ GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
+ GPIO_FN_CS5B_, GPIO_FN_FCE1_,
+ GPIO_FN_CS6B_, GPIO_FN_DACK0,
+ GPIO_FN_FCE0_, GPIO_FN_CS6A_,
+ GPIO_FN_WAIT_, GPIO_FN_DREQ0,
+ GPIO_FN_RD__FSC,
+ GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
+ GPIO_FN_WE1_,
+ GPIO_FN_FRB,
+ GPIO_FN_CKO,
+ GPIO_FN_NBRSTOUT_,
+ GPIO_FN_NBRST_,
+ GPIO_FN_BBIF2_TXD,
+ GPIO_FN_BBIF2_RXD,
+ GPIO_FN_BBIF2_SYNC,
+ GPIO_FN_BBIF2_SCK,
+ GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2,
+ GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1,
+ GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1,
+ GPIO_FN_SCIFA3_TXD,
+ GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
+ GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
+ GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
+ GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
+ GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \
+ GPIO_FN_PORT115_I2C_SCL3,
+ GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
+ GPIO_FN_PORT116_I2C_SDA3,
+ GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
+ GPIO_FN_HSI_TX_FLAG,
+ GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \
+ GPIO_FN_LCD2D0,
+
+ GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \
+ GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1,
+ GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10,
+ GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \
+ GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11,
+ GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \
+ GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12,
+ GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13,
+ GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14,
+ GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15,
+ GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16,
+ GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17,
+ GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \
+ GPIO_FN_LCD2D6,
+ GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \
+ GPIO_FN_LCD2D7,
+ GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8,
+ GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9,
+ GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \
+ GPIO_FN_LCD2D2,
+ GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \
+ GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3,
+ GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
+ GPIO_FN_LCD2D4,
+ GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
+ GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
+ GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
+ GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
+ GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
+ GPIO_FN_VIO_CKO,
+ GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
+ GPIO_FN_PORT149_KEYOUT9,
+ GPIO_FN_MFG0_IN2,
+ GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
+ GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
+ GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
+ GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
+ GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
+ GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2,
+ GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD,
+ GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
+ GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
+ GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
+ GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
+ GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
+ GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
+ GPIO_FN_TPU3TO0,
+ GPIO_FN_LCDD0,
+ GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
+ GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
+ GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
+ GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
+ GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
+ GPIO_FN_TPU2TO1,
+ GPIO_FN_LCDD6,
+ GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
+ GPIO_FN_LCDD8, GPIO_FN_D16,
+ GPIO_FN_LCDD9, GPIO_FN_D17,
+ GPIO_FN_LCDD10, GPIO_FN_D18,
+ GPIO_FN_LCDD11, GPIO_FN_D19,
+ GPIO_FN_LCDD12, GPIO_FN_D20,
+ GPIO_FN_LCDD13, GPIO_FN_D21,
+ GPIO_FN_LCDD14, GPIO_FN_D22,
+ GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
+ GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
+ GPIO_FN_LCDD17, GPIO_FN_D25,
+ GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
+ GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
+ GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
+ GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
+ GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
+ GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
+ GPIO_FN_LCDDCK, GPIO_FN_LCDWR_,
+ GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \
+ GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
+ GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
+ GPIO_FN_PORT218_VIO_CKOR,
+ GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
+ GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
+ GPIO_FN_LCD2DCK_2,
+ GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
+ GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
+ GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
+ GPIO_FN_PORT221_LCD2HSYN,
+ GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \
+ GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN,
+
+ GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
+ GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2,
+ GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN,
+ GPIO_FN_SCIFA1_RXD,
+ GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1,
+ GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2,
+ GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_,
+ GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2,
+ GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
+ GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
+ GPIO_FN_LCD2D20,
+ GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
+ GPIO_FN_LCD2D21,
+ GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
+ GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
+ GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22,
+ GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23,
+ GPIO_FN_SCIFA6_TXD,
+ GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
+ GPIO_FN_TPU4TO0,
+ GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
+ GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
+ GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \
+ GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD,
+ GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \
+ GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD,
+ GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \
+ GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
+ GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \
+ GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
+ GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \
+ GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \
+ GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK,
+ GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
+ GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC,
+ GPIO_FN_SDHICLK0,
+ GPIO_FN_SDHICD0,
+ GPIO_FN_SDHID0_0,
+ GPIO_FN_SDHID0_1,
+ GPIO_FN_SDHID0_2,
+ GPIO_FN_SDHID0_3,
+ GPIO_FN_SDHICMD0,
+ GPIO_FN_SDHIWP0,
+ GPIO_FN_SDHICLK1,
+ GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2,
+ GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2,
+ GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2,
+ GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2,
+ GPIO_FN_SDHICMD1,
+ GPIO_FN_SDHICLK2,
+ GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4,
+ GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4,
+ GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4,
+ GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4,
+ GPIO_FN_SDHICMD2,
+ GPIO_FN_MMCCLK0,
+ GPIO_FN_MMCD0_0,
+ GPIO_FN_MMCD0_1,
+ GPIO_FN_MMCD0_2,
+ GPIO_FN_MMCD0_3,
+ GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5,
+ GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5,
+ GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5,
+ GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5,
+ GPIO_FN_MMCCMD0,
+ GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT,
+ GPIO_FN_MCP_WAIT__MCP_FRB,
+ GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1,
+ GPIO_FN_MCP_D15_MCP_NAF15,
+ GPIO_FN_MCP_D14_MCP_NAF14,
+ GPIO_FN_MCP_D13_MCP_NAF13,
+ GPIO_FN_MCP_D12_MCP_NAF12,
+ GPIO_FN_MCP_D11_MCP_NAF11,
+ GPIO_FN_MCP_D10_MCP_NAF10,
+ GPIO_FN_MCP_D9_MCP_NAF9,
+ GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1,
+ GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7,
+
+ GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6,
+ GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5,
+ GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4,
+ GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3,
+ GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2,
+ GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1,
+ GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0,
+ GPIO_FN_MCP_NBRSTOUT_,
+ GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE,
+
+ /* MSEL2 special case */
+ GPIO_FN_TSIF2_TS_XX1,
+ GPIO_FN_TSIF2_TS_XX2,
+ GPIO_FN_TSIF2_TS_XX3,
+ GPIO_FN_TSIF2_TS_XX4,
+ GPIO_FN_TSIF2_TS_XX5,
+ GPIO_FN_TSIF1_TS_XX1,
+ GPIO_FN_TSIF1_TS_XX2,
+ GPIO_FN_TSIF1_TS_XX3,
+ GPIO_FN_TSIF1_TS_XX4,
+ GPIO_FN_TSIF1_TS_XX5,
+ GPIO_FN_TSIF0_TS_XX1,
+ GPIO_FN_TSIF0_TS_XX2,
+ GPIO_FN_TSIF0_TS_XX3,
+ GPIO_FN_TSIF0_TS_XX4,
+ GPIO_FN_TSIF0_TS_XX5,
+ GPIO_FN_MST1_TS_XX1,
+ GPIO_FN_MST1_TS_XX2,
+ GPIO_FN_MST1_TS_XX3,
+ GPIO_FN_MST1_TS_XX4,
+ GPIO_FN_MST1_TS_XX5,
+ GPIO_FN_MST0_TS_XX1,
+ GPIO_FN_MST0_TS_XX2,
+ GPIO_FN_MST0_TS_XX3,
+ GPIO_FN_MST0_TS_XX4,
+ GPIO_FN_MST0_TS_XX5,
+
+ /* MSEL3 special cases */
+ GPIO_FN_SDHI0_VCCQ_MC0_ON,
+ GPIO_FN_SDHI0_VCCQ_MC0_OFF,
+ GPIO_FN_DEBUG_MON_VIO,
+ GPIO_FN_DEBUG_MON_LCDD,
+ GPIO_FN_LCDC_LCDC0,
+ GPIO_FN_LCDC_LCDC1,
+
+ /* MSEL4 special cases */
+ GPIO_FN_IRQ9_MEM_INT,
+ GPIO_FN_IRQ9_MCP_INT,
+ GPIO_FN_A11,
+ GPIO_FN_KEYOUT8,
+ GPIO_FN_TPU4TO3,
+ GPIO_FN_RESETA_N_PU_ON,
+ GPIO_FN_RESETA_N_PU_OFF,
+ GPIO_FN_EDBGREQ_PD,
+ GPIO_FN_EDBGREQ_PU,
+
+ /* Functions with pull-ups */
+ GPIO_FN_KEYIN0_PU,
+ GPIO_FN_KEYIN1_PU,
+ GPIO_FN_KEYIN2_PU,
+ GPIO_FN_KEYIN3_PU,
+ GPIO_FN_KEYIN4_PU,
+ GPIO_FN_KEYIN5_PU,
+ GPIO_FN_KEYIN6_PU,
+ GPIO_FN_KEYIN7_PU,
+ GPIO_FN_SDHICD0_PU,
+ GPIO_FN_SDHID0_0_PU,
+ GPIO_FN_SDHID0_1_PU,
+ GPIO_FN_SDHID0_2_PU,
+ GPIO_FN_SDHID0_3_PU,
+ GPIO_FN_SDHICMD0_PU,
+ GPIO_FN_SDHIWP0_PU,
+ GPIO_FN_SDHID1_0_PU,
+ GPIO_FN_SDHID1_1_PU,
+ GPIO_FN_SDHID1_2_PU,
+ GPIO_FN_SDHID1_3_PU,
+ GPIO_FN_SDHICMD1_PU,
+ GPIO_FN_SDHID2_0_PU,
+ GPIO_FN_SDHID2_1_PU,
+ GPIO_FN_SDHID2_2_PU,
+ GPIO_FN_SDHID2_3_PU,
+ GPIO_FN_SDHICMD2_PU,
+ GPIO_FN_MMCCMD0_PU,
+ GPIO_FN_MMCCMD1_PU,
+ GPIO_FN_MMCD0_0_PU,
+ GPIO_FN_MMCD0_1_PU,
+ GPIO_FN_MMCD0_2_PU,
+ GPIO_FN_MMCD0_3_PU,
+ GPIO_FN_MMCD0_4_PU,
+ GPIO_FN_MMCD0_5_PU,
+ GPIO_FN_MMCD0_6_PU,
+ GPIO_FN_MMCD0_7_PU,
+ GPIO_FN_FSIACK_PU,
+ GPIO_FN_FSIAILR_PU,
+ GPIO_FN_FSIAIBT_PU,
+ GPIO_FN_FSIAISLD_PU,
+
+ /* end of GPIO */
+ GPIO_NR,
+};
+
+/* DMA slave IDs */
+enum {
+ SHDMA_SLAVE_INVALID,
+ SHDMA_SLAVE_SCIF0_TX,
+ SHDMA_SLAVE_SCIF0_RX,
+ SHDMA_SLAVE_SCIF1_TX,
+ SHDMA_SLAVE_SCIF1_RX,
+ SHDMA_SLAVE_SCIF2_TX,
+ SHDMA_SLAVE_SCIF2_RX,
+ SHDMA_SLAVE_SCIF3_TX,
+ SHDMA_SLAVE_SCIF3_RX,
+ SHDMA_SLAVE_SCIF4_TX,
+ SHDMA_SLAVE_SCIF4_RX,
+ SHDMA_SLAVE_SCIF5_TX,
+ SHDMA_SLAVE_SCIF5_RX,
+ SHDMA_SLAVE_SCIF6_TX,
+ SHDMA_SLAVE_SCIF6_RX,
+ SHDMA_SLAVE_SCIF7_TX,
+ SHDMA_SLAVE_SCIF7_RX,
+ SHDMA_SLAVE_SCIF8_TX,
+ SHDMA_SLAVE_SCIF8_RX,
+ SHDMA_SLAVE_SDHI0_TX,
+ SHDMA_SLAVE_SDHI0_RX,
+ SHDMA_SLAVE_SDHI1_TX,
+ SHDMA_SLAVE_SDHI1_RX,
+ SHDMA_SLAVE_SDHI2_TX,
+ SHDMA_SLAVE_SDHI2_RX,
+ SHDMA_SLAVE_MMCIF_TX,
+ SHDMA_SLAVE_MMCIF_RX,
+};
+
+/*
+ * SH73A0 IRQ LOCATION TABLE
+ *
+ * 416 -----------------------------------------
+ * IRQ0-IRQ15
+ * 431 -----------------------------------------
+ * ...
+ * 448 -----------------------------------------
+ * sh73a0-intcs
+ * sh73a0-intca-irq-pins
+ * 680 -----------------------------------------
+ * ...
+ * 700 -----------------------------------------
+ * sh73a0-pint0
+ * 731 -----------------------------------------
+ * 732 -----------------------------------------
+ * sh73a0-pint1
+ * 739 -----------------------------------------
+ * ...
+ * 800 -----------------------------------------
+ * IRQ16-IRQ31
+ * 815 -----------------------------------------
+ * ...
+ * 928 -----------------------------------------
+ * sh73a0-intca-irq-pins
+ * 943 -----------------------------------------
+ */
+
+/* PINT interrupts are located at Linux IRQ 700 and up */
+#define SH73A0_PINT0_IRQ(irq) ((irq) + 700)
+#define SH73A0_PINT1_IRQ(irq) ((irq) + 732)
+
+#endif /* __ASM_SH73A0_H__ */
diff --git a/arch/arm/include/asm/arch-rmobile/sh73a0.h b/arch/arm/include/asm/arch-rmobile/sh73a0.h
new file mode 100644
index 0000000..c33bf21
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/sh73a0.h
@@ -0,0 +1,281 @@
+#ifndef __ASM_ARCH_RMOBILE_SH73A0_H
+#define __ASM_ARCH_RMOBILE_SH73A0_H
+
+/* Global Timer */
+#define GLOBAL_TIMER_BASE_ADDR (0xF0000200)
+#define MERAM_BASE (0xE5580000)
+
+/* GIC */
+#define GIC_BASE (0xF0000100)
+#define ICCICR GIC_BASE
+
+/* Secure control register */
+#define LIFEC_SEC_SRC (0xE6110008)
+
+/* RWDT */
+#define RWDT_BASE (0xE6020000)
+
+/* HPB Semaphore Control Registers */
+#define HPB_BASE (0xE6001010)
+
+/* Bus Semaphore Control Registers */
+#define HPBSCR_BASE (0xE6001600)
+
+/* SBSC1 */
+#define SBSC1_BASE (0xFE400000)
+#define SDMRA1A (SBSC1_BASE + 0x100000)
+#define SDMRA2A (SBSC1_BASE + 0x1C0000)
+#define SDMRA3A (SBSC1_BASE + 0x104000)
+
+/* SBSC2 */
+#define SBSC2_BASE (0xFB400000)
+#define SDMRA1B (SBSC2_BASE + 0x100000)
+#define SDMRA2B (SBSC2_BASE + 0x1C0000)
+#define SDMRA3B (SBSC2_BASE + 0x104000)
+
+/* CPG */
+#define CPG_BASE (0xE6150000)
+#define CPG_SRCR_BASE (CPG_BASE + 0x80A0)
+#define WUPCR (CPG_BASE + 0x1010)
+#define SRESCR (CPG_BASE + 0x1018)
+#define PCLKCR (CPG_BASE + 0x1020)
+
+/* BSC */
+#define BSC_BASE (0xFEC10000)
+
+/* SCIF */
+#define SCIF0_BASE (0xE6C40000)
+#define SCIF1_BASE (0xE6C50000)
+#define SCIF2_BASE (0xE6C60000)
+#define SCIF3_BASE (0xE6C70000)
+#define SCIF4_BASE (0xE6C80000)
+#define SCIF5_BASE (0xE6CB0000)
+#define SCIF6_BASE (0xE6CC0000)
+#define SCIF7_BASE (0xE6CD0000)
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct sh73a0_rwdt {
+ u16 rwtcnt0; /* 0x00 */
+ u16 rwtcsra0; /* 0x04 */
+ u16 rwtcsrb0; /* 0x08 */
+};
+
+/* HPB Semaphore Control Registers */
+struct sh73a0_hpb {
+ u32 hpbctrl0;
+ u32 hpbctrl1;
+ u32 hpbctrl2;
+ u32 cccr;
+ u32 dummy0; /* 0x20 */
+ u32 hpbctrl4;
+ u32 hpbctrl5;
+ u32 dummy1; /* 0x2C */
+ u32 hpbctrl6;
+};
+
+/* Bus Semaphore Control Registers */
+struct sh73a0_hpb_bscr {
+ u32 mpsrc; /* 0x00 */
+ u32 mpacctl; /* 0x04 */
+ u32 dummy0[6];
+ u32 smgpiosrc; /* 0x20 */
+ u32 smgpioerr;
+ u32 smgpiotime;
+ u32 smgpiocnt;
+ u32 dummy1[4]; /* 0x30 .. 0x3C */
+ u32 smcmt2src;
+ u32 smcmt2err;
+ u32 smcmt2time;
+ u32 smcmt2cnt;
+ u32 smcpgsrc;
+ u32 smcpgerr;
+ u32 smcpgtime;
+ u32 smcpgcnt;
+ u32 dummy2[4]; /* 0x60 - 0x6C */
+ u32 smsyscsrc;
+ u32 smsyscerr;
+ u32 smsysctime;
+ u32 smsysccnt;
+};
+
+/* SBSC */
+struct sh73a0_sbsc {
+ u32 dummy0[2]; /* 0x00, 0x04 */
+ u32 sdcr0;
+ u32 sdcr1;
+ u32 sdpcr;
+ u32 dummy1; /* 0x14 */
+ u32 sdcr0s;
+ u32 sdcr1s;
+ u32 rtcsr;
+ u32 dummy2; /* 0x24 */
+ u32 rtcor;
+ u32 rtcorh;
+ u32 rtcors;
+ u32 rtcorsh;
+ u32 dummy3[2]; /* 0x38, 0x3C */
+ u32 sdwcrc0;
+ u32 sdwcrc1;
+ u32 sdwcr00;
+ u32 sdwcr01;
+ u32 sdwcr10;
+ u32 sdwcr11;
+ u32 sdpdcr0;
+ u32 dummy4; /* 0x5C */
+ u32 sdwcr2;
+ u32 sdwcrc2;
+ u32 zqccr;
+ u32 dummy5[6]; /* 0x6C .. 0x80 */
+ u32 sdmracr0;
+ u32 dummy6; /* 0x88 */
+ u32 sdmrtmpcr;
+ u32 dummy7; /* 0x90 */
+ u32 sdmrtmpmsk;
+ u32 dummy8; /* 0x98 */
+ u32 sdgencnt;
+ u32 dphycnt0;
+ u32 dphycnt1;
+ u32 dphycnt2;
+ u32 dummy9[2]; /* 0xAC .. 0xB0 */
+ u32 sddrvcr0;
+ u32 dummy10[14]; /* 0xB8 .. 0xEC */
+ u32 dptdivcr0;
+ u32 dptdivcr1;
+ u32 dptdivcr2;
+ u32 dummy11; /* 0xFC */
+ u32 sdptcr0;
+ u32 sdptcr1;
+ u32 sdptcr2;
+ u32 sdptcr3; /* 0x10C */
+ u32 dummy12[145]; /* 0x110 .. 0x350 */
+ u32 dllcnt0; /* 0x354 */
+ u32 sbscmon0;
+};
+
+/* CPG */
+struct sh73a0_sbsc_cpg {
+ u32 frqcra; /* 0x00 */
+ u32 frqcrb;
+ u32 vclkcr1;
+ u32 vclkcr2;
+ u32 zbckcr;
+ u32 flckcr;
+ u32 fsiackcr;
+ u32 vclkcr3;
+ u32 rtstbcr;
+ u32 systbcr;
+ u32 pll1cr;
+ u32 pll2cr;
+ u32 mstpsr0;
+ u32 dummy0; /* 0x34 */
+ u32 mstpsr1;
+ u32 mstpsr5;
+ u32 mstpsr2;
+ u32 dummy1; /* 0x44 */
+ u32 mstpsr3;
+ u32 mstpsr4;
+ u32 dummy2; /* 0x50 */
+ u32 astat;
+ u32 dvfscr0;
+ u32 dvfscr1;
+ u32 dsitckcr;
+ u32 dsi0pckcr;
+ u32 dsi1pckcr;
+ u32 dsi0phycr;
+ u32 dsi1phycr;
+ u32 sd0ckcr;
+ u32 sd1ckcr;
+ u32 sd2ckcr;
+ u32 subckcr;
+ u32 spuackcr;
+ u32 msuckcr;
+ u32 hsickcr;
+ u32 fsibckcr;
+ u32 spuvckcr;
+ u32 mfck1cr;
+ u32 mfck2cr;
+ u32 dummy3[8]; /* 0xA0 .. 0xBC */
+ u32 ckscr;
+ u32 dummy4; /* 0xC4 */
+ u32 pll1stpcr;
+ u32 mpmode;
+ u32 pllecr;
+ u32 dummy5; /* 0xD4 */
+ u32 pll0cr;
+ u32 pll3cr;
+ u32 dummy6; /* 0xE0 */
+ u32 frqcrd;
+ u32 dummyi7; /* 0xE8 */
+ u32 vrefcr;
+ u32 pll0stpcr;
+ u32 dummy8; /* 0xF4 */
+ u32 pll2stpcr;
+ u32 pll3stpcr;
+ u32 dummy9[4]; /* 0x100 .. 0x10c */
+ u32 rmstpcr0;
+ u32 rmstpcr1;
+ u32 rmstpcr2;
+ u32 rmstpcr3;
+ u32 rmstpcr4;
+ u32 rmstpcr5;
+ u32 dummy10[2]; /* 0x128 .. 0x12c */
+ u32 smstpcr0;
+ u32 smstpcr1;
+ u32 smstpcr2;
+ u32 smstpcr3;
+ u32 smstpcr4;
+ u32 smstpcr5;
+ u32 dummy11[10]; /* 0x148 .. 0x16c */
+ u32 dvfscr2;
+ u32 dvfscr3;
+ u32 dvfscr4;
+ u32 dvfscr5; /* 0x17C */
+};
+
+/* CPG SRCR part OK */
+struct sh73a0_sbsc_cpg_srcr {
+ u32 srcr0;
+ u32 dummy0; /* 0xA4 */
+ u32 srcr1;
+ u32 dummy1; /* 0xAC */
+ u32 srcr2;
+ u32 dummy2; /* 0xB4 */
+ u32 srcr3;
+ u32 srcr4;
+ u32 dummy3; /* 0xC0 */
+ u32 srcr5;
+};
+
+/* BSC */
+struct sh73a0_bsc {
+ u32 cmncr;
+ u32 cs0bcr;
+ u32 cs2bcr;
+ u32 dummy0; /* 0x0C */
+ u32 cs4bcr;
+ u32 cs5abcr;
+ u32 cs5bbcr;
+ u32 cs6abcr;
+ u32 cs6bbcr;
+ u32 cs0wcr;
+ u32 cs2wcr;
+ u32 dummy1; /* 0x2C */
+ u32 cs4wcr;
+ u32 cs5awcr;
+ u32 cs5bwcr;
+ u32 cs6awcr;
+ u32 cs6bwcr;
+ u32 rbwtcnt;
+ u32 busycr;
+ u32 dummy2; /* 0x5c */
+ u32 cs7abcr;
+ u32 cs7awcr;
+ u32 dummy3[2]; /* 0x68, 0x6C */
+ u32 bromtimcr;
+};
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARCH_RMOBILE_SH73A0_H */
diff --git a/arch/arm/include/asm/arch-rmobile/sys_proto.h b/arch/arm/include/asm/arch-rmobile/sys_proto.h
new file mode 100644
index 0000000..fad4e4e
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/sys_proto.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+struct rmobile_sysinfo {
+ char *board_string;
+};
+extern const struct rmobile_sysinfo sysinfo;
+
+#endif