tree 9d046959fc79a25c3d6fc3172854027bc8a72320
parent fb59a78946f5f0552c91dcbdf3dd734ea5f9c446
author Fabio Estevam <fabio.estevam@freescale.com> 1386102373 -0200
committer Stefano Babic <sbabic@denx.de> 1387301922 +0100

mx6: clock: Fix the calculation of PLL_ENET frequency

According to the mx6 quad reference manual, the DIV_SELECT field of register
CCM_ANALOG_PLL_ENETn has the following meaning:

"Controls the frequency of the ethernet reference clock.
- 00 - 25MHz
- 01 - 50MHz
- 10 - 100MHz
- 11 - 125MHz"

Current logic does not handle the 25MHz case correctly, so fix it.

Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>