diff --git a/Bindings/fpga/xlnx,pr-decoupler.yaml b/Bindings/fpga/xlnx,pr-decoupler.yaml
index a7d4b8e..5bf731f 100644
--- a/Bindings/fpga/xlnx,pr-decoupler.yaml
+++ b/Bindings/fpga/xlnx,pr-decoupler.yaml
@@ -9,6 +9,9 @@
 maintainers:
   - Nava kishore Manne <nava.kishore.manne@amd.com>
 
+allOf:
+  - $ref: fpga-bridge.yaml#
+
 description: |
   The Xilinx LogiCORE Partial Reconfig(PR) Decoupler manages one or more
   decouplers/fpga bridges. The controller can decouple/disable the bridges
@@ -51,7 +54,7 @@
   - clocks
   - clock-names
 
-additionalProperties: false
+unevaluatedProperties: false
 
 examples:
   - |