diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c
index 4fb6a48..4a7b4f6 100644
--- a/arch/x86/cpu/baytrail/cpu.c
+++ b/arch/x86/cpu/baytrail/cpu.c
@@ -64,7 +64,7 @@
 
 	return 0;
 }
-EVENT_SPY(EVT_DM_POST_INIT, baytrail_uart_init);
+EVENT_SPY(EVT_DM_POST_INIT_F, baytrail_uart_init);
 
 static void set_max_freq(void)
 {
diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c
index 7877961..f30aebf 100644
--- a/arch/x86/cpu/broadwell/cpu.c
+++ b/arch/x86/cpu/broadwell/cpu.c
@@ -40,7 +40,7 @@
 
 	return 0;
 }
-EVENT_SPY(EVT_DM_POST_INIT, broadwell_init_cpu);
+EVENT_SPY(EVT_DM_POST_INIT_F, broadwell_init_cpu);
 
 void set_max_freq(void)
 {
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index cffc5d5..c988d7f 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -86,7 +86,7 @@
 
 	return 0;
 }
-EVENT_SPY(EVT_DM_POST_INIT, ivybridge_cpu_init);
+EVENT_SPY(EVT_DM_POST_INIT_F, ivybridge_cpu_init);
 
 #define PCH_EHCI0_TEMP_BAR0 0xe8000000
 #define PCH_EHCI1_TEMP_BAR0 0xe8000400
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 0a1fbb3..1be8e38 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -263,7 +263,7 @@
 
 	return 0;
 }
-EVENT_SPY(EVT_DM_POST_INIT, quark_init_pcie);
+EVENT_SPY(EVT_DM_POST_INIT_F, quark_init_pcie);
 
 int checkcpu(void)
 {
diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c
index b15926e..afec7d0 100644
--- a/arch/x86/lib/fsp2/fsp_init.c
+++ b/arch/x86/lib/fsp2/fsp_init.c
@@ -42,7 +42,7 @@
 
 	return ret;
 }
-EVENT_SPY(EVT_DM_POST_INIT, fsp_setup_pinctrl);
+EVENT_SPY(EVT_DM_POST_INIT_F, fsp_setup_pinctrl);
 
 #if !defined(CONFIG_TPL_BUILD)
 binman_sym_declare(ulong, intel_fsp_m, image_pos);