Merge tag 'u-boot-at91-2023.10-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next
First set of u-boot-at91 features for the 2023.10 cycle:
This feature set includes a new board sama5d29 Curiosity, and various
fixes and alignments for sam9x60 and sam9x60 curiosity board.
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 2678e5a..48cbdd4 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -2,7 +2,7 @@
windows_vm: windows-2019
ubuntu_vm: ubuntu-22.04
macos_vm: macOS-12
- ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20230624-20Jul2023
+ ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20230804-25Aug2023
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
@@ -163,10 +163,10 @@
. /tmp/venv/bin/activate
pip install -r test/py/requirements.txt
pip install -r tools/buildman/requirements.txt
- export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
+ export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only
export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
- ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board sandbox_spl
+ ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board tools-only
set -ex
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test
./tools/buildman/buildman -t
@@ -195,7 +195,7 @@
ln -s /opt/nokia/libc6_2.5.1-1eglibc27+0m5_armel.deb nokia_rx51_tmp/
ln -s /opt/nokia/busybox_1.10.2.legal-1osso30+0m5_armel.deb nokia_rx51_tmp/
ln -s /opt/nokia/qemu-system-arm nokia_rx51_tmp/
- export PATH=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin:$PATH
+ export PATH=/opt/gcc-13.2.0-nolibc/arm-linux-gnueabi/bin:$PATH
test/nokia_rx51_test.sh
- job: pylint
@@ -215,8 +215,8 @@
export PATH=${PATH}:~/.local/bin
echo "[MASTER]" >> .pylintrc
echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
- export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
- ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board sandbox_spl
+ export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only
+ ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board tools-only
set -ex
pylint --version
export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
@@ -275,7 +275,7 @@
TEST_PY_BD: "sandbox"
BUILD_ENV: "FTRACE=1 NO_LTO=1"
TEST_PY_TEST_SPEC: "trace"
- OVERRIDE: "-a CONFIG_TRACE=y -a CONFIG_TRACE_EARLY=y -a CONFIG_TRACE_EARLY_SIZE=0x01000000"
+ OVERRIDE: "-a CONFIG_TRACE=y -a CONFIG_TRACE_EARLY=y -a CONFIG_TRACE_EARLY_SIZE=0x01000000 -a CONFIG_TRACE_BUFFER_SIZE=0x02000000"
coreboot:
TEST_PY_BD: "coreboot"
TEST_PY_ID: "--id qemu"
@@ -426,7 +426,7 @@
cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
fi
if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
- wget -O - "https://drive.google.com/uc?id=1x6nrtWIyIRPLS2cQBwYTnT2TbOI8UjmM&export=download" |xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
+ wget -O - "https://drive.google.com/uc?id=1uJ2VkUQ8czWFZmhJQ90Tp8V_zrJ6BrBH&export=download" |xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
wget -O - "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >cbfstool;
chmod a+x cbfstool;
./cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
@@ -475,8 +475,8 @@
# Use almost the same target division in .travis.yml, only merged
# 3 small build jobs (arc/microblaze/xtensa) into one.
matrix:
- arc_microblaze_xtensa:
- BUILDMAN: "arc microblaze xtensa"
+ arc_nios2_m68k_microblaze_xtensa:
+ BUILDMAN: "arc nios2 microblaze m68k xtensa"
amlogic:
BUILDMAN: "amlogic"
arm11_arm7_arm920t_arm946es:
@@ -493,90 +493,64 @@
BUILDMAN: "bcm -x mips"
nxp_arm32:
BUILDMAN: "freescale -x powerpc,m68k,aarch64,ls101,ls102,ls104,ls108,ls20,lx216"
- nxp_ls101x:
- BUILDMAN: "freescale&ls101"
+ nxp_ls101x_ls108x:
+ BUILDMAN: "freescale&ls101 freescale&ls108"
nxp_ls102x:
BUILDMAN: "freescale&ls102 -x keymile"
nxp_ls104x:
BUILDMAN: "freescale&ls104"
- nxp_ls108x:
- BUILDMAN: "freescale&ls108"
- nxp_ls20xx:
- BUILDMAN: "freescale&ls20"
- nxp_lx216x:
- BUILDMAN: "freescale&lx216"
+ nxp_ls20xx_lx216x:
+ BUILDMAN: "freescale&ls20 freescale&lx216"
imx6:
BUILDMAN: "mx6 -x boundary,engicam,freescale,technexion,toradex"
imx:
BUILDMAN: "mx -x mx6,imx8,freescale,technexion,toradex"
imx8_imx9:
BUILDMAN: "imx8 imx9 -x engicam,technexion,toradex"
- keymile:
- BUILDMAN: "keymile"
+ keymiles_siemens_technexion:
+ BUILDMAN: "keymile siemens technexion"
keystone2_keystone3:
- BUILDMAN: "k2 k3"
+ BUILDMAN: "k2 k3 -x siemens,toradex"
sandbox_asan:
BUILDMAN: "sandbox"
OVERRIDE: "-a ASAN"
sandbox_clang_asan:
BUILDMAN: "sandbox"
OVERRIDE: "-O clang-16 -a ASAN"
- samsung_socfpga:
- BUILDMAN: "samsung socfpga"
- sun4i:
- BUILDMAN: "sun4i"
- sun5i:
- BUILDMAN: "sun5i"
- sun6i:
- BUILDMAN: "sun6i"
+ samsung_socfpga_renesas:
+ BUILDMAN: "samsung socfpga renesas"
+ sun4i_sun9i:
+ BUILDMAN: "sun4i sun9i"
+ sun5i_sun6i:
+ BUILDMAN: "sun5i sun6i"
sun7i:
BUILDMAN: "sun7i"
- sun8i_32bit:
- BUILDMAN: "sun8i&armv7"
- sun8i_64bit:
- BUILDMAN: "sun8i&aarch64"
- sun9i:
- BUILDMAN: "sun9i"
+ sun8i:
+ BUILDMAN: "sun8i"
sun50i:
BUILDMAN: "sun50i"
arm_catch_all:
- BUILDMAN: "arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,renesas,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,rk,toradex,socfpga,k2,k3,zynq"
+ BUILDMAN: "arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,renesas,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,toradex,socfpga,k2,k3,zynq"
sandbox_x86:
BUILDMAN: "sandbox x86"
- technexion:
- BUILDMAN: "technexion"
- kirkwood:
- BUILDMAN: "kirkwood"
- mvebu:
- BUILDMAN: "mvebu"
- m68k:
- BUILDMAN: "m68k"
+ kirkwood_mvebu_uniphier:
+ BUILDMAN: "kirkwood mvebu uniphier"
mips:
BUILDMAN: "mips"
powerpc:
BUILDMAN: "powerpc -x keymile"
- siemens:
- BUILDMAN: "siemens"
tegra:
BUILDMAN: "tegra -x toradex"
- am33xx_no_siemens:
- BUILDMAN: "am33xx -x siemens"
- omap:
- BUILDMAN: "omap"
- uniphier:
- BUILDMAN: "uniphier"
+ am33xx_omap:
+ BUILDMAN: "am33xx omap -x siemens"
aarch64_catch_all:
BUILDMAN: "aarch64 -x amlogic,bcm,imx8,imx9,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,renesas,sunxi,samsung,socfpga,rk,versal,zynq"
- rk_rv_non_rockchip:
- BUILDMAN: "rk|rv -x rockchip"
- rk_rv_and_rockchip:
- BUILDMAN: "(rk|rv)&rockchip"
- renesas:
- BUILDMAN: "renesas"
- zynq:
- BUILDMAN: "zynq&armv7"
- zynqmp_versal:
- BUILDMAN: "versal|zynqmp&aarch64"
+ rk_non_rockchip_64bit:
+ BUILDMAN: "rk&aarch64 -x rockchip"
+ rk_rockchip_64bit:
+ BUILDMAN: "rk&aarch64&rockchip"
+ zynq_zynqmp_versal:
+ BUILDMAN: "zynq&armv7 versal zynqmp&aarch64"
riscv:
BUILDMAN: "riscv"
steps:
diff --git a/.get_maintainer.ignore b/.get_maintainer.ignore
new file mode 100644
index 0000000..899a146
--- /dev/null
+++ b/.get_maintainer.ignore
@@ -0,0 +1 @@
+"Pali Rohár" <pali@kernel.org>
diff --git a/.gitignore b/.gitignore
index 3a4d056..002f95d 100644
--- a/.gitignore
+++ b/.gitignore
@@ -53,6 +53,7 @@
#
!.gitignore
!.mailmap
+!.get_maintainer.*
#
# Generated files
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 8010afa..6d7ffdd 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -10,7 +10,7 @@
# Grab our configured image. The source for this is found
# in the u-boot tree at tools/docker/Dockerfile
-image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20230624-20Jul2023
+image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20230804-25Aug2023
# We run some tests in different order, to catch some failures quicker.
stages:
@@ -69,7 +69,7 @@
fi
- if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
wget -O -
- "https://drive.google.com/uc?id=1x6nrtWIyIRPLS2cQBwYTnT2TbOI8UjmM&export=download" |
+ "https://drive.google.com/uc?id=1uJ2VkUQ8czWFZmhJQ90Tp8V_zrJ6BrBH&export=download" |
xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
wget -O -
"https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >
@@ -212,12 +212,12 @@
. /tmp/venv/bin/activate;
pip install -r test/py/requirements.txt;
pip install -r tools/buildman/requirements.txt;
- export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl;
+ export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only;
export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
set +e;
./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w
- --board sandbox_spl;
+ --board tools-only;
set -e;
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test;
./tools/buildman/buildman -t;
@@ -235,7 +235,7 @@
ln -s /opt/nokia/libc6_2.5.1-1eglibc27+0m5_armel.deb nokia_rx51_tmp/;
ln -s /opt/nokia/busybox_1.10.2.legal-1osso30+0m5_armel.deb nokia_rx51_tmp/;
ln -s /opt/nokia/qemu-system-arm nokia_rx51_tmp/;
- export PATH=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin:$PATH;
+ export PATH=/opt/gcc-13.2.0-nolibc/arm-linux-gnueabi/bin:$PATH;
test/nokia_rx51_test.sh
# Check for any pylint regressions
@@ -249,10 +249,10 @@
- export PATH=${PATH}:~/.local/bin
- echo "[MASTER]" >> .pylintrc
- echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
- - export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
+ - export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only
- set +e
- ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w
- --board sandbox_spl
+ --board tools-only
- set -e
- pylint --version
- export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"
@@ -315,7 +315,7 @@
TEST_PY_BD: "sandbox"
BUILD_ENV: "FTRACE=1 NO_LTO=1"
TEST_PY_TEST_SPEC: "trace"
- OVERRIDE: "-a CONFIG_TRACE=y -a CONFIG_TRACE_EARLY=y -a CONFIG_TRACE_EARLY_SIZE=0x01000000"
+ OVERRIDE: "-a CONFIG_TRACE=y -a CONFIG_TRACE_EARLY=y -a CONFIG_TRACE_EARLY_SIZE=0x01000000 -a CONFIG_TRACE_BUFFER_SIZE=0x02000000"
<<: *buildman_and_testpy_dfn
evb-ast2500 test.py:
diff --git a/Kconfig b/Kconfig
index 70efb41..91170bf 100644
--- a/Kconfig
+++ b/Kconfig
@@ -298,7 +298,7 @@
config SPL_SYS_MALLOC_F_LEN
hex "Size of malloc() pool in SPL"
depends on SYS_MALLOC_F && SPL
- default 0 if !SPL_FRAMEWORK
+ default 0x0 if !SPL_FRAMEWORK
default 0x2800 if RCAR_GEN3
default 0x2000 if IMX8MQ
default SYS_MALLOC_F_LEN
diff --git a/MAINTAINERS b/MAINTAINERS
index 47581cf..ea56662 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -123,6 +123,7 @@
F: drivers/iommu/apple_dart.c
F: drivers/nvme/nvme_apple.c
F: drivers/pci/pcie_apple.c
+F: drivers/phy/phy-apple-atc.c
F: drivers/pinctrl/pinctrl-apple.c
F: drivers/watchdog/apple_wdt.c
F: include/configs/apple.h
@@ -132,6 +133,7 @@
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-arm.git
F: arch/arm/
+F: arch/arm/dts/Makefile
F: cmd/arm/
ARM ALTERA SOCFPGA
@@ -266,6 +268,19 @@
F: drivers/net/phy/ca_phy.c
F: configs/cortina_presidio-asic-pnand_defconfig
+ARM FF-A
+M: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+S: Maintained
+F: arch/sandbox/include/asm/sandbox_arm_ffa.h
+F: arch/sandbox/include/asm/sandbox_arm_ffa_priv.h
+F: cmd/armffa.c
+F: doc/arch/arm64.ffa.rst
+F: doc/usage/cmd/armffa.rst
+F: drivers/firmware/arm-ffa/
+F: include/arm_ffa.h
+F: test/cmd/armffa.c
+F: test/dm/ffa.c
+
ARM FREESCALE IMX
M: Stefano Babic <sbabic@denx.de>
M: Fabio Estevam <festevam@gmail.com>
@@ -412,13 +427,21 @@
M: Eugen Hristev <eugen.hristev@microchip.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-at91.git
+F: arch/arm/dts/at91*
+F: arch/arm/dts/sam*
F: arch/arm/mach-at91/
F: board/atmel/
F: drivers/cpu/at91_cpu.c
F: drivers/memory/atmel-ebi.c
F: drivers/misc/microchip_flexcom.c
F: drivers/timer/atmel_tcb_timer.c
+F: include/dt-bindings/clk/at91.h
+F: include/dt-bindings/clock/at91.h
+F: include/dt-bindings/dma/at91.h
+F: include/dt-bindings/mfd/at91-usart.h
F: include/dt-bindings/mfd/atmel-flexcom.h
+F: include/dt-bindings/pinctrl/at91.h
+F: include/dt-bindings/sound/microchip,pdmc.h
F: drivers/timer/mchp-pit64b-timer.c
ARM MSC SM2S IMX8MP SOM
@@ -462,10 +485,30 @@
ARM RENESAS RMOBILE/R-CAR
M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-M: Marek Vasut <marek.vasut+renesas@gmail.com>
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-sh.git
F: arch/arm/mach-rmobile/
+F: drivers/clk/renesas/
+F: drivers/gpio/gpio-rcar.c
+F: drivers/i2c/rcar_*
+F: drivers/i2c/sh_i2c.c
+F: drivers/mmc/renesas-sdhi.c
+F: drivers/mmc/sh_mmcif*
+F: drivers/mmc/tmio-common*
+F: drivers/mtd/renesas_rpc_hf.c
+F: drivers/net/ravb.c
+F: drivers/net/rswitch.c
+F: drivers/net/sh_eth*
+F: drivers/pci/pci-rcar-*
+F: drivers/phy/phy-rcar-*
+F: drivers/phy/renesas/
+F: drivers/pinctrl/renesas/
+F: drivers/serial/serial_sh*
+F: drivers/spi/renesas_rpc_spi.c
+F: drivers/spi/sh_qspi.c
+F: drivers/sysinfo/rcar3.c
+F: drivers/usb/host/xhci-rcar*
ARM ROCKCHIP
M: Simon Glass <sjg@chromium.org>
@@ -473,12 +516,24 @@
M: Kever Yang <kever.yang@rock-chips.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-rockchip.git
+F: arch/arm/dts/px30*
F: arch/arm/dts/rk3*
F: arch/arm/dts/rockchip*
-F: arch/arm/dts/rv1108*
+F: arch/arm/dts/rv11*
F: arch/arm/include/asm/arch-rockchip/
F: arch/arm/mach-rockchip/
+F: board/amarula/vyasa-rk3288/
+F: board/anbernic/rgxx3_rk3566/
+F: board/chipspark/popmetal_rk3288
+F: board/engicam/px30_core/
+F: board/firefly/
+F: board/mqmaker/miqi_rk3288/
+F: board/phytec/phycore_rk3288
+F: board/pine64
+F: board/radxa/
F: board/rockchip/
+F: board/theobroma-systems
+F: board/vamrs/rock960_rk3399/
F: drivers/clk/rockchip/
F: drivers/gpio/rk_gpio.c
F: drivers/misc/rockchip-efuse.c
@@ -580,6 +635,7 @@
F: include/dt-bindings/pinctrl/stm32-pinfunc.h
F: include/dt-bindings/reset/stm32mp*
F: include/stm32_rcc.h
+F: tools/logos/st.bmp
F: tools/stm32image.c
N: stm
N: stm32
@@ -1544,7 +1600,8 @@
F: drivers/mtd/ubi/
UFS
-M: Faiz Abbas <faiz_abbas@ti.com>
+M: Bhupesh Sharma <bhupesh.sharma@linaro.org>
+M: Neha Malcom Francis <n-francis@ti.com>
S: Maintained
F: drivers/ufs/
@@ -1565,6 +1622,11 @@
F: drivers/usb/host/xhci*
F: include/usb/xhci.h
+UUID testing
+M: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+S: Maintained
+F: test/lib/uuid.c
+
VIDEO
M: Anatolij Gustschin <agust@denx.de>
S: Maintained
diff --git a/Makefile b/Makefile
index 96c3f14..9b90204 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
VERSION = 2023
PATCHLEVEL = 10
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*
@@ -1328,13 +1328,18 @@
# Use 'make BINMAN_VERBOSE=3' to set vebosity level
default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE))
+# Temporary workaround for Venice boards
+ifneq ($(CONFIG_TARGET_IMX8MM_VENICE),$(CONFIG_TARGET_IMX8MN_VENICE),$(CONFIG_TARGET_IMX8MP_VENICE),)
+ignore_dups := --ignore-dup-phandles
+endif
+
quiet_cmd_binman = BINMAN $@
cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
$(foreach f,$(BINMAN_TOOLPATHS),--toolpath $(f)) \
--toolpath $(objtree)/tools \
$(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \
build -u -d u-boot.dtb -O . -m \
- $(if $(BINMAN_ALLOW_MISSING),--allow-missing --ignore-missing) \
+ --allow-missing $(if $(BINMAN_ALLOW_MISSING),--ignore-missing) \
-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
-I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \
$(foreach f,$(BINMAN_INDIRS),-I $(f)) \
@@ -1349,6 +1354,7 @@
-a spl-dtb=$(CONFIG_SPL_OF_REAL) \
-a tpl-dtb=$(CONFIG_TPL_OF_REAL) \
-a pre-load-key-path=${PRE_LOAD_KEY_PATH} \
+ $(ignore_dups) \
$(BINMAN_$(@F))
OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h
index 1c9c9db..ffad4a6 100644
--- a/arch/arc/include/asm/sections.h
+++ b/arch/arc/include/asm/sections.h
@@ -8,7 +8,8 @@
#include <asm-generic/sections.h>
-extern ulong __ivt_start;
-extern ulong __ivt_end;
+extern char __ivt_start[];
+extern char __ivt_end[];
+extern char __text_end[];
#endif /* __ASM_ARC_SECTIONS_H */
diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c
index 7f531c9..fd6f4fb 100644
--- a/arch/arc/lib/relocate.c
+++ b/arch/arc/lib/relocate.c
@@ -6,32 +6,27 @@
#include <common.h>
#include <elf.h>
#include <log.h>
-#include <asm-generic/sections.h>
+#include <asm/sections.h>
#include <asm/global_data.h>
-extern ulong __image_copy_start;
-extern ulong __ivt_start;
-extern ulong __ivt_end;
-extern ulong __text_end;
-
DECLARE_GLOBAL_DATA_PTR;
int copy_uboot_to_ram(void)
{
- size_t len = (size_t)&__image_copy_end - (size_t)&__image_copy_start;
+ size_t len = (size_t)__image_copy_end - (size_t)__image_copy_start;
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
- memcpy((void *)gd->relocaddr, (void *)&__image_copy_start, len);
+ memcpy((void *)gd->relocaddr, (void *)__image_copy_start, len);
return 0;
}
int clear_bss(void)
{
- ulong dst_addr = (ulong)&__bss_start + gd->reloc_off;
- size_t len = (size_t)&__bss_end - (size_t)&__bss_start;
+ ulong dst_addr = (ulong)__bss_start + gd->reloc_off;
+ size_t len = (size_t)__bss_end - (size_t)__bss_start;
memset((void *)dst_addr, 0x00, len);
@@ -43,8 +38,8 @@
*/
int do_elf_reloc_fixups(void)
{
- Elf32_Rela *re_src = (Elf32_Rela *)(&__rel_dyn_start);
- Elf32_Rela *re_end = (Elf32_Rela *)(&__rel_dyn_end);
+ Elf32_Rela *re_src = (Elf32_Rela *)__rel_dyn_start;
+ Elf32_Rela *re_end = (Elf32_Rela *)__rel_dyn_end;
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
@@ -60,8 +55,8 @@
offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
/* Check that the location of the relocation is in .text */
- if (offset_ptr_rom >= (Elf32_Addr *)&__image_copy_start &&
- offset_ptr_rom < (Elf32_Addr *)&__image_copy_end) {
+ if (offset_ptr_rom >= (Elf32_Addr *)__image_copy_start &&
+ offset_ptr_rom < (Elf32_Addr *)__image_copy_end) {
unsigned int val, do_swap = 0;
/* Switch to the in-RAM version */
offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom +
@@ -69,11 +64,11 @@
#ifdef __LITTLE_ENDIAN__
/* If location in ".text" section swap value */
- if (((u32)offset_ptr_rom >= (u32)&__text_start &&
- (u32)offset_ptr_rom <= (u32)&__text_end)
+ if (((u32)offset_ptr_rom >= (u32)__text_start &&
+ (u32)offset_ptr_rom <= (u32)__text_end)
#if defined(__ARC700__) || defined(__ARC600__)
- || ((u32)offset_ptr_rom >= (u32)&__ivt_start &&
- (u32)offset_ptr_rom <= (u32)&__ivt_end)
+ || ((u32)offset_ptr_rom >= (u32)__ivt_start &&
+ (u32)offset_ptr_rom <= (u32)__ivt_end)
#endif
)
do_swap = 1;
@@ -96,8 +91,8 @@
val = (val << 16) | (val >> 16);
/* Check that the target points into executable */
- if (val < (unsigned int)&__image_copy_start ||
- val > (unsigned int)&__image_copy_end) {
+ if (val < (unsigned int)__image_copy_start ||
+ val > (unsigned int)__image_copy_end) {
/* TODO: Use panic() instead of debug()
*
* For some reason GCC might generate
@@ -106,7 +101,7 @@
* ----------------------->8--------------------
* static int setup_mon_len(void)
* {
- * gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
+ * gd->mon_len = (ulong)__bss_end - CONFIG_SYS_MONITOR_BASE;
* return 0;
* }
* ----------------------->8--------------------
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 97c25b4..71f820e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -998,6 +998,7 @@
select OF_BOARD_SETUP
select OF_CONTROL
select PCI
+ select PHY
select PINCTRL
select POSITION_INDEPENDENT
select POWER_DOMAIN
@@ -1036,6 +1037,16 @@
imply DM_RTC
imply RTC_PL031
imply OF_HAS_PRIOR_STAGE
+ imply VIDEO
+ imply VIDEO_BOCHS
+ imply SYS_WHITE_ON_BLACK
+ imply SYS_CONSOLE_IS_IN_ENV
+ imply PRE_CONSOLE_BUFFER
+ imply USB
+ imply USB_XHCI_HCD
+ imply USB_XHCI_PCI
+ imply USB_KEYBOARD
+ imply CMD_USB
config ARCH_RMOBILE
bool "Renesas ARM SoCs"
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index 4d21e3d..6d6166c 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -100,7 +100,7 @@
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
- mx28_fixup_vt((uint32_t)&_start);
+ mx28_fixup_vt((uint32_t)_start);
/*
* Enable NAND clock
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index 5598c55..5e7bdb7 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -103,7 +103,7 @@
*/
/* cppcheck-suppress nullPointer */
- memcpy(0x0, &_start, 0x60);
+ memcpy(0x0, _start, 0x60);
}
static void mxs_spl_console_init(void)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 3e292bf..46ace7e 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -98,7 +98,6 @@
config SYS_FSL_QSPI_SKIP_CLKSEL
bool "Skip setting QSPI clock during SoC init"
- default 0
help
To improve startup times when booting from QSPI flash, the QSPI
frequency can be set very early in the boot process. If this option
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index a8b493e..d46934c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -739,7 +739,7 @@
config SYS_FSL_BOOTROM_BASE
hex
depends on FSL_LSCH2
- default 0
+ default 0x0
config SYS_FSL_BOOTROM_SIZE
hex
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 359cbc0..3bfdc3f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -575,11 +575,6 @@
return vdd;
}
-__weak int board_switch_core_volt(u32 vdd)
-{
- return 0;
-}
-
static int setup_core_volt(u32 vdd)
{
return board_setup_core_volt(vdd);
@@ -810,7 +805,7 @@
#ifdef CONFIG_TFABOOT
#define MAX_BOOTCMD_SIZE 512
-int fsl_setenv_bootcmd(void)
+__weak int fsl_setenv_bootcmd(void)
{
int ret;
enum boot_src src = get_boot_src();
diff --git a/arch/arm/cpu/armv8/smccc-call.S b/arch/arm/cpu/armv8/smccc-call.S
index dc92b28..93f66d3 100644
--- a/arch/arm/cpu/armv8/smccc-call.S
+++ b/arch/arm/cpu/armv8/smccc-call.S
@@ -1,7 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015, Linaro Limited
- */
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+*/
#include <linux/linkage.h>
#include <linux/arm-smccc.h>
#include <generated/asm-offsets.h>
@@ -45,3 +49,54 @@
ENTRY(__arm_smccc_hvc)
SMCCC hvc
ENDPROC(__arm_smccc_hvc)
+
+#ifdef CONFIG_ARM64
+
+ .macro SMCCC_1_2 instr
+ /* Save `res` and free a GPR that won't be clobbered */
+ stp x1, x19, [sp, #-16]!
+
+ /* Ensure `args` won't be clobbered while loading regs in next step */
+ mov x19, x0
+
+ /* Load the registers x0 - x17 from the struct arm_smccc_1_2_regs */
+ ldp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
+ ldp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]
+ ldp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]
+ ldp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]
+ ldp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
+ ldp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]
+ ldp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]
+ ldp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]
+ ldp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
+
+ \instr #0
+
+ /* Load the `res` from the stack */
+ ldr x19, [sp]
+
+ /* Store the registers x0 - x17 into the result structure */
+ stp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
+ stp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]
+ stp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]
+ stp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]
+ stp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
+ stp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]
+ stp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]
+ stp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]
+ stp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
+
+ /* Restore original x19 */
+ ldp xzr, x19, [sp], #16
+ ret
+ .endm
+
+/*
+ * void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args,
+ * struct arm_smccc_1_2_regs *res);
+ */
+ENTRY(arm_smccc_1_2_smc)
+ SMCCC_1_2 smc
+ENDPROC(arm_smccc_1_2_smc)
+
+#endif
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index f3ea858..6cc1d26 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -58,7 +58,7 @@
.globl save_boot_params_ret
save_boot_params_ret:
-#if CONFIG_POSITION_INDEPENDENT
+#if CONFIG_POSITION_INDEPENDENT && !defined(CONFIG_SPL_BUILD)
/* Verify that we're 4K aligned. */
adr x0, _start
ands x0, x0, #0xfff
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8fa8442..928511c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -178,6 +178,7 @@
rk3566-soquartz-cm4.dtb \
rk3566-soquartz-model-a.dtb \
rk3568-evb.dtb \
+ rk3568-lubancat-2.dtb \
rk3568-nanopi-r5c.dtb \
rk3568-nanopi-r5s.dtb \
rk3568-odroid-m1.dtb \
@@ -254,9 +255,22 @@
tegra20-ventana.dtb \
tegra20-colibri.dtb \
tegra30-apalis.dtb \
+ tegra30-asus-nexus7-grouper-PM269.dtb \
+ tegra30-asus-nexus7-grouper-E1565.dtb \
+ tegra30-asus-nexus7-tilapia-E1565.dtb \
+ tegra30-asus-p1801-t.dtb \
+ tegra30-asus-tf201.dtb \
+ tegra30-asus-tf300t.dtb \
+ tegra30-asus-tf300tg.dtb \
+ tegra30-asus-tf300tl.dtb \
+ tegra30-asus-tf600t.dtb \
+ tegra30-asus-tf700t.dtb \
tegra30-beaver.dtb \
tegra30-cardhu.dtb \
tegra30-colibri.dtb \
+ tegra30-htc-endeavoru.dtb \
+ tegra30-lg-p880.dtb \
+ tegra30-lg-p895.dtb \
tegra30-tec-ng.dtb \
tegra114-dalmore.dtb \
tegra124-apalis.dtb \
@@ -1322,7 +1336,9 @@
k3-am642-r5-sk.dtb
dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
- k3-am625-r5-sk.dtb
+ k3-am625-r5-sk.dtb \
+ k3-am625-verdin-wifi-dev.dtb \
+ k3-am625-verdin-r5.dtb
dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-sk.dtb \
k3-am62a7-r5-sk.dtb
@@ -1344,6 +1360,8 @@
mt7986b-sd-rfb.dtb \
mt7986a-emmc-rfb.dtb \
mt7986b-emmc-rfb.dtb \
+ mt7988-rfb.dtb \
+ mt7988-sd-rfb.dtb \
mt8183-pumpkin.dtb \
mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \
diff --git a/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi
index 89566bf..4e6700d 100644
--- a/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi
+++ b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi
@@ -6,6 +6,16 @@
/{
aliases {
spi0 = &qspi;
+ ethernet0 = &dpmac7;
+ ethernet1 = &dpmac8;
+ ethernet2 = &dpmac9;
+ ethernet3 = &dpmac10;
+ ethernet4 = &dpmac3;
+ ethernet5 = &dpmac4;
+ ethernet6 = &dpmac5;
+ ethernet7 = &dpmac6;
+ ethernet8 = &dpmac2;
+ ethernet9 = &dpmac1;
};
};
diff --git a/arch/arm/dts/k3-am62-verdin-dev.dtsi b/arch/arm/dts/k3-am62-verdin-dev.dtsi
new file mode 100644
index 0000000..846caee
--- /dev/null
+++ b/arch/arm/dts/k3-am62-verdin-dev.dtsi
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ *
+ * Common dtsi for Verdin AM62 SoM on Development carrier board
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
+ * https://www.toradex.com/products/carrier-board/verdin-development-board-kit
+ */
+
+/* Verdin ETHs */
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>;
+ status = "okay";
+};
+
+/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
+&cpsw3g_mdio {
+ status = "okay";
+
+ cpsw3g_phy1: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eth2_rgmii_int>;
+ micrel,led-mode = <0>;
+ };
+};
+
+/* Verdin ETH_1 (On-module PHY) */
+&cpsw_port1 {
+ status = "okay";
+};
+
+/* Verdin ETH_2_RGMII */
+&cpsw_port2 {
+ phy-handle = <&cpsw3g_phy1>;
+ phy-mode = "rgmii-rxid";
+ status = "okay";
+};
+
+/* Verdin PWM_1, PWM_2 */
+&epwm0 {
+ status = "okay";
+};
+
+/* Verdin PWM_3_DSI */
+&epwm1 {
+ status = "okay";
+};
+
+&main_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>,
+ <&pinctrl_gpio_5>,
+ <&pinctrl_gpio_6>,
+ <&pinctrl_gpio_7>,
+ <&pinctrl_gpio_8>;
+};
+
+/* Verdin I2C_1 */
+&main_i2c1 {
+ status = "okay";
+
+ /* IO Expander */
+ gpio_expander_21: gpio@21 {
+ compatible = "nxp,pcal6416";
+ reg = <0x21>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ /* Current measurement into module VCC */
+ hwmon@40 {
+ compatible = "ti,ina219";
+ reg = <0x40>;
+ shunt-resistor = <10000>;
+ };
+
+ /* Temperature sensor */
+ sensor@4f {
+ compatible = "ti,tmp75c";
+ reg = <0x4f>;
+ };
+
+ /* EEPROM */
+ eeprom@57 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+/* Verdin I2C_2_DSI */
+&main_i2c2 {
+ status = "okay";
+};
+
+/* Verdin I2C_4_CSI */
+&main_i2c3 {
+ status = "okay";
+};
+
+/* Verdin CAN_1 */
+&main_mcan0 {
+ status = "okay";
+};
+
+/* Verdin SPI_1 */
+&main_spi1 {
+ status = "okay";
+};
+
+/* Verdin UART_3 */
+&main_uart0 {
+ status = "okay";
+};
+
+/* Verdin UART_1, connector X50 through RS485 transceiver. */
+&main_uart1 {
+ linux,rs485-enabled-at-boot-time;
+ rs485-rx-during-tx;
+ status = "okay";
+};
+
+/* Verdin I2S_1 */
+&mcasp0 {
+ status = "okay";
+};
+
+&mcu_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_1>,
+ <&pinctrl_gpio_2>,
+ <&pinctrl_gpio_3>,
+ <&pinctrl_gpio_4>;
+};
+
+/* Verdin I2C_3_HDMI */
+&mcu_i2c0 {
+ status = "okay";
+};
+
+/* Verdin UART_4 */
+&mcu_uart0 {
+ status = "okay";
+};
+
+/* Verdin QSPI_1 */
+&ospi0 {
+ status = "okay";
+};
+
+/* Verdin SD_1 */
+&sdhci1 {
+ ti,driver-strength-ohm = <33>;
+ status = "okay";
+};
+
+/* Verdin USB_1 */
+&usbss0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+/* Verdin USB_2 */
+&usbss1 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+/* Verdin CTRL_WAKE1_MICO# */
+&verdin_gpio_keys {
+ status = "okay";
+};
+
+/* Verdin UART_2 */
+&wkup_uart0 {
+ /* FIXME: WKUP UART0 is used by DM firmware */
+ status = "reserved";
+};
diff --git a/arch/arm/dts/k3-am62-verdin-wifi.dtsi b/arch/arm/dts/k3-am62-verdin-wifi.dtsi
new file mode 100644
index 0000000..90ddc71
--- /dev/null
+++ b/arch/arm/dts/k3-am62-verdin-wifi.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ *
+ * Common dtsi for Verdin AM62 SoM WB variant
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
+ */
+
+/ {
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_en>;
+ reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_LOW>;
+ };
+};
+
+/* On-module Wi-Fi */
+&sdhci2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci2>;
+ bus-width = <4>;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ ti,fails-without-test-cd;
+ ti,driver-strength-ohm = <50>;
+ vmmc-supply = <®_3v3>;
+ status = "okay";
+};
+
+/* On-module Bluetooth */
+&main_uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/k3-am62-verdin.dtsi b/arch/arm/dts/k3-am62-verdin.dtsi
new file mode 100644
index 0000000..57dd061
--- /dev/null
+++ b/arch/arm/dts/k3-am62-verdin.dtsi
@@ -0,0 +1,1401 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ *
+ * Common dtsi for Verdin AM62 SoM
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ aliases {
+ ethernet0 = &cpsw_port1;
+ ethernet1 = &cpsw_port2;
+ i2c0 = &main_i2c0;
+ i2c1 = &main_i2c1;
+ i2c2 = &main_i2c2;
+ i2c3 = &mcu_i2c0;
+ i2c4 = &main_i2c3;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ mmc2 = &sdhci2;
+ rtc0 = &rtc_i2c;
+ rtc1 = &wkup_rtc0;
+ serial0 = &main_uart1;
+ serial1 = &wkup_uart0;
+ serial2 = &main_uart0;
+ serial3 = &mcu_uart0;
+ serial4 = &main_uart5;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ };
+
+ verdin_gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_wake1_mico>;
+ status = "disabled";
+
+ verdin_key_wakeup: key-wakeup {
+ debounce-interval = <10>;
+ /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
+ gpios = <&main_gpio0 32 GPIO_ACTIVE_LOW>;
+ label = "Wake-Up";
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0x00000000 0x40000000>; /* 1G RAM */
+ };
+
+ opp-table {
+ /* Add 1.4GHz OPP. Requires VDD_CORE to be at 0.85V */
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-supported-hw = <0x01 0x0004>;
+ clock-latency-ns = <6000000>;
+ };
+ };
+
+ /* Module Power Supply */
+ reg_vsodimm: regulator-vsodimm {
+ compatible = "regulator-fixed";
+ regulator-name = "+V_SODIMM";
+ };
+
+ /* Non PMIC On-module Supplies */
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "On-module +V3.3";
+ vin-supply = <®_vsodimm>;
+ };
+
+ reg_1v2_dsi: regulator-1v2-dsi {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microvolt = <1200000>;
+ regulator-name = "On-module +V1.2_DSI";
+ vin-supply = <®_1v8>;
+ };
+
+ /* Enabled by +V1.2_DSI */
+ reg_1v8_dsi: regulator-1v8-dsi {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "On-module +V1.8_DSI";
+ vin-supply = <®_1v8>;
+ };
+
+ /* Enabled by +V2.5_ETH */
+ reg_1v0_eth: regulator-1v0-eth {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1000000>;
+ regulator-min-microvolt = <1000000>;
+ regulator-name = "On-module +V1.0_ETH";
+ vin-supply = <®_1v8>;
+ };
+
+ /* Enabled by +V2.5_ETH */
+ reg_1v8_eth: regulator-1v8-eth {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "On-module +V1.8_ETH";
+ vin-supply = <®_1v8>;
+ };
+
+ /* Verdin SD_1 Power Supply */
+ reg_sdhc1_vmmc: regulator-sdhci1 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sd1_pwr_en>;
+ enable-active-high;
+ /* Verdin SD_1_PWR_EN (SODIMM 76) */
+ gpio = <&main_gpio0 29 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <100000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "+V3.3_SD";
+ startup-delay-us = <2000>;
+ };
+
+ reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_vsel_sd>;
+ /* PMIC_VSEL_SD */
+ gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>;
+ regulator-name = "LDO1-VSEL-SD (PMIC)";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
+ vin-supply = <®_sd_3v3_1v8>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_tfa_ddr: tfa@9e780000 {
+ reg = <0x00 0x9e780000 0x00 0x80000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+ alignment = <0x1000>;
+ no-map;
+ };
+
+ wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9db00000 0x00 0xc00000>;
+ no-map;
+ };
+ };
+};
+
+&main_pmx0 {
+ /* Verdin PWM_1 */
+ pinctrl_epwm0_a: main-epwm0a-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01b4, PIN_OUTPUT, 2) /* (A13) SPI0_CS0.EHRPWM0_A */ /* SODIMM 15 */
+ >;
+ };
+
+ /* Verdin PWM_2 */
+ pinctrl_epwm0_b: main-epwm0b-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (C13) SPI0_CS1.EHRPWM0_B */ /* SODIMM 16 */
+ >;
+ };
+
+ /* Verdin PWM_3_DSI */
+ pinctrl_epwm1_a: main-epwm1a-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01bc, PIN_OUTPUT, 2) /* (A14) SPI0_CLK.EHRPWM1_A */ /* SODIMM 19 */
+ >;
+ };
+
+ /* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */
+ pinctrl_qspi1_clk_gpio: main-gpio0-0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0000, PIN_INPUT, 7) /* (H24) OSPI0_CLK.GPIO0_0 */ /* SODIMM 52 */
+ >;
+ };
+
+ /* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */
+ pinctrl_qspi1_io0_gpio: main-gpio0-3-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */ /* SODIMM 56 */
+ >;
+ };
+
+ /* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */
+ pinctrl_qspi1_io1_gpio: main-gpio0-4-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */ /* SODIMM 58 */
+ >;
+ };
+
+ /* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */
+ pinctrl_qspi1_io2_gpio: main-gpio0-5-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */ /* SODIMM 60 */
+ >;
+ };
+
+ /* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */
+ pinctrl_qspi1_io3_gpio: main-gpio0-6-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */ /* SODIMM 62 */
+ >;
+ };
+
+ /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */
+ pinctrl_qspi1_cs_gpio: main-gpio0-11-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */
+ >;
+ };
+
+ /* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */
+ pinctrl_qspi1_cs2_gpio: main-gpio0-12-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */ /* SODIMM 64 */
+ >;
+ };
+
+ /* WiFi_W_WKUP_HOST# */
+ pinctrl_wifi_w_wkup_host: main-gpio0-15-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x003c, PIN_INPUT, 7) /* (M25) GPMC0_AD0.GPIO0_15 */ /* SODIMM 174 */
+ >;
+ };
+
+ /* WiFi_BT_WKUP_HOST# */
+ pinctrl_bt_wkup_host: main-gpio0-16-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0040, PIN_INPUT, 7) /* (N23) GPMC0_AD1.GPIO0_16 */ /* SODIMM 172 */
+ >;
+ };
+
+ /* PMIC_ETH_RESET# */
+ pinctrl_eth_reset: main-gpio0-17-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0044, PIN_INPUT, 7) /* (N24) GPMC0_AD2.GPIO0_17 */
+ >;
+ };
+
+ /* PMIC_BRIDGE_RESET# */
+ pinctrl_bridge_reset: main-gpio0-20-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0050, PIN_INPUT, 7) /* (P22) GPMC0_AD5.GPIO0_20 */
+ >;
+ };
+
+ /* PMIC_VSEL_SD */
+ pinctrl_vsel_sd: main-gpio0-21-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0054, PIN_INPUT, 7) /* (P21) GPMC0_AD6.GPIO0_21 */
+ >;
+ };
+
+ /* PMIC_EN_WIFI */
+ pinctrl_wifi_en: main-gpio0-22-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0058, PIN_INPUT, 7) /* (R23) GPMC0_AD7.GPIO0_22 */
+ >;
+ };
+
+ /* PMIC_ETH_INT# */
+ pinctrl_eth_int: main-gpio0-25-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0064, PIN_INPUT_PULLUP, 7) /* (T25) GPMC0_AD10.GPIO0_25 */
+ >;
+ };
+
+ /* WiFi_WKUP_BT# */
+ pinctrl_wifi_wkup_bt: main-gpio0-26-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0068, PIN_INPUT, 7) /* (R21) GPMC0_AD11.GPIO0_26 */
+ >;
+ };
+
+ /* WiFi_WKUP_WLAN# */
+ pinctrl_wifi_wkup_wlan: main-gpio0-27-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x006c, PIN_INPUT, 7) /* (T22) GPMC0_AD12.GPIO0_27 */
+ >;
+ };
+
+ /* Verdin SD_1_PWR_EN */
+ pinctrl_sd1_pwr_en: main-gpio0-29-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0074, PIN_INPUT, 7) /* (U25) GPMC0_AD14.GPIO0_29 */ /* SODIMM 76 */
+ >;
+ };
+
+ /* Verdin DSI_1_BKL_EN */
+ pinctrl_dsi1_bkl_en: main-gpio0-30-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0078, PIN_INPUT, 7) /* (U24) GPMC0_AD15.GPIO0_30 */ /* SODIMM 21 */
+ >;
+ };
+
+ /* Verdin CTRL_SLEEP_MOCI# */
+ pinctrl_ctrl_sleep_moci: main-gpio0-31-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x007c, PIN_INPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ /* SODIMM 256 */
+ >;
+ };
+
+ /* Verdin CTRL_WAKE1_MICO# */
+ pinctrl_ctrl_wake1_mico: main-gpio0-32-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */ /* SODIMM 252 */
+ >;
+ };
+
+ /* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2 interface) */
+ pinctrl_i2s_2_d_out_gpio: main-gpio0-34-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x008c, PIN_INPUT, 7) /* (L25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */
+ >;
+ };
+
+ /* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2 interface) */
+ pinctrl_i2s_2_bclk_gpio: main-gpio0-35-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0090, PIN_INPUT, 7) /* (M24) GPMC0_BE0n_CLE.GPIO0_35 */ /* SODIMM 42 */
+ >;
+ };
+
+ /* Verdin GPIO_6 */
+ pinctrl_gpio_6: main-gpio0-36-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0094, PIN_INPUT, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */ /* SODIMM 218 */
+ >;
+ };
+
+ /* Verdin ETH_2_RGMII_INT# */
+ pinctrl_eth2_rgmii_int: main-gpio0-38-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x009c, PIN_INPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ /* SODIMM 189 */
+ >;
+ };
+
+ /* Verdin GPIO_5 */
+ pinctrl_gpio_5: main-gpio0-40-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ /* SODIMM 216 */
+ >;
+ };
+
+ /* Verdin GPIO_7 */
+ pinctrl_gpio_7: main-gpio0-41-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ /* SODIMM 220 */
+ >;
+ };
+
+ /* Verdin GPIO_8 */
+ pinctrl_gpio_8: main-gpio0-42-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */ /* SODIMM 222 */
+ >;
+ };
+
+ /* Verdin USB_1_OC# */
+ pinctrl_usb1_oc: main-gpio0-71-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0124, PIN_INPUT, 7) /* (A23) MMC2_SDCD.GPIO0_71 */ /* SODIMM 157 */
+ >;
+ };
+
+ /* Verdin USB_2_OC# */
+ pinctrl_usb2_oc: main-gpio0-72-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0128, PIN_INPUT, 7) /* (B23) MMC2_SDWP.GPIO0_72 */ /* SODIMM 187 */
+ >;
+ };
+
+ /* Verdin PWM_3_DSI as GPIO */
+ pinctrl_pwm3_dsi_gpio: main-gpio1-17-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01bc, PIN_INPUT, 7) /* (A14) SPI0_CLK.GPIO1_17 */ /* SODIMM 19 */
+ >;
+ };
+
+ /* Verdin QSPI_1_DQS as GPIO */
+ pinctrl_qspi1_dqs_gpio: main-gpio1-18-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01c0, PIN_INPUT, 7) /* (B13) SPI0_D0.GPIO1_18 */ /* SODIMM 66 */
+ >;
+ };
+
+ /* Verdin USB_1_ID */
+ pinctrl_usb0_id: main-gpio1-19-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1.GPIO1_19 */ /* SODIMM 161 */
+ >;
+ };
+
+ /* Verdin DSI_1_INT# (pulled-up as active-low) */
+ pinctrl_dsi1_int: main-gpio1-49-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0244, PIN_INPUT_PULLUP, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ /* SODIMM 17 */
+ >;
+ };
+
+ /* On-module I2C - PMIC_I2C */
+ pinctrl_i2c0: main-i2c0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01e0, PIN_INPUT, 0) /* (B16) I2C0_SCL */ /* PMIC_I2C_SCL */
+ AM62X_IOPAD(0x01e4, PIN_INPUT, 0) /* (A16) I2C0_SDA */ /* PMIC_I2C_SDA */
+ >;
+ };
+
+ /* Verdin I2C_1 */
+ pinctrl_i2c1: main-i2c1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ /* SODIMM 14 */
+ AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ /* SODIMM 12 */
+ >;
+ };
+
+ /* Verdin I2C_2_DSI */
+ pinctrl_i2c2: main-i2c2-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x00b0, PIN_INPUT, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ /* SODIMM 55 */
+ AM62X_IOPAD(0x00b4, PIN_INPUT, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ /* SODIMM 53 */
+ >;
+ };
+
+ /* Verdin I2C_4_CSI */
+ pinctrl_i2c3: main-i2c3-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01d0, PIN_INPUT, 2) /* (A15) UART0_CTSn.I2C3_SCL */ /* SODIMM 95 */
+ AM62X_IOPAD(0x01d4, PIN_INPUT, 2) /* (B15) UART0_RTSn.I2C3_SDA */ /* SODIMM 93 */
+ >;
+ };
+
+ /* I2S_1_MCLK */
+ pinctrl_i2s1_mclk: main-system-audio-ext-reflock1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ /* SODIMM 38 */
+ >;
+ };
+
+ /* Verdin I2S_1 */
+ pinctrl_mcasp0: main-mcasp0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01a4, PIN_INPUT, 0) /* (B20) MCASP0_ACLKX */ /* SODIMM 30 */
+ AM62X_IOPAD(0x01a8, PIN_INPUT, 0) /* (D20) MCASP0_AFSX */ /* SODIMM 32 */
+ AM62X_IOPAD(0x01a0, PIN_OUTPUT, 0) /* (E18) MCASP0_AXR0 */ /* SODIMM 34 */
+ AM62X_IOPAD(0x019c, PIN_INPUT, 0) /* (B18) MCASP0_AXR1 */ /* SODIMM 36 */
+ >;
+ };
+
+ /* Verdin I2S_2 */
+ pinctrl_mcasp1: main-mcasp1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ /* SODIMM 42 */
+ AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ /* SODIMM 44 */
+ AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEn.MCASP1_AXR0 */ /* SODIMM 46 */
+ AM62X_IOPAD(0x0088, PIN_INPUT, 2) /* (L24) GPMC0_OEn_REn.MCASP1_AXR1 */ /* SODIMM 48 */
+ >;
+ };
+
+ /* Verdin CAN_1 */
+ pinctrl_mcan0: main-mcan0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ /* SODIMM 22 */
+ AM62X_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ /* SODIMM 20 */
+ >;
+ };
+
+ /* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
+ pinctrl_mdio: main-mdio1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ /* ETH_1_MDC, SODIMM 193 */
+ AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ /* ETH_1_MDIO, SODIMM 191 */
+ >;
+ };
+
+ /* On-module eMMC */
+ pinctrl_sdhci0: main-mmc0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
+ AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
+ AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
+ AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
+ AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
+ AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */
+ AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
+ AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
+ AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
+ AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
+ >;
+ };
+
+ /* Verdin SD_1 */
+ pinctrl_sdhci1: main-mmc1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ /* SODIMM 74 */
+ AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ /* SODIMM 78 */
+ AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ /* SODIMM 80 */
+ AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ /* SODIMM 82 */
+ AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ /* SODIMM 70 */
+ AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ /* SODIMM 72 */
+ AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ /* SODIMM 84 */
+ >;
+ };
+
+ /* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */
+ pinctrl_sdhci2: main-mmc2-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ /* WiFi_SDIO_CMD */
+ AM62X_IOPAD(0x118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ /* WiFi_SDIO_CLK */
+ AM62X_IOPAD(0x114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */ /* WiFi_SDIO_DATA0 */
+ AM62X_IOPAD(0x110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */ /* WiFi_SDIO_DATA1 */
+ AM62X_IOPAD(0x10c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */ /* WiFi_SDIO_DATA2 */
+ AM62X_IOPAD(0x108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */ /* WiFi_SDIO_DATA3 */
+ AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */
+ >;
+ };
+
+ /* Verdin QSPI_1 */
+ pinctrl_ospi0: main-ospi0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ /* SODIMM 52 */
+ AM62X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ /* SODIMM 54 */
+ AM62X_IOPAD(0x0030, PIN_OUTPUT, 0) /* (G21) OSPI0_CSn1 */ /* SODIMM 64 */
+ AM62X_IOPAD(0x000c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ /* SODIMM 56 */
+ AM62X_IOPAD(0x0010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ /* SODIMM 58 */
+ AM62X_IOPAD(0x0014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ /* SODIMM 60 */
+ AM62X_IOPAD(0x0018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ /* SODIMM 62 */
+ >;
+ };
+
+ /* Verdin ETH_1 RGMII (On-module PHY) */
+ pinctrl_rgmii1: main-rgmii1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
+ AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
+ AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
+ AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
+ AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
+ AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
+ AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
+ AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
+ AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
+ AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
+ AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
+ AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
+ >;
+ };
+
+ /* Verdin ETH_2 RGMII */
+ pinctrl_rgmii2: main-rgmii2-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ /* SODIMM 201 */
+ AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ /* SODIMM 203 */
+ AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ /* SODIMM 205 */
+ AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ /* SODIMM 207 */
+ AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ /* SODIMM 197 */
+ AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ /* SODIMM 199 */
+ AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ /* SODIMM 221 */
+ AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ /* SODIMM 219 */
+ AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ /* SODIMM 217 */
+ AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ /* SODIMM 215 */
+ AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ /* SODIMM 213 */
+ AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ /* SODIMM 211 */
+ >;
+ };
+
+ /* Verdin SPI_1 */
+ pinctrl_spi1: main-spi1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0020, PIN_INPUT, 1) /* (J25) OSPI0_D5.SPI1_CLK */ /* SODIMM 196 */
+ AM62X_IOPAD(0x001c, PIN_INPUT, 1) /* (J23) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */
+ AM62X_IOPAD(0x0024, PIN_INPUT, 1) /* (H25) OSPI0_D6.SPI1_D0 */ /* SODIMM 200 */
+ AM62X_IOPAD(0x0028, PIN_INPUT, 1) /* (J22) OSPI0_D7.SPI1_D1 */ /* SODIMM 198 */
+ >;
+ };
+
+ /* ETH_25MHz_CLK */
+ pinctrl_eth_clock: main-system-clkout0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01f0, PIN_OUTPUT_PULLUP, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */
+ >;
+ };
+
+ /* PMIC_EXTINT# */
+ pinctrl_pmic_extint: main-system-extint-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */
+ >;
+ };
+
+ /* Verdin UART_3, used as the Linux console */
+ pinctrl_uart0: main-uart0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x1c8, PIN_INPUT_PULLUP, 0) /* (D14) UART0_RXD */ /* SODIMM 147 */
+ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ /* SODIMM 149 */
+ >;
+ };
+
+ /* Verdin UART_1 */
+ pinctrl_uart1: main-uart1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0194, PIN_INPUT_PULLUP, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ /* SODIMM 135 */
+ AM62X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ /* SODIMM 133 */
+ AM62X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ /* SODIMM 129 */
+ AM62X_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ /* SODIMM 131 */
+ >;
+ };
+
+ /* Bluetooth on WB SKUs, module-specific UART otherwise */
+ pinctrl_uart5: main-uart5-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0008, PIN_INPUT_PULLUP, 5) /* (J24) OSPI0_DQS.UART5_CTSn */ /* WiFi_UART_CTS */
+ AM62X_IOPAD(0x0004, PIN_OUTPUT, 5) /* (G25) OSPI0_LBCLKO.UART5_RTSn */ /* WiFi_UART_RTS */
+ AM62X_IOPAD(0x0034, PIN_INPUT_PULLUP, 5) /* (H21) OSPI0_CSn2.UART5_RXD */ /* WiFi_UART_RXD */
+ AM62X_IOPAD(0x0038, PIN_OUTPUT, 5) /* (E24) OSPI0_CSn3.UART5_TXD */ /* WiFi_UART_TXD */
+ >;
+ };
+
+ /* Verdin USB_1 */
+ pinctrl_usb0: main-usb0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0254, PIN_OUTPUT, 0) /* (C20) USB0_DRVVBUS */ /* SODIMM 155 */
+ >;
+ };
+
+ /* Verdin USB_2 */
+ pinctrl_usb1: main-usb1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ /* SODIMM 185 */
+ >;
+ };
+
+ /* DSS VOUT0 RGB */
+ pinctrl_parallel_rgb: main-vout-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
+ AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
+ AM62X_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
+ AM62X_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
+ AM62X_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
+ AM62X_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
+ AM62X_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
+ AM62X_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
+ AM62X_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
+ AM62X_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
+ AM62X_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
+ AM62X_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
+ AM62X_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
+ AM62X_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
+ AM62X_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
+ AM62X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
+ AM62X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
+ AM62X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
+ AM62X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
+ AM62X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
+ AM62X_IOPAD(0x005c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */
+ AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */
+ >;
+ };
+};
+
+&mcu_pmx0 {
+ /* Verdin PCIE_1_RESET# */
+ pinctrl_pcie_1_reset: mcu-gpio0-0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_MCU_IOPAD(0x0000, PIN_INPUT, 7) /* (E8) MCU_SPI0_CS0.MCU_GPIO0_0 */ /* SODIMM 244 */
+ >;
+ };
+
+ /* Verdin GPIO_1 */
+ pinctrl_gpio_1: mcu-gpio0-1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_MCU_IOPAD(0x0004, PIN_INPUT, 7) /* (B8) MCU_SPI0_CS1.MCU_GPIO0_1 */ /* SODIMM 206 */
+ >;
+ };
+
+ /* Verdin GPIO_2 */
+ pinctrl_gpio_2: mcu-gpio0-2-default-pins {
+ pinctrl-single,pins = <
+ AM62X_MCU_IOPAD(0x0008, PIN_INPUT, 7) /* (A7) MCU_SPI0_CLK.MCU_GPIO0_2 */ /* SODIMM 208 */
+ >;
+ };
+
+ /* Verdin GPIO_3 */
+ pinctrl_gpio_3: mcu-gpio0-3-default-pins {
+ pinctrl-single,pins = <
+ AM62X_MCU_IOPAD(0x000c, PIN_INPUT, 7) /* (D9) MCU_SPI0_D0.MCU_GPIO0_3 */ /* SODIMM 210 */
+ >;
+ };
+
+ /* Verdin GPIO_4 */
+ pinctrl_gpio_4: mcu-gpio0-4-default-pins {
+ pinctrl-single,pins = <
+ AM62X_MCU_IOPAD(0x0010, PIN_INPUT, 7) /* (C9) MCU_SPI0_D1.MCU_GPIO0_4 */ /* SODIMM 212 */
+ >;
+ };
+
+ /* Verdin I2C_3_HDMI */
+ pinctrl_mcu_i2c0: mcu-i2c0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */ /* SODIMM 59 */
+ AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ /* SODIMM 57 */
+ >;
+ };
+
+ /* Verdin UART_4 - Reserved to Cortex-M4 */
+ pinctrl_mcu_uart0: mcu-uart0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_MCU_IOPAD(0x0014, PIN_INPUT_PULLUP, 0) /* (B5) MCU_UART0_RXD */ /* SODIMM 151 */
+ AM62X_MCU_IOPAD(0x0018, PIN_OUTPUT, 0) /* (A5) MCU_UART0_TXD */ /* SODIMM 153 */
+ >;
+ };
+
+ /* Verdin CSI_1_MCLK */
+ pinctrl_csi1_mclk: wkup-clkout0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ /* SODIMM 91 */
+ >;
+ };
+
+ /* Verdin UART_2 */
+ pinctrl_wkup_uart0: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_MCU_IOPAD(0x002c, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_UART0_CTSn */ /* SODIMM 143 */
+ AM62X_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ /* SODIMM 141 */
+ AM62X_MCU_IOPAD(0x0024, PIN_INPUT_PULLUP, 0) /* (B4) WKUP_UART0_RXD */ /* SODIMM 137 */
+ AM62X_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ /* SODIMM 139 */
+ >;
+ };
+};
+
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii1>;
+ status = "disabled";
+};
+
+/* Verdin ETH_1 (On-module PHY) */
+&cpsw_port1 {
+ phy-handle = <&cpsw3g_phy0>;
+ phy-mode = "rgmii-rxid";
+ status = "disabled";
+};
+
+/* Verdin ETH_2_RGMII */
+&cpsw_port2 {
+ status = "disabled";
+};
+
+/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
+&cpsw3g_mdio {
+ assigned-clocks = <&k3_clks 157 20>;
+ assigned-clock-parents = <&k3_clks 157 22>;
+ assigned-clock-rates = <25000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eth_clock>, <&pinctrl_mdio>;
+ status = "disabled";
+
+ cpsw3g_phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id2000.a231";
+ reg = <0>;
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eth_int>, <&pinctrl_eth_reset>;
+ reset-gpios = <&main_gpio0 17 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10>;
+ reset-deassert-us = <1000>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ };
+};
+
+/* Verdin PWM_1, PWM_2 */
+&epwm0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_epwm0_a>, <&pinctrl_epwm0_b>;
+ status = "disabled";
+};
+
+/* Verdin PWM_3_DSI */
+&epwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_epwm1_a>;
+ status = "disabled";
+};
+
+&main_gpio0 {
+ gpio-line-names =
+ "SODIMM_52", /* 0 */
+ "",
+ "",
+ "SODIMM_56",
+ "SODIMM_58",
+ "SODIMM_60",
+ "SODIMM_62",
+ "",
+ "",
+ "",
+ "", /* 10 */
+ "SODIMM_54",
+ "SODIMM_64",
+ "",
+ "",
+ "SODIMM_174",
+ "SODIMM_172",
+ "",
+ "",
+ "",
+ "", /* 20 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_76",
+ "SODIMM_21", /* 30 */
+ "SODIMM_256",
+ "SODIMM_252",
+ "",
+ "SODIMM_46",
+ "SODIMM_42",
+ "SODIMM_218",
+ "",
+ "SODIMM_189",
+ "",
+ "SODIMM_216", /* 40 */
+ "SODIMM_220",
+ "SODIMM_222",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 50 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 60 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 70 */
+ "SODIMM_157",
+ "SODIMM_187",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 80 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "";
+
+ verdin_ctrl_sleep_moci: ctrl-sleep-moci-hog {
+ gpio-hog;
+ /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
+ gpios = <31 GPIO_ACTIVE_HIGH>;
+ line-name = "CTRL_SLEEP_MOCI#";
+ output-high;
+ };
+};
+
+&main_gpio1 {
+ gpio-line-names =
+ "", /* 0 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 10 */
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_15",
+ "SODIMM_16",
+ "SODIMM_19",
+ "SODIMM_66",
+ "SODIMM_161",
+ "", /* 20 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 30 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 40 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_17",
+ "", /* 50 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 60 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 70 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 80 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "";
+};
+
+/* On-module I2C - PMIC_I2C */
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ dsi_bridge: dsi@e {
+ compatible = "toshiba,tc358778";
+ reg = <0xe>;
+ assigned-clocks = <&k3_clks 157 20>;
+ assigned-clock-parents = <&k3_clks 157 22>;
+ assigned-clock-rates = <25000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_bridge_reset>;
+ clocks = <&k3_clks 157 20>;
+ clock-names = "refclk";
+ reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>;
+ vddc-supply = <®_1v2_dsi>;
+ vddmipi-supply = <®_1v2_dsi>;
+ vddio-supply = <®_1v8_dsi>;
+
+ dsi_bridge_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ rgb_in: endpoint {
+ data-lines = <18>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ pmic@30 {
+ compatible = "ti,tps65219";
+ reg = <0x30>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic_extint>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+
+ buck1-supply = <®_vsodimm>;
+ buck2-supply = <®_vsodimm>;
+ buck3-supply = <®_vsodimm>;
+ ldo1-supply = <®_3v3>;
+ ldo2-supply = <®_1v8>;
+ ldo3-supply = <®_3v3>;
+ ldo4-supply = <®_3v3>;
+ system-power-controller;
+ ti,power-button;
+
+ regulators {
+ reg_vdd_core: buck1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <850000>;
+ regulator-min-microvolt = <850000>;
+ regulator-name = "+VDD_CORE (PMIC BUCK1)";
+ };
+
+ reg_1v8: buck2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V1.8 (PMIC BUCK2)"; /* On-module and SODIMM 214 */
+ };
+
+ reg_vdd_ddr: buck3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1100000>;
+ regulator-name = "+VDD_DDR (PMIC BUCK3)";
+ };
+
+ reg_sd_3v3_1v8: ldo1 {
+ regulator-allow-bypass;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "+V3.3_1.8_SD (PMIC LDO1)";
+ };
+
+ reg_vddr_core: ldo2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <850000>;
+ regulator-min-microvolt = <850000>;
+ regulator-name = "+VDDR_CORE (PMIC LDO2)";
+ };
+
+ reg_1v8a: ldo3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V1.8A (PMIC LDO3)";
+ };
+
+ reg_eth_2v5: ldo4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <2500000>;
+ regulator-min-microvolt = <2500000>;
+ regulator-name = "+V2.5_ETH (PMIC LDO4)";
+ };
+ };
+ };
+
+ rtc_i2c: rtc@32 {
+ compatible = "epson,rx8130";
+ reg = <0x32>;
+ };
+
+ sensor@48 {
+ compatible = "ti,tmp1075";
+ reg = <0x48>;
+ };
+
+ adc@49 {
+ compatible = "ti,ads1015";
+ reg = <0x49>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Verdin PMIC_I2C (ADC_4 - ADC_3) */
+ channel@0 {
+ reg = <0>;
+ ti,datarate = <4>;
+ ti,gain = <2>;
+ };
+
+ /* Verdin PMIC_I2C (ADC_4 - ADC_1) */
+ channel@1 {
+ reg = <1>;
+ ti,datarate = <4>;
+ ti,gain = <2>;
+ };
+
+ /* Verdin PMIC_I2C (ADC_3 - ADC_1) */
+ channel@2 {
+ reg = <2>;
+ ti,datarate = <4>;
+ ti,gain = <2>;
+ };
+
+ /* Verdin PMIC_I2C (ADC_2 - ADC_1) */
+ channel@3 {
+ reg = <3>;
+ ti,datarate = <4>;
+ ti,gain = <2>;
+ };
+
+ /* Verdin PMIC_I2C ADC_4 */
+ channel@4 {
+ reg = <4>;
+ ti,datarate = <4>;
+ ti,gain = <2>;
+ };
+
+ /* Verdin PMIC_I2C ADC_3 */
+ channel@5 {
+ reg = <5>;
+ ti,datarate = <4>;
+ ti,gain = <2>;
+ };
+
+ /* Verdin PMIC_I2C ADC_2 */
+ channel@6 {
+ reg = <6>;
+ ti,datarate = <4>;
+ ti,gain = <2>;
+ };
+
+ /* Verdin PMIC_I2C ADC_1 */
+ channel@7 {
+ reg = <7>;
+ ti,datarate = <4>;
+ ti,gain = <2>;
+ };
+ };
+
+ eeprom@50 {
+ compatible = "st,24c02", "atmel,24c02";
+ pagesize = <16>;
+ reg = <0x50>;
+ };
+};
+
+/* Verdin I2C_1 */
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "disabled";
+};
+
+/* Verdin I2C_2_DSI */
+&main_i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "disabled";
+};
+
+/* Verdin I2C_4_CSI */
+&main_i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "disabled";
+};
+
+&mailbox0_cluster0 {
+ mbox_m4_0: mbox-m4-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+};
+
+/* Verdin CAN_1 */
+&main_mcan0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcan0>;
+ status = "disabled";
+};
+
+/* Verdin CAN_2 - Reserved to Cortex-M4 */
+
+/* Verdin SPI_1 */
+&main_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ ti,pindir-d0-out-d1-in;
+ status = "disabled";
+};
+
+/* Verdin UART_3, used as the Linux console */
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ status = "disabled";
+};
+
+/* Verdin UART_1 */
+&main_uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "disabled";
+};
+
+/* Verdin I2S_1 */
+&mcasp0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcasp0>;
+ op-mode = <0>; /* I2S mode */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ 0 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ >;
+ tdm-slots = <2>;
+ rx-num-evt = <32>;
+ tx-num-evt = <32>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+};
+
+/* Verdin I2S_2 */
+&mcasp1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcasp1>;
+ op-mode = <0>; /* I2S mode */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ 0 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ >;
+ tdm-slots = <2>;
+ rx-num-evt = <32>;
+ tx-num-evt = <32>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+};
+
+/* Verdin I2C_3_HDMI */
+&mcu_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcu_i2c0>;
+ status = "disabled";
+};
+
+&mcu_gpio0 {
+ gpio-line-names =
+ "SODIMM_244",
+ "SODIMM_206",
+ "SODIMM_208",
+ "SODIMM_210",
+ "SODIMM_212",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "";
+};
+
+/* Verdin UART_4 - Cortex-M4 UART */
+&mcu_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcu_uart0>;
+ status = "disabled";
+};
+
+/* Verdin QSPI_1 */
+&ospi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ospi0>;
+ status = "disabled";
+};
+
+/* On-module eMMC */
+&sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci0>;
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ status = "okay";
+};
+
+/* Verdin SD_1 */
+&sdhci1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1>;
+ disable-wp;
+ ti,driver-strength-ohm = <50>;
+ vmmc-supply = <®_sdhc1_vmmc>;
+ vqmmc-supply = <®_sdhc1_vqmmc>;
+ status = "disabled";
+};
+
+/* Verdin USB_1 */
+&usbss0 {
+ ti,vbus-divider;
+ status = "disabled";
+};
+
+/* TODO: role swich using ID pin */
+&usb0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb0_id>;
+ status = "disabled";
+};
+
+/* Verdin USB_2 */
+&usbss1 {
+ ti,vbus-divider;
+ status = "disabled";
+};
+
+&usb1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ dr_mode = "host";
+ status = "disabled";
+};
+
+/* Verdin UART_2 */
+&wkup_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wkup_uart0>;
+ status = "disabled";
+};
diff --git a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
new file mode 100644
index 0000000..9bad430
--- /dev/null
+++ b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
@@ -0,0 +1,2190 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * This file was generated with the
+ * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.08
+ * Fri Jun 09 2023 08:01:37 GMT+0200 (Central European Summer Time)
+ * DDR Type: LPDDR4
+ * F0 = 50MHz F1 = NA F2 = 800MHz
+ * Density (per channel): 16Gb
+ * Write DBI: Enable
+ * Number of Ranks: 1
+ */
+
+#define DDRSS_PLL_FHS_CNT 3
+#define DDRSS_PLL_FREQUENCY_1 400000000
+#define DDRSS_PLL_FREQUENCY_2 400000000
+
+#define DDRSS_CTL_0_DATA 0x00000B00
+#define DDRSS_CTL_1_DATA 0x00000000
+#define DDRSS_CTL_2_DATA 0x00000000
+#define DDRSS_CTL_3_DATA 0x00000000
+#define DDRSS_CTL_4_DATA 0x00000000
+#define DDRSS_CTL_5_DATA 0x00000000
+#define DDRSS_CTL_6_DATA 0x00000000
+#define DDRSS_CTL_7_DATA 0x00002710
+#define DDRSS_CTL_8_DATA 0x000186A0
+#define DDRSS_CTL_9_DATA 0x00000005
+#define DDRSS_CTL_10_DATA 0x00000064
+#define DDRSS_CTL_11_DATA 0x00027100
+#define DDRSS_CTL_12_DATA 0x00186A00
+#define DDRSS_CTL_13_DATA 0x00000005
+#define DDRSS_CTL_14_DATA 0x00000640
+#define DDRSS_CTL_15_DATA 0x00027100
+#define DDRSS_CTL_16_DATA 0x00186A00
+#define DDRSS_CTL_17_DATA 0x00000005
+#define DDRSS_CTL_18_DATA 0x00000640
+#define DDRSS_CTL_19_DATA 0x01010100
+#define DDRSS_CTL_20_DATA 0x01010100
+#define DDRSS_CTL_21_DATA 0x01000110
+#define DDRSS_CTL_22_DATA 0x02010002
+#define DDRSS_CTL_23_DATA 0x0000000A
+#define DDRSS_CTL_24_DATA 0x000186A0
+#define DDRSS_CTL_25_DATA 0x00000000
+#define DDRSS_CTL_26_DATA 0x00000000
+#define DDRSS_CTL_27_DATA 0x00000000
+#define DDRSS_CTL_28_DATA 0x00000000
+#define DDRSS_CTL_29_DATA 0x00020200
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x08000010
+#define DDRSS_CTL_35_DATA 0x00002020
+#define DDRSS_CTL_36_DATA 0x00000000
+#define DDRSS_CTL_37_DATA 0x00000000
+#define DDRSS_CTL_38_DATA 0x0000040C
+#define DDRSS_CTL_39_DATA 0x00000000
+#define DDRSS_CTL_40_DATA 0x0000081C
+#define DDRSS_CTL_41_DATA 0x00000000
+#define DDRSS_CTL_42_DATA 0x0000081C
+#define DDRSS_CTL_43_DATA 0x00000000
+#define DDRSS_CTL_44_DATA 0x05000804
+#define DDRSS_CTL_45_DATA 0x00000B00
+#define DDRSS_CTL_46_DATA 0x09090004
+#define DDRSS_CTL_47_DATA 0x00000204
+#define DDRSS_CTL_48_DATA 0x00370008
+#define DDRSS_CTL_49_DATA 0x09090024
+#define DDRSS_CTL_50_DATA 0x00001910
+#define DDRSS_CTL_51_DATA 0x00370008
+#define DDRSS_CTL_52_DATA 0x09090024
+#define DDRSS_CTL_53_DATA 0x09001910
+#define DDRSS_CTL_54_DATA 0x000A0A09
+#define DDRSS_CTL_55_DATA 0x0400036D
+#define DDRSS_CTL_56_DATA 0x09092004
+#define DDRSS_CTL_57_DATA 0x00000C0A
+#define DDRSS_CTL_58_DATA 0x060036D8
+#define DDRSS_CTL_59_DATA 0x09092006
+#define DDRSS_CTL_60_DATA 0x00000C0A
+#define DDRSS_CTL_61_DATA 0x060036D8
+#define DDRSS_CTL_62_DATA 0x03042006
+#define DDRSS_CTL_63_DATA 0x06050002
+#define DDRSS_CTL_64_DATA 0x10111011
+#define DDRSS_CTL_65_DATA 0x01010008
+#define DDRSS_CTL_66_DATA 0x0420200A
+#define DDRSS_CTL_67_DATA 0x04131304
+#define DDRSS_CTL_68_DATA 0x00001313
+#define DDRSS_CTL_69_DATA 0x00000101
+#define DDRSS_CTL_70_DATA 0x00000000
+#define DDRSS_CTL_71_DATA 0x01000000
+#define DDRSS_CTL_72_DATA 0x00130803
+#define DDRSS_CTL_73_DATA 0x00000059
+#define DDRSS_CTL_74_DATA 0x00000130
+#define DDRSS_CTL_75_DATA 0x00000610
+#define DDRSS_CTL_76_DATA 0x00000130
+#define DDRSS_CTL_77_DATA 0x00000610
+#define DDRSS_CTL_78_DATA 0x00000005
+#define DDRSS_CTL_79_DATA 0x0000000A
+#define DDRSS_CTL_80_DATA 0x00000004
+#define DDRSS_CTL_81_DATA 0x00000098
+#define DDRSS_CTL_82_DATA 0x000000BB
+#define DDRSS_CTL_83_DATA 0x00000098
+#define DDRSS_CTL_84_DATA 0x000000BB
+#define DDRSS_CTL_85_DATA 0x03004000
+#define DDRSS_CTL_86_DATA 0x00001201
+#define DDRSS_CTL_87_DATA 0x00060005
+#define DDRSS_CTL_88_DATA 0x00000006
+#define DDRSS_CTL_89_DATA 0x00000000
+#define DDRSS_CTL_90_DATA 0x05141408
+#define DDRSS_CTL_91_DATA 0x05030A05
+#define DDRSS_CTL_92_DATA 0x05030C06
+#define DDRSS_CTL_93_DATA 0x01030C06
+#define DDRSS_CTL_94_DATA 0x02010201
+#define DDRSS_CTL_95_DATA 0x00001401
+#define DDRSS_CTL_96_DATA 0x01360014
+#define DDRSS_CTL_97_DATA 0x01360136
+#define DDRSS_CTL_98_DATA 0x00000136
+#define DDRSS_CTL_99_DATA 0x00000000
+#define DDRSS_CTL_100_DATA 0x05010303
+#define DDRSS_CTL_101_DATA 0x0C040505
+#define DDRSS_CTL_102_DATA 0x06050203
+#define DDRSS_CTL_103_DATA 0x030C0605
+#define DDRSS_CTL_104_DATA 0x05060502
+#define DDRSS_CTL_105_DATA 0x03030306
+#define DDRSS_CTL_106_DATA 0x03010000
+#define DDRSS_CTL_107_DATA 0x00010000
+#define DDRSS_CTL_108_DATA 0x00000000
+#define DDRSS_CTL_109_DATA 0x01000000
+#define DDRSS_CTL_110_DATA 0x80104002
+#define DDRSS_CTL_111_DATA 0x00040003
+#define DDRSS_CTL_112_DATA 0x00040005
+#define DDRSS_CTL_113_DATA 0x00030000
+#define DDRSS_CTL_114_DATA 0x00050004
+#define DDRSS_CTL_115_DATA 0x00000004
+#define DDRSS_CTL_116_DATA 0x00040003
+#define DDRSS_CTL_117_DATA 0x00040005
+#define DDRSS_CTL_118_DATA 0x00000000
+#define DDRSS_CTL_119_DATA 0x00001640
+#define DDRSS_CTL_120_DATA 0x00001640
+#define DDRSS_CTL_121_DATA 0x00001640
+#define DDRSS_CTL_122_DATA 0x00001640
+#define DDRSS_CTL_123_DATA 0x00001640
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x0000026F
+#define DDRSS_CTL_126_DATA 0x00018400
+#define DDRSS_CTL_127_DATA 0x00018400
+#define DDRSS_CTL_128_DATA 0x00018400
+#define DDRSS_CTL_129_DATA 0x00018400
+#define DDRSS_CTL_130_DATA 0x00018400
+#define DDRSS_CTL_131_DATA 0x00000000
+#define DDRSS_CTL_132_DATA 0x00002A70
+#define DDRSS_CTL_133_DATA 0x00018400
+#define DDRSS_CTL_134_DATA 0x00018400
+#define DDRSS_CTL_135_DATA 0x00018400
+#define DDRSS_CTL_136_DATA 0x00018400
+#define DDRSS_CTL_137_DATA 0x00018400
+#define DDRSS_CTL_138_DATA 0x00000000
+#define DDRSS_CTL_139_DATA 0x00002A70
+#define DDRSS_CTL_140_DATA 0x00000000
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x00000000
+#define DDRSS_CTL_149_DATA 0x00000000
+#define DDRSS_CTL_150_DATA 0x00000000
+#define DDRSS_CTL_151_DATA 0x00000000
+#define DDRSS_CTL_152_DATA 0x00000000
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00000000
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x03050000
+#define DDRSS_CTL_157_DATA 0x03050305
+#define DDRSS_CTL_158_DATA 0x00000000
+#define DDRSS_CTL_159_DATA 0x08010000
+#define DDRSS_CTL_160_DATA 0x000E0808
+#define DDRSS_CTL_161_DATA 0x01000000
+#define DDRSS_CTL_162_DATA 0x0E080808
+#define DDRSS_CTL_163_DATA 0x00000000
+#define DDRSS_CTL_164_DATA 0x08080801
+#define DDRSS_CTL_165_DATA 0x0000080E
+#define DDRSS_CTL_166_DATA 0x00040003
+#define DDRSS_CTL_167_DATA 0x00000007
+#define DDRSS_CTL_168_DATA 0x00000000
+#define DDRSS_CTL_169_DATA 0x00000000
+#define DDRSS_CTL_170_DATA 0x00000000
+#define DDRSS_CTL_171_DATA 0x00000000
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x01000000
+#define DDRSS_CTL_175_DATA 0x00000000
+#define DDRSS_CTL_176_DATA 0x00001500
+#define DDRSS_CTL_177_DATA 0x0000100E
+#define DDRSS_CTL_178_DATA 0x00000002
+#define DDRSS_CTL_179_DATA 0x00000000
+#define DDRSS_CTL_180_DATA 0x00000001
+#define DDRSS_CTL_181_DATA 0x00000002
+#define DDRSS_CTL_182_DATA 0x00000C00
+#define DDRSS_CTL_183_DATA 0x00001000
+#define DDRSS_CTL_184_DATA 0x00000C00
+#define DDRSS_CTL_185_DATA 0x00001000
+#define DDRSS_CTL_186_DATA 0x00000C00
+#define DDRSS_CTL_187_DATA 0x00001000
+#define DDRSS_CTL_188_DATA 0x00000000
+#define DDRSS_CTL_189_DATA 0x00000000
+#define DDRSS_CTL_190_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x0005000A
+#define DDRSS_CTL_193_DATA 0x0404000D
+#define DDRSS_CTL_194_DATA 0x0000000D
+#define DDRSS_CTL_195_DATA 0x005000A0
+#define DDRSS_CTL_196_DATA 0x060600C8
+#define DDRSS_CTL_197_DATA 0x000000C8
+#define DDRSS_CTL_198_DATA 0x005000A0
+#define DDRSS_CTL_199_DATA 0x060600C8
+#define DDRSS_CTL_200_DATA 0x000000C8
+#define DDRSS_CTL_201_DATA 0x00000000
+#define DDRSS_CTL_202_DATA 0x00000000
+#define DDRSS_CTL_203_DATA 0x00000000
+#define DDRSS_CTL_204_DATA 0x00000000
+#define DDRSS_CTL_205_DATA 0x00000004
+#define DDRSS_CTL_206_DATA 0x00000000
+#define DDRSS_CTL_207_DATA 0x00000000
+#define DDRSS_CTL_208_DATA 0x00000024
+#define DDRSS_CTL_209_DATA 0x00000012
+#define DDRSS_CTL_210_DATA 0x00000000
+#define DDRSS_CTL_211_DATA 0x00000024
+#define DDRSS_CTL_212_DATA 0x00000012
+#define DDRSS_CTL_213_DATA 0x00000000
+#define DDRSS_CTL_214_DATA 0x00000004
+#define DDRSS_CTL_215_DATA 0x00000000
+#define DDRSS_CTL_216_DATA 0x00000000
+#define DDRSS_CTL_217_DATA 0x00000024
+#define DDRSS_CTL_218_DATA 0x00000012
+#define DDRSS_CTL_219_DATA 0x00000000
+#define DDRSS_CTL_220_DATA 0x00000024
+#define DDRSS_CTL_221_DATA 0x00000012
+#define DDRSS_CTL_222_DATA 0x00000000
+#define DDRSS_CTL_223_DATA 0x00000000
+#define DDRSS_CTL_224_DATA 0x00000031
+#define DDRSS_CTL_225_DATA 0x000000B1
+#define DDRSS_CTL_226_DATA 0x000000B1
+#define DDRSS_CTL_227_DATA 0x00000031
+#define DDRSS_CTL_228_DATA 0x000000B1
+#define DDRSS_CTL_229_DATA 0x000000B1
+#define DDRSS_CTL_230_DATA 0x00000000
+#define DDRSS_CTL_231_DATA 0x00000000
+#define DDRSS_CTL_232_DATA 0x00000000
+#define DDRSS_CTL_233_DATA 0x00000000
+#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00000000
+#define DDRSS_CTL_237_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0x00000000
+#define DDRSS_CTL_239_DATA 0x00000000
+#define DDRSS_CTL_240_DATA 0x00000000
+#define DDRSS_CTL_241_DATA 0x00000000
+#define DDRSS_CTL_242_DATA 0x00000000
+#define DDRSS_CTL_243_DATA 0x00000000
+#define DDRSS_CTL_244_DATA 0x00000000
+#define DDRSS_CTL_245_DATA 0x00000000
+#define DDRSS_CTL_246_DATA 0x00000000
+#define DDRSS_CTL_247_DATA 0x00000000
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x46004646
+#define DDRSS_CTL_255_DATA 0x00002746
+#define DDRSS_CTL_256_DATA 0x00000027
+#define DDRSS_CTL_257_DATA 0x00000027
+#define DDRSS_CTL_258_DATA 0x00000027
+#define DDRSS_CTL_259_DATA 0x00000027
+#define DDRSS_CTL_260_DATA 0x00000027
+#define DDRSS_CTL_261_DATA 0x00000000
+#define DDRSS_CTL_262_DATA 0x00000000
+#define DDRSS_CTL_263_DATA 0x0000000F
+#define DDRSS_CTL_264_DATA 0x0000000F
+#define DDRSS_CTL_265_DATA 0x0000000F
+#define DDRSS_CTL_266_DATA 0x0000000F
+#define DDRSS_CTL_267_DATA 0x0000000F
+#define DDRSS_CTL_268_DATA 0x0000000F
+#define DDRSS_CTL_269_DATA 0x00000000
+#define DDRSS_CTL_270_DATA 0x00001000
+#define DDRSS_CTL_271_DATA 0x00000015
+#define DDRSS_CTL_272_DATA 0x00000015
+#define DDRSS_CTL_273_DATA 0x00000010
+#define DDRSS_CTL_274_DATA 0x00000015
+#define DDRSS_CTL_275_DATA 0x00000015
+#define DDRSS_CTL_276_DATA 0x00000020
+#define DDRSS_CTL_277_DATA 0x00010000
+#define DDRSS_CTL_278_DATA 0x00000100
+#define DDRSS_CTL_279_DATA 0x00000000
+#define DDRSS_CTL_280_DATA 0x00000000
+#define DDRSS_CTL_281_DATA 0x00000101
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000000
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00000000
+#define DDRSS_CTL_287_DATA 0x00000000
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x0C181511
+#define DDRSS_CTL_291_DATA 0x00000304
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x00000000
+#define DDRSS_CTL_297_DATA 0x00000000
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00020000
+#define DDRSS_CTL_306_DATA 0x00400100
+#define DDRSS_CTL_307_DATA 0x00080032
+#define DDRSS_CTL_308_DATA 0x01000200
+#define DDRSS_CTL_309_DATA 0x03200040
+#define DDRSS_CTL_310_DATA 0x00020018
+#define DDRSS_CTL_311_DATA 0x00400100
+#define DDRSS_CTL_312_DATA 0x00180320
+#define DDRSS_CTL_313_DATA 0x00030000
+#define DDRSS_CTL_314_DATA 0x00280028
+#define DDRSS_CTL_315_DATA 0x00000100
+#define DDRSS_CTL_316_DATA 0x01010000
+#define DDRSS_CTL_317_DATA 0x00000000
+#define DDRSS_CTL_318_DATA 0x3FFF0000
+#define DDRSS_CTL_319_DATA 0x000FFF00
+#define DDRSS_CTL_320_DATA 0xFFFFFFFF
+#define DDRSS_CTL_321_DATA 0x00FFFF00
+#define DDRSS_CTL_322_DATA 0x0B000000
+#define DDRSS_CTL_323_DATA 0x0001FFFF
+#define DDRSS_CTL_324_DATA 0x01010101
+#define DDRSS_CTL_325_DATA 0x01010101
+#define DDRSS_CTL_326_DATA 0x00000118
+#define DDRSS_CTL_327_DATA 0x00000C01
+#define DDRSS_CTL_328_DATA 0x01000100
+#define DDRSS_CTL_329_DATA 0x00000000
+#define DDRSS_CTL_330_DATA 0x00000000
+#define DDRSS_CTL_331_DATA 0x01030303
+#define DDRSS_CTL_332_DATA 0x00000001
+#define DDRSS_CTL_333_DATA 0x00000000
+#define DDRSS_CTL_334_DATA 0x00000000
+#define DDRSS_CTL_335_DATA 0x00000000
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x00000000
+#define DDRSS_CTL_339_DATA 0x00000000
+#define DDRSS_CTL_340_DATA 0x00000000
+#define DDRSS_CTL_341_DATA 0x00000000
+#define DDRSS_CTL_342_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x00000000
+#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_362_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_364_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00000000
+#define DDRSS_CTL_366_DATA 0x00000000
+#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_368_DATA 0x00000000
+#define DDRSS_CTL_369_DATA 0x00000000
+#define DDRSS_CTL_370_DATA 0x00000000
+#define DDRSS_CTL_371_DATA 0x01000101
+#define DDRSS_CTL_372_DATA 0x01010001
+#define DDRSS_CTL_373_DATA 0x00010101
+#define DDRSS_CTL_374_DATA 0x01050503
+#define DDRSS_CTL_375_DATA 0x05020201
+#define DDRSS_CTL_376_DATA 0x08080C0C
+#define DDRSS_CTL_377_DATA 0x00080308
+#define DDRSS_CTL_378_DATA 0x000B030E
+#define DDRSS_CTL_379_DATA 0x000B0310
+#define DDRSS_CTL_380_DATA 0x0B0B0810
+#define DDRSS_CTL_381_DATA 0x01000000
+#define DDRSS_CTL_382_DATA 0x03020301
+#define DDRSS_CTL_383_DATA 0x04000102
+#define DDRSS_CTL_384_DATA 0x1B000004
+#define DDRSS_CTL_385_DATA 0x000000B2
+#define DDRSS_CTL_386_DATA 0x00000200
+#define DDRSS_CTL_387_DATA 0x00000200
+#define DDRSS_CTL_388_DATA 0x00000200
+#define DDRSS_CTL_389_DATA 0x00000200
+#define DDRSS_CTL_390_DATA 0x00000321
+#define DDRSS_CTL_391_DATA 0x000006F4
+#define DDRSS_CTL_392_DATA 0x03050202
+#define DDRSS_CTL_393_DATA 0x00260201
+#define DDRSS_CTL_394_DATA 0x00000C20
+#define DDRSS_CTL_395_DATA 0x00000200
+#define DDRSS_CTL_396_DATA 0x00000200
+#define DDRSS_CTL_397_DATA 0x00000200
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x00003690
+#define DDRSS_CTL_400_DATA 0x00007940
+#define DDRSS_CTL_401_DATA 0x070D0402
+#define DDRSS_CTL_402_DATA 0x00260405
+#define DDRSS_CTL_403_DATA 0x00000C20
+#define DDRSS_CTL_404_DATA 0x00000200
+#define DDRSS_CTL_405_DATA 0x00000200
+#define DDRSS_CTL_406_DATA 0x00000200
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x00003690
+#define DDRSS_CTL_409_DATA 0x00007940
+#define DDRSS_CTL_410_DATA 0x070D0402
+#define DDRSS_CTL_411_DATA 0x00000405
+#define DDRSS_CTL_412_DATA 0x00000000
+#define DDRSS_CTL_413_DATA 0x0302000A
+#define DDRSS_CTL_414_DATA 0x01000500
+#define DDRSS_CTL_415_DATA 0x01010001
+#define DDRSS_CTL_416_DATA 0x00010001
+#define DDRSS_CTL_417_DATA 0x01010001
+#define DDRSS_CTL_418_DATA 0x02010000
+#define DDRSS_CTL_419_DATA 0x00000200
+#define DDRSS_CTL_420_DATA 0x02000201
+#define DDRSS_CTL_421_DATA 0x10100600
+#define DDRSS_CTL_422_DATA 0x00202020
+#define DDRSS_PI_0_DATA 0x00000B00
+#define DDRSS_PI_1_DATA 0x00000000
+#define DDRSS_PI_2_DATA 0x00000000
+#define DDRSS_PI_3_DATA 0x01000000
+#define DDRSS_PI_4_DATA 0x00000001
+#define DDRSS_PI_5_DATA 0x00010064
+#define DDRSS_PI_6_DATA 0x00000000
+#define DDRSS_PI_7_DATA 0x00000000
+#define DDRSS_PI_8_DATA 0x00000000
+#define DDRSS_PI_9_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000002
+#define DDRSS_PI_12_DATA 0x00000005
+#define DDRSS_PI_13_DATA 0x00010001
+#define DDRSS_PI_14_DATA 0x08000000
+#define DDRSS_PI_15_DATA 0x00010300
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00010000
+#define DDRSS_PI_24_DATA 0x280A0001
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x00010000
+#define DDRSS_PI_27_DATA 0x00003200
+#define DDRSS_PI_28_DATA 0x00000000
+#define DDRSS_PI_29_DATA 0x00000000
+#define DDRSS_PI_30_DATA 0x01010102
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x00000000
+#define DDRSS_PI_34_DATA 0x00000001
+#define DDRSS_PI_35_DATA 0x000000AA
+#define DDRSS_PI_36_DATA 0x00000055
+#define DDRSS_PI_37_DATA 0x000000B5
+#define DDRSS_PI_38_DATA 0x0000004A
+#define DDRSS_PI_39_DATA 0x00000056
+#define DDRSS_PI_40_DATA 0x000000A9
+#define DDRSS_PI_41_DATA 0x000000A9
+#define DDRSS_PI_42_DATA 0x000000B5
+#define DDRSS_PI_43_DATA 0x00000000
+#define DDRSS_PI_44_DATA 0x00000000
+#define DDRSS_PI_45_DATA 0x00010100
+#define DDRSS_PI_46_DATA 0x00000015
+#define DDRSS_PI_47_DATA 0x000007D0
+#define DDRSS_PI_48_DATA 0x00000300
+#define DDRSS_PI_49_DATA 0x00000000
+#define DDRSS_PI_50_DATA 0x00000000
+#define DDRSS_PI_51_DATA 0x01000000
+#define DDRSS_PI_52_DATA 0x00010101
+#define DDRSS_PI_53_DATA 0x01000000
+#define DDRSS_PI_54_DATA 0x03000000
+#define DDRSS_PI_55_DATA 0x00000000
+#define DDRSS_PI_56_DATA 0x00001701
+#define DDRSS_PI_57_DATA 0x00000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x00000000
+#define DDRSS_PI_60_DATA 0x0A0A140A
+#define DDRSS_PI_61_DATA 0x10020101
+#define DDRSS_PI_62_DATA 0x01000210
+#define DDRSS_PI_63_DATA 0x05000404
+#define DDRSS_PI_64_DATA 0x00010001
+#define DDRSS_PI_65_DATA 0x0001000E
+#define DDRSS_PI_66_DATA 0x01010100
+#define DDRSS_PI_67_DATA 0x00010000
+#define DDRSS_PI_68_DATA 0x00000034
+#define DDRSS_PI_69_DATA 0x00000000
+#define DDRSS_PI_70_DATA 0x00000000
+#define DDRSS_PI_71_DATA 0x0000FFFF
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00000000
+#define DDRSS_PI_74_DATA 0x00000000
+#define DDRSS_PI_75_DATA 0x00000000
+#define DDRSS_PI_76_DATA 0x01000000
+#define DDRSS_PI_77_DATA 0x08000100
+#define DDRSS_PI_78_DATA 0x00020000
+#define DDRSS_PI_79_DATA 0x00010002
+#define DDRSS_PI_80_DATA 0x00000001
+#define DDRSS_PI_81_DATA 0x00020001
+#define DDRSS_PI_82_DATA 0x00020002
+#define DDRSS_PI_83_DATA 0x00000000
+#define DDRSS_PI_84_DATA 0x00000000
+#define DDRSS_PI_85_DATA 0x00000000
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000400
+#define DDRSS_PI_92_DATA 0x0A090B0C
+#define DDRSS_PI_93_DATA 0x04060708
+#define DDRSS_PI_94_DATA 0x01000005
+#define DDRSS_PI_95_DATA 0x00000800
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x00010008
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x0000AA00
+#define DDRSS_PI_100_DATA 0x00000000
+#define DDRSS_PI_101_DATA 0x00010000
+#define DDRSS_PI_102_DATA 0x00000000
+#define DDRSS_PI_103_DATA 0x00000000
+#define DDRSS_PI_104_DATA 0x00000000
+#define DDRSS_PI_105_DATA 0x00000000
+#define DDRSS_PI_106_DATA 0x00000000
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x00000000
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00000000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000008
+#define DDRSS_PI_125_DATA 0x00000000
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00010000
+#define DDRSS_PI_134_DATA 0x00000000
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x0000000A
+#define DDRSS_PI_137_DATA 0x000186A0
+#define DDRSS_PI_138_DATA 0x00000100
+#define DDRSS_PI_139_DATA 0x00000000
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x01000000
+#define DDRSS_PI_145_DATA 0x00010003
+#define DDRSS_PI_146_DATA 0x02000101
+#define DDRSS_PI_147_DATA 0x01030001
+#define DDRSS_PI_148_DATA 0x00010400
+#define DDRSS_PI_149_DATA 0x06000105
+#define DDRSS_PI_150_DATA 0x01070001
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00010001
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x00000000
+#define DDRSS_PI_157_DATA 0x00000000
+#define DDRSS_PI_158_DATA 0x00000000
+#define DDRSS_PI_159_DATA 0x00010000
+#define DDRSS_PI_160_DATA 0x00000004
+#define DDRSS_PI_161_DATA 0x00000000
+#define DDRSS_PI_162_DATA 0x00000000
+#define DDRSS_PI_163_DATA 0x00000000
+#define DDRSS_PI_164_DATA 0x00000800
+#define DDRSS_PI_165_DATA 0x00780078
+#define DDRSS_PI_166_DATA 0x00101001
+#define DDRSS_PI_167_DATA 0x00000034
+#define DDRSS_PI_168_DATA 0x00000043
+#define DDRSS_PI_169_DATA 0x00020043
+#define DDRSS_PI_170_DATA 0x02000200
+#define DDRSS_PI_171_DATA 0x00000004
+#define DDRSS_PI_172_DATA 0x0000080C
+#define DDRSS_PI_173_DATA 0x00081C00
+#define DDRSS_PI_174_DATA 0x001C0000
+#define DDRSS_PI_175_DATA 0x00000013
+#define DDRSS_PI_176_DATA 0x00000059
+#define DDRSS_PI_177_DATA 0x00000130
+#define DDRSS_PI_178_DATA 0x00000610
+#define DDRSS_PI_179_DATA 0x00000130
+#define DDRSS_PI_180_DATA 0x04000610
+#define DDRSS_PI_181_DATA 0x01010404
+#define DDRSS_PI_182_DATA 0x00001501
+#define DDRSS_PI_183_DATA 0x001D001D
+#define DDRSS_PI_184_DATA 0x01000100
+#define DDRSS_PI_185_DATA 0x00000100
+#define DDRSS_PI_186_DATA 0x00000000
+#define DDRSS_PI_187_DATA 0x05050503
+#define DDRSS_PI_188_DATA 0x01010C0C
+#define DDRSS_PI_189_DATA 0x01010101
+#define DDRSS_PI_190_DATA 0x000C0C0A
+#define DDRSS_PI_191_DATA 0x00000000
+#define DDRSS_PI_192_DATA 0x00000000
+#define DDRSS_PI_193_DATA 0x04000000
+#define DDRSS_PI_194_DATA 0x04020808
+#define DDRSS_PI_195_DATA 0x04040204
+#define DDRSS_PI_196_DATA 0x00090031
+#define DDRSS_PI_197_DATA 0x00110039
+#define DDRSS_PI_198_DATA 0x00110039
+#define DDRSS_PI_199_DATA 0x01010101
+#define DDRSS_PI_200_DATA 0x0002000D
+#define DDRSS_PI_201_DATA 0x000200C8
+#define DDRSS_PI_202_DATA 0x010000C8
+#define DDRSS_PI_203_DATA 0x000E000E
+#define DDRSS_PI_204_DATA 0x00C90100
+#define DDRSS_PI_205_DATA 0x010000C9
+#define DDRSS_PI_206_DATA 0x00C900C9
+#define DDRSS_PI_207_DATA 0x32103200
+#define DDRSS_PI_208_DATA 0x01013210
+#define DDRSS_PI_209_DATA 0x0A070601
+#define DDRSS_PI_210_DATA 0x0D09070D
+#define DDRSS_PI_211_DATA 0x0D09070D
+#define DDRSS_PI_212_DATA 0x000C000D
+#define DDRSS_PI_213_DATA 0x00001000
+#define DDRSS_PI_214_DATA 0x00000C00
+#define DDRSS_PI_215_DATA 0x00001000
+#define DDRSS_PI_216_DATA 0x00000C00
+#define DDRSS_PI_217_DATA 0x02001000
+#define DDRSS_PI_218_DATA 0x0016000D
+#define DDRSS_PI_219_DATA 0x001600C8
+#define DDRSS_PI_220_DATA 0x000000C8
+#define DDRSS_PI_221_DATA 0x00001900
+#define DDRSS_PI_222_DATA 0x32000056
+#define DDRSS_PI_223_DATA 0x06000101
+#define DDRSS_PI_224_DATA 0x001D0204
+#define DDRSS_PI_225_DATA 0x32120058
+#define DDRSS_PI_226_DATA 0x05000101
+#define DDRSS_PI_227_DATA 0x001D0408
+#define DDRSS_PI_228_DATA 0x32120058
+#define DDRSS_PI_229_DATA 0x05000101
+#define DDRSS_PI_230_DATA 0x00000408
+#define DDRSS_PI_231_DATA 0x05040900
+#define DDRSS_PI_232_DATA 0x00060900
+#define DDRSS_PI_233_DATA 0x00000315
+#define DDRSS_PI_234_DATA 0x20010004
+#define DDRSS_PI_235_DATA 0x0A0A0A03
+#define DDRSS_PI_236_DATA 0x13090000
+#define DDRSS_PI_237_DATA 0x10090011
+#define DDRSS_PI_238_DATA 0x0000315C
+#define DDRSS_PI_239_DATA 0x20030024
+#define DDRSS_PI_240_DATA 0x0C0A0C0C
+#define DDRSS_PI_241_DATA 0x13090000
+#define DDRSS_PI_242_DATA 0x10090011
+#define DDRSS_PI_243_DATA 0x0000315C
+#define DDRSS_PI_244_DATA 0x20030024
+#define DDRSS_PI_245_DATA 0x0C0A0C0C
+#define DDRSS_PI_246_DATA 0x00000000
+#define DDRSS_PI_247_DATA 0x000000B2
+#define DDRSS_PI_248_DATA 0x000006F4
+#define DDRSS_PI_249_DATA 0x00000C20
+#define DDRSS_PI_250_DATA 0x00007940
+#define DDRSS_PI_251_DATA 0x00000C20
+#define DDRSS_PI_252_DATA 0x00007940
+#define DDRSS_PI_253_DATA 0x01360014
+#define DDRSS_PI_254_DATA 0x03030136
+#define DDRSS_PI_255_DATA 0x00000003
+#define DDRSS_PI_256_DATA 0x00000000
+#define DDRSS_PI_257_DATA 0x05030503
+#define DDRSS_PI_258_DATA 0x00000503
+#define DDRSS_PI_259_DATA 0x00002710
+#define DDRSS_PI_260_DATA 0x000186A0
+#define DDRSS_PI_261_DATA 0x00000005
+#define DDRSS_PI_262_DATA 0x00000064
+#define DDRSS_PI_263_DATA 0x00000014
+#define DDRSS_PI_264_DATA 0x00027100
+#define DDRSS_PI_265_DATA 0x000186A0
+#define DDRSS_PI_266_DATA 0x00000005
+#define DDRSS_PI_267_DATA 0x00000640
+#define DDRSS_PI_268_DATA 0x00000136
+#define DDRSS_PI_269_DATA 0x00027100
+#define DDRSS_PI_270_DATA 0x000186A0
+#define DDRSS_PI_271_DATA 0x00000005
+#define DDRSS_PI_272_DATA 0x00000640
+#define DDRSS_PI_273_DATA 0x01000136
+#define DDRSS_PI_274_DATA 0x00320040
+#define DDRSS_PI_275_DATA 0x00010008
+#define DDRSS_PI_276_DATA 0x03200040
+#define DDRSS_PI_277_DATA 0x00010018
+#define DDRSS_PI_278_DATA 0x03200040
+#define DDRSS_PI_279_DATA 0x00000318
+#define DDRSS_PI_280_DATA 0x00280028
+#define DDRSS_PI_281_DATA 0x03040404
+#define DDRSS_PI_282_DATA 0x00000303
+#define DDRSS_PI_283_DATA 0x02020101
+#define DDRSS_PI_284_DATA 0x67676767
+#define DDRSS_PI_285_DATA 0x00000000
+#define DDRSS_PI_286_DATA 0x55000000
+#define DDRSS_PI_287_DATA 0x00000000
+#define DDRSS_PI_288_DATA 0x3C00005A
+#define DDRSS_PI_289_DATA 0x00005500
+#define DDRSS_PI_290_DATA 0x00005A00
+#define DDRSS_PI_291_DATA 0x0D100F3C
+#define DDRSS_PI_292_DATA 0x0003020E
+#define DDRSS_PI_293_DATA 0x00000001
+#define DDRSS_PI_294_DATA 0x01000000
+#define DDRSS_PI_295_DATA 0x00020201
+#define DDRSS_PI_296_DATA 0x00000000
+#define DDRSS_PI_297_DATA 0x00000000
+#define DDRSS_PI_298_DATA 0x00000004
+#define DDRSS_PI_299_DATA 0x00000000
+#define DDRSS_PI_300_DATA 0x00000031
+#define DDRSS_PI_301_DATA 0x00000000
+#define DDRSS_PI_302_DATA 0x00000000
+#define DDRSS_PI_303_DATA 0x00000000
+#define DDRSS_PI_304_DATA 0x00100F27
+#define DDRSS_PI_305_DATA 0x00000000
+#define DDRSS_PI_306_DATA 0x00000024
+#define DDRSS_PI_307_DATA 0x00000012
+#define DDRSS_PI_308_DATA 0x000000B1
+#define DDRSS_PI_309_DATA 0x00000000
+#define DDRSS_PI_310_DATA 0x00000000
+#define DDRSS_PI_311_DATA 0x46000000
+#define DDRSS_PI_312_DATA 0x00150F27
+#define DDRSS_PI_313_DATA 0x00000000
+#define DDRSS_PI_314_DATA 0x00000024
+#define DDRSS_PI_315_DATA 0x00000012
+#define DDRSS_PI_316_DATA 0x000000B1
+#define DDRSS_PI_317_DATA 0x00000000
+#define DDRSS_PI_318_DATA 0x00000000
+#define DDRSS_PI_319_DATA 0x46000000
+#define DDRSS_PI_320_DATA 0x00150F27
+#define DDRSS_PI_321_DATA 0x00000000
+#define DDRSS_PI_322_DATA 0x00000004
+#define DDRSS_PI_323_DATA 0x00000000
+#define DDRSS_PI_324_DATA 0x00000031
+#define DDRSS_PI_325_DATA 0x00000000
+#define DDRSS_PI_326_DATA 0x00000000
+#define DDRSS_PI_327_DATA 0x00000000
+#define DDRSS_PI_328_DATA 0x00100F27
+#define DDRSS_PI_329_DATA 0x00000000
+#define DDRSS_PI_330_DATA 0x00000024
+#define DDRSS_PI_331_DATA 0x00000012
+#define DDRSS_PI_332_DATA 0x000000B1
+#define DDRSS_PI_333_DATA 0x00000000
+#define DDRSS_PI_334_DATA 0x00000000
+#define DDRSS_PI_335_DATA 0x46000000
+#define DDRSS_PI_336_DATA 0x00150F27
+#define DDRSS_PI_337_DATA 0x00000000
+#define DDRSS_PI_338_DATA 0x00000024
+#define DDRSS_PI_339_DATA 0x00000012
+#define DDRSS_PI_340_DATA 0x000000B1
+#define DDRSS_PI_341_DATA 0x00000000
+#define DDRSS_PI_342_DATA 0x00000000
+#define DDRSS_PI_343_DATA 0x46000000
+#define DDRSS_PI_344_DATA 0x00150F27
+#define DDRSS_PHY_0_DATA 0x04F00000
+#define DDRSS_PHY_1_DATA 0x00000000
+#define DDRSS_PHY_2_DATA 0x00030200
+#define DDRSS_PHY_3_DATA 0x00000000
+#define DDRSS_PHY_4_DATA 0x00000000
+#define DDRSS_PHY_5_DATA 0x01000000
+#define DDRSS_PHY_6_DATA 0x03000400
+#define DDRSS_PHY_7_DATA 0x00000001
+#define DDRSS_PHY_8_DATA 0x00000001
+#define DDRSS_PHY_9_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x01010000
+#define DDRSS_PHY_12_DATA 0x00010000
+#define DDRSS_PHY_13_DATA 0x00C00001
+#define DDRSS_PHY_14_DATA 0x00CC0008
+#define DDRSS_PHY_15_DATA 0x00660601
+#define DDRSS_PHY_16_DATA 0x00000003
+#define DDRSS_PHY_17_DATA 0x00000000
+#define DDRSS_PHY_18_DATA 0x00000000
+#define DDRSS_PHY_19_DATA 0x0000AAAA
+#define DDRSS_PHY_20_DATA 0x00005555
+#define DDRSS_PHY_21_DATA 0x0000B5B5
+#define DDRSS_PHY_22_DATA 0x00004A4A
+#define DDRSS_PHY_23_DATA 0x00005656
+#define DDRSS_PHY_24_DATA 0x0000A9A9
+#define DDRSS_PHY_25_DATA 0x0000B7B7
+#define DDRSS_PHY_26_DATA 0x00004848
+#define DDRSS_PHY_27_DATA 0x00000000
+#define DDRSS_PHY_28_DATA 0x00000000
+#define DDRSS_PHY_29_DATA 0x08000000
+#define DDRSS_PHY_30_DATA 0x0F000008
+#define DDRSS_PHY_31_DATA 0x00000F0F
+#define DDRSS_PHY_32_DATA 0x00E4E400
+#define DDRSS_PHY_33_DATA 0x00071020
+#define DDRSS_PHY_34_DATA 0x000C0020
+#define DDRSS_PHY_35_DATA 0x00062000
+#define DDRSS_PHY_36_DATA 0x00000000
+#define DDRSS_PHY_37_DATA 0x55555555
+#define DDRSS_PHY_38_DATA 0xAAAAAAAA
+#define DDRSS_PHY_39_DATA 0x55555555
+#define DDRSS_PHY_40_DATA 0xAAAAAAAA
+#define DDRSS_PHY_41_DATA 0x00005555
+#define DDRSS_PHY_42_DATA 0x01000100
+#define DDRSS_PHY_43_DATA 0x00800180
+#define DDRSS_PHY_44_DATA 0x00000001
+#define DDRSS_PHY_45_DATA 0x00000000
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000004
+#define DDRSS_PHY_66_DATA 0x00000000
+#define DDRSS_PHY_67_DATA 0x00000000
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x041F07FF
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x01CC0B01
+#define DDRSS_PHY_75_DATA 0x1003CC0B
+#define DDRSS_PHY_76_DATA 0x20000140
+#define DDRSS_PHY_77_DATA 0x07FF0200
+#define DDRSS_PHY_78_DATA 0x0000DD01
+#define DDRSS_PHY_79_DATA 0x00100303
+#define DDRSS_PHY_80_DATA 0x00000000
+#define DDRSS_PHY_81_DATA 0x00000000
+#define DDRSS_PHY_82_DATA 0x00021000
+#define DDRSS_PHY_83_DATA 0x00100010
+#define DDRSS_PHY_84_DATA 0x00100010
+#define DDRSS_PHY_85_DATA 0x00100010
+#define DDRSS_PHY_86_DATA 0x00100010
+#define DDRSS_PHY_87_DATA 0x02020010
+#define DDRSS_PHY_88_DATA 0x51516041
+#define DDRSS_PHY_89_DATA 0x31C06000
+#define DDRSS_PHY_90_DATA 0x07AB0340
+#define DDRSS_PHY_91_DATA 0x0000C0C0
+#define DDRSS_PHY_92_DATA 0x04050000
+#define DDRSS_PHY_93_DATA 0x00000504
+#define DDRSS_PHY_94_DATA 0x42100010
+#define DDRSS_PHY_95_DATA 0x010C053E
+#define DDRSS_PHY_96_DATA 0x000F0C1D
+#define DDRSS_PHY_97_DATA 0x01000140
+#define DDRSS_PHY_98_DATA 0x007A0120
+#define DDRSS_PHY_99_DATA 0x00000C00
+#define DDRSS_PHY_100_DATA 0x000001CC
+#define DDRSS_PHY_101_DATA 0x20100200
+#define DDRSS_PHY_102_DATA 0x00000005
+#define DDRSS_PHY_103_DATA 0x56704132
+#define DDRSS_PHY_104_DATA 0x00000008
+#define DDRSS_PHY_105_DATA 0x034C034C
+#define DDRSS_PHY_106_DATA 0x034C034C
+#define DDRSS_PHY_107_DATA 0x034C034C
+#define DDRSS_PHY_108_DATA 0x034C034C
+#define DDRSS_PHY_109_DATA 0x0000034C
+#define DDRSS_PHY_110_DATA 0x00008000
+#define DDRSS_PHY_111_DATA 0x00800080
+#define DDRSS_PHY_112_DATA 0x00800080
+#define DDRSS_PHY_113_DATA 0x00800080
+#define DDRSS_PHY_114_DATA 0x00800080
+#define DDRSS_PHY_115_DATA 0x00800080
+#define DDRSS_PHY_116_DATA 0x00800080
+#define DDRSS_PHY_117_DATA 0x00800080
+#define DDRSS_PHY_118_DATA 0x00800080
+#define DDRSS_PHY_119_DATA 0x01800080
+#define DDRSS_PHY_120_DATA 0x01000000
+#define DDRSS_PHY_121_DATA 0x00000000
+#define DDRSS_PHY_122_DATA 0x00000000
+#define DDRSS_PHY_123_DATA 0x00080200
+#define DDRSS_PHY_124_DATA 0x00000000
+#define DDRSS_PHY_125_DATA 0x0000F0F0
+#define DDRSS_PHY_126_DATA 0x00000000
+#define DDRSS_PHY_127_DATA 0x00000000
+#define DDRSS_PHY_128_DATA 0x00000000
+#define DDRSS_PHY_129_DATA 0x00000000
+#define DDRSS_PHY_130_DATA 0x00000000
+#define DDRSS_PHY_131_DATA 0x00000000
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x00000000
+#define DDRSS_PHY_134_DATA 0x00000000
+#define DDRSS_PHY_135_DATA 0x00000000
+#define DDRSS_PHY_136_DATA 0x00000000
+#define DDRSS_PHY_137_DATA 0x00000000
+#define DDRSS_PHY_138_DATA 0x00000000
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x04F00000
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00030200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x01000000
+#define DDRSS_PHY_262_DATA 0x03000400
+#define DDRSS_PHY_263_DATA 0x00000001
+#define DDRSS_PHY_264_DATA 0x00000001
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x01010000
+#define DDRSS_PHY_268_DATA 0x00010000
+#define DDRSS_PHY_269_DATA 0x00C00001
+#define DDRSS_PHY_270_DATA 0x00CC0008
+#define DDRSS_PHY_271_DATA 0x00660601
+#define DDRSS_PHY_272_DATA 0x00000003
+#define DDRSS_PHY_273_DATA 0x00000000
+#define DDRSS_PHY_274_DATA 0x00000000
+#define DDRSS_PHY_275_DATA 0x0000AAAA
+#define DDRSS_PHY_276_DATA 0x00005555
+#define DDRSS_PHY_277_DATA 0x0000B5B5
+#define DDRSS_PHY_278_DATA 0x00004A4A
+#define DDRSS_PHY_279_DATA 0x00005656
+#define DDRSS_PHY_280_DATA 0x0000A9A9
+#define DDRSS_PHY_281_DATA 0x0000B7B7
+#define DDRSS_PHY_282_DATA 0x00004848
+#define DDRSS_PHY_283_DATA 0x00000000
+#define DDRSS_PHY_284_DATA 0x00000000
+#define DDRSS_PHY_285_DATA 0x08000000
+#define DDRSS_PHY_286_DATA 0x0F000008
+#define DDRSS_PHY_287_DATA 0x00000F0F
+#define DDRSS_PHY_288_DATA 0x00E4E400
+#define DDRSS_PHY_289_DATA 0x00071020
+#define DDRSS_PHY_290_DATA 0x000C0020
+#define DDRSS_PHY_291_DATA 0x00062000
+#define DDRSS_PHY_292_DATA 0x00000000
+#define DDRSS_PHY_293_DATA 0x55555555
+#define DDRSS_PHY_294_DATA 0xAAAAAAAA
+#define DDRSS_PHY_295_DATA 0x55555555
+#define DDRSS_PHY_296_DATA 0xAAAAAAAA
+#define DDRSS_PHY_297_DATA 0x00005555
+#define DDRSS_PHY_298_DATA 0x01000100
+#define DDRSS_PHY_299_DATA 0x00800180
+#define DDRSS_PHY_300_DATA 0x00000000
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000004
+#define DDRSS_PHY_322_DATA 0x00000000
+#define DDRSS_PHY_323_DATA 0x00000000
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x041F07FF
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x01CC0B01
+#define DDRSS_PHY_331_DATA 0x1003CC0B
+#define DDRSS_PHY_332_DATA 0x20000140
+#define DDRSS_PHY_333_DATA 0x07FF0200
+#define DDRSS_PHY_334_DATA 0x0000DD01
+#define DDRSS_PHY_335_DATA 0x00100303
+#define DDRSS_PHY_336_DATA 0x00000000
+#define DDRSS_PHY_337_DATA 0x00000000
+#define DDRSS_PHY_338_DATA 0x00021000
+#define DDRSS_PHY_339_DATA 0x00100010
+#define DDRSS_PHY_340_DATA 0x00100010
+#define DDRSS_PHY_341_DATA 0x00100010
+#define DDRSS_PHY_342_DATA 0x00100010
+#define DDRSS_PHY_343_DATA 0x02020010
+#define DDRSS_PHY_344_DATA 0x51516041
+#define DDRSS_PHY_345_DATA 0x31C06000
+#define DDRSS_PHY_346_DATA 0x07AB0340
+#define DDRSS_PHY_347_DATA 0x0000C0C0
+#define DDRSS_PHY_348_DATA 0x04050000
+#define DDRSS_PHY_349_DATA 0x00000504
+#define DDRSS_PHY_350_DATA 0x42100010
+#define DDRSS_PHY_351_DATA 0x010C053E
+#define DDRSS_PHY_352_DATA 0x000F0C1D
+#define DDRSS_PHY_353_DATA 0x01000140
+#define DDRSS_PHY_354_DATA 0x007A0120
+#define DDRSS_PHY_355_DATA 0x00000C00
+#define DDRSS_PHY_356_DATA 0x000001CC
+#define DDRSS_PHY_357_DATA 0x20100200
+#define DDRSS_PHY_358_DATA 0x00000005
+#define DDRSS_PHY_359_DATA 0x03415762
+#define DDRSS_PHY_360_DATA 0x00000008
+#define DDRSS_PHY_361_DATA 0x034C034C
+#define DDRSS_PHY_362_DATA 0x034C034C
+#define DDRSS_PHY_363_DATA 0x034C034C
+#define DDRSS_PHY_364_DATA 0x034C034C
+#define DDRSS_PHY_365_DATA 0x0000034C
+#define DDRSS_PHY_366_DATA 0x00008000
+#define DDRSS_PHY_367_DATA 0x00800080
+#define DDRSS_PHY_368_DATA 0x00800080
+#define DDRSS_PHY_369_DATA 0x00800080
+#define DDRSS_PHY_370_DATA 0x00800080
+#define DDRSS_PHY_371_DATA 0x00800080
+#define DDRSS_PHY_372_DATA 0x00800080
+#define DDRSS_PHY_373_DATA 0x00800080
+#define DDRSS_PHY_374_DATA 0x00800080
+#define DDRSS_PHY_375_DATA 0x01800080
+#define DDRSS_PHY_376_DATA 0x01000000
+#define DDRSS_PHY_377_DATA 0x00000000
+#define DDRSS_PHY_378_DATA 0x00000000
+#define DDRSS_PHY_379_DATA 0x00080200
+#define DDRSS_PHY_380_DATA 0x00000000
+#define DDRSS_PHY_381_DATA 0x0000F0F0
+#define DDRSS_PHY_382_DATA 0x00000000
+#define DDRSS_PHY_383_DATA 0x00000000
+#define DDRSS_PHY_384_DATA 0x00000000
+#define DDRSS_PHY_385_DATA 0x00000000
+#define DDRSS_PHY_386_DATA 0x00000000
+#define DDRSS_PHY_387_DATA 0x00000000
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x00000000
+#define DDRSS_PHY_390_DATA 0x00000000
+#define DDRSS_PHY_391_DATA 0x00000000
+#define DDRSS_PHY_392_DATA 0x00000000
+#define DDRSS_PHY_393_DATA 0x00000000
+#define DDRSS_PHY_394_DATA 0x00000000
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x00000000
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00000000
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x00000100
+#define DDRSS_PHY_518_DATA 0x00000200
+#define DDRSS_PHY_519_DATA 0x00000000
+#define DDRSS_PHY_520_DATA 0x00000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x00400000
+#define DDRSS_PHY_524_DATA 0x00000080
+#define DDRSS_PHY_525_DATA 0x00DCBA98
+#define DDRSS_PHY_526_DATA 0x03000000
+#define DDRSS_PHY_527_DATA 0x00200000
+#define DDRSS_PHY_528_DATA 0x00000000
+#define DDRSS_PHY_529_DATA 0x00000000
+#define DDRSS_PHY_530_DATA 0x00000000
+#define DDRSS_PHY_531_DATA 0x00000000
+#define DDRSS_PHY_532_DATA 0x0000002A
+#define DDRSS_PHY_533_DATA 0x00000015
+#define DDRSS_PHY_534_DATA 0x00000015
+#define DDRSS_PHY_535_DATA 0x0000002A
+#define DDRSS_PHY_536_DATA 0x00000033
+#define DDRSS_PHY_537_DATA 0x0000000C
+#define DDRSS_PHY_538_DATA 0x0000000C
+#define DDRSS_PHY_539_DATA 0x00000033
+#define DDRSS_PHY_540_DATA 0x0A418820
+#define DDRSS_PHY_541_DATA 0x003F0000
+#define DDRSS_PHY_542_DATA 0x000F013F
+#define DDRSS_PHY_543_DATA 0x0000000F
+#define DDRSS_PHY_544_DATA 0x020002CC
+#define DDRSS_PHY_545_DATA 0x00030000
+#define DDRSS_PHY_546_DATA 0x00000300
+#define DDRSS_PHY_547_DATA 0x00000300
+#define DDRSS_PHY_548_DATA 0x00000300
+#define DDRSS_PHY_549_DATA 0x00000300
+#define DDRSS_PHY_550_DATA 0x00000300
+#define DDRSS_PHY_551_DATA 0x42080010
+#define DDRSS_PHY_552_DATA 0x0000803E
+#define DDRSS_PHY_553_DATA 0x00000003
+#define DDRSS_PHY_554_DATA 0x00000002
+#define DDRSS_PHY_555_DATA 0x00000000
+#define DDRSS_PHY_556_DATA 0x00000000
+#define DDRSS_PHY_557_DATA 0x00000000
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000000
+#define DDRSS_PHY_579_DATA 0x00000000
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x00000000
+#define DDRSS_PHY_587_DATA 0x00000000
+#define DDRSS_PHY_588_DATA 0x00000000
+#define DDRSS_PHY_589_DATA 0x00000000
+#define DDRSS_PHY_590_DATA 0x00000000
+#define DDRSS_PHY_591_DATA 0x00000000
+#define DDRSS_PHY_592_DATA 0x00000000
+#define DDRSS_PHY_593_DATA 0x00000000
+#define DDRSS_PHY_594_DATA 0x00000000
+#define DDRSS_PHY_595_DATA 0x00000000
+#define DDRSS_PHY_596_DATA 0x00000000
+#define DDRSS_PHY_597_DATA 0x00000000
+#define DDRSS_PHY_598_DATA 0x00000000
+#define DDRSS_PHY_599_DATA 0x00000000
+#define DDRSS_PHY_600_DATA 0x00000000
+#define DDRSS_PHY_601_DATA 0x00000000
+#define DDRSS_PHY_602_DATA 0x00000000
+#define DDRSS_PHY_603_DATA 0x00000000
+#define DDRSS_PHY_604_DATA 0x00000000
+#define DDRSS_PHY_605_DATA 0x00000000
+#define DDRSS_PHY_606_DATA 0x00000000
+#define DDRSS_PHY_607_DATA 0x00000000
+#define DDRSS_PHY_608_DATA 0x00000000
+#define DDRSS_PHY_609_DATA 0x00000000
+#define DDRSS_PHY_610_DATA 0x00000000
+#define DDRSS_PHY_611_DATA 0x00000000
+#define DDRSS_PHY_612_DATA 0x00000000
+#define DDRSS_PHY_613_DATA 0x00000000
+#define DDRSS_PHY_614_DATA 0x00000000
+#define DDRSS_PHY_615_DATA 0x00000000
+#define DDRSS_PHY_616_DATA 0x00000000
+#define DDRSS_PHY_617_DATA 0x00000000
+#define DDRSS_PHY_618_DATA 0x00000000
+#define DDRSS_PHY_619_DATA 0x00000000
+#define DDRSS_PHY_620_DATA 0x00000000
+#define DDRSS_PHY_621_DATA 0x00000000
+#define DDRSS_PHY_622_DATA 0x00000000
+#define DDRSS_PHY_623_DATA 0x00000000
+#define DDRSS_PHY_624_DATA 0x00000000
+#define DDRSS_PHY_625_DATA 0x00000000
+#define DDRSS_PHY_626_DATA 0x00000000
+#define DDRSS_PHY_627_DATA 0x00000000
+#define DDRSS_PHY_628_DATA 0x00000000
+#define DDRSS_PHY_629_DATA 0x00000000
+#define DDRSS_PHY_630_DATA 0x00000000
+#define DDRSS_PHY_631_DATA 0x00000000
+#define DDRSS_PHY_632_DATA 0x00000000
+#define DDRSS_PHY_633_DATA 0x00000000
+#define DDRSS_PHY_634_DATA 0x00000000
+#define DDRSS_PHY_635_DATA 0x00000000
+#define DDRSS_PHY_636_DATA 0x00000000
+#define DDRSS_PHY_637_DATA 0x00000000
+#define DDRSS_PHY_638_DATA 0x00000000
+#define DDRSS_PHY_639_DATA 0x00000000
+#define DDRSS_PHY_640_DATA 0x00000000
+#define DDRSS_PHY_641_DATA 0x00000000
+#define DDRSS_PHY_642_DATA 0x00000000
+#define DDRSS_PHY_643_DATA 0x00000000
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x00000000
+#define DDRSS_PHY_646_DATA 0x00000000
+#define DDRSS_PHY_647_DATA 0x00000000
+#define DDRSS_PHY_648_DATA 0x00000000
+#define DDRSS_PHY_649_DATA 0x00000000
+#define DDRSS_PHY_650_DATA 0x00000000
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x00000000
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00000000
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x00000100
+#define DDRSS_PHY_774_DATA 0x00000200
+#define DDRSS_PHY_775_DATA 0x00000000
+#define DDRSS_PHY_776_DATA 0x00000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x00400000
+#define DDRSS_PHY_780_DATA 0x00000080
+#define DDRSS_PHY_781_DATA 0x00DCBA98
+#define DDRSS_PHY_782_DATA 0x03000000
+#define DDRSS_PHY_783_DATA 0x00200000
+#define DDRSS_PHY_784_DATA 0x00000000
+#define DDRSS_PHY_785_DATA 0x00000000
+#define DDRSS_PHY_786_DATA 0x00000000
+#define DDRSS_PHY_787_DATA 0x00000000
+#define DDRSS_PHY_788_DATA 0x0000002A
+#define DDRSS_PHY_789_DATA 0x00000015
+#define DDRSS_PHY_790_DATA 0x00000015
+#define DDRSS_PHY_791_DATA 0x0000002A
+#define DDRSS_PHY_792_DATA 0x00000033
+#define DDRSS_PHY_793_DATA 0x0000000C
+#define DDRSS_PHY_794_DATA 0x0000000C
+#define DDRSS_PHY_795_DATA 0x00000033
+#define DDRSS_PHY_796_DATA 0x00000000
+#define DDRSS_PHY_797_DATA 0x00000000
+#define DDRSS_PHY_798_DATA 0x000F0000
+#define DDRSS_PHY_799_DATA 0x0000000F
+#define DDRSS_PHY_800_DATA 0x020002CC
+#define DDRSS_PHY_801_DATA 0x00030000
+#define DDRSS_PHY_802_DATA 0x00000300
+#define DDRSS_PHY_803_DATA 0x00000300
+#define DDRSS_PHY_804_DATA 0x00000300
+#define DDRSS_PHY_805_DATA 0x00000300
+#define DDRSS_PHY_806_DATA 0x00000300
+#define DDRSS_PHY_807_DATA 0x42080010
+#define DDRSS_PHY_808_DATA 0x0000803E
+#define DDRSS_PHY_809_DATA 0x00000003
+#define DDRSS_PHY_810_DATA 0x00000002
+#define DDRSS_PHY_811_DATA 0x00000000
+#define DDRSS_PHY_812_DATA 0x00000000
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000000
+#define DDRSS_PHY_835_DATA 0x00000000
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x00000000
+#define DDRSS_PHY_843_DATA 0x00000000
+#define DDRSS_PHY_844_DATA 0x00000000
+#define DDRSS_PHY_845_DATA 0x00000000
+#define DDRSS_PHY_846_DATA 0x00000000
+#define DDRSS_PHY_847_DATA 0x00000000
+#define DDRSS_PHY_848_DATA 0x00000000
+#define DDRSS_PHY_849_DATA 0x00000000
+#define DDRSS_PHY_850_DATA 0x00000000
+#define DDRSS_PHY_851_DATA 0x00000000
+#define DDRSS_PHY_852_DATA 0x00000000
+#define DDRSS_PHY_853_DATA 0x00000000
+#define DDRSS_PHY_854_DATA 0x00000000
+#define DDRSS_PHY_855_DATA 0x00000000
+#define DDRSS_PHY_856_DATA 0x00000000
+#define DDRSS_PHY_857_DATA 0x00000000
+#define DDRSS_PHY_858_DATA 0x00000000
+#define DDRSS_PHY_859_DATA 0x00000000
+#define DDRSS_PHY_860_DATA 0x00000000
+#define DDRSS_PHY_861_DATA 0x00000000
+#define DDRSS_PHY_862_DATA 0x00000000
+#define DDRSS_PHY_863_DATA 0x00000000
+#define DDRSS_PHY_864_DATA 0x00000000
+#define DDRSS_PHY_865_DATA 0x00000000
+#define DDRSS_PHY_866_DATA 0x00000000
+#define DDRSS_PHY_867_DATA 0x00000000
+#define DDRSS_PHY_868_DATA 0x00000000
+#define DDRSS_PHY_869_DATA 0x00000000
+#define DDRSS_PHY_870_DATA 0x00000000
+#define DDRSS_PHY_871_DATA 0x00000000
+#define DDRSS_PHY_872_DATA 0x00000000
+#define DDRSS_PHY_873_DATA 0x00000000
+#define DDRSS_PHY_874_DATA 0x00000000
+#define DDRSS_PHY_875_DATA 0x00000000
+#define DDRSS_PHY_876_DATA 0x00000000
+#define DDRSS_PHY_877_DATA 0x00000000
+#define DDRSS_PHY_878_DATA 0x00000000
+#define DDRSS_PHY_879_DATA 0x00000000
+#define DDRSS_PHY_880_DATA 0x00000000
+#define DDRSS_PHY_881_DATA 0x00000000
+#define DDRSS_PHY_882_DATA 0x00000000
+#define DDRSS_PHY_883_DATA 0x00000000
+#define DDRSS_PHY_884_DATA 0x00000000
+#define DDRSS_PHY_885_DATA 0x00000000
+#define DDRSS_PHY_886_DATA 0x00000000
+#define DDRSS_PHY_887_DATA 0x00000000
+#define DDRSS_PHY_888_DATA 0x00000000
+#define DDRSS_PHY_889_DATA 0x00000000
+#define DDRSS_PHY_890_DATA 0x00000000
+#define DDRSS_PHY_891_DATA 0x00000000
+#define DDRSS_PHY_892_DATA 0x00000000
+#define DDRSS_PHY_893_DATA 0x00000000
+#define DDRSS_PHY_894_DATA 0x00000000
+#define DDRSS_PHY_895_DATA 0x00000000
+#define DDRSS_PHY_896_DATA 0x00000000
+#define DDRSS_PHY_897_DATA 0x00000000
+#define DDRSS_PHY_898_DATA 0x00000000
+#define DDRSS_PHY_899_DATA 0x00000000
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x00000000
+#define DDRSS_PHY_902_DATA 0x00000000
+#define DDRSS_PHY_903_DATA 0x00000000
+#define DDRSS_PHY_904_DATA 0x00000000
+#define DDRSS_PHY_905_DATA 0x00000000
+#define DDRSS_PHY_906_DATA 0x00000000
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000000
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000200
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00400000
+#define DDRSS_PHY_1036_DATA 0x00000080
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x03000000
+#define DDRSS_PHY_1039_DATA 0x00200000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x0000002A
+#define DDRSS_PHY_1045_DATA 0x00000015
+#define DDRSS_PHY_1046_DATA 0x00000015
+#define DDRSS_PHY_1047_DATA 0x0000002A
+#define DDRSS_PHY_1048_DATA 0x00000033
+#define DDRSS_PHY_1049_DATA 0x0000000C
+#define DDRSS_PHY_1050_DATA 0x0000000C
+#define DDRSS_PHY_1051_DATA 0x00000033
+#define DDRSS_PHY_1052_DATA 0x2307B9AC
+#define DDRSS_PHY_1053_DATA 0x10000000
+#define DDRSS_PHY_1054_DATA 0x000F0000
+#define DDRSS_PHY_1055_DATA 0x0000000F
+#define DDRSS_PHY_1056_DATA 0x020002CC
+#define DDRSS_PHY_1057_DATA 0x00030000
+#define DDRSS_PHY_1058_DATA 0x00000300
+#define DDRSS_PHY_1059_DATA 0x00000300
+#define DDRSS_PHY_1060_DATA 0x00000300
+#define DDRSS_PHY_1061_DATA 0x00000300
+#define DDRSS_PHY_1062_DATA 0x00000300
+#define DDRSS_PHY_1063_DATA 0x42080010
+#define DDRSS_PHY_1064_DATA 0x0000803E
+#define DDRSS_PHY_1065_DATA 0x00000003
+#define DDRSS_PHY_1066_DATA 0x00000002
+#define DDRSS_PHY_1067_DATA 0x00000000
+#define DDRSS_PHY_1068_DATA 0x00000000
+#define DDRSS_PHY_1069_DATA 0x00000000
+#define DDRSS_PHY_1070_DATA 0x00000000
+#define DDRSS_PHY_1071_DATA 0x00000000
+#define DDRSS_PHY_1072_DATA 0x00000000
+#define DDRSS_PHY_1073_DATA 0x00000000
+#define DDRSS_PHY_1074_DATA 0x00000000
+#define DDRSS_PHY_1075_DATA 0x00000000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00010100
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00000000
+#define DDRSS_PHY_1285_DATA 0x00000000
+#define DDRSS_PHY_1286_DATA 0x00050000
+#define DDRSS_PHY_1287_DATA 0x04000000
+#define DDRSS_PHY_1288_DATA 0x00000055
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00000000
+#define DDRSS_PHY_1292_DATA 0x00000000
+#define DDRSS_PHY_1293_DATA 0x00002001
+#define DDRSS_PHY_1294_DATA 0x00004001
+#define DDRSS_PHY_1295_DATA 0x00020028
+#define DDRSS_PHY_1296_DATA 0x01010100
+#define DDRSS_PHY_1297_DATA 0x00000000
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x0F0F0E06
+#define DDRSS_PHY_1300_DATA 0x00010101
+#define DDRSS_PHY_1301_DATA 0x010F0004
+#define DDRSS_PHY_1302_DATA 0x00000000
+#define DDRSS_PHY_1303_DATA 0x00000000
+#define DDRSS_PHY_1304_DATA 0x00000064
+#define DDRSS_PHY_1305_DATA 0x00000000
+#define DDRSS_PHY_1306_DATA 0x00000000
+#define DDRSS_PHY_1307_DATA 0x01020103
+#define DDRSS_PHY_1308_DATA 0x0F020102
+#define DDRSS_PHY_1309_DATA 0x03030303
+#define DDRSS_PHY_1310_DATA 0x03030303
+#define DDRSS_PHY_1311_DATA 0x00041B42
+#define DDRSS_PHY_1312_DATA 0x00005201
+#define DDRSS_PHY_1313_DATA 0x00000000
+#define DDRSS_PHY_1314_DATA 0x00000000
+#define DDRSS_PHY_1315_DATA 0x00000000
+#define DDRSS_PHY_1316_DATA 0x00000000
+#define DDRSS_PHY_1317_DATA 0x00000000
+#define DDRSS_PHY_1318_DATA 0x00000000
+#define DDRSS_PHY_1319_DATA 0x07030101
+#define DDRSS_PHY_1320_DATA 0x00005400
+#define DDRSS_PHY_1321_DATA 0x000040A2
+#define DDRSS_PHY_1322_DATA 0x00024410
+#define DDRSS_PHY_1323_DATA 0x00004410
+#define DDRSS_PHY_1324_DATA 0x00004410
+#define DDRSS_PHY_1325_DATA 0x00004410
+#define DDRSS_PHY_1326_DATA 0x00004410
+#define DDRSS_PHY_1327_DATA 0x00004410
+#define DDRSS_PHY_1328_DATA 0x00004410
+#define DDRSS_PHY_1329_DATA 0x00004410
+#define DDRSS_PHY_1330_DATA 0x00004410
+#define DDRSS_PHY_1331_DATA 0x00004410
+#define DDRSS_PHY_1332_DATA 0x00000000
+#define DDRSS_PHY_1333_DATA 0x00000076
+#define DDRSS_PHY_1334_DATA 0x00000400
+#define DDRSS_PHY_1335_DATA 0x00000008
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x00000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x03000000
+#define DDRSS_PHY_1342_DATA 0x00000000
+#define DDRSS_PHY_1343_DATA 0x00000000
+#define DDRSS_PHY_1344_DATA 0x00000000
+#define DDRSS_PHY_1345_DATA 0x04102006
+#define DDRSS_PHY_1346_DATA 0x00041020
+#define DDRSS_PHY_1347_DATA 0x01C98C98
+#define DDRSS_PHY_1348_DATA 0x3F400000
+#define DDRSS_PHY_1349_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1350_DATA 0x0000001F
+#define DDRSS_PHY_1351_DATA 0x00000000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000001
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x00000000
+#define DDRSS_PHY_1357_DATA 0x00000000
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x76543210
+#define DDRSS_PHY_1360_DATA 0x00040198
+#define DDRSS_PHY_1361_DATA 0x00000000
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00040700
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000000
+#define DDRSS_PHY_1368_DATA 0x00000002
+#define DDRSS_PHY_1369_DATA 0x00000000
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x0001F7C2
+#define DDRSS_PHY_1372_DATA 0x00020002
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00001142
+#define DDRSS_PHY_1375_DATA 0x03020000
+#define DDRSS_PHY_1376_DATA 0x00000080
+#define DDRSS_PHY_1377_DATA 0x03900390
+#define DDRSS_PHY_1378_DATA 0x03900390
+#define DDRSS_PHY_1379_DATA 0x03900390
+#define DDRSS_PHY_1380_DATA 0x03900390
+#define DDRSS_PHY_1381_DATA 0x03000300
+#define DDRSS_PHY_1382_DATA 0x03000300
+#define DDRSS_PHY_1383_DATA 0x00000300
+#define DDRSS_PHY_1384_DATA 0x00000300
+#define DDRSS_PHY_1385_DATA 0x00000300
+#define DDRSS_PHY_1386_DATA 0x00000300
+#define DDRSS_PHY_1387_DATA 0x3183BF77
+#define DDRSS_PHY_1388_DATA 0x00000000
+#define DDRSS_PHY_1389_DATA 0x0C000DFF
+#define DDRSS_PHY_1390_DATA 0x30000DFF
+#define DDRSS_PHY_1391_DATA 0x3F0DFF11
+#define DDRSS_PHY_1392_DATA 0x01990000
+#define DDRSS_PHY_1393_DATA 0x780DFFCC
+#define DDRSS_PHY_1394_DATA 0x00000C11
+#define DDRSS_PHY_1395_DATA 0x00018011
+#define DDRSS_PHY_1396_DATA 0x0089FF00
+#define DDRSS_PHY_1397_DATA 0x000C3F11
+#define DDRSS_PHY_1398_DATA 0x01990000
+#define DDRSS_PHY_1399_DATA 0x000C3F11
+#define DDRSS_PHY_1400_DATA 0x01990000
+#define DDRSS_PHY_1401_DATA 0x3F0DFF11
+#define DDRSS_PHY_1402_DATA 0x01990000
+#define DDRSS_PHY_1403_DATA 0x00018011
+#define DDRSS_PHY_1404_DATA 0x0089FF00
+#define DDRSS_PHY_1405_DATA 0x20040004
diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts
new file mode 100644
index 0000000..0cae9c5
--- /dev/null
+++ b/arch/arm/dts/k3-am625-verdin-r5.dts
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Toradex Verdin AM62 dts file for R5 SPL
+ * Copyright 2023 Toradex - https://www.toradex.com/
+ */
+
+#include "k3-am625-verdin-wifi-dev.dts"
+#include "k3-am625-verdin-lpddr4-1600MTs.dtsi"
+#include "k3-am62-ddr.dtsi"
+
+#include "k3-am625-verdin-wifi-dev-u-boot.dtsi"
+
+/ {
+ a53_0: a53@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x00 0x00a90000 0x00 0x10>;
+ /*
+ * FIXME: Currently only the SPL running on the R5 has a clock
+ * driver. As a workaround therefore move the assigned-clock
+ * stuff required for our ETH_25MHz_CLK from the cpsw3g_mdio
+ * node of the regular device tree to here (last one each in
+ * below three lines, adding a <0> as spacing for parents).
+ */
+ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 20>;
+ assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 22>;
+ assigned-clock-rates = <200000000>, <1200000000>, <25000000>;
+ clocks = <&k3_clks 61 0>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 135 0>;
+ ti,sci = <&dmsc>;
+ ti,sci-host-id = <10>;
+ ti,sci-proc-id = <32>;
+ bootph-pre-ram;
+ };
+
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a53_0;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_main 22>,
+ <&secure_proxy_main 23>;
+ ti,host-id = <36>;
+ ti,secure-host;
+ bootph-pre-ram;
+ };
+};
+
+&cbass_main {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
+ mbox-names = "tx", "rx", "boot_notify";
+ bootph-pre-ram;
+ };
+};
+
+&dmsc {
+ mboxes= <&secure_proxy_main 0>,
+ <&secure_proxy_main 1>,
+ <&secure_proxy_main 0>;
+ mbox-names = "rx", "tx", "notify";
+ ti,host-id = <35>;
+ ti,secure-host;
+};
+
+&main_esm {
+ bootph-pre-ram;
+};
+
+&mcu_esm {
+ bootph-pre-ram;
+};
+
+&secure_proxy_sa3 {
+ bootph-pre-ram;
+ /* We require this for boot handshake */
+ status = "okay";
+};
diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
new file mode 100644
index 0000000..089b2a5
--- /dev/null
+++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
@@ -0,0 +1,532 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ */
+
+#include "k3-binman.dtsi"
+
+&custmpk_pem {
+ filename = "../../ti/keys/custMpk.pem";
+};
+
+&dkey_pem {
+ filename = "../../ti/keys/ti-degenerate-key.pem";
+};
+
+#ifndef CONFIG_ARM64
+
+&bcfg_yaml {
+ schema = "../../ti/common/schema.yaml";
+};
+
+&pcfg_yaml {
+ schema = "../../ti/common/schema.yaml";
+};
+
+&rcfg_yaml {
+ schema = "../../ti/common/schema.yaml";
+};
+
+&scfg_yaml {
+ schema = "../../ti/common/schema.yaml";
+};
+
+/* combined-tifs-cfg */
+
+&bcfg_yaml_tifs {
+ schema = "../../ti/common/schema.yaml";
+};
+
+&pcfg_yaml_tifs {
+ schema = "../../ti/common/schema.yaml";
+};
+
+&rcfg_yaml_tifs {
+ schema = "../../ti/common/schema.yaml";
+};
+
+&scfg_yaml_tifs {
+ schema = "../../ti/common/schema.yaml";
+};
+
+/* combined-dm-cfg */
+
+&pcfg_yaml_dm {
+ schema = "../../ti/common/schema.yaml";
+};
+
+&rcfg_yaml_dm {
+ schema = "../../ti/common/schema.yaml";
+};
+
+/* combined-sysfw-cfg */
+
+&bcfg_yaml_sysfw {
+ schema = "../../ti/common/schema.yaml";
+};
+
+&pcfg_yaml_sysfw {
+ schema = "../../ti/common/schema.yaml";
+};
+
+&rcfg_yaml_sysfw {
+ schema = "../../ti/common/schema.yaml";
+};
+
+&scfg_yaml_sysfw {
+ schema = "../../ti/common/schema.yaml";
+};
+
+#endif /* CONFIG_ARM64 */
+
+#ifdef CONFIG_TARGET_VERDIN_AM62_R5
+
+&binman {
+ tiboot3-am62x-hs-verdin.bin {
+ filename = "tiboot3-am62x-hs-verdin.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
+ <&combined_dm_cfg>, <&sysfw_inner_cert>;
+ combined;
+ dm-data;
+ sysfw-inner-cert;
+ keyfile = "custMpk.pem";
+ sw-rev = <1>;
+ content-sbl = <&u_boot_spl>;
+ content-sysfw = <&ti_fs_enc>;
+ content-sysfw-data = <&combined_tifs_cfg>;
+ content-sysfw-inner-cert = <&sysfw_inner_cert>;
+ content-dm-data = <&combined_dm_cfg>;
+ load = <0x43c00000>;
+ load-sysfw = <0x40000>;
+ load-sysfw-data = <0x67000>;
+ load-dm-data = <0x43c3a800>;
+ };
+ u_boot_spl: u-boot-spl {
+ no-expanded;
+ };
+ ti_fs_enc: ti-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-firmware-am62x-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_tifs_cfg: combined-tifs-cfg.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+ sysfw_inner_cert: sysfw-inner-cert {
+ filename = "ti-sysfw/ti-fs-firmware-am62x-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_dm_cfg: combined-dm-cfg.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+};
+
+&binman {
+ tiboot3-am62x-hs-fs-verdin.bin {
+ filename = "tiboot3-am62x-hs-fs-verdin.bin";
+ symlink = "tiboot3.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
+ <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
+ combined;
+ dm-data;
+ sysfw-inner-cert;
+ keyfile = "custMpk.pem";
+ sw-rev = <1>;
+ content-sbl = <&u_boot_spl_fs>;
+ content-sysfw = <&ti_fs_enc_fs>;
+ content-sysfw-data = <&combined_tifs_cfg_fs>;
+ content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
+ content-dm-data = <&combined_dm_cfg_fs>;
+ load = <0x43c00000>;
+ load-sysfw = <0x40000>;
+ load-sysfw-data = <0x67000>;
+ load-dm-data = <0x43c3a800>;
+ };
+ u_boot_spl_fs: u-boot-spl {
+ no-expanded;
+ };
+ ti_fs_enc_fs: ti-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_tifs_cfg_fs: combined-tifs-cfg.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+ sysfw_inner_cert_fs: sysfw-inner-cert {
+ filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_dm_cfg_fs: combined-dm-cfg.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+};
+
+&binman {
+ tiboot3-am62x-gp-verdin.bin {
+ filename = "tiboot3-am62x-gp-verdin.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
+ <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
+ combined;
+ dm-data;
+ content-sbl = <&u_boot_spl_unsigned>;
+ load = <0x43c00000>;
+ content-sysfw = <&ti_fs_gp>;
+ load-sysfw = <0x40000>;
+ content-sysfw-data = <&combined_tifs_cfg_gp>;
+ load-sysfw-data = <0x67000>;
+ content-dm-data = <&combined_dm_cfg_gp>;
+ load-dm-data = <0x43c3a800>;
+ sw-rev = <1>;
+ keyfile = "ti-degenerate-key.pem";
+ };
+ u_boot_spl_unsigned: u-boot-spl {
+ no-expanded;
+ };
+ ti_fs_gp: ti-fs-gp.bin {
+ filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+ combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+};
+
+#endif /* CONFIG_TARGET_VERDIN_AM62_R5 */
+
+#ifdef CONFIG_TARGET_VERDIN_AM62_A53
+
+#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
+#define SPL_VERDIN_AM62_DTB "spl/dts/k3-am625-verdin-wifi-dev.dtb"
+
+#define UBOOT_NODTB "u-boot-nodtb.bin"
+#define VERDIN_AM62_DTB "u-boot.dtb"
+
+&binman {
+ ti-dm {
+ filename = "ti-dm.bin";
+ blob-ext {
+ filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ };
+ };
+ ti-spl {
+ filename = "tispl.bin";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "Configuration to load ATF and SPL";
+ #address-cells = <1>;
+
+ images {
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ os = "arm-trusted-firmware";
+ load = <CONFIG_K3_ATF_LOAD_ADDR>;
+ entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+ ti-secure {
+ content = <&atf>;
+ keyfile = "custMpk.pem";
+ };
+ atf: atf-bl31 {
+ };
+ };
+
+ tee {
+ description = "OP-TEE";
+ type = "tee";
+ arch = "arm64";
+ compression = "none";
+ os = "tee";
+ load = <0x9e800000>;
+ entry = <0x9e800000>;
+ ti-secure {
+ content = <&tee>;
+ keyfile = "custMpk.pem";
+ };
+ tee: tee-os {
+ };
+ };
+
+ dm {
+ description = "DM binary";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "DM";
+ load = <0x89000000>;
+ entry = <0x89000000>;
+ ti-secure {
+ content = <&dm>;
+ keyfile = "custMpk.pem";
+ };
+ dm: blob-ext {
+ filename = "ti-dm.bin";
+ };
+ };
+
+ spl {
+ description = "SPL (64-bit)";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SPL_TEXT_BASE>;
+ entry = <CONFIG_SPL_TEXT_BASE>;
+ ti-secure {
+ content = <&u_boot_spl_nodtb>;
+ keyfile = "custMpk.pem";
+ };
+ u_boot_spl_nodtb: blob-ext {
+ filename = SPL_NODTB;
+ };
+ };
+
+ fdt-0 {
+ description = "k3-am625-verdin-wifi-dev";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <&spl_verdin_am62_dtb>;
+ keyfile = "custMpk.pem";
+ };
+ spl_verdin_am62_dtb: blob-ext {
+ filename = SPL_VERDIN_AM62_DTB;
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-am625-verdin-wifi-dev";
+ firmware = "atf";
+ loadables = "tee", "dm", "spl";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+};
+
+&binman {
+ u-boot {
+ filename = "u-boot.img";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "FIT image with multiple configurations";
+
+ images {
+ uboot {
+ description = "U-Boot for AM625 board";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ ti-secure {
+ content = <&u_boot_nodtb>;
+ keyfile = "custMpk.pem";
+ };
+ u_boot_nodtb: u-boot-nodtb {
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+
+ fdt-0 {
+ description = "k3-am625-verdin-wifi-dev";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <&verdin_am62_dtb>;
+ keyfile = "custMpk.pem";
+ };
+ verdin_am62_dtb: blob-ext {
+ filename = VERDIN_AM62_DTB;
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-am625-verdin-wifi-dev";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+};
+
+&binman {
+ ti-spl_unsigned {
+ filename = "tispl.bin_unsigned";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "Configuration to load ATF and SPL";
+ #address-cells = <1>;
+
+ images {
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ os = "arm-trusted-firmware";
+ load = <CONFIG_K3_ATF_LOAD_ADDR>;
+ entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+ atf-bl31 {
+ filename = "bl31.bin";
+ };
+ };
+
+ tee {
+ description = "OP-TEE";
+ type = "tee";
+ arch = "arm64";
+ compression = "none";
+ os = "tee";
+ load = <0x9e800000>;
+ entry = <0x9e800000>;
+ tee-os {
+ filename = "tee-raw.bin";
+ };
+ };
+
+ dm {
+ description = "DM binary";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "DM";
+ load = <0x89000000>;
+ entry = <0x89000000>;
+ blob-ext {
+ filename = "ti-dm.bin";
+ };
+ };
+
+ spl {
+ description = "SPL (64-bit)";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SPL_TEXT_BASE>;
+ entry = <CONFIG_SPL_TEXT_BASE>;
+ blob {
+ filename = "spl/u-boot-spl-nodtb.bin";
+ };
+ };
+
+ fdt-0 {
+ description = "k3-am625-verdin-wifi-dev";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ blob {
+ filename = SPL_VERDIN_AM62_DTB;
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-am625-verdin-wifi-dev";
+ firmware = "atf";
+ loadables = "tee", "dm", "spl";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+};
+
+&binman {
+ u-boot_unsigned {
+ filename = "u-boot.img_unsigned";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "FIT image with multiple configurations";
+
+ images {
+ uboot {
+ description = "U-Boot for AM625 board";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ blob {
+ filename = UBOOT_NODTB;
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+
+ fdt-0 {
+ description = "k3-am625-verdin-wifi-dev";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ blob {
+ filename = VERDIN_AM62_DTB;
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-am625-verdin-wifi-dev";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+};
+
+#endif /* CONFIG_TARGET_VERDIN_AM62_A53 */
diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
new file mode 100644
index 0000000..5d56460
--- /dev/null
+++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ */
+
+#include "k3-am625-verdin-wifi-dev-binman.dtsi"
+
+/ {
+ aliases {
+ eeprom0 = &eeprom_module;
+ eeprom1 = &eeprom_carrier_board;
+ eeprom2 = &eeprom_display_adapter;
+ };
+
+ chosen {
+ tick-timer = &main_timer0;
+ };
+
+ memory@80000000 {
+ bootph-pre-ram;
+ };
+};
+
+&cbass_main {
+ bootph-pre-ram;
+
+ timer@2400000 {
+ clock-frequency = <25000000>;
+ bootph-pre-ram;
+ };
+};
+
+&cbass_mcu {
+ bootph-pre-ram;
+};
+
+&cbass_wakeup {
+ bootph-pre-ram;
+};
+
+&chipid {
+ bootph-pre-ram;
+};
+
+&cpsw3g {
+ bootph-pre-ram;
+};
+
+&cpsw3g_phy0 {
+ bootph-pre-ram;
+};
+
+&cpsw3g_phy1 {
+ bootph-pre-ram;
+};
+
+&cpsw_port1 {
+ bootph-pre-ram;
+};
+
+&cpsw_port2 {
+ bootph-pre-ram;
+};
+
+/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
+&cpsw3g_mdio {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+ bootph-pre-ram;
+};
+
+&dmsc {
+ bootph-pre-ram;
+
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ bootph-pre-ram;
+ };
+};
+
+&dmss {
+ bootph-pre-ram;
+};
+
+&fss {
+ bootph-pre-ram;
+};
+
+&k3_clks {
+ bootph-pre-ram;
+};
+
+&k3_pds {
+ bootph-pre-ram;
+};
+
+&k3_reset {
+ bootph-pre-ram;
+};
+
+&main_gpio0 {
+ bootph-pre-ram;
+};
+
+/* On-module I2C - PMIC_I2C */
+&main_i2c0 {
+ eeprom_module: eeprom@50 {
+ compatible = "i2c-eeprom";
+ pagesize = <16>;
+ reg = <0x50>;
+ };
+};
+
+/* Verdin I2C_1 */
+&main_i2c1 {
+ /* EEPROM on display adapter (MIPI DSI Display Adapter) */
+ eeprom_display_adapter: eeprom@50 {
+ compatible = "i2c-eeprom";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ /* EEPROM on carrier board */
+ eeprom_carrier_board: eeprom@57 {
+ compatible = "i2c-eeprom";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+&main_pmx0 {
+ bootph-pre-ram;
+};
+
+/* Verdin UART_3, used as the Linux console */
+&main_uart0 {
+ bootph-pre-ram;
+};
+
+/* Verdin UART_1 */
+&main_uart1 {
+ bootph-pre-ram;
+};
+
+&mcu_pmx0 {
+ bootph-pre-ram;
+};
+
+&pinctrl_ctrl_sleep_moci {
+ bootph-pre-ram;
+};
+
+&pinctrl_i2c0 {
+ bootph-pre-ram;
+};
+
+&pinctrl_i2c1 {
+ bootph-pre-ram;
+};
+
+&pinctrl_sdhci0 {
+ bootph-pre-ram;
+};
+
+&pinctrl_uart0 {
+ bootph-pre-ram;
+};
+
+&pinctrl_uart1 {
+ bootph-pre-ram;
+};
+
+&pinctrl_wkup_uart0 {
+ bootph-pre-ram;
+};
+
+&sdhci0 {
+ bootph-pre-ram;
+};
+
+&sdhci2 {
+ status = "disabled";
+};
+
+&secure_proxy_main {
+ bootph-pre-ram;
+};
+
+&verdin_ctrl_sleep_moci {
+ bootph-pre-ram;
+};
+
+&wkup_conf {
+ bootph-pre-ram;
+};
+
+/* Verdin UART_2 */
+&wkup_uart0 {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev.dts b/arch/arm/dts/k3-am625-verdin-wifi-dev.dts
new file mode 100644
index 0000000..4b657d6
--- /dev/null
+++ b/arch/arm/dts/k3-am625-verdin-wifi-dev.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
+ * https://www.toradex.com/products/carrier-board/verdin-development-board-kit
+ */
+
+/dts-v1/;
+
+#include "k3-am625.dtsi"
+#include "k3-am62-verdin.dtsi"
+#include "k3-am62-verdin-wifi.dtsi"
+#include "k3-am62-verdin-dev.dtsi"
+
+/ {
+ model = "Toradex Verdin AM62 WB on Verdin Development Board";
+ compatible = "toradex,verdin-am62-wifi-dev",
+ "toradex,verdin-am62-wifi",
+ "toradex,verdin-am62",
+ "ti,am625";
+};
diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi
index 5e8036f..1664d9f 100644
--- a/arch/arm/dts/k3-am64-main.dtsi
+++ b/arch/arm/dts/k3-am64-main.dtsi
@@ -228,12 +228,161 @@
};
};
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 36 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 36 1>;
+ assigned-clock-parents = <&k3_clks 36 2>;
+ power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 37 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 37 1>;
+ assigned-clock-parents = <&k3_clks 37 2>;
+ power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 38 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 38 1>;
+ assigned-clock-parents = <&k3_clks 38 2>;
+ power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 39 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 39 1>;
+ assigned-clock-parents = <&k3_clks 39 2>;
+ power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 40 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 40 1>;
+ assigned-clock-parents = <&k3_clks 40 2>;
+ power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 41 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 41 1>;
+ assigned-clock-parents = <&k3_clks 41 2>;
+ power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 42 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 42 1>;
+ assigned-clock-parents = <&k3_clks 42 2>;
+ power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 43 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 43 1>;
+ assigned-clock-parents = <&k3_clks 43 2>;
+ power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer8: timer@2480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2480000 0x00 0x400>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 44 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 44 1>;
+ assigned-clock-parents = <&k3_clks 44 2>;
+ power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer9: timer@2490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2490000 0x00 0x400>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 45 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 45 1>;
+ assigned-clock-parents = <&k3_clks 45 2>;
+ power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer10: timer@24a0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24a0000 0x00 0x400>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 46 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 46 1>;
+ assigned-clock-parents = <&k3_clks 46 2>;
+ power-domains = <&k3_pds 46 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer11: timer@24b0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24b0000 0x00 0x400>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 47 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 47 1>;
+ assigned-clock-parents = <&k3_clks 47 2>;
+ power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_esm: esm@420000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x420000 0x00 0x1000>;
+ ti,esm-pins = <160>, <161>;
+ };
+
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 0>;
clock-names = "fclk";
@@ -245,7 +394,6 @@
reg = <0x00 0x02810000 0x00 0x100>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 152 0>;
clock-names = "fclk";
@@ -257,7 +405,6 @@
reg = <0x00 0x02820000 0x00 0x100>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 153 0>;
clock-names = "fclk";
@@ -269,7 +416,6 @@
reg = <0x00 0x02830000 0x00 0x100>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 154 0>;
clock-names = "fclk";
@@ -281,7 +427,6 @@
reg = <0x00 0x02840000 0x00 0x100>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 155 0>;
clock-names = "fclk";
@@ -293,7 +438,6 @@
reg = <0x00 0x02850000 0x00 0x100>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 156 0>;
clock-names = "fclk";
@@ -305,7 +449,6 @@
reg = <0x00 0x02860000 0x00 0x100>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 158 0>;
clock-names = "fclk";
@@ -676,6 +819,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster3: mailbox@29030000 {
@@ -686,6 +830,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster4: mailbox@29040000 {
@@ -696,6 +841,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster5: mailbox@29050000 {
@@ -706,6 +852,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster6: mailbox@29060000 {
@@ -715,6 +862,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster7: mailbox@29070000 {
@@ -724,6 +872,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
main_r5fss0: r5fss@78000000 {
@@ -1392,4 +1541,12 @@
clock-names = "fck";
status = "disabled";
};
+
+ main_vtm0: temperature-sensor@b00000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x00 0xb00000 0x00 0x400>,
+ <0x00 0xb01000 0x00 0x400>;
+ power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm/dts/k3-am64-mcu.dtsi b/arch/arm/dts/k3-am64-mcu.dtsi
index 38ddf0b..686d497 100644
--- a/arch/arm/dts/k3-am64-mcu.dtsi
+++ b/arch/arm/dts/k3-am64-mcu.dtsi
@@ -6,11 +6,55 @@
*/
&cbass_mcu {
+ /*
+ * The MCU domain timer interrupts are routed only to the ESM module,
+ * and not currently available for Linux. The MCU domain timers are
+ * of limited use without interrupts, and likely reserved by the ESM.
+ */
+ mcu_timer0: timer@4800000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4800000 0x00 0x400>;
+ clocks = <&k3_clks 35 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@4810000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4810000 0x00 0x400>;
+ clocks = <&k3_clks 48 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@4820000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4820000 0x00 0x400>;
+ clocks = <&k3_clks 49 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@4830000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4830000 0x00 0x400>;
+ clocks = <&k3_clks 50 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 0>;
clock-names = "fclk";
@@ -21,7 +65,6 @@
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a10000 0x00 0x100>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 160 0>;
clock-names = "fclk";
@@ -109,4 +152,10 @@
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
+
+ mcu_esm: esm@4100000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x4100000 0x00 0x1000>;
+ ti,esm-pins = <0>, <1>;
+ };
};
diff --git a/arch/arm/dts/k3-am64-thermal.dtsi b/arch/arm/dts/k3-am64-thermal.dtsi
new file mode 100644
index 0000000..036db56
--- /dev/null
+++ b/arch/arm/dts/k3-am64-thermal.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ main0_thermal: main0-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&main_vtm0 0>;
+
+ trips {
+ main0_crit: main0-crit {
+ temperature = <105000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main1_thermal: main1-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&main_vtm0 1>;
+
+ trips {
+ main1_crit: main1-crit {
+ temperature = <105000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-am64.dtsi b/arch/arm/dts/k3-am64.dtsi
index c858725..8e9c2bc 100644
--- a/arch/arm/dts/k3-am64.dtsi
+++ b/arch/arm/dts/k3-am64.dtsi
@@ -8,9 +8,10 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
+#include "k3-pinctrl.h"
+
/ {
model = "Texas Instruments K3 AM642 SoC";
compatible = "ti,am642";
@@ -18,22 +19,6 @@
#address-cells = <2>;
#size-cells = <2>;
- aliases {
- serial0 = &mcu_uart0;
- serial1 = &mcu_uart1;
- serial2 = &main_uart0;
- serial3 = &main_uart1;
- serial4 = &main_uart2;
- serial5 = &main_uart3;
- serial6 = &main_uart4;
- serial7 = &main_uart5;
- serial8 = &main_uart6;
- ethernet0 = &cpsw_port1;
- ethernet1 = &cpsw_port2;
- mmc0 = &sdhci0;
- mmc1 = &sdhci1;
- };
-
chosen { };
firmware {
@@ -69,6 +54,7 @@
<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+ <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
<0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
@@ -105,6 +91,8 @@
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
};
};
+
+ #include "k3-am64-thermal.dtsi"
};
/* Now include the peripherals for each bus segments */
diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
index 73577e8..c85f57d 100644
--- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
@@ -7,8 +7,7 @@
/ {
chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
+ tick-timer = &main_timer0;
};
memory@80000000 {
@@ -16,15 +15,21 @@
};
};
-&cbass_main{
+&vtt_supply {
bootph-pre-ram;
- timer1: timer@2400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x2400000 0x0 0x80>;
- ti,timer-alwon;
- clock-frequency = <200000000>;
- bootph-pre-ram;
- };
+};
+
+&cbass_main {
+ bootph-pre-ram;
+};
+
+&cbass_mcu {
+ bootph-pre-ram;
+};
+
+&main_timer0 {
+ bootph-pre-ram;
+ clock-frequency = <200000000>;
};
&main_conf {
@@ -36,23 +41,20 @@
&main_pmx0 {
bootph-pre-ram;
- main_i2c0_pins_default: main-i2c0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
- AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
- >;
- };
+};
+
+&main_i2c0_pins_default {
+ bootph-pre-ram;
};
&main_i2c0 {
- status = "okay";
bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
};
+&main_uart0_pins_default {
+ bootph-pre-ram;
+};
+
&main_uart0 {
bootph-pre-ram;
};
@@ -111,18 +113,7 @@
};
&cpsw3g {
- reg = <0x0 0x8000000 0x0 0x200000>,
- <0x0 0x43000200 0x0 0x8>;
- reg-names = "cpsw_nuss", "mac_efuse";
- /delete-property/ ranges;
- pinctrl-0 = <&mdio1_pins_default /* HACK: as MDIO driver is not DM enabled */
- &rgmii1_pins_default
- &rgmii2_pins_default>;
-
- cpsw-phy-sel@04044 {
- compatible = "ti,am64-phy-gmii-sel";
- reg = <0x0 0x43004044 0x0 0x8>;
- };
+ bootph-pre-ram;
};
&cpsw_port2 {
diff --git a/arch/arm/dts/k3-am642-evm.dts b/arch/arm/dts/k3-am642-evm.dts
index 39feea7..15c282c 100644
--- a/arch/arm/dts/k3-am642-evm.dts
+++ b/arch/arm/dts/k3-am642-evm.dts
@@ -17,15 +17,26 @@
model = "Texas Instruments AM642 EVM";
chosen {
- stdout-path = "serial2:115200n8";
- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ stdout-path = &main_uart0;
};
+ aliases {
+ serial0 = &mcu_uart0;
+ serial1 = &main_uart1;
+ serial2 = &main_uart0;
+ serial3 = &main_uart3;
+ i2c0 = &main_i2c0;
+ i2c1 = &main_i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ ethernet0 = &cpsw_port1;
+ ethernet1 = &cpsw_port2;
+ };
+
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
-
};
reserved-memory {
@@ -94,7 +105,7 @@
};
};
- evm_12v0: fixedregulator-evm12v0 {
+ evm_12v0: regulator-0 {
/* main DC jack */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
@@ -104,7 +115,7 @@
regulator-boot-on;
};
- vsys_5v0: fixedregulator-vsys5v0 {
+ vsys_5v0: regulator-1 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
@@ -115,7 +126,7 @@
regulator-boot-on;
};
- vsys_3v3: fixedregulator-vsys3v3 {
+ vsys_3v3: regulator-2 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
@@ -126,7 +137,7 @@
regulator-boot-on;
};
- vdd_mmc1: fixed-regulator-sd {
+ vdd_mmc1: regulator-3 {
/* TPS2051BD */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
@@ -138,12 +149,26 @@
gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
};
- vddb: fixedregulator-vddb {
+ vddb: regulator-4 {
compatible = "regulator-fixed";
regulator-name = "vddb_3v3_display";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vtt_supply: regulator-5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vtt";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ddr_vtt_pins_default>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
vin-supply = <&vsys_3v3>;
+ enable-active-high;
regulator-always-on;
regulator-boot-on;
};
@@ -201,7 +226,7 @@
};
&main_pmx0 {
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
@@ -215,7 +240,16 @@
>;
};
- main_uart0_pins_default: main-uart0-pins-default {
+ main_uart1_pins_default: main-uart1-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
+ AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
+ AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
+ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
+ >;
+ };
+
+ main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
@@ -224,7 +258,7 @@
>;
};
- main_spi0_pins_default: main-spi0-pins-default {
+ main_spi0_pins_default: main-spi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
@@ -233,21 +267,28 @@
>;
};
- main_i2c1_pins_default: main-i2c1-pins-default {
+ main_i2c0_pins_default: main-i2c0-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
+ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
- mdio1_pins_default: mdio1-pins-default {
+ mdio1_pins_default: mdio1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
>;
};
- rgmii1_pins_default: rgmii1-pins-default {
+ rgmii1_pins_default: rgmii1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
@@ -264,7 +305,7 @@
>;
};
- rgmii2_pins_default: rgmii2-pins-default {
+ rgmii2_pins_default: rgmii2-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
@@ -281,13 +322,13 @@
>;
};
- main_usb0_pins_default: main-usb0-pins-default {
+ main_usb0_pins_default: main-usb0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
- ospi0_pins_default: ospi0-pins-default {
+ ospi0_pins_default: ospi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
@@ -303,38 +344,60 @@
>;
};
- main_ecap0_pins_default: main-ecap0-pins-default {
+ main_ecap0_pins_default: main-ecap0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
>;
};
- main_mcan0_pins_default: main-mcan0-pins-default {
+ main_mcan0_pins_default: main-mcan0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
>;
};
- main_mcan1_pins_default: main-mcan1-pins-default {
+ main_mcan1_pins_default: main-mcan1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
>;
};
+
+ ddr_vtt_pins_default: ddr-vtt-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
+ >;
+ };
};
&main_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
+ current-speed = <115200>;
};
/* main_uart1 is reserved for firmware usage */
&main_uart1 {
status = "reserved";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
};
+&main_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ eeprom@50 {
+ /* AT24CM01 */
+ compatible = "atmel,24c1024";
+ reg = <0x50>;
+ };
+};
+
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
@@ -425,8 +488,7 @@
&cpsw3g {
pinctrl-names = "default";
- pinctrl-0 = <&rgmii1_pins_default
- &rgmii2_pins_default>;
+ pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
};
&cpsw_port1 {
@@ -471,10 +533,53 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x0 0x100000>;
+ };
+
+ partition@100000 {
+ label = "ospi.tispl";
+ reg = <0x100000 0x200000>;
+ };
+
+ partition@300000 {
+ label = "ospi.u-boot";
+ reg = <0x300000 0x400000>;
+ };
+
+ partition@700000 {
+ label = "ospi.env";
+ reg = <0x700000 0x40000>;
+ };
+
+ partition@740000 {
+ label = "ospi.env.backup";
+ reg = <0x740000 0x40000>;
+ };
+
+ partition@800000 {
+ label = "ospi.rootfs";
+ reg = <0x800000 0x37c0000>;
+ };
+
+ partition@3fc0000 {
+ label = "ospi.phypattern";
+ reg = <0x3fc0000 0x40000>;
+ };
+ };
};
};
&mailbox0_cluster2 {
+ status = "okay";
+
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@@ -486,11 +591,9 @@
};
};
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
&mailbox0_cluster4 {
+ status = "okay";
+
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@@ -502,41 +605,35 @@
};
};
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
&mailbox0_cluster6 {
+ status = "okay";
+
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+ mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+ mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts
index b490641..73461f8 100644
--- a/arch/arm/dts/k3-am642-r5-evm.dts
+++ b/arch/arm/dts/k3-am642-r5-evm.dts
@@ -1,34 +1,20 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
-/dts-v1/;
-
-#include "k3-am642.dtsi"
+#include "k3-am642-evm.dts"
#include "k3-am64-evm-ddr4-1600MTs.dtsi"
#include "k3-am64-ddr.dtsi"
-#include "k3-am64x-binman.dtsi"
-/ {
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
+#include "k3-am642-evm-u-boot.dtsi"
+/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
- memory@80000000 {
- device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
-
- bootph-pre-ram;
- };
-
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
@@ -46,34 +32,12 @@
bootph-pre-ram;
};
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
- };
-
clk_200mhz: dummy-clock-200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
bootph-pre-ram;
};
-
- vtt_supply: vtt-supply {
- compatible = "regulator-gpio";
- regulator-name = "vtt";
- regulator-min-microvolt = <0>;
- regulator-max-microvolt = <3300000>;
- gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
- states = <0 0x0 3300000 0x1>;
- bootph-pre-ram;
- };
};
&cbass_main {
@@ -85,131 +49,12 @@
};
};
-&cbass_main {
- main_esm: esm@420000 {
- compatible = "ti,j721e-esm";
- reg = <0x0 0x420000 0x0 0x1000>;
- ti,esm-pins = <160>, <161>;
- bootph-pre-ram;
- };
-};
-
-&cbass_mcu {
+&main_esm {
bootph-pre-ram;
- mcu_esm: esm@4100000 {
- compatible = "ti,j721e-esm";
- reg = <0x0 0x4100000 0x0 0x1000>;
- ti,esm-pins = <0>, <1>;
- bootph-pre-ram;
- };
};
-&main_pmx0 {
+&mcu_esm {
bootph-pre-ram;
- main_uart0_pins_default: main-uart0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
- AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
- AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
- AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
- >;
- };
-
- main_uart1_pins_default: main-uart1-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
- AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
- AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
- AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
- >;
- };
-
- main_mmc0_pins_default: main-mmc0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
- AM64X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
- AM64X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
- AM64X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
- AM64X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
- AM64X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
- AM64X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
- AM64X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
- AM64X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
- AM64X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
- AM64X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
- AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
- AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
- AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
- AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
- AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
- AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
- AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
- >;
- };
-
- ddr_vtt_pins_default: ddr-vtt-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
- >;
- };
-
- main_usb0_pins_default: main-usb0-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
- >;
- };
-
- mdio1_pins_default: mdio1-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
- AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
- >;
- };
-
- rgmii1_pins_default: rgmii1-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
- AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
- AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
- AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
- AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
- AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
- AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
- AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
- AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
- AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
- AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
- AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
- >;
- };
-
- rgmii2_pins_default: rgmii2-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
- AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
- AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
- AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
- AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
- AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
- AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
- AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
- AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
- AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
- AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
- AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
- >;
- };
};
&dmsc {
@@ -221,65 +66,41 @@
ti,secure-host;
};
-&main_uart0 {
- /delete-property/ power-domains;
- /delete-property/ clocks;
- /delete-property/ clock-names;
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- status = "okay";
-};
-
-&main_uart1 {
- bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
-};
-
-&memorycontroller {
- vtt-supply = <&vtt_supply>;
- pinctrl-names = "default";
- pinctrl-0 = <&ddr_vtt_pins_default>;
-};
-
&sdhci0 {
- /delete-property/ power-domains;
clocks = <&clk_200mhz>;
clock-names = "clk_xin";
- ti,driver-strength-ohm = <50>;
- disable-wp;
- pinctrl-0 = <&main_mmc0_pins_default>;
};
&sdhci1 {
- /delete-property/ power-domains;
clocks = <&clk_200mhz>;
clock-names = "clk_xin";
- ti,driver-strength-ohm = <50>;
- disable-wp;
- pinctrl-0 = <&main_mmc1_pins_default>;
};
&main_gpio0 {
bootph-pre-ram;
- /delete-property/ power-domains;
};
-/* EEPROM might be read before SYSFW is available */
-&main_i2c0 {
+/* UART is initialized before SYSFW is started
+ * so we can't do any power-domain/clock operations.
+ * Delete clock/power-domain properties to avoid
+ * UART init failure
+ */
+&main_uart0 {
/delete-property/ power-domains;
-};
-
-&usbss0 {
- ti,vbus-divider;
- ti,usb2-only;
+ /delete-property/ clocks;
+ /delete-property/ clock-names;
};
-&usb0 {
- dr_mode = "otg";
- maximum-speed = "high-speed";
- pinctrl-names = "default";
- pinctrl-0 = <&main_usb0_pins_default>;
+/* timer init is called as part of rproc_start() while
+ * starting System Firmware, so any clock/power-domain
+ * operations will fail as SYSFW is not yet up and running.
+ * Delete all clock/power-domain properties to avoid
+ * timer init failure.
+ * This is an always on timer at 20MHz.
+ */
+&main_timer0 {
+ /delete-property/ clocks;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ power-domains;
};
-
-#include "k3-am642-evm-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts
index 32d4c31..def4622 100644
--- a/arch/arm/dts/k3-am642-r5-sk.dts
+++ b/arch/arm/dts/k3-am642-r5-sk.dts
@@ -3,33 +3,18 @@
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
-/dts-v1/;
-
-#include <dt-bindings/mux/ti-serdes.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include "k3-am642.dtsi"
+#include "k3-am642-sk.dts"
#include "k3-am64-sk-lp4-1600MTs.dtsi"
#include "k3-am64-ddr.dtsi"
-/ {
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
+#include "k3-am642-sk-u-boot.dtsi"
+/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
- memory@80000000 {
- device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
- bootph-pre-ram;
- };
-
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
@@ -47,18 +32,6 @@
bootph-pre-ram;
};
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
- };
-
clk_200mhz: dummy-clock-200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -76,108 +49,12 @@
};
};
-&cbass_main {
- main_esm: esm@420000 {
- compatible = "ti,j721e-esm";
- reg = <0x0 0x420000 0x0 0x1000>;
- ti,esm-pins = <160>, <161>;
- bootph-pre-ram;
- };
-};
-
-&cbass_mcu {
+&main_esm {
bootph-pre-ram;
- mcu_esm: esm@4100000 {
- compatible = "ti,j721e-esm";
- reg = <0x0 0x4100000 0x0 0x1000>;
- ti,esm-pins = <0>, <1>;
- bootph-pre-ram;
- };
};
-&main_pmx0 {
+&mcu_esm {
bootph-pre-ram;
- main_uart0_pins_default: main-uart0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
- AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
- AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
- AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
- >;
- };
-
- main_uart1_pins_default: main-uart1-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
- AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
- AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
- AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
- AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
- AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
- AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
- AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
- AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
- AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
- AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
- >;
- };
-
- main_usb0_pins_default: main-usb0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
- >;
- };
-
- mdio1_pins_default: mdio1-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
- AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
- >;
- };
-
- rgmii1_pins_default: rgmii1-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
- AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
- AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
- AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
- AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
- AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
- AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
- AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
- AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
- AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
- AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
- AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
- >;
- };
-
- rgmii2_pins_default: rgmii2-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
- AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
- AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
- AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
- AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
- AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
- AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
- AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
- AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
- AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
- AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
- AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
- >;
- };
};
&dmsc {
@@ -189,79 +66,36 @@
ti,secure-host;
};
-&main_uart0 {
- /delete-property/ power-domains;
- /delete-property/ clocks;
- /delete-property/ clock-names;
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- status = "okay";
-};
-
-&main_uart1 {
- bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
-};
-
&sdhci1 {
- /delete-property/ power-domains;
clocks = <&clk_200mhz>;
clock-names = "clk_xin";
- ti,driver-strength-ohm = <50>;
- disable-wp;
- pinctrl-0 = <&main_mmc1_pins_default>;
};
-&serdes_ln_ctrl {
- idle-states = <AM64_SERDES0_LANE0_USB>;
-};
-
&serdes_wiz0 {
status = "okay";
};
-&serdes0 {
- serdes0_usb_link: link@0 {
- reg = <0>;
- cdns,num-lanes = <1>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_USB3>;
- resets = <&serdes_wiz0 1>;
- };
-};
-
-&usbss0 {
- ti,vbus-divider;
-};
-
-&usb0 {
- dr_mode = "host";
- maximum-speed = "super-speed";
- pinctrl-names = "default";
- pinctrl-0 = <&main_usb0_pins_default>;
- phys = <&serdes0_usb_link>;
- phy-names = "cdns3,usb3-phy";
-};
-
-&cpsw3g {
- pinctrl-names = "default";
- pinctrl-0 = <&mdio1_pins_default
- &rgmii1_pins_default
- &rgmii2_pins_default>;
-};
-
-&cpsw_port2 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy1>;
+/* UART is initialized before SYSFW is started
+ * so we can't do any power-domain/clock operations.
+ * Delete clock/power-domain properties to avoid
+ * UART init failure
+ */
+&main_uart0 {
+ /delete-property/ power-domains;
+ /delete-property/ clocks;
+ /delete-property/ clock-names;
};
-&cpsw3g_mdio {
- cpsw3g_phy1: ethernet-phy@1 {
- reg = <1>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
+/* timer init is called as part of rproc_start() while
+ * starting System Firmware, so any clock/power-domain
+ * operations will fail as SYSFW is not yet up and running.
+ * Delete all clock/power-domain properties to avoid
+ * timer init failure.
+ * This is an always on timer at 20MHz.
+ */
+&main_timer0 {
+ /delete-property/ clocks;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ power-domains;
};
-
-#include "k3-am642-sk-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
index 3d6be02..c277ef8 100644
--- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
@@ -7,14 +7,9 @@
/ {
chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
+ tick-timer = &main_timer0;
};
- aliases {
- mmc1 = &sdhci1;
- };
-
memory@80000000 {
bootph-pre-ram;
};
@@ -22,15 +17,17 @@
&cbass_main{
bootph-pre-ram;
- timer1: timer@2400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x2400000 0x0 0x80>;
- ti,timer-alwon;
- clock-frequency = <200000000>;
- bootph-pre-ram;
- };
+};
+
+&cbass_mcu {
+ bootph-pre-ram;
};
+&main_timer0 {
+ bootph-pre-ram;
+ clock-frequency = <200000000>;
+};
+
&main_conf {
bootph-pre-ram;
chipid@14 {
@@ -40,81 +37,18 @@
&main_pmx0 {
bootph-pre-ram;
- main_i2c0_pins_default: main-i2c0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
- AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
- >;
- };
};
-&main_i2c0 {
+&main_i2c0_pins_default {
bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- tps65219: pmic@30 {
- compatible = "ti,tps65219";
- reg = <0x30>;
-
- regulators {
- buck1_reg: buck1 {
- regulator-name = "VDD_CORE";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck2_reg: buck2 {
- regulator-name = "VCC1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck3_reg: buck3 {
- regulator-name = "VDD_LPDDR4";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1_reg: ldo1 {
- regulator-name = "VDDSHV_SD_IO_PMIC";
- regulator-min-microvolt = <33000000>;
- regulator-max-microvolt = <33000000>;
- };
-
- ldo2_reg: ldo2 {
- regulator-name = "VDDAR_CORE";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-boot-on;
- regulator-always-on;
- };
+};
- ldo3_reg: ldo3 {
- regulator-name = "VDDA_1V8";
- regulator-min-microvolt = <18000000>;
- regulator-max-microvolt = <18000000>;
- regulator-boot-on;
- regulator-always-on;
- };
+&main_i2c0 {
+ bootph-pre-ram;
+};
- ldo4_reg: ldo4 {
- regulator-name = "VDD_PHY_2V5";
- regulator-min-microvolt = <25000000>;
- regulator-max-microvolt = <25000000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
+&main_uart0_pins_default {
+ bootph-pre-ram;
};
&main_uart0 {
@@ -163,18 +97,8 @@
};
&cpsw3g {
- reg = <0x0 0x8000000 0x0 0x200000>,
- <0x0 0x43000200 0x0 0x8>;
- reg-names = "cpsw_nuss", "mac_efuse";
- /delete-property/ ranges;
bootph-pre-ram;
- cpsw-phy-sel@04044 {
- compatible = "ti,am64-phy-gmii-sel";
- reg = <0x0 0x43004044 0x0 0x8>;
- bootph-pre-ram;
- };
-
ethernet-ports {
bootph-pre-ram;
};
@@ -221,7 +145,6 @@
};
&usb0 {
- dr_mode = "host";
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-am642-sk.dts b/arch/arm/dts/k3-am642-sk.dts
index 2e2d40d..cbce43d 100644
--- a/arch/arm/dts/k3-am642-sk.dts
+++ b/arch/arm/dts/k3-am642-sk.dts
@@ -17,15 +17,25 @@
model = "Texas Instruments AM642 SK";
chosen {
- stdout-path = "serial2:115200n8";
- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ stdout-path = &main_uart0;
};
+ aliases {
+ serial0 = &mcu_uart0;
+ serial1 = &main_uart1;
+ serial2 = &main_uart0;
+ i2c0 = &main_i2c0;
+ i2c1 = &main_i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ ethernet0 = &cpsw_port1;
+ ethernet1 = &cpsw_port2;
+ };
+
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
-
};
reserved-memory {
@@ -94,7 +104,7 @@
};
};
- vusb_main: fixed-regulator-vusb-main5v0 {
+ vusb_main: regulator-0 {
/* USB MAIN INPUT 5V DC */
compatible = "regulator-fixed";
regulator-name = "vusb_main5v0";
@@ -104,7 +114,7 @@
regulator-boot-on;
};
- vcc_3v3_sys: fixedregulator-vcc-3v3-sys {
+ vcc_3v3_sys: regulator-1 {
/* output of LP8733xx */
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
@@ -115,7 +125,7 @@
regulator-boot-on;
};
- vdd_mmc1: fixed-regulator-sd {
+ vdd_mmc1: regulator-2 {
/* TPS2051BD */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
@@ -127,7 +137,7 @@
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
};
- com8_ls_en: regulator-1 {
+ com8_ls_en: regulator-3 {
compatible = "regulator-fixed";
regulator-name = "com8_ls_en";
regulator-min-microvolt = <3300000>;
@@ -139,7 +149,7 @@
gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>;
};
- wlan_en: regulator-2 {
+ wlan_en: regulator-4 {
/* output of SN74AVC4T245RSVR */
compatible = "regulator-fixed";
regulator-name = "wlan_en";
@@ -222,20 +232,21 @@
};
&main_pmx0 {
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
- AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
+ AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
+ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
+ AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
- AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
- AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
- AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
- AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
- AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
- AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
+ AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
+ AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
+ AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
+ AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
+ AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
>;
};
- main_uart0_pins_default: main-uart0-pins-default {
+ main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
@@ -244,27 +255,43 @@
>;
};
- main_usb0_pins_default: main-usb0-pins-default {
+ main_uart1_pins_default: main-uart1-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
+ AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
+ AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
+ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
+ >;
+ };
+
+ main_usb0_pins_default: main-usb0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
+ main_i2c0_pins_default: main-i2c0-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
+ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
+ >;
+ };
+
- main_i2c1_pins_default: main-i2c1-pins-default {
+ main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
- mdio1_pins_default: mdio1-pins-default {
+ mdio1_pins_default: mdio1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
>;
};
- rgmii1_pins_default: rgmii1-pins-default {
+ rgmii1_pins_default: rgmii1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
@@ -281,7 +308,7 @@
>;
};
- rgmii2_pins_default: rgmii2-pins-default {
+ rgmii2_pins_default: rgmii2-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
@@ -298,7 +325,7 @@
>;
};
- ospi0_pins_default: ospi0-pins-default {
+ ospi0_pins_default: ospi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
@@ -314,24 +341,24 @@
>;
};
- main_ecap0_pins_default: main-ecap0-pins-default {
+ main_ecap0_pins_default: main-ecap0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
>;
};
- main_wlan_en_pins_default: main-wlan-en-pins-default {
+ main_wlan_en_pins_default: main-wlan-en-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */
>;
};
- main_com8_ls_en_pins_default: main-com8-ls-en-pins-default {
+ main_com8_ls_en_pins_default: main-com8-ls-en-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */
>;
};
- main_wlan_pins_default: main-wlan-pins-default {
+ main_wlan_pins_default: main-wlan-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */
>;
@@ -342,13 +369,28 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
+ current-speed = <115200>;
};
&main_uart1 {
/* main_uart1 is reserved for firmware usage */
status = "reserved";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
};
+&main_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ eeprom@51 {
+ compatible = "atmel,24c512";
+ reg = <0x51>;
+ };
+};
+
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
@@ -439,8 +481,7 @@
&cpsw3g {
pinctrl-names = "default";
- pinctrl-0 = <&rgmii1_pins_default
- &rgmii2_pins_default>;
+ pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
};
&cpsw_port1 {
@@ -490,10 +531,53 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x0 0x100000>;
+ };
+
+ partition@100000 {
+ label = "ospi.tispl";
+ reg = <0x100000 0x200000>;
+ };
+
+ partition@300000 {
+ label = "ospi.u-boot";
+ reg = <0x300000 0x400000>;
+ };
+
+ partition@700000 {
+ label = "ospi.env";
+ reg = <0x700000 0x40000>;
+ };
+
+ partition@740000 {
+ label = "ospi.env.backup";
+ reg = <0x740000 0x40000>;
+ };
+
+ partition@800000 {
+ label = "ospi.rootfs";
+ reg = <0x800000 0x37c0000>;
+ };
+
+ partition@3fc0000 {
+ label = "ospi.phypattern";
+ reg = <0x3fc0000 0x40000>;
+ };
+ };
};
};
&mailbox0_cluster2 {
+ status = "okay";
+
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@@ -505,11 +589,9 @@
};
};
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
&mailbox0_cluster4 {
+ status = "okay";
+
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@@ -521,41 +603,35 @@
};
};
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
&mailbox0_cluster6 {
+ status = "okay";
+
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+ mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+ mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
diff --git a/arch/arm/dts/k3-am642.dtsi b/arch/arm/dts/k3-am642.dtsi
index 8a76f48..7a6eede 100644
--- a/arch/arm/dts/k3-am642.dtsi
+++ b/arch/arm/dts/k3-am642.dtsi
@@ -58,6 +58,7 @@
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <256>;
diff --git a/arch/arm/dts/k3-binman.dtsi b/arch/arm/dts/k3-binman.dtsi
index 2a67ceb..2ea2dd1 100644
--- a/arch/arm/dts/k3-binman.dtsi
+++ b/arch/arm/dts/k3-binman.dtsi
@@ -12,14 +12,14 @@
&binman {
custMpk {
filename = "custMpk.pem";
- blob-ext {
+ custmpk_pem: blob-ext {
filename = "../keys/custMpk.pem";
};
};
ti-degenerate-key {
filename = "ti-degenerate-key.pem";
- blob-ext {
+ dkey_pem: blob-ext {
filename = "../keys/ti-degenerate-key.pem";
};
};
@@ -37,14 +37,14 @@
};
pm-cfg {
filename = "pm-cfg.bin";
- rcfg_yaml: ti-board-config {
+ pcfg_yaml: ti-board-config {
config = "pm-cfg.yaml";
schema = "../common/schema.yaml";
};
};
rm-cfg {
filename = "rm-cfg.bin";
- pcfg_yaml: ti-board-config {
+ rcfg_yaml: ti-board-config {
config = "rm-cfg.yaml";
schema = "../common/schema.yaml";
};
@@ -93,19 +93,19 @@
combined-sysfw-cfg {
filename = "combined-sysfw-cfg.bin";
ti-board-config {
- board-cfg {
+ bcfg_yaml_sysfw: board-cfg {
config = "board-cfg.yaml";
schema = "../common/schema.yaml";
};
- sec-cfg {
+ scfg_yaml_sysfw: sec-cfg {
config = "sec-cfg.yaml";
schema = "../common/schema.yaml";
};
- pm-cfg {
+ pcfg_yaml_sysfw: pm-cfg {
config = "pm-cfg.yaml";
schema = "../common/schema.yaml";
};
- rm-cfg {
+ rcfg_yaml_sysfw: rm-cfg {
config = "rm-cfg.yaml";
schema = "../common/schema.yaml";
};
diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
index 7c55744..717baf2 100644
--- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
@@ -224,12 +224,12 @@
ð {
status = "okay";
mediatek,gmac-id = <0>;
- phy-mode = "sgmii";
+ phy-mode = "2500base-x";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
fixed-link {
- speed = <1000>;
+ speed = <2500>;
full-duplex;
};
};
diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts
index 886a133..321de75 100644
--- a/arch/arm/dts/mt7622-rfb.dts
+++ b/arch/arm/dts/mt7622-rfb.dts
@@ -233,12 +233,12 @@
ð {
status = "okay";
mediatek,gmac-id = <0>;
- phy-mode = "sgmii";
+ phy-mode = "2500base-x";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
fixed-link {
- speed = <1000>;
+ speed = <2500>;
full-duplex;
};
};
diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts
index 82f6a34..f347725 100644
--- a/arch/arm/dts/mt7629-rfb.dts
+++ b/arch/arm/dts/mt7629-rfb.dts
@@ -25,12 +25,12 @@
ð {
status = "okay";
mediatek,gmac-id = <0>;
- phy-mode = "sgmii";
+ phy-mode = "2500base-x";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
fixed-link {
- speed = <1000>;
+ speed = <2500>;
full-duplex;
};
};
diff --git a/arch/arm/dts/mt7981-emmc-rfb.dts b/arch/arm/dts/mt7981-emmc-rfb.dts
index 2b7eae9..9aa7cd8 100644
--- a/arch/arm/dts/mt7981-emmc-rfb.dts
+++ b/arch/arm/dts/mt7981-emmc-rfb.dts
@@ -18,6 +18,11 @@
tick-timer = &timer0;
};
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x10000000>;
+ };
+
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
@@ -41,12 +46,12 @@
ð {
status = "okay";
mediatek,gmac-id = <0>;
- phy-mode = "sgmii";
+ phy-mode = "2500base-x";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
fixed-link {
- speed = <1000>;
+ speed = <2500>;
full-duplex;
};
};
diff --git a/arch/arm/dts/mt7981-rfb.dts b/arch/arm/dts/mt7981-rfb.dts
index 5559ace..22a022a 100644
--- a/arch/arm/dts/mt7981-rfb.dts
+++ b/arch/arm/dts/mt7981-rfb.dts
@@ -17,6 +17,11 @@
stdout-path = &uart0;
tick-timer = &timer0;
};
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x10000000>;
+ };
};
&uart0 {
@@ -32,12 +37,12 @@
ð {
status = "okay";
mediatek,gmac-id = <0>;
- phy-mode = "sgmii";
+ phy-mode = "2500base-x";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
fixed-link {
- speed = <1000>;
+ speed = <2500>;
full-duplex;
};
};
diff --git a/arch/arm/dts/mt7981-sd-rfb.dts b/arch/arm/dts/mt7981-sd-rfb.dts
index 34ac227..7d70808 100644
--- a/arch/arm/dts/mt7981-sd-rfb.dts
+++ b/arch/arm/dts/mt7981-sd-rfb.dts
@@ -18,6 +18,11 @@
tick-timer = &timer0;
};
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x10000000>;
+ };
+
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
@@ -41,12 +46,12 @@
ð {
status = "okay";
mediatek,gmac-id = <0>;
- phy-mode = "sgmii";
+ phy-mode = "2500base-x";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
fixed-link {
- speed = <1000>;
+ speed = <2500>;
full-duplex;
};
};
diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi
index 2c8ef14..7aaa777 100644
--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
@@ -152,6 +152,20 @@
status = "disabled";
};
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt7981-i2c";
+ reg = <0x11007000 0x1000>,
+ <0x10217080 0x80>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ clock-div = <1>;
+ clocks = <&infracfg_ao CK_INFRA_I2CO_CK>,
+ <&infracfg_ao CK_INFRA_AP_DMA_CK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,hsuart";
reg = <0x11002000 0x400>;
@@ -223,6 +237,7 @@
reset-names = "fe";
mediatek,ethsys = <ðsys>;
mediatek,sgmiisys = <&sgmiisys0>;
+ mediatek,infracfg = <&topmisc>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -241,6 +256,12 @@
#clock-cells = <1>;
};
+ topmisc: topmisc@11d10000 {
+ compatible = "mediatek,mt7981-topmisc", "syscon";
+ reg = <0x11d10000 0x10000>;
+ #clock-cells = <1>;
+ };
+
spi0: spi@1100a000 {
compatible = "mediatek,ipm-spi";
reg = <0x1100a000 0x100>;
diff --git a/arch/arm/dts/mt7986a-bpi-r3-sd.dts b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
index 4d12440..c156a81 100644
--- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts
+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
@@ -19,6 +19,11 @@
tick-timer = &timer0;
};
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x80000000>;
+ };
+
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
@@ -71,12 +76,12 @@
ð {
status = "okay";
mediatek,gmac-id = <0>;
- phy-mode = "sgmii";
+ phy-mode = "2500base-x";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
fixed-link {
- speed = <1000>;
+ speed = <2500>;
full-duplex;
};
};
diff --git a/arch/arm/dts/mt7986a-rfb.dts b/arch/arm/dts/mt7986a-rfb.dts
index 80def57..e5c9be7 100644
--- a/arch/arm/dts/mt7986a-rfb.dts
+++ b/arch/arm/dts/mt7986a-rfb.dts
@@ -18,6 +18,11 @@
tick-timer = &timer0;
};
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x10000000>;
+ };
+
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
@@ -50,12 +55,12 @@
ð {
status = "okay";
mediatek,gmac-id = <0>;
- phy-mode = "sgmii";
+ phy-mode = "2500base-x";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
fixed-link {
- speed = <1000>;
+ speed = <2500>;
full-duplex;
};
};
diff --git a/arch/arm/dts/mt7986a-sd-rfb.dts b/arch/arm/dts/mt7986a-sd-rfb.dts
index 5807c5d..4f8fa70 100644
--- a/arch/arm/dts/mt7986a-sd-rfb.dts
+++ b/arch/arm/dts/mt7986a-sd-rfb.dts
@@ -19,6 +19,11 @@
tick-timer = &timer0;
};
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x10000000>;
+ };
+
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
@@ -42,12 +47,12 @@
ð {
status = "okay";
mediatek,gmac-id = <0>;
- phy-mode = "sgmii";
+ phy-mode = "2500base-x";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
fixed-link {
- speed = <1000>;
+ speed = <2500>;
full-duplex;
};
};
diff --git a/arch/arm/dts/mt7986b-rfb.dts b/arch/arm/dts/mt7986b-rfb.dts
index 0c4e3e8..8196845 100644
--- a/arch/arm/dts/mt7986b-rfb.dts
+++ b/arch/arm/dts/mt7986b-rfb.dts
@@ -18,6 +18,11 @@
tick-timer = &timer0;
};
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x10000000>;
+ };
+
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
@@ -41,12 +46,12 @@
ð {
status = "okay";
mediatek,gmac-id = <0>;
- phy-mode = "sgmii";
+ phy-mode = "2500base-x";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
fixed-link {
- speed = <1000>;
+ speed = <2500>;
full-duplex;
};
};
diff --git a/arch/arm/dts/mt7986b-sd-rfb.dts b/arch/arm/dts/mt7986b-sd-rfb.dts
index 48f9320..ec80a2f 100644
--- a/arch/arm/dts/mt7986b-sd-rfb.dts
+++ b/arch/arm/dts/mt7986b-sd-rfb.dts
@@ -19,6 +19,11 @@
tick-timer = &timer0;
};
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x10000000>;
+ };
+
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
@@ -42,12 +47,12 @@
ð {
status = "okay";
mediatek,gmac-id = <0>;
- phy-mode = "sgmii";
+ phy-mode = "2500base-x";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
fixed-link {
- speed = <1000>;
+ speed = <2500>;
full-duplex;
};
};
diff --git a/arch/arm/dts/mt7988-rfb.dts b/arch/arm/dts/mt7988-rfb.dts
new file mode 100644
index 0000000..2c11428
--- /dev/null
+++ b/arch/arm/dts/mt7988-rfb.dts
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "mt7988-rfb";
+ compatible = "mediatek,mt7988-rfb";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x10000000>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "okay";
+};
+
+ð {
+ status = "okay";
+ mediatek,gmac-id = <0>;
+ phy-mode = "usxgmii";
+ mediatek,switch = "mt7988";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+};
+
+&pinctrl {
+ i2c1_pins: i2c1-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c1_0";
+ };
+ };
+
+ pwm_pins: pwm-pins {
+ mux {
+ function = "pwm";
+ groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
+ "pwm5", "pwm6", "pwm7";
+ };
+ };
+
+ spi0_pins: spi0-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ };
+
+ spi2_pins: spi2-pins {
+ mux {
+ function = "spi";
+ groups = "spi2", "spi2_wp_hold";
+ };
+ };
+
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "flash";
+ groups = "emmc_51";
+ };
+
+ conf-cmd-dat {
+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+ input-enable;
+ };
+
+ conf-clk {
+ pins = "EMMC_CK";
+ };
+
+ conf-dsl {
+ pins = "EMMC_DSL";
+ };
+
+ conf-rst {
+ pins = "EMMC_RSTB";
+ };
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ must_tx;
+ enhance_timing;
+ dma_ext;
+ ipm_design;
+ support_quad;
+ tick_dly = <2>;
+ sample_sel = <0>;
+
+ spi_nand@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+ };
+};
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ must_tx;
+ enhance_timing;
+ dma_ext;
+ ipm_design;
+ support_quad;
+ tick_dly = <2>;
+ sample_sel = <0>;
+
+ spi_nor@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_default>;
+ max-frequency = <52000000>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ non-removable;
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt7988-sd-rfb.dts b/arch/arm/dts/mt7988-sd-rfb.dts
new file mode 100644
index 0000000..a3df37d
--- /dev/null
+++ b/arch/arm/dts/mt7988-sd-rfb.dts
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "mt7988-rfb";
+ compatible = "mediatek,mt7988-rfb", "mediatek,mt7988-sd-rfb";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x10000000>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "okay";
+};
+
+ð {
+ status = "okay";
+ mediatek,gmac-id = <0>;
+ phy-mode = "usxgmii";
+ mediatek,switch = "mt7988";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+};
+
+&pinctrl {
+ i2c1_pins: i2c1-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c1_0";
+ };
+ };
+
+ pwm_pins: pwm-pins {
+ mux {
+ function = "pwm";
+ groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
+ "pwm5", "pwm6", "pwm7";
+ };
+ };
+
+ spi0_pins: spi0-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ };
+
+ mmc1_pins_default: mmc1default {
+ mux {
+ function = "flash";
+ groups = "emmc_45";
+ };
+
+ conf-cmd-dat {
+ pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI",
+ "SPI2_CLK", "SPI2_HOLD";
+ input-enable;
+ };
+
+ conf-clk {
+ pins = "SPI2_WP";
+ };
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ must_tx;
+ enhance_timing;
+ dma_ext;
+ ipm_design;
+ support_quad;
+ tick_dly = <2>;
+ sample_sel = <0>;
+
+ spi_nand@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_default>;
+ max-frequency = <52000000>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_3p3v>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt7988-u-boot.dtsi b/arch/arm/dts/mt7988-u-boot.dtsi
new file mode 100644
index 0000000..43e00a3
--- /dev/null
+++ b/arch/arm/dts/mt7988-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+&system_clk {
+ bootph-all;
+};
+
+&spi_clk {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&uart1 {
+ bootph-all;
+};
+
+&uart2 {
+ bootph-all;
+};
diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi
new file mode 100644
index 0000000..ac476d5
--- /dev/null
+++ b/arch/arm/dts/mt7988.dtsi
@@ -0,0 +1,451 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt7988-clk.h>
+#include <dt-bindings/reset/mt7988-reset.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ compatible = "mediatek,mt7988-rfb";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x0>;
+ mediatek,hwver = <&hwver>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x1>;
+ mediatek,hwver = <&hwver>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x2>;
+ mediatek,hwver = <&hwver>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x3>;
+ mediatek,hwver = <&hwver>;
+ };
+ };
+
+ system_clk: dummy40m {
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ #clock-cells = <0>;
+ };
+
+ spi_clk: dummy208m {
+ compatible = "fixed-clock";
+ clock-frequency = <208000000>;
+ #clock-cells = <0>;
+ };
+
+ hwver: hwver {
+ compatible = "mediatek,hwver", "syscon";
+ reg = <0 0x8000000 0 0x1000>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ clock-frequency = <13000000>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ watchdog: watchdog@1001c000 {
+ compatible = "mediatek,mt7622-wdt",
+ "mediatek,mt6589-wdt",
+ "syscon";
+ reg = <0 0x1001c000 0 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ };
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>, /* GICD */
+ <0 0x0c080000 0 0x200000>; /* GICR */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ infracfg_ao_cgs: infracfg_ao_cgs@10001000 {
+ compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ clock-parent = <&infracfg_ao>;
+ #clock-cells = <1>;
+ };
+
+ apmixedsys: apmixedsys@1001e000 {
+ compatible = "mediatek,mt7988-fixed-plls", "syscon";
+ reg = <0 0x1001e000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ topckgen: topckgen@1001b000 {
+ compatible = "mediatek,mt7988-topckgen", "syscon";
+ reg = <0 0x1001b000 0 0x1000>;
+ clock-parent = <&apmixedsys>;
+ #clock-cells = <1>;
+ };
+
+ pinctrl: pinctrl@1001f000 {
+ compatible = "mediatek,mt7988-pinctrl";
+ reg = <0 0x1001f000 0 0x1000>,
+ <0 0x11c10000 0 0x1000>,
+ <0 0x11d00000 0 0x1000>,
+ <0 0x11d20000 0 0x1000>,
+ <0 0x11e00000 0 0x1000>,
+ <0 0x11f00000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base",
+ "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
+ "eint";
+ gpio: gpio-controller {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ sgmiisys0: syscon@10060000 {
+ compatible = "mediatek,mt7988-sgmiisys_0", "syscon";
+ reg = <0 0x10060000 0 0x1000>;
+ clock-parent = <&topckgen>;
+ #clock-cells = <1>;
+ };
+
+ sgmiisys1: syscon@10070000 {
+ compatible = "mediatek,mt7988-sgmiisys_1", "syscon";
+ reg = <0 0x10070000 0 0x1000>;
+ clock-parent = <&topckgen>;
+ #clock-cells = <1>;
+ };
+
+ usxgmiisys0: syscon@10080000 {
+ compatible = "mediatek,mt7988-usxgmiisys_0", "syscon";
+ reg = <0 0x10080000 0 0x1000>;
+ clock-parent = <&topckgen>;
+ #clock-cells = <1>;
+ };
+
+ usxgmiisys1: syscon@10081000 {
+ compatible = "mediatek,mt7988-usxgmiisys_1", "syscon";
+ reg = <0 0x10081000 0 0x1000>;
+ clock-parent = <&topckgen>;
+ #clock-cells = <1>;
+ };
+
+ dummy_clk: dummy12m {
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ #clock-cells = <0>;
+ /* must need this line, or uart uanable to get dummy_clk */
+ bootph-all;
+ };
+
+ xhci1: xhci@11200000 {
+ compatible = "mediatek,mt7988-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x2e00>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&tphyu2port0 PHY_TYPE_USB2>,
+ <&tphyu3port0 PHY_TYPE_USB3>;
+ clocks = <&dummy_clk>,
+ <&dummy_clk>,
+ <&dummy_clk>,
+ <&dummy_clk>,
+ <&dummy_clk>;
+ clock-names = "sys_ck",
+ "xhci_ck",
+ "ref_ck",
+ "mcu_ck",
+ "dma_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "okay";
+ };
+
+ usbtphy: usb-phy@11c50000 {
+ compatible = "mediatek,mt7988",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "okay";
+
+ tphyu2port0: usb-phy@11c50000 {
+ reg = <0 0x11c50000 0 0x700>;
+ clocks = <&dummy_clk>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ tphyu3port0: usb-phy@11c50700 {
+ reg = <0 0x11c50700 0 0x900>;
+ clocks = <&dummy_clk>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ mediatek,usb3-pll-ssc-delta;
+ mediatek,usb3-pll-ssc-delta1;
+ status = "okay";
+ };
+ };
+
+ xfi_pextp0: syscon@11f20000 {
+ compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
+ reg = <0 0x11f20000 0 0x10000>;
+ clock-parent = <&topckgen>;
+ #clock-cells = <1>;
+ };
+
+ xfi_pextp1: syscon@11f30000 {
+ compatible = "mediatek,mt7988-xfi_pextp_1", "syscon";
+ reg = <0 0x11f30000 0 0x10000>;
+ clock-parent = <&topckgen>;
+ #clock-cells = <1>;
+ };
+
+ xfi_pll: syscon@11f40000 {
+ compatible = "mediatek,mt7988-xfi_pll", "syscon";
+ reg = <0 0x11f40000 0 0x1000>;
+ clock-parent = <&topckgen>;
+ #clock-cells = <1>;
+ };
+
+ topmisc: topmisc@11d10000 {
+ compatible = "mediatek,mt7988-topmisc", "syscon",
+ "mediatek,mt7988-power-controller";
+ reg = <0 0x11d10000 0 0x10000>;
+ clock-parent = <&topckgen>;
+ #clock-cells = <1>;
+ };
+
+ infracfg_ao: infracfg@10001000 {
+ compatible = "mediatek,mt7988-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ clock-parent = <&topckgen>;
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@11000000 {
+ compatible = "mediatek,hsuart";
+ reg = <0 0x11000000 0 0x100>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>;
+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+ <&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+ <&infracfg_ao CK_INFRA_UART_O0>;
+ status = "disabled";
+ };
+
+ uart1: serial@11000100 {
+ compatible = "mediatek,hsuart";
+ reg = <0 0x11000100 0 0x100>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>;
+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+ <&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+ <&infracfg_ao CK_INFRA_UART_O1>;
+ status = "disabled";
+ };
+
+ uart2: serial@11000200 {
+ compatible = "mediatek,hsuart";
+ reg = <0 0x11000200 0 0x100>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>;
+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+ <&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+ <&infracfg_ao CK_INFRA_UART_O2>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@11003000 {
+ compatible = "mediatek,mt7988-i2c",
+ "mediatek,mt7981-i2c";
+ reg = <0 0x11003000 0 0x1000>,
+ <0 0x10217080 0 0x80>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ clock-div = <1>;
+ clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
+ <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11004000 {
+ compatible = "mediatek,mt7988-i2c",
+ "mediatek,mt7981-i2c";
+ reg = <0 0x11004000 0 0x1000>,
+ <0 0x10217100 0 0x80>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clock-div = <1>;
+ clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
+ <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11005000 {
+ compatible = "mediatek,mt7988-i2c",
+ "mediatek,mt7981-i2c";
+ reg = <0 0x11005000 0 0x1000>,
+ <0 0x10217180 0 0x80>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clock-div = <1>;
+ clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
+ <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pwm: pwm@10048000 {
+ compatible = "mediatek,mt7988-pwm";
+ reg = <0 0x10048000 0 0x1000>;
+ #pwm-cells = <2>;
+ clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
+ <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
+ <&infracfg_ao CK_INFRA_66M_PWM_CK1>,
+ <&infracfg_ao CK_INFRA_66M_PWM_CK2>,
+ <&infracfg_ao CK_INFRA_66M_PWM_CK3>,
+ <&infracfg_ao CK_INFRA_66M_PWM_CK4>,
+ <&infracfg_ao CK_INFRA_66M_PWM_CK5>,
+ <&infracfg_ao CK_INFRA_66M_PWM_CK6>,
+ <&infracfg_ao CK_INFRA_66M_PWM_CK7>,
+ <&infracfg_ao CK_INFRA_66M_PWM_CK8>;
+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
+ "pwm4","pwm5","pwm6","pwm7","pwm8";
+ status = "disabled";
+ };
+
+ snand: snand@11001000 {
+ compatible = "mediatek,mt7988-snand",
+ "mediatek,mt7986-snand";
+ reg = <0 0x11001000 0 0x1000>,
+ <0 0x11002000 0 0x1000>;
+ reg-names = "nfi", "ecc";
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg_ao CK_INFRA_SPINFI>,
+ <&infracfg_ao CK_INFRA_NFI>,
+ <&infracfg_ao CK_INFRA_66M_NFI_HCK>;
+ clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
+ assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
+ <&topckgen CK_TOP_NFI1X_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
+ <&topckgen CK_TOP_CB_M_D8>;
+ status = "disabled";
+ };
+
+ spi0: spi@1100a000 {
+ compatible = "mediatek,ipm-spi";
+ reg = <0 0x11007000 0 0x100>;
+ clocks = <&spi_clk>,
+ <&spi_clk>;
+ clock-names = "sel-clk", "spi-clk";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ spi1: spi@1100b000 {
+ compatible = "mediatek,ipm-spi";
+ reg = <0 0x11008000 0 0x100>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ spi2: spi@11009000 {
+ compatible = "mediatek,ipm-spi";
+ reg = <0 0x11009000 0 0x100>;
+ clocks = <&spi_clk>,
+ <&spi_clk>;
+ clock-names = "sel-clk", "spi-clk";
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt7988-mmc",
+ "mediatek,mt7986-mmc";
+ reg = <0 0x11230000 0 0x1000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>,
+ <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>,
+ <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>,
+ <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>;
+ clock-names = "source", "hclk", "source_cg", "axi_cg";
+ status = "disabled";
+ };
+
+ ethdma: syscon@15000000 {
+ compatible = "mediatek,mt7988-ethdma", "syscon";
+ reg = <0 0x15000000 0 0x20000>;
+ clock-parent = <&topckgen>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ ethwarp: syscon@15031000 {
+ compatible = "mediatek,mt7988-ethwarp", "syscon";
+ reg = <0 0x15031000 0 0x1000>;
+ clock-parent = <&topckgen>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ eth: ethernet@15100000 {
+ compatible = "mediatek,mt7988-eth", "syscon";
+ reg = <0 0x15100000 0 0x20000>;
+ mediatek,ethsys = <ðdma>;
+ mediatek,sgmiisys = <&sgmiisys0>;
+ mediatek,usxgmiisys = <&usxgmiisys0>;
+ mediatek,xfi_pextp = <&xfi_pextp0>;
+ mediatek,xfi_pll = <&xfi_pll>;
+ mediatek,infracfg = <&topmisc>;
+ mediatek,toprgu = <&watchdog>;
+ resets = <ðdma ETHDMA_FE_RST>, <ðwarp ETHWARP_GSW_RST>;
+ reset-names = "fe", "mcm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mediatek,mcm;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm/dts/nuvoton-npcm845-evb.dts b/arch/arm/dts/nuvoton-npcm845-evb.dts
index 3cab780..a93666c 100644
--- a/arch/arm/dts/nuvoton-npcm845-evb.dts
+++ b/arch/arm/dts/nuvoton-npcm845-evb.dts
@@ -354,4 +354,4 @@
&r1en_pins
&r1oen_pins
>;
-};
\ No newline at end of file
+};
diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
index 09694b4..d88dee8 100644
--- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
@@ -12,6 +12,31 @@
&uart0 {
bootph-all;
- clock-frequency = <24000000>;
- status = "okay";
+};
+
+&pinctrl {
+ bootph-some-ram;
+
+ uart0 {
+ bootph-some-ram;
+ };
+ rtc {
+ bootph-some-ram;
+ };
+};
+
+&uart0_xfer {
+ bootph-some-ram;
+};
+
+&uart0_cts {
+ bootph-some-ram;
+};
+
+&uart0_rts {
+ bootph-some-ram;
+};
+
+&rtc_32k {
+ bootph-some-ram;
};
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
index 8498543..6904515 100644
--- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
@@ -54,7 +54,7 @@
};
&spi0 {
- spi_flash: spiflash@0 {
+ spi_flash: flash@0 {
bootph-all;
};
};
diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts
index 1b0f7e4..f69a38f 100644
--- a/arch/arm/dts/rk3328-rock64.dts
+++ b/arch/arm/dts/rk3328-rock64.dts
@@ -345,7 +345,7 @@
&spi0 {
status = "okay";
- spiflash@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index ce96ce4..a9f2536 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -26,6 +26,12 @@
0x0 0xff720000 0x0 0x1000
0x0 0xff798000 0x0 0x1000>;
};
+
+ rng: rng@ff060000 {
+ compatible = "rockchip,cryptov1-rng";
+ reg = <0x0 0xff060000 0x0 0x4000>;
+ status = "okay";
+ };
};
&cru {
diff --git a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
new file mode 100644
index 0000000..27c6277
--- /dev/null
+++ b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2023 Andy Yan <andyshrk@163.com>
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&sdhci {
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+};
+
+&uart2 {
+ bootph-all;
+ clock-frequency = <24000000>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-lubancat-2.dts b/arch/arm/dts/rk3568-lubancat-2.dts
new file mode 100644
index 0000000..e653b06
--- /dev/null
+++ b/arch/arm/dts/rk3568-lubancat-2.dts
@@ -0,0 +1,733 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 EmbedFire <embedfire@embedfire.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+ model = "EmbedFire LubanCat 2";
+ compatible = "embedfire,lubancat-2", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ user_led: user-led {
+ label = "user_led";
+ linux,default-trigger = "heartbeat";
+ default-state = "on";
+ gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_led_pin>;
+ };
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ dc_5v: dc-5v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_5v>;
+ };
+
+ vcc3v3_m2_pcie: vcc3v3-m2-pcie-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "m2_pcie_3v3";
+ enable-active-high;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&vcc3v3_m2_pcie_en>;
+ pinctrl-names = "default";
+ startup-delay-us = <200000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_mini_pcie: vcc3v3-mini-pcie-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "minipcie_3v3";
+ enable-active-high;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&vcc3v3_mini_pcie_en>;
+ pinctrl-names = "default";
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb20_host: vcc5v0-usb20-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb20_host";
+ enable-active-high;
+ gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&vcc5v0_usb20_host_en>;
+ pinctrl-names = "default";
+ };
+
+ vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb30_host";
+ enable-active-high;
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&vcc5v0_usb30_host_en>;
+ pinctrl-names = "default";
+ };
+
+ vcc5v0_otg_vbus: vcc5v0-otg-vbus-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_otg_vbus";
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&vcc5v0_otg_vbus_en>;
+ pinctrl-names = "default";
+ };
+};
+
+&combphy0 {
+ status = "okay";
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&combphy2 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vdda0v9_image>;
+ avdd-1v8-supply = <&vcca1v8_image>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ #clock-cells = <1>;
+ clock-names = "mclk";
+ clocks = <&cru I2S1_MCLKOUT_TX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ rockchip,system-power-controller;
+ #sound-dai-cells = <0>;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2s1_8ch {
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&gmac0 {
+ phy-mode = "rgmii";
+ clock_in_out = "output";
+
+ snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus>;
+
+ tx_delay = <0x22>;
+ rx_delay = <0x0e>;
+
+ phy-handle = <&rgmii_phy0>;
+ status = "okay";
+};
+
+&mdio0 {
+ rgmii_phy0: phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ };
+};
+
+&gmac1 {
+ phy-mode = "rgmii";
+ clock_in_out = "output";
+
+ snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus>;
+
+ tx_delay = <0x21>;
+ rx_delay = <0x0e>;
+
+ phy-handle = <&rgmii_phy1>;
+ status = "okay";
+};
+
+&mdio1 {
+ rgmii_phy1: phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ };
+};
+
+&gic {
+ mbi-ranges = <94 31>, <229 31>, <289 31>;
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x2 {
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_m2_pcie>;
+ status = "okay";
+};
+
+&pcie2x1 {
+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+ disable-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_mini_pcie>;
+ status = "okay";
+};
+
+&pmu_io_domains {
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&pwm8 {
+ status = "okay";
+};
+
+&pwm9 {
+ status = "disabled";
+};
+
+&pwm10 {
+ status = "disabled";
+};
+
+&pwm14 {
+ status = "disabled";
+};
+
+&spi3 {
+ pinctrl-0 = <&spi3m1_pins>;
+ status = "disabled";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3m1_xfer>;
+ status = "disabled";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&sdhci {
+ assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>;
+ assigned-clock-rates = <200000000>, <24000000>, <200000000>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ mmc-hs200-1_8v;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
+ supports-emmc;
+ status = "okay";
+};
+
+&sdmmc0 {
+ max-frequency = <150000000>;
+ no-sdio;
+ no-mmc;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ status = "okay";
+};
+
+/* USB OTG/USB Host_1 USB 2.0 Comb */
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb30_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_otg_vbus>;
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+/* USB Host_2/USB Host_3 USB 2.0 Comb */
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb2phy1_host {
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_usb20_host>;
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+/* MULTI_PHY0 For SATA0, USB3.0 OTG Only USB2.0 */
+&usb_host0_xhci {
+ phys = <&usb2phy0_otg>;
+ phy-names = "usb2-phy";
+ extcon = <&usb2phy0>;
+ maximum-speed = "high-speed";
+ dr_mode = "host";
+ status = "okay";
+};
+
+&sata0 {
+ status = "okay";
+};
+
+/* USB3.0 Host */
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
+
+&pinctrl {
+ leds {
+ user_led_pin: user-status-led-pin {
+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_usb30_host_en: vcc5v0-usb30-host-en {
+ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_otg_vbus_en: vcc5v0-otg-vbus-en {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ vcc3v3_m2_pcie_en: vcc3v3-m2-pcie-en {
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc3v3_mini_pcie_en: vcc3v3-mini-pcie-en {
+ rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index d21b182..32f687f 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -126,12 +126,11 @@
&sdhci {
bootph-pre-ram;
- status = "okay";
+ max-frequency = <200000000>;
};
&sdmmc0 {
bootph-pre-ram;
- status = "okay";
};
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
index 19b5451..522cffb 100644
--- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
@@ -169,7 +169,7 @@
ltdc_pins: ltdc@0 {
pins {
pinmux = <STM32_PINMUX('E', 4, AF14)>, /* B0 */
- <STM32_PINMUX('G',12, AF14)>, /* B4 */
+ <STM32_PINMUX('G',12, AF9)>, /* B4 */
<STM32_PINMUX('I', 9, AF14)>, /* VSYNC */
<STM32_PINMUX('I',10, AF14)>, /* HSYNC */
<STM32_PINMUX('I',14, AF14)>, /* CLK */
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index b2dce3a..27e0c38 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -258,4 +258,133 @@
bias-disable;
};
};
+
+ uart4_idle_pins_a: uart4-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart4_sleep_pins_a: uart4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
+ <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
+ };
+ };
+
+ uart8_pins_a: uart8-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
+ bias-pull-up;
+ };
+ };
+
+ uart8_idle_pins_a: uart8-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
+ bias-pull-up;
+ };
+ };
+
+ uart8_sleep_pins_a: uart8-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
+ <STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
+ };
+ };
+
+ usart1_pins_a: usart1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
+ <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
+ <STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
+ bias-pull-up;
+ };
+ };
+
+ usart1_idle_pins_a: usart1-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
+ <STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
+ bias-pull-up;
+ };
+ };
+
+ usart1_sleep_pins_a: usart1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */
+ <STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
+ <STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
+ };
+ };
+
+ usart2_pins_a: usart2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
+ <STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ usart2_idle_pins_a: usart2-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usart2_sleep_pins_a: usart2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
+ <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
+ <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ };
};
diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
index d94ba25..d163c26 100644
--- a/arch/arm/dts/stm32mp131.dtsi
+++ b/arch/arm/dts/stm32mp131.dtsi
@@ -397,15 +397,45 @@
status = "disabled";
};
+ usart3: serial@4000f000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x4000f000 0x400>;
+ interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc USART3_K>;
+ resets = <&rcc USART3_R>;
+ wakeup-source;
+ dmas = <&dmamux1 45 0x400 0x5>,
+ <&dmamux1 46 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
uart4: serial@40010000 {
compatible = "st,stm32h7-uart";
reg = <0x40010000 0x400>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART4_K>;
resets = <&rcc UART4_R>;
+ wakeup-source;
+ dmas = <&dmamux1 63 0x400 0x5>,
+ <&dmamux1 64 0x400 0x1>;
+ dma-names = "rx", "tx";
status = "disabled";
};
+ uart5: serial@40011000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40011000 0x400>;
+ interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc UART5_K>;
+ resets = <&rcc UART5_R>;
+ wakeup-source;
+ dmas = <&dmamux1 65 0x400 0x5>,
+ <&dmamux1 66 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
i2c1: i2c@40012000 {
compatible = "st,stm32mp13-i2c";
reg = <0x40012000 0x400>;
@@ -442,6 +472,32 @@
status = "disabled";
};
+ uart7: serial@40018000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40018000 0x400>;
+ interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc UART7_K>;
+ resets = <&rcc UART7_R>;
+ wakeup-source;
+ dmas = <&dmamux1 79 0x400 0x5>,
+ <&dmamux1 80 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart8: serial@40019000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40019000 0x400>;
+ interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc UART8_K>;
+ resets = <&rcc UART8_R>;
+ wakeup-source;
+ dmas = <&dmamux1 81 0x400 0x5>,
+ <&dmamux1 82 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
timers1: timer@44000000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -524,6 +580,19 @@
};
};
+ usart6: serial@44003000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x44003000 0x400>;
+ interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc USART6_K>;
+ resets = <&rcc USART6_R>;
+ wakeup-source;
+ dmas = <&dmamux1 71 0x400 0x5>,
+ <&dmamux1 72 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
i2s1: audio-controller@44004000 {
compatible = "st,stm32h7-i2s";
reg = <0x44004000 0x400>;
@@ -748,6 +817,32 @@
status = "disabled";
};
+ usart1: serial@4c000000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x4c000000 0x400>;
+ interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc USART1_K>;
+ resets = <&rcc USART1_R>;
+ wakeup-source;
+ dmas = <&dmamux1 41 0x400 0x5>,
+ <&dmamux1 42 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ usart2: serial@4c001000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x4c001000 0x400>;
+ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc USART2_K>;
+ resets = <&rcc USART2_R>;
+ wakeup-source;
+ dmas = <&dmamux1 43 0x400 0x5>,
+ <&dmamux1 44 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
i2s4: audio-controller@4c002000 {
compatible = "st,stm32h7-i2s";
reg = <0x4c002000 0x400>;
@@ -1001,8 +1096,6 @@
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
-
clock-names = "hse", "hsi", "csi", "lse", "lsi";
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,
diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts
index c40686c..f0900ca 100644
--- a/arch/arm/dts/stm32mp135f-dk.dts
+++ b/arch/arm/dts/stm32mp135f-dk.dts
@@ -19,8 +19,15 @@
aliases {
serial0 = &uart4;
+ serial1 = &usart1;
+ serial2 = &uart8;
+ serial3 = &usart2;
};
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
@@ -267,8 +274,41 @@
};
&uart4 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart4_pins_a>;
+ pinctrl-1 = <&uart4_sleep_pins_a>;
+ pinctrl-2 = <&uart4_idle_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+&uart8 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart8_pins_a>;
+ pinctrl-1 = <&uart8_sleep_pins_a>;
+ pinctrl-2 = <&uart8_idle_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+};
+
+&usart1 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart1_pins_a>;
+ pinctrl-1 = <&usart1_sleep_pins_a>;
+ pinctrl-2 = <&usart1_idle_pins_a>;
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+/* Bluetooth */
+&usart2 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart2_pins_a>;
+ pinctrl-1 = <&usart2_sleep_pins_a>;
+ pinctrl-2 = <&usart2_idle_pins_a>;
+ uart-has-rtscts;
status = "okay";
};
diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
index a9d2bec..e86d989 100644
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
@@ -1880,6 +1880,21 @@
};
};
+ spi1_pins_b: spi1-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
+ <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
+ bias-disable;
+ };
+ };
+
spi2_pins_a: spi2-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
@@ -2163,7 +2178,7 @@
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
@@ -2181,7 +2196,7 @@
pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
@@ -2448,19 +2463,4 @@
bias-disable;
};
};
-
- spi1_pins_b: spi1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
- <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
- bias-disable;
- };
- };
};
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
index b3baacb..21d11be 100644
--- a/arch/arm/dts/stm32mp151.dtsi
+++ b/arch/arm/dts/stm32mp151.dtsi
@@ -1148,8 +1148,8 @@
usbotg_hs: usb-otg@49000000 {
compatible = "st,stm32mp15-hsotg", "snps,dwc2";
reg = <0x49000000 0x10000>;
- clocks = <&rcc USBO_K>;
- clock-names = "otg";
+ clocks = <&rcc USBO_K>, <&usbphyc>;
+ clock-names = "otg", "utmi";
resets = <&rcc USBO_R>;
reset-names = "dwc2";
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
index 4c8be9c..0da3667 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/dts/stm32mp157a-dk1.dts
@@ -17,9 +17,6 @@
aliases {
ethernet0 = ðernet0;
- serial0 = &uart4;
- serial1 = &usart3;
- serial2 = &uart7;
};
chosen {
diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
index 2bc92ef..ab13e34 100644
--- a/arch/arm/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/dts/stm32mp157c-dk2.dts
@@ -18,9 +18,6 @@
aliases {
ethernet0 = ðernet0;
- serial0 = &uart4;
- serial1 = &usart3;
- serial2 = &uart7;
serial3 = &usart2;
};
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index fe5c8f2..3541a17 100644
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -16,6 +16,10 @@
model = "STMicroelectronics STM32MP157C eval daughter";
compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
+ aliases {
+ serial0 = &uart4;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -65,17 +69,8 @@
reg = <0x38000000 0x10000>;
no-map;
};
-
- gpu_reserved: gpu@e8000000 {
- reg = <0xe8000000 0x8000000>;
- no-map;
- };
};
- aliases {
- serial0 = &uart4;
- };
-
sd_switch: regulator-sd_switch {
compatible = "regulator-gpio";
regulator-name = "sd_switch";
@@ -148,10 +143,6 @@
status = "okay";
};
-&gpu {
- contiguous-area = <&gpu_reserved>;
-};
-
&hash1 {
status = "okay";
};
diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
index 542226c..ba8e9d9 100644
--- a/arch/arm/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/dts/stm32mp157c-ev1.dts
@@ -14,16 +14,15 @@
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
aliases {
- serial0 = &uart4;
serial1 = &usart3;
ethernet0 = ðernet0;
};
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
clocks {
clk_ext_camera: clk-ext-camera {
#clock-cells = <0>;
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi
index de76174..d3b85a8 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi
@@ -118,13 +118,12 @@
ðernet0 {
status = "okay";
- pinctrl-0 = <ðernet0_rmii_pins_a>;
- pinctrl-1 = <ðernet0_rmii_sleep_pins_a>;
+ pinctrl-0 = <ðernet0_rmii_pins_c &mco2_pins_a>;
+ pinctrl-1 = <ðernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rmii";
max-speed = <100>;
phy-handle = <&phy0>;
- st,eth-ref-clk-sel;
mdio0 {
#address-cells = <1>;
@@ -136,7 +135,7 @@
/* LAN8710Ai */
compatible = "ethernet-phy-id0007.c0f0",
"ethernet-phy-ieee802.3-c22";
- clocks = <&rcc ETHCK_K>;
+ clocks = <&rcc CK_MCO2>;
reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
reset-assert-us = <500>;
reset-deassert-us = <500>;
@@ -450,6 +449,21 @@
};
};
+&rcc {
+ /* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */
+ clocks = <&rcc CK_MCO2>;
+ clock-names = "ETH_RX_CLK/ETH_REF_CLK";
+
+ /*
+ * Set PLL4P output to 100 MHz to supply SDMMC with faster clock,
+ * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2,
+ * so that MCO2 behaves as a divider for the ETHRX clock here.
+ */
+ assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>;
+ assigned-clock-parents = <&rcc PLL4_P>;
+ assigned-clock-rates = <50000000>, <100000000>;
+};
+
&rng1 {
status = "okay";
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index a808620..f12941b 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -153,6 +153,20 @@
};
&rcc {
+ /*
+ * Reinstate clock names from stm32mp151.dtsi, the MCO2 trick
+ * used in stm32mp15xx-dhcom-som.dtsi is not supported by the
+ * U-Boot clock framework.
+ */
+ clock-names = "hse", "hsi", "csi", "lse", "lsi";
+ clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
+ <&clk_lse>, <&clk_lsi>;
+
+ /* The MCO2 is already configured correctly, remove those. */
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi
index 49b3e76..f4de6c0 100644
--- a/arch/arm/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi
@@ -8,6 +8,12 @@
#include <dt-bindings/mfd/st,stpmic1.h>
/ {
+ aliases {
+ serial0 = &uart4;
+ serial1 = &usart3;
+ serial2 = &uart7;
+ };
+
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
@@ -53,11 +59,6 @@
reg = <0x38000000 0x10000>;
no-map;
};
-
- gpu_reserved: gpu@d4000000 {
- reg = <0xd4000000 0x4000000>;
- no-map;
- };
};
led {
@@ -159,10 +160,6 @@
};
};
-&gpu {
- contiguous-area = <&gpu_reserved>;
-};
-
&hash1 {
status = "okay";
};
diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts
index e19001e..fa942d2 100644
--- a/arch/arm/dts/tegra20-trimslice.dts
+++ b/arch/arm/dts/tegra20-trimslice.dts
@@ -27,7 +27,13 @@
spi@7000c380 {
status = "okay";
- spi-max-frequency = <25000000>;
+ spi-max-frequency = <48000000>;
+
+ flash@0 {
+ compatible = "winbond,w25q80bl", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <48000000>;
+ };
};
pcie@80003000 {
diff --git a/arch/arm/dts/tegra30-asus-grouper-common.dtsi b/arch/arm/dts/tegra30-asus-grouper-common.dtsi
new file mode 100644
index 0000000..4fa980f
--- /dev/null
+++ b/arch/arm/dts/tegra30-asus-grouper-common.dtsi
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/input/input.h>
+
+#include "tegra30.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uarta;
+ };
+
+ aliases {
+ i2c0 = &pwr_i2c;
+
+ mmc0 = &sdmmc4; /* eMMC */
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ usb0 = &usb1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ host1x@50000000 {
+ dc@54200000 {
+ nvidia,180-rotation;
+ rgb {
+ status = "okay";
+
+ nvidia,panel = <&panel>;
+ };
+ };
+ };
+
+ gpio@6000d000 {
+ volume-buttons-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ };
+
+ uarta: serial@70006000 {
+ status = "okay";
+ };
+
+ pwm: pwm@7000a000 {
+ status = "okay";
+ };
+
+ pwr_i2c: i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ sdmmc4: sdhci@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+ };
+
+ usb1: usb@7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ power-supply = <&vdd_5v0_bl>;
+ pwms = <&pwm 0 50000>;
+
+ brightness-levels = <1 35 70 105 140 175 210 255>;
+ default-brightness-level = <5>;
+ };
+
+ /* PMIC has a built-in 32KHz oscillator which is used by PMC */
+ clk32k_in: clock-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic-oscillator";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_ENTER>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_UP>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_DOWN>;
+ };
+ };
+
+ panel: panel {
+ compatible = "simple-panel";
+
+ power-supply = <&vdd_pnl_reg>;
+ enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>;
+
+ backlight = <&backlight>;
+
+ display-timings {
+ timing@0 {
+ /* 1280x800@60Hz */
+ clock-frequency = <68000000>;
+
+ hactive = <800>;
+ hfront-porch = <24>;
+ hback-porch = <32>;
+ hsync-len = <24>;
+
+ vactive = <1280>;
+ vfront-porch = <5>;
+ vback-porch = <32>;
+ vsync-len = <1>;
+ };
+ };
+ };
+
+ vdd_pnl_reg: regulator-pnl {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_panel";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_5v0_bl: regulator-bl {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0_bl";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
diff --git a/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts b/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts
new file mode 100644
index 0000000..a98d3e2
--- /dev/null
+++ b/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-asus-grouper-common.dtsi"
+
+/ {
+ model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) E1565";
+ compatible = "asus,grouper", "nvidia,tegra30";
+
+ i2c@7000d000 {
+ pmic: max77663@3c {
+ compatible = "maxim,max77663";
+ reg = <0x3c>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ regulators {
+ vdd_1v8: sd2 {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* eMMC VDD */
+ vcore_emmc: ldo3 {
+ regulator-name = "vcore_emmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts b/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts
new file mode 100644
index 0000000..44ea218
--- /dev/null
+++ b/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-asus-grouper-common.dtsi"
+
+/ {
+ model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) PM269";
+ compatible = "asus,grouper", "nvidia,tegra30";
+
+ i2c@7000d000 {
+ /* Texas Instruments TPS659110 PMIC */
+ pmic: tps65911@2d {
+ compatible = "ti,tps65911";
+ reg = <0x2d>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ regulators {
+ /* eMMC VDD */
+ vcore_emmc: ldo1 {
+ regulator-name = "vdd_emmc_core";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts b/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts
new file mode 100644
index 0000000..812d5a1
--- /dev/null
+++ b/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-asus-grouper-common.dtsi"
+
+/ {
+ model = "ASUS Google Nexus 7 (Project Bach / ME370TG) E1565";
+ compatible = "asus,tilapia", "nvidia,tegra30";
+
+ i2c@7000d000 {
+ pmic: max77663@3c {
+ compatible = "maxim,max77663";
+ reg = <0x3c>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ regulators {
+ vdd_1v8: sd2 {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* eMMC VDD */
+ vcore_emmc: ldo3 {
+ regulator-name = "vcore_emmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+
+ panel {
+ display-timings {
+ timing@0 {
+ /* 1280x800@60Hz */
+ clock-frequency = <81750000>;
+
+ hactive = <800>;
+ hfront-porch = <64>;
+ hback-porch = <128>;
+ hsync-len = <64>;
+
+ vactive = <1280>;
+ vfront-porch = <5>;
+ vback-porch = <2>;
+ vsync-len = <1>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts
new file mode 100644
index 0000000..4b2dc61
--- /dev/null
+++ b/arch/arm/dts/tegra30-asus-p1801-t.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-asus-transformer.dtsi"
+
+/ {
+ model = "ASUS Portable AiO P1801-T";
+ compatible = "asus,p1801-t", "nvidia,tegra30";
+
+ /delete-node/ host1x@50000000;
+ /delete-node/ pwm@7000a000;
+
+ /delete-node/ backlight;
+ /delete-node/ panel;
+
+ /delete-node/ regulator-pnl;
+ /delete-node/ regulator-bl;
+};
diff --git a/arch/arm/dts/tegra30-asus-tf201.dts b/arch/arm/dts/tegra30-asus-tf201.dts
new file mode 100644
index 0000000..54f359e
--- /dev/null
+++ b/arch/arm/dts/tegra30-asus-tf201.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-asus-transformer.dtsi"
+
+/ {
+ model = "ASUS Transformer Prime TF201";
+ compatible = "asus,tf201", "nvidia,tegra30";
+};
diff --git a/arch/arm/dts/tegra30-asus-tf300t.dts b/arch/arm/dts/tegra30-asus-tf300t.dts
new file mode 100644
index 0000000..db08488
--- /dev/null
+++ b/arch/arm/dts/tegra30-asus-tf300t.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-asus-transformer.dtsi"
+
+/ {
+ model = "ASUS Transformer Pad TF300T";
+ compatible = "asus,tf300t", "nvidia,tegra30";
+
+ gpio@6000d000 {
+ volume-buttons-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(K, 7) GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ };
+};
diff --git a/arch/arm/dts/tegra30-asus-tf300tg.dts b/arch/arm/dts/tegra30-asus-tf300tg.dts
new file mode 100644
index 0000000..6f42182
--- /dev/null
+++ b/arch/arm/dts/tegra30-asus-tf300tg.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-asus-transformer.dtsi"
+
+/ {
+ model = "ASUS Transformer Pad 3G TF300TG";
+ compatible = "asus,tf300tg", "nvidia,tegra30";
+};
diff --git a/arch/arm/dts/tegra30-asus-tf300tl.dts b/arch/arm/dts/tegra30-asus-tf300tl.dts
new file mode 100644
index 0000000..242f791
--- /dev/null
+++ b/arch/arm/dts/tegra30-asus-tf300tl.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-asus-transformer.dtsi"
+
+/ {
+ model = "ASUS Transformer Pad LTE TF300TL";
+ compatible = "asus,tf300tl", "nvidia,tegra30";
+};
diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts
new file mode 100644
index 0000000..c9b8f4f
--- /dev/null
+++ b/arch/arm/dts/tegra30-asus-tf600t.dts
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-asus-transformer.dtsi"
+
+/ {
+ model = "ASUS VivoTab RT TF600T";
+ compatible = "asus,tf600t", "nvidia,tegra30";
+
+ aliases {
+ spi0 = &spi4;
+ };
+
+ /delete-node/ host1x@50000000;
+
+ pmic_i2c: i2c@7000d000 {
+ /* Texas Instruments TPS659110 PMIC */
+ pmic: tps65911@2d {
+ regulators {
+ vdd_1v2_bl: vdd1 {
+ regulator-name = "vdd_1v2_backlight";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ti,regulator-ext-sleep-control = <8>;
+ };
+
+ /delete-node/ ldo2;
+ /delete-node/ ldo3;
+
+ /* uSD slot VDDIO */
+ vddio_usd: ldo5 {
+ regulator-name = "vddio_sdmmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ avdd_dsi_csi: ldo6 {
+ regulator-name = "avdd_dsi_csi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ };
+ };
+ };
+
+ spi4: spi@7000da00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+
+ spi-flash@1 {
+ compatible = "winbond,w25q32", "jedec,spi-nor";
+ reg = <1>;
+ spi-max-frequency = <20000000>;
+ };
+ };
+
+ backlight {
+ power-supply = <&vdd_1v2_bl>;
+ };
+
+ gpio-keys {
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_UP>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_DOWN>;
+ };
+ };
+
+ /delete-node/ panel;
+
+ vdd_usd: regulator-usd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_usd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ /delete-node/ regulator-pnl;
+ /delete-node/ regulator-bl;
+};
diff --git a/arch/arm/dts/tegra30-asus-tf700t.dts b/arch/arm/dts/tegra30-asus-tf700t.dts
new file mode 100644
index 0000000..d530527
--- /dev/null
+++ b/arch/arm/dts/tegra30-asus-tf700t.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-asus-transformer.dtsi"
+
+/ {
+ model = "ASUS Transformer Infinity TF700T";
+ compatible = "asus,tf700t", "nvidia,tegra30";
+
+ /delete-node/ host1x@50000000;
+
+ /delete-node/ panel;
+};
diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi
new file mode 100644
index 0000000..4eee1df
--- /dev/null
+++ b/arch/arm/dts/tegra30-asus-transformer.dtsi
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/input/input.h>
+
+#include "tegra30.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uarta;
+ };
+
+ aliases {
+ i2c0 = &pwr_i2c;
+ i2c1 = &gen1_i2c;
+
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc1; /* uSD slot */
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ usb0 = &usb1;
+ usb1 = &usb3; /* Dock USB */
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ host1x@50000000 {
+ dc@54200000 {
+ rgb {
+ status = "okay";
+
+ nvidia,panel = <&panel>;
+ };
+ };
+ };
+
+ uarta: serial@70006000 {
+ status = "okay";
+ };
+
+ pwm: pwm@7000a000 {
+ status = "okay";
+ };
+
+ gen1_i2c: i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ pwr_i2c: i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Texas Instruments TPS659110 PMIC */
+ pmic: tps65911@2d {
+ compatible = "ti,tps65911";
+ reg = <0x2d>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ regulators {
+ /* eMMC VDD */
+ vcore_emmc: ldo1 {
+ regulator-name = "vdd_emmc_core";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ /* uSD slot VDD */
+ vdd_usd: ldo2 {
+ regulator-name = "vdd_usd";
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3100000>;
+ };
+
+ /* uSD slot VDDIO */
+ vddio_usd: ldo3 {
+ regulator-name = "vddio_usd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3100000>;
+ };
+ };
+ };
+ };
+
+ sdmmc1: sdhci@78000000 {
+ status = "okay";
+ bus-width = <4>;
+
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
+
+ vmmc-supply = <&vdd_usd>;
+ vqmmc-supply = <&vddio_usd>;
+ };
+
+ sdmmc4: sdhci@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+ };
+
+ /* USB via ASUS connector */
+ usb1: usb@7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ /* Dock's USB port */
+ usb3: usb@7d008000 {
+ status = "okay";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ power-supply = <&vdd_5v0_bl>;
+ pwms = <&pwm 0 4000000>;
+
+ brightness-levels = <1 35 70 105 140 175 210 255>;
+ default-brightness-level = <5>;
+ };
+
+ /* PMIC has a built-in 32KHz oscillator which is used by PMC */
+ clk32k_in: clock-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic-oscillator";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_ENTER>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_UP>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_DOWN>;
+ };
+ };
+
+ panel: panel {
+ compatible = "simple-panel";
+
+ power-supply = <&vdd_pnl_reg>;
+ enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>;
+
+ backlight = <&backlight>;
+
+ display-timings {
+ timing@0 {
+ /* 1280x800@60Hz */
+ clock-frequency = <68000000>;
+
+ hactive = <1280>;
+ hfront-porch = <48>;
+ hback-porch = <18>;
+ hsync-len = <30>;
+
+ vactive = <800>;
+ vfront-porch = <3>;
+ vback-porch = <12>;
+ vsync-len = <5>;
+ };
+ };
+ };
+
+ vdd_pnl_reg: regulator-pnl {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_panel";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_5v0_bl: regulator-bl {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0_bl";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
diff --git a/arch/arm/dts/tegra30-htc-endeavoru.dts b/arch/arm/dts/tegra30-htc-endeavoru.dts
new file mode 100644
index 0000000..c55e193
--- /dev/null
+++ b/arch/arm/dts/tegra30-htc-endeavoru.dts
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/* This dts file describes the HTC One X smartphone */
+/* CPU Speedo ID 4, Soc Speedo ID 1, CPU Process: 1, Core Process: 0 */
+
+#include <dt-bindings/input/input.h>
+
+#include "tegra30.dtsi"
+
+/ {
+ model = "HTC One X";
+ compatible = "htc,endeavoru", "nvidia,tegra30";
+
+ chosen {
+ stdout-path = &uarta;
+ };
+
+ aliases {
+ i2c0 = &pwr_i2c;
+
+ mmc0 = &sdmmc4; /* eMMC */
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ usb0 = µ_usb;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ host1x@50000000 {
+ dc@54200000 {
+ clocks = <&tegra_car TEGRA30_CLK_DISP1>,
+ <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
+
+ rgb {
+ status = "okay";
+
+ nvidia,panel = <&dsia>;
+ };
+ };
+
+ dsia: dsi@54300000 {
+ status = "okay";
+
+ avdd-dsi-csi-supply = <&avdd_dsi_csi>;
+
+ panel = <&panel>;
+ };
+ };
+
+ uarta: serial@70006000 {
+ status = "okay";
+ };
+
+ pwr_i2c: i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ /* Texas Instruments TPS80032 PMIC */
+ pmic: tps80032@48 {
+ compatible = "ti,tps80032";
+ reg = <0x48>;
+
+ regulators {
+ /* DSI VDD */
+ avdd_dsi_csi: ldo1 {
+ regulator-name = "avdd_dsi_csi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+
+ sdmmc4: sdhci@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+ };
+
+ micro_usb: usb@7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ backlight: backlight {
+ compatible = "nvidia,tegra-pwm-backlight";
+
+ nvidia,pwm-source = <1>;
+ nvidia,default-brightness = <0x8E>;
+ };
+
+ /* PMIC has a built-in 32KHz oscillator which is used by PMC */
+ clk32k_in: clock-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic-oscillator";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_ENTER>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_UP>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(W, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_DOWN>;
+ };
+ };
+
+ panel: panel {
+ compatible = "htc,edge-panel";
+
+ reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>;
+
+ vdd-supply = <&vdd_3v3_panel>;
+ vddio-supply = <&vdd_1v8_panel>;
+
+ backlight = <&backlight>;
+ };
+
+ vcore_emmc: regulator-emmc {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_2v85_sdmmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ gpio = <&gpio TEGRA_GPIO(M, 3) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_3v3_panel: regulator-lcm {
+ compatible = "regulator-fixed";
+ regulator-name = "v_lcm_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA_GPIO(E, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_1v8_panel: regulator-lcmio {
+ compatible = "regulator-fixed";
+ regulator-name = "v_lcmio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio TEGRA_GPIO(E, 5) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
diff --git a/arch/arm/dts/tegra30-lg-p880.dts b/arch/arm/dts/tegra30-lg-p880.dts
new file mode 100644
index 0000000..81d3643
--- /dev/null
+++ b/arch/arm/dts/tegra30-lg-p880.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-lg-x3.dtsi"
+
+/ {
+ model = "LG Optimus 4X HD";
+ compatible = "lge,p880", "nvidia,tegra30";
+
+ aliases {
+ mmc1 = &sdmmc3; /* uSD slot */
+ };
+
+ sdmmc3: sdhci@78000400 {
+ status = "okay";
+ bus-width = <4>;
+
+ cd-gpios = <&gpio TEGRA_GPIO(W, 5) GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vdd_usd>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+ };
+
+ gpio-keys {
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(O, 7) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_UP>;
+ };
+ };
+
+ panel: panel {
+ compatible = "jdi,dx12d100vm0eaa";
+
+ enable-gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
+
+ backlight = <&backlight>;
+ };
+};
diff --git a/arch/arm/dts/tegra30-lg-p895.dts b/arch/arm/dts/tegra30-lg-p895.dts
new file mode 100644
index 0000000..074205d
--- /dev/null
+++ b/arch/arm/dts/tegra30-lg-p895.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-lg-x3.dtsi"
+
+/ {
+ model = "LG Optimus Vu";
+ compatible = "lge,p895", "nvidia,tegra30";
+
+ gpio-keys {
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_UP>;
+ };
+ };
+
+ panel: panel {
+ compatible = "hitachi,tx13d100vm0eaa";
+
+ reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
+
+ renesas,gamma = <3>;
+ renesas,inversion;
+ renesas,contrast;
+
+ vcc-supply = <&vcc_3v0_lcd>;
+ iovcc-supply = <&iovcc_1v8_lcd>;
+
+ backlight = <&backlight>;
+ };
+
+ vcc_3v0_lcd: regulator-lcd {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v0_lcd";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ iovcc_1v8_lcd: regulator-lcdvio {
+ compatible = "regulator-fixed";
+ regulator-name = "iovcc_1v8_lcd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
diff --git a/arch/arm/dts/tegra30-lg-x3.dtsi b/arch/arm/dts/tegra30-lg-x3.dtsi
new file mode 100644
index 0000000..922e399
--- /dev/null
+++ b/arch/arm/dts/tegra30-lg-x3.dtsi
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/input/input.h>
+
+#include "tegra30.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uartd;
+ };
+
+ aliases {
+ i2c0 = &pwr_i2c;
+ i2c1 = &gen2_i2c;
+
+ mmc0 = &sdmmc4; /* eMMC */
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ spi0 = &dsi_spi;
+
+ usb0 = µ_usb;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ host1x@50000000 {
+ dc@54200000 {
+ rgb {
+ status = "okay";
+
+ nvidia,panel = <&bridge>;
+ };
+ };
+ };
+
+ uartd: serial@70006300 {
+ status = "okay";
+ };
+
+ gen2_i2c: i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ backlight: lm3533@36 {
+ compatible = "ti,lm3533";
+ reg = <0x36>;
+
+ enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>;
+ default-brightness-level = <128>;
+ };
+
+ muic@44 {
+ compatible = "maxim,max14526-muic";
+ reg = <0x44>;
+
+ maxim,ap-usb;
+
+ usif-gpios = <&gpio TEGRA_GPIO(Y, 3) GPIO_ACTIVE_HIGH>;
+ dp2t-gpios = <&gpio TEGRA_GPIO(CC, 2) GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ pwr_i2c: i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pmic: max77663@1c {
+ compatible = "maxim,max77663";
+ reg = <0x1c>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ system-power-controller;
+
+ regulators {
+ vdd_1v8_vio: sd2 {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_usd: ldo3 {
+ regulator-name = "vdd_sdmmc3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcore_emmc: ldo5 {
+ regulator-name = "vdd_ddr_rx";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+ };
+
+ dsi_spi: spi@7000dc00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+
+ bridge: bridge-spi@2 {
+ compatible = "solomon,ssd2825";
+ reg = <2>;
+
+ spi-cpol;
+ spi-cpha;
+
+ spi-max-frequency = <1000000>;
+
+ power-gpios = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_HIGH>;
+
+ clocks = <&ssd2825_refclk>;
+ clock-names = "tx_clk";
+
+ panel = <&panel>;
+ };
+ };
+
+ sdmmc4: sdhci@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+ };
+
+ micro_usb: usb@7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ /* PMIC has a built-in 32KHz oscillator which is used by PMC */
+ clk32k_in: clock-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic-oscillator";
+ };
+
+ ssd2825_refclk: clock-ssd2825 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "ssd2825-refclk";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_ENTER>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(O, 4) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_DOWN>;
+ };
+ };
+};
diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
index 86c906b..84b63e4 100644
--- a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
+++ b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
@@ -189,6 +189,21 @@
DCLK_VOP_DIV_SHIFT = 0,
DCLK_VOP_DIV_MASK = 0xff,
+ /* CRU_CLKSEL_CON10 */
+ /* CRU_CLKSEL_CON13 */
+ /* CRU_CLKSEL_CON16 */
+ /* CRU_CLKSEL_CON19 */
+ /* CRU_CLKSEL_CON22 */
+ CLK_UART_PLL_SEL_SHIFT = 13,
+ CLK_UART_PLL_SEL_MASK = 0x7 << CLK_UART_PLL_SEL_SHIFT,
+ CLK_UART_PLL_SEL_DPLL = 0,
+ CLK_UART_PLL_SEL_VPLL0,
+ CLK_UART_PLL_SEL_VPLL1,
+ CLK_UART_PLL_SEL_480M,
+ CLK_UART_PLL_SEL_24M,
+ CLK_UART_DIV_CON_SHIFT = 0,
+ CLK_UART_DIV_CON_MASK = 0x1f << CLK_UART_DIV_CON_SHIFT,
+
/* CRU_CLK_SEL25_CON */
/* CRU_CLK_SEL26_CON */
/* CRU_CLK_SEL27_CON */
diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
index 13ea4ab..9778790 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -15,6 +15,8 @@
# include <asm/arch-rockchip/cru_rk3288.h>
#elif defined(CONFIG_ROCKCHIP_RK3399)
# include <asm/arch-rockchip/cru_rk3399.h>
+#elif defined(CONFIG_ROCKCHIP_RK3568)
+#include <asm/arch-rockchip/cru_rk3568.h>
#endif
/* CRU_GLB_RST_ST */
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
index 399f19a..9c7ddd7 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
@@ -106,6 +106,8 @@
unsigned int emmc_con[2];/* Address Offset: 0x0598 */
};
+#define rockchip_cru rk3568_cru
+
check_member(rk3568_cru, mode_con00, 0xc0);
check_member(rk3568_cru, softrst_con[0], 0x400);
@@ -493,7 +495,7 @@
/* CRU_CLK_SEL81_CON */
CPLL_25M_DIV_SHIFT = 8,
- CPLL_25M_DIV_MASK = 0x1f << CPLL_25M_DIV_SHIFT,
+ CPLL_25M_DIV_MASK = 0x3f << CPLL_25M_DIV_SHIFT,
CPLL_50M_DIV_SHIFT = 0,
CPLL_50M_DIV_MASK = 0x1f << CPLL_50M_DIV_SHIFT,
diff --git a/arch/arm/include/asm/arch-tegra/fuse.h b/arch/arm/include/asm/arch-tegra/fuse.h
index 5b8e0bd..f3f2ad8 100644
--- a/arch/arm/include/asm/arch-tegra/fuse.h
+++ b/arch/arm/include/asm/arch-tegra/fuse.h
@@ -19,4 +19,11 @@
u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */
};
+/**
+ * Calculate SoC UID
+ *
+ * Return: uid if ok, 0 on error
+ */
+unsigned long long tegra_chip_uid(void);
+
#endif /* ifndef _FUSE_H_ */
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index fa85486..8e89783 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -15,9 +15,34 @@
#ifndef __ASM_ARM_BITOPS_H
#define __ASM_ARM_BITOPS_H
+#if __LINUX_ARM_ARCH__ < 5
+
#include <asm-generic/bitops/__ffs.h>
#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/fls.h>
+
+#else
+
+#define PLATFORM_FFS
+#define PLATFORM_FLS
+
+#if !IS_ENABLED(CONFIG_HAS_THUMB2) && CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
+
+unsigned long __fls(unsigned long word);
+unsigned long __ffs(unsigned long word);
+int fls(unsigned int x);
+int ffs(int x);
+
+#else
+
+#include <asm-generic/bitops/builtin-__fls.h>
+#include <asm-generic/bitops/builtin-__ffs.h>
+#include <asm-generic/bitops/builtin-fls.h>
+#include <asm-generic/bitops/builtin-ffs.h>
+
+#endif
+#endif
+
#include <asm-generic/bitops/fls64.h>
#ifdef __KERNEL__
@@ -113,7 +138,7 @@
static inline int __ilog2(unsigned int x)
{
- return generic_fls(x) - 1;
+ return fls(x) - 1;
}
#define ffz(x) __ffs(~(x))
diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index 0ece4b0..ee79a19 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -34,9 +34,6 @@
};
#endif
-/* Linker symbols. */
-extern char __bss_start[], __bss_end[];
-
#ifndef CONFIG_DM
extern gd_t gdata;
#endif
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 62cf80f..b1bcd37 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -113,6 +113,11 @@
AFLAGS_REMOVE_memcpy.o := -mthumb -mthumb-interwork
AFLAGS_memset.o := -DMEMSET_NO_THUMB_BUILD
AFLAGS_memcpy.o := -DMEMCPY_NO_THUMB_BUILD
+
+# This is only necessary to force ARM mode on THUMB1 targets.
+ifneq ($(CONFIG_SYS_ARM_ARCH),4)
+obj-y += bitops.o
+endif
endif
endif
diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c
index 6de0ce9..181a8ac 100644
--- a/arch/arm/lib/asm-offsets.c
+++ b/arch/arm/lib/asm-offsets.c
@@ -9,6 +9,11 @@
* generate asm statements containing #defines,
* compile this file to assembler, and then extract the
* #defines from the assembly-language output.
+ *
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
*/
#include <common.h>
@@ -90,6 +95,17 @@
DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2));
DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id));
DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state));
+#ifdef CONFIG_ARM64
+ DEFINE(ARM_SMCCC_1_2_REGS_X0_OFFS, offsetof(struct arm_smccc_1_2_regs, a0));
+ DEFINE(ARM_SMCCC_1_2_REGS_X2_OFFS, offsetof(struct arm_smccc_1_2_regs, a2));
+ DEFINE(ARM_SMCCC_1_2_REGS_X4_OFFS, offsetof(struct arm_smccc_1_2_regs, a4));
+ DEFINE(ARM_SMCCC_1_2_REGS_X6_OFFS, offsetof(struct arm_smccc_1_2_regs, a6));
+ DEFINE(ARM_SMCCC_1_2_REGS_X8_OFFS, offsetof(struct arm_smccc_1_2_regs, a8));
+ DEFINE(ARM_SMCCC_1_2_REGS_X10_OFFS, offsetof(struct arm_smccc_1_2_regs, a10));
+ DEFINE(ARM_SMCCC_1_2_REGS_X12_OFFS, offsetof(struct arm_smccc_1_2_regs, a12));
+ DEFINE(ARM_SMCCC_1_2_REGS_X14_OFFS, offsetof(struct arm_smccc_1_2_regs, a14));
+ DEFINE(ARM_SMCCC_1_2_REGS_X16_OFFS, offsetof(struct arm_smccc_1_2_regs, a16));
+#endif
#endif
return 0;
diff --git a/arch/arm/lib/bitops.S b/arch/arm/lib/bitops.S
new file mode 100644
index 0000000..29d1524
--- /dev/null
+++ b/arch/arm/lib/bitops.S
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 Sean Anderson <sean.anderson@seco.com>
+ *
+ * ARM bitops to call when using THUMB1, which doesn't have these instructions.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+.pushsection .text.__fls
+ENTRY(__fls)
+ clz r0, r0
+ rsb r0, r0, #31
+ ret lr
+ENDPROC(__fls)
+.popsection
+
+.pushsection .text.__ffs
+ENTRY(__ffs)
+ rsb r3, r0, #0
+ and r0, r0, r3
+ clz r0, r0
+ rsb r0, r0, #31
+ ret lr
+ENDPROC(__ffs)
+.popsection
+
+.pushsection .text.fls
+ENTRY(fls)
+ cmp r0, #0
+ clzne r0, r0
+ rsbne r0, r0, #32
+ ret lr
+ENDPROC(fls)
+.popsection
+
+.pushsection .text.ffs
+ENTRY(ffs)
+ rsb r3, r0, #0
+ and r0, r0, r3
+ clz r0, r0
+ rsb r0, r0, #32
+ ret lr
+ENDPROC(ffs)
+.popsection
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 183650a..7265faf 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -146,6 +146,14 @@
return 0;
}
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ printf("CPU: BCM283x\n");
+ return 0;
+}
+#endif
+
#ifdef CONFIG_ARMV7_LPAE
#ifdef CONFIG_TARGET_RPI_4_32B
#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xffc00000UL
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index d94b582..2136ab7 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -181,7 +181,7 @@
config SPL_IMX_ROMAPI_LOADADDR
hex "Default load address to load image through ROM API"
depends on IMX8_ROMAPI || SPL_BOOTROM_SUPPORT
- default 0
+ default 0x0
config IMX_DCD_ADDR
hex "DCD Blocks location on the image"
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 15f844f..59d11b3 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -34,11 +34,11 @@
config BOOTAUX_RESERVED_MEM_BASE
hex "i.MX auxiliary core dram memory base"
- default 0
+ default 0x0
config BOOTAUX_RESERVED_MEM_SIZE
hex "i.MX auxiliary core dram memory size"
- default 0
+ default 0x0
choice
prompt "i.MX8 board select"
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index d525488..78b775f 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -333,7 +333,7 @@
}
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
ulong top_addr;
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index bf1c3c5..9168bf8 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -194,4 +194,5 @@
source "board/ti/j721e/Kconfig"
source "board/siemens/iot2050/Kconfig"
source "board/ti/j721s2/Kconfig"
+source "board/toradex/verdin-am62/Kconfig"
endif
diff --git a/arch/arm/mach-k3/am62x/clk-data.c b/arch/arm/mach-k3/am62x/clk-data.c
index c088177..d7bfed0 100644
--- a/arch/arm/mach-k3/am62x/clk-data.c
+++ b/arch/arm/mach-k3/am62x/clk-data.c
@@ -57,7 +57,7 @@
static const char * const clkout0_ctrl_out0_parents[] = {
"hsdiv4_16fft_main_2_hsdivout1_clk",
- "hsdiv4_16fft_main_2_hsdivout1_clk",
+ "hsdiv4_16fft_main_2_hsdivout1_clk10",
};
static const char * const clk_32k_rc_sel_out0_parents[] = {
@@ -195,6 +195,7 @@
CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
@@ -313,7 +314,7 @@
DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(157, 20, "clkout0_ctrl_out0"),
DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
- DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk10"),
DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(157, 25, "board_0_ddr0_ck0_out"),
DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 04aa2fd..8971e2d 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -58,6 +58,15 @@
including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
Gigabit Ethernet, I2C, built-in 4x4 Wi-Fi, and PCIe.
+config TARGET_MT7988
+ bool "MediaTek MT7988 SoC"
+ select ARM64
+ select CPU
+ help
+ The MediaTek MT7988 is a ARM64-based SoC with a quad-core Cortex-A73.
+ including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
+ 10 Gigabit Ethernet , I2C, and PCIe.
+
config TARGET_MT8183
bool "MediaTek MT8183 SoC"
select ARM64
@@ -104,6 +113,7 @@
default "mt7629" if TARGET_MT7629
default "mt7981" if TARGET_MT7981
default "mt7986" if TARGET_MT7986
+ default "mt7988" if TARGET_MT7988
default "mt8183" if TARGET_MT8183
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
@@ -121,6 +131,7 @@
default "mt7629" if TARGET_MT7629
default "mt7981" if TARGET_MT7981
default "mt7986" if TARGET_MT7986
+ default "mt7988" if TARGET_MT7988
default "mt8183" if TARGET_MT8183
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
@@ -135,7 +146,7 @@
string
default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
- default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
+ default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988
default "lk=1" if TARGET_MT7623
endif
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index fc85293..71aa341 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -9,6 +9,7 @@
obj-$(CONFIG_TARGET_MT7629) += mt7629/
obj-$(CONFIG_TARGET_MT7981) += mt7981/
obj-$(CONFIG_TARGET_MT7986) += mt7986/
+obj-$(CONFIG_TARGET_MT7988) += mt7988/
obj-$(CONFIG_TARGET_MT8183) += mt8183/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
obj-$(CONFIG_TARGET_MT8518) += mt8518/
diff --git a/arch/arm/mach-mediatek/mt7622/init.c b/arch/arm/mach-mediatek/mt7622/init.c
index e501907..00d3eb9 100644
--- a/arch/arm/mach-mediatek/mt7622/init.c
+++ b/arch/arm/mach-mediatek/mt7622/init.c
@@ -4,11 +4,15 @@
* Author: Sam Shih <sam.shih@mediatek.com>
*/
-#include <common.h>
#include <fdtdec.h>
#include <init.h>
#include <asm/armv8/mmu.h>
-#include <asm/cache.h>
+#include <asm/system.h>
+#include <asm/global_data.h>
+#include <asm/u-boot.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
int print_cpuinfo(void)
{
@@ -20,11 +24,13 @@
{
int ret;
- ret = fdtdec_setup_memory_banksize();
+ ret = fdtdec_setup_mem_size_base();
if (ret)
return ret;
- return fdtdec_setup_mem_size_base();
+ gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G);
+
+ return 0;
}
void reset_cpu(void)
diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c
index 3c921d6..862f0ca 100644
--- a/arch/arm/mach-mediatek/mt7981/init.c
+++ b/arch/arm/mach-mediatek/mt7981/init.c
@@ -4,18 +4,25 @@
* Author: Sam Shih <sam.shih@mediatek.com>
*/
-#include <cpu_func.h>
+#include <fdtdec.h>
#include <init.h>
#include <asm/armv8/mmu.h>
#include <asm/system.h>
#include <asm/global_data.h>
+#include <asm/u-boot.h>
#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
+ int ret;
+
+ ret = fdtdec_setup_mem_size_base();
+ if (ret)
+ return ret;
+
+ gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_1G);
return 0;
}
diff --git a/arch/arm/mach-mediatek/mt7986/init.c b/arch/arm/mach-mediatek/mt7986/init.c
index 9d0c0cd..905a3ab 100644
--- a/arch/arm/mach-mediatek/mt7986/init.c
+++ b/arch/arm/mach-mediatek/mt7986/init.c
@@ -4,18 +4,25 @@
* Author: Sam Shih <sam.shih@mediatek.com>
*/
-#include <cpu_func.h>
+#include <fdtdec.h>
#include <init.h>
#include <asm/armv8/mmu.h>
#include <asm/system.h>
#include <asm/global_data.h>
+#include <asm/u-boot.h>
#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
+ int ret;
+
+ ret = fdtdec_setup_mem_size_base();
+ if (ret)
+ return ret;
+
+ gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G);
return 0;
}
diff --git a/arch/arm/mach-mediatek/mt7988/Makefile b/arch/arm/mach-mediatek/mt7988/Makefile
new file mode 100644
index 0000000..007eb4a
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7988/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o
diff --git a/arch/arm/mach-mediatek/mt7988/init.c b/arch/arm/mach-mediatek/mt7988/init.c
new file mode 100644
index 0000000..082f12b
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7988/init.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+#include <asm/u-boot.h>
+#include <asm/system.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SZ_8G _AC(0x200000000, ULL)
+
+int dram_init(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_mem_size_base();
+ if (ret)
+ return ret;
+
+ gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_8G);
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = gd->ram_base;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
+
+static struct mm_region mt7988_mem_map[] = {
+ {
+ /* DDR */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x200000000ULL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+ }, {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ 0,
+ }
+};
+
+struct mm_region *mem_map = mt7988_mem_map;
diff --git a/arch/arm/mach-mediatek/mt7988/lowlevel_init.S b/arch/arm/mach-mediatek/mt7988/lowlevel_init.S
new file mode 100644
index 0000000..2ae3cc4
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7988/lowlevel_init.S
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/*
+ * Switch from AArch64 EL2 to AArch32 EL2
+ * @param inputs:
+ * x0: argument, zero
+ * x1: machine nr
+ * x2: fdt address
+ * x3: input argument
+ * x4: kernel entry point
+ * @param outputs for secure firmware:
+ * x0: function id
+ * x1: kernel entry point
+ * x2: machine nr
+ * x3: fdt address
+*/
+
+.global armv8_el2_to_aarch32
+armv8_el2_to_aarch32:
+ mov x3, x2
+ mov x2, x1
+ mov x1, x4
+ mov x4, #0
+ ldr x0, =0x82000200
+ SMC #0
+ ret
diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c
index d3a9573..4c67f1a 100644
--- a/arch/arm/mach-mvebu/arm64-common.c
+++ b/arch/arm/mach-mvebu/arm64-common.c
@@ -30,7 +30,7 @@
*/
#define USABLE_RAM_SIZE 0x80000000ULL
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
unsigned long top = CFG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE);
diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index fadb6eb..4eddba5 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -25,6 +25,13 @@
spl/u-boot-spl.srec: spl/u-boot-spl FORCE
$(call if_changed,objcopy)
+srec_cat_gte_160 := ${shell expr `srec_cat -VERSION | grep ^srec_cat | sed 's/^.* //g' | cut -f1-2 -d.` \>= "1.60"}
+ifeq "$(srec_cat_gte_160)" "1"
+ srec_cat_le_cmd := "-constant-l-e"
+else
+ srec_cat_le_cmd := "-l-e-constant"
+endif
+
ifneq ($(CONFIG_R8A774C0)$(CONFIG_R8A77990)$(CONFIG_R8A77995),)
#
# The first 6 generate statements generate the R-Car Gen3 SCIF loader header.
@@ -52,34 +59,34 @@
cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
-offset -0x13fd0 \
-Output_Block_Size 16 \
- -generate 0xe6300400 0xe6300404 -l-e-constant 0x0 4 \
- -generate 0xe630048c 0xe6300490 -l-e-constant 0x0 4 \
- -generate 0xe63005d4 0xe63005d8 -l-e-constant 0xe6304000 4 \
- -generate 0xe63006e4 0xe63006e8 -l-e-constant $2 4 \
- -generate 0xe6301154 0xe6301158 -l-e-constant 0xe6304000 4 \
- -generate 0xe6301264 0xe6301268 -l-e-constant $2 4 \
- -generate 0xe6304000 0xe6304004 -l-e-constant 0xd2bcc000 4 \
- -generate 0xe6304004 0xe6304008 -l-e-constant 0xb26c0400 4 \
- -generate 0xe6304008 0xe630400c -l-e-constant 0xb2720001 4 \
- -generate 0xe630400c 0xe6304010 -l-e-constant 0xb27c0421 4 \
- -generate 0xe6304010 0xe6304014 -l-e-constant 0xb2710402 4 \
- -generate 0xe6304014 0xe6304018 -l-e-constant 0xaa0203e0 4 \
- -generate 0xe6304018 0xe630401c -l-e-constant 0xd28e0003 4 \
- -generate 0xe630401c 0xe6304020 -l-e-constant 0xa8c11424 4 \
- -generate 0xe6304020 0xe6304024 -l-e-constant 0xa8811444 4 \
- -generate 0xe6304024 0xe6304028 -l-e-constant 0xf1004063 4 \
- -generate 0xe6304028 0xe630402c -l-e-constant 0x54ffffaa 4 \
- -generate 0xe630402c 0xe6304030 -l-e-constant 0xd61f0000 4
+ -generate 0xe6300400 0xe6300404 $(srec_cat_le_cmd) 0x0 4 \
+ -generate 0xe630048c 0xe6300490 $(srec_cat_le_cmd) 0x0 4 \
+ -generate 0xe63005d4 0xe63005d8 $(srec_cat_le_cmd) 0xe6304000 4 \
+ -generate 0xe63006e4 0xe63006e8 $(srec_cat_le_cmd) $2 4 \
+ -generate 0xe6301154 0xe6301158 $(srec_cat_le_cmd) 0xe6304000 4 \
+ -generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4 \
+ -generate 0xe6304000 0xe6304004 $(srec_cat_le_cmd) 0xd2bcc000 4 \
+ -generate 0xe6304004 0xe6304008 $(srec_cat_le_cmd) 0xb26c0400 4 \
+ -generate 0xe6304008 0xe630400c $(srec_cat_le_cmd) 0xb2720001 4 \
+ -generate 0xe630400c 0xe6304010 $(srec_cat_le_cmd) 0xb27c0421 4 \
+ -generate 0xe6304010 0xe6304014 $(srec_cat_le_cmd) 0xb2710402 4 \
+ -generate 0xe6304014 0xe6304018 $(srec_cat_le_cmd) 0xaa0203e0 4 \
+ -generate 0xe6304018 0xe630401c $(srec_cat_le_cmd) 0xd28e0003 4 \
+ -generate 0xe630401c 0xe6304020 $(srec_cat_le_cmd) 0xa8c11424 4 \
+ -generate 0xe6304020 0xe6304024 $(srec_cat_le_cmd) 0xa8811444 4 \
+ -generate 0xe6304024 0xe6304028 $(srec_cat_le_cmd) 0xf1004063 4 \
+ -generate 0xe6304028 0xe630402c $(srec_cat_le_cmd) 0x54ffffaa 4 \
+ -generate 0xe630402c 0xe6304030 $(srec_cat_le_cmd) 0xd61f0000 4
else
quiet_cmd_srec_cat = SRECCAT $@
cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
-Output_Block_Size 16 \
- -generate 0xe6300400 0xe6300404 -l-e-constant 0x0 4 \
- -generate 0xe630048c 0xe6300490 -l-e-constant 0x0 4 \
- -generate 0xe63005d4 0xe63005d8 -l-e-constant $(CONFIG_SPL_TEXT_BASE) 4 \
- -generate 0xe63006e4 0xe63006e8 -l-e-constant $2 4 \
- -generate 0xe6301154 0xe6301158 -l-e-constant $(CONFIG_SPL_TEXT_BASE) 4 \
- -generate 0xe6301264 0xe6301268 -l-e-constant $2 4
+ -generate 0xe6300400 0xe6300404 $(srec_cat_le_cmd) 0x0 4 \
+ -generate 0xe630048c 0xe6300490 $(srec_cat_le_cmd) 0x0 4 \
+ -generate 0xe63005d4 0xe63005d8 $(srec_cat_le_cmd) $(CONFIG_SPL_TEXT_BASE) 4 \
+ -generate 0xe63006e4 0xe63006e8 $(srec_cat_le_cmd) $2 4 \
+ -generate 0xe6301154 0xe6301158 $(srec_cat_le_cmd) $(CONFIG_SPL_TEXT_BASE) 4 \
+ -generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4
endif
spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index 1d33e2a..7651e43 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -86,7 +86,7 @@
int i = 0;
u32 cpu_type = rmobile_get_cpu_type();
- for (; i < ARRAY_SIZE(rmobile_cpuinfo); i++)
+ for (; i < ARRAY_SIZE(rmobile_cpuinfo) - 1; i++)
if (rmobile_cpuinfo[i].cpu_type == cpu_type)
break;
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 49da93d..03c2b37 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -359,6 +359,7 @@
select PMIC_RK8XX
select BOARD_LATE_INIT
imply ROCKCHIP_COMMON_BOARD
+ imply OF_LIBFDT_OVERLAY
imply TPL_DM
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
@@ -469,7 +470,7 @@
config ROCKCHIP_SPL_RESERVE_IRAM
hex "Size of IRAM reserved in SPL"
- default 0
+ default 0x0
help
SPL may need reserve memory for firmware loaded by SPL, whose load
address is in IRAM and may overlay with SPL text area if not
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index a7cc91a..cbd2ea0 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -280,15 +280,5 @@
if (cru->glb_rst_st != 0)
rk3399_force_power_on_reset();
}
-
- if (IS_ENABLED(CONFIG_SPL_DM_REGULATOR)) {
- /*
- * Turning the eMMC and SPI back on (if disabled via the Qseven
- * BIOS_ENABLE) signal is done through a always-on regulator).
- */
- if (regulators_enable_boot_on(false))
- debug("%s: Cannot enable boot on regulator\n",
- __func__);
- }
}
#endif
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 1d17a74..99ecbdc 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -216,7 +216,7 @@
return 0;
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
index 30be640..87280e2 100644
--- a/arch/arm/mach-rockchip/spl.c
+++ b/arch/arm/mach-rockchip/spl.c
@@ -112,19 +112,6 @@
{
int ret;
-#ifdef CONFIG_DEBUG_UART
- /*
- * Debug UART can be used from here if required:
- *
- * debug_uart_init();
- * printch('a');
- * printhex8(0x1234);
- * printascii("string");
- */
- debug_uart_init();
- debug("\nspl:debug uart enabled in %s\n", __func__);
-#endif
-
board_early_init_f();
ret = spl_early_init();
diff --git a/arch/arm/mach-stm32mp/boot_params.c b/arch/arm/mach-stm32mp/boot_params.c
index 24d04dc..158bf40 100644
--- a/arch/arm/mach-stm32mp/boot_params.c
+++ b/arch/arm/mach-stm32mp/boot_params.c
@@ -29,7 +29,7 @@
return (void *)nt_fw_dtb;
log_debug("%s: DTB not found.\n", __func__);
}
- log_debug("%s: fall back to builtin DTB, %p\n", __func__, &_end);
+ log_debug("%s: fall back to builtin DTB, %p\n", __func__, _end);
- return (void *)&_end;
+ return (void *)_end;
}
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c
index 80ba5c2..7f37b0d 100644
--- a/arch/arm/mach-stm32mp/dram_init.c
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -40,7 +40,7 @@
return 0;
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
phys_size_t size;
phys_addr_t reg;
diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c
index 39b5200..8cdeb0a 100644
--- a/arch/arm/mach-stm32mp/psci.c
+++ b/arch/arm/mach-stm32mp/psci.c
@@ -729,7 +729,7 @@
setbits_le32(STM32_RCC_BASE + RCC_MP_CIER, RCC_MP_CIFR_WKUPF);
setbits_le32(STM32_PWR_BASE + PWR_MPUCR,
- PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_PDDS);
+ PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS);
saved_mcudivr = readl(STM32_RCC_BASE + RCC_MCUDIVR);
saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR);
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index e20c3a3..9d5df2c 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -568,7 +568,7 @@
config DRAM_TPR3
hex "sunxi dram tpr3 value"
- default 0
+ default 0x0
---help---
Set the dram controller tpr3 parameter. This parameter configures
the delay on the command lane and also phase shifts, which are
@@ -579,7 +579,7 @@
config DRAM_DQS_GATING_DELAY
hex "sunxi dram dqs_gating_delay value"
- default 0
+ default 0x0
---help---
Set the dram controller dqs_gating_delay parmeter. Each byte
encodes the DQS gating delay for each byte lane. The delay
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 391a65a..78597ad 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -64,7 +64,7 @@
};
struct mm_region *mem_map = sunxi_mem_map;
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
/* Some devices (like the EMAC) have a 32-bit DMA limit. */
if (gd->ram_top > (1ULL << 32))
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 9147050..a5733b0 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -32,6 +32,10 @@
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
obj-y += pmc.o
+ifndef CONFIG_TEGRA186
+obj-y += fuse.o
+endif
+
obj-$(CONFIG_TEGRA20) += tegra20/
obj-$(CONFIG_TEGRA30) += tegra30/
obj-$(CONFIG_TEGRA114) += tegra114/
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 0df1836..981768b 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -403,7 +403,7 @@
* This function is called before dram_init_banksize(), so we can't simply
* return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
ulong ram_top;
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
new file mode 100644
index 0000000..83bd505
--- /dev/null
+++ b/arch/arm/mach-tegra/fuse.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2012-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2022
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <common.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+
+#include <asm/arch/tegra.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/clock.h>
+#include <asm/arch-tegra/fuse.h>
+
+#include "cpu.h"
+
+#define FUSE_UID_LOW 0x108
+#define FUSE_UID_HIGH 0x10c
+
+#define FUSE_VENDOR_CODE 0x200
+#define FUSE_FAB_CODE 0x204
+#define FUSE_LOT_CODE_0 0x208
+#define FUSE_LOT_CODE_1 0x20c
+#define FUSE_WAFER_ID 0x210
+#define FUSE_X_COORDINATE 0x214
+#define FUSE_Y_COORDINATE 0x218
+
+#define FUSE_VENDOR_CODE_MASK 0xf
+#define FUSE_FAB_CODE_MASK 0x3f
+#define FUSE_WAFER_ID_MASK 0x3f
+#define FUSE_X_COORDINATE_MASK 0x1ff
+#define FUSE_Y_COORDINATE_MASK 0x1ff
+
+static u32 tegra_fuse_readl(unsigned long offset)
+{
+ return readl(NV_PA_FUSE_BASE + offset);
+}
+
+static void tegra_fuse_init(void)
+{
+ u32 reg;
+
+ /*
+ * Performed by downstream and is not
+ * documented by TRM. Whithout setting
+ * this bit fuse region will not work.
+ */
+ reg = readl_relaxed(NV_PA_CLK_RST_BASE + 0x48);
+ reg |= BIT(28);
+ writel(reg, NV_PA_CLK_RST_BASE + 0x48);
+
+ clock_enable(PERIPH_ID_FUSE);
+ udelay(2);
+ reset_set_enable(PERIPH_ID_FUSE, 0);
+}
+
+unsigned long long tegra_chip_uid(void)
+{
+ u64 uid = 0ull;
+ u32 reg;
+ u32 cid;
+ u32 vendor;
+ u32 fab;
+ u32 lot;
+ u32 wafer;
+ u32 x;
+ u32 y;
+ u32 i;
+
+ tegra_fuse_init();
+
+ /* This used to be so much easier in prior chips. Unfortunately, there
+ is no one-stop shopping for the unique id anymore. It must be
+ constructed from various bits of information burned into the fuses
+ during the manufacturing process. The 64-bit unique id is formed
+ by concatenating several bit fields. The notation used for the
+ various fields is <fieldname:size_in_bits> with the UID composed
+ thusly:
+ <CID:4><VENDOR:4><FAB:6><LOT:26><WAFER:6><X:9><Y:9>
+ Where:
+ Field Bits Position Data
+ ------- ---- -------- ----------------------------------------
+ CID 4 60 Chip id
+ VENDOR 4 56 Vendor code
+ FAB 6 50 FAB code
+ LOT 26 24 Lot code (5-digit base-36-coded-decimal,
+ re-encoded to 26 bits binary)
+ WAFER 6 18 Wafer id
+ X 9 9 Wafer X-coordinate
+ Y 9 0 Wafer Y-coordinate
+ ------- ----
+ Total 64
+ */
+
+ switch (tegra_get_chip()) {
+ case CHIPID_TEGRA20:
+ /* T20 has simple calculation */
+ return ((unsigned long long)tegra_fuse_readl(FUSE_UID_HIGH) << 32ull) |
+ (unsigned long long)tegra_fuse_readl(FUSE_UID_LOW);
+ case CHIPID_TEGRA30:
+ /* T30 chip id is 0 */
+ cid = 0;
+ break;
+ case CHIPID_TEGRA114:
+ /* T11x chip id is 1 */
+ cid = 1;
+ break;
+ case CHIPID_TEGRA124:
+ /* T12x chip id is 3 */
+ cid = 3;
+ break;
+ case CHIPID_TEGRA210:
+ /* T210 chip id is 5 */
+ cid = 5;
+ default:
+ return 0;
+ }
+
+ vendor = tegra_fuse_readl(FUSE_VENDOR_CODE) & FUSE_VENDOR_CODE_MASK;
+ fab = tegra_fuse_readl(FUSE_FAB_CODE) & FUSE_FAB_CODE_MASK;
+
+ /* Lot code must be re-encoded from a 5 digit base-36 'BCD' number
+ to a binary number. */
+ lot = 0;
+ reg = tegra_fuse_readl(FUSE_LOT_CODE_0) << 2;
+
+ for (i = 0; i < 5; ++i) {
+ u32 digit = (reg & 0xFC000000) >> 26;
+ lot *= 36;
+ lot += digit;
+ reg <<= 6;
+ }
+
+ wafer = tegra_fuse_readl(FUSE_WAFER_ID) & FUSE_WAFER_ID_MASK;
+ x = tegra_fuse_readl(FUSE_X_COORDINATE) & FUSE_X_COORDINATE_MASK;
+ y = tegra_fuse_readl(FUSE_Y_COORDINATE) & FUSE_Y_COORDINATE_MASK;
+
+ uid = ((unsigned long long)cid << 60ull)
+ | ((unsigned long long)vendor << 56ull)
+ | ((unsigned long long)fab << 50ull)
+ | ((unsigned long long)lot << 24ull)
+ | ((unsigned long long)wafer << 18ull)
+ | ((unsigned long long)x << 9ull)
+ | ((unsigned long long)y << 0ull);
+
+ return uid;
+}
diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig
index 85b8ce2..3e478b3 100644
--- a/arch/arm/mach-tegra/tegra30/Kconfig
+++ b/arch/arm/mach-tegra/tegra30/Kconfig
@@ -20,10 +20,26 @@
bool "Toradex Colibri T30 board"
select BOARD_LATE_INIT
+config TARGET_ENDEAVORU
+ bool "HTC Endeavoru T30 board"
+ select BOARD_LATE_INIT
+
+config TARGET_GROUPER
+ bool "Asus and Google Grouper board"
+ select BOARD_LATE_INIT
+
config TARGET_TEC_NG
bool "Avionic Design TEC-NG board"
select BOARD_LATE_INIT
+config TARGET_TRANSFORMER_T30
+ bool "Asus Tegra30 Transformer board"
+ select BOARD_LATE_INIT
+
+config TARGET_X3_T30
+ bool "LG X3 Tegra30 board"
+ select BOARD_LATE_INIT
+
endchoice
config SYS_SOC
@@ -33,6 +49,10 @@
source "board/nvidia/beaver/Kconfig"
source "board/nvidia/cardhu/Kconfig"
source "board/toradex/colibri_t30/Kconfig"
+source "board/htc/endeavoru/Kconfig"
+source "board/asus/grouper/Kconfig"
source "board/avionic-design/tec-ng/Kconfig"
+source "board/asus/transformer-t30/Kconfig"
+source "board/lg/x3-t30/Kconfig"
endif
diff --git a/arch/microblaze/include/asm/processor.h b/arch/microblaze/include/asm/processor.h
index 958018c..c0423ea 100644
--- a/arch/microblaze/include/asm/processor.h
+++ b/arch/microblaze/include/asm/processor.h
@@ -6,11 +6,6 @@
#ifndef __ASM_MICROBLAZE_PROCESSOR_H
#define __ASM_MICROBLAZE_PROCESSOR_H
-/* References to section boundaries */
-
-extern char _end[];
-extern char __text_start[];
-
/* Microblaze board initialization function */
void board_init(void);
diff --git a/arch/mips/lib/reloc.c b/arch/mips/lib/reloc.c
index 67c8af2..9cf6809 100644
--- a/arch/mips/lib/reloc.c
+++ b/arch/mips/lib/reloc.c
@@ -146,7 +146,7 @@
/* Clear the .bss section */
bss_start = (uint8_t *)((unsigned long)__bss_start + off);
- bss_len = (unsigned long)&__bss_end - (unsigned long)__bss_start;
+ bss_len = (unsigned long)__bss_end - (unsigned long)__bss_start;
memset(bss_start, 0, bss_len);
/* Jump to the relocated U-Boot */
diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c
index 15d1eff..56fdf04 100644
--- a/arch/mips/mach-jz47xx/jz4780/jz4780.c
+++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c
@@ -42,7 +42,7 @@
enable_caches();
/* Clear the BSS */
- memset(__bss_start, 0, (char *)&__bss_end - __bss_start);
+ memset(__bss_start, 0, (size_t)__bss_end - (size_t)__bss_start);
gd->flags |= GD_FLG_SPL_INIT;
@@ -76,7 +76,7 @@
}
#endif /* CONFIG_SPL_BUILD */
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return CFG_SYS_SDRAM_BASE + (256 * 1024 * 1024);
}
diff --git a/arch/mips/mach-mtmips/mt7621/spl/launch.c b/arch/mips/mach-mtmips/mt7621/spl/launch.c
index 37c20a5..95dd659 100644
--- a/arch/mips/mach-mtmips/mt7621/spl/launch.c
+++ b/arch/mips/mach-mtmips/mt7621/spl/launch.c
@@ -70,7 +70,7 @@
cpumask = 0x0f;
/* Make BootROM/TPL redirect Core1's bootup flow to our entry point */
- writel((uintptr_t)&_start, sysc + BOOT_SRAM_BASE_REG);
+ writel((uintptr_t)_start, sysc + BOOT_SRAM_BASE_REG);
bootup_secondary_core();
}
diff --git a/arch/mips/mach-mtmips/mt7621/spl/spl.c b/arch/mips/mach-mtmips/mt7621/spl/spl.c
index aa5b267..25b409e 100644
--- a/arch/mips/mach-mtmips/mt7621/spl/spl.c
+++ b/arch/mips/mach-mtmips/mt7621/spl/spl.c
@@ -86,7 +86,7 @@
uint32_t spl_nand_get_uboot_raw_page(void)
{
- const struct stage_header *sh = (const struct stage_header *)&_start;
+ const struct stage_header *sh = (const struct stage_header *)_start;
u32 addr;
addr = image_get_header_size() + be32_to_cpu(sh->stage_size);
diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c
index 85cb084..5b1311d 100644
--- a/arch/mips/mach-octeon/dram.c
+++ b/arch/mips/mach-octeon/dram.c
@@ -77,7 +77,7 @@
return UBOOT_RAM_SIZE_MAX;
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
if (IS_ENABLED(CONFIG_RAM_OCTEON)) {
/* Map a maximum of 256MiB - return not size but address */
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index bd2af8d..1731c96 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -94,7 +94,7 @@
config SYS_SYPCR
hex "SYPCR register" if !WDT_MPC8xxx
- default 0
+ default 0x0
help
System Protection Control (11-9)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 867cbcb..6771d8d 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -64,6 +64,14 @@
help
Do not enable data cache in SPL.
+config SPL_ZERO_MEM_BEFORE_USE
+ bool "Zero memory before use"
+ depends on SPL
+ default n
+ help
+ Zero stack/GD/malloc area in SPL before using them, this is needed for
+ Sifive core devices that uses L2 cache to store SPL.
+
# board-specific options below
source "board/AndesTech/ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c
index 44e11bd..94d8018 100644
--- a/arch/riscv/cpu/fu540/dram.c
+++ b/arch/riscv/cpu/fu540/dram.c
@@ -21,7 +21,7 @@
return fdtdec_setup_memory_banksize();
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
/*
* Ensure that we run from first 4GB so that all
diff --git a/arch/riscv/cpu/fu740/dram.c b/arch/riscv/cpu/fu740/dram.c
index d6d4a41..8657fcd 100644
--- a/arch/riscv/cpu/fu740/dram.c
+++ b/arch/riscv/cpu/fu740/dram.c
@@ -20,7 +20,7 @@
return fdtdec_setup_memory_banksize();
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
#ifdef CONFIG_64BIT
/*
diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c
index 44e11bd..94d8018 100644
--- a/arch/riscv/cpu/generic/dram.c
+++ b/arch/riscv/cpu/generic/dram.c
@@ -21,7 +21,7 @@
return fdtdec_setup_memory_banksize();
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
/*
* Ensure that we run from first 4GB so that all
diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
index 4d95811..8469ee7 100644
--- a/arch/riscv/cpu/jh7110/Kconfig
+++ b/arch/riscv/cpu/jh7110/Kconfig
@@ -13,6 +13,8 @@
select SUPPORT_SPL
select SPL_RAM if SPL
select SPL_STARFIVE_DDR
+ select SYS_CACHE_SHIFT_6
+ select SPL_ZERO_MEM_BEFORE_USE
select PINCTRL_STARFIVE_JH7110
imply MMC
imply MMC_BROKEN_CD
diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c
index 2ad3f20..1a9fa46 100644
--- a/arch/riscv/cpu/jh7110/dram.c
+++ b/arch/riscv/cpu/jh7110/dram.c
@@ -21,7 +21,7 @@
return fdtdec_setup_memory_banksize();
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
/*
* Ensure that we run from first 4GB so that all
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 72adcef..4047b10 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -13,7 +13,6 @@
#include <init.h>
#define CSR_U74_FEATURE_DISABLE 0x7c1
-#define L2_LIM_MEM_END 0x81FFFFFUL
DECLARE_GLOBAL_DATA_PTR;
@@ -59,9 +58,6 @@
void harts_early_init(void)
{
- ulong *ptr;
- u8 *tmp;
- ulong len, remain;
/*
* Feature Disable CSR
*
@@ -70,25 +66,4 @@
*/
if (CONFIG_IS_ENABLED(RISCV_MMODE))
csr_write(CSR_U74_FEATURE_DISABLE, 0);
-
- /* clear L2 LIM memory
- * set __bss_end to 0x81FFFFF region to zero
- * The L2 Cache Controller supports ECC. ECC is applied to SRAM.
- * If it is not cleared, the ECC part is invalid, and an ECC error
- * will be reported when reading data.
- */
- ptr = (ulong *)&__bss_end;
- len = L2_LIM_MEM_END - (ulong)&__bss_end;
- remain = len % sizeof(ulong);
- len /= sizeof(ulong);
-
- while (len--)
- *ptr++ = 0;
-
- /* clear the remain bytes */
- if (remain) {
- tmp = (u8 *)ptr;
- while (remain--)
- *tmp++ = 0;
- }
}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 59d58a5..30cf674 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -111,6 +111,18 @@
* It's essential before any function call, otherwise, we get data-race.
*/
+/* clear stack if necessary */
+#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE)
+clear_stack:
+ li t1, 1
+ slli t1, t1, CONFIG_STACK_SIZE_SHIFT
+ sub t1, sp, t1
+clear_stack_loop:
+ SREG zero, 0(t1) /* t1 is always 16 byte aligned */
+ addi t1, t1, REGBYTES
+ blt t1, sp, clear_stack_loop
+#endif
+
call_board_init_f_0:
/* find top of reserve space */
#if CONFIG_IS_ENABLED(SMP)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index b90e7f8..e40f57a 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -7,6 +7,7 @@
#include "jh7110.dtsi"
#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
serial0 = &uart0;
@@ -308,6 +309,16 @@
};
};
+&pcie0 {
+ reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie1 {
+ reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
&syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
<&syscrg JH7110_SYSCLK_BUS_ROOT>,
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 825fbb7..081b833 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -648,5 +648,79 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+ pcie0: pcie@2b000000 {
+ compatible = "starfive,jh7110-pcie";
+ reg = <0x0 0x2b000000 0x0 0x1000000
+ 0x9 0x40000000 0x0 0x10000000>;
+ reg-names = "reg", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
+ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
+ interrupts = <56>;
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+ <0x0 0x0 0x0 0x2 &plic 0x2>,
+ <0x0 0x0 0x0 0x3 &plic 0x3>,
+ <0x0 0x0 0x0 0x4 &plic 0x4>;
+ msi-parent = <&plic>;
+ device_type = "pci";
+ starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
+ bus-range = <0x0 0xff>;
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE0_TL>,
+ <&stgcrg JH7110_STGCLK_PCIE0_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE0_APB>;
+ clock-names = "noc", "tl", "axi", "apb";
+ resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
+ <&stgcrg JH7110_STGRST_PCIE0_SLV0>,
+ <&stgcrg JH7110_STGRST_PCIE0_SLV>,
+ <&stgcrg JH7110_STGRST_PCIE0_BRG>,
+ <&stgcrg JH7110_STGRST_PCIE0_CORE>,
+ <&stgcrg JH7110_STGRST_PCIE0_APB>;
+ reset-names = "mst0", "slv0", "slv", "brg",
+ "core", "apb";
+ status = "disabled";
+ };
+
+ pcie1: pcie@2c000000 {
+ compatible = "starfive,jh7110-pcie";
+ reg = <0x0 0x2c000000 0x0 0x1000000
+ 0x9 0xc0000000 0x0 0x10000000>;
+ reg-names = "reg", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
+ <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
+ interrupts = <57>;
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+ <0x0 0x0 0x0 0x2 &plic 0x2>,
+ <0x0 0x0 0x0 0x3 &plic 0x3>,
+ <0x0 0x0 0x0 0x4 &plic 0x4>;
+ msi-parent = <&plic>;
+ device_type = "pci";
+ starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
+ bus-range = <0x0 0xff>;
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE1_TL>,
+ <&stgcrg JH7110_STGCLK_PCIE1_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE1_APB>;
+ clock-names = "noc", "tl", "axi", "apb";
+ resets = <&stgcrg JH7110_STGRST_PCIE1_MST0>,
+ <&stgcrg JH7110_STGRST_PCIE1_SLV0>,
+ <&stgcrg JH7110_STGRST_PCIE1_SLV>,
+ <&stgcrg JH7110_STGRST_PCIE1_BRG>,
+ <&stgcrg JH7110_STGRST_PCIE1_CORE>,
+ <&stgcrg JH7110_STGRST_PCIE1_APB>;
+ reset-names = "mst0", "slv0", "slv", "brg",
+ "core", "apb";
+ status = "disabled";
+ };
};
};
diff --git a/arch/riscv/include/asm/acpi_table.h b/arch/riscv/include/asm/acpi_table.h
new file mode 100644
index 0000000..cd85199
--- /dev/null
+++ b/arch/riscv/include/asm/acpi_table.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __ASM_ACPI_TABLE_H__
+#define __ASM_ACPI_TABLE_H__
+
+/*
+ * This file is needed by some drivers.
+ * We will fill it when adding ACPI support for RISC-V.
+ */
+
+#endif /* __ASM_ACPI_TABLE_H__ */
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 7693699..009a268 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -31,6 +31,8 @@
SBI_EXT_DBCN = 0x4442434E,
SBI_EXT_SUSP = 0x53555350,
SBI_EXT_CPPC = 0x43505043,
+ SBI_EXT_NACL = 0x4E41434C,
+ SBI_EXT_STA = 0x535441,
};
enum sbi_ext_base_fid {
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 9e93a0f..85d0d6a 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -258,6 +258,30 @@
return 0;
}
+int os_persistent_file(char *buf, int maxsize, const char *fname)
+{
+ const char *dirname = getenv("U_BOOT_PERSISTENT_DATA_DIR");
+ char *ptr;
+ int len;
+
+ len = strlen(fname) + (dirname ? strlen(dirname) + 1 : 0) + 1;
+ if (len > maxsize)
+ return -ENOSPC;
+
+ ptr = buf;
+ if (dirname) {
+ strcpy(ptr, dirname);
+ ptr += strlen(dirname);
+ *ptr++ = '/';
+ }
+ strcpy(ptr, fname);
+
+ if (access(buf, F_OK) == -1)
+ return -ENOENT;
+
+ return 0;
+}
+
/* Restore tty state when we exit */
static struct termios orig_term;
static bool term_setup;
diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi
index f0ee0b3..ff7e558 100644
--- a/arch/sandbox/dts/sandbox.dtsi
+++ b/arch/sandbox/dts/sandbox.dtsi
@@ -16,12 +16,6 @@
stdout-path = "/serial";
};
- cedit-theme {
- font-size = <30>;
- menu-inset = <3>;
- menuitem-gap-y = <1>;
- };
-
alarm_wdt: alarm-wdt {
compatible = "sandbox,alarm-wdt";
timeout-sec = <5>;
@@ -36,6 +30,12 @@
bootstd {
compatible = "u-boot,boot-std";
filename-prefixes = "./";
+
+ cedit-theme {
+ font-size = <30>;
+ menu-inset = <3>;
+ menuitem-gap-y = <1>;
+ };
};
buttons {
@@ -451,6 +451,15 @@
thermal {
compatible = "sandbox,thermal";
};
+
+ arm-ffa-emul {
+ compatible = "sandbox,arm-ffa-emul";
+
+ sandbox-arm-ffa {
+ compatible = "sandbox,arm-ffa";
+ };
+ };
+
};
&cros_ec {
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index b5509ee..b48456a 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -39,6 +39,8 @@
mmc1 = "/mmc1";
mmc2 = "/mmc2";
mmc3 = "/mmc3";
+ mmc4 = "/mmc4";
+ mmc5 = "/mmc5";
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
@@ -100,6 +102,12 @@
menuitem-gap-y = <1>;
};
+ cedit-theme {
+ font-size = <30>;
+ menu-inset = <3>;
+ menuitem-gap-y = <1>;
+ };
+
/*
* This is used for the VBE OS-request tests. A FAT filesystem
* created in a partition with the VBE information appearing
@@ -144,12 +152,6 @@
cedit: cedit {
};
- cedit-theme {
- font-size = <30>;
- menu-inset = <3>;
- menuitem-gap-y = <1>;
- };
-
fuzzing-engine {
compatible = "sandbox,fuzzing-engine";
};
@@ -1055,6 +1057,13 @@
filename = "mmc4.img";
};
+ /* This is used for ChromiumOS tests */
+ mmc5 {
+ status = "disabled";
+ compatible = "sandbox,mmc";
+ filename = "mmc5.img";
+ };
+
pch {
compatible = "sandbox,pch";
};
@@ -1831,6 +1840,14 @@
extcon {
compatible = "sandbox,extcon";
};
+
+ arm-ffa-emul {
+ compatible = "sandbox,arm-ffa-emul";
+
+ sandbox-arm-ffa {
+ compatible = "sandbox,arm-ffa";
+ };
+ };
};
#include "sandbox_pmic.dtsi"
diff --git a/arch/sandbox/include/asm/sandbox_arm_ffa.h b/arch/sandbox/include/asm/sandbox_arm_ffa.h
new file mode 100644
index 0000000..be2790f
--- /dev/null
+++ b/arch/sandbox/include/asm/sandbox_arm_ffa.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#ifndef __SANDBOX_ARM_FFA_H
+#define __SANDBOX_ARM_FFA_H
+
+#include <arm_ffa.h>
+
+/*
+ * This header provides public sandbox FF-A emulator declarations
+ * and declarations needed by FF-A sandbox clients
+ */
+
+/* UUIDs strings of the emulated services */
+#define SANDBOX_SERVICE1_UUID "ed32d533-4209-99e6-2d72-cdd998a79cc0"
+#define SANDBOX_SERVICE2_UUID "ed32d544-4209-99e6-2d72-cdd998a79cc0"
+
+/* IDs of the emulated secure partitions (SPs) */
+#define SANDBOX_SP1_ID 0x1245
+#define SANDBOX_SP2_ID 0x9836
+#define SANDBOX_SP3_ID 0x6452
+#define SANDBOX_SP4_ID 0x7814
+
+/* Invalid service UUID (no matching SP) */
+#define SANDBOX_SERVICE3_UUID "55d532ed-0942-e699-722d-c09ca798d9cd"
+
+/* Invalid service UUID (invalid UUID string format) */
+#define SANDBOX_SERVICE4_UUID "32ed-0942-e699-722d-c09ca798d9cd"
+
+/* Number of valid services */
+#define SANDBOX_SP_COUNT_PER_VALID_SERVICE 2
+
+/**
+ * struct ffa_sandbox_data - query ABI state data structure
+ * @data0_size: size of the first argument
+ * @data0: pointer to the first argument
+ * @data1_size>: size of the second argument
+ * @data1: pointer to the second argument
+ *
+ * Used to pass various types of data with different sizes between
+ * the test cases and the sandbox emulator.
+ * The data is for querying FF-A ABIs state.
+ */
+struct ffa_sandbox_data {
+ u32 data0_size; /* size of the first argument */
+ void *data0; /* pointer to the first argument */
+ u32 data1_size; /* size of the second argument */
+ void *data1; /* pointer to the second argument */
+};
+
+/* The sandbox FF-A emulator public functions */
+
+/**
+ * sandbox_query_ffa_emul_state() - Inspect the FF-A ABIs
+ * @queried_func_id: The FF-A function to be queried
+ * @func_data: Pointer to the FF-A function arguments container structure
+ *
+ * Query the status of FF-A ABI specified in the input argument.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int sandbox_query_ffa_emul_state(u32 queried_func_id,
+ struct ffa_sandbox_data *func_data);
+
+#endif
diff --git a/arch/sandbox/include/asm/sandbox_arm_ffa_priv.h b/arch/sandbox/include/asm/sandbox_arm_ffa_priv.h
new file mode 100644
index 0000000..b088182
--- /dev/null
+++ b/arch/sandbox/include/asm/sandbox_arm_ffa_priv.h
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#ifndef __SANDBOX_ARM_FFA_PRV_H
+#define __SANDBOX_ARM_FFA_PRV_H
+
+#include <arm_ffa_priv.h>
+
+/* This header is exclusively used by the Sandbox FF-A driver and emulator */
+
+/* Non-secure physical FF-A instance */
+#define NS_PHYS_ENDPOINT_ID (0)
+
+#define GET_NS_PHYS_ENDPOINT_ID_MASK GENMASK(31, 16)
+#define GET_NS_PHYS_ENDPOINT_ID(x) \
+ ((u16)(FIELD_GET(GET_NS_PHYS_ENDPOINT_ID_MASK, (x))))
+
+/* Helper macro for reading the destination partition ID */
+#define GET_DST_SP_ID_MASK GENMASK(15, 0)
+#define GET_DST_SP_ID(x) \
+ ((u16)(FIELD_GET(GET_DST_SP_ID_MASK, (x))))
+
+/* Helper macro for setting the source partition ID */
+#define PREP_SRC_SP_ID_MASK GENMASK(31, 16)
+#define PREP_SRC_SP_ID(x) \
+ (FIELD_PREP(PREP_SRC_SP_ID_MASK, (x)))
+
+/* Helper macro for setting the destination endpoint ID */
+#define PREP_NS_PHYS_ENDPOINT_ID_MASK GENMASK(15, 0)
+#define PREP_NS_PHYS_ENDPOINT_ID(x) \
+ (FIELD_PREP(PREP_NS_PHYS_ENDPOINT_ID_MASK, (x)))
+
+/* RX/TX buffers minimum size */
+#define RXTX_BUFFERS_MIN_SIZE (RXTX_4K)
+#define RXTX_BUFFERS_MIN_PAGES (1)
+
+/* MBZ registers info */
+
+/* x1-x7 MBZ */
+#define FFA_X1X7_MBZ_CNT (7)
+#define FFA_X1X7_MBZ_REG_START (&res->a1)
+
+/* x4-x7 MBZ */
+#define FFA_X4X7_MBZ_CNT (4)
+#define FFA_X4X7_MBZ_REG_START (&res->a4)
+
+/* x3-x7 MBZ */
+#define FFA_X3X7_MBZ_CNT (5)
+#define FFA_X3_MBZ_REG_START (&res->a3)
+
+/* number of emulated FF-A secure partitions (SPs) */
+#define SANDBOX_PARTITIONS_CNT (4)
+
+/* Binary data of the emulated services UUIDs */
+
+/* service 1 UUID binary data (little-endian format) */
+#define SANDBOX_SERVICE1_UUID_A1 0xed32d533
+#define SANDBOX_SERVICE1_UUID_A2 0x99e64209
+#define SANDBOX_SERVICE1_UUID_A3 0x9cc02d72
+#define SANDBOX_SERVICE1_UUID_A4 0xcdd998a7
+
+/* service 2 UUID binary data (little-endian format) */
+#define SANDBOX_SERVICE2_UUID_A1 0xed32d544
+#define SANDBOX_SERVICE2_UUID_A2 0x99e64209
+#define SANDBOX_SERVICE2_UUID_A3 0x9cc02d72
+#define SANDBOX_SERVICE2_UUID_A4 0xcdd998a7
+
+/**
+ * struct ffa_rxtxpair_info - structure hosting the RX/TX buffers flags
+ * @rxbuf_owned: RX buffer ownership flag (the owner is non secure world)
+ * @rxbuf_mapped: RX buffer mapping flag
+ * @txbuf_owned TX buffer ownership flag
+ * @txbuf_mapped: TX buffer mapping flag
+ * @rxtx_buf_size: RX/TX buffers size
+ *
+ * Hosts the ownership/mapping flags of the RX/TX buffers
+ * When a buffer is owned/mapped its corresponding flag is set to 1 otherwise 0.
+ */
+struct ffa_rxtxpair_info {
+ u8 rxbuf_owned;
+ u8 rxbuf_mapped;
+ u8 txbuf_owned;
+ u8 txbuf_mapped;
+ u32 rxtx_buf_size;
+};
+
+/**
+ * struct sandbox_ffa_emul - emulator data
+ *
+ * @fwk_version: FF-A framework version
+ * @id: u-boot endpoint ID
+ * @partitions: The partitions descriptors structure
+ * @pair: The RX/TX buffers pair
+ * @pair_info: The RX/TX buffers pair flags and size
+ * @test_ffa_data: The data of the FF-A bus under test
+ *
+ * Hosts all the emulated secure world data.
+ */
+struct sandbox_ffa_emul {
+ u32 fwk_version;
+ u16 id;
+ struct ffa_partitions partitions;
+ struct ffa_rxtxpair pair;
+ struct ffa_rxtxpair_info pair_info;
+};
+
+/**
+ * ffa_emul_find() - Finds the FF-A emulator
+ * @dev: the sandbox FF-A device (sandbox-arm-ffa)
+ * @emulp: the FF-A emulator device (sandbox-ffa-emul)
+ * Return:
+ * 0 on success. Otherwise, failure
+ */
+int ffa_emul_find(struct udevice *dev, struct udevice **emulp);
+
+#endif
diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
index 1295121..f477d51 100644
--- a/arch/x86/cpu/broadwell/sdram.c
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -25,7 +25,7 @@
#include <asm/arch/pei_data.h>
#include <asm/arch/pm.h>
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return mrc_common_board_get_usable_ram_top(total_size);
}
diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c
index f4ee4cd..26352df 100644
--- a/arch/x86/cpu/coreboot/sdram.c
+++ b/arch/x86/cpu/coreboot/sdram.c
@@ -27,7 +27,7 @@
* address, and how far U-Boot is moved by relocation are set in the global
* data structure.
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
uintptr_t dest_addr = 0;
int i;
diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c
index 19a25dd6..d8920ef 100644
--- a/arch/x86/cpu/efi/payload.c
+++ b/arch/x86/cpu/efi/payload.c
@@ -27,7 +27,7 @@
* the relocation address, and how far U-Boot is moved by relocation are
* set in the global data structure.
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
struct efi_mem_desc *desc, *end;
struct efi_entry_memmap *map;
diff --git a/arch/x86/cpu/efi/sdram.c b/arch/x86/cpu/efi/sdram.c
index f3086db..56f3326 100644
--- a/arch/x86/cpu/efi/sdram.c
+++ b/arch/x86/cpu/efi/sdram.c
@@ -11,7 +11,7 @@
DECLARE_GLOBAL_DATA_PTR;
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return (ulong)efi_get_ram_base() + gd->ram_size;
}
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 0718aef..95a826d 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -46,7 +46,7 @@
#define CMOS_OFFSET_MRC_SEED_S3 156
#define CMOS_OFFSET_MRC_SEED_CHK 160
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return mrc_common_board_get_usable_ram_top(total_size);
}
diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig
index aa329b0..f8f2f64 100644
--- a/arch/x86/cpu/qemu/Kconfig
+++ b/arch/x86/cpu/qemu/Kconfig
@@ -12,7 +12,7 @@
imply SYS_NS16550
imply USB
imply USB_EHCI_HCD
- imply VIDEO_BOCHS
+ imply VIDEO_VESA
if QEMU
diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c
index 595c397..d83abf0 100644
--- a/arch/x86/cpu/qemu/dram.c
+++ b/arch/x86/cpu/qemu/dram.c
@@ -8,6 +8,7 @@
#include <asm/global_data.h>
#include <asm/post.h>
#include <asm/arch/qemu.h>
+#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -71,7 +72,7 @@
* the relocation address, and how far U-Boot is moved by relocation are
* set in the global data structure.
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return qemu_get_low_memory_size();
}
diff --git a/arch/x86/cpu/qemu/e820.c b/arch/x86/cpu/qemu/e820.c
index 19e54c5..ebfe595 100644
--- a/arch/x86/cpu/qemu/e820.c
+++ b/arch/x86/cpu/qemu/e820.c
@@ -12,6 +12,7 @@
#include <asm/e820.h>
#include <asm/arch/qemu.h>
#include <asm/global_data.h>
+#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 274978c0..7041455 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -48,7 +48,7 @@
pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
}
-static void qemu_chipset_init(void)
+void qemu_chipset_init(void)
{
u16 device, xbcs;
int pam, i;
diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c
index 8b1ee2d..ad98f3e 100644
--- a/arch/x86/cpu/quark/dram.c
+++ b/arch/x86/cpu/quark/dram.c
@@ -184,7 +184,7 @@
* the relocation address, and how far U-Boot is moved by relocation are
* set in the global data structure.
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return gd->ram_size;
}
diff --git a/arch/x86/cpu/slimbootloader/sdram.c b/arch/x86/cpu/slimbootloader/sdram.c
index d748d5c..fbb33b2 100644
--- a/arch/x86/cpu/slimbootloader/sdram.c
+++ b/arch/x86/cpu/slimbootloader/sdram.c
@@ -48,7 +48,7 @@
* @total_size: The memory size that u-boot occupies
* Return: : The top available memory address lower than 4GB
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
struct sbl_memory_map_info *data;
int i;
diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c
index 8a4b1c5..ee74a1f 100644
--- a/arch/x86/cpu/tangier/sdram.c
+++ b/arch/x86/cpu/tangier/sdram.c
@@ -204,7 +204,7 @@
* address, and how far U-Boot is moved by relocation are set in the global
* data structure.
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
struct sfi_table_simple *sb;
struct sfi_mem_entry *mentry;
diff --git a/arch/x86/include/asm/qemu.h b/arch/x86/include/asm/qemu.h
new file mode 100644
index 0000000..f1e95ff
--- /dev/null
+++ b/arch/x86/include/asm/qemu.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Generic QEMU header
+ *
+ * Copyright 2023 Google LLC
+ */
+
+#ifndef __QEMU_H
+#define __QEMU_H
+
+/* set up the chipset for QEMU so that video can be used */
+void qemu_chipset_init(void);
+
+#endif
diff --git a/arch/x86/include/asm/sections.h b/arch/x86/include/asm/sections.h
index a6be360..874a43d 100644
--- a/arch/x86/include/asm/sections.h
+++ b/arch/x86/include/asm/sections.h
@@ -8,4 +8,6 @@
#include <asm-generic/sections.h>
+extern char __data_end[];
+
#endif
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index 02a8b0f..3acc58a 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -77,7 +77,7 @@
void x86_enable_caches(void);
void x86_disable_caches(void);
int x86_init_cache(void);
-phys_size_t board_get_usable_ram_top(phys_size_t total_size);
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size);
int default_print_cpuinfo(void);
/* Set up a UART which can be used with printch(), printhex8(), etc. */
diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h
index 9ad74dc..655675b 100644
--- a/arch/x86/include/asm/zimage.h
+++ b/arch/x86/include/asm/zimage.h
@@ -62,41 +62,4 @@
int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
ulong initrd_addr, ulong initrd_size, ulong cmdline_force);
-/**
- * zimage_dump() - Dump the metadata of a zimage
- *
- * This shows all available information in a zimage that has been loaded.
- *
- * @base_ptr: Pointer to the boot parameters, typically at address
- * DEFAULT_SETUP_BASE
- */
-void zimage_dump(struct boot_params *base_ptr);
-
-/**
- * zboot_start() - Boot a zimage
- *
- * Boot a zimage, given the component parts
- *
- * @addr: Address where the bzImage is moved before booting, either
- * BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR
- * @base: Pointer to the boot parameters, typically at address
- * DEFAULT_SETUP_BASE
- * @initrd: Address of the initial ramdisk, or 0 if none
- * @initrd_size: Size of the initial ramdisk, or 0 if none
- * @cmdline: Command line to use for booting
- * Return: -EFAULT on error (normally it does not return)
- */
-int zboot_start(ulong addr, ulong size, ulong initrd, ulong initrd_size,
- ulong base, char *cmdline);
-
-/*
- * zimage_get_kernel_version() - Get the version string from a kernel
- *
- * @params: boot_params pointer
- * @kernel_base: base address of kernel
- * Return: Kernel version as a NUL-terminated string
- */
-const char *zimage_get_kernel_version(struct boot_params *params,
- void *kernel_base);
-
#endif
diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c
index e29cae7..f146bbd 100644
--- a/arch/x86/lib/bios.c
+++ b/arch/x86/lib/bios.c
@@ -204,7 +204,7 @@
realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000, mi->video_mode,
0x0000, buffer_seg, buffer_adr);
- memcpy(mi->mode_info_block, buffer, sizeof(struct vesa_state));
+ memcpy(mi->mode_info_block, buffer, sizeof(struct vesa_mode_info));
mi->valid = true;
return 0;
diff --git a/arch/x86/lib/fsp1/fsp_dram.c b/arch/x86/lib/fsp1/fsp_dram.c
index 5825221..eee9ce5 100644
--- a/arch/x86/lib/fsp1/fsp_dram.c
+++ b/arch/x86/lib/fsp1/fsp_dram.c
@@ -34,7 +34,7 @@
* the relocation address, and how far U-Boot is moved by relocation are
* set in the global data structure.
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return fsp_get_usable_lowmem_top(gd->arch.hob_list);
}
diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c
index f9ea1ab..a143223 100644
--- a/arch/x86/lib/fsp2/fsp_dram.c
+++ b/arch/x86/lib/fsp2/fsp_dram.c
@@ -77,7 +77,7 @@
return 0;
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
if (!ll_boot_init())
return gd->ram_size;
diff --git a/arch/x86/lib/i8254.c b/arch/x86/lib/i8254.c
index 0f97538..a8d1db1 100644
--- a/arch/x86/lib/i8254.c
+++ b/arch/x86/lib/i8254.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/i8254.h>
+#include <asm/ibmpc.h>
#define TIMER1_VALUE 18 /* 15.6us */
#define BEEP_FREQUENCY_HZ 440
diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c
index 1eb97ac..382f768 100644
--- a/arch/x86/lib/physmem.c
+++ b/arch/x86/lib/physmem.c
@@ -14,6 +14,7 @@
#include <asm/cpu.h>
#include <asm/global_data.h>
#include <linux/compiler.h>
+#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -144,7 +145,7 @@
/* Make sure the window is below U-Boot. */
assert(window + LARGE_PAGE_SIZE <
- gd->relocaddr - CONFIG_SYS_MALLOC_LEN - CFG_SYS_STACK_SIZE);
+ gd->relocaddr - CONFIG_SYS_MALLOC_LEN - SZ_32K);
/* Map the page into the window and then memset the appropriate part. */
x86_phys_map_page(window, map_addr, 1);
memset((void *)(window + offset), c, size);
diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c
index 5b1b420..da819b9 100644
--- a/arch/x86/lib/relocate.c
+++ b/arch/x86/lib/relocate.c
@@ -26,11 +26,11 @@
int copy_uboot_to_ram(void)
{
- size_t len = (uintptr_t)&__data_end - (uintptr_t)&__text_start;
+ size_t len = (uintptr_t)__data_end - (uintptr_t)__text_start;
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
- memcpy((void *)gd->relocaddr, (void *)&__text_start, len);
+ memcpy((void *)gd->relocaddr, (void *)__text_start, len);
return 0;
}
@@ -38,8 +38,8 @@
#ifndef CONFIG_EFI_APP
int clear_bss(void)
{
- ulong dst_addr = (ulong)&__bss_start + gd->reloc_off;
- size_t len = (uintptr_t)&__bss_end - (uintptr_t)&__bss_start;
+ ulong dst_addr = (ulong)__bss_start + gd->reloc_off;
+ size_t len = (uintptr_t)__bss_end - (uintptr_t)__bss_start;
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
@@ -150,12 +150,12 @@
*/
int do_elf_reloc_fixups(void)
{
- void *re_src = (void *)(&__rel_dyn_start);
- void *re_end = (void *)(&__rel_dyn_end);
+ void *re_src = (void *)__rel_dyn_start;
+ void *re_end = (void *)__rel_dyn_end;
uint text_base;
/* The size of the region of u-boot that runs out of RAM. */
- uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start;
+ uintptr_t size = (uintptr_t)__bss_end - (uintptr_t)__text_start;
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index b6812bb..58fa572 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -27,6 +27,7 @@
#include <asm/mtrr.h>
#include <asm/pci.h>
#include <asm/processor.h>
+#include <asm/qemu.h>
#include <asm/spl.h>
#include <asm-generic/sections.h>
@@ -137,10 +138,9 @@
}
#ifndef CONFIG_SYS_COREBOOT
- log_debug("bss\n");
- debug("BSS clear from %lx to %lx len %lx\n", (ulong)&__bss_start,
- (ulong)&__bss_end, (ulong)&__bss_end - (ulong)&__bss_start);
- memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
+ debug("BSS clear from %lx to %lx len %lx\n", (ulong)__bss_start,
+ (ulong)__bss_end, (ulong)__bss_end - (ulong)__bss_start);
+ memset(__bss_start, 0, (ulong)__bss_end - (ulong)__bss_start);
# ifndef CONFIG_TPL
/* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */
@@ -292,6 +292,8 @@
#ifndef CONFIG_TPL
preloader_console_init();
#endif
+ if (IS_ENABLED(CONFIG_QEMU))
+ qemu_chipset_init();
if (CONFIG_IS_ENABLED(VIDEO)) {
struct udevice *dev;
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 062e3d3..a41e1cc 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -692,7 +692,7 @@
printf("\n");
}
-void zimage_dump(struct boot_params *base_ptr)
+void zimage_dump(struct boot_params *base_ptr, bool show_cmdline)
{
struct setup_header *hdr;
const char *version;
@@ -703,7 +703,7 @@
printf("E820: %d entries\n", base_ptr->e820_entries);
if (base_ptr->e820_entries) {
- printf("%18s %16s %s\n", "Addr", "Size", "Type");
+ printf("%12s %10s %s\n", "Addr", "Size", "Type");
for (i = 0; i < base_ptr->e820_entries; i++) {
struct e820_entry *entry = &base_ptr->e820_map[i];
@@ -749,7 +749,7 @@
print_num("Ext loader ver", hdr->ext_loader_ver);
print_num("Ext loader type", hdr->ext_loader_type);
print_num("Command line ptr", hdr->cmd_line_ptr);
- if (hdr->cmd_line_ptr) {
+ if (show_cmdline && hdr->cmd_line_ptr) {
printf(" ");
/* Use puts() to avoid limits from CONFIG_SYS_PBSIZE */
puts((char *)(ulong)hdr->cmd_line_ptr);
@@ -787,7 +787,7 @@
printf("No zboot setup_base\n");
return CMD_RET_FAILURE;
}
- zimage_dump(base_ptr);
+ zimage_dump(base_ptr, true);
return 0;
}
diff --git a/arch/xtensa/lib/relocate.c b/arch/xtensa/lib/relocate.c
index 3dc8edc..a499590 100644
--- a/arch/xtensa/lib/relocate.c
+++ b/arch/xtensa/lib/relocate.c
@@ -9,8 +9,8 @@
int clear_bss(void)
{
- size_t len = (size_t)&__bss_end - (size_t)&__bss_start;
+ size_t len = (size_t)__bss_end - (size_t)__bss_start;
- memset((void *)&__bss_start, 0x00, len);
+ memset((void *)__bss_start, 0x00, len);
return 0;
}
diff --git a/board/advantech/imx8qm_dmsse20_a1/spl.c b/board/advantech/imx8qm_dmsse20_a1/spl.c
index f36caec..e8959ed 100644
--- a/board/advantech/imx8qm_dmsse20_a1/spl.c
+++ b/board/advantech/imx8qm_dmsse20_a1/spl.c
@@ -14,6 +14,7 @@
#include <firmware/imx/sci/sci.h>
#include <asm/arch/imx8-pins.h>
#include <asm/arch/iomux.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/advantech/imx8qm_rom7720_a1/spl.c b/board/advantech/imx8qm_rom7720_a1/spl.c
index 922bb0b..d324001 100644
--- a/board/advantech/imx8qm_rom7720_a1/spl.c
+++ b/board/advantech/imx8qm_rom7720_a1/spl.c
@@ -17,6 +17,7 @@
#include <firmware/imx/sci/sci.h>
#include <asm/arch/imx8-pins.h>
#include <asm/arch/iomux.h>
+#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/amlogic/vim3/vim3.c b/board/amlogic/vim3/vim3.c
index fcd60ab..8bdfb30 100644
--- a/board/amlogic/vim3/vim3.c
+++ b/board/amlogic/vim3/vim3.c
@@ -104,8 +104,8 @@
}
/* Update PHY names (mandatory to disable USB3.0) */
- len = strlcpy(data, "usb2-phy0", 32);
- len += strlcpy(&data[len], "usb2-phy1", 32 - len);
+ len = strlcpy(data, "usb2-phy0", 32) + 1;
+ len += strlcpy(&data[len], "usb2-phy1", 32 - len) + 1;
ret = fdt_setprop(blob, node, "phy-names", data, len);
if (ret < 0) {
printf("vim3: failed to update usb phy names property (%d)\n", ret);
@@ -132,7 +132,7 @@
}
/* Enable PCIe */
- len = strlcpy(data, "okay", 32);
+ len = strlcpy(data, "okay", 32) + 1;
ret = fdt_setprop(blob, node, "status", data, len);
if (ret < 0) {
printf("vim3: failed to enable pcie node (%d)\n", ret);
diff --git a/board/anbernic/rgxx3_rk3566/MAINTAINERS b/board/anbernic/rgxx3_rk3566/MAINTAINERS
index 1c0d3fe..7970e5a 100644
--- a/board/anbernic/rgxx3_rk3566/MAINTAINERS
+++ b/board/anbernic/rgxx3_rk3566/MAINTAINERS
@@ -3,4 +3,7 @@
S: Maintained
F: board/anbernic/rgxx3_rk3566
F: include/configs/anbernic-rgxx3-rk3566.h
-F: configs/anbernic-rgxx3_defconfig
+F: configs/anbernic-rgxx3-rk3566_defconfig
+F: arch/arm/dts/rk3566-anbernic-rgxx3.dts
+F: arch/arm/dts/rk3566-anbernic-rgxx3.dtsi
+F: arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index 4dcf3f3..17f37ba 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -27,6 +27,7 @@
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
+#include <asm/sections.h>
#include <bmp_logo.h>
#include <dm/root.h>
#include <env.h>
@@ -216,7 +217,6 @@
&iomuxc_regs->gpr[12]);
}
-extern char __bss_start[], __bss_end[];
int board_early_init_f(void)
{
select_ldb_di_clock_source(MXC_PLL5_CLK);
diff --git a/board/armltd/corstone1000/MAINTAINERS b/board/armltd/corstone1000/MAINTAINERS
index 8c90568..1cc9aaa 100644
--- a/board/armltd/corstone1000/MAINTAINERS
+++ b/board/armltd/corstone1000/MAINTAINERS
@@ -1,6 +1,6 @@
CORSTONE1000 BOARD
-M: Rui Miguel Silva <rui.silva@linaro.org>
-M: Vishnu Banavath <vishnu.banavath@arm.com>
+M: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+M: Xueliang Zhong <xueliang.zhong@arm.com>
S: Maintained
F: board/armltd/corstone1000/
F: include/configs/corstone1000.h
diff --git a/board/armltd/vexpress64/MAINTAINERS b/board/armltd/vexpress64/MAINTAINERS
index b3ecc9b..c38ab52 100644
--- a/board/armltd/vexpress64/MAINTAINERS
+++ b/board/armltd/vexpress64/MAINTAINERS
@@ -1,9 +1,10 @@
-VEXPRESS64 BOARD
+VEXPRESS64 PLATFORM
M: David Feng <fenghua@phytium.com.cn>
+M: Linus Walleij <linus.walleij@linaro.org>
+M: Peter Hoyes <Peter.Hoyes@arm.com>
S: Maintained
F: board/armltd/vexpress64/
-F: include/configs/vexpress_aemv8a.h
-F: configs/vexpress_aemv8a_defconfig
+F: include/configs/vexpress_aemv8.h
VEXPRESS_AEMV8A_SEMI BOARD
M: Linus Walleij <linus.walleij@linaro.org>
diff --git a/board/asus/grouper/Kconfig b/board/asus/grouper/Kconfig
new file mode 100644
index 0000000..912c6c5
--- /dev/null
+++ b/board/asus/grouper/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_GROUPER
+
+config SYS_BOARD
+ default "grouper"
+
+config SYS_VENDOR
+ default "asus"
+
+config SYS_CONFIG_NAME
+ default "grouper"
+
+config GROUPER_TPS65911
+ bool "Enable support TI TPS65911 PMIC"
+ select CMD_POWEROFF
+ default n
+
+config GROUPER_MAX77663
+ bool "Enable support MAXIM MAX77663 PMIC"
+ select CMD_POWEROFF
+ default n
+
+endif
diff --git a/board/asus/grouper/MAINTAINERS b/board/asus/grouper/MAINTAINERS
new file mode 100644
index 0000000..18b4f06
--- /dev/null
+++ b/board/asus/grouper/MAINTAINERS
@@ -0,0 +1,10 @@
+GROUPER BOARD
+M: Svyatoslav Ryhel <clamor95@gmail.com>
+S: Maintained
+F: board/asus/grouper/
+F: configs/grouper_E1565.config
+F: configs/grouper_PM269.config
+F: configs/tilapia.config
+F: configs/grouper_common_defconfig
+F: doc/board/asus/grouper_common.rst
+F: include/configs/grouper.h
diff --git a/board/asus/grouper/Makefile b/board/asus/grouper/Makefile
new file mode 100644
index 0000000..e4a477a
--- /dev/null
+++ b/board/asus/grouper/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010-2012
+# NVIDIA Corporation <www.nvidia.com>
+#
+# (C) Copyright 2021
+# Svyatoslav Ryhel <clamor95@gmail.com>
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_GROUPER_MAX77663) += grouper-spl-max.o
+obj-$(CONFIG_GROUPER_TPS65911) += grouper-spl-ti.o
+endif
+
+obj-y += grouper.o
diff --git a/board/asus/grouper/grouper-spl-max.c b/board/asus/grouper/grouper-spl-max.c
new file mode 100644
index 0000000..8443837
--- /dev/null
+++ b/board/asus/grouper/grouper-spl-max.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * T30 Grouper MAX SPL stage configuration
+ *
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2022
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+#define MAX77663_I2C_ADDR (0x3C << 1)
+
+#define MAX77663_REG_SD0 0x16
+#define MAX77663_REG_SD0_DATA (0x2100 | MAX77663_REG_SD0)
+#define MAX77663_REG_SD1 0x17
+#define MAX77663_REG_SD1_DATA (0x3000 | MAX77663_REG_SD1)
+#define MAX77663_REG_LDO4 0x2B
+#define MAX77663_REG_LDO4_DATA (0xE000 | MAX77663_REG_LDO4)
+
+#define MAX77663_REG_GPIO4 0x3A
+#define MAX77663_REG_GPIO4_DATA (0x0100 | MAX77663_REG_GPIO4)
+
+void pmic_enable_cpu_vdd(void)
+{
+ /* Set VDD_CORE to 1.200V. */
+ tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD1_DATA);
+
+ udelay(1000);
+
+ /* Bring up VDD_CPU to 1.0125V. */
+ tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD0_DATA);
+ udelay(1000);
+
+ /* Bring up VDD_RTC to 1.200V. */
+ tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_LDO4_DATA);
+ udelay(10 * 1000);
+
+ /* Set 32k-out gpio state */
+ tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO4_DATA);
+}
diff --git a/board/asus/grouper/grouper-spl-ti.c b/board/asus/grouper/grouper-spl-ti.c
new file mode 100644
index 0000000..e5b78f0
--- /dev/null
+++ b/board/asus/grouper/grouper-spl-ti.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * T30 Grouper TI SPL stage configuration
+ *
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2022
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+#define TPS65911_I2C_ADDR (0x2D << 1)
+#define TPS65911_VDDCTRL_OP_REG 0x28
+#define TPS65911_VDDCTRL_SR_REG 0x27
+#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
+
+#define TPS62361B_I2C_ADDR (0x60 << 1)
+#define TPS62361B_SET3_REG 0x03
+#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
+
+void pmic_enable_cpu_vdd(void)
+{
+ /* Set VDD_CORE to 1.200V. */
+ tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA);
+
+ udelay(1000);
+
+ /*
+ * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+ * First set VDD to 1.0125V, then enable the VDD regulator.
+ */
+ tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA);
+ udelay(1000);
+ tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA);
+ udelay(10 * 1000);
+}
diff --git a/board/asus/grouper/grouper.c b/board/asus/grouper/grouper.c
new file mode 100644
index 0000000..2769313
--- /dev/null
+++ b/board/asus/grouper/grouper.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2021
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <log.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch-tegra/fuse.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+#include "pinmux-config-grouper.h"
+
+#define TPS65911_I2C_ADDRESS 0x2D
+
+#define TPS65911_REG_LDO1 0x30
+#define TPS65911_REG_DEVCTRL 0x3F
+#define DEVCTRL_PWR_OFF_MASK BIT(7)
+#define DEVCTRL_DEV_ON_MASK BIT(2)
+#define DEVCTRL_DEV_OFF_MASK BIT(0)
+
+#define MAX77663_I2C_ADDRESS 0x3C
+
+#define MAX77663_REG_SD2 0x18
+#define MAX77663_REG_LDO3 0x29
+#define MAX77663_REG_ONOFF_CFG1 0x41
+#define ONOFF_PWR_OFF BIT(1)
+
+#ifdef CONFIG_CMD_POWEROFF
+#ifdef CONFIG_GROUPER_TPS65911
+int do_poweroff(struct cmd_tbl *cmdtp,
+ int flag, int argc, char *const argv[])
+{
+ struct udevice *dev;
+ uchar data_buffer[1];
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev);
+ if (ret) {
+ log_debug("cannot find PMIC I2C chip\n");
+ return 0;
+ }
+
+ ret = dm_i2c_read(dev, TPS65911_REG_DEVCTRL, data_buffer, 1);
+ if (ret)
+ return ret;
+
+ data_buffer[0] |= DEVCTRL_PWR_OFF_MASK;
+
+ ret = dm_i2c_write(dev, TPS65911_REG_DEVCTRL, data_buffer, 1);
+ if (ret)
+ return ret;
+
+ data_buffer[0] |= DEVCTRL_DEV_OFF_MASK;
+ data_buffer[0] &= ~DEVCTRL_DEV_ON_MASK;
+
+ ret = dm_i2c_write(dev, TPS65911_REG_DEVCTRL, data_buffer, 1);
+ if (ret)
+ return ret;
+
+ // wait some time and then print error
+ mdelay(5000);
+
+ printf("Failed to power off!!!\n");
+ return 1;
+}
+#endif /* CONFIG_GROUPER_TPS65911 */
+
+#ifdef CONFIG_GROUPER_MAX77663
+int do_poweroff(struct cmd_tbl *cmdtp,
+ int flag, int argc, char *const argv[])
+{
+ struct udevice *dev;
+ uchar data_buffer[1];
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDRESS, 1, &dev);
+ if (ret) {
+ log_debug("cannot find PMIC I2C chip\n");
+ return 0;
+ }
+
+ ret = dm_i2c_read(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1);
+ if (ret)
+ return ret;
+
+ data_buffer[0] |= ONOFF_PWR_OFF;
+
+ ret = dm_i2c_write(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1);
+ if (ret)
+ return ret;
+
+ // wait some time and then print error
+ mdelay(5000);
+
+ printf("Failed to power off!!!\n");
+ return 1;
+}
+#endif /* CONFIG_GROUPER_MAX77663 */
+#endif /* CONFIG_CMD_POWEROFF */
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_config_pingrp_table(grouper_pinmux_common,
+ ARRAY_SIZE(grouper_pinmux_common));
+
+ pinmux_config_drvgrp_table(grouper_padctrl,
+ ARRAY_SIZE(grouper_padctrl));
+}
+
+#ifdef CONFIG_MMC_SDHCI_TEGRA
+static void __maybe_unused tps65911_voltage_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev);
+ if (ret) {
+ log_debug("cannot find PMIC I2C chip\n");
+ return;
+ }
+
+ /* TPS659110: LDO1_REG = 3.3v, ACTIVE to SDMMC4 */
+ ret = dm_i2c_reg_write(dev, TPS65911_REG_LDO1, 0xC9);
+ if (ret)
+ log_debug("vcore_emmc set failed: %d\n", ret);
+}
+
+static void __maybe_unused max77663_voltage_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDRESS, 1, &dev);
+ if (ret) {
+ log_debug("cannot find PMIC I2C chip\n");
+ return;
+ }
+
+ /* 0x60 for 1.8v, bit7:0 = voltage */
+ ret = dm_i2c_reg_write(dev, MAX77663_REG_SD2, 0x60);
+ if (ret)
+ log_debug("vdd_1v8_vio set failed: %d\n", ret);
+
+ /* 0xEC for 3.00v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+ ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO3, 0xEC);
+ if (ret)
+ log_debug("vcore_emmc set failed: %d\n", ret);
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the MMC muxes, power rails, etc.
+ */
+void pin_mux_mmc(void)
+{
+#ifdef CONFIG_GROUPER_MAX77663
+ /* Bring up eMMC power on MAX PMIC */
+ max77663_voltage_init();
+#endif
+
+#ifdef CONFIG_GROUPER_TPS65911
+ /* Bring up eMMC power on TI PMIC */
+ tps65911_voltage_init();
+#endif
+}
+#endif /* MMC */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /* Remove TrustZone nodes */
+ fdt_del_node_and_alias(blob, "/firmware");
+ fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000");
+
+ return 0;
+}
+#endif
+
+void nvidia_board_late_init(void)
+{
+ char serialno_str[17];
+
+ /* Set chip id as serialno */
+ sprintf(serialno_str, "%016llx", tegra_chip_uid());
+ env_set("serial#", serialno_str);
+ env_set("platform", "Tegra 3 T30");
+}
diff --git a/board/asus/grouper/pinmux-config-grouper.h b/board/asus/grouper/pinmux-config-grouper.h
new file mode 100644
index 0000000..98134f7
--- /dev/null
+++ b/board/asus/grouper/pinmux-config-grouper.h
@@ -0,0 +1,362 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#ifndef _PINMUX_CONFIG_GROUPER_H_
+#define _PINMUX_CONFIG_GROUPER_H_
+
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
+ }
+
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
+ }
+
+static struct pmux_pingrp_config grouper_pinmux_common[] = {
+ /* SDMMC1 pinmux */
+ DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
+
+ /* SDMMC3 pinmux */
+ DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, NORMAL, INPUT),
+
+ /* SDMMC4 pinmux */
+ LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD2, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* I2C pinmux */
+ I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* HDMI-CEC pinmux */
+ DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
+
+ /* ULPI pinmux */
+ DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, UP, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(ULPI_CLK_PY0, ULPI, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DIR_PY1, ULPI, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(ULPI_NXT_PY2, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(ULPI_STP_PY3, RSVD1, NORMAL, TRISTATE, OUTPUT),
+
+ /* DAP3 pinmux */
+ DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, DOWN, TRISTATE, INPUT),
+
+ DEFAULT_PINMUX(PV0, RSVD1, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV2, OWR, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(PV3, RSVD1, NORMAL, TRISTATE, INPUT),
+
+ /* CLK2 pinmux */
+ DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
+
+ /* LCD pinmux */
+ DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
+
+ /* VI-group pinmux */
+ LV_PINMUX(VI_D0_PT4, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D1_PD5, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D2_PL0, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D3_PL1, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D4_PL2, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D5_PL3, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D6_PL4, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D7_PL5, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D8_PL6, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D9_PL7, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D10_PT2, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D11_PT3, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_PCLK_PT0, SDMMC2, UP, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_MCLK_PT1, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_HSYNC_PD7, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_VSYNC_PD6, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
+
+ /* UART-B pinmux */
+ DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
+
+ /* UART-C pinmux */
+ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
+
+ /* U-gpio group pinmux */
+ DEFAULT_PINMUX(PU0, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU3, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU4, PWM1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU6, RSVD4, NORMAL, NORMAL, INPUT),
+
+ /* DAP4 pinmux */
+ DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
+
+ /* CLK3 pinmux */
+ DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, DOWN, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(PCC1, RSVD2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB0, RSVD2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, UP, NORMAL, INPUT),
+
+ /* KBC keys */
+ DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW1_PR1, KBC, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW2_PR2, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW3_PR3, KBC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW4_PR4, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW10_PS2, KBC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW11_PS3, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW12_PS4, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW13_PS5, KBC, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW14_PS6, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW15_PS7, KBC, NORMAL, NORMAL, OUTPUT),
+
+ DEFAULT_PINMUX(KB_COL0_PQ0, KBC, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(KB_COL2_PQ2, RSVD4, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_COL3_PQ3, RSVD4, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_COL4_PQ4, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_COL5_PQ5, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, TRISTATE, INPUT),
+
+ /* CLK */
+ DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+
+ /* DAP1 pinmux */
+ DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
+
+ /* CLK1 pinmux */
+ DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+
+ /* SPDIF pinmux */
+ DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
+
+ /* DAP2 pinmux */
+ DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
+
+ /* SPI pinmux */
+ DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_MISO_PX1, SPI2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_SCK_PX2, SPI2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_CS2_N_PW3, SPI2, NORMAL, NORMAL, INPUT),
+
+ /* PEX pinmux */
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, OUTPUT),
+
+ /* GMI pinmux */
+ DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WAIT_PI7, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_ADV_N_PK0, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS0_N_PJ0, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_CS1_N_PJ2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS6_N_PI3, GMI, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD0_PG0, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD1_PG1, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD2_PG2, RSVD1, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD3_PG3, RSVD1, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD6_PG6, RSVD1, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD7_PG7, RSVD1, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD9_PH1, RSVD4, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD10_PH2, PWM2, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11_PH3, PWM3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD13_PH5, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD14_PH6, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD15_PH7, RSVD1, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_WR_N_PI0, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_OE_N_PI1, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_DQS_PI2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_RST_N_PI4, NAND, UP, NORMAL, OUTPUT),
+};
+
+static struct pmux_drvgrp_config grouper_padctrl[] = {
+ /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+ DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
+ SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
+};
+#endif /* _PINMUX_CONFIG_GROUPER_H_ */
diff --git a/board/asus/transformer-t30/Kconfig b/board/asus/transformer-t30/Kconfig
new file mode 100644
index 0000000..3c36f4a
--- /dev/null
+++ b/board/asus/transformer-t30/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_TRANSFORMER_T30
+
+config SYS_BOARD
+ default "transformer-t30"
+
+config SYS_VENDOR
+ default "asus"
+
+config SYS_CONFIG_NAME
+ default "transformer-t30"
+
+config TRANSFORMER_SPI_BOOT
+ bool "Enable support for SPI based flash"
+ select TEGRA20_SLINK
+ select DM_SPI_FLASH
+ select SPI_FLASH_WINBOND
+ default n
+ help
+ Tegra 3 based Transformers with Windows RT have core
+ boot sequence (BCT and EBT) on separate SPI FLASH
+ memory with 4MB size.
+
+endif
diff --git a/board/asus/transformer-t30/MAINTAINERS b/board/asus/transformer-t30/MAINTAINERS
new file mode 100644
index 0000000..c6c1532
--- /dev/null
+++ b/board/asus/transformer-t30/MAINTAINERS
@@ -0,0 +1,15 @@
+TRANSFORMER BOARD
+M: Svyatoslav Ryhel <clamor95@gmail.com>
+S: Maintained
+F: board/asus/transformer-t30/
+F: configs/p1801-t.config
+F: configs/tf201.config
+F: configs/tf300t.config
+F: configs/tf300tg.config
+F: configs/tf300tl.config
+F: configs/tf600t.config
+F: configs/tf700t.config
+F: configs/transformer_t30_defconfig
+F: doc/board/asus/transformer_t30.rst
+F: include/configs/transformer-common.h
+F: include/configs/transformer-t30.h
diff --git a/board/asus/transformer-t30/Makefile b/board/asus/transformer-t30/Makefile
new file mode 100644
index 0000000..c083f22
--- /dev/null
+++ b/board/asus/transformer-t30/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010-2012
+# NVIDIA Corporation <www.nvidia.com>
+#
+# (C) Copyright 2021
+# Svyatoslav Ryhel <clamor95@gmail.com>
+
+obj-$(CONFIG_SPL_BUILD) += transformer-t30-spl.o
+
+obj-y += transformer-t30.o
diff --git a/board/asus/transformer-t30/pinmux-config-transformer.h b/board/asus/transformer-t30/pinmux-config-transformer.h
new file mode 100644
index 0000000..96ff45d
--- /dev/null
+++ b/board/asus/transformer-t30/pinmux-config-transformer.h
@@ -0,0 +1,365 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Copyright (c) 2021, Svyatoslav Ryhel.
+ */
+
+#ifndef _PINMUX_CONFIG_TRANSFORMER_H_
+#define _PINMUX_CONFIG_TRANSFORMER_H_
+
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
+ }
+
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
+ }
+
+static struct pmux_pingrp_config transformer_pinmux_common[] = {
+ /* SDMMC1 pinmux */
+ DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
+
+ /* SDMMC3 pinmux */
+ DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, NORMAL, INPUT),
+
+ /* SDMMC4 pinmux */
+ LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* I2C pinmux */
+ I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* HDMI-CEC pinmux */
+ DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
+
+ /* ULPI pinmux */
+ DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, DOWN, TRISTATE, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3_PO4, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, TRISTATE, OUTPUT),
+
+ /* DAP3 pinmux */
+ DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(PV0, RSVD1, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PV2, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PV3, RSVD1, NORMAL, TRISTATE, OUTPUT),
+
+ /* CLK2 pinmux */
+ DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
+
+ /* LCD pinmux */
+ DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, TRISTATE, OUTPUT),
+
+ /* VI-group pinmux */
+ LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* UART-B pinmux */
+ DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
+
+ /* UART-C pinmux */
+ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
+
+ /* U-gpio group pinmux */
+ DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU4, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU6, RSVD1, DOWN, NORMAL, INPUT),
+
+ /* DAP4 pinmux */
+ DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
+
+ /* CLK3 pinmux */
+ DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, TRISTATE, INPUT),
+
+ DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
+
+ /* KBC keys */
+ DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW2_PR2, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW4_PR4, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW11_PS3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW12_PS4, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW13_PS5, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(KB_COL0_PQ0, KBC, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2_PQ2, RSVD4, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_COL3_PQ3, RSVD4, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_COL4_PQ4, RSVD4, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_COL5_PQ5, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, TRISTATE, INPUT),
+
+ /* CLK */
+ DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+
+ /* DAP1 pinmux */
+ DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, TRISTATE, INPUT),
+
+ /* CLK1 pinmux */
+ DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+
+ /* SPDIF pinmux */
+ DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, TRISTATE, OUTPUT),
+
+ /* DAP2 pinmux */
+ DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
+
+ /* SPI pinmux */
+ DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT),
+
+ /* PEX pinmux */
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
+
+ /* GMI pinmux */
+ DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WAIT_PI7, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD13_PH5, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD15_PH7, NAND, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT),
+};
+
+static struct pmux_pingrp_config tf700t_mipi_pinmux[] = {
+ DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS4_N_PK2, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, TRISTATE, INPUT),
+};
+
+static struct pmux_drvgrp_config transformer_padctrl[] = {
+ /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+ DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
+ SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
+};
+#endif /* _PINMUX_CONFIG_TRANSFORMER_H_ */
diff --git a/board/asus/transformer-t30/transformer-t30-spl.c b/board/asus/transformer-t30/transformer-t30-spl.c
new file mode 100644
index 0000000..89819b2
--- /dev/null
+++ b/board/asus/transformer-t30/transformer-t30-spl.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * T30 Transformers SPL stage configuration
+ *
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2021
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+#define TPS65911_I2C_ADDR (0x2D << 1)
+#define TPS65911_VDDCTRL_OP_REG 0x28
+#define TPS65911_VDDCTRL_SR_REG 0x27
+#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
+
+#define TPS62361B_I2C_ADDR (0x60 << 1)
+#define TPS62361B_SET3_REG 0x03
+#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
+
+void pmic_enable_cpu_vdd(void)
+{
+ /* Set VDD_CORE to 1.200V. */
+ tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA);
+
+ udelay(1000);
+
+ /*
+ * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+ * First set VDD to 1.0125V, then enable the VDD regulator.
+ */
+ tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA);
+ udelay(1000);
+ tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA);
+ udelay(10 * 1000);
+}
diff --git a/board/asus/transformer-t30/transformer-t30.c b/board/asus/transformer-t30/transformer-t30.c
new file mode 100644
index 0000000..b6fd19d
--- /dev/null
+++ b/board/asus/transformer-t30/transformer-t30.c
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2021
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+/* T30 Transformers derive from Cardhu board */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <log.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch-tegra/fuse.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+#include "pinmux-config-transformer.h"
+
+#define TPS65911_I2C_ADDRESS 0x2D
+
+#define TPS65911_VDD1 0x21
+#define TPS65911_VDD1_OP 0x22
+#define TPS65911_LDO1 0x30
+#define TPS65911_LDO2 0x31
+#define TPS65911_LDO3 0x37
+#define TPS65911_LDO5 0x32
+#define TPS65911_LDO6 0x35
+
+#define TPS65911_GPIO0 0x60
+#define TPS65911_GPIO6 0x66
+#define TPS65911_GPIO7 0x67
+#define TPS65911_GPIO8 0x68
+
+#define TPS65911_DEVCTRL 0x3F
+#define DEVCTRL_PWR_OFF_MASK BIT(7)
+#define DEVCTRL_DEV_ON_MASK BIT(2)
+#define DEVCTRL_DEV_OFF_MASK BIT(0)
+
+#ifdef CONFIG_CMD_POWEROFF
+int do_poweroff(struct cmd_tbl *cmdtp, int flag,
+ int argc, char *const argv[])
+{
+ struct udevice *dev;
+ uchar data_buffer[1];
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev);
+ if (ret) {
+ log_debug("cannot find PMIC I2C chip\n");
+ return 0;
+ }
+
+ ret = dm_i2c_read(dev, TPS65911_DEVCTRL, data_buffer, 1);
+ if (ret)
+ return ret;
+
+ data_buffer[0] |= DEVCTRL_PWR_OFF_MASK;
+
+ ret = dm_i2c_write(dev, TPS65911_DEVCTRL, data_buffer, 1);
+ if (ret)
+ return ret;
+
+ data_buffer[0] |= DEVCTRL_DEV_OFF_MASK;
+ data_buffer[0] &= ~DEVCTRL_DEV_ON_MASK;
+
+ ret = dm_i2c_write(dev, TPS65911_DEVCTRL, data_buffer, 1);
+ if (ret)
+ return ret;
+
+ // wait some time and then print error
+ mdelay(5000);
+ printf("Failed to power off!!!\n");
+ return 1;
+}
+#endif
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_config_pingrp_table(transformer_pinmux_common,
+ ARRAY_SIZE(transformer_pinmux_common));
+
+ pinmux_config_drvgrp_table(transformer_padctrl,
+ ARRAY_SIZE(transformer_padctrl));
+
+ if (of_machine_is_compatible("asus,tf700t")) {
+ pinmux_config_pingrp_table(tf700t_mipi_pinmux,
+ ARRAY_SIZE(tf700t_mipi_pinmux));
+ }
+}
+
+#ifdef CONFIG_MMC_SDHCI_TEGRA
+static void tps65911_voltage_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev);
+ if (ret) {
+ log_debug("cannot find PMIC I2C chip\n");
+ return;
+ }
+
+ /* TPS659110: LDO1_REG = 3.3v, ACTIVE to SDMMC4 */
+ ret = dm_i2c_reg_write(dev, TPS65911_LDO1, 0xc9);
+ if (ret)
+ log_debug("vcore_emmc set failed: %d\n", ret);
+
+ if (of_machine_is_compatible("asus,tf600t")) {
+ /* TPS659110: VDD1_REG = 1.2v, ACTIVE to backlight */
+ ret = dm_i2c_reg_write(dev, TPS65911_VDD1_OP, 0x33);
+ if (ret)
+ log_debug("vdd_bl set failed: %d\n", ret);
+
+ ret = dm_i2c_reg_write(dev, TPS65911_VDD1, 0x0d);
+ if (ret)
+ log_debug("vdd_bl enable failed: %d\n", ret);
+
+ /* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 VIO */
+ ret = dm_i2c_reg_write(dev, TPS65911_LDO5, 0x65);
+ if (ret)
+ log_debug("vdd_usd set failed: %d\n", ret);
+
+ /* TPS659110: LDO6_REG = 1.2v, ACTIVE to MIPI */
+ ret = dm_i2c_reg_write(dev, TPS65911_LDO6, 0x11);
+ if (ret)
+ log_debug("vdd_mipi set failed: %d\n", ret);
+ } else {
+ /* TPS659110: LDO2_REG = 3.1v, ACTIVE to SDMMC1 */
+ ret = dm_i2c_reg_write(dev, TPS65911_LDO2, 0xb9);
+ if (ret)
+ log_debug("vdd_usd set failed: %d\n", ret);
+
+ /* TPS659110: LDO3_REG = 3.1v, ACTIVE to SDMMC1 VIO */
+ ret = dm_i2c_reg_write(dev, TPS65911_LDO3, 0x5d);
+ if (ret)
+ log_debug("vddio_usd set failed: %d\n", ret);
+ }
+
+ /* TPS659110: GPIO0_REG output high to VDD_5V0_SBY */
+ ret = dm_i2c_reg_write(dev, TPS65911_GPIO0, 0x07);
+ if (ret)
+ log_debug("vdd_5v0_sby set failed: %d\n", ret);
+
+ /* TPS659110: GPIO6_REG output high to VDD_3V3_SYS */
+ ret = dm_i2c_reg_write(dev, TPS65911_GPIO6, 0x07);
+ if (ret)
+ log_debug("vdd_3v3_sys set failed: %d\n", ret);
+
+ /* TPS659110: GPIO7_REG output high to VDD_1V5_DDR */
+ ret = dm_i2c_reg_write(dev, TPS65911_GPIO7, 0x07);
+ if (ret)
+ log_debug("vdd_1v5_ddr set failed: %d\n", ret);
+
+ /* TPS659110: GPIO8_REG pull_down output high to VDD_5V0_SYS */
+ ret = dm_i2c_reg_write(dev, TPS65911_GPIO8, 0x0f);
+ if (ret)
+ log_debug("vdd_5v0_sys set failed: %d\n", ret);
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the MMC muxes, power rails, etc.
+ */
+void pin_mux_mmc(void)
+{
+ /* Bring up uSD and eMMC power */
+ tps65911_voltage_init();
+}
+#endif /* MMC */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /* Remove TrustZone nodes */
+ fdt_del_node_and_alias(blob, "/firmware");
+ fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000");
+
+ return 0;
+}
+#endif
+
+void nvidia_board_late_init(void)
+{
+ char serialno_str[17];
+
+ /* Set chip id as serialno */
+ sprintf(serialno_str, "%016llx", tegra_chip_uid());
+ env_set("serial#", serialno_str);
+ env_set("platform", "Tegra 3 T30");
+}
diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c
index b2830c5..1632238 100644
--- a/board/beacon/imx8mm/spl.c
+++ b/board/beacon/imx8mm/spl.c
@@ -14,6 +14,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/ddr.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c
index 9acd916..b4d46f1 100644
--- a/board/beacon/imx8mn/spl.c
+++ b/board/beacon/imx8mn/spl.c
@@ -20,6 +20,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <linux/delay.h>
diff --git a/board/bosch/acc/acc.c b/board/bosch/acc/acc.c
index 7c49b20..34088ad 100644
--- a/board/bosch/acc/acc.c
+++ b/board/bosch/acc/acc.c
@@ -27,6 +27,7 @@
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/iomux-v3.h>
+#include <asm/sections.h>
#include <usb.h>
#include <usb/ehci-ci.h>
#include <fuse.h>
diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
index 2a78df6..7ae6742 100644
--- a/board/broadcom/bcmns3/ns3.c
+++ b/board/broadcom/bcmns3/ns3.c
@@ -183,7 +183,7 @@
}
/* Limit RAM used by U-Boot to the DDR first bank End region */
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return BCM_NS3_MEM_END;
}
diff --git a/board/bsh/imx8mn_smm_s2/spl.c b/board/bsh/imx8mn_smm_s2/spl.c
index ce0504a..5a77d28 100644
--- a/board/bsh/imx8mn_smm_s2/spl.c
+++ b/board/bsh/imx8mn_smm_s2/spl.c
@@ -13,6 +13,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/gpio.h>
+#include <asm/sections.h>
#include <dm/device.h>
#include <dm/uclass.h>
diff --git a/board/cloos/imx8mm_phg/spl.c b/board/cloos/imx8mm_phg/spl.c
index e63904e..0c3a013 100644
--- a/board/cloos/imx8mm_phg/spl.c
+++ b/board/cloos/imx8mm_phg/spl.c
@@ -19,6 +19,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/ddr.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
diff --git a/board/compulab/cl-som-imx7/spl.c b/board/compulab/cl-som-imx7/spl.c
index 5d4c4d3..98c3b83 100644
--- a/board/compulab/cl-som-imx7/spl.c
+++ b/board/compulab/cl-som-imx7/spl.c
@@ -16,6 +16,7 @@
#include <asm/arch-mx7/mx7-pins.h>
#include <asm/arch-mx7/clock.h>
#include <asm/arch-mx7/mx7-ddr.h>
+#include <asm/sections.h>
#include "common.h"
#ifdef CONFIG_FSL_ESDHC_IMX
diff --git a/board/compulab/imx8mm-cl-iot-gate/spl.c b/board/compulab/imx8mm-cl-iot-gate/spl.c
index d2d2026..19c1acd 100644
--- a/board/compulab/imx8mm-cl-iot-gate/spl.c
+++ b/board/compulab/imx8mm-cl-iot-gate/spl.c
@@ -21,6 +21,7 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/gpio.h>
#include <asm/arch/ddr.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
diff --git a/board/congatec/cgtqmx8/spl.c b/board/congatec/cgtqmx8/spl.c
index dea34e4..b432ce2 100644
--- a/board/congatec/cgtqmx8/spl.c
+++ b/board/congatec/cgtqmx8/spl.c
@@ -10,6 +10,7 @@
#include <init.h>
#include <log.h>
#include <spl.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
diff --git a/board/coreboot/coreboot/coreboot.env b/board/coreboot/coreboot/coreboot.env
new file mode 100644
index 0000000..0f5bb6f
--- /dev/null
+++ b/board/coreboot/coreboot/coreboot.env
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <env/x86.env>
+
+splashsource=virtio_fs
+splashimage=0x1000000
diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
index 20a330c..e6d5657 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
@@ -21,6 +21,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
+#include <asm/sections.h>
#include <asm/system.h>
#include <errno.h>
#include <fuse.h>
diff --git a/board/dhelectronics/dh_imx8mp/MAINTAINERS b/board/dhelectronics/dh_imx8mp/MAINTAINERS
index 7c70cfd..db69781 100644
--- a/board/dhelectronics/dh_imx8mp/MAINTAINERS
+++ b/board/dhelectronics/dh_imx8mp/MAINTAINERS
@@ -1,8 +1,8 @@
-DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus
+DH electronics DHCOM i.MX8M Plus and matching carrier boards
M: Marek Vasut <marex@denx.de>
+L: u-boot@dh-electronics.com
S: Maintained
-F: arch/arm/dts/imx8mp-dhcom-pdk2.dts
-F: arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi
-F: board/dhelectronics/imx8mp_dhcom_pdk2/
-F: configs/imx8mp_dhcom_pdk2_defconfig
-F: include/configs/imx8mp_dhcom_pdk2.h
+F: arch/arm/dts/imx8mp-dhcom*
+F: board/dhelectronics/dh_imx8mp/
+F: configs/imx8mp_dhcom*defconfig
+F: include/configs/imx8mp_dhcom*
diff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c
index e2aa874..a8fda13 100644
--- a/board/dhelectronics/dh_imx8mp/spl.c
+++ b/board/dhelectronics/dh_imx8mp/spl.c
@@ -15,6 +15,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/ddr.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
diff --git a/board/edgeble/neural-compute-module-6/MAINTAINERS b/board/edgeble/neural-compute-module-6/MAINTAINERS
index bc7f9b0..42e5df5 100644
--- a/board/edgeble/neural-compute-module-6/MAINTAINERS
+++ b/board/edgeble/neural-compute-module-6/MAINTAINERS
@@ -5,3 +5,9 @@
F: include/configs/neural-compute-module-6.h
F: configs/neu6a-io-rk3588_defconfig
F: configs/neu6b-io-rk3588_defconfig
+F: arch/arm/dts/rk3588-edgeble-neu6a.dtsi
+F: arch/arm/dts/rk3588-edgeble-neu6a-io.dts
+F: arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
+F: arch/arm/dts/rk3588-edgeble-neu6b.dtsi
+F: arch/arm/dts/rk3588-edgeble-neu6b-io.dts
+F: arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
diff --git a/board/efi/efi-x86_app/efi-x86_app.env b/board/efi/efi-x86_app/efi-x86_app.env
new file mode 100644
index 0000000..106836a
--- /dev/null
+++ b/board/efi/efi-x86_app/efi-x86_app.env
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ */
+
+#include <env/x86.env>
diff --git a/board/efi/efi-x86_payload/efi-x86_payload.env b/board/efi/efi-x86_payload/efi-x86_payload.env
new file mode 100644
index 0000000..6a65628
--- /dev/null
+++ b/board/efi/efi-x86_payload/efi-x86_payload.env
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <env/x86.env>
diff --git a/board/emulation/qemu-arm/Kconfig b/board/emulation/qemu-arm/Kconfig
index ed99496..09c9541 100644
--- a/board/emulation/qemu-arm/Kconfig
+++ b/board/emulation/qemu-arm/Kconfig
@@ -12,6 +12,10 @@
imply VIRTIO_NET
imply VIRTIO_BLK
+config PRE_CON_BUF_ADDR
+ hex
+ default 0x40100000
+
endif
if TARGET_QEMU_ARM_64BIT && !TFABOOT
diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c
index dfea0d9..942f1ff 100644
--- a/board/emulation/qemu-arm/qemu-arm.c
+++ b/board/emulation/qemu-arm/qemu-arm.c
@@ -11,6 +11,7 @@
#include <fdtdec.h>
#include <init.h>
#include <log.h>
+#include <usb.h>
#include <virtio_types.h>
#include <virtio.h>
@@ -114,6 +115,10 @@
*/
virtio_init();
+ /* start usb so that usb keyboard can be used as input device */
+ if (CONFIG_IS_ENABLED(USB_KEYBOARD))
+ usb_init();
+
return 0;
}
diff --git a/board/emulation/qemu-arm/qemu-arm.env b/board/emulation/qemu-arm/qemu-arm.env
index e658d5e..fb4adef 100644
--- a/board/emulation/qemu-arm/qemu-arm.env
+++ b/board/emulation/qemu-arm/qemu-arm.env
@@ -2,6 +2,9 @@
/* environment for qemu-arm and qemu-arm64 */
+stdin=serial,usbkbd
+stdout=serial,vidconsole
+stderr=serial,vidconsole
fdt_high=0xffffffff
initrd_high=0xffffffff
fdt_addr=0x40000000
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 6114e1b..d56b4b5 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -25,6 +25,10 @@
hex
default 0x80100000
+config PRE_CON_BUF_ADDR
+ hex
+ default 0x81000000
+
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
@@ -53,6 +57,7 @@
imply NVME
imply PCI
imply PCIE_ECAM_GENERIC
+ imply DM_RNG
imply SCSI
imply DM_SCSI
imply SYS_NS16550
@@ -68,5 +73,14 @@
imply MTD_NOR_FLASH
imply CFI_FLASH
imply OF_HAS_PRIOR_STAGE
+ imply VIDEO
+ imply VIDEO_BOCHS
+ imply SYS_WHITE_ON_BLACK
+ imply PRE_CONSOLE_BUFFER
+ imply USB
+ imply USB_XHCI_HCD
+ imply USB_XHCI_PCI
+ imply USB_KEYBOARD
+ imply CMD_USB
endif
diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c
index ae3b7a3..181abbb 100644
--- a/board/emulation/qemu-riscv/qemu-riscv.c
+++ b/board/emulation/qemu-riscv/qemu-riscv.c
@@ -12,6 +12,7 @@
#include <log.h>
#include <spl.h>
#include <init.h>
+#include <usb.h>
#include <virtio_types.h>
#include <virtio.h>
@@ -41,29 +42,9 @@
int board_late_init(void)
{
- ulong kernel_start;
- ofnode chosen_node;
- int ret;
-
- chosen_node = ofnode_path("/chosen");
- if (!ofnode_valid(chosen_node)) {
- debug("No chosen node found, can't get kernel start address\n");
- return 0;
- }
-
-#ifdef CONFIG_ARCH_RV64I
- ret = ofnode_read_u64(chosen_node, "riscv,kernel-start",
- (u64 *)&kernel_start);
-#else
- ret = ofnode_read_u32(chosen_node, "riscv,kernel-start",
- (u32 *)&kernel_start);
-#endif
- if (ret) {
- debug("Can't find kernel start address in device tree\n");
- return 0;
- }
-
- env_set_hex("kernel_start", kernel_start);
+ /* start usb so that usb keyboard can be used as input device */
+ if (CONFIG_IS_ENABLED(USB_KEYBOARD))
+ usb_init();
return 0;
}
diff --git a/board/emulation/qemu-x86/qemu-x86.env b/board/emulation/qemu-x86/qemu-x86.env
new file mode 100644
index 0000000..adcc1c5
--- /dev/null
+++ b/board/emulation/qemu-x86/qemu-x86.env
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <env/x86.env>
diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c
index 1846134..af9044a 100644
--- a/board/engicam/imx8mm/spl.c
+++ b/board/engicam/imx8mm/spl.c
@@ -16,6 +16,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/ddr.h>
+#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c
index 6e95138..3543781 100644
--- a/board/freescale/imx8mm_evk/spl.c
+++ b/board/freescale/imx8mm_evk/spl.c
@@ -19,6 +19,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/ddr.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c
index ec0378b..dd54fa9 100644
--- a/board/freescale/imx8mn_evk/spl.c
+++ b/board/freescale/imx8mn_evk/spl.c
@@ -20,6 +20,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/ddr.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c
index bea9ddc..818cdd6 100644
--- a/board/freescale/imx8mq_evk/spl.c
+++ b/board/freescale/imx8mq_evk/spl.c
@@ -20,6 +20,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <fsl_sec.h>
#include <mmc.h>
diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c
index 332a662..17fd437 100644
--- a/board/freescale/imx8qm_mek/spl.c
+++ b/board/freescale/imx8qm_mek/spl.c
@@ -17,6 +17,7 @@
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <asm/arch/sys_proto.h>
+#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c
index 75aab16..462c43c 100644
--- a/board/freescale/imx8qxp_mek/spl.c
+++ b/board/freescale/imx8qxp_mek/spl.c
@@ -22,6 +22,7 @@
#include <asm/arch/imx8-pins.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
+#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c
index 66d0f68..c49b5be 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -20,6 +20,7 @@
#include <asm/arch/rdc.h>
#include <asm/arch/upower.h>
#include <asm/mach-imx/ele_api.h>
+#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index 63883b3..be9c24f 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -20,6 +20,7 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch-mx7ulp/gpio.h>
#include <asm/mach-imx/syscounter.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS
index 5fc7e93..89d1085 100644
--- a/board/freescale/ls1012afrdm/MAINTAINERS
+++ b/board/freescale/ls1012afrdm/MAINTAINERS
@@ -1,5 +1,5 @@
LS1012AFRDM BOARD
-M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+M: Pramod Kumar <pramod.kumar_1@nxp.com>
S: Maintained
F: board/freescale/ls1012afrdm/
F: include/configs/ls1012afrdm.h
diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS
index c1bb8d5..eabf580 100644
--- a/board/freescale/ls1012aqds/MAINTAINERS
+++ b/board/freescale/ls1012aqds/MAINTAINERS
@@ -1,5 +1,4 @@
LS1012AQDS BOARD
-M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
M: Pramod Kumar <pramod.kumar_1@nxp.com>
S: Maintained
F: board/freescale/ls1012aqds/
diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS
index b0c008b..ce2f9a1 100644
--- a/board/freescale/ls1012ardb/MAINTAINERS
+++ b/board/freescale/ls1012ardb/MAINTAINERS
@@ -1,5 +1,4 @@
LS1012ARDB BOARD
-M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
M: Pramod Kumar <pramod.kumar_1@nxp.com>
S: Maintained
F: board/freescale/ls1012ardb/
diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c
index 8605d06..d6f22bd 100644
--- a/board/freescale/ls1021aiot/ls1021aiot.c
+++ b/board/freescale/ls1021aiot/ls1021aiot.c
@@ -18,6 +18,7 @@
#include <asm/arch/ls102xa_devdis.h>
#include <asm/arch/ls102xa_soc.h>
+#include <asm/sections.h>
#include <fsl_csu.h>
#include <fsl_immap.h>
#include <netdev.h>
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index d5cb731..a618ce1 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -16,6 +16,7 @@
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/ls102xa_devdis.h>
+#include <asm/sections.h>
#include <hwconfig.h>
#include <mmc.h>
#include <fsl_csu.h>
diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c
index d144f25..d0e4e79 100644
--- a/board/freescale/ls1021atsn/ls1021atsn.c
+++ b/board/freescale/ls1021atsn/ls1021atsn.c
@@ -12,6 +12,7 @@
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/global_data.h>
+#include <asm/sections.h>
#include <linux/delay.h>
#include "../common/sleep.h"
#include <fsl_validate.h>
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 4f58343..27b9d79 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -18,6 +18,7 @@
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_devdis.h>
#include <asm/arch/ls102xa_soc.h>
+#include <asm/sections.h>
#include <hwconfig.h>
#include <mmc.h>
#include <fsl_csu.h>
diff --git a/board/freescale/ls1028a/MAINTAINERS b/board/freescale/ls1028a/MAINTAINERS
index 9e7b069..551f6a0 100644
--- a/board/freescale/ls1028a/MAINTAINERS
+++ b/board/freescale/ls1028a/MAINTAINERS
@@ -1,5 +1,4 @@
LS1028AQDS BOARD
-M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
M: Tang Yuantian <andy.tang@nxp.com>
S: Maintained
F: board/freescale/ls1028a/
@@ -9,7 +8,6 @@
F: configs/ls1028aqds_tfa_lpuart_defconfig
LS1028ARDB BOARD
-M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
M: Tang Yuantian <andy.tang@nxp.com>
S: Maintained
F: board/freescale/ls1028a/
diff --git a/board/freescale/ls1043aqds/MAINTAINERS b/board/freescale/ls1043aqds/MAINTAINERS
index 9fb6cc8..f7420ec 100644
--- a/board/freescale/ls1043aqds/MAINTAINERS
+++ b/board/freescale/ls1043aqds/MAINTAINERS
@@ -1,6 +1,5 @@
LS1043AQDS BOARD
M: Mingkai Hu <mingkai.hu@nxp.com>
-M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls1043aqds/
F: include/configs/ls1043aqds.h
diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS
index 8e14ba3..06b2388 100644
--- a/board/freescale/ls1043ardb/MAINTAINERS
+++ b/board/freescale/ls1043ardb/MAINTAINERS
@@ -1,6 +1,5 @@
LS1043A BOARD
M: Mingkai Hu <mingkai.hu@nxp.com>
-M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls1043ardb/
F: include/configs/ls1043ardb.h
diff --git a/board/freescale/ls1046aqds/MAINTAINERS b/board/freescale/ls1046aqds/MAINTAINERS
index 72c4253..e1db2aa 100644
--- a/board/freescale/ls1046aqds/MAINTAINERS
+++ b/board/freescale/ls1046aqds/MAINTAINERS
@@ -1,6 +1,5 @@
LS1046AQDS BOARD
M: Mingkai Hu <Mingkai.Hu@nxp.com>
-M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls1046aqds/
F: include/configs/ls1046aqds.h
diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS
index 3c8cfe7..d5a6b26 100644
--- a/board/freescale/ls1046ardb/MAINTAINERS
+++ b/board/freescale/ls1046ardb/MAINTAINERS
@@ -1,6 +1,5 @@
LS1046A BOARD
M: Mingkai Hu <mingkai.hu@nxp.com>
-M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls1046ardb/
F: board/freescale/ls1046ardb/ls1046ardb.c
diff --git a/board/freescale/ls1088a/MAINTAINERS b/board/freescale/ls1088a/MAINTAINERS
index 5c7925a..95a1414 100644
--- a/board/freescale/ls1088a/MAINTAINERS
+++ b/board/freescale/ls1088a/MAINTAINERS
@@ -1,6 +1,5 @@
LS1088ARDB BOARD
M: Ashish Kumar <Ashish.Kumar@nxp.com>
-M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls1088a/
F: include/configs/ls1088ardb.h
@@ -11,7 +10,6 @@
LS1088AQDS BOARD
M: Ashish Kumar <Ashish.Kumar@nxp.com>
-M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls1088a/
F: include/configs/ls1088aqds.h
diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS
index 39d02ae..fdad199 100644
--- a/board/freescale/ls2080aqds/MAINTAINERS
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@@ -1,6 +1,5 @@
LS2080A BOARD
M: Priyanka Jain <priyanka.jain@nxp.com>
-M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
M: Wasim Khan <wasim.khan@nxp.com>
S: Maintained
F: board/freescale/ls2080aqds/
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
index f49d26a..f2f834f 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -10,7 +10,6 @@
LS2088A_QSPI-boot BOARD
M: Priyanka Jain <priyanka.jain@nxp.com>
-M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
M: Wasim Khan <wasim.khan@nxp.com>
S: Maintained
F: configs/ls2088ardb_qspi_defconfig
diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c
index 039deb5..77e9200 100644
--- a/board/freescale/mx6sabreauto/mx6sabreauto.c
+++ b/board/freescale/mx6sabreauto/mx6sabreauto.c
@@ -15,6 +15,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
+#include <asm/sections.h>
#include <env.h>
#include <linux/errno.h>
#include <asm/gpio.h>
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 96a76b0..b558a59 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -14,6 +14,7 @@
#include <asm/arch/mx6-pins.h>
#include <asm/global_data.h>
#include <asm/mach-imx/spi.h>
+#include <asm/sections.h>
#include <env.h>
#include <linux/errno.h>
#include <asm/gpio.h>
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 2c90a35..e9ac571 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -19,6 +19,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
+#include <asm/sections.h>
#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc_imx.h>
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 570b501..534b16c 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -18,6 +18,7 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
+#include <asm/sections.h>
#include <common.h>
#include <env.h>
#include <fsl_esdhc_imx.h>
diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS
index 4e82f7f..55fdb60 100644
--- a/board/freescale/t104xrdb/MAINTAINERS
+++ b/board/freescale/t104xrdb/MAINTAINERS
@@ -24,8 +24,3 @@
F: configs/T1040D4RDB_SDCARD_defconfig
F: configs/T1042D4RDB_SDCARD_defconfig
F: configs/T1042RDB_PI_SDCARD_defconfig
-
-T1042D4RDB_SECURE_BOOT BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
-F: configs/T1042D4RDB_SECURE_BOOT_defconfig
diff --git a/board/freescale/t208xrdb/MAINTAINERS b/board/freescale/t208xrdb/MAINTAINERS
index 6e9b25f..5be7a25 100644
--- a/board/freescale/t208xrdb/MAINTAINERS
+++ b/board/freescale/t208xrdb/MAINTAINERS
@@ -12,8 +12,3 @@
F: configs/T2080RDB_revD_NAND_defconfig
F: configs/T2080RDB_revD_SDCARD_defconfig
F: configs/T2080RDB_revD_SPIFLASH_defconfig
-
-T2080RDB_SECURE_BOOT BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
-F: configs/T2080RDB_SECURE_BOOT_defconfig
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
index 5aa2095..774a990 100644
--- a/board/gateworks/venice/spl.c
+++ b/board/gateworks/venice/spl.c
@@ -19,6 +19,7 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/ddr.h>
#include <asm-generic/gpio.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/pinctrl.h>
diff --git a/board/htc/endeavoru/Kconfig b/board/htc/endeavoru/Kconfig
new file mode 100644
index 0000000..0b72c4a
--- /dev/null
+++ b/board/htc/endeavoru/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ENDEAVORU
+
+config SYS_BOARD
+ default "endeavoru"
+
+config SYS_VENDOR
+ default "htc"
+
+config SYS_CONFIG_NAME
+ default "endeavoru"
+
+endif
diff --git a/board/htc/endeavoru/MAINTAINERS b/board/htc/endeavoru/MAINTAINERS
new file mode 100644
index 0000000..85f439f
--- /dev/null
+++ b/board/htc/endeavoru/MAINTAINERS
@@ -0,0 +1,7 @@
+ENDEAVORU BOARD
+M: Svyatoslav Ryhel <clamor95@gmail.com>
+S: Maintained
+F: board/htc/endeavoru/
+F: configs/endeavoru_defconfig
+F: doc/board/htc/endeavoru.rst
+F: include/configs/endeavoru.h
diff --git a/board/htc/endeavoru/Makefile b/board/htc/endeavoru/Makefile
new file mode 100644
index 0000000..0c6ba4a
--- /dev/null
+++ b/board/htc/endeavoru/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010-2012
+# NVIDIA Corporation <www.nvidia.com>
+#
+# (C) Copyright 2021
+# Svyatoslav Ryhel <clamor95@gmail.com>
+
+obj-$(CONFIG_SPL_BUILD) += endeavoru-spl.o
+
+obj-y += endeavoru.o
diff --git a/board/htc/endeavoru/endeavoru-spl.c b/board/htc/endeavoru/endeavoru-spl.c
new file mode 100644
index 0000000..7921ff1
--- /dev/null
+++ b/board/htc/endeavoru/endeavoru-spl.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * T30 HTC Endeavoru SPL stage configuration
+ *
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2022
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+/*
+ * Endeavoru uses TPS80032 PMIC with SMPS1 and SMPS2 in strandard
+ * mode with zero offset.
+ */
+
+#define TPS80032_DVS_I2C_ADDR (0x12 << 1)
+#define TPS80032_SMPS1_CFG_VOLTAGE_REG 0x56
+#define TPS80032_SMPS2_CFG_VOLTAGE_REG 0x5C
+#define TPS80032_SMPS1_CFG_VOLTAGE_DATA (0x2100 | TPS80032_SMPS1_CFG_VOLTAGE_REG)
+#define TPS80032_SMPS2_CFG_VOLTAGE_DATA (0x3000 | TPS80032_SMPS2_CFG_VOLTAGE_REG)
+
+#define TPS80032_CTL1_I2C_ADDR (0x48 << 1)
+#define TPS80032_SMPS1_CFG_STATE_REG 0x54
+#define TPS80032_SMPS2_CFG_STATE_REG 0x5A
+#define TPS80032_SMPS1_CFG_STATE_DATA (0x0100 | TPS80032_SMPS1_CFG_STATE_REG)
+#define TPS80032_SMPS2_CFG_STATE_DATA (0x0100 | TPS80032_SMPS2_CFG_STATE_REG)
+
+void pmic_enable_cpu_vdd(void)
+{
+ /* Set VDD_CORE to 1.200V. */
+ tegra_i2c_ll_write(TPS80032_DVS_I2C_ADDR, TPS80032_SMPS2_CFG_VOLTAGE_DATA);
+ udelay(1000);
+ tegra_i2c_ll_write(TPS80032_CTL1_I2C_ADDR, TPS80032_SMPS2_CFG_STATE_DATA);
+
+ udelay(1000);
+
+ /* Bring up VDD_CPU to 1.0125V. */
+ tegra_i2c_ll_write(TPS80032_DVS_I2C_ADDR, TPS80032_SMPS1_CFG_VOLTAGE_DATA);
+ udelay(1000);
+ tegra_i2c_ll_write(TPS80032_CTL1_I2C_ADDR, TPS80032_SMPS1_CFG_STATE_DATA);
+ udelay(10 * 1000);
+}
diff --git a/board/htc/endeavoru/endeavoru.c b/board/htc/endeavoru/endeavoru.c
new file mode 100644
index 0000000..1d92870
--- /dev/null
+++ b/board/htc/endeavoru/endeavoru.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2021
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <log.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch-tegra/fuse.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+#include "pinmux-config-endeavoru.h"
+
+#define TPS80032_CTL1_I2C_ADDR 0x48
+#define TPS80032_PHOENIX_DEV_ON 0x25
+#define DEVOFF BIT(0)
+#define TPS80032_LDO1_CFG_STATE 0x9E
+#define TPS80032_LDO1_CFG_VOLTAGE 0x9F
+
+#ifdef CONFIG_CMD_POWEROFF
+int do_poweroff(struct cmd_tbl *cmdtp, int flag,
+ int argc, char *const argv[])
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(0, TPS80032_CTL1_I2C_ADDR, 1, &dev);
+ if (ret) {
+ log_debug("cannot find PMIC I2C chip\n");
+ return 0;
+ }
+
+ ret = dm_i2c_reg_write(dev, TPS80032_PHOENIX_DEV_ON, DEVOFF);
+ if (ret)
+ return ret;
+
+ // wait some time and then print error
+ mdelay(5000);
+
+ printf("Failed to power off!!!\n");
+ return 1;
+}
+#endif
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_config_pingrp_table(endeavoru_pinmux_common,
+ ARRAY_SIZE(endeavoru_pinmux_common));
+}
+
+#ifdef CONFIG_MMC_SDHCI_TEGRA
+static void tps80032_voltage_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(0, TPS80032_CTL1_I2C_ADDR, 1, &dev);
+ if (ret)
+ log_debug("cannot find PMIC I2C chip\n");
+
+ /* TPS80032: LDO1_REG = 1.2v to DSI */
+ ret = dm_i2c_reg_write(dev, TPS80032_LDO1_CFG_VOLTAGE, 0x03);
+ if (ret)
+ log_debug("avdd_dsi_csi voltage set failed: %d\n", ret);
+
+ /* TPS80032: LDO1_REG enable */
+ ret = dm_i2c_reg_write(dev, TPS80032_LDO1_CFG_STATE, 0x01);
+ if (ret)
+ log_debug("avdd_dsi_csi enable failed: %d\n", ret);
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the MMC muxes, power rails, etc.
+ */
+void pin_mux_mmc(void)
+{
+ /* Bring up DSI power */
+ tps80032_voltage_init();
+}
+#endif /* MMC */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /* Remove TrustZone nodes */
+ fdt_del_node_and_alias(blob, "/firmware");
+ fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000");
+
+ return 0;
+}
+#endif
+
+void nvidia_board_late_init(void)
+{
+ char serialno_str[17];
+
+ /* Set chip id as serialno */
+ sprintf(serialno_str, "%016llx", tegra_chip_uid());
+ env_set("serial#", serialno_str);
+ env_set("platform", "Tegra 3 T30");
+}
diff --git a/board/htc/endeavoru/pinmux-config-endeavoru.h b/board/htc/endeavoru/pinmux-config-endeavoru.h
new file mode 100644
index 0000000..a00c5c9
--- /dev/null
+++ b/board/htc/endeavoru/pinmux-config-endeavoru.h
@@ -0,0 +1,362 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Copyright (c) 2022, Svyatoslav Ryhel.
+ */
+
+#ifndef _PINMUX_CONFIG_ENDEAVORU_H_
+#define _PINMUX_CONFIG_ENDEAVORU_H_
+
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
+ }
+
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
+ }
+
+static struct pmux_pingrp_config endeavoru_pinmux_common[] = {
+ /* SDMMC1 pinmux */
+ DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3_PY4, UARTE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2_PY5, UARTE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1_PY6, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
+
+ /* SDMMC3 pinmux */
+ DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT6_PD3, INVALID, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT7_PD4, INVALID, NORMAL, NORMAL, INPUT),
+
+ /* SDMMC4 pinmux */
+ LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* I2C pinmux */
+ I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* HDMI pinmux */
+ DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
+
+ /* ULPI pinmux */
+ DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2_PO3, SPI3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3_PO4, HSI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4_PO5, SPI2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7_PO0, SPI2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_CLK_PY0, RSVD2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DIR_PY1, RSVD2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_NXT_PY2, ULPI, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_STP_PY3, ULPI, NORMAL, NORMAL, INPUT),
+
+ /* DAP3 pinmux */
+ DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
+
+ /* PV-gpio group pinmux */
+ DEFAULT_PINMUX(PV0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV2, RSVD2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PV3, RSVD2, NORMAL, NORMAL, OUTPUT),
+
+ /* CLK2 pinmux */
+ DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD4, NORMAL, NORMAL, OUTPUT),
+
+ /* LCD pinmux */
+ DEFAULT_PINMUX(LCD_PWR1_PC1, RSVD4, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS0_N_PN4, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, UP, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D2_PE2, RSVD3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D6_PE6, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D8_PF0, RSVD4, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D14_PF6, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D15_PF7, RSVD4, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D18_PM2, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D19_PM3, RSVD4, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D21_PM5, RSVD4, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(LCD_D22_PM6, RSVD4, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(LCD_D23_PM7, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS1_N_PW0, RSVD4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(LCD_DC1_PD2, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CRT_VSYNC_PV7, RSVD4, NORMAL, NORMAL, OUTPUT),
+
+ /* VI-group pinmux */
+ LV_PINMUX(VI_D0_PT4, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D4_PL2, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D6_PL4, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D10_PT2, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D11_PT3, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_PCLK_PT0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_MCLK_PT1, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_VSYNC_PD6, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_HSYNC_PD7, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* UART-2 pinmux */
+ DEFAULT_PINMUX(UART2_RXD_PC3, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD_PC2, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_RTS_N_PJ6, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_CTS_N_PJ5, SPI4, NORMAL, NORMAL, INPUT),
+
+ /* UART-3 pinmux */
+ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
+
+ /* PU-gpio group pinmux */
+ DEFAULT_PINMUX(PU0, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU1, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU2, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU3, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU4, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU5, RSVD4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU6, PWM3, UP, TRISTATE, INPUT),
+
+ /* DAP4 pinmux */
+ DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT_PP6, RSVD4, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP4_SCLK_PP7, RSVD4, NORMAL, NORMAL, OUTPUT),
+
+ /* CLK3 pinmux */
+ DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD4, NORMAL, TRISTATE, INPUT),
+
+ /* GMI pinmux */
+ DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_WAIT_PI7, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_ADV_N_PK0, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CLK_PK1, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS1_N_PJ2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS6_N_PI3, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD0_PG0, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD1_PG1, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD2_PG2, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD3_PG3, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD4_PG4, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD5_PG5, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD6_PG6, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD7_PG7, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD9_PH1, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11_PH3, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD12_PH4, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD13_PH5, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD14_PH6, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD15_PH7, NAND, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_WR_N_PI0, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_OE_N_PI1, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_DQS_PI2, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_RST_N_PI4, RSVD4, UP, TRISTATE, INPUT),
+
+ DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(PCC1, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB0, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB7, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PCC2, RSVD3, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, UP, NORMAL, INPUT),
+
+ /* KBC keys */
+ DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW1_PR1, KBC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW2_PR2, RSVD4, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW3_PR3, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW4_PR4, RSVD4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW10_PS2, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW11_PS3, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW12_PS4, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW13_PS5, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW14_PS6, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW15_PS7, KBC, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6_PQ6, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, NORMAL, INPUT),
+
+ /* CLK */
+ DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(OWR, OWR, UP, NORMAL, INPUT),
+
+ /* DAP1 pinmux */
+ DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, TRISTATE, OUTPUT),
+
+ /* CLK1 pinmux */
+ DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_OUT_PW4, RSVD4, NORMAL, NORMAL, INPUT),
+
+ /* SPDIF pinmux */
+ DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, TRISTATE, OUTPUT),
+
+ /* DAP2 pinmux */
+ DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, DOWN, NORMAL, INPUT),
+
+ /* SPI pinmux */
+ DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SPI2_MISO_PX1, SPI2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_CS0_N_PX3, SPI2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SPI2_SCK_PX2, SPI2, NORMAL, NORMAL, OUTPUT),
+
+ DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_CS2_N_PW3, SPI2, UP, TRISTATE, INPUT),
+
+ DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_SCK_PX5, SPI2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MISO_PX7, RSVD4, NORMAL, NORMAL, OUTPUT),
+
+ /* PEX pinmux */
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
+};
+
+#endif /* _PINMUX_CONFIG_TRANSFORMER_H_ */
diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c
index 8532225..cecf454 100644
--- a/board/imgtec/boston/ddr.c
+++ b/board/imgtec/boston/ddr.c
@@ -23,7 +23,7 @@
return 0;
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/intel/bayleybay/bayleybay.env b/board/intel/bayleybay/bayleybay.env
new file mode 100644
index 0000000..89e1849
--- /dev/null
+++ b/board/intel/bayleybay/bayleybay.env
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <env/x86.env>
+
+/* don't use i8042-kbd */
+stdin=serial,usbkbd
diff --git a/board/intel/cherryhill/cherryhill.env b/board/intel/cherryhill/cherryhill.env
new file mode 100644
index 0000000..929b6a1
--- /dev/null
+++ b/board/intel/cherryhill/cherryhill.env
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <env/x86.env>
+
+/* don't use i8042-kbd */
+stdin=serial,usbkbd
diff --git a/board/intel/cougarcanyon2/cougarcanyon2.env b/board/intel/cougarcanyon2/cougarcanyon2.env
new file mode 100644
index 0000000..6329b0f
--- /dev/null
+++ b/board/intel/cougarcanyon2/cougarcanyon2.env
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <env/x86.env>
diff --git a/board/intel/crownbay/crownbay.env b/board/intel/crownbay/crownbay.env
new file mode 100644
index 0000000..9e95414
--- /dev/null
+++ b/board/intel/crownbay/crownbay.env
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <env/x86.env>
diff --git a/board/intel/edison/edison.env b/board/intel/edison/edison.env
new file mode 100644
index 0000000..c7d4de7
--- /dev/null
+++ b/board/intel/edison/edison.env
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Intel Corp.
+ */
+
+/* empty environment */
diff --git a/board/intel/galileo/galileo.env b/board/intel/galileo/galileo.env
new file mode 100644
index 0000000..83e77bb
--- /dev/null
+++ b/board/intel/galileo/galileo.env
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <env/x86.env>
+
+/* use just serial */
+stdin=serial
+stdout=serial
+stderr=serial
diff --git a/board/intel/minnowmax/minnowmax.env b/board/intel/minnowmax/minnowmax.env
new file mode 100644
index 0000000..71f3607
--- /dev/null
+++ b/board/intel/minnowmax/minnowmax.env
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Google, Inc
+ */
+
+#include <env/x86.env>
+
+/* don't use i8042-kbd */
+stdin=usbkbd,serial
+
+usb_pgood_delay=40
diff --git a/board/intel/slimbootloader/slimbootloader.env b/board/intel/slimbootloader/slimbootloader.env
new file mode 100644
index 0000000..3fce487
--- /dev/null
+++ b/board/intel/slimbootloader/slimbootloader.env
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <env/x86.env>
+
+/* don't use video */
+stdout=serial
+stderr=serial
+
+usb_pgood_delay=40
+
+ramdiskaddr=0x4000000
+ramdiskfile=initrd
+bootdev=usb
+bootdevnum=0
+bootdevpart=0
+bootfsload=fatload
+bootusb=setenv bootdev usb; boot
+bootscsi=setenv bootdev scsi; boot
+bootmmc=setenv bootdev mmc; boot
+bootargs=console=ttyS0,115200 console=tty0
diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
index 103c453..5490243 100644
--- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
+++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
@@ -14,6 +14,7 @@
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
+#include <asm/sections.h>
#include <asm/io.h>
#include <errno.h>
#include <spl.h>
diff --git a/board/keymile/km83xx/km83xx.env b/board/keymile/km83xx/km83xx.env
index ed2487c..1f13aaa 100644
--- a/board/keymile/km83xx/km83xx.env
+++ b/board/keymile/km83xx/km83xx.env
@@ -13,8 +13,8 @@
uimage=uImage
#endif
-#include <environment/pg-wcom/common.env>
-#include <environment/pg-wcom/powerpc.env>
+#include <env/pg-wcom/common.env>
+#include <env/pg-wcom/powerpc.env>
#if CONFIG_TARGET_KMCOGE5NE
add_default+= eccmode=bch
diff --git a/board/keymile/kmcent2/kmcent2.env b/board/keymile/kmcent2/kmcent2.env
index 6b676a4..efa762e 100644
--- a/board/keymile/kmcent2/kmcent2.env
+++ b/board/keymile/kmcent2/kmcent2.env
@@ -1,4 +1,4 @@
-#include <environment/pg-wcom/common.env>
+#include <env/pg-wcom/common.env>
EEprom_ivm=pca9547:70:9
arch=ppc_82xx
diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env b/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env
index d960de6..1054dbf 100644
--- a/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env
+++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env
@@ -1,3 +1,3 @@
-#include <environment/pg-wcom/ls102xa.env>
+#include <env/pg-wcom/ls102xa.env>
hostname=EXPU1
diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env b/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env
index 4031f8b..1232fe9 100644
--- a/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env
+++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env
@@ -1,3 +1,3 @@
-#include <environment/pg-wcom/ls102xa.env>
+#include <env/pg-wcom/ls102xa.env>
hostname=SELI8
diff --git a/board/kontron/pitx_imx8m/spl.c b/board/kontron/pitx_imx8m/spl.c
index f6fd170..a247803 100644
--- a/board/kontron/pitx_imx8m/spl.c
+++ b/board/kontron/pitx_imx8m/spl.c
@@ -16,6 +16,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/sections.h>
#include <linux/delay.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
diff --git a/board/kontron/sl-mx6ul/spl.c b/board/kontron/sl-mx6ul/spl.c
index a9d370b..b175885 100644
--- a/board/kontron/sl-mx6ul/spl.c
+++ b/board/kontron/sl-mx6ul/spl.c
@@ -11,6 +11,7 @@
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/mach-imx/iomux-v3.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <init.h>
#include <linux/delay.h>
diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c
index b493734..54ee1e66 100644
--- a/board/kontron/sl-mx8mm/spl.c
+++ b/board/kontron/sl-mx8mm/spl.c
@@ -12,6 +12,7 @@
#include <asm/gpio.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
diff --git a/board/lg/x3-t30/Kconfig b/board/lg/x3-t30/Kconfig
new file mode 100644
index 0000000..20ea4f5
--- /dev/null
+++ b/board/lg/x3-t30/Kconfig
@@ -0,0 +1,26 @@
+if TARGET_X3_T30
+
+config SYS_BOARD
+ default "x3-t30"
+
+config SYS_VENDOR
+ default "lg"
+
+config SYS_CONFIG_NAME
+ default "x3-t30"
+
+config DEVICE_P880
+ bool "Enable support for LG Optimus 4X HD"
+ default n
+ help
+ LG Optimus 4X HD derives from x3 board but has slight
+ differences.
+
+config DEVICE_P895
+ bool "Enable support for LG Optimus Vu"
+ default n
+ help
+ LG Optimus Vu derives from x3 board but has slight
+ differences.
+
+endif
diff --git a/board/lg/x3-t30/MAINTAINERS b/board/lg/x3-t30/MAINTAINERS
new file mode 100644
index 0000000..0ad2956
--- /dev/null
+++ b/board/lg/x3-t30/MAINTAINERS
@@ -0,0 +1,9 @@
+X3 BOARD
+M: Svyatoslav Ryhel <clamor95@gmail.com>
+S: Maintained
+F: board/lg/x3-t30/
+F: configs/p880.config
+F: configs/p895.config
+F: configs/x3_t30_defconfig
+F: doc/board/lg/x3_t30.rst
+F: include/configs/x3-t30.h
diff --git a/board/lg/x3-t30/Makefile b/board/lg/x3-t30/Makefile
new file mode 100644
index 0000000..3eeb132
--- /dev/null
+++ b/board/lg/x3-t30/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010-2012
+# NVIDIA Corporation <www.nvidia.com>
+#
+# (C) Copyright 2021
+# Svyatoslav Ryhel <clamor95@gmail.com>
+
+obj-$(CONFIG_SPL_BUILD) += x3-t30-spl.o
+
+obj-y += x3-t30.o
diff --git a/board/lg/x3-t30/pinmux-config-x3.h b/board/lg/x3-t30/pinmux-config-x3.h
new file mode 100644
index 0000000..cdb2809
--- /dev/null
+++ b/board/lg/x3-t30/pinmux-config-x3.h
@@ -0,0 +1,449 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Copyright (c) 2021, Svyatoslav Ryhel.
+ */
+
+#ifndef _PINMUX_CONFIG_X3_H_
+#define _PINMUX_CONFIG_X3_H_
+
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
+ }
+
+static struct pmux_pingrp_config tegra3_x3_pinmux_common[] = {
+ /* SDMMC1 pinmux */
+ DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
+
+ /* SDMMC3 pinmux */
+// DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific
+// DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific
+// DEFAULT_PINMUX(SDMMC3_DAT0_PB7, RSVD1, NORMAL, TRISTATE, INPUT), // device specific
+// DEFAULT_PINMUX(SDMMC3_DAT1_PB6, RSVD1, NORMAL, NORMAL, INPUT), // device specific
+// DEFAULT_PINMUX(SDMMC3_DAT2_PB5, RSVD1, NORMAL, TRISTATE, INPUT), // device specific
+// DEFAULT_PINMUX(SDMMC3_DAT3_PB4, RSVD1, NORMAL, TRISTATE, INPUT), // device specific
+// DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific
+// DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific
+// DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific
+// DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD2, NORMAL, TRISTATE, INPUT), // device specific
+
+ /* SDMMC4 pinmux */
+ LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+// LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), // device specific
+ LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD2, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* I2C1 pinmux */
+ I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C2 pinmux */
+ I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, UP, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, UP, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C3 pinmux */
+ I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C4 pinmux */
+ I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* Power I2C pinmux */
+ I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* HDMI-CEC pinmux */
+ DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
+
+ /* ULPI pinmux */
+ DEFAULT_PINMUX(ULPI_DATA0_PO1, SPI3, UP, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DATA1_PO2, SPI3, UP, NORMAL, OUTPUT), // LCD_BRIDGE_RESET_N
+ DEFAULT_PINMUX(ULPI_DATA2_PO3, SPI3, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3_PO4, SPI3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT),
+// DEFAULT_PINMUX(ULPI_DATA5_PO6, SPI2, UP, TRISTATE, INPUT), // unconfigured
+// DEFAULT_PINMUX(ULPI_DATA6_PO7, SPI2, UP, NORMAL, INPUT), // device specific
+// DEFAULT_PINMUX(ULPI_DATA7_PO0, SPI2, UP, NORMAL, INPUT), // unconfigured
+ DEFAULT_PINMUX(ULPI_CLK_PY0, RSVD2, DOWN, NORMAL, OUTPUT), // LCD_EN
+ DEFAULT_PINMUX(ULPI_DIR_PY1, RSVD2, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_NXT_PY2, RSVD2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT),
+
+ /* DAP3 pinmux */
+ DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PV3, RSVD2, DOWN, NORMAL, INPUT),
+
+ /* CLK2 pinmux */
+ DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, OUTPUT),
+
+ /* LCD pinmux */
+ DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, OUTPUT),
+// DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, DOWN, TRISTATE, OUTPUT), // unconfigured
+ DEFAULT_PINMUX(LCD_SDIN_PZ2, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_SDI
+ DEFAULT_PINMUX(LCD_SDOUT_PN5, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_SDO
+ DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS0_N_PN4, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_CS
+ DEFAULT_PINMUX(LCD_DC0_PN6, RSVD3, NORMAL, NORMAL, OUTPUT), // LCD_CP_EN / BL
+ DEFAULT_PINMUX(LCD_SCK_PZ4, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_SCL
+ DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), // LCD_RGB_PCLK
+ DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), // LCD_RGB_HSYNC
+ DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), // LCD_RGB_VSYNC
+ DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS1_N_PW0, RSVD4, UP, NORMAL, OUTPUT), // LCD_RESET_N
+ DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, TRISTATE, OUTPUT), // LCD_MAKER_ID
+ DEFAULT_PINMUX(LCD_DC1_PD2, RSVD3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CRT_HSYNC_PV6, RSVD2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CRT_VSYNC_PV7, RSVD2, NORMAL, NORMAL, INPUT),
+
+ /* VI-group pinmux */
+ LV_PINMUX(VI_D0_PT4, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D10_PT2, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D11_PT3, RSVD2, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_HSYNC_PD7, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_VSYNC_PD6, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* UART-B pinmux */
+// DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), // device specific
+// DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), // device specific
+ DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
+
+ /* UART-C pinmux */
+ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
+
+ /* PU-gpio group pinmux */
+// DEFAULT_PINMUX(PU0, UARTA, NORMAL, NORMAL, OUTPUT), // device specific
+// DEFAULT_PINMUX(PU1, UARTA, NORMAL, NORMAL, INPUT), // device specific
+// DEFAULT_PINMUX(PU2, RSVD1, NORMAL, TRISTATE, INPUT), // device specific
+// DEFAULT_PINMUX(PU3, PWM0, NORMAL, TRISTATE, INPUT), // device specific
+// DEFAULT_PINMUX(PU4, PWM1, NORMAL, TRISTATE, INPUT), // device specific
+ DEFAULT_PINMUX(PU5, RSVD4, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU6, PWM3, DOWN, NORMAL, INPUT),
+
+ /* DAP4 pinmux */
+ DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
+
+ /* CLK3 pinmux */
+ DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), // MIPI_BRIDGE_CLK
+ DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(PCC1, RSVD3, NORMAL, NORMAL, OUTPUT),
+// DEFAULT_PINMUX(PBB0, RSVD2, NORMAL, NORMAL, OUTPUT), // device specific
+ DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB7, I2S4, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PCC2, RSVD3, NORMAL, NORMAL, OUTPUT),
+
+ DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
+
+ /* KBC keys */
+ DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW2_PR2, RSVD4, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW3_PR3, RSVD3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW4_PR4, RSVD4, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW5_PR5, KBC, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW6_PR6, KBC, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW7_PR7, KBC, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW9_PS1, KBC, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW10_PS2, KBC, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW11_PS3, KBC, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW12_PS4, KBC, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW14_PS6, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW15_PS7, KBC, DOWN, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL3_PQ3, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT),
+
+ /* CLK */
+ DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, INPUT),
+// DEFAULT_PINMUX(CORE_PWR_REQ, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured
+// DEFAULT_PINMUX(CPU_PWR_REQ, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured
+// DEFAULT_PINMUX(PWR_INT_N, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured
+// DEFAULT_PINMUX(CLK_32K_IN, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured
+ DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+
+ /* DAP1 pinmux */
+ DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
+
+ /* CLK1 pinmux */
+ DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, DOWN, NORMAL, INPUT),
+
+ /* SPDIF pinmux */
+ DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, OUTPUT),
+// DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, DOWN, NORMAL, OUTPUT), // device specific
+
+ /* DAP2 pinmux */
+ DEFAULT_PINMUX(DAP2_FS_PA2, HDA, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN_PA4, HDA, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT_PA5, HDA, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK_PA3, HDA, DOWN, NORMAL, INPUT),
+
+ /* SPI pinmux */
+ DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI2, NORMAL, NORMAL, OUTPUT),
+// DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, OUTPUT), // device specific
+// DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT), // device specific
+ DEFAULT_PINMUX(SPI1_MISO_PX7, RSVD4, NORMAL, NORMAL, OUTPUT),
+
+ DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SPI2_MISO_PX1, GMI, NORMAL, NORMAL, OUTPUT),
+// DEFAULT_PINMUX(SPI2_CS0_N_PX3, SPI6, UP, NORMAL, INPUT), // unconfigured
+// DEFAULT_PINMUX(SPI2_SCK_PX2, SPI6, UP, NORMAL, INPUT), // unconfigured
+ DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT),
+// DEFAULT_PINMUX(SPI2_CS2_N_PW3, SPI2, UP, TRISTATE, INPUT), // unconfigured
+
+ /* PEX pinmux */
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, TRISTATE, INPUT),
+
+ /* GMI pinmux */
+ DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WAIT_PI7, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_ADV_N_PK0, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CLK_PK1, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, UP, TRISTATE, INPUT), // LCD_RGB_DE
+ DEFAULT_PINMUX(GMI_CS1_N_PJ2, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, NORMAL, OUTPUT),
+// DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD4, UP, NORMAL, INPUT), // device specific
+ DEFAULT_PINMUX(GMI_CS6_N_PI3, GMI, UP, NORMAL, INPUT),
+// DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT), // device specific
+ DEFAULT_PINMUX(GMI_AD0_PG0, GMI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD1_PG1, GMI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD2_PG2, GMI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD3_PG3, GMI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD4_PG4, GMI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD5_PG5, GMI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD6_PG6, GMI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD7_PG7, GMI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD8_PH0, GMI, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD9_PH1, GMI, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD10_PH2, GMI, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11_PH3, PWM3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD12_PH4, RSVD4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD13_PH5, RSVD4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD14_PH6, GMI, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD15_PH7, GMI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A18_PB1, UARTD, DOWN, NORMAL, OUTPUT), // RGB_IC_EN
+ DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_WR_N_PI0, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_OE_N_PI1, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_DQS_PI2, GMI, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_RST_N_PI4, GMI, UP, NORMAL, INPUT),
+};
+
+#ifdef CONFIG_DEVICE_P880
+static struct pmux_pingrp_config tegra3_p880_pinmux[] = {
+ /* SDMMC3 pinmux */
+ DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, TRISTATE, INPUT),
+
+ /* SDMMC4 pinmux */
+ LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* ULPI pinmux */
+ DEFAULT_PINMUX(ULPI_DATA6_PO7, SPI2, NORMAL, NORMAL, INPUT),
+
+ /* UART-B pinmux */
+ DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, UP, NORMAL, OUTPUT),
+
+ /* GPIO group pinmux */
+ DEFAULT_PINMUX(PU0, UARTA, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU1, UARTA, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU2, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU3, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB0, I2S4, NORMAL, TRISTATE, INPUT),
+
+ /* SPDIF pinmux */
+ DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, UP, TRISTATE, OUTPUT),
+
+ /* SPI pinmux */
+ DEFAULT_PINMUX(SPI1_SCK_PX5, SPI2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
+
+ /* GMI pinmux */
+ DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, DOWN, NORMAL, OUTPUT),
+};
+#endif /* CONFIG_DEVICE_P880 */
+
+#ifdef CONFIG_DEVICE_P895
+static struct pmux_pingrp_config tegra3_p895_pinmux[] = {
+ /* SDMMC3 pinmux */
+ DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0_PB7, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1_PB6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2_PB5, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3_PB4, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD2, NORMAL, TRISTATE, INPUT),
+
+ /* SDMMC4 pinmux */
+ LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* ULPI pinmux */
+ DEFAULT_PINMUX(ULPI_DATA6_PO7, SPI2, UP, NORMAL, INPUT),
+
+ /* UART-B pinmux */
+ DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
+
+ /* Gpio group pinmux */
+ DEFAULT_PINMUX(PU0, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU1, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PU3, PWM0, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PU4, PWM1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PBB0, RSVD2, NORMAL, NORMAL, OUTPUT), // LCD_EN_3V0
+
+ /* SPDIF pinmux */
+ DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, DOWN, NORMAL, OUTPUT),
+
+ /* SPI pinmux */
+ DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT),
+
+ /* GMI pinmux */
+ DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT),
+};
+#endif /* CONFIG_DEVICE_P895 */
+#endif /* _PINMUX_CONFIG_X3_H_ */
diff --git a/board/lg/x3-t30/x3-t30-spl.c b/board/lg/x3-t30/x3-t30-spl.c
new file mode 100644
index 0000000..864f2de
--- /dev/null
+++ b/board/lg/x3-t30/x3-t30-spl.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * T30 LGE X3 SPL stage configuration
+ *
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2022
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+#define MAX77663_I2C_ADDR (0x1C << 1)
+
+#define MAX77663_REG_SD0 0x16
+#define MAX77663_REG_SD0_DATA (0x2100 | MAX77663_REG_SD0)
+#define MAX77663_REG_SD1 0x17
+#define MAX77663_REG_SD1_DATA (0x3000 | MAX77663_REG_SD1)
+#define MAX77663_REG_LDO4 0x2B
+#define MAX77663_REG_LDO4_DATA (0xE000 | MAX77663_REG_LDO4)
+
+#define MAX77663_REG_GPIO1 0x37
+#define MAX77663_REG_GPIO1_DATA (0x0800 | MAX77663_REG_GPIO1)
+#define MAX77663_REG_GPIO4 0x3A
+#define MAX77663_REG_GPIO4_DATA (0x0100 | MAX77663_REG_GPIO4)
+
+void pmic_enable_cpu_vdd(void)
+{
+ /* Set VDD_CORE to 1.200V. */
+ tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD1_DATA);
+
+ udelay(1000);
+
+ /* Bring up VDD_CPU to 1.0125V. */
+ tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD0_DATA);
+ udelay(1000);
+
+ /* Bring up VDD_RTC to 1.200V. */
+ tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_LDO4_DATA);
+ udelay(10 * 1000);
+
+ /* Set GPIO4 and GPIO1 states */
+ tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO4_DATA);
+ tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO1_DATA);
+}
diff --git a/board/lg/x3-t30/x3-t30.c b/board/lg/x3-t30/x3-t30.c
new file mode 100644
index 0000000..594563c
--- /dev/null
+++ b/board/lg/x3-t30/x3-t30.c
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2022
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <log.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/fuse.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+#include "pinmux-config-x3.h"
+
+#define MAX77663_I2C_ADDR 0x1C
+
+#define MAX77663_REG_SD2 0x18
+#define MAX77663_REG_LDO2 0x27
+#define MAX77663_REG_LDO3 0x29
+#define MAX77663_REG_LDO5 0x2D
+#define MAX77663_REG_ONOFF_CFG1 0x41
+#define ONOFF_PWR_OFF BIT(1)
+
+#ifdef CONFIG_CMD_POWEROFF
+int do_poweroff(struct cmd_tbl *cmdtp, int flag,
+ int argc, char *const argv[])
+{
+ struct udevice *dev;
+ uchar data_buffer[1];
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDR, 1, &dev);
+ if (ret) {
+ log_debug("cannot find PMIC I2C chip\n");
+ return 0;
+ }
+
+ ret = dm_i2c_read(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1);
+ if (ret)
+ return ret;
+
+ data_buffer[0] |= ONOFF_PWR_OFF;
+
+ ret = dm_i2c_write(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1);
+ if (ret)
+ return ret;
+
+ /* wait some time and then print error */
+ mdelay(5000);
+
+ printf("Failed to power off!!!\n");
+ return 1;
+}
+#endif
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_config_pingrp_table(tegra3_x3_pinmux_common,
+ ARRAY_SIZE(tegra3_x3_pinmux_common));
+
+#ifdef CONFIG_DEVICE_P880
+ pinmux_config_pingrp_table(tegra3_p880_pinmux,
+ ARRAY_SIZE(tegra3_p880_pinmux));
+#endif
+
+#ifdef CONFIG_DEVICE_P895
+ pinmux_config_pingrp_table(tegra3_p895_pinmux,
+ ARRAY_SIZE(tegra3_p895_pinmux));
+#endif
+}
+
+#ifdef CONFIG_MMC_SDHCI_TEGRA
+static void max77663_voltage_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDR, 1, &dev);
+ if (ret) {
+ log_debug("cannot find PMIC I2C chip\n");
+ return;
+ }
+
+ /* 0x60 for 1.8v, bit7:0 = voltage */
+ ret = dm_i2c_reg_write(dev, MAX77663_REG_SD2, 0x60);
+ if (ret)
+ log_debug("vdd_1v8_vio set failed: %d\n", ret);
+
+ /* 0xF2 for 3.30v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+ ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO2, 0xF2);
+ if (ret)
+ log_debug("avdd_usb set failed: %d\n", ret);
+
+ /* 0xEC for 3.00v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+ ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO3, 0xEC);
+ if (ret)
+ log_debug("vdd_usd set failed: %d\n", ret);
+
+ /* 0xE9 for 2.85v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+ ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO5, 0xE9);
+ if (ret)
+ log_debug("vcore_emmc set failed: %d\n", ret);
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the MMC muxes, power rails, etc.
+ */
+void pin_mux_mmc(void)
+{
+ /* Bring up uSD and eMMC power */
+ max77663_voltage_init();
+}
+#endif /* MMC */
+
+int nvidia_board_init(void)
+{
+ /* Set up panel bridge clocks */
+ clock_start_periph_pll(PERIPH_ID_EXTPERIPH3, CLOCK_ID_PERIPH,
+ 24 * 1000000);
+ clock_external_output(3);
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /* First 3 bytes refer to LG vendor */
+ u8 btmacaddr[6] = { 0x00, 0x00, 0x00, 0xD0, 0xC9, 0x88 };
+
+ /* Generate device 3 bytes based on chip sd */
+ u64 bt_device = tegra_chip_uid() >> 24ull;
+
+ btmacaddr[0] = (bt_device >> 1 & 0x0F) |
+ (bt_device >> 5 & 0xF0);
+ btmacaddr[1] = (bt_device >> 11 & 0x0F) |
+ (bt_device >> 17 & 0xF0);
+ btmacaddr[2] = (bt_device >> 23 & 0x0F) |
+ (bt_device >> 29 & 0xF0);
+
+ /* Set BT MAC address */
+ fdt_find_and_setprop(blob, "/serial@70006200/bluetooth",
+ "local-bd-address", btmacaddr, 6, 1);
+
+ /* Remove TrustZone nodes */
+ fdt_del_node_and_alias(blob, "/firmware");
+ fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000");
+
+ return 0;
+}
+#endif
+
+void nvidia_board_late_init(void)
+{
+ char serialno_str[17];
+
+ /* Set chip id as serialno */
+ sprintf(serialno_str, "%016llx", tegra_chip_uid());
+ env_set("serial#", serialno_str);
+ env_set("platform", "Tegra 3 T30");
+}
diff --git a/board/liebherr/display5/spl.c b/board/liebherr/display5/spl.c
index 4219d00..97928e9 100644
--- a/board/liebherr/display5/spl.c
+++ b/board/liebherr/display5/spl.c
@@ -25,6 +25,7 @@
#include "asm/arch/iomux.h"
#include <asm/mach-imx/iomux-v3.h>
#include <asm/gpio.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <netdev.h>
#include <bootcount.h>
diff --git a/board/mediatek/mt7622/mt7622_rfb.c b/board/mediatek/mt7622/mt7622_rfb.c
index ff233e9..2cc73bc 100644
--- a/board/mediatek/mt7622/mt7622_rfb.c
+++ b/board/mediatek/mt7622/mt7622_rfb.c
@@ -14,7 +14,6 @@
int board_init(void)
{
- gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/board/mediatek/mt7988/MAINTAINERS b/board/mediatek/mt7988/MAINTAINERS
new file mode 100644
index 0000000..a45bfff
--- /dev/null
+++ b/board/mediatek/mt7988/MAINTAINERS
@@ -0,0 +1,7 @@
+MT7988
+M: Sam Shih <sam.shih@mediatek.com>
+S: Maintained
+F: board/mediatek/mt7988
+F: include/configs/mt7988.h
+F: configs/mt7988_rfb_defconfig
+F: configs/mt7988_sd_rfb_defconfig
diff --git a/board/mediatek/mt7988/Makefile b/board/mediatek/mt7988/Makefile
new file mode 100644
index 0000000..f1249ab
--- /dev/null
+++ b/board/mediatek/mt7988/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += mt7988_rfb.o
diff --git a/board/mediatek/mt7988/mt7988_rfb.c b/board/mediatek/mt7988/mt7988_rfb.c
new file mode 100644
index 0000000..846c715
--- /dev/null
+++ b/board/mediatek/mt7988/mt7988_rfb.c
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+int board_init(void)
+{
+ return 0;
+}
diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c
index ca3b81c..b8dffb0 100644
--- a/board/menlo/m53menlo/m53menlo.c
+++ b/board/menlo/m53menlo/m53menlo.c
@@ -42,7 +42,7 @@
static u32 mx53_dram_size[2];
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
/*
* WARNING: We must override get_effective_memsize() function here
diff --git a/board/mntre/imx8mq_reform2/spl.c b/board/mntre/imx8mq_reform2/spl.c
index 21fad49..5120c62 100644
--- a/board/mntre/imx8mq_reform2/spl.c
+++ b/board/mntre/imx8mq_reform2/spl.c
@@ -21,6 +21,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <linux/delay.h>
diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c
index 5e5b129..b37c6fe 100644
--- a/board/phytec/pcm058/pcm058.c
+++ b/board/phytec/pcm058/pcm058.c
@@ -17,6 +17,7 @@
#include <asm/global_data.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/sys_proto.h>
+#include <asm/sections.h>
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c
index 1bae9b1..690a51f 100644
--- a/board/phytec/phycore_imx8mm/spl.c
+++ b/board/phytec/phycore_imx8mm/spl.c
@@ -12,6 +12,7 @@
#include <asm/global_data.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
+#include <asm/sections.h>
#include <hang.h>
#include <init.h>
#include <log.h>
diff --git a/board/radxa/rock5a-rk3588s/MAINTAINERS b/board/radxa/rock5a-rk3588s/MAINTAINERS
index 62fb6b4..a569efa 100644
--- a/board/radxa/rock5a-rk3588s/MAINTAINERS
+++ b/board/radxa/rock5a-rk3588s/MAINTAINERS
@@ -1,6 +1,9 @@
ROCK5A-RK3588
M: Eugen Hristev <eugen.hristev@collabora.com>
+R: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: board/radxa/rock5a-rk3588s
F: include/configs/rock5a-rk3588s.h
F: configs/rock5a-rk3588s_defconfig
+F: arch/arm/dts/rk3588s-rock-5a.dts
+F: arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
diff --git a/board/radxa/rock5b-rk3588/MAINTAINERS b/board/radxa/rock5b-rk3588/MAINTAINERS
index 693751e..4460c99 100644
--- a/board/radxa/rock5b-rk3588/MAINTAINERS
+++ b/board/radxa/rock5b-rk3588/MAINTAINERS
@@ -1,6 +1,9 @@
ROCK5B-RK3588
M: Eugen Hristev <eugen.hristev@collabora.com>
+R: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: board/radxa/rock5b-rk3588
-F: include/configs/rock5b-rk3588
+F: include/configs/rock5b-rk3588.h
F: configs/rock5b-rk3588_defconfig
+F: arch/arm/dts/rk3588-rock-5b.dts
+F: arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 1057ebb..cd823ad 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -334,7 +334,7 @@
/*
* Prevent relocation from stomping on a firmware provided FDT blob.
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
if ((gd->ram_top - fw_dtb_pointer) > SZ_64M)
return gd->ram_top;
@@ -561,6 +561,8 @@
node = fdt_node_offset_by_compatible(blob, -1, "simple-framebuffer");
if (node < 0)
fdt_simplefb_add_node(blob);
+ else
+ fdt_simplefb_enable_and_mem_rsv(blob);
#ifdef CONFIG_EFI_LOADER
/* Reserve the spin table */
diff --git a/board/renesas/alt/MAINTAINERS b/board/renesas/alt/MAINTAINERS
index 6ec140b..ee84678 100644
--- a/board/renesas/alt/MAINTAINERS
+++ b/board/renesas/alt/MAINTAINERS
@@ -1,6 +1,8 @@
ALT BOARD
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
M: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
S: Maintained
+F: arch/arm/dts/r8a7794-alt*
F: board/renesas/alt/
-F: include/configs/alt.h
F: configs/alt_defconfig
+F: include/configs/alt.h
diff --git a/board/renesas/blanche/MAINTAINERS b/board/renesas/blanche/MAINTAINERS
index 4b3114a..39fb93e 100644
--- a/board/renesas/blanche/MAINTAINERS
+++ b/board/renesas/blanche/MAINTAINERS
@@ -1,7 +1,8 @@
BLANCHE BOARD
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
M: Masakazu Mochizuki <masakazu.mochizuki.wd@hitachi.com>
S: Maintained
+F: arch/arm/dts/r8a7792*
F: board/renesas/blanche/
-F: include/configs/blanche.h
F: configs/blanche_defconfig
-
+F: include/configs/blanche.h
diff --git a/board/renesas/condor/MAINTAINERS b/board/renesas/condor/MAINTAINERS
index 73b010b..6bc9876 100644
--- a/board/renesas/condor/MAINTAINERS
+++ b/board/renesas/condor/MAINTAINERS
@@ -1,6 +1,7 @@
CONDOR BOARD
-M: Marek Vasut <marek.vasut+renesas@gmail.com>
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
S: Maintained
+F: arch/arm/dts/r8a77980-condor*
F: board/renesas/condor/
-F: include/configs/condor.h
F: configs/r8a77980_condor_defconfig
+F: include/configs/condor.h
diff --git a/board/renesas/draak/MAINTAINERS b/board/renesas/draak/MAINTAINERS
index 1dbcc28..6464784 100644
--- a/board/renesas/draak/MAINTAINERS
+++ b/board/renesas/draak/MAINTAINERS
@@ -1,6 +1,7 @@
DRAAK BOARD
-M: Marek Vasut <marek.vasut+renesas@gmail.com>
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
S: Maintained
+F: arch/arm/dts/r8a77995*
F: board/renesas/draak/
-F: include/configs/draak.h
F: configs/r8a77995_draak_defconfig
+F: include/configs/draak.h
diff --git a/board/renesas/eagle/MAINTAINERS b/board/renesas/eagle/MAINTAINERS
index f387c13..c28b650 100644
--- a/board/renesas/eagle/MAINTAINERS
+++ b/board/renesas/eagle/MAINTAINERS
@@ -1,6 +1,7 @@
EAGLE BOARD
-M: Marek Vasut <marek.vasut+renesas@gmail.com>
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
S: Maintained
+F: arch/arm/dts/r8a77970-eagle*
F: board/renesas/eagle/
-F: include/configs/eagle.h
F: configs/r8a77970_eagle_defconfig
+F: include/configs/eagle.h
diff --git a/board/renesas/ebisu/MAINTAINERS b/board/renesas/ebisu/MAINTAINERS
index facad52..c41aa1e 100644
--- a/board/renesas/ebisu/MAINTAINERS
+++ b/board/renesas/ebisu/MAINTAINERS
@@ -1,6 +1,7 @@
EBISU BOARD
-M: Marek Vasut <marek.vasut+renesas@gmail.com>
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
S: Maintained
+F: arch/arm/dts/r8a77990*
F: board/renesas/ebisu/
-F: include/configs/ebisu.h
F: configs/r8a77990_ebisu_defconfig
+F: include/configs/ebisu.h
diff --git a/board/renesas/falcon/MAINTAINERS b/board/renesas/falcon/MAINTAINERS
index 2cacc91..861f068 100644
--- a/board/renesas/falcon/MAINTAINERS
+++ b/board/renesas/falcon/MAINTAINERS
@@ -1,6 +1,7 @@
FALCON BOARD
-M: Marek Vasut <marek.vasut+renesas@gmail.com>
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
S: Maintained
+F: arch/arm/dts/r8a779a0*
F: board/renesas/falcon/
-F: include/configs/falcon.h
F: configs/r8a779a0_falcon_defconfig
+F: include/configs/falcon.h
diff --git a/board/renesas/gose/MAINTAINERS b/board/renesas/gose/MAINTAINERS
index cad5be9..c6b9902 100644
--- a/board/renesas/gose/MAINTAINERS
+++ b/board/renesas/gose/MAINTAINERS
@@ -1,6 +1,8 @@
-ALT BOARD
+GOSE BOARD
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
M: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
S: Maintained
+F: arch/arm/dts/r8a7793*
F: board/renesas/gose/
-F: include/configs/gose.h
F: configs/gose_defconfig
+F: include/configs/gose.h
diff --git a/board/renesas/grpeach/MAINTAINERS b/board/renesas/grpeach/MAINTAINERS
index 4ab7773..c0f4fbc 100644
--- a/board/renesas/grpeach/MAINTAINERS
+++ b/board/renesas/grpeach/MAINTAINERS
@@ -1,6 +1,16 @@
GRPEACH BOARD
-M: Marek Vasut <marek.vasut@gmail.com>
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
S: Maintained
+F: arch/arm/dts/r7s72100*
F: board/renesas/grpeach/
-F: include/configs/grpeach.h
F: configs/grpeach_defconfig
+F: drivers/gpio/gpio-rza1.c
+F: drivers/mtd/renesas_rpc_hf.c
+F: drivers/net/sh_eth*
+F: drivers/pinctrl/renesas/pfc-r7s72100.c
+F: drivers/serial/serial_sh*
+F: drivers/spi/renesas_rpc_spi.c
+F: drivers/timer/ostm_timer.c
+F: drivers/usb/host/r8a66597-hcd.c
+F: drivers/usb/host/r8a66597.h
+F: include/configs/grpeach.h
diff --git a/board/renesas/koelsch/MAINTAINERS b/board/renesas/koelsch/MAINTAINERS
index 5267b9f..788f01a 100644
--- a/board/renesas/koelsch/MAINTAINERS
+++ b/board/renesas/koelsch/MAINTAINERS
@@ -1,6 +1,8 @@
KOELSCH BOARD
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
M: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
S: Maintained
+F: arch/arm/dts/r8a7791-koelsch*
F: board/renesas/koelsch/
-F: include/configs/koelsch.h
F: configs/koelsch_defconfig
+F: include/configs/koelsch.h
diff --git a/board/renesas/lager/MAINTAINERS b/board/renesas/lager/MAINTAINERS
index a098686..48b690d 100644
--- a/board/renesas/lager/MAINTAINERS
+++ b/board/renesas/lager/MAINTAINERS
@@ -1,6 +1,8 @@
LAGER BOARD
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
M: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
S: Maintained
+F: arch/arm/dts/r8a7790-lager*
F: board/renesas/lager/
-F: include/configs/lager.h
F: configs/lager_defconfig
+F: include/configs/lager.h
diff --git a/board/renesas/porter/MAINTAINERS b/board/renesas/porter/MAINTAINERS
index 1dc6a1c..4671b5b 100644
--- a/board/renesas/porter/MAINTAINERS
+++ b/board/renesas/porter/MAINTAINERS
@@ -1,6 +1,8 @@
PORTER BOARD
M: Cogent Embedded, Inc. <source@cogentembedded.com>
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
S: Maintained
+F: arch/arm/dts/r8a7791-porter*
F: board/renesas/porter/
-F: include/configs/porter.h
F: configs/porter_defconfig
+F: include/configs/porter.h
diff --git a/board/renesas/r2dplus/MAINTAINERS b/board/renesas/r2dplus/MAINTAINERS
index 58877c5..a5cc2f0 100644
--- a/board/renesas/r2dplus/MAINTAINERS
+++ b/board/renesas/r2dplus/MAINTAINERS
@@ -1,7 +1,11 @@
R2DPLUS BOARD
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
S: Maintained
+F: arch/sh/dts/sh7751-r2dplus*
F: board/renesas/r2dplus/
-F: include/configs/r2dplus.h
F: configs/r2dplus_defconfig
+F: drivers/pci/pci_sh7751.c
+F: drivers/serial/serial_sh*
+F: include/configs/r2dplus.h
diff --git a/board/renesas/salvator-x/MAINTAINERS b/board/renesas/salvator-x/MAINTAINERS
index 7335bc3..a85e9d9 100644
--- a/board/renesas/salvator-x/MAINTAINERS
+++ b/board/renesas/salvator-x/MAINTAINERS
@@ -1,6 +1,8 @@
SALVATOR_X BOARD
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
S: Maintained
+F: arch/arm/dts/*salvator-x*
F: board/renesas/salvator-x/
-F: include/configs/salvator-x.h
F: configs/rcar3_salvator-x_defconfig
+F: include/configs/salvator-x.h
diff --git a/board/renesas/silk/MAINTAINERS b/board/renesas/silk/MAINTAINERS
index b566ccf..40fa271 100644
--- a/board/renesas/silk/MAINTAINERS
+++ b/board/renesas/silk/MAINTAINERS
@@ -1,6 +1,8 @@
SILK BOARD
M: Cogent Embedded, Inc. <source@cogentembedded.com>
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
S: Maintained
+F: arch/arm/dts/r8a7794-silk*
F: board/renesas/silk/
-F: include/configs/silk.h
F: configs/silk_defconfig
+F: include/configs/silk.h
diff --git a/board/renesas/spider/MAINTAINERS b/board/renesas/spider/MAINTAINERS
new file mode 100644
index 0000000..731ca35
--- /dev/null
+++ b/board/renesas/spider/MAINTAINERS
@@ -0,0 +1,7 @@
+SPIDER BOARD
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
+S: Maintained
+F: arch/arm/dts/r8a779f0*
+F: board/renesas/spider/
+F: configs/r8a779f0_spider_defconfig
+F: include/configs/spider.h
diff --git a/board/renesas/stout/MAINTAINERS b/board/renesas/stout/MAINTAINERS
index b7098e7..a6042d8 100644
--- a/board/renesas/stout/MAINTAINERS
+++ b/board/renesas/stout/MAINTAINERS
@@ -1,6 +1,8 @@
STOUT BOARD
M: Cogent Embedded, Inc. <source@cogentembedded.com>
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
S: Maintained
+F: arch/arm/dts/r8a7790-stout*
F: board/renesas/stout/
-F: include/configs/stout.h
F: configs/stout_defconfig
+F: include/configs/stout.h
diff --git a/board/renesas/ulcb/MAINTAINERS b/board/renesas/ulcb/MAINTAINERS
index 564eb56..18b9b42 100644
--- a/board/renesas/ulcb/MAINTAINERS
+++ b/board/renesas/ulcb/MAINTAINERS
@@ -1,6 +1,7 @@
ULCB BOARD
-M: Marek Vasut <marek.vasut+renesas@gmail.com>
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
S: Maintained
+F: arch/arm/dts/*ulcb*
F: board/renesas/ulcb/
-F: include/configs/ulcb.h
F: configs/rcar3_ulcb_defconfig
+F: include/configs/ulcb.h
diff --git a/board/renesas/v3hsk/MAINTAINERS b/board/renesas/v3hsk/MAINTAINERS
new file mode 100644
index 0000000..8a5af85
--- /dev/null
+++ b/board/renesas/v3hsk/MAINTAINERS
@@ -0,0 +1,7 @@
+V3HSK BOARD
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
+S: Maintained
+F: arch/arm/dts/r8a77980-v3hsk*
+F: board/renesas/v3hsk/
+F: configs/r8a77980_v3hsk_defconfig
+F: include/configs/v3hsk.h
diff --git a/board/renesas/v3msk/MAINTAINERS b/board/renesas/v3msk/MAINTAINERS
index 12822a4..c198cf8 100644
--- a/board/renesas/v3msk/MAINTAINERS
+++ b/board/renesas/v3msk/MAINTAINERS
@@ -1,6 +1,8 @@
V3MSK BOARD
M: Cogent Embedded, Inc. <source@cogentembedded.com>
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
S: Maintained
+F: arch/arm/dts/r8a77970-v3msk*
F: board/renesas/v3msk/
-F: include/configs/v3msk.h
F: configs/r8a77970_v3msk_defconfig
+F: include/configs/v3msk.h
diff --git a/board/renesas/whitehawk/MAINTAINERS b/board/renesas/whitehawk/MAINTAINERS
new file mode 100644
index 0000000..f893abff
--- /dev/null
+++ b/board/renesas/whitehawk/MAINTAINERS
@@ -0,0 +1,7 @@
+WHITEHAWK BOARD
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
+S: Maintained
+F: arch/arm/dts/r8a779g0*
+F: board/renesas/whitehawk/
+F: configs/r8a779g0_whitehawk_defconfig
+F: include/configs/whitehawk.h
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS
index cb44bc9..c7e412b 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -80,7 +80,7 @@
F: arch/arm/dts/rk3399-u-boot.dtsi
F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi
-RADXA ROCK 4C+
+ROCK-4C+
M: FUKAUMI Naoki <naoki@radxa.com>
S: Maintained
F: configs/rock-4c-plus-rk3399_defconfig
diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS
index 82a92b8..cc9eb43 100644
--- a/board/rockchip/evb_rk3568/MAINTAINERS
+++ b/board/rockchip/evb_rk3568/MAINTAINERS
@@ -1,31 +1,44 @@
EVB-RK3568
-M: Joseph Chen <chenjh@rock-chips.com>
-S: Maintained
-F: board/rockchip/evb_rk3568
-F: include/configs/evb_rk3568.h
-F: configs/evb-rk3568_defconfig
-F: arch/arm/dts/rk3568-evb-boot.dtsi
+M: Joseph Chen <chenjh@rock-chips.com>
+S: Maintained
+F: board/rockchip/evb_rk3568
+F: include/configs/evb_rk3568.h
+F: configs/evb-rk3568_defconfig
+F: arch/arm/dts/rk3568-evb-u-boot.dtsi
F: arch/arm/dts/rk3568-evb.dts
+LUBANCAT-2
+M: Andy Yan <andyshrk@163.com>
+S: Maintained
+F: configs/lubancat-2-rk3568_defconfig
+F: arch/arm/dts/rk3568-lubancat-2.dts
+F: arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
+
NANOPI-R5C
-M: Tianling Shen <cnsztl@gmail.com>
-S: Maintained
-F: configs/nanopi-r5c-rk3568_defconfig
-F: arch/arm/dts/rk3568-nanopi-r5c.dts
-F: arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
+M: Tianling Shen <cnsztl@gmail.com>
+R: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: configs/nanopi-r5c-rk3568_defconfig
+F: arch/arm/dts/rk3568-nanopi-r5c.dts
+F: arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
NANOPI-R5S
-M: Tianling Shen <cnsztl@gmail.com>
-S: Maintained
-F: configs/nanopi-r5s-rk3568_defconfig
-F: arch/arm/dts/rk3568-nanopi-r5s.dts
-F: arch/arm/dts/rk3568-nanopi-r5s.dtsi
-F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
+M: Tianling Shen <cnsztl@gmail.com>
+R: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: configs/nanopi-r5s-rk3568_defconfig
+F: arch/arm/dts/rk3568-nanopi-r5s.dts
+F: arch/arm/dts/rk3568-nanopi-r5s.dtsi
+F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
-RADXA-CM3
+RADXA-CM3-IO
M: Jagan Teki <jagan@amarulasolutions.com>
+R: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: configs/radxa-cm3-io-rk3566_defconfig
+F: arch/arm/dts/rk3566-radxa-cm3.dtsi
+F: arch/arm/dts/rk3566-radxa-cm3-io.dts
+F: arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
RADXA-E25
M: Jonas Karlman <jonas@kwiboo.se>
@@ -36,8 +49,9 @@
F: arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
ROCK-3A
-M: Akash Gajjar <gajjar04akash@gmail.com>
-S: Maintained
-F: configs/rock-3a-rk3568_defconfig
-F: arch/arm/dts/rk3568-rock-3a.dts
-F: arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+M: Akash Gajjar <gajjar04akash@gmail.com>
+R: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: configs/rock-3a-rk3568_defconfig
+F: arch/arm/dts/rk3568-rock-3a.dts
+F: arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS
index 7b7df3c..6b2c257 100644
--- a/board/rockchip/evb_rk3588/MAINTAINERS
+++ b/board/rockchip/evb_rk3588/MAINTAINERS
@@ -4,4 +4,5 @@
F: board/rockchip/evb_rk3588
F: include/configs/evb_rk3588.h
F: configs/evb-rk3588_defconfig
-F: arch/arm/dts/rk3588-evb-u-boot.dtsi
+F: arch/arm/dts/rk3588-evb1-v10.dts
+F: arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi
diff --git a/board/ronetix/imx7-cm/spl.c b/board/ronetix/imx7-cm/spl.c
index d36f734..b94cfd6 100644
--- a/board/ronetix/imx7-cm/spl.c
+++ b/board/ronetix/imx7-cm/spl.c
@@ -16,6 +16,7 @@
#include <asm/arch-mx7/mx7-ddr.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/gpio.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <spl.h>
diff --git a/board/ronetix/imx8mq-cm/spl.c b/board/ronetix/imx8mq-cm/spl.c
index b9a6745..1c675bc 100644
--- a/board/ronetix/imx8mq-cm/spl.c
+++ b/board/ronetix/imx8mq-cm/spl.c
@@ -13,6 +13,7 @@
#include <asm/arch/clock.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <linux/delay.h>
#include <spl.h>
diff --git a/board/sandbox/capsule_priv_key_bad.key b/board/sandbox/capsule_priv_key_bad.key
new file mode 100644
index 0000000..2324f69
--- /dev/null
+++ b/board/sandbox/capsule_priv_key_bad.key
@@ -0,0 +1,28 @@
+-----BEGIN PRIVATE KEY-----
+MIIEvQIBADANBgkqhkiG9w0BAQEFAASCBKcwggSjAgEAAoIBAQCmPw1pGd2xNW0p
+lesRXkkek3uwUB06Nt61tnZvpMkBKt4IokqGWz1tZls+Z2CqvwOfcsPZ27cPRYSu
+xRnM3YdL4MG6SePV7i/YSNw3rq8CP8zLGtCbNIfsfsNfPQEtPBpw6+7pMJKhjqpV
+2U2UQzZEiX4qlnhLpyv2JNJag27yf0feLdJi7HnJ9xdvcXpA1DSGm4y+DDhgYeI8
+DEteEu6s0TYQfnOZSQOeJi+1/Qz0S594uFJB37MyGh/mB15ILb8gva4nA3ayHOBK
+0dd+HSiUCGYrLYO7aj+nfzQj9N1qTlzCnC1603bMczU5pkwcODg6xP0Sn11J6RYy
+y0c0qzJLAgMBAAECggEABDY2MLoew3IkBltrParAWAUUcFLi95jw92q6BkOHEJg8
+2qia1yCitPUtPodMLmOKF5x4EdgXg5sv2O8MGbWP1VtUKXGh3QJcnRnNmsZ1hXJC
+RBcrei2aVLsqf0V2Mg3+GuG8PW3vLWHyZ/Sd6afeuXEYm2Bzrw9J5rfd3dBVKm7f
+HBvIyy1ATO/2cbUaEaCLOyhxLhssTI2TIK5SjlsjFLxiQXEi6RyGfBxUCriKZykS
+krMdvYh7Tf0uYcv0STmQ5s5Rd+RhRIGCVAdsNBxxJjgBAgqqa/B+kWbcc6o2D41n
+yWjErUaBBx3t0A7oT4K4DSTYwMNDVY3fhdd+szsocQKBgQDjnm8LG4UO6OQDm6iX
+0vTQTItoAz5TU6GEjHTCfVEqiupD4LKfHhSXwp2hRyzxXO5oNTU9MQCzYd7Npes0
+oVk4Tjo3YDacNPgxqKjODu/Q+tkTH15ydzGr674+YXHfCA1uT5GKOiiF0H1FZgMa
+Dk0s+3uWX34vbL4QCu97bUhBewKBgQC6+Z0J9sClgWvvjkglJN3XhRnAacp+WgX7
+bkpgSboXIIsqeqhd1WCLeV7L1pcZgifYBMPojf5LTBqBedL1q3RuqiqQWD/bSIYN
+Oc9KCdTjksS8Zo+w+s5zDObDhW9y13H2mKwDqilYBrT4fiA62wPMf1SjEF+RSC6K
+ZrQzHO1xcQKBgAILsXnLFIYOx8XUh05eAf9BQNt9c/jxvnjffkklMS6Nsw9LHK/b
+aFn40MvbROcia64aFFFpeFUkYwk8HYIKlS+xXEqVHciHnVds6Z94eOVK69qFJKco
+tRSTeNE8tPZJLz23j1pLrYOOXSHbidmZGU53MCQo1Yx9kLO6NW7Ji6WzAoGBALP4
+lEoE80Xbn3NEdvkZ1VcfzLvCmKCqMlvjuz+Xd8HPF2VaDznSq01VFAQMmAB7obJy
+U8hC9OSxakn6Yy8JS9dBgBrUdxKxaibM4FQZxosOuMPHzMPDhniDkJPemnnmGtIL
+/nbAkW8jdYpCjO9Z5PwwC92xYuvKmNGrLgSM8ZhhAoGAfgSZTpASXubM18E3ecfw
+5z333wf9qEQgZj7i9MzByFZudyHUhv/FPW1ocUJf36Wu1dfofZg3noSL6oakrm2v
+dFDo4PoyCStuF0w9SSzpIld01ZG0t7XqphY0DmshCXIXsqr7Vb4WrbBI7KX+b3Um
+BzmROfaSud97NjQ/RA26OZk=
+-----END PRIVATE KEY-----
diff --git a/board/sandbox/capsule_priv_key_good.key b/board/sandbox/capsule_priv_key_good.key
new file mode 100644
index 0000000..9a37f59
--- /dev/null
+++ b/board/sandbox/capsule_priv_key_good.key
@@ -0,0 +1,28 @@
+-----BEGIN PRIVATE KEY-----
+MIIEvQIBADANBgkqhkiG9w0BAQEFAASCBKcwggSjAgEAAoIBAQCwBfaV0P1jRzS6
+13U1T+4VbuMVsxFXhwHJY5z5Fx6v+cWBf3K1ruK+7cEnW55ZHXvNE2JCkjMvISKm
+hI/DLJWIPnAus8tFdU/R2u5oJbKI+b6GbuamO/CG9HsXZ58lOC6r2ckjixxovsA9
+SFshccdIv2YrwiVsWeyFpH+rB3/+cFbrgdWpaUc1367GkU/ZCnSRDBvVvzRRI1a4
+y2NogFqbZHXHENpzWNJ3TTXhf9dwM5HFGkmX7SA43Dtazae6CB4EaUKzLYWj3+ae
+AQbdvBrupKZQz1PUKn7X6+BGaLujHthvibYppNegPvqbJ1xBbv59CQK+lRULwC05
+NYw5+sIxAgMBAAECggEAHn8h/knjpMAw/BAZP//VrYP1Nwy7u/Dpl9U43JUrXWzG
+Uc3dd2nR4id6GBIRCLqJePnbQ9JlqMwyXyxHZhbC34SF1imTVbjh9+dY99VULdQr
+NMphDrsCzLbt3pu24HFv8Jk+dniDFwi5cMSo+U3nq4xxrLIp3rBjwLHD5sNZYyEU
+9xZnj7ziTn5X8da8iRxNpyzz2kQeVemJ0ahr/IkX718bkakSFMesGkln06vH7rAs
+069SeqOPrFEbWYXI5iMktLugl3JZpzasRE48j0M42PuProgvT7jb8B35ZF7kn0jT
+MqTIHglsJRWcSY0fAb2lHSAvd2vLLVunxr9PDWZvGQKBgQDVzVTuvo1CrVrQLy+B
+tpy2k5mjR3qxAOcoWTnKcMErLe8imWWaxukODenP4XqQIX4Sl+X3BXxOqun0Klap
+FEsI7TWSHf0eULFtFj0SCgqfRR+V/nblP05eO2nFXgr5YdNa1bWf/aMHplBo4q9e
+bbAr4InUB7IGWL2cWjhOhWuJbQKBgQDSw81cBM+vGPUYH/wlxlTVgZCo2Dg2NHjt
+LUBqvOZNr21j2F+w8t1vKmqwhkqpc5HIi3pHjEA5gZLTRtmf4GQyo973I6MGn4bS
+eayOd6/+FkAi9DUD+WaF7yctJqeevav6KF2UCiz78OtCAU5Y9jFFJpuOANIztI7m
+t7ZCUpMFVQKBgFnAsP7oj3SGQbFTnaXeeztKCx04TJExx9hwXIpXe0AdMF5d9wFa
+r0tvG9Bg34rSBJLZoXhpnR2JMl2FyIuCMV219t84J6IqTdF1nH2OKZdi9TeKc28Z
+fFSirGxmZkT6hDeFr5FScLYtY2QkhWomseY5hKK1+E4hwrd4SFruN46hAoGBAJgh
+nzTBgEtqH1enlrCJhSiLmihV0dVGcNb559pjuXTvoG0GfKPT2gPowRPkCzZe5ia0
+jrHgSWd44MtCA8nEBW8MG9+VyJH6Si3Yh7ZaLB2iX+8bCL1yow8f/c44bZtGW0F5
+K3q1EZ1VW+rL2IqcQhog8P1CGHgb514f0x3yTo71AoGACGdb+Nb6lg8OSJPUcuuH
+xsWk6RhkJl9bldTleS+QT3R9zO3FvbTwnCCYJboh5Cq/jVmiA7T+fcVAyEJNHSdm
+hxbHdScuiJdNWL9+FczOkylnKH3VEdG3RS5lGdyi6r+miTMs3h8WfzGp4JINysjg
+PUFskK36qGjASfkRUn0hizQ=
+-----END PRIVATE KEY-----
diff --git a/board/sandbox/capsule_pub_esl_good.esl b/board/sandbox/capsule_pub_esl_good.esl
new file mode 100644
index 0000000..f8cc272
--- /dev/null
+++ b/board/sandbox/capsule_pub_esl_good.esl
Binary files differ
diff --git a/board/sandbox/capsule_pub_key_bad.crt b/board/sandbox/capsule_pub_key_bad.crt
new file mode 100644
index 0000000..2e8e5d5
--- /dev/null
+++ b/board/sandbox/capsule_pub_key_bad.crt
@@ -0,0 +1,19 @@
+-----BEGIN CERTIFICATE-----
+MIIDDzCCAfegAwIBAgIUWw3vHYnrjoHUXytxSm2eYWzbYVAwDQYJKoZIhvcNAQEL
+BQAwFjEUMBIGA1UEAwwLVEVTVF9TSUdORVIwIBcNMjMwODA0MTgwODEyWhgPMzAw
+MzEwMDYxODA4MTJaMBYxFDASBgNVBAMMC1RFU1RfU0lHTkVSMIIBIjANBgkqhkiG
+9w0BAQEFAAOCAQ8AMIIBCgKCAQEApj8NaRndsTVtKZXrEV5JHpN7sFAdOjbetbZ2
+b6TJASreCKJKhls9bWZbPmdgqr8Dn3LD2du3D0WErsUZzN2HS+DBuknj1e4v2Ejc
+N66vAj/MyxrQmzSH7H7DXz0BLTwacOvu6TCSoY6qVdlNlEM2RIl+KpZ4S6cr9iTS
+WoNu8n9H3i3SYux5yfcXb3F6QNQ0hpuMvgw4YGHiPAxLXhLurNE2EH5zmUkDniYv
+tf0M9EufeLhSQd+zMhof5gdeSC2/IL2uJwN2shzgStHXfh0olAhmKy2Du2o/p380
+I/Tdak5cwpwtetN2zHM1OaZMHDg4OsT9Ep9dSekWMstHNKsySwIDAQABo1MwUTAd
+BgNVHQ4EFgQUm9b8SnF811nweXSfGisfpzUHGwgwHwYDVR0jBBgwFoAUm9b8SnF8
+11nweXSfGisfpzUHGwgwDwYDVR0TAQH/BAUwAwEB/zANBgkqhkiG9w0BAQsFAAOC
+AQEAaOZFOcQzF1MRekcBmIZMaHSWYxOUrVLzBNSNhFD8muYiUAAufrkyTUq0Mmat
+w5hAnJ34VGpU1wxQlr/uwH7wpZZnGuj10rAp3tqES0g24AeH1bC9wmRs+rD6dcZR
+YmZq6FxtV7Cv3pQX7lhDYbcBj2za3YT6I1+yczskAHR6KYYuJzKJ7XRVCL7ZlYRX
+pUMZBQq2eAVWlW/c5iDT3KoGZUD9Of71F7qyUAqMMYafeDxguDz7gKstoXVCklQ+
+I4C7JKmRbrRvMgXx6O1clGhAsRZ0nNAtzi7XT5tD27qFwIPgwv48RWgsmPtzE03S
+YGQ5WhYMdHOOjWmcV6MDkCpiSA==
+-----END CERTIFICATE-----
diff --git a/board/sandbox/capsule_pub_key_good.crt b/board/sandbox/capsule_pub_key_good.crt
new file mode 100644
index 0000000..82d8576
--- /dev/null
+++ b/board/sandbox/capsule_pub_key_good.crt
@@ -0,0 +1,19 @@
+-----BEGIN CERTIFICATE-----
+MIIDDzCCAfegAwIBAgIUUzrWhMi7oPFshQP6eFlccqf7exswDQYJKoZIhvcNAQEL
+BQAwFjEUMBIGA1UEAwwLVEVTVF9TSUdORVIwIBcNMjMwODA0MTgwNzQyWhgPMzAw
+MzEwMDYxODA3NDJaMBYxFDASBgNVBAMMC1RFU1RfU0lHTkVSMIIBIjANBgkqhkiG
+9w0BAQEFAAOCAQ8AMIIBCgKCAQEAsAX2ldD9Y0c0utd1NU/uFW7jFbMRV4cByWOc
++Rcer/nFgX9yta7ivu3BJ1ueWR17zRNiQpIzLyEipoSPwyyViD5wLrPLRXVP0dru
+aCWyiPm+hm7mpjvwhvR7F2efJTguq9nJI4scaL7APUhbIXHHSL9mK8IlbFnshaR/
+qwd//nBW64HVqWlHNd+uxpFP2Qp0kQwb1b80USNWuMtjaIBam2R1xxDac1jSd001
+4X/XcDORxRpJl+0gONw7Ws2nuggeBGlCsy2Fo9/mngEG3bwa7qSmUM9T1Cp+1+vg
+Rmi7ox7Yb4m2KaTXoD76mydcQW7+fQkCvpUVC8AtOTWMOfrCMQIDAQABo1MwUTAd
+BgNVHQ4EFgQUHvG7Xchqzwdggky+oyzlpNem8UowHwYDVR0jBBgwFoAUHvG7Xchq
+zwdggky+oyzlpNem8UowDwYDVR0TAQH/BAUwAwEB/zANBgkqhkiG9w0BAQsFAAOC
+AQEAUn1ncSqeXbQAHNrVOFldLwu70hNlMxf2z4EfH2M7vJgrpwkRuIFw7PXNITBh
+CImd/ghm5NGFysrK7BwdHkFvUXZV3rE93BhcLC9leWfky33kW9olIzpE14i5FfBn
+ABmaokPhOrzAneGzU35sZHNotlqOrzgpKVkpOWrykhYZ5Qjk8Sz0xvzuG8TJc20s
+2og+W8Rm2u/xI9xPxtFbq9vUjvFS35o1pm+vkzpgNdo4YS1PG37BW/aopsooLSk7
+9Rxv5vzNXtQqeZ5qBdKbAVh3OsgqwigTmXVvOX3xpy9r9qiimhaISxCt83RZ7wQW
+I19t9pXyxAi6u7MRhJZlAeH/3w==
+-----END CERTIFICATE-----
diff --git a/board/schneider/rzn1-snarc/MAINTAINERS b/board/schneider/rzn1-snarc/MAINTAINERS
new file mode 100644
index 0000000..a39b96c
--- /dev/null
+++ b/board/schneider/rzn1-snarc/MAINTAINERS
@@ -0,0 +1,9 @@
+RZN1 SNARC
+M: Ralph Siemsen <ralph.siemsen@linaro.org>
+S: Maintained
+F: board/schneider/rzn1-snarc/
+F: arch/arm/dts/r9a06g032-ddr.dtsi
+F: arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi
+F: arch/arm/dts/r9a06g032-rzn1-snarc.dts
+F: configs/rzn1_snarc_defconfig
+F: include/configs/rzn1-snarc.h
diff --git a/board/siemens/capricorn/spl.c b/board/siemens/capricorn/spl.c
index 8e077d7..e160c61 100644
--- a/board/siemens/capricorn/spl.c
+++ b/board/siemens/capricorn/spl.c
@@ -10,6 +10,7 @@
#include <spl.h>
#include <dm.h>
#include <asm/global_data.h>
+#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
diff --git a/board/siemens/iot2050/iot2050.env b/board/siemens/iot2050/iot2050.env
index 7fd836e..caa9f80 100644
--- a/board/siemens/iot2050/iot2050.env
+++ b/board/siemens/iot2050/iot2050.env
@@ -6,7 +6,7 @@
* Jan Kiszka <jan.kiszka@siemens.com>
*/
-#include <environment/ti/ti_armv7_common.env>
+#include <env/ti/ti_armv7_common.env>
usb_pgood_delay=900
diff --git a/board/sifive/unleashed/unleashed.c b/board/sifive/unleashed/unleashed.c
index b6ab06a..3c5dd50 100644
--- a/board/sifive/unleashed/unleashed.c
+++ b/board/sifive/unleashed/unleashed.c
@@ -122,7 +122,7 @@
return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
}
- return (ulong *)&_end;
+ return (ulong *)_end;
}
int board_init(void)
diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c
index 6295dee..6675548 100644
--- a/board/sifive/unmatched/unmatched.c
+++ b/board/sifive/unmatched/unmatched.c
@@ -19,7 +19,7 @@
return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
}
- return (ulong *)&_end;
+ return (ulong *)_end;
}
int board_init(void)
diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c
index aaeeee3..4483bd7 100644
--- a/board/softing/vining_2000/vining_2000.c
+++ b/board/softing/vining_2000/vining_2000.c
@@ -19,6 +19,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/sections.h>
#include <env.h>
#include <linux/bitops.h>
#include <linux/delay.h>
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 6fa5cf4..e119330 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -32,6 +32,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/sata.h>
#include <asm/mach-imx/video.h>
+#include <asm/sections.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <malloc.h>
diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c
index d52dce4..969ad48 100644
--- a/board/st/common/stpmic1.c
+++ b/board/st/common/stpmic1.c
@@ -185,21 +185,17 @@
}
/* early init of PMIC */
-void stpmic1_init(u32 voltage_mv)
+struct udevice *stpmic1_init(u32 voltage_mv)
{
struct udevice *dev;
if (uclass_get_device_by_driver(UCLASS_PMIC,
DM_DRIVER_GET(pmic_stpmic1), &dev))
- return;
+ return NULL;
/* update VDDCORE = BUCK1 */
if (voltage_mv)
stmpic_buck1_set(dev, voltage_mv);
- /* Keep vdd on during the reset cycle */
- pmic_clrsetbits(dev,
- STPMIC1_BUCKS_MRST_CR,
- STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
- STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
+ return dev;
}
diff --git a/board/st/common/stpmic1.h b/board/st/common/stpmic1.h
index b17d6f1..7a7169d 100644
--- a/board/st/common/stpmic1.h
+++ b/board/st/common/stpmic1.h
@@ -3,4 +3,4 @@
* Copyright (C) 2020, STMicroelectronics - All Rights Reserved
*/
-void stpmic1_init(u32 voltage_mv);
+struct udevice *stpmic1_init(u32 voltage_mv);
diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c
index 747ec7e..8b4a529 100644
--- a/board/st/stm32mp1/spl.c
+++ b/board/st/stm32mp1/spl.c
@@ -5,6 +5,8 @@
#include <config.h>
#include <common.h>
+#include <power/pmic.h>
+#include <power/stpmic1.h>
#include <asm/arch/sys_proto.h>
#include "../common/stpmic1.h"
@@ -19,8 +21,15 @@
int board_early_init_f(void)
{
- if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER))
- stpmic1_init(opp_voltage_mv);
+ if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER)) {
+ struct udevice *dev = stpmic1_init(opp_voltage_mv);
+
+ /* Keep vdd on during the reset cycle */
+ pmic_clrsetbits(dev,
+ STPMIC1_BUCKS_MRST_CR,
+ STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
+ STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
+ }
return 0;
}
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c
index 07dcca2..d609262 100644
--- a/board/starfive/visionfive2/starfive_visionfive2.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -49,5 +49,5 @@
return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
}
- return (ulong *)&_end;
+ return (ulong *)_end;
}
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index f321cd5..de0f350 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -33,7 +33,6 @@
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <linux/delay.h>
-#include <u-boot/crc.h>
#ifndef CONFIG_ARM64
#include <asm/armv7.h>
#endif
diff --git a/board/technexion/pico-imx6ul/spl.c b/board/technexion/pico-imx6ul/spl.c
index 251f5a1..ff56fd8 100644
--- a/board/technexion/pico-imx6ul/spl.c
+++ b/board/technexion/pico-imx6ul/spl.c
@@ -14,6 +14,7 @@
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <linux/libfdt.h>
#include <spl.h>
diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c
index f86fee9..c6b21aa 100644
--- a/board/technexion/pico-imx7d/spl.c
+++ b/board/technexion/pico-imx7d/spl.c
@@ -16,6 +16,7 @@
#include <asm/arch-mx7/mx7-ddr.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/gpio.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <spl.h>
diff --git a/board/technexion/pico-imx8mq/spl.c b/board/technexion/pico-imx8mq/spl.c
index 2afb4d3..1a9c799 100644
--- a/board/technexion/pico-imx8mq/spl.c
+++ b/board/technexion/pico-imx8mq/spl.c
@@ -16,6 +16,7 @@
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/sections.h>
#include <linux/delay.h>
#include <errno.h>
#include <fsl_esdhc_imx.h>
diff --git a/board/ti/am62ax/am62ax.env b/board/ti/am62ax/am62ax.env
index 491ec97..3f7c333 100644
--- a/board/ti/am62ax/am62ax.env
+++ b/board/ti/am62ax/am62ax.env
@@ -1,5 +1,5 @@
-#include <environment/ti/ti_armv7_common.env>
-#include <environment/ti/mmc.env>
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/mmc.env>
default_device_tree=ti/k3-am62a7-sk.dtb
findfdt=
diff --git a/board/ti/am62x/am62x.env b/board/ti/am62x/am62x.env
index bb37d21..f2dc878 100644
--- a/board/ti/am62x/am62x.env
+++ b/board/ti/am62x/am62x.env
@@ -1,5 +1,5 @@
-#include <environment/ti/ti_armv7_common.env>
-#include <environment/ti/mmc.env>
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/mmc.env>
default_device_tree=ti/k3-am625-sk.dtb
findfdt=
diff --git a/board/ti/am64x/am64x.env b/board/ti/am64x/am64x.env
index ecb0736..1567907 100644
--- a/board/ti/am64x/am64x.env
+++ b/board/ti/am64x/am64x.env
@@ -1,6 +1,6 @@
-#include <environment/ti/ti_armv7_common.env>
-#include <environment/ti/mmc.env>
-#include <environment/ti/k3_dfu.env>
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/mmc.env>
+#include <env/ti/k3_dfu.env>
findfdt=
if test $board_name = am64x_gpevm; then
diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c
index 96f4e30..a080b2b 100644
--- a/board/ti/am64x/evm.c
+++ b/board/ti/am64x/evm.c
@@ -18,7 +18,8 @@
#include "../common/board_detect.h"
-#define board_is_am64x_gpevm() board_ti_k3_is("AM64-GPEVM")
+#define board_is_am64x_gpevm() (board_ti_k3_is("AM64-GPEVM") || \
+ board_ti_k3_is("AM64-HSEVM"))
#define board_is_am64x_skevm() (board_ti_k3_is("AM64-SKEVM") || \
board_ti_k3_is("AM64B-SKEVM"))
diff --git a/board/ti/am65x/am65x.env b/board/ti/am65x/am65x.env
index 036f475..755bff2 100644
--- a/board/ti/am65x/am65x.env
+++ b/board/ti/am65x/am65x.env
@@ -1,8 +1,8 @@
-#include <environment/ti/ti_armv7_common.env>
-#include <environment/ti/mmc.env>
-#include <environment/ti/k3_dfu.env>
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/mmc.env>
+#include <env/ti/k3_dfu.env>
#if CONFIG_CMD_REMOTEPROC
-#include <environment/ti/k3_rproc.env>
+#include <env/ti/k3_rproc.env>
#endif
findfdt=
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index 706b219..d52ac33 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -59,7 +59,7 @@
return 0;
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
#ifdef CONFIG_PHYS_64BIT
/* Limit RAM used by U-Boot to the DDR low region */
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 2398bea..38fe447 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -55,7 +55,7 @@
return 0;
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
#ifdef CONFIG_PHYS_64BIT
/* Limit RAM used by U-Boot to the DDR low region */
diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env
index f7a4880..2f2fb05 100644
--- a/board/ti/j721e/j721e.env
+++ b/board/ti/j721e/j721e.env
@@ -1,10 +1,10 @@
-#include <environment/ti/ti_armv7_common.env>
-#include <environment/ti/mmc.env>
-#include <environment/ti/ufs.env>
-#include <environment/ti/k3_dfu.env>
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/mmc.env>
+#include <env/ti/ufs.env>
+#include <env/ti/k3_dfu.env>
#if CONFIG_CMD_REMOTEPROC
-#include <environment/ti/k3_rproc.env>
+#include <env/ti/k3_rproc.env>
#endif
default_device_tree=ti/k3-j721e-common-proc-board.dtb
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index 8eaca9d..7795300 100644
--- a/board/ti/j721s2/evm.c
+++ b/board/ti/j721s2/evm.c
@@ -43,7 +43,7 @@
return 0;
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
#ifdef CONFIG_PHYS_64BIT
/* Limit RAM used by U-Boot to the DDR low region */
diff --git a/board/ti/j721s2/j721s2.env b/board/ti/j721s2/j721s2.env
index 2ec652d..6825b14 100644
--- a/board/ti/j721s2/j721s2.env
+++ b/board/ti/j721s2/j721s2.env
@@ -1,10 +1,10 @@
-#include <environment/ti/ti_armv7_common.env>
-#include <environment/ti/mmc.env>
-#include <environment/ti/ufs.env>
-#include <environment/ti/k3_dfu.env>
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/mmc.env>
+#include <env/ti/ufs.env>
+#include <env/ti/k3_dfu.env>
#if CONFIG_CMD_REMOTEPROC
-#include <environment/ti/k3_rproc.env>
+#include <env/ti/k3_rproc.env>
#endif
default_device_tree=ti/k3-j721s2-common-proc-board.dtb
diff --git a/board/ti/ks2_evm/k2e_evm.env b/board/ti/ks2_evm/k2e_evm.env
index 746e406..a145db5 100644
--- a/board/ti/ks2_evm/k2e_evm.env
+++ b/board/ti/ks2_evm/k2e_evm.env
@@ -1,5 +1,5 @@
-#include <environment/ti/ti_armv7_common.env>
-#include <environment/ti/ti_armv7_keystone2.env>
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_armv7_keystone2.env>
findfdt=setenv fdtfile ${name_fdt}
boot=ubi
diff --git a/board/ti/ks2_evm/k2g_evm.env b/board/ti/ks2_evm/k2g_evm.env
index 72807ac..4f4941d 100644
--- a/board/ti/ks2_evm/k2g_evm.env
+++ b/board/ti/ks2_evm/k2g_evm.env
@@ -1,6 +1,6 @@
-#include <environment/ti/ti_armv7_common.env>
-#include <environment/ti/ti_armv7_keystone2.env>
-#include <environment/ti/mmc.env>
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_armv7_keystone2.env>
+#include <env/ti/mmc.env>
set_name_pmmc=setenv name_pmmc ti-sci-firmware-k2g.bin
dev_pmmc=0
diff --git a/board/ti/ks2_evm/k2hk_evm.env b/board/ti/ks2_evm/k2hk_evm.env
index f1cdc70..0714a51 100644
--- a/board/ti/ks2_evm/k2hk_evm.env
+++ b/board/ti/ks2_evm/k2hk_evm.env
@@ -1,5 +1,5 @@
-#include <environment/ti/ti_armv7_common.env>
-#include <environment/ti/ti_armv7_keystone2.env>
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_armv7_keystone2.env>
findfdt=setenv fdtfile ${name_fdt}
boot=ubi
diff --git a/board/ti/ks2_evm/k2l_evm.env b/board/ti/ks2_evm/k2l_evm.env
index ddb5cd4..e8a803a 100644
--- a/board/ti/ks2_evm/k2l_evm.env
+++ b/board/ti/ks2_evm/k2l_evm.env
@@ -1,5 +1,5 @@
-#include <environment/ti/ti_armv7_common.env>
-#include <environment/ti/ti_armv7_keystone2.env>
+#include <env/ti/ti_armv7_common.env>
+#include <env/ti/ti_armv7_keystone2.env>
findfdt=setenv fdtfile ${name_fdt}
boot=ubi
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index 3c7cfa3..fa6b722 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -30,6 +30,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/sata.h>
#include <asm/mach-imx/video.h>
+#include <asm/sections.h>
#include <dm/device-internal.h>
#include <dm/platform_data/serial_mxc.h>
#include <dwc_ahsata.h>
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 677caa4..e6c9b10 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -29,6 +29,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/sata.h>
#include <asm/mach-imx/video.h>
+#include <asm/sections.h>
#include <cpu.h>
#include <dm/platform_data/serial_mxc.h>
#include <fsl_esdhc_imx.h>
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index e513f4a..7187e1b 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -139,26 +139,67 @@
[66] = { "Verdin iMX8M Plus Quad 8GB WB", TARGET_IS_ENABLED(VERDIN_IMX8MP) },
[67] = { "Apalis iMX8QM 8GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) },
[68] = { "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
+ [69] = { "Verdin AM62 Quad 1GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
[70] = { "Verdin iMX8M Plus Quad 8GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) },
+ [71] = { "Verdin AM62 Solo 512MB", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+ [72] = { "Verdin AM62 Solo 512MB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+ [73] = { "Verdin AM62 Dual 1GB ET", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+ [74] = { "Verdin AM62 Dual 1GB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+ [75] = { "Verdin AM62 Dual 1GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+ [76] = { "Verdin AM62 Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
};
-const char * const toradex_carrier_boards[] = {
- [0] = "UNKNOWN CARRIER BOARD",
- [155] = "Dahlia",
- [156] = "Verdin Development Board",
+struct pid4list {
+ int pid4;
+ char * const name;
};
-const char * const toradex_display_adapters[] = {
- [0] = "UNKNOWN DISPLAY ADAPTER",
- [157] = "Verdin DSI to HDMI Adapter",
- [159] = "Verdin DSI to LVDS Adapter",
+const struct pid4list toradex_carrier_boards[] = {
+ /* the code assumes unknown at index 0 */
+ {0, "UNKNOWN CARRIER BOARD"},
+ {DAHLIA, "Dahlia"},
+ {VERDIN_DEVELOPMENT_BOARD, "Verdin Development Board"},
+ {YAVIA, "Yavia"},
};
+const struct pid4list toradex_display_adapters[] = {
+ /* the code assumes unknown at index 0 */
+ {0, "UNKNOWN DISPLAY ADAPTER"},
+ {VERDIN_DSI_TO_HDMI_ADAPTER, "Verdin DSI to HDMI Adapter"},
+ {VERDIN_DSI_TO_LVDS_ADAPTER, "Verdin DSI to LVDS Adapter"},
+};
+
const u32 toradex_ouis[] = {
[0] = 0x00142dUL,
[1] = 0x8c06cbUL,
};
+const char * const get_toradex_carrier_boards(int pid4)
+{
+ int i, index = 0;
+
+ for (i = 1; i < ARRAY_SIZE(toradex_carrier_boards); i++) {
+ if (pid4 == toradex_carrier_boards[i].pid4) {
+ index = i;
+ break;
+ }
+ }
+ return toradex_carrier_boards[index].name;
+}
+
+const char * const get_toradex_display_adapters(int pid4)
+{
+ int i, index = 0;
+
+ for (i = 1; i < ARRAY_SIZE(toradex_display_adapters); i++) {
+ if (pid4 == toradex_display_adapters[i].pid4) {
+ index = i;
+ break;
+ }
+ }
+ return toradex_display_adapters[index].name;
+}
+
static u32 get_serial_from_mac(struct toradex_eth_addr *eth_addr)
{
int i;
@@ -638,10 +679,11 @@
int ret = 0;
printf("Supported carrier boards:\n");
- printf("CARRIER BOARD NAME\t\t [ID]\n");
+ printf("%30s\t[ID]\n", "CARRIER BOARD NAME");
for (int i = 0; i < ARRAY_SIZE(toradex_carrier_boards); i++)
- if (toradex_carrier_boards[i])
- printf("%s \t\t [%d]\n", toradex_carrier_boards[i], i);
+ printf("%30s\t[%d]\n",
+ toradex_carrier_boards[i].name,
+ toradex_carrier_boards[i].pid4);
sprintf(message, "Choose your carrier board (provide ID): ");
len = cli_readline(message);
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
index 45fa04c..ea58bd4 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -94,13 +94,20 @@
VERDIN_IMX8MPQ_8GB_WIFI_BT,
APALIS_IMX8QM_8GB_WIFI_BT_IT,
VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN,
- /* 69 */
- VERDIN_IMX8MPQ_8GB_WIFI_BT_IT = 70, /* 70 */
+ VERDIN_AM62Q_WIFI_BT_IT,
+ VERDIN_IMX8MPQ_8GB_WIFI_BT_IT, /* 70 */
+ VERDIN_AM62S_512MB,
+ VERDIN_AM62S_512MB_WIFI_BT_IT,
+ VERDIN_AM62D_1G_ET,
+ VERDIN_AM62D_1G_IT,
+ VERDIN_AM62D_1G_WIFI_BT_IT, /* 75 */
+ VERDIN_AM62Q_2G_WIFI_BT_IT,
};
enum {
DAHLIA = 155,
VERDIN_DEVELOPMENT_BOARD = 156,
+ YAVIA = 173,
};
enum {
@@ -109,7 +116,6 @@
};
extern const struct toradex_som toradex_modules[];
-extern const char * const toradex_carrier_boards[];
extern bool valid_cfgblock;
extern struct toradex_hw tdx_hw_tag;
extern struct toradex_hw tdx_car_hw_tag;
@@ -119,7 +125,8 @@
int read_tdx_cfg_block(void);
int read_tdx_cfg_block_carrier(void);
-
+const char * const get_toradex_carrier_boards(int pid4);
+const char * const get_toradex_display_adapters(int pid4);
int try_migrate_tdx_cfg_block_carrier(void);
void get_mac_from_serial(u32 tdx_serial, struct toradex_eth_addr *eth_addr);
diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c
index 071961f..d144914 100644
--- a/board/toradex/common/tdx-common.c
+++ b/board/toradex/common/tdx-common.c
@@ -31,7 +31,7 @@
#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA
static char tdx_car_serial_str[SERIAL_STR_LEN + 1];
static char tdx_car_rev_str[MODULE_VER_STR_LEN + MODULE_REV_STR_LEN + 1];
-static char *tdx_carrier_board_name;
+static const char *tdx_carrier_board_name;
#endif
#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
@@ -125,8 +125,8 @@
printf("MISSING TORADEX CARRIER CONFIG BLOCKS\n");
try_migrate_tdx_cfg_block_carrier();
} else {
- tdx_carrier_board_name = (char *)
- toradex_carrier_boards[tdx_car_hw_tag.prodid];
+ tdx_carrier_board_name =
+ get_toradex_carrier_boards(tdx_car_hw_tag.prodid);
snprintf(tdx_car_serial_str, sizeof(tdx_car_serial_str),
"%08u", tdx_car_serial);
diff --git a/board/toradex/verdin-am62/Kconfig b/board/toradex/verdin-am62/Kconfig
new file mode 100644
index 0000000..e752224
--- /dev/null
+++ b/board/toradex/verdin-am62/Kconfig
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright 2023 Toradex
+#
+
+choice
+ prompt "Toradex Verdin AM62 based boards"
+ optional
+
+config TARGET_VERDIN_AM62_A53
+ bool "Toradex Verdin AM62 running on A53"
+ select ARM64
+ select BINMAN
+
+config TARGET_VERDIN_AM62_R5
+ bool "Toradex Verdin AM62 running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+
+endchoice
+
+if TARGET_VERDIN_AM62_A53
+
+config SYS_BOARD
+ default "verdin-am62"
+
+config SYS_CONFIG_NAME
+ default "verdin-am62"
+
+config SYS_VENDOR
+ default "toradex"
+
+config TDX_CFG_BLOCK
+ default y
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+ default y
+
+config TDX_CFG_BLOCK_DEV
+ default "0"
+
+config TDX_CFG_BLOCK_EXTRA
+ default y
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+ default "-512"
+
+config TDX_CFG_BLOCK_PART
+ default "1"
+
+config TDX_HAVE_EEPROM_EXTRA
+ default y
+
+config TDX_HAVE_MMC
+ default y
+
+source "board/toradex/common/Kconfig"
+
+endif
+
+if TARGET_VERDIN_AM62_R5
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+config SYS_BOARD
+ default "verdin-am62"
+
+config SYS_CONFIG_NAME
+ default "verdin-am62"
+
+config SYS_VENDOR
+ default "toradex"
+
+endif
diff --git a/board/toradex/verdin-am62/MAINTAINERS b/board/toradex/verdin-am62/MAINTAINERS
new file mode 100644
index 0000000..4e75980
--- /dev/null
+++ b/board/toradex/verdin-am62/MAINTAINERS
@@ -0,0 +1,17 @@
+Verdin AM62
+F: arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
+F: arch/arm/dts/k3-am625-verdin-r5.dts
+F: arch/arm/dts/k3-am625-verdin-wifi-dev.dts
+F: arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
+F: arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
+F: arch/arm/dts/k3-am62-verdin-dev.dtsi
+F: arch/arm/dts/k3-am62-verdin.dtsi
+F: arch/arm/dts/k3-am62-verdin-wifi.dtsi
+F: board/toradex/verdin-am62/
+F: configs/verdin-am62_a53_defconfig
+F: configs/verdin-am62_r5_defconfig
+F: doc/board/toradex/verdin-am62.rst
+F: include/configs/verdin-am62.h
+M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+S: Maintained
+W: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am-62
diff --git a/board/toradex/verdin-am62/Makefile b/board/toradex/verdin-am62/Makefile
new file mode 100644
index 0000000..af1a550
--- /dev/null
+++ b/board/toradex/verdin-am62/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright 2023 Toradex
+#
+
+obj-y += verdin-am62.o
diff --git a/board/toradex/verdin-am62/board-cfg.yaml b/board/toradex/verdin-am62/board-cfg.yaml
new file mode 100644
index 0000000..36cfb55
--- /dev/null
+++ b/board/toradex/verdin-am62/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for AM62
+#
+
+---
+
+board-cfg:
+ rev:
+ boardcfg_abi_maj : 0x0
+ boardcfg_abi_min : 0x1
+ control:
+ subhdr:
+ magic: 0xC1D3
+ size: 7
+ main_isolation_enable : 0x5A
+ main_isolation_hostid : 0x2
+ secproxy:
+ subhdr:
+ magic: 0x1207
+ size: 7
+ scaling_factor : 0x1
+ scaling_profile : 0x1
+ disable_main_nav_secure_proxy : 0
+ msmc:
+ subhdr:
+ magic: 0xA5C3
+ size: 5
+ msmc_cache_size : 0x0
+ debug_cfg:
+ subhdr:
+ magic: 0x020C
+ size: 8
+ trace_dst_enables : 0x00
+ trace_src_enables : 0x00
diff --git a/board/toradex/verdin-am62/pm-cfg.yaml b/board/toradex/verdin-am62/pm-cfg.yaml
new file mode 100644
index 0000000..5d04cf8
--- /dev/null
+++ b/board/toradex/verdin-am62/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for AM62
+#
+
+---
+
+pm-cfg:
+ rev:
+ boardcfg_abi_maj : 0x0
+ boardcfg_abi_min : 0x1
diff --git a/board/toradex/verdin-am62/rm-cfg.yaml b/board/toradex/verdin-am62/rm-cfg.yaml
new file mode 100644
index 0000000..c28707b
--- /dev/null
+++ b/board/toradex/verdin-am62/rm-cfg.yaml
@@ -0,0 +1,1088 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM62
+#
+
+---
+
+rm-cfg:
+ rm_boardcfg:
+ rev:
+ boardcfg_abi_maj : 0x0
+ boardcfg_abi_min : 0x1
+ host_cfg:
+ subhdr:
+ magic: 0x4C41
+ size : 356
+ host_cfg_entries:
+ - #1
+ host_id: 12
+ allowed_atype : 0x2A
+ allowed_qos : 0xAAAA
+ allowed_orderid : 0xAAAAAAAA
+ allowed_priority : 0xAAAA
+ allowed_sched_priority : 0xAA
+ - #2
+ host_id: 30
+ allowed_atype : 0x2A
+ allowed_qos : 0xAAAA
+ allowed_orderid : 0xAAAAAAAA
+ allowed_priority : 0xAAAA
+ allowed_sched_priority : 0xAA
+ - #3
+ host_id: 36
+ allowed_atype : 0x2A
+ allowed_qos : 0xAAAA
+ allowed_orderid : 0xAAAAAAAA
+ allowed_priority : 0xAAAA
+ allowed_sched_priority : 0xAA
+ - #4
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #5
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #6
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #7
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #8
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #9
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #10
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #11
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
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diff --git a/board/toradex/verdin-am62/sec-cfg.yaml b/board/toradex/verdin-am62/sec-cfg.yaml
new file mode 100644
index 0000000..07081ce
--- /dev/null
+++ b/board/toradex/verdin-am62/sec-cfg.yaml
@@ -0,0 +1,379 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security management configuration for AM62
+#
+
+---
+
+sec-cfg:
+ rev:
+ boardcfg_abi_maj : 0x0
+ boardcfg_abi_min : 0x1
+ processor_acl_list:
+ subhdr:
+ magic: 0xF1EA
+ size: 164
+ proc_acl_entries:
+ - #1
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #2
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #3
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #4
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #5
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #6
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #7
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #8
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #9
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #10
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #11
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #12
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #13
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #14
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #15
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #16
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #17
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #18
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #19
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #20
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #21
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #22
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #23
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #24
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #25
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #26
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #27
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #28
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #29
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #30
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #31
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #32
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ host_hierarchy:
+ subhdr:
+ magic: 0x8D27
+ size: 68
+ host_hierarchy_entries:
+ - #1
+ host_id: 0
+ supervisor_host_id: 0
+ - #2
+ host_id: 0
+ supervisor_host_id: 0
+ - #3
+ host_id: 0
+ supervisor_host_id: 0
+ - #4
+ host_id: 0
+ supervisor_host_id: 0
+ - #5
+ host_id: 0
+ supervisor_host_id: 0
+ - #6
+ host_id: 0
+ supervisor_host_id: 0
+ - #7
+ host_id: 0
+ supervisor_host_id: 0
+ - #8
+ host_id: 0
+ supervisor_host_id: 0
+ - #9
+ host_id: 0
+ supervisor_host_id: 0
+ - #10
+ host_id: 0
+ supervisor_host_id: 0
+ - #11
+ host_id: 0
+ supervisor_host_id: 0
+ - #12
+ host_id: 0
+ supervisor_host_id: 0
+ - #13
+ host_id: 0
+ supervisor_host_id: 0
+ - #14
+ host_id: 0
+ supervisor_host_id: 0
+ - #15
+ host_id: 0
+ supervisor_host_id: 0
+ - #16
+ host_id: 0
+ supervisor_host_id: 0
+ - #17
+ host_id: 0
+ supervisor_host_id: 0
+ - #18
+ host_id: 0
+ supervisor_host_id: 0
+ - #19
+ host_id: 0
+ supervisor_host_id: 0
+ - #20
+ host_id: 0
+ supervisor_host_id: 0
+ - #21
+ host_id: 0
+ supervisor_host_id: 0
+ - #22
+ host_id: 0
+ supervisor_host_id: 0
+ - #23
+ host_id: 0
+ supervisor_host_id: 0
+ - #24
+ host_id: 0
+ supervisor_host_id: 0
+ - #25
+ host_id: 0
+ supervisor_host_id: 0
+ - #26
+ host_id: 0
+ supervisor_host_id: 0
+ - #27
+ host_id: 0
+ supervisor_host_id: 0
+ - #28
+ host_id: 0
+ supervisor_host_id: 0
+ - #29
+ host_id: 0
+ supervisor_host_id: 0
+ - #30
+ host_id: 0
+ supervisor_host_id: 0
+ - #31
+ host_id: 0
+ supervisor_host_id: 0
+ - #32
+ host_id: 0
+ supervisor_host_id: 0
+ otp_config:
+ subhdr:
+ magic: 0x4081
+ size: 69
+ write_host_id : 0
+ otp_entry:
+ - #1
+ host_id: 0
+ host_perms: 0
+ - #2
+ host_id: 0
+ host_perms: 0
+ - #3
+ host_id: 0
+ host_perms: 0
+ - #4
+ host_id: 0
+ host_perms: 0
+ - #5
+ host_id: 0
+ host_perms: 0
+ - #6
+ host_id: 0
+ host_perms: 0
+ - #7
+ host_id: 0
+ host_perms: 0
+ - #8
+ host_id: 0
+ host_perms: 0
+ - #9
+ host_id: 0
+ host_perms: 0
+ - #10
+ host_id: 0
+ host_perms: 0
+ - #11
+ host_id: 0
+ host_perms: 0
+ - #12
+ host_id: 0
+ host_perms: 0
+ - #13
+ host_id: 0
+ host_perms: 0
+ - #14
+ host_id: 0
+ host_perms: 0
+ - #15
+ host_id: 0
+ host_perms: 0
+ - #16
+ host_id: 0
+ host_perms: 0
+ - #17
+ host_id: 0
+ host_perms: 0
+ - #18
+ host_id: 0
+ host_perms: 0
+ - #19
+ host_id: 0
+ host_perms: 0
+ - #20
+ host_id: 0
+ host_perms: 0
+ - #21
+ host_id: 0
+ host_perms: 0
+ - #22
+ host_id: 0
+ host_perms: 0
+ - #23
+ host_id: 0
+ host_perms: 0
+ - #24
+ host_id: 0
+ host_perms: 0
+ - #25
+ host_id: 0
+ host_perms: 0
+ - #26
+ host_id: 0
+ host_perms: 0
+ - #27
+ host_id: 0
+ host_perms: 0
+ - #28
+ host_id: 0
+ host_perms: 0
+ - #29
+ host_id: 0
+ host_perms: 0
+ - #30
+ host_id: 0
+ host_perms: 0
+ - #31
+ host_id: 0
+ host_perms: 0
+ - #32
+ host_id: 0
+ host_perms: 0
+ dkek_config:
+ subhdr:
+ magic: 0x5170
+ size: 12
+ allowed_hosts: [128, 0, 0, 0]
+ allow_dkek_export_tisci : 0x5A
+ rsvd: [0, 0, 0]
+ sa2ul_cfg:
+ subhdr:
+ magic: 0x23BE
+ size : 0
+ auth_resource_owner: 0
+ enable_saul_psil_global_config_writes: 0x5A
+ rsvd: [0, 0]
+ sec_dbg_config:
+ subhdr:
+ magic: 0x42AF
+ size: 16
+ allow_jtag_unlock : 0x5A
+ allow_wildcard_unlock : 0x5A
+ allowed_debug_level_rsvd: 0
+ rsvd: 0
+ min_cert_rev : 0x0
+ jtag_unlock_hosts: [0, 0, 0, 0]
+ sec_handover_cfg:
+ subhdr:
+ magic: 0x608F
+ size: 10
+ handover_msg_sender : 0
+ handover_to_host_id : 0
+ rsvd: [0, 0, 0, 0]
diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c
new file mode 100644
index 0000000..a3d1d07
--- /dev/null
+++ b/board/toradex/verdin-am62/verdin-am62.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Board specific initialization for Verdin AM62 SoM
+ *
+ * Copyright 2023 Toradex - https://www.toradex.com/
+ *
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <dm/uclass.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <k3-ddrss.h>
+#include <spl.h>
+
+#include "../common/tdx-cfg-block.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE);
+
+ if (gd->ram_size < SZ_64M)
+ puts("## WARNING: Less than 64MB RAM detected\n");
+
+ return 0;
+}
+
+/*
+ * Avoid relocated U-Boot clash with Linux reserved-memory on 512 MB SoM
+ */
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
+{
+ return 0x9C000000;
+}
+
+#if defined(CONFIG_SPL_LOAD_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ return 0;
+}
+#endif
+
+#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ return ft_common_board_setup(blob, bd);
+}
+#endif
+
+static void select_dt_from_module_version(void)
+{
+ char variant[32];
+ char *env_variant = env_get("variant");
+ int is_wifi = 0;
+
+ if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) {
+ /*
+ * If we have a valid config block and it says we are a module with
+ * Wi-Fi/Bluetooth make sure we use the -wifi device tree.
+ */
+ is_wifi = (tdx_hw_tag.prodid == VERDIN_AM62Q_WIFI_BT_IT) ||
+ (tdx_hw_tag.prodid == VERDIN_AM62S_512MB_WIFI_BT_IT) ||
+ (tdx_hw_tag.prodid == VERDIN_AM62D_1G_WIFI_BT_IT) ||
+ (tdx_hw_tag.prodid == VERDIN_AM62Q_2G_WIFI_BT_IT);
+ }
+
+ if (is_wifi)
+ strlcpy(&variant[0], "wifi", sizeof(variant));
+ else
+ strlcpy(&variant[0], "nonwifi", sizeof(variant));
+
+ if (strcmp(variant, env_variant)) {
+ printf("Setting variant to %s\n", variant);
+ env_set("variant", variant);
+ }
+}
+
+int board_late_init(void)
+{
+ select_dt_from_module_version();
+
+ return 0;
+}
+
+#define CTRLMMR_USB0_PHY_CTRL 0x43004008
+#define CTRLMMR_USB1_PHY_CTRL 0x43004018
+#define CORE_VOLTAGE 0x80000000
+#define MCU_CTRL_LFXOSC_32K_BYPASS_VAL BIT(4)
+
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+ u32 val;
+
+ /* Set USB0 PHY core voltage to 0.85V */
+ val = readl(CTRLMMR_USB0_PHY_CTRL);
+ val &= ~(CORE_VOLTAGE);
+ writel(val, CTRLMMR_USB0_PHY_CTRL);
+
+ /* Set USB1 PHY core voltage to 0.85V */
+ val = readl(CTRLMMR_USB1_PHY_CTRL);
+ val &= ~(CORE_VOLTAGE);
+ writel(val, CTRLMMR_USB1_PHY_CTRL);
+
+ /* We use the 32k FOUT from the Epson RX8130CE RTC chip */
+ /* In WKUP_LFOSC0 clear the power down bit and set the bypass bit
+ * The bypass bit is required as we provide a CMOS clock signal and
+ * the power down seems to be required also in the bypass case
+ * despite of the datasheet stating otherwise
+ */
+ /* Compare with the AM62 datasheet,
+ * Table 7-21. LFXOSC Modes of Operation
+ */
+ val = readl(MCU_CTRL_LFXOSC_CTRL);
+ val &= ~MCU_CTRL_LFXOSC_32K_DISABLE_VAL;
+ val |= MCU_CTRL_LFXOSC_32K_BYPASS_VAL;
+ writel(val, MCU_CTRL_LFXOSC_CTRL);
+ /* Make sure to mux up to take the SoC 32k from the LFOSC input */
+ writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL,
+ MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
+}
+#endif
diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c
index 9d54d60..afa3686 100644
--- a/board/toradex/verdin-imx8mm/spl.c
+++ b/board/toradex/verdin-imx8mm/spl.c
@@ -16,6 +16,7 @@
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
+#include <asm/sections.h>
#include <cpu_func.h>
#include <dm/device.h>
#include <dm/device-internal.h>
diff --git a/board/traverse/ten64/ten64.c b/board/traverse/ten64/ten64.c
index 5dfb716..df9f0af 100644
--- a/board/traverse/ten64/ten64.c
+++ b/board/traverse/ten64/ten64.c
@@ -31,6 +31,7 @@
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <nvme.h>
#include <fsl_immap.h>
@@ -47,7 +48,9 @@
enum {
TEN64_BOARD_REV_A = 0xFF,
TEN64_BOARD_REV_B = 0xFE,
- TEN64_BOARD_REV_C = 0xFD
+ TEN64_BOARD_REV_C = 0xFD,
+ TEN64_BOARD_REV_D = 0xFC,
+ TEN64_BOARD_MAX
};
#define RESV_MEM_IN_BANK(b) (gd->arch.resv_ram >= base[b] && \
@@ -75,20 +78,24 @@
switch (board_rev) {
case TEN64_BOARD_REV_A:
- snprintf(boardmodel, 32, "1064-0201A (Alpha)");
+ snprintf(boardmodel, 32, "A (Alpha)");
break;
case TEN64_BOARD_REV_B:
- snprintf(boardmodel, 32, "1064-0201B (Beta)");
+ snprintf(boardmodel, 32, "B (Beta)");
break;
case TEN64_BOARD_REV_C:
- snprintf(boardmodel, 32, "1064-0201C");
+ snprintf(boardmodel, 32, "C");
+ break;
+ case TEN64_BOARD_REV_D:
+ snprintf(boardmodel, 32, "D");
break;
default:
- snprintf(boardmodel, 32, "1064 Revision %X", (0xFF - board_rev));
+ snprintf(boardmodel, 32, " Revision %X", (0xFF - board_rev));
break;
}
+ printf("Board: 1064-0201%s, boot from ", boardmodel);
+
- printf("Board: %s, boot from ", boardmodel);
if (src == BOOT_SOURCE_SD_MMC)
puts("SD card\n");
else if (src == BOOT_SOURCE_QSPI_NOR)
@@ -167,6 +174,12 @@
return;
}
+ /* In the U-Boot FDT, a 'simple-mfd' compatible is added.
+ * Remove this as FreeBSD will only match "fsl,qoriq-mc"
+ * exactly on the DPAA2 bus/MC node.
+ */
+ fdt_setprop(fdt, offset, "compatible", "fsl,qoriq-mc", 12);
+
if (get_mc_boot_status() == 0 &&
(is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
fdt_status_okay(fdt, offset);
@@ -178,6 +191,11 @@
int fsl_board_late_init(void)
{
ten64_board_retimer_ds110df410_init();
+
+ /* Ensure nvme storage devices are available to bootflow */
+ if (IS_ENABLED(CONFIG_NVME))
+ nvme_scan_namespace();
+
return 0;
}
@@ -284,6 +302,7 @@
{
char ethaddr[18];
char enetvar[10];
+ char serial[18];
u8 intfidx, this_dpmac_num;
u64 macaddr = 0;
/* We will copy the MAC address returned from the
@@ -304,6 +323,19 @@
*/
macaddr = __be64_to_cpu(macaddr);
+ /* Set serial# to GE0/DPMAC7 MAC address
+ * (Matches the labels on the board and appliance)
+ */
+ snprintf(serial, 18, "%02X%02X%02X%02X%02X%02X",
+ MACADDRBITS(macaddr, 40),
+ MACADDRBITS(macaddr, 32),
+ MACADDRBITS(macaddr, 24),
+ MACADDRBITS(macaddr, 16),
+ MACADDRBITS(macaddr, 8),
+ MACADDRBITS(macaddr, 0));
+ if (!env_get("serial#"))
+ env_set("serial#", serial);
+
for (intfidx = 0; intfidx < 10; intfidx++) {
snprintf(ethaddr, 18, "%02X:%02X:%02X:%02X:%02X:%02X",
MACADDRBITS(macaddr, 40),
@@ -316,8 +348,8 @@
this_dpmac_num = allocation_order[intfidx];
printf("DPMAC%d: %s\n", this_dpmac_num, ethaddr);
snprintf(enetvar, 10,
- (this_dpmac_num != 1) ? "eth%daddr" : "ethaddr",
- this_dpmac_num - 1);
+ (intfidx != 0) ? "eth%daddr" : "ethaddr",
+ intfidx);
macaddr++;
if (!env_get(enetvar))
@@ -335,20 +367,32 @@
u8 loop;
struct udevice *uc_dev;
struct udevice *i2cbus;
+ u32 board_rev = ten64_get_board_rev();
ret = ten64_get_micro_udevice(&uc_dev, &i2cbus);
if (ret)
return ret;
- ret = dm_i2c_probe(i2cbus, I2C_RETIMER_ADDR, 0, retim_dev);
- if (ret == 0) {
- puts("(retimer on, resetting...) ");
+ /* Retimer power cycle not implemented on early board
+ * revisions/controller firmwares
+ */
+ if (IS_ENABLED(CONFIG_TEN64_CONTROLLER) &&
+ board_rev <= TEN64_BOARD_REV_C) {
+ ret = dm_i2c_probe(i2cbus, I2C_RETIMER_ADDR, 0, retim_dev);
+ if (ret == 0) {
+ puts("(retimer on, resetting...) ");
- ret = misc_call(uc_dev, TEN64_CNTRL_10G_OFF, NULL, 0, NULL, 0);
- mdelay(1000);
- }
+ ret = misc_call(uc_dev, TEN64_CNTRL_10G_OFF, NULL, 0, NULL, 0);
+ if (ret)
+ return ret;
+ mdelay(1000);
+ }
- ret = misc_call(uc_dev, TEN64_CNTRL_10G_ON, NULL, 0, NULL, 0);
+ /* Turn on the retimer */
+ ret = misc_call(uc_dev, TEN64_CNTRL_10G_ON, NULL, 0, NULL, 0);
+ if (ret)
+ return ret;
+ }
// Wait for retimer to come back
for (loop = 0; loop < 5; loop++) {
@@ -369,19 +413,13 @@
u8 reg;
int ret;
struct udevice *retim_dev;
- u32 board_rev = ten64_get_board_rev();
puts("Retimer: ");
- /* Retimer power cycle not implemented on early board
- * revisions/controller firmwares
- */
- if (IS_ENABLED(CONFIG_TEN64_CONTROLLER) &&
- board_rev >= TEN64_BOARD_REV_C) {
- ret = board_cycle_retimer(&retim_dev);
- if (ret) {
- puts("Retimer power on failed\n");
- return;
- }
+
+ ret = board_cycle_retimer(&retim_dev);
+ if (ret) {
+ puts("Retimer power on failed\n");
+ return;
}
/* Access to Control/Shared register */
@@ -437,3 +475,13 @@
puts("OK\n");
}
+
+/* Opt out of the fsl_setenv_bootcmd
+ * in arch/arm/cpu/armv8/fsl-layerscape/soc.c
+ * which is invoked by board_late_init.
+ */
+int fsl_setenv_bootcmd(void)
+{
+ return 0;
+}
+
diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
index 1287f71..730e266 100644
--- a/board/udoo/neo/neo.c
+++ b/board/udoo/neo/neo.c
@@ -17,6 +17,7 @@
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
+#include <asm/sections.h>
#include <dm.h>
#include <env.h>
#include <mmc.h>
diff --git a/board/variscite/dart_6ul/spl.c b/board/variscite/dart_6ul/spl.c
index 17b1ae7..1dff69c 100644
--- a/board/variscite/dart_6ul/spl.c
+++ b/board/variscite/dart_6ul/spl.c
@@ -12,6 +12,7 @@
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/crm_regs.h>
+#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
diff --git a/board/variscite/imx8mn_var_som/spl.c b/board/variscite/imx8mn_var_som/spl.c
index 41e7050..01a63c6 100644
--- a/board/variscite/imx8mn_var_som/spl.c
+++ b/board/variscite/imx8mn_var_som/spl.c
@@ -13,6 +13,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/gpio.h>
+#include <asm/sections.h>
#include <dm/device.h>
#include <dm/uclass.h>
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 0328d68..2caeb32 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -374,12 +374,12 @@
* region
*/
if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
- fdt_blob = (ulong *)&_image_binary_end;
+ fdt_blob = (ulong *)_image_binary_end;
else
- fdt_blob = (ulong *)&__bss_end;
+ fdt_blob = (ulong *)__bss_end;
} else {
/* FDT is at end of image */
- fdt_blob = (ulong *)&_end;
+ fdt_blob = (ulong *)_end;
}
if (fdt_magic(fdt_blob) == FDT_MAGIC)
@@ -627,7 +627,7 @@
#endif
#if defined(CONFIG_LMB)
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
phys_size_t size;
phys_addr_t reg;
diff --git a/boot/Kconfig b/boot/Kconfig
index e8fb03b..86ccfd7 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -464,8 +464,11 @@
config BOOTMETH_CROS
bool "Bootdev support for Chromium OS"
- depends on X86 || SANDBOX
- default y
+ depends on X86 || ARM || SANDBOX
+ default y if !ARM
+ select EFI_PARTITION
+ select PARTITION_TYPE_GUID
+ select PARTITION_UUIDS
help
Enables support for booting Chromium OS using bootdevs. This uses the
kernel A slot and obtains the kernel command line from the parameters
@@ -1007,7 +1010,7 @@
config BOOTSTAGE_STASH_ADDR
hex "Address to stash boot timing information"
- default 0
+ default 0x0
help
Provide an address which will not be overwritten by the OS when it
starts, so that it can read this information when ready.
diff --git a/boot/android_ab.c b/boot/android_ab.c
index 73b55c1..0f20a34 100644
--- a/boot/android_ab.c
+++ b/boot/android_ab.c
@@ -12,7 +12,6 @@
#include <memalign.h>
#include <linux/err.h>
#include <u-boot/crc.h>
-#include <u-boot/crc.h>
/**
* Compute the CRC-32 of the bootloader control struct.
diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c
index 9660ff7..69506e3 100644
--- a/boot/bootdev-uclass.c
+++ b/boot/bootdev-uclass.c
@@ -111,6 +111,8 @@
int bootdev_find_in_blk(struct udevice *dev, struct udevice *blk,
struct bootflow_iter *iter, struct bootflow *bflow)
{
+ struct bootmeth_uc_plat *plat = dev_get_uclass_plat(bflow->method);
+ bool allow_any_part = plat->flags & BOOTMETHF_ANY_PART;
struct blk_desc *desc = dev_get_uclass_plat(blk);
struct disk_partition info;
char partstr[20];
@@ -142,6 +144,7 @@
* us whether there is valid media there
*/
ret = part_get_info(desc, iter->part, &info);
+ log_debug("part_get_info() returned %d\n", ret);
if (!iter->part && ret == -ENOENT)
ret = 0;
@@ -154,7 +157,7 @@
ret = -ESHUTDOWN;
else
bflow->state = BOOTFLOWST_MEDIA;
- if (ret) {
+ if (ret && !allow_any_part) {
/* allow partition 1 to be missing */
if (iter->part == 1) {
iter->max_part = 3;
@@ -174,9 +177,15 @@
if (!iter->part) {
iter->first_bootable = part_get_bootable(desc);
log_debug("checking bootable=%d\n", iter->first_bootable);
+ } else if (allow_any_part) {
+ /*
+ * allow any partition to be scanned, by skipping any checks
+ * for filesystems or partition contents on this disk
+ */
/* if there are bootable partitions, scan only those */
- } else if (iter->first_bootable ? !info.bootable : iter->part != 1) {
+ } else if (iter->first_bootable >= 0 &&
+ (iter->first_bootable ? !info.bootable : iter->part != 1)) {
return log_msg_ret("boot", -EINVAL);
} else {
ret = fs_set_blk_dev_with_part(desc, bflow->part);
@@ -184,16 +193,16 @@
if (ret)
return log_msg_ret("fs", ret);
- /* Use an #ifdef due to info.sys_ind */
-#ifdef CONFIG_DOS_PARTITION
log_debug("%s: Found partition %x type %x fstype %d\n",
- blk->name, bflow->part, info.sys_ind,
+ blk->name, bflow->part,
+ IS_ENABLED(CONFIG_DOS_PARTITION) ?
+ disk_partition_sys_ind(&info) : 0,
ret ? -1 : fs_get_type());
-#endif
bflow->blk = blk;
bflow->state = BOOTFLOWST_FS;
}
+ log_debug("method %s\n", bflow->method->name);
ret = bootmeth_read_bootflow(bflow->method, bflow);
if (ret)
return log_msg_ret("method", ret);
@@ -216,7 +225,7 @@
for (i = 0; dev; i++) {
printf("%3x [ %c ] %6s %-9.9s %s\n", dev_seq(dev),
device_active(dev) ? '+' : ' ',
- ret ? simple_itoa(ret) : "OK",
+ ret ? simple_itoa(-ret) : "OK",
dev_get_uclass_name(dev_get_parent(dev)), dev->name);
if (probe)
ret = uclass_next_device_check(&dev);
@@ -262,7 +271,7 @@
return len;
}
-int bootdev_setup_sibling_blk(struct udevice *blk, const char *drv_name)
+int bootdev_setup_for_sibling_blk(struct udevice *blk, const char *drv_name)
{
struct udevice *parent, *dev;
char dev_name[50];
@@ -305,7 +314,9 @@
if (device_get_uclass_id(dev) != UCLASS_BOOTDEV)
return -EINVAL;
- /* This should always work if bootdev_setup_sibling_blk() was used */
+ /*
+ * This should always work if bootdev_setup_for_sibling_blk() was used
+ */
len = bootdev_get_suffix_start(dev, ".bootdev");
ret = device_find_child_by_namelen(parent, dev->name, len, &blk);
if (ret) {
@@ -335,7 +346,7 @@
if (device_get_uclass_id(blk) != UCLASS_BLK)
return -EINVAL;
- /* This should always work if bootdev_setup_sibling_blk() was used */
+ /* This should always work if bootdev_setup_for_sibling_blk() was used */
len = bootdev_get_suffix_start(blk, ".blk");
snprintf(dev_name, sizeof(dev_name), "%.*s.%s", len, blk->name,
"bootdev");
@@ -535,6 +546,8 @@
int ret;
ret = bootdev_get_sibling_blk(dev, &blk);
+ log_debug("sibling_blk ret=%d, blk=%s\n", ret,
+ ret ? "(none)" : blk->name);
/*
* If there is no media, indicate that no more partitions should be
* checked
@@ -556,7 +569,8 @@
{
const struct bootdev_ops *ops = bootdev_get_ops(dev);
- log_debug("->get_bootflow %s=%p\n", dev->name, ops->get_bootflow);
+ log_debug("->get_bootflow %s,%x=%p\n", dev->name, iter->part,
+ ops->get_bootflow);
bootflow_init(bflow, dev, iter->method);
if (!ops->get_bootflow)
return default_get_bootflow(dev, iter, bflow);
@@ -660,7 +674,8 @@
ret = bootdev_hunt_prio(iter->cur_prio,
iter->flags &
BOOTFLOWIF_SHOW);
- log_debug("- hunt ret %d\n", ret);
+ log_debug("- bootdev_hunt_prio() ret %d\n",
+ ret);
if (ret)
return log_msg_ret("hun", ret);
}
@@ -696,6 +711,7 @@
/* hunt for any pre-scan devices */
if (iter->flags & BOOTFLOWIF_HUNT) {
ret = bootdev_hunt_prio(BOOTDEVP_1_PRE_SCAN, show);
+ log_debug("- bootdev_hunt_prio() ret %d\n", ret);
if (ret)
return log_msg_ret("pre", ret);
}
@@ -766,6 +782,7 @@
log_debug("Hunting with: %s\n", name);
if (info->hunt) {
ret = info->hunt(info, show);
+ log_debug(" - hunt result %d\n", ret);
if (ret)
return ret;
}
@@ -831,9 +848,11 @@
if (prio != info->prio)
continue;
ret = bootdev_hunt_drv(info, i, show);
+ log_debug("bootdev_hunt_drv() return %d\n", ret);
if (ret && ret != -ENOENT)
result = ret;
}
+ log_debug("exit %d\n", result);
return result;
}
diff --git a/boot/bootflow.c b/boot/bootflow.c
index 81b5829..6ef62e1 100644
--- a/boot/bootflow.c
+++ b/boot/bootflow.c
@@ -432,6 +432,7 @@
free(bflow->buf);
free(bflow->os_name);
free(bflow->fdt_fname);
+ free(bflow->bootmeth_priv);
}
void bootflow_remove(struct bootflow *bflow)
@@ -444,6 +445,22 @@
free(bflow);
}
+#if CONFIG_IS_ENABLED(BOOTSTD_FULL)
+int bootflow_read_all(struct bootflow *bflow)
+{
+ int ret;
+
+ if (bflow->state != BOOTFLOWST_READY)
+ return log_msg_ret("rd", -EPROTO);
+
+ ret = bootmeth_read_all(bflow->method, bflow);
+ if (ret)
+ return log_msg_ret("rd2", ret);
+
+ return 0;
+}
+#endif /* BOOTSTD_FULL */
+
int bootflow_boot(struct bootflow *bflow)
{
int ret;
diff --git a/boot/bootm.c b/boot/bootm.c
index 75f0b4a..b1c3afe 100644
--- a/boot/bootm.c
+++ b/boot/bootm.c
@@ -823,6 +823,43 @@
return ret;
}
+int bootm_boot_start(ulong addr, const char *cmdline)
+{
+ static struct cmd_tbl cmd = {"bootm"};
+ char addr_str[30];
+ char *argv[] = {addr_str, NULL};
+ int states;
+ int ret;
+
+ /*
+ * TODO(sjg@chromium.org): This uses the command-line interface, but
+ * should not. To clean this up, the various bootm states need to be
+ * passed an info structure instead of cmdline flags. Then this can
+ * set up the required info and move through the states without needing
+ * the command line.
+ */
+ states = BOOTM_STATE_START | BOOTM_STATE_FINDOS | BOOTM_STATE_PRE_LOAD |
+ BOOTM_STATE_FINDOTHER | BOOTM_STATE_LOADOS |
+ BOOTM_STATE_OS_PREP | BOOTM_STATE_OS_FAKE_GO |
+ BOOTM_STATE_OS_GO;
+ if (IS_ENABLED(CONFIG_SYS_BOOT_RAMDISK_HIGH))
+ states |= BOOTM_STATE_RAMDISK;
+ if (IS_ENABLED(CONFIG_PPC) || IS_ENABLED(CONFIG_MIPS))
+ states |= BOOTM_STATE_OS_CMDLINE;
+ images.state |= states;
+
+ snprintf(addr_str, sizeof(addr_str), "%lx", addr);
+
+ ret = env_set("bootargs", cmdline);
+ if (ret) {
+ printf("Failed to set cmdline\n");
+ return ret;
+ }
+ ret = do_bootm_states(&cmd, 0, 1, argv, states, &images, 1);
+
+ return ret;
+}
+
#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
/**
* image_get_kernel - verify legacy format kernel image
diff --git a/boot/bootmeth-uclass.c b/boot/bootmeth-uclass.c
index eeded08..1d157d5 100644
--- a/boot/bootmeth-uclass.c
+++ b/boot/bootmeth-uclass.c
@@ -61,6 +61,18 @@
return ops->set_bootflow(dev, bflow, buf, size);
}
+#if CONFIG_IS_ENABLED(BOOTSTD_FULL)
+int bootmeth_read_all(struct udevice *dev, struct bootflow *bflow)
+{
+ const struct bootmeth_ops *ops = bootmeth_get_ops(dev);
+
+ if (!ops->read_all)
+ return -ENOSYS;
+
+ return ops->read_all(dev, bflow);
+}
+#endif /* BOOTSTD_FULL */
+
int bootmeth_boot(struct udevice *dev, struct bootflow *bflow)
{
const struct bootmeth_ops *ops = bootmeth_get_ops(dev);
@@ -240,18 +252,7 @@
return 0;
}
-/**
- * setup_fs() - Set up read to read a file
- *
- * We must redo the setup before each filesystem operation. This function
- * handles that, including setting the filesystem type if a block device is not
- * being used
- *
- * @bflow: Information about file to try
- * @desc: Block descriptor to read from (NULL if not a block device)
- * Return: 0 if OK, -ve on error
- */
-static int setup_fs(struct bootflow *bflow, struct blk_desc *desc)
+int bootmeth_setup_fs(struct bootflow *bflow, struct blk_desc *desc)
{
int ret;
@@ -288,7 +289,7 @@
log_debug(" %s - err=%d\n", path, ret);
/* Sadly FS closes the file after fs_size() so we must redo this */
- ret2 = setup_fs(bflow, desc);
+ ret2 = bootmeth_setup_fs(bflow, desc);
if (ret2)
return log_msg_ret("fs", ret2);
@@ -337,14 +338,14 @@
if (bflow->blk)
desc = dev_get_uclass_plat(bflow->blk);
- ret = setup_fs(bflow, desc);
+ ret = bootmeth_setup_fs(bflow, desc);
if (ret)
return log_msg_ret("fs", ret);
ret = fs_size(path, &size);
log_debug(" %s - err=%d\n", path, ret);
- ret = setup_fs(bflow, desc);
+ ret = bootmeth_setup_fs(bflow, desc);
if (ret)
return log_msg_ret("fs", ret);
@@ -369,7 +370,7 @@
if (bflow->blk)
desc = dev_get_uclass_plat(bflow->blk);
- ret = setup_fs(bflow, desc);
+ ret = bootmeth_setup_fs(bflow, desc);
if (ret)
return log_msg_ret("fs", ret);
@@ -379,7 +380,7 @@
if (size > *sizep)
return log_msg_ret("spc", -ENOSPC);
- ret = setup_fs(bflow, desc);
+ ret = bootmeth_setup_fs(bflow, desc);
if (ret)
return log_msg_ret("fs", ret);
diff --git a/boot/bootmeth_cros.c b/boot/bootmeth_cros.c
index aa19ae0..20e0b1e 100644
--- a/boot/bootmeth_cros.c
+++ b/boot/bootmeth_cros.c
@@ -12,26 +12,81 @@
#include <blk.h>
#include <bootdev.h>
#include <bootflow.h>
+#include <bootm.h>
#include <bootmeth.h>
+#include <display_options.h>
#include <dm.h>
+#include <efi.h>
#include <malloc.h>
#include <mapmem.h>
#include <part.h>
-#ifdef CONFIG_X86
-#include <asm/zimage.h>
-#endif
#include <linux/sizes.h>
+#include "bootmeth_cros.h"
+
+static const efi_guid_t cros_kern_type = PARTITION_CROS_KERNEL;
+
+/*
+ * Layout of the ChromeOS kernel
+ *
+ * Partitions 2 and 4 contain kernels with type GUID_CROS_KERNEL
+ *
+ * Contents are:
+ *
+ * Offset Contents
+ * 0 struct vb2_keyblock
+ * m struct vb2_kernel_preamble
+ * m + n kernel buffer
+ *
+ * m is keyblock->keyblock_size
+ * n is preamble->preamble_size
+ *
+ * The kernel buffer itself consists of various parts:
+ *
+ * Offset Contents
+ * m + n kernel image (Flat vmlinux binary or FIT)
+ * b - 8KB Command line text
+ * b - 4KB X86 setup block (struct boot_params, extends for about 16KB)
+ * b X86 bootloader (continuation of setup block)
+ * b + 16KB X86 setup block (copy, used for hold data pointed to)
+ *
+ * b is m + n + preamble->bootloader_address - preamble->body_load_address
+ *
+ * Useful metadata extends from b - 8KB through to b + 32 KB
+ */
enum {
- /* Offsets in the kernel-partition header */
- KERN_START = 0x4f0,
- KERN_SIZE = 0x518,
+ PROBE_SIZE = SZ_4K, /* initial bytes read from partition */
- SETUP_OFFSET = 0x1000, /* bytes before base */
- CMDLINE_OFFSET = 0x2000, /* bytes before base */
- OFFSET_BASE = 0x100000, /* assumed kernel load-address */
+ X86_SETUP_OFFSET = -0x1000, /* setup offset relative to base */
+ CMDLINE_OFFSET = -0x2000, /* cmdline offset relative to base */
+ X86_KERNEL_OFFSET = 0x4000, /* kernel offset relative to base */
};
+/**
+ * struct cros_priv - Private data
+ *
+ * This is read from the disk and recorded for use when the full kernel must
+ * be loaded and booted
+ *
+ * @body_offset: Offset of kernel body from start of partition (in bytes)
+ * @body_size: Size of kernel body in bytes
+ * @part_start: Block offset of selected partition from the start of the disk
+ * @body_load_address: Nominal load address for kernel body
+ * @bootloader_address: Address of bootloader, after body is loaded at
+ * body_load_address
+ * @bootloader_size: Size of bootloader in bytes
+ * @info_buf: Buffer containing ChromiumOS info
+ */
+struct cros_priv {
+ ulong body_offset;
+ ulong body_size;
+ lbaint_t part_start;
+ ulong body_load_address;
+ ulong bootloader_address;
+ ulong bootloader_size;
+ void *info_buf;
+};
+
static int cros_check(struct udevice *dev, struct bootflow_iter *iter)
{
/* This only works on block and network devices */
@@ -77,61 +132,96 @@
return 0;
}
-static int cros_read_bootflow(struct udevice *dev, struct bootflow *bflow)
+/**
+ * scan_part() - Scan a kernel partition to see if has a ChromeOS header
+ *
+ * This reads the first PROBE_SIZE of a partition, loookng for
+ * VB2_KEYBLOCK_MAGIC
+ *
+ * @blk: Block device to scan
+ * @partnum: Partition number to scan
+ * @info: Please to put partition info
+ * @hdrp: Return allocated keyblock header on success
+ */
+static int scan_part(struct udevice *blk, int partnum,
+ struct disk_partition *info, struct vb2_keyblock **hdrp)
{
- struct blk_desc *desc = dev_get_uclass_plat(bflow->blk);
- ulong base, start, size, setup, cmdline, num_blks, kern_base;
- struct disk_partition info;
- const char *uuid = NULL;
- void *buf, *hdr;
+ struct blk_desc *desc = dev_get_uclass_plat(blk);
+ struct vb2_keyblock *hdr;
+ struct uuid type;
+ ulong num_blks;
int ret;
- log_debug("starting, part=%d\n", bflow->part);
+ if (!partnum)
+ return log_msg_ret("efi", -ENOENT);
- /* We consider the whole disk, not any one partition */
- if (bflow->part)
- return log_msg_ret("max", -ENOENT);
-
- /* Check partition 2 */
- ret = part_get_info(desc, 2, &info);
+ ret = part_get_info(desc, partnum, info);
if (ret)
return log_msg_ret("part", ret);
+ /* Check for kernel partition type */
+ log_debug("part %x: type=%s\n", partnum, info->type_guid);
+ if (uuid_str_to_bin(info->type_guid, (u8 *)&type, UUID_STR_FORMAT_GUID))
+ return log_msg_ret("typ", -EINVAL);
+
+ if (memcmp(&cros_kern_type, &type, sizeof(type)))
+ return log_msg_ret("typ", -ENOEXEC);
+
/* Make a buffer for the header information */
- num_blks = SZ_4K >> desc->log2blksz;
+ num_blks = PROBE_SIZE >> desc->log2blksz;
log_debug("Reading header, blk=%s, start=%lx, blocks=%lx\n",
- bflow->blk->name, (ulong)info.start, num_blks);
- hdr = memalign(SZ_1K, SZ_4K);
+ blk->name, (ulong)info->start, num_blks);
+ hdr = memalign(SZ_1K, PROBE_SIZE);
if (!hdr)
return log_msg_ret("hdr", -ENOMEM);
- ret = blk_read(bflow->blk, info.start, num_blks, hdr);
- if (ret != num_blks)
- return log_msg_ret("inf", ret);
+ ret = blk_read(blk, info->start, num_blks, hdr);
+ if (ret != num_blks) {
+ free(hdr);
+ return log_msg_ret("inf", -EIO);
+ }
- if (memcmp("CHROMEOS", hdr, 8))
+ if (memcmp(VB2_KEYBLOCK_MAGIC, hdr->magic, VB2_KEYBLOCK_MAGIC_SIZE)) {
+ free(hdr);
+ log_debug("no magic\n");
return -ENOENT;
+ }
- log_info("Header at %lx\n", (ulong)map_to_sysmem(hdr));
- start = *(u32 *)(hdr + KERN_START);
- size = ALIGN(*(u32 *)(hdr + KERN_SIZE), desc->blksz);
- log_debug("Reading start %lx size %lx\n", start, size);
- bflow->size = size;
+ *hdrp = hdr;
- buf = memalign(SZ_1K, size);
- if (!buf)
- return log_msg_ret("buf", -ENOMEM);
+ return 0;
+}
+
+/**
+ * cros_read_buf() - Read information into a buf and parse it
+ *
+ * @bflow: Bootflow to update
+ * @buf: Buffer to use
+ * @size: Size of buffer and number of bytes to read thereinto
+ * @start: Start offset to read from on disk
+ * @before_base: Number of bytes to read before the bootloader base
+ * @uuid: UUID string if supported, else NULL
+ * Return: 0 if OK, -ENOMEM if out of memory, -EIO on read failure
+ */
+static int cros_read_buf(struct bootflow *bflow, void *buf, ulong size,
+ loff_t start, ulong before_base, const char *uuid)
+{
+ struct blk_desc *desc = dev_get_uclass_plat(bflow->blk);
+ ulong base, setup, cmdline, kern_base;
+ ulong num_blks;
+ int ret;
+
num_blks = size >> desc->log2blksz;
- log_debug("Reading data, blk=%s, start=%lx, blocks=%lx\n",
- bflow->blk->name, (ulong)info.start, num_blks);
- ret = blk_read(bflow->blk, (ulong)info.start + 0x80, num_blks, buf);
+ log_debug("Reading info to %lx, blk=%s, size=%lx, blocks=%lx\n",
+ (ulong)map_to_sysmem(buf), bflow->blk->name, size, num_blks);
+ ret = blk_read(bflow->blk, start, num_blks, buf);
if (ret != num_blks)
- return log_msg_ret("inf", ret);
- base = map_to_sysmem(buf);
+ return log_msg_ret("inf", -EIO);
+ base = map_to_sysmem(buf) + before_base;
- setup = base + start - OFFSET_BASE - SETUP_OFFSET;
- cmdline = base + start - OFFSET_BASE - CMDLINE_OFFSET;
- kern_base = base + start - OFFSET_BASE + SZ_16K;
- log_debug("base %lx setup %lx, cmdline %lx, kern_base %lx\n", base,
+ setup = base + X86_SETUP_OFFSET;
+ cmdline = base + CMDLINE_OFFSET;
+ kern_base = base + X86_KERNEL_OFFSET;
+ log_debug("base %lx setup %lx cmdline %lx kern_base %lx\n", base,
setup, cmdline, kern_base);
#ifdef CONFIG_X86
@@ -151,35 +241,206 @@
if (!bflow->os_name)
return log_msg_ret("os", -ENOMEM);
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- uuid = info.uuid;
-#endif
ret = copy_cmdline(map_sysmem(cmdline, 0), uuid, &bflow->cmdline);
if (ret)
return log_msg_ret("cmd", ret);
+ bflow->x86_setup = map_sysmem(setup, 0);
- bflow->state = BOOTFLOWST_READY;
+ return 0;
+}
+
+/**
+ * cros_read_info() - Read information and fill out the bootflow
+ *
+ * @bflow: Bootflow to update
+ * @uuid: UUID string if supported, else NULL
+ * @preamble: Kernel preamble information
+ * Return: 0 if OK, -ENOMEM if out of memory, -EIO on read failure
+ */
+static int cros_read_info(struct bootflow *bflow, const char *uuid,
+ const struct vb2_kernel_preamble *preamble)
+{
+ struct cros_priv *priv = bflow->bootmeth_priv;
+ struct udevice *blk = bflow->blk;
+ struct blk_desc *desc = dev_get_uclass_plat(blk);
+ ulong offset, size, before_base;
+ void *buf;
+ int ret;
+
+ log_debug("Kernel preamble at %lx, version major %x, minor %x\n",
+ (ulong)map_to_sysmem(preamble),
+ preamble->header_version_major,
+ preamble->header_version_minor);
+
+ log_debug(" - load_address %lx, bl_addr %lx, bl_size %lx\n",
+ (ulong)preamble->body_load_address,
+ (ulong)preamble->bootloader_address,
+ (ulong)preamble->bootloader_size);
+
+ priv->body_size = preamble->body_signature.data_size;
+ priv->body_load_address = preamble->body_load_address;
+ priv->bootloader_address = preamble->bootloader_address;
+ priv->bootloader_size = preamble->bootloader_size;
+ log_debug("Kernel body at %lx size %lx\n", priv->body_offset,
+ priv->body_size);
+
+ /* Work out how many bytes to read before the bootloader base */
+ before_base = -CMDLINE_OFFSET;
+
+ /* Read the cmdline through to the end of the bootloader */
+ size = priv->bootloader_size + before_base;
+ offset = priv->body_offset +
+ (priv->bootloader_address - priv->body_load_address) +
+ CMDLINE_OFFSET;
+ buf = malloc(size);
+ if (!buf)
+ return log_msg_ret("buf", -ENOMEM);
+
+ ret = cros_read_buf(bflow, buf, size,
+ priv->part_start + (offset >> desc->log2blksz),
+ before_base, uuid);
+ if (ret) {
+ /* Clear this since the buffer is invalid */
+ bflow->x86_setup = NULL;
+ free(buf);
+ return log_msg_ret("pro", ret);
+ }
+ priv->info_buf = buf;
+
+ return 0;
+}
+
+static int cros_read_kernel(struct bootflow *bflow)
+{
+ struct blk_desc *desc = dev_get_uclass_plat(bflow->blk);
+ struct cros_priv *priv = bflow->bootmeth_priv;
+ ulong base, setup;
+ ulong num_blks;
+ void *buf;
+ int ret;
+
+ bflow->size = priv->body_size;
+
+ buf = memalign(SZ_1K, priv->body_size);
+ if (!buf)
+ return log_msg_ret("buf", -ENOMEM);
+
+ /* Check that the header is not smaller than permitted */
+ if (priv->body_offset < PROBE_SIZE)
+ return log_msg_ret("san", EFAULT);
+
+ /* Read kernel body */
+ num_blks = priv->body_size >> desc->log2blksz;
+ log_debug("Reading body to %lx, blk=%s, size=%lx, blocks=%lx\n",
+ (ulong)map_to_sysmem(buf), bflow->blk->name, priv->body_size,
+ num_blks);
+ ret = blk_read(bflow->blk,
+ priv->part_start + (priv->body_offset >> desc->log2blksz),
+ num_blks, buf);
+ if (ret != num_blks)
+ return log_msg_ret("inf", -EIO);
+ base = map_to_sysmem(buf) + priv->bootloader_address -
+ priv->body_load_address;
+ setup = base + X86_SETUP_OFFSET;
+
bflow->buf = buf;
bflow->x86_setup = map_sysmem(setup, 0);
return 0;
}
+static int cros_read_bootflow(struct udevice *dev, struct bootflow *bflow)
+{
+ const struct vb2_kernel_preamble *preamble;
+ struct disk_partition info;
+ struct vb2_keyblock *hdr;
+ const char *uuid = NULL;
+ struct cros_priv *priv;
+ int ret;
+
+ log_debug("starting, part=%x\n", bflow->part);
+
+ /* Check for kernel partitions */
+ ret = scan_part(bflow->blk, bflow->part, &info, &hdr);
+ if (ret) {
+ log_debug("- scan failed: err=%d\n", ret);
+ return log_msg_ret("scan", ret);
+ }
+
+ priv = malloc(sizeof(struct cros_priv));
+ if (!priv) {
+ free(hdr);
+ return log_msg_ret("buf", -ENOMEM);
+ }
+ bflow->bootmeth_priv = priv;
+
+ log_debug("Selected partition %d, header at %lx\n", bflow->part,
+ (ulong)map_to_sysmem(hdr));
+
+ /* Grab a few things from the preamble */
+ preamble = (void *)hdr + hdr->keyblock_size;
+ priv->body_offset = hdr->keyblock_size + preamble->preamble_size;
+ priv->part_start = info.start;
+
+ /* Now read everything we can learn about kernel */
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
+ uuid = info.uuid;
+#endif
+ ret = cros_read_info(bflow, uuid, preamble);
+ preamble = NULL;
+ free(hdr);
+ if (ret) {
+ free(priv->info_buf);
+ free(priv);
+ return log_msg_ret("inf", ret);
+ }
+ bflow->size = priv->body_size;
+ bflow->state = BOOTFLOWST_READY;
+
+ return 0;
+}
+
static int cros_read_file(struct udevice *dev, struct bootflow *bflow,
const char *file_path, ulong addr, ulong *sizep)
{
return -ENOSYS;
}
+#if CONFIG_IS_ENABLED(BOOSTD_FULL)
+static int cros_read_all(struct udevice *dev, struct bootflow *bflow)
+{
+ int ret;
+
+ if (bflow->buf)
+ return log_msg_ret("ld", -EALREADY);
+ ret = cros_read_kernel(bflow);
+ if (ret)
+ return log_msg_ret("rd", ret);
+
+ return 0;
+}
+#endif /* BOOSTD_FULL */
+
static int cros_boot(struct udevice *dev, struct bootflow *bflow)
{
-#ifdef CONFIG_X86
- zboot_start(map_to_sysmem(bflow->buf), bflow->size, 0, 0,
- map_to_sysmem(bflow->x86_setup),
- bflow->cmdline);
-#endif
+ int ret;
+
+ if (!bflow->buf) {
+ ret = cros_read_kernel(bflow);
+ if (ret)
+ return log_msg_ret("rd", ret);
+ }
+
+ if (IS_ENABLED(CONFIG_X86)) {
+ ret = zboot_start(map_to_sysmem(bflow->buf), bflow->size, 0, 0,
+ map_to_sysmem(bflow->x86_setup),
+ bflow->cmdline);
+ } else {
+ ret = bootm_boot_start(map_to_sysmem(bflow->buf),
+ bflow->cmdline);
+ }
- return log_msg_ret("go", -EFAULT);
+ return log_msg_ret("go", ret);
}
static int cros_bootmeth_bind(struct udevice *dev)
@@ -187,6 +448,7 @@
struct bootmeth_uc_plat *plat = dev_get_uclass_plat(dev);
plat->desc = "ChromiumOS boot";
+ plat->flags = BOOTMETHF_ANY_PART;
return 0;
}
@@ -196,6 +458,9 @@
.read_bootflow = cros_read_bootflow,
.read_file = cros_read_file,
.boot = cros_boot,
+#if CONFIG_IS_ENABLED(BOOSTD_FULL)
+ .read_all = cros_read_all,
+#endif /* BOOSTD_FULL */
};
static const struct udevice_id cros_bootmeth_ids[] = {
diff --git a/boot/bootmeth_cros.h b/boot/bootmeth_cros.h
new file mode 100644
index 0000000..8e30385
--- /dev/null
+++ b/boot/bootmeth_cros.h
@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Structures used by the ChromiumOS bootmeth
+ *
+ * See docs at:
+ * https://www.chromium.org/chromium-os/chromiumos-design-docs/verified-boot-data-structures/
+ *
+ * Original code at:
+ * https://chromium.googlesource.com/chromiumos/platform/vboot_reference/+/refs/heads/main/firmware/2lib/include/2struct.h
+ *
+ * Code taken from vboot_reference commit 5b8596ce file 2struct.h
+ *
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __BOOTMETH_CROS_H
+#define __BOOTMETH_CROS_H
+
+/* Signature data (a secure hash, possibly signed) */
+struct vb2_signature {
+ /* Offset of signature data from start of this struct */
+ uint32_t sig_offset;
+ uint32_t reserved0;
+
+ /* Size of signature data in bytes */
+ uint32_t sig_size;
+ uint32_t reserved1;
+
+ /* Size of the data block which was signed in bytes */
+ uint32_t data_size;
+ uint32_t reserved2;
+} __attribute__((packed));
+
+#define EXPECTED_VB2_SIGNATURE_SIZE 24
+
+/* Packed public key data */
+struct vb2_packed_key {
+ /* Offset of key data from start of this struct */
+ uint32_t key_offset;
+ uint32_t reserved0;
+
+ /* Size of key data in bytes (NOT strength of key in bits) */
+ uint32_t key_size;
+ uint32_t reserved1;
+
+ /* Signature algorithm used by the key (enum vb2_crypto_algorithm) */
+ uint32_t algorithm;
+ uint32_t reserved2;
+
+ /* Key version */
+ uint32_t key_version;
+ uint32_t reserved3;
+
+ /* TODO: when redoing this struct, add a text description of the key */
+} __attribute__((packed));
+
+#define EXPECTED_VB2_PACKED_KEY_SIZE 32
+
+#define VB2_KEYBLOCK_MAGIC "CHROMEOS"
+#define VB2_KEYBLOCK_MAGIC_SIZE 8
+
+/*
+ * Keyblock, containing the public key used to sign some other chunk of data.
+ *
+ * This should be followed by:
+ * 1) The data_key key data, pointed to by data_key.key_offset.
+ * 2) The checksum data for (vb2_keyblock + data_key data), pointed to
+ * by keyblock_checksum.sig_offset.
+ * 3) The signature data for (vb2_keyblock + data_key data), pointed to
+ * by keyblock_signature.sig_offset.
+ */
+struct vb2_keyblock {
+ /* Magic number */
+ uint8_t magic[VB2_KEYBLOCK_MAGIC_SIZE];
+
+ /* Version of this header format */
+ uint32_t header_version_major;
+ uint32_t header_version_minor;
+
+ /*
+ * Length of this entire keyblock, including keys, signatures, and
+ * padding, in bytes
+ */
+ uint32_t keyblock_size;
+ uint32_t reserved0;
+
+ /*
+ * Signature for this keyblock (header + data pointed to by data_key)
+ * For use with signed data keys
+ */
+ struct vb2_signature keyblock_signature;
+
+ /*
+ * SHA-512 hash for this keyblock (header + data pointed to by
+ * data_key) For use with unsigned data keys.
+ *
+ * Only supported for kernel keyblocks, not firmware keyblocks.
+ */
+ struct vb2_signature keyblock_hash;
+
+ /* Flags for key (VB2_KEYBLOCK_FLAG_*) */
+ uint32_t keyblock_flags;
+ uint32_t reserved1;
+
+ /* Key to verify the chunk of data */
+ struct vb2_packed_key data_key;
+} __attribute__((packed));
+
+#define EXPECTED_VB2_KEYBLOCK_SIZE 112
+
+/*
+ * Preamble block for kernel, version 2.2
+ *
+ * This should be followed by:
+ * 1) The signature data for the kernel body, pointed to by
+ * body_signature.sig_offset.
+ * 2) The signature data for (vb2_kernel_preamble + body signature data),
+ * pointed to by preamble_signature.sig_offset.
+ * 3) The 16-bit vmlinuz header, which is used for reconstruction of
+ * vmlinuz image.
+ */
+struct vb2_kernel_preamble {
+ /*
+ * Size of this preamble, including keys, signatures, vmlinuz header,
+ * and padding, in bytes
+ */
+ uint32_t preamble_size;
+ uint32_t reserved0;
+
+ /* Signature for this preamble (header + body signature) */
+ struct vb2_signature preamble_signature;
+
+ /* Version of this header format */
+ uint32_t header_version_major;
+ uint32_t header_version_minor;
+
+ /* Kernel version */
+ uint32_t kernel_version;
+ uint32_t reserved1;
+
+ /* Load address for kernel body */
+ uint64_t body_load_address;
+ /* TODO (vboot 2.1): we never used that */
+
+ /* Address of bootloader, after body is loaded at body_load_address */
+ uint64_t bootloader_address;
+ /* TODO (vboot 2.1): should be a 32-bit offset */
+
+ /* Size of bootloader in bytes */
+ uint32_t bootloader_size;
+ uint32_t reserved2;
+
+ /* Signature for the kernel body */
+ struct vb2_signature body_signature;
+
+ /*
+ * TODO (vboot 2.1): fields for kernel offset and size. Right now the
+ * size is implicitly the same as the size of data signed by the body
+ * signature, and the offset is implicitly at the end of the preamble.
+ * But that forces us to pad the preamble to 64KB rather than just
+ * having a tiny preamble and an offset field.
+ */
+
+ /*
+ * Fields added in header version 2.1. You must verify the header
+ * version before reading these fields!
+ */
+
+ /*
+ * Address of 16-bit header for vmlinuz reassembly. Readers should
+ * return 0 for header version < 2.1.
+ */
+ uint64_t vmlinuz_header_address;
+
+ /* Size of 16-bit header for vmlinuz in bytes. Readers should return 0
+ for header version < 2.1 */
+ uint32_t vmlinuz_header_size;
+ uint32_t reserved3;
+
+ /*
+ * Fields added in header version 2.2. You must verify the header
+ * version before reading these fields!
+ */
+
+ /*
+ * Flags; see VB2_KERNEL_PREAMBLE_*. Readers should return 0 for
+ * header version < 2.2. Flags field is currently defined as:
+ * [31:2] - Reserved (for future use)
+ * [1:0] - Kernel image type (0b00 - CrOS,
+ * 0b01 - bootimg,
+ * 0b10 - multiboot)
+ */
+ uint32_t flags;
+} __attribute__((packed));
+
+#endif /* __BOOTMETH_CROS_H */
diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c
index af31fbf..ae936c8 100644
--- a/boot/bootmeth_efi.c
+++ b/boot/bootmeth_efi.c
@@ -21,6 +21,7 @@
#include <mmc.h>
#include <net.h>
#include <pxe_utils.h>
+#include <linux/sizes.h>
#define EFI_DIRNAME "efi/boot/"
@@ -94,6 +95,20 @@
return 0;
}
+/**
+ * bootmeth_uses_network() - check if the media device is Ethernet
+ *
+ * @bflow: Bootflow to check
+ * Returns: true if the media device is Ethernet, else false
+ */
+static bool bootmeth_uses_network(struct bootflow *bflow)
+{
+ const struct udevice *media = dev_get_parent(bflow->dev);
+
+ return IS_ENABLED(CONFIG_CMD_DHCP) &&
+ device_get_uclass_id(media) == UCLASS_ETH;
+}
+
static void set_efi_bootdev(struct blk_desc *desc, struct bootflow *bflow)
{
const struct udevice *media_dev;
@@ -129,13 +144,24 @@
efi_set_bootdev(dev_name, devnum_str, bflow->fname, bflow->buf, size);
}
-static int efiload_read_file(struct blk_desc *desc, struct bootflow *bflow)
+static int efiload_read_file(struct bootflow *bflow, ulong addr)
{
+ struct blk_desc *desc = NULL;
+ loff_t bytes_read;
int ret;
- ret = bootmeth_alloc_file(bflow, 0x2000000, 0x10000);
+ if (bflow->blk)
+ desc = dev_get_uclass_plat(bflow->blk);
+ ret = bootmeth_setup_fs(bflow, desc);
+ if (ret)
+ return log_msg_ret("set", ret);
+
+ ret = fs_read(bflow->fname, addr, 0, bflow->size, &bytes_read);
if (ret)
return log_msg_ret("read", ret);
+ bflow->buf = map_sysmem(addr, bflow->size);
+
+ set_efi_bootdev(desc, bflow);
return 0;
}
@@ -209,7 +235,18 @@
return 0;
}
-static int distro_efi_read_bootflow_file(struct udevice *dev,
+/*
+ * distro_efi_try_bootflow_files() - Check that files are present
+ *
+ * This reads any FDT file and checks whether the bootflow file is present, for
+ * later reading. We avoid reading the bootflow now, since it is likely large,
+ * it may take a long time and we want to avoid needing to allocate memory for
+ * it
+ *
+ * @dev: bootmeth device to use
+ * @bflow: bootflow to update
+ */
+static int distro_efi_try_bootflow_files(struct udevice *dev,
struct bootflow *bflow)
{
struct blk_desc *desc = NULL;
@@ -233,9 +270,8 @@
if (ret)
return log_msg_ret("try", ret);
- ret = efiload_read_file(desc, bflow);
- if (ret)
- return log_msg_ret("read", ret);
+ /* Since we can access the file, let's call it ready */
+ bflow->state = BOOTFLOWST_READY;
fdt_addr = env_get_hex("fdt_addr_r", 0);
@@ -246,9 +282,12 @@
ret = distro_efi_get_fdt_name(fname, sizeof(fname), seq);
if (ret == -EALREADY)
bflow->flags = BOOTFLOWF_USE_PRIOR_FDT;
- if (!ret)
+ if (!ret) {
+ /* Limit FDT files to 4MB */
+ size = SZ_4M;
ret = bootmeth_common_read_file(dev, bflow, fname,
fdt_addr, &size);
+ }
}
if (*fname) {
@@ -354,17 +393,15 @@
static int distro_efi_read_bootflow(struct udevice *dev, struct bootflow *bflow)
{
- const struct udevice *media = dev_get_parent(bflow->dev);
int ret;
- if (IS_ENABLED(CONFIG_CMD_DHCP) &&
- device_get_uclass_id(media) == UCLASS_ETH) {
+ if (bootmeth_uses_network(bflow)) {
/* we only support reading from one device, so ignore 'dev' */
ret = distro_efi_read_bootflow_net(bflow);
if (ret)
return log_msg_ret("net", ret);
} else {
- ret = distro_efi_read_bootflow_file(dev, bflow);
+ ret = distro_efi_try_bootflow_files(dev, bflow);
if (ret)
return log_msg_ret("blk", ret);
}
@@ -372,21 +409,17 @@
return 0;
}
-int distro_efi_boot(struct udevice *dev, struct bootflow *bflow)
+static int distro_efi_boot(struct udevice *dev, struct bootflow *bflow)
{
ulong kernel, fdt;
char cmd[50];
-
- /* A non-zero buffer indicates the kernel is there */
- if (bflow->buf) {
- /* Set the EFI bootdev again, since reading an FDT loses it! */
- if (bflow->blk) {
- struct blk_desc *desc = dev_get_uclass_plat(bflow->blk);
-
- set_efi_bootdev(desc, bflow);
- }
+ int ret;
- kernel = (ulong)map_to_sysmem(bflow->buf);
+ kernel = env_get_hex("kernel_addr_r", 0);
+ if (!bootmeth_uses_network(bflow)) {
+ ret = efiload_read_file(bflow, kernel);
+ if (ret)
+ return log_msg_ret("read", ret);
/*
* use the provided device tree if available, else fall back to
@@ -405,7 +438,6 @@
* But this is the same behaviour for distro boot, so it can be
* fixed here.
*/
- kernel = env_get_hex("kernel_addr_r", 0);
fdt = env_get_hex("fdt_addr_r", 0);
}
diff --git a/boot/bootmeth_pxe.c b/boot/bootmeth_pxe.c
index ce986bd..8d489a1 100644
--- a/boot/bootmeth_pxe.c
+++ b/boot/bootmeth_pxe.c
@@ -31,6 +31,9 @@
int ret;
addr = simple_strtoul(file_addr, NULL, 16);
+
+ /* Allow up to 1GB */
+ *sizep = 1 << 30;
ret = bootmeth_read_file(info->dev, info->bflow, file_path, addr,
sizep);
if (ret)
diff --git a/boot/cedit.c b/boot/cedit.c
index ee24658..73645f7 100644
--- a/boot/cedit.c
+++ b/boot/cedit.c
@@ -6,15 +6,50 @@
* Written by Simon Glass <sjg@chromium.org>
*/
+#define LOG_CATEGORY LOGC_EXPO
+
#include <common.h>
+#include <abuf.h>
+#include <cedit.h>
#include <cli.h>
#include <dm.h>
+#include <env.h>
#include <expo.h>
+#include <malloc.h>
#include <menu.h>
+#include <rtc.h>
#include <video.h>
#include <linux/delay.h>
#include "scene_internal.h"
+enum {
+ CMOS_MAX_BITS = 2048,
+ CMOS_MAX_BYTES = CMOS_MAX_BITS / 8,
+};
+
+#define CMOS_BYTE(bit) ((bit) / 8)
+#define CMOS_BIT(bit) ((bit) % 8)
+
+/**
+ * struct cedit_iter_priv - private data for cedit operations
+ *
+ * @buf: Buffer to use when writing settings to the devicetree
+ * @node: Node to read from when reading settings from devicetree
+ * @verbose: true to show writing to environment variables
+ * @mask: Mask bits for the CMOS RAM. If a bit is set the byte containing it
+ * will be written
+ * @value: Value bits for CMOS RAM. This is the actual value written
+ * @dev: RTC device to write to
+ */
+struct cedit_iter_priv {
+ struct abuf *buf;
+ ofnode node;
+ bool verbose;
+ u8 *mask;
+ u8 *value;
+ struct udevice *dev;
+};
+
int cedit_arange(struct expo *exp, struct video_priv *vpriv, uint scene_id)
{
struct scene_obj_txt *txt;
@@ -46,18 +81,15 @@
return 0;
}
-int cedit_run(struct expo *exp)
+int cedit_prepare(struct expo *exp, struct video_priv **vid_privp,
+ struct scene **scnp)
{
- struct cli_ch_state s_cch, *cch = &s_cch;
struct video_priv *vid_priv;
- uint scene_id;
struct udevice *dev;
struct scene *scn;
- bool done;
+ uint scene_id;
int ret;
- cli_ch_init(cch);
-
/* For now we only support a video console */
ret = uclass_first_device_err(UCLASS_VIDEO, &dev);
if (ret)
@@ -92,6 +124,27 @@
if (ret)
return log_msg_ret("dim", ret);
+ *vid_privp = vid_priv;
+ *scnp = scn;
+
+ return scene_id;
+}
+
+int cedit_run(struct expo *exp)
+{
+ struct cli_ch_state s_cch, *cch = &s_cch;
+ struct video_priv *vid_priv;
+ uint scene_id;
+ struct scene *scn;
+ bool done;
+ int ret;
+
+ cli_ch_init(cch);
+ ret = cedit_prepare(exp, &vid_priv, &scn);
+ if (ret < 0)
+ return log_msg_ret("prep", ret);
+ scene_id = ret;
+
done = false;
do {
struct expo_action act;
@@ -161,3 +214,507 @@
return 0;
}
+
+static int check_space(int ret, struct abuf *buf)
+{
+ if (ret == -FDT_ERR_NOSPACE) {
+ if (!abuf_realloc_inc(buf, CEDIT_SIZE_INC))
+ return log_msg_ret("spc", -ENOMEM);
+ ret = fdt_resize(abuf_data(buf), abuf_data(buf),
+ abuf_size(buf));
+ if (ret)
+ return log_msg_ret("res", -EFAULT);
+ }
+
+ return 0;
+}
+
+static int get_cur_menuitem_text(const struct scene_obj_menu *menu,
+ const char **strp)
+{
+ struct scene *scn = menu->obj.scene;
+ const struct scene_menitem *mi;
+ const struct scene_obj_txt *txt;
+ const char *str;
+
+ mi = scene_menuitem_find(menu, menu->cur_item_id);
+ if (!mi)
+ return log_msg_ret("mi", -ENOENT);
+
+ txt = scene_obj_find(scn, mi->label_id, SCENEOBJT_TEXT);
+ if (!txt)
+ return log_msg_ret("txt", -ENOENT);
+
+ str = expo_get_str(scn->expo, txt->str_id);
+ if (!str)
+ return log_msg_ret("str", -ENOENT);
+ *strp = str;
+
+ return 0;
+}
+
+static int h_write_settings(struct scene_obj *obj, void *vpriv)
+{
+ struct cedit_iter_priv *priv = vpriv;
+ struct abuf *buf = priv->buf;
+
+ switch (obj->type) {
+ case SCENEOBJT_NONE:
+ case SCENEOBJT_IMAGE:
+ case SCENEOBJT_TEXT:
+ break;
+ case SCENEOBJT_MENU: {
+ const struct scene_obj_menu *menu;
+ const char *str;
+ char name[80];
+ int ret, i;
+
+ menu = (struct scene_obj_menu *)obj;
+ ret = -EAGAIN;
+ for (i = 0; ret && i < 2; i++) {
+ ret = fdt_property_u32(abuf_data(buf), obj->name,
+ menu->cur_item_id);
+ if (!i) {
+ ret = check_space(ret, buf);
+ if (ret)
+ return log_msg_ret("res", -ENOMEM);
+ }
+ }
+ /* this should not happen */
+ if (ret)
+ return log_msg_ret("wrt", -EFAULT);
+
+ ret = get_cur_menuitem_text(menu, &str);
+ if (ret)
+ return log_msg_ret("mis", ret);
+
+ snprintf(name, sizeof(name), "%s-str", obj->name);
+ ret = -EAGAIN;
+ for (i = 0; ret && i < 2; i++) {
+ ret = fdt_property_string(abuf_data(buf), name, str);
+ if (!i) {
+ ret = check_space(ret, buf);
+ if (ret)
+ return log_msg_ret("rs2", -ENOMEM);
+ }
+ }
+
+ /* this should not happen */
+ if (ret)
+ return log_msg_ret("wr2", -EFAULT);
+
+ break;
+ }
+ }
+
+ return 0;
+}
+
+int cedit_write_settings(struct expo *exp, struct abuf *buf)
+{
+ struct cedit_iter_priv priv;
+ void *fdt;
+ int ret;
+
+ abuf_init(buf);
+ if (!abuf_realloc(buf, CEDIT_SIZE_INC))
+ return log_msg_ret("buf", -ENOMEM);
+
+ fdt = abuf_data(buf);
+ ret = fdt_create(fdt, abuf_size(buf));
+ if (!ret)
+ ret = fdt_finish_reservemap(fdt);
+ if (!ret)
+ ret = fdt_begin_node(fdt, "");
+ if (!ret)
+ ret = fdt_begin_node(fdt, CEDIT_NODE_NAME);
+ if (ret) {
+ log_debug("Failed to start FDT (err=%d)\n", ret);
+ return log_msg_ret("sta", -EINVAL);
+ }
+
+ /* write out the items */
+ priv.buf = buf;
+ ret = expo_iter_scene_objs(exp, h_write_settings, &priv);
+ if (ret) {
+ log_debug("Failed to write settings (err=%d)\n", ret);
+ return log_msg_ret("set", ret);
+ }
+
+ ret = fdt_end_node(fdt);
+ if (!ret)
+ ret = fdt_end_node(fdt);
+ if (!ret)
+ ret = fdt_finish(fdt);
+ if (ret) {
+ log_debug("Failed to finish FDT (err=%d)\n", ret);
+ return log_msg_ret("fin", -EINVAL);
+ }
+
+ return 0;
+}
+
+static int h_read_settings(struct scene_obj *obj, void *vpriv)
+{
+ struct cedit_iter_priv *priv = vpriv;
+ ofnode node = priv->node;
+
+ switch (obj->type) {
+ case SCENEOBJT_NONE:
+ case SCENEOBJT_IMAGE:
+ case SCENEOBJT_TEXT:
+ break;
+ case SCENEOBJT_MENU: {
+ struct scene_obj_menu *menu;
+ uint val;
+
+ if (ofnode_read_u32(node, obj->name, &val))
+ return log_msg_ret("rd", -ENOENT);
+ menu = (struct scene_obj_menu *)obj;
+ menu->cur_item_id = val;
+
+ break;
+ }
+ }
+
+ return 0;
+}
+
+int cedit_read_settings(struct expo *exp, oftree tree)
+{
+ struct cedit_iter_priv priv;
+ ofnode root, node;
+ int ret;
+
+ root = oftree_root(tree);
+ if (!ofnode_valid(root))
+ return log_msg_ret("roo", -ENOENT);
+ node = ofnode_find_subnode(root, CEDIT_NODE_NAME);
+ if (!ofnode_valid(node))
+ return log_msg_ret("pat", -ENOENT);
+
+ /* read in the items */
+ priv.node = node;
+ ret = expo_iter_scene_objs(exp, h_read_settings, &priv);
+ if (ret) {
+ log_debug("Failed to read settings (err=%d)\n", ret);
+ return log_msg_ret("set", ret);
+ }
+
+ return 0;
+}
+
+static int h_write_settings_env(struct scene_obj *obj, void *vpriv)
+{
+ const struct scene_obj_menu *menu;
+ struct cedit_iter_priv *priv = vpriv;
+ char name[80], var[60];
+ const char *str;
+ int val, ret;
+
+ if (obj->type != SCENEOBJT_MENU)
+ return 0;
+
+ menu = (struct scene_obj_menu *)obj;
+ val = menu->cur_item_id;
+ snprintf(var, sizeof(var), "c.%s", obj->name);
+
+ if (priv->verbose)
+ printf("%s=%d\n", var, val);
+
+ ret = env_set_ulong(var, val);
+ if (ret)
+ return log_msg_ret("set", ret);
+
+ ret = get_cur_menuitem_text(menu, &str);
+ if (ret)
+ return log_msg_ret("mis", ret);
+
+ snprintf(name, sizeof(name), "c.%s-str", obj->name);
+ if (priv->verbose)
+ printf("%s=%s\n", name, str);
+
+ ret = env_set(name, str);
+ if (ret)
+ return log_msg_ret("st2", ret);
+
+ return 0;
+}
+
+int cedit_write_settings_env(struct expo *exp, bool verbose)
+{
+ struct cedit_iter_priv priv;
+ int ret;
+
+ /* write out the items */
+ priv.verbose = verbose;
+ ret = expo_iter_scene_objs(exp, h_write_settings_env, &priv);
+ if (ret) {
+ log_debug("Failed to write settings to env (err=%d)\n", ret);
+ return log_msg_ret("set", ret);
+ }
+
+ return 0;
+}
+
+static int h_read_settings_env(struct scene_obj *obj, void *vpriv)
+{
+ struct cedit_iter_priv *priv = vpriv;
+ struct scene_obj_menu *menu;
+ char var[60];
+ int val;
+
+ if (obj->type != SCENEOBJT_MENU)
+ return 0;
+
+ menu = (struct scene_obj_menu *)obj;
+ val = menu->cur_item_id;
+ snprintf(var, sizeof(var), "c.%s", obj->name);
+
+ val = env_get_ulong(var, 10, 0);
+ if (priv->verbose)
+ printf("%s=%d\n", var, val);
+ if (!val)
+ return log_msg_ret("get", -ENOENT);
+
+ /*
+ * note that no validation is done here, to make sure the ID is valid
+ * and actually points to a menu item
+ */
+ menu->cur_item_id = val;
+
+ return 0;
+}
+
+int cedit_read_settings_env(struct expo *exp, bool verbose)
+{
+ struct cedit_iter_priv priv;
+ int ret;
+
+ /* write out the items */
+ priv.verbose = verbose;
+ ret = expo_iter_scene_objs(exp, h_read_settings_env, &priv);
+ if (ret) {
+ log_debug("Failed to read settings from env (err=%d)\n", ret);
+ return log_msg_ret("set", ret);
+ }
+
+ return 0;
+}
+
+/**
+ * get_cur_menuitem_seq() - Get the sequence number of a menu's current item
+ *
+ * Enumerates the items of a menu (0, 1, 2) and returns the sequence number of
+ * the currently selected item. If the first item is selected, this returns 0;
+ * if the second, 1; etc.
+ *
+ * @menu: Menu to check
+ * Return: Sequence number on success, else -ve error value
+ */
+static int get_cur_menuitem_seq(const struct scene_obj_menu *menu)
+{
+ const struct scene_menitem *mi;
+ int seq, found;
+
+ seq = 0;
+ found = -1;
+ list_for_each_entry(mi, &menu->item_head, sibling) {
+ if (mi->id == menu->cur_item_id) {
+ found = seq;
+ break;
+ }
+ seq++;
+ }
+
+ if (found == -1)
+ return log_msg_ret("nf", -ENOENT);
+
+ return found;
+}
+
+static int h_write_settings_cmos(struct scene_obj *obj, void *vpriv)
+{
+ const struct scene_obj_menu *menu;
+ struct cedit_iter_priv *priv = vpriv;
+ int val, ret;
+ uint i, seq;
+
+ if (obj->type != SCENEOBJT_MENU)
+ return 0;
+
+ menu = (struct scene_obj_menu *)obj;
+ val = menu->cur_item_id;
+
+ ret = get_cur_menuitem_seq(menu);
+ if (ret < 0)
+ return log_msg_ret("cur", ret);
+ seq = ret;
+ log_debug("%s: seq=%d\n", menu->obj.name, seq);
+
+ /* figure out where to place this item */
+ if (!obj->bit_length)
+ return log_msg_ret("len", -EINVAL);
+ if (obj->start_bit + obj->bit_length > CMOS_MAX_BITS)
+ return log_msg_ret("bit", -E2BIG);
+
+ for (i = 0; i < obj->bit_length; i++, seq >>= 1) {
+ uint bitnum = obj->start_bit + i;
+
+ priv->mask[CMOS_BYTE(bitnum)] |= 1 << CMOS_BIT(bitnum);
+ if (seq & 1)
+ priv->value[CMOS_BYTE(bitnum)] |= BIT(CMOS_BIT(bitnum));
+ log_debug("bit %x %x %x\n", bitnum,
+ priv->mask[CMOS_BYTE(bitnum)],
+ priv->value[CMOS_BYTE(bitnum)]);
+ }
+
+ return 0;
+}
+
+int cedit_write_settings_cmos(struct expo *exp, struct udevice *dev,
+ bool verbose)
+{
+ struct cedit_iter_priv priv;
+ int ret, i, count, first, last;
+
+ /* write out the items */
+ priv.mask = calloc(1, CMOS_MAX_BYTES);
+ if (!priv.mask)
+ return log_msg_ret("mas", -ENOMEM);
+ priv.value = calloc(1, CMOS_MAX_BYTES);
+ if (!priv.value) {
+ free(priv.mask);
+ return log_msg_ret("val", -ENOMEM);
+ }
+
+ ret = expo_iter_scene_objs(exp, h_write_settings_cmos, &priv);
+ if (ret) {
+ log_debug("Failed to write CMOS (err=%d)\n", ret);
+ ret = log_msg_ret("set", ret);
+ goto done;
+ }
+
+ /* write the data to the RTC */
+ first = CMOS_MAX_BYTES;
+ last = -1;
+ for (i = 0, count = 0; i < CMOS_MAX_BYTES; i++) {
+ if (priv.mask[i]) {
+ log_debug("Write byte %x: %x\n", i, priv.value[i]);
+ ret = rtc_write8(dev, i, priv.value[i]);
+ if (ret) {
+ ret = log_msg_ret("wri", ret);
+ goto done;
+ }
+ count++;
+ first = min(first, i);
+ last = max(last, i);
+ }
+ }
+ if (verbose) {
+ printf("Write %d bytes from offset %x to %x\n", count, first,
+ last);
+ }
+
+done:
+ free(priv.mask);
+ free(priv.value);
+ return ret;
+}
+
+static int h_read_settings_cmos(struct scene_obj *obj, void *vpriv)
+{
+ struct cedit_iter_priv *priv = vpriv;
+ const struct scene_menitem *mi;
+ struct scene_obj_menu *menu;
+ int val, ret;
+ uint i;
+
+ if (obj->type != SCENEOBJT_MENU)
+ return 0;
+
+ menu = (struct scene_obj_menu *)obj;
+
+ /* figure out where to place this item */
+ if (!obj->bit_length)
+ return log_msg_ret("len", -EINVAL);
+ if (obj->start_bit + obj->bit_length > CMOS_MAX_BITS)
+ return log_msg_ret("bit", -E2BIG);
+
+ val = 0;
+ for (i = 0; i < obj->bit_length; i++) {
+ uint bitnum = obj->start_bit + i;
+ uint offset = CMOS_BYTE(bitnum);
+
+ /* read the byte if not already read */
+ if (!priv->mask[offset]) {
+ ret = rtc_read8(priv->dev, offset);
+ if (ret < 0)
+ return log_msg_ret("rea", ret);
+ priv->value[offset] = ret;
+
+ /* mark it as read */
+ priv->mask[offset] = 0xff;
+ }
+
+ if (priv->value[offset] & BIT(CMOS_BIT(bitnum)))
+ val |= BIT(i);
+ log_debug("bit %x %x\n", bitnum, val);
+ }
+
+ /* update the current item */
+ mi = scene_menuitem_find_seq(menu, val);
+ if (!mi)
+ return log_msg_ret("seq", -ENOENT);
+
+ menu->cur_item_id = mi->id;
+ log_debug("Update menu %d cur_item_id %d\n", menu->obj.id, mi->id);
+
+ return 0;
+}
+
+int cedit_read_settings_cmos(struct expo *exp, struct udevice *dev,
+ bool verbose)
+{
+ struct cedit_iter_priv priv;
+ int ret, i, count, first, last;
+
+ /* read in the items */
+ priv.mask = calloc(1, CMOS_MAX_BYTES);
+ if (!priv.mask)
+ return log_msg_ret("mas", -ENOMEM);
+ priv.value = calloc(1, CMOS_MAX_BYTES);
+ if (!priv.value) {
+ free(priv.mask);
+ return log_msg_ret("val", -ENOMEM);
+ }
+ priv.dev = dev;
+
+ ret = expo_iter_scene_objs(exp, h_read_settings_cmos, &priv);
+ if (ret) {
+ log_debug("Failed to read CMOS (err=%d)\n", ret);
+ ret = log_msg_ret("set", ret);
+ goto done;
+ }
+
+ /* read the data to the RTC */
+ first = CMOS_MAX_BYTES;
+ last = -1;
+ for (i = 0, count = 0; i < CMOS_MAX_BYTES; i++) {
+ if (priv.mask[i]) {
+ log_debug("Read byte %x: %x\n", i, priv.value[i]);
+ count++;
+ first = min(first, i);
+ last = max(last, i);
+ }
+ }
+ if (verbose) {
+ printf("Read %d bytes from offset %x to %x\n", count, first,
+ last);
+ }
+
+done:
+ free(priv.mask);
+ free(priv.value);
+ return ret;
+}
diff --git a/boot/expo.c b/boot/expo.c
index db837f7..139d684 100644
--- a/boot/expo.c
+++ b/boot/expo.c
@@ -266,3 +266,18 @@
return 0;
}
+
+int expo_iter_scene_objs(struct expo *exp, expo_scene_obj_iterator iter,
+ void *priv)
+{
+ struct scene *scn;
+ int ret;
+
+ list_for_each_entry(scn, &exp->scene_head, sibling) {
+ ret = scene_iter_objs(scn, iter, priv);
+ if (ret)
+ return log_msg_ret("wr", ret);
+ }
+
+ return 0;
+}
diff --git a/boot/expo_build.c b/boot/expo_build.c
index 22f62eb..bb33cc2 100644
--- a/boot/expo_build.c
+++ b/boot/expo_build.c
@@ -214,22 +214,21 @@
* @info: Build information
* @node: Node containing the menu description
* @scn: Scene to add the menu to
+ * @id: ID for the menu
+ * @objp: Returns the object pointer
* Returns: 0 if OK, -ENOMEM if out of memory, -EINVAL if there is a format
* error, -ENOENT if there is a references to a non-existent string
*/
-static int menu_build(struct build_info *info, ofnode node, struct scene *scn)
+static int menu_build(struct build_info *info, ofnode node, struct scene *scn,
+ uint id, struct scene_obj **objp)
{
struct scene_obj_menu *menu;
uint title_id, menu_id;
const u32 *item_ids;
int ret, size, i;
const char *name;
- u32 id;
name = ofnode_get_name(node);
- ret = ofnode_read_u32(node, "id", &id);
- if (ret)
- return log_msg_ret("id", -EINVAL);
ret = scene_menu(scn, name, id, &menu);
if (ret < 0)
@@ -275,12 +274,13 @@
if (ret < 0)
return log_msg_ret("mi", ret);
}
+ *objp = &menu->obj;
return 0;
}
/**
- * menu_build() - Build an expo object and add it to a scene
+ * obj_build() - Build an expo object and add it to a scene
*
* See doc/developer/expo.rst for a description of the format
*
@@ -292,8 +292,9 @@
*/
static int obj_build(struct build_info *info, ofnode node, struct scene *scn)
{
+ struct scene_obj *obj;
const char *type;
- u32 id;
+ u32 id, val;
int ret;
log_debug("- object %s\n", ofnode_get_name(node));
@@ -306,12 +307,17 @@
return log_msg_ret("typ", -EINVAL);
if (!strcmp("menu", type))
- ret = menu_build(info, node, scn);
+ ret = menu_build(info, node, scn, id, &obj);
else
ret = -EINVAL;
if (ret)
return log_msg_ret("bld", ret);
+ if (!ofnode_read_u32(node, "start-bit", &val))
+ obj->start_bit = val;
+ if (!ofnode_read_u32(node, "bit-length", &val))
+ obj->bit_length = val;
+
return 0;
}
diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c
index d13c47d..ac1414a 100644
--- a/boot/pxe_utils.c
+++ b/boot/pxe_utils.c
@@ -702,8 +702,8 @@
}
}
- if (label->kaslrseed)
- label_boot_kaslrseed();
+ if (label->kaslrseed)
+ label_boot_kaslrseed();
#ifdef CONFIG_OF_LIBFDT_OVERLAY
if (label->fdtoverlays)
diff --git a/boot/scene.c b/boot/scene.c
index e523333..6c52948 100644
--- a/boot/scene.c
+++ b/boot/scene.c
@@ -79,7 +79,7 @@
return count;
}
-void *scene_obj_find(struct scene *scn, uint id, enum scene_obj_t type)
+void *scene_obj_find(const struct scene *scn, uint id, enum scene_obj_t type)
{
struct scene_obj *obj;
@@ -681,3 +681,19 @@
return 0;
}
+
+int scene_iter_objs(struct scene *scn, expo_scene_obj_iterator iter,
+ void *priv)
+{
+ struct scene_obj *obj;
+
+ list_for_each_entry(obj, &scn->obj_head, sibling) {
+ int ret;
+
+ ret = iter(obj, priv);
+ if (ret)
+ return log_msg_ret("itr", ret);
+ }
+
+ return 0;
+}
diff --git a/boot/scene_internal.h b/boot/scene_internal.h
index fb1ea55..695a907 100644
--- a/boot/scene_internal.h
+++ b/boot/scene_internal.h
@@ -9,6 +9,8 @@
#ifndef __SCENE_INTERNAL_H
#define __SCENE_INTERNAL_H
+typedef int (*expo_scene_obj_iterator)(struct scene_obj *obj, void *priv);
+
/**
* expo_lookup_scene_id() - Look up a scene ID
*
@@ -38,7 +40,7 @@
* @type: Type of the object, or SCENEOBJT_NONE to match any type
* Returns: Object found, or NULL if not found
*/
-void *scene_obj_find(struct scene *scn, uint id, enum scene_obj_t type);
+void *scene_obj_find(const struct scene *scn, uint id, enum scene_obj_t type);
/**
* scene_obj_find_by_name() - Find an object in a scene by name
@@ -198,4 +200,50 @@
*/
int scene_menu_calc_dims(struct scene_obj_menu *menu);
+/**
+ * scene_iter_objs() - Iterate through all scene objects
+ *
+ * @scn: Scene to process
+ * @iter: Iterator to call on each object
+ * @priv: Private data to pass to the iterator, in addition to the object
+ * Return: 0 if OK, -ve on error
+ */
+int scene_iter_objs(struct scene *scn, expo_scene_obj_iterator iter,
+ void *priv);
+
+/**
+ * expo_iter_scene_objects() - Iterate through all scene objects
+ *
+ * @exp: Expo to process
+ * @iter: Iterator to call on each object
+ * @priv: Private data to pass to the iterator, in addition to the object
+ * Return: 0 if OK, -ve on error
+ */
+int expo_iter_scene_objs(struct expo *exp, expo_scene_obj_iterator iter,
+ void *priv);
+
+/**
+ * scene_menuitem_find() - Find the menu item for an ID
+ *
+ * Looks up the menu to find the item with the given ID
+ *
+ * @menu: Menu to check
+ * @id: ID to look for
+ * Return: Menu item, or NULL if not found
+ */
+struct scene_menitem *scene_menuitem_find(const struct scene_obj_menu *menu,
+ int id);
+
+/**
+ * scene_menuitem_find_seq() - Find the menu item at a sequential position
+ *
+ * This numbers the items from 0 and returns the seq'th one
+ *
+ * @menu: Menu to check
+ * @seq: Sequence number to look for
+ * Return: menu item if found, else NULL
+ */
+struct scene_menitem *scene_menuitem_find_seq(const struct scene_obj_menu *menu,
+ uint seq);
+
#endif /* __SCENE_INTERNAL_H */
diff --git a/boot/scene_menu.c b/boot/scene_menu.c
index 8a355f8..e0dcd0a 100644
--- a/boot/scene_menu.c
+++ b/boot/scene_menu.c
@@ -33,8 +33,8 @@
scene_menuitem_destroy(item);
}
-static struct scene_menitem *scene_menuitem_find(struct scene_obj_menu *menu,
- int id)
+struct scene_menitem *scene_menuitem_find(const struct scene_obj_menu *menu,
+ int id)
{
struct scene_menitem *item;
@@ -46,6 +46,22 @@
return NULL;
}
+struct scene_menitem *scene_menuitem_find_seq(const struct scene_obj_menu *menu,
+ uint seq)
+{
+ struct scene_menitem *item;
+ uint i;
+
+ i = 0;
+ list_for_each_entry(item, &menu->item_head, sibling) {
+ if (i == seq)
+ return item;
+ i++;
+ }
+
+ return NULL;
+}
+
/**
* update_pointers() - Update the pointer object and handle highlights
*
@@ -416,7 +432,7 @@
if (!scene_obj_find(scn, label_id, SCENEOBJT_TEXT))
return log_msg_ret("txt", -EINVAL);
- item = calloc(1, sizeof(struct scene_obj_menu));
+ item = calloc(1, sizeof(struct scene_menitem));
if (!item)
return log_msg_ret("item", -ENOMEM);
item->name = strdup(name);
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 2d6e5f9..3f14923 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -517,7 +517,7 @@
config CMD_SPL_NAND_OFS
hex "Offset of OS args or dtb for Falcon-mode NAND boot"
depends on CMD_SPL && (TPL_NAND_SUPPORT || SPL_NAND_SUPPORT)
- default 0
+ default 0x0
help
This provides the offset of the command line arguments for Linux
when booting from NAND in Falcon mode. See doc/README.falcon
@@ -527,7 +527,7 @@
config CMD_SPL_NOR_OFS
hex "Offset of OS args or dtb for Falcon-mode NOR boot"
depends on CMD_SPL && SPL_NOR_SUPPORT
- default 0
+ default 0x0
help
This provides the offset of the command line arguments or dtb for
Linux when booting from NOR in Falcon mode.
@@ -952,6 +952,16 @@
menu "Device access commands"
+config CMD_ARMFFA
+ bool "Arm FF-A test command"
+ depends on ARM_FFA_TRANSPORT
+ help
+ Provides a test command for the FF-A support
+ supported options:
+ - Listing the partition(s) info
+ - Sending a data pattern to the specified partition
+ - Displaying the arm_ffa device info
+
config CMD_ARMFLASH
#depends on FLASH_CFI_DRIVER
bool "armflash"
@@ -986,6 +996,7 @@
config CMD_BIND
bool "bind/unbind - Bind or unbind a device to/from a driver"
depends on DM
+ default y if USB_ETHER
help
Bind or unbind a device to/from a driver from the command line.
This is useful in situations where a device may be handled by several
@@ -1513,7 +1524,7 @@
config DEFAULT_SPI_MODE
hex "default spi mode used by sspi command (see include/spi.h)"
depends on CMD_SPI
- default 0
+ default 0x0
config CMD_TEMPERATURE
bool "temperature - display the temperature from thermal sensors"
@@ -1804,7 +1815,7 @@
depends on BOOTP_PXE
default 0x16 if ARM64
default 0x15 if ARM
- default 0 if X86
+ default 0x0 if X86
config BOOTP_VCI_STRING
string
diff --git a/cmd/Makefile b/cmd/Makefile
index 9f8c0b0..9bebf32 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -12,6 +12,7 @@
obj-y += version.o
# command
+obj-$(CONFIG_CMD_ARMFFA) += armffa.o
obj-$(CONFIG_CMD_2048) += 2048.o
obj-$(CONFIG_CMD_ACPI) += acpi.o
obj-$(CONFIG_CMD_ADDRMAP) += addrmap.o
diff --git a/cmd/armffa.c b/cmd/armffa.c
new file mode 100644
index 0000000..7e6eafc
--- /dev/null
+++ b/cmd/armffa.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+#include <common.h>
+#include <arm_ffa.h>
+#include <command.h>
+#include <dm.h>
+#include <mapmem.h>
+#include <stdlib.h>
+#include <asm/io.h>
+
+/* Select the right physical address formatting according to the platform */
+#ifdef CONFIG_PHYS_64BIT
+#define PhysAddrLength "ll"
+#else
+#define PhysAddrLength ""
+#endif
+#define PHYS_ADDR_LN "%" PhysAddrLength "x"
+
+/**
+ * ffa_get_dev() - Return the FF-A device
+ * @devp: pointer to the FF-A device
+ *
+ * Search for the FF-A device.
+ *
+ * Return:
+ * 0 on success. Otherwise, failure
+ */
+static int ffa_get_dev(struct udevice **devp)
+{
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_FFA, devp);
+ if (ret) {
+ log_err("Cannot find FF-A bus device\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * do_ffa_getpart() - implementation of the getpart subcommand
+ * @cmdtp: Command Table
+ * @flag: flags
+ * @argc: number of arguments
+ * @argv: arguments
+ *
+ * Query a secure partition information. The secure partition UUID is provided
+ * as an argument. The function uses the arm_ffa driver
+ * partition_info_get operation which implements FFA_PARTITION_INFO_GET
+ * ABI to retrieve the data. The input UUID string is expected to be in big
+ * endian format.
+ *
+ * Return:
+ *
+ * CMD_RET_SUCCESS: on success, otherwise failure
+ */
+static int do_ffa_getpart(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ u32 count = 0;
+ int ret;
+ struct ffa_partition_desc *descs;
+ u32 i;
+ struct udevice *dev;
+
+ if (argc != 2) {
+ log_err("Missing argument\n");
+ return CMD_RET_USAGE;
+ }
+
+ ret = ffa_get_dev(&dev);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ /* Ask the driver to fill the buffer with the SPs info */
+
+ ret = ffa_partition_info_get(dev, argv[1], &count, &descs);
+ if (ret) {
+ log_err("Failure in querying partition(s) info (error code: %d)\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ /* SPs found , show the partition information */
+ for (i = 0; i < count ; i++) {
+ log_info("Partition: id = %x , exec_ctxt %x , properties %x\n",
+ descs[i].info.id,
+ descs[i].info.exec_ctxt,
+ descs[i].info.properties);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+/**
+ * do_ffa_ping() - implementation of the ping subcommand
+ * @cmdtp: Command Table
+ * @flag: flags
+ * @argc: number of arguments
+ * @argv: arguments
+ *
+ * Send data to a secure partition. The secure partition UUID is provided
+ * as an argument. Use the arm_ffa driver sync_send_receive operation
+ * which implements FFA_MSG_SEND_DIRECT_{REQ,RESP} ABIs to send/receive data.
+ *
+ * Return:
+ *
+ * CMD_RET_SUCCESS: on success, otherwise failure
+ */
+static int do_ffa_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct ffa_send_direct_data msg = {
+ .data0 = 0xaaaaaaaa,
+ .data1 = 0xbbbbbbbb,
+ .data2 = 0xcccccccc,
+ .data3 = 0xdddddddd,
+ .data4 = 0xeeeeeeee,
+ };
+ u16 part_id;
+ int ret;
+ struct udevice *dev;
+
+ if (argc != 2) {
+ log_err("Missing argument\n");
+ return CMD_RET_USAGE;
+ }
+
+ part_id = strtoul(argv[1], NULL, 16);
+ if (!part_id) {
+ log_err("Partition ID can not be 0\n");
+ return CMD_RET_USAGE;
+ }
+
+ ret = ffa_get_dev(&dev);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ ret = ffa_sync_send_receive(dev, part_id, &msg, 1);
+ if (!ret) {
+ u8 cnt;
+
+ log_info("SP response:\n[LSB]\n");
+ for (cnt = 0;
+ cnt < sizeof(struct ffa_send_direct_data) / sizeof(u64);
+ cnt++)
+ log_info("%llx\n", ((u64 *)&msg)[cnt]);
+ return CMD_RET_SUCCESS;
+ }
+
+ log_err("Sending direct request error (%d)\n", ret);
+ return CMD_RET_FAILURE;
+}
+
+/**
+ *do_ffa_devlist() - implementation of the devlist subcommand
+ * @cmdtp: [in] Command Table
+ * @flag: flags
+ * @argc: number of arguments
+ * @argv: arguments
+ *
+ * Query the device belonging to the UCLASS_FFA
+ * class.
+ *
+ * Return:
+ *
+ * CMD_RET_SUCCESS: on success, otherwise failure
+ */
+static int do_ffa_devlist(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = ffa_get_dev(&dev);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ log_info("device %s, addr " PHYS_ADDR_LN ", driver %s, ops " PHYS_ADDR_LN "\n",
+ dev->name,
+ map_to_sysmem(dev),
+ dev->driver->name,
+ map_to_sysmem(dev->driver->ops));
+
+ return CMD_RET_SUCCESS;
+}
+
+static char armffa_help_text[] =
+ "getpart <partition UUID>\n"
+ " - lists the partition(s) info\n"
+ "ping <partition ID>\n"
+ " - sends a data pattern to the specified partition\n"
+ "devlist\n"
+ " - displays information about the FF-A device/driver\n";
+
+U_BOOT_CMD_WITH_SUBCMDS(armffa, "Arm FF-A test command", armffa_help_text,
+ U_BOOT_SUBCMD_MKENT(getpart, 2, 1, do_ffa_getpart),
+ U_BOOT_SUBCMD_MKENT(ping, 2, 1, do_ffa_ping),
+ U_BOOT_SUBCMD_MKENT(devlist, 1, 1, do_ffa_devlist));
diff --git a/cmd/bootdev.c b/cmd/bootdev.c
index 5b1efaa..a657de6 100644
--- a/cmd/bootdev.c
+++ b/cmd/bootdev.c
@@ -99,7 +99,7 @@
printf("Name: %s\n", dev->name);
printf("Sequence: %d\n", dev_seq(dev));
- printf("Status: %s\n", ret ? simple_itoa(ret) : device_active(dev) ?
+ printf("Status: %s\n", ret ? simple_itoa(-ret) : device_active(dev) ?
"Probed" : "OK");
printf("Uclass: %s\n", dev_get_uclass_name(dev_get_parent(dev)));
printf("Bootflows: %d (%d valid)\n", i, num_valid);
diff --git a/cmd/bootflow.c b/cmd/bootflow.c
index c0aa4f8..300ad3a 100644
--- a/cmd/bootflow.c
+++ b/cmd/bootflow.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <bootdev.h>
#include <bootflow.h>
+#include <bootm.h>
#include <bootstd.h>
#include <command.h>
#include <console.h>
@@ -70,7 +71,7 @@
printf("%3x %-11s %-6s %-9.9s %4x %-25.25s %s\n", index,
bflow->method->name, bootflow_state_get_name(bflow->state),
bflow->dev ? dev_get_uclass_name(dev_get_parent(bflow->dev)) :
- "(none)", bflow->part, bflow->name, bflow->fname);
+ "(none)", bflow->part, bflow->name, bflow->fname ?: "");
if (errors)
report_bootflow_err(bflow, bflow->err);
}
@@ -303,11 +304,14 @@
{
struct bootstd_priv *std;
struct bootflow *bflow;
+ bool x86_setup = false;
bool dump = false;
int ret;
- if (argc > 1 && *argv[1] == '-')
+ if (argc > 1 && *argv[1] == '-') {
dump = strchr(argv[1], 'd');
+ x86_setup = strchr(argv[1], 's');
+ }
ret = bootstd_get_priv(&std);
if (ret)
@@ -319,6 +323,12 @@
}
bflow = std->cur_bootflow;
+ if (IS_ENABLED(CONFIG_X86) && x86_setup) {
+ zimage_dump(bflow->x86_setup, false);
+
+ return 0;
+ }
+
printf("Name: %s\n", bflow->name);
printf("Device: %s\n", bflow->dev->name);
printf("Block dev: %s\n", bflow->blk ? bflow->blk->name : "(none)");
@@ -369,6 +379,35 @@
return 0;
}
+static int do_bootflow_read(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct bootstd_priv *std;
+ struct bootflow *bflow;
+ int ret;
+
+ ret = bootstd_get_priv(&std);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ /*
+ * Require a current bootflow. Users can use 'bootflow scan -b' to
+ * automatically scan and boot, if needed.
+ */
+ if (!std->cur_bootflow) {
+ printf("No bootflow selected\n");
+ return CMD_RET_FAILURE;
+ }
+ bflow = std->cur_bootflow;
+ ret = bootflow_read_all(bflow);
+ if (ret) {
+ printf("Failed: err=%dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
static int do_bootflow_boot(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -508,8 +547,9 @@
"scan [-abeGl] [bdev] - scan for valid bootflows (-l list, -a all, -e errors, -b boot, -G no global)\n"
"bootflow list [-e] - list scanned bootflows (-e errors)\n"
"bootflow select [<num>|<name>] - select a bootflow\n"
- "bootflow info [-d] - show info on current bootflow (-d dump bootflow)\n"
- "bootflow boot - boot current bootflow (or first available if none selected)\n"
+ "bootflow info [-ds] - show info on current bootflow (-d dump bootflow)\n"
+ "bootflow read - read all current-bootflow files\n"
+ "bootflow boot - boot current bootflow\n"
"bootflow menu [-t] - show a menu of available bootflows\n"
"bootflow cmdline [set|get|clear|delete|auto] <param> [<value>] - update cmdline";
#else
@@ -523,6 +563,7 @@
U_BOOT_SUBCMD_MKENT(list, 2, 1, do_bootflow_list),
U_BOOT_SUBCMD_MKENT(select, 2, 1, do_bootflow_select),
U_BOOT_SUBCMD_MKENT(info, 2, 1, do_bootflow_info),
+ U_BOOT_SUBCMD_MKENT(read, 1, 1, do_bootflow_read),
U_BOOT_SUBCMD_MKENT(boot, 1, 1, do_bootflow_boot),
U_BOOT_SUBCMD_MKENT(menu, 2, 1, do_bootflow_menu),
U_BOOT_SUBCMD_MKENT(cmdline, 4, 1, do_bootflow_cmdline),
diff --git a/cmd/cedit.c b/cmd/cedit.c
index 0cae304..2ff284f 100644
--- a/cmd/cedit.c
+++ b/cmd/cedit.c
@@ -7,14 +7,29 @@
*/
#include <common.h>
+#include <abuf.h>
+#include <cedit.h>
#include <command.h>
+#include <dm.h>
#include <expo.h>
#include <fs.h>
+#include <malloc.h>
+#include <mapmem.h>
#include <dm/ofnode.h>
#include <linux/sizes.h>
struct expo *cur_exp;
+static int check_cur_expo(void)
+{
+ if (!cur_exp) {
+ printf("No expo loaded\n");
+ return -ENOENT;
+ }
+
+ return 0;
+}
+
static int do_cedit_load(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -53,18 +68,192 @@
return 0;
}
+static int do_cedit_write_fdt(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ const char *fname;
+ struct abuf buf;
+ loff_t bytes;
+ int ret;
+
+ if (argc < 4)
+ return CMD_RET_USAGE;
+ fname = argv[3];
+
+ if (check_cur_expo())
+ return CMD_RET_FAILURE;
+
+ ret = cedit_write_settings(cur_exp, &buf);
+ if (ret) {
+ printf("Failed to write settings: %dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ if (fs_set_blk_dev(argv[1], argv[2], FS_TYPE_ANY))
+ return CMD_RET_FAILURE;
+
+ ret = fs_write(fname, map_to_sysmem(abuf_data(&buf)), 0,
+ abuf_size(&buf), &bytes);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return 0;
+}
+
+static int do_cedit_read_fdt(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ const char *fname;
+ void *buf;
+ oftree tree;
+ ulong size;
+ int ret;
+
+ if (argc < 4)
+ return CMD_RET_USAGE;
+ fname = argv[3];
+
+ ret = fs_load_alloc(argv[1], argv[2], argv[3], SZ_1M, 0, &buf, &size);
+ if (ret) {
+ printf("File not found\n");
+ return CMD_RET_FAILURE;
+ }
+
+ tree = oftree_from_fdt(buf);
+ if (!oftree_valid(tree)) {
+ free(buf);
+ printf("Cannot create oftree\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = cedit_read_settings(cur_exp, tree);
+ oftree_dispose(tree);
+ free(buf);
+ if (ret) {
+ printf("Failed to read settings: %dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+static int do_cedit_write_env(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ bool verbose;
+ int ret;
+
+ if (check_cur_expo())
+ return CMD_RET_FAILURE;
+
+ verbose = argc > 1 && !strcmp(argv[1], "-v");
+
+ ret = cedit_write_settings_env(cur_exp, verbose);
+ if (ret) {
+ printf("Failed to write settings to environment: %dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+static int do_cedit_read_env(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ bool verbose;
+ int ret;
+
+ if (check_cur_expo())
+ return CMD_RET_FAILURE;
+
+ verbose = argc > 1 && !strcmp(argv[1], "-v");
+
+ ret = cedit_read_settings_env(cur_exp, verbose);
+ if (ret) {
+ printf("Failed to read settings from environment: %dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+static int do_cedit_write_cmos(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct udevice *dev;
+ bool verbose = false;
+ int ret;
+
+ if (check_cur_expo())
+ return CMD_RET_FAILURE;
+
+ if (argc > 1 && !strcmp(argv[1], "-v")) {
+ verbose = true;
+ argc--;
+ argv++;
+ }
+
+ if (argc > 1)
+ ret = uclass_get_device_by_name(UCLASS_RTC, argv[1], &dev);
+ else
+ ret = uclass_first_device_err(UCLASS_RTC, &dev);
+ if (ret) {
+ printf("Failed to get RTC device: %dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ if (cedit_write_settings_cmos(cur_exp, dev, verbose)) {
+ printf("Failed to write settings to CMOS\n");
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+static int do_cedit_read_cmos(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct udevice *dev;
+ bool verbose = false;
+ int ret;
+
+ if (check_cur_expo())
+ return CMD_RET_FAILURE;
+
+ if (argc > 1 && !strcmp(argv[1], "-v")) {
+ verbose = true;
+ argc--;
+ argv++;
+ }
+
+ if (argc > 1)
+ ret = uclass_get_device_by_name(UCLASS_RTC, argv[1], &dev);
+ else
+ ret = uclass_first_device_err(UCLASS_RTC, &dev);
+ if (ret) {
+ printf("Failed to get RTC device: %dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ ret = cedit_read_settings_cmos(cur_exp, dev, verbose);
+ if (ret) {
+ printf("Failed to read settings from CMOS: %dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
static int do_cedit_run(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
ofnode node;
int ret;
- if (!cur_exp) {
- printf("No expo loaded\n");
+ if (check_cur_expo())
return CMD_RET_FAILURE;
- }
- node = ofnode_path("/cedit-theme");
+ node = ofnode_path("/bootstd/cedit-theme");
if (ofnode_valid(node)) {
ret = expo_apply_theme(cur_exp, node);
if (ret)
@@ -84,10 +273,22 @@
#ifdef CONFIG_SYS_LONGHELP
static char cedit_help_text[] =
"load <interface> <dev[:part]> <filename> - load config editor\n"
+ "cedit read_fdt <i/f> <dev[:part]> <filename> - read settings\n"
+ "cedit write_fdt <i/f> <dev[:part]> <filename> - write settings\n"
+ "cedit read_env [-v] - read settings from env vars\n"
+ "cedit write_env [-v] - write settings to env vars\n"
+ "cedit read_cmos [-v] [dev] - read settings from CMOS RAM\n"
+ "cedit write_cmos [-v] [dev] - write settings to CMOS RAM\n"
"cedit run - run config editor";
#endif /* CONFIG_SYS_LONGHELP */
U_BOOT_CMD_WITH_SUBCMDS(cedit, "Configuration editor", cedit_help_text,
U_BOOT_SUBCMD_MKENT(load, 5, 1, do_cedit_load),
+ U_BOOT_SUBCMD_MKENT(read_fdt, 5, 1, do_cedit_read_fdt),
+ U_BOOT_SUBCMD_MKENT(write_fdt, 5, 1, do_cedit_write_fdt),
+ U_BOOT_SUBCMD_MKENT(read_env, 2, 1, do_cedit_read_env),
+ U_BOOT_SUBCMD_MKENT(write_env, 2, 1, do_cedit_write_env),
+ U_BOOT_SUBCMD_MKENT(read_cmos, 2, 1, do_cedit_read_cmos),
+ U_BOOT_SUBCMD_MKENT(write_cmos, 2, 1, do_cedit_write_cmos),
U_BOOT_SUBCMD_MKENT(run, 1, 1, do_cedit_run),
);
diff --git a/cmd/cyclic.c b/cmd/cyclic.c
index 97324d8..946f1d7 100644
--- a/cmd/cyclic.c
+++ b/cmd/cyclic.c
@@ -77,7 +77,7 @@
}
static char cyclic_help_text[] =
- "cyclic demo <cycletime_ms> <delay_us> - register cyclic demo function\n"
+ "demo <cycletime_ms> <delay_us> - register cyclic demo function\n"
"cyclic list - list cyclic functions\n";
U_BOOT_CMD_WITH_SUBCMDS(cyclic, "Cyclic", cyclic_help_text,
diff --git a/cmd/gpt.c b/cmd/gpt.c
index 007a68e..8969efb 100644
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -211,12 +211,10 @@
PART_TYPE_LEN);
newpart->gpt_part_info.type[PART_TYPE_LEN - 1] = '\0';
newpart->gpt_part_info.bootable = info->bootable;
-#ifdef CONFIG_PARTITION_UUIDS
- strncpy(newpart->gpt_part_info.uuid, (const char *)info->uuid,
- UUID_STR_LEN);
- /* UUID_STR_LEN is correct, as uuid[]'s length is UUID_STR_LEN+1 chars */
- newpart->gpt_part_info.uuid[UUID_STR_LEN] = '\0';
-#endif
+ if (IS_ENABLED(CONFIG_PARTITION_UUIDS)) {
+ strlcpy(newpart->gpt_part_info.uuid, disk_partition_uuid(info),
+ UUID_STR_LEN + 1);
+ }
newpart->partnum = partnum;
return newpart;
diff --git a/cmd/mux.c b/cmd/mux.c
index 833266f..c75907a 100644
--- a/cmd/mux.c
+++ b/cmd/mux.c
@@ -49,7 +49,7 @@
chip = dev_get_uclass_priv(dev);
if (!chip)
- return ERR_PTR(ret);
+ return ERR_PTR(-EINVAL);
if (id >= chip->controllers)
return ERR_PTR(-EINVAL);
diff --git a/cmd/nvedit_efi.c b/cmd/nvedit_efi.c
index 24944ab..7a30b5c 100644
--- a/cmd/nvedit_efi.c
+++ b/cmd/nvedit_efi.c
@@ -262,7 +262,7 @@
char *tmp_buf = NULL, *new_buf = NULL, *value;
unsigned long len = 0;
- if (!strncmp(data, "=0x", 2)) { /* hexadecimal number */
+ if (!strncmp(data, "=0x", 3)) { /* hexadecimal number */
union {
u8 u8;
u16 u16;
diff --git a/cmd/pxe.c b/cmd/pxe.c
index 6771425..7bfb1b9 100644
--- a/cmd/pxe.c
+++ b/cmd/pxe.c
@@ -333,8 +333,7 @@
}
U_BOOT_CMD(pxe, 4, 1, do_pxe,
- "commands to get and boot from pxe files\n"
- "To use IPv6 add -ipv6 parameter",
+ "get and boot from pxe files",
"get [" USE_IP6_CMD_PARAM "] - try to retrieve a pxe file using tftp\n"
"pxe boot [pxefile_addr_r] [-ipv6] - boot from the pxe file at pxefile_addr_r\n"
);
diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
index c4707fe..32761c5 100644
--- a/cmd/riscv/sbi.c
+++ b/cmd/riscv/sbi.c
@@ -27,6 +27,8 @@
{ 4, "RustSBI" },
{ 5, "Diosix" },
{ 6, "Coffer" },
+ { 7, "Xen Project" },
+ { 8, "PolarFire Hart Software Services" },
};
static struct sbi_ext extensions[] = {
@@ -49,6 +51,8 @@
{ SBI_EXT_DBCN, "Debug Console Extension" },
{ SBI_EXT_SUSP, "System Suspend Extension" },
{ SBI_EXT_CPPC, "Collaborative Processor Performance Control Extension" },
+ { SBI_EXT_NACL, "Nested Acceleration Extension" },
+ { SBI_EXT_STA, "Steal-time Accounting Extension" },
};
static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
diff --git a/cmd/tpm_test.c b/cmd/tpm_test.c
index c4ed8e5..9bdc9c6 100644
--- a/cmd/tpm_test.c
+++ b/cmd/tpm_test.c
@@ -294,8 +294,8 @@
*/
index_0 += 1;
if (tpm_nv_write_value(dev, INDEX0, (uint8_t *)&index_0,
- sizeof(index_0) !=
- TPM_SUCCESS)) {
+ sizeof(index_0)) !=
+ TPM_SUCCESS) {
pr_err("\tcould not write index 0\n");
}
tpm_nv_write_value_lock(dev, INDEX0);
diff --git a/cmd/ubi.c b/cmd/ubi.c
index b61ae1e..0a6a80b 100644
--- a/cmd/ubi.c
+++ b/cmd/ubi.c
@@ -653,7 +653,7 @@
if (strcmp(argv[1], "list") == 0) {
int numeric = 0;
- if (argc >= 2 && argv[2][0] == '-') {
+ if (argc >= 3 && argv[2][0] == '-') {
if (strcmp(argv[2], "-numeric") == 0)
numeric = 1;
else
diff --git a/common/Kconfig b/common/Kconfig
index 973482f..0b09bd6 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -226,7 +226,7 @@
config CONSOLE_MUX
bool "Enable console multiplexing"
- default y if VIDEO || VIDEO || LCD
+ default y if VIDEO || LCD
help
This allows multiple devices to be used for each console 'file'.
For example, stdout can be set to go to serial and video.
@@ -951,6 +951,7 @@
config BLOBLIST
bool "Support for a bloblist"
+ select CRC32
help
This enables support for a bloblist in U-Boot, which can be passed
from TPL to SPL to U-Boot proper (and potentially to Linux). The
@@ -961,6 +962,7 @@
config SPL_BLOBLIST
bool "Support for a bloblist in SPL"
depends on BLOBLIST && SPL_LIBGENERIC_SUPPORT && SPL_LIBCOMMON_SUPPORT
+ select SPL_CRC32
default y if SPL
help
This enables a bloblist in SPL. If this is the first part of U-Boot
@@ -970,6 +972,7 @@
config TPL_BLOBLIST
bool "Support for a bloblist in TPL"
depends on BLOBLIST && TPL_LIBGENERIC_SUPPORT && TPL_LIBCOMMON_SUPPORT
+ select TPL_CRC32
default y if TPL
help
This enables a bloblist in TPL. The bloblist is set up in TPL and
@@ -1028,7 +1031,7 @@
config BLOBLIST_SIZE_RELOC
hex "Size of bloblist after relocation"
default BLOBLIST_SIZE if BLOBLIST_FIXED || BLOBLIST_ALLOC
- default 0 if BLOBLIST_PASSAGE
+ default 0x0 if BLOBLIST_PASSAGE
help
Sets the size of the bloblist in bytes after relocation. Since U-Boot
has a lot more memory available then, it is possible to use a larger
@@ -1171,7 +1174,7 @@
Enable bmp functions to display bmp image and get bmp info.
config SPL_BMP
- bool "Enable bmp image display at SPL"
+ bool "Enable bmp image display at SPL"
depends on SPL_VIDEO
help
Enable bmp functions to display bmp image and get bmp info at SPL.
diff --git a/common/Makefile b/common/Makefile
index c87bb2e..f5c3d90 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -79,7 +79,7 @@
obj-$(CONFIG_CROS_EC) += cros_ec.o
obj-y += dlmalloc.o
ifdef CONFIG_SYS_MALLOC_F
-ifneq ($(CONFIG_$(SPL_TPL_)SYS_MALLOC_F_LEN),0)
+ifneq ($(CONFIG_$(SPL_TPL_)SYS_MALLOC_F_LEN),0x0)
obj-y += malloc_simple.o
endif
endif
diff --git a/common/board_f.c b/common/board_f.c
index 7d2c380..2f986d9 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -124,8 +124,8 @@
#if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
ulong bss_start, bss_end, text_base;
- bss_start = (ulong)&__bss_start;
- bss_end = (ulong)&__bss_end;
+ bss_start = (ulong)__bss_start;
+ bss_end = (ulong)__bss_end;
#ifdef CONFIG_TEXT_BASE
text_base = CONFIG_TEXT_BASE;
@@ -148,11 +148,12 @@
bool status_printed = false;
int ret;
- /* Not all boards have sysreset drivers available during early
+ /*
+ * Not all boards have sysreset drivers available during early
* boot, so don't fail if one can't be found.
*/
for (ret = uclass_first_device_check(UCLASS_SYSRESET, &dev); dev;
- ret = uclass_next_device_check(&dev)) {
+ ret = uclass_next_device_check(&dev)) {
if (ret) {
debug("%s: %s sysreset device (error: %d)\n",
__func__, dev->name, ret);
@@ -289,21 +290,21 @@
static int setup_mon_len(void)
{
#if defined(__ARM__) || defined(__MICROBLAZE__)
- gd->mon_len = (ulong)&__bss_end - (ulong)_start;
+ gd->mon_len = (ulong)__bss_end - (ulong)_start;
#elif defined(CONFIG_SANDBOX) && !defined(__riscv)
- gd->mon_len = (ulong)&_end - (ulong)_init;
+ gd->mon_len = (ulong)_end - (ulong)_init;
#elif defined(CONFIG_SANDBOX)
/* gcc does not provide _init in crti.o on RISC-V */
gd->mon_len = 0;
#elif defined(CONFIG_EFI_APP)
- gd->mon_len = (ulong)&_end - (ulong)_init;
+ gd->mon_len = (ulong)_end - (ulong)_init;
#elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
gd->mon_len = CONFIG_SYS_MONITOR_LEN;
#elif defined(CONFIG_SH) || defined(CONFIG_RISCV)
- gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
+ gd->mon_len = (ulong)(__bss_end) - (ulong)(_start);
#elif defined(CONFIG_SYS_MONITOR_BASE)
- /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
- gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
+ /* TODO: use (ulong)__bss_end - (ulong)__text_start; ? */
+ gd->mon_len = (ulong)__bss_end - CONFIG_SYS_MONITOR_BASE;
#endif
return 0;
}
@@ -330,7 +331,7 @@
}
/* Get the top of usable RAM */
-__weak phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+__weak phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
#if defined(CFG_SYS_SDRAM_BASE) && CFG_SYS_SDRAM_BASE > 0
/*
@@ -411,8 +412,7 @@
static int reserve_video(void)
{
- if (IS_ENABLED(CONFIG_SPL_VIDEO) && spl_phase() > PHASE_SPL &&
- CONFIG_IS_ENABLED(BLOBLIST)) {
+ if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && spl_phase() > PHASE_SPL) {
struct video_handoff *ho;
ho = bloblist_find(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho));
diff --git a/common/board_r.c b/common/board_r.c
index 4aaa894..598155c 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -126,9 +126,9 @@
#ifdef __ARM__
monitor_flash_len = _end - __image_copy_start;
#elif defined(CONFIG_RISCV)
- monitor_flash_len = (ulong)&_end - (ulong)&_start;
+ monitor_flash_len = (ulong)_end - (ulong)_start;
#elif !defined(CONFIG_SANDBOX) && !defined(CONFIG_NIOS2)
- monitor_flash_len = (ulong)&__init_end - gd->relocaddr;
+ monitor_flash_len = (ulong)__init_end - gd->relocaddr;
#endif
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
/*
diff --git a/common/bouncebuf.c b/common/bouncebuf.c
index 93a3566..934b83f 100644
--- a/common/bouncebuf.c
+++ b/common/bouncebuf.c
@@ -79,7 +79,7 @@
{
if (state->flags & GEN_BB_WRITE) {
/* Invalidate cache so that CPU can see any newly DMA'd data */
- dma_unmap_single((dma_addr_t)state->bounce_buffer,
+ dma_unmap_single((dma_addr_t)(uintptr_t)state->bounce_buffer,
state->len_aligned,
DMA_BIDIRECTIONAL);
}
diff --git a/common/console.c b/common/console.c
index 71ad8ef..98c3ee6 100644
--- a/common/console.c
+++ b/common/console.c
@@ -1010,29 +1010,41 @@
return 0;
}
-void stdio_print_current_devices(void)
+static void stdio_print_current_devices(void)
{
- /* Print information */
- puts("In: ");
- if (stdio_devices[stdin] == NULL) {
- puts("No input devices available!\n");
+ char *stdinname, *stdoutname, *stderrname;
+
+ if (CONFIG_IS_ENABLED(CONSOLE_MUX) &&
+ CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV)) {
+ /* stdin stdout and stderr are in environment */
+ stdinname = env_get("stdin");
+ stdoutname = env_get("stdout");
+ stderrname = env_get("stderr");
+
+ stdinname = stdinname ? : "No input devices available!";
+ stdoutname = stdoutname ? : "No output devices available!";
+ stderrname = stderrname ? : "No error devices available!";
} else {
- printf ("%s\n", stdio_devices[stdin]->name);
+ stdinname = stdio_devices[stdin] ?
+ stdio_devices[stdin]->name :
+ "No input devices available!";
+ stdoutname = stdio_devices[stdout] ?
+ stdio_devices[stdout]->name :
+ "No output devices available!";
+ stderrname = stdio_devices[stderr] ?
+ stdio_devices[stderr]->name :
+ "No error devices available!";
}
+ /* Print information */
+ puts("In: ");
+ printf("%s\n", stdinname);
+
puts("Out: ");
- if (stdio_devices[stdout] == NULL) {
- puts("No output devices available!\n");
- } else {
- printf ("%s\n", stdio_devices[stdout]->name);
- }
+ printf("%s\n", stdoutname);
puts("Err: ");
- if (stdio_devices[stderr] == NULL) {
- puts("No error devices available!\n");
- } else {
- printf ("%s\n", stdio_devices[stderr]->name);
- }
+ printf("%s\n", stderrname);
}
#if CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV)
diff --git a/common/event.c b/common/event.c
index 20720c5..3224e28 100644
--- a/common/event.c
+++ b/common/event.c
@@ -27,7 +27,7 @@
"test",
/* Events related to driver model */
- "dm_post_init",
+ "dm_post_init_f",
"dm_pre_probe",
"dm_post_probe",
"dm_pre_remove",
diff --git a/common/hash.c b/common/hash.c
index cbffdfd..159179e 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -21,7 +21,6 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/errno.h>
-#include <u-boot/crc.h>
#else
#include "mkimage.h"
#include <linux/compiler_attributes.h>
diff --git a/common/init/board_init.c b/common/init/board_init.c
index 96ffb79..ab8c508 100644
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
@@ -162,6 +162,9 @@
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
/* go down one 'early malloc arena' */
gd->malloc_base = base;
+#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE)
+ memset((void *)base, '\0', CONFIG_VAL(SYS_MALLOC_F_LEN));
+#endif
#endif
if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index bee231b..1c2fe78 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -67,7 +67,7 @@
config SPL_SIZE_LIMIT_PROVIDE_STACK
hex "SPL image size check: provide stack space before relocation"
depends on SPL_SIZE_LIMIT > 0
- default 0
+ default 0x0
help
If set, this size is reserved in SPL_SIZE_LIMIT check to ensure such
an image does not overflow SRAM if SPL_SIZE_LIMIT describes the size
@@ -550,29 +550,6 @@
the eMMC EXT_CSC_PART_CONFIG selection should be overridden in SPL
by user defined partition number.
-config SPL_CRC32
- bool "Support CRC32"
- default y if SPL_LEGACY_IMAGE_FORMAT || SPL_EFI_PARTITION
- default y if SPL_ENV_SUPPORT || TPL_BLOBLIST
- help
- Enable this to support CRC32 in uImages or FIT images within SPL.
- This is a 32-bit checksum value that can be used to verify images.
- For FIT images, this is the least secure type of checksum, suitable
- for detected accidental image corruption. For secure applications you
- should consider SHA1 or SHA256.
-
-config SPL_MD5
- bool "Support MD5"
- depends on SPL_FIT
- help
- Enable this to support MD5 in FIT images within SPL. An MD5
- checksum is a 128-bit hash value used to check that the image
- contents have not been corrupted. Note that MD5 is not considered
- secure as it is possible (with a brute-force attack) to adjust the
- image while still retaining the same MD5 hash value. For secure
- applications where images may be changed maliciously, you should
- consider SHA256 or SHA384.
-
config SPL_FIT_IMAGE_TINY
bool "Remove functionality from SPL FIT loading to reduce size"
depends on SPL_FIT
diff --git a/common/spl/Kconfig.tpl b/common/spl/Kconfig.tpl
index 3d6cf1e..cc71578 100644
--- a/common/spl/Kconfig.tpl
+++ b/common/spl/Kconfig.tpl
@@ -126,7 +126,7 @@
config TPL_TEXT_BASE
hex "Base address for the .text section of the TPL stage"
- default 0
+ default 0x0
help
The base address for the .text section of the TPL stage.
diff --git a/common/spl/spl_blk_fs.c b/common/spl/spl_blk_fs.c
index 16ecece..eb6f526 100644
--- a/common/spl/spl_blk_fs.c
+++ b/common/spl/spl_blk_fs.c
@@ -44,7 +44,6 @@
enum uclass_id uclass_id, int devnum, int partnum)
{
const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME;
- struct disk_partition part_info = {};
struct legacy_img_hdr *header;
struct blk_desc *blk_desc;
loff_t actlen, filesize;
@@ -59,11 +58,6 @@
blk_show_device(uclass_id, devnum);
header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
- ret = part_get_info(blk_desc, 1, &part_info);
- if (ret) {
- printf("spl: no partition table found. Err - %d\n", ret);
- goto out;
- }
dev.ifname = blk_get_uclass_name(uclass_id);
snprintf(dev.dev_part_str, sizeof(dev.dev_part_str) - 1, "%x:%x",
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index a665091..20f687e 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -229,7 +229,7 @@
{
int ret;
-#if CONFIG_VAL(SYS_MMCSD_RAW_MODE_ARGS_SECTOR)
+#if defined(CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR)
unsigned long count;
count = blk_dread(mmc_get_blk_desc(mmc),
diff --git a/common/spl/spl_semihosting.c b/common/spl/spl_semihosting.c
index 5b5e842..f7dd289 100644
--- a/common/spl/spl_semihosting.c
+++ b/common/spl/spl_semihosting.c
@@ -21,6 +21,23 @@
return 0;
}
+static ulong smh_fit_read(struct spl_load_info *load, ulong file_offset,
+ ulong size, void *buf)
+{
+ long fd;
+ ulong ret;
+
+ fd = smh_open(load->filename, MODE_READ | MODE_BINARY);
+ if (fd < 0) {
+ log_debug("could not open %s: %ld\n", load->filename, fd);
+ return 0;
+ }
+ ret = smh_read(fd, buf, size);
+ smh_close(fd);
+
+ return ret;
+}
+
static int spl_smh_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
@@ -49,6 +66,20 @@
goto out;
}
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+ image_get_magic(header) == FDT_MAGIC) {
+ struct spl_load_info load;
+
+ debug("Found FIT\n");
+ load.read = smh_fit_read;
+ load.bl_len = 1;
+ load.filename = filename;
+ load.priv = NULL;
+ smh_close(fd);
+
+ return spl_load_simple_fit(spl_image, &load, 0, header);
+ }
+
ret = spl_parse_image_header(spl_image, bootdev, header);
if (ret) {
log_debug("failed to parse image header: %d\n", ret);
diff --git a/common/usb_storage.c b/common/usb_storage.c
index ac64275..8577422 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -246,7 +246,7 @@
if (ret)
return ret;
- ret = bootdev_setup_sibling_blk(dev, "usb_bootdev");
+ ret = bootdev_setup_for_sibling_blk(dev, "usb_bootdev");
if (ret) {
int ret2;
diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig
index a485cc6..7c4085d 100644
--- a/configs/am335x_guardian_defconfig
+++ b/configs/am335x_guardian_defconfig
@@ -17,7 +17,6 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_ENV_OFFSET_REDUND=0x540000
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SYS_MEMTEST_START=0x80000000
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index 9bdb767..718ad17 100644
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@@ -82,7 +82,6 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig
index 45d3265..b501c17 100644
--- a/configs/am64x_evm_r5_defconfig
+++ b/configs/am64x_evm_r5_defconfig
@@ -92,7 +92,6 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
diff --git a/configs/anbernic-rgxx3_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig
similarity index 100%
rename from configs/anbernic-rgxx3_defconfig
rename to configs/anbernic-rgxx3-rk3566_defconfig
diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig
index 7555609..d58a903 100644
--- a/configs/apple_m1_defconfig
+++ b/configs/apple_m1_defconfig
@@ -16,6 +16,7 @@
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_DWC3=y
CONFIG_USB_KEYBOARD=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_NO_FB_CLEAR=y
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index 5eeeb08..5d6dd2a 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -49,7 +49,6 @@
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20ba0000
CONFIG_SYS_SPL_MALLOC_SIZE=0x460000
-CONFIG_SPL_CRC32=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_RAW_ONLY=y
CONFIG_SPL_NAND_DRIVERS=y
@@ -102,4 +101,5 @@
CONFIG_ATMEL_USART=y
CONFIG_WDT=y
CONFIG_WDT_AT91=y
+CONFIG_SPL_CRC32=y
CONFIG_HEXDUMP=y
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index ce46dd5..6a9b509 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -38,7 +38,6 @@
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-# CONFIG_SPL_CRC32 is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 1a9d633..9fdad32 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -37,7 +37,6 @@
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-# CONFIG_SPL_CRC32 is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index 52e0fa3..811d666 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -38,7 +38,6 @@
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-# CONFIG_SPL_CRC32 is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
index b82f70b..8b6d995 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -38,7 +38,6 @@
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-# CONFIG_SPL_CRC32 is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
index c68e52b..3b5733b 100644
--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
@@ -42,6 +42,7 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
+CONFIG_ARM_FFA_TRANSPORT=y
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_NVMXIP_QSPI=y
@@ -54,9 +55,15 @@
CONFIG_RTC_EMULATION=y
CONFIG_DM_SERIAL=y
CONFIG_SYSRESET=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
CONFIG_USB=y
CONFIG_USB_ISP1760=y
CONFIG_ERRNO_STR=y
+CONFIG_EFI_MM_COMM_TEE=y
+CONFIG_FFA_SHARED_MM_BUF_SIZE=4096
+CONFIG_FFA_SHARED_MM_BUF_OFFSET=0
+CONFIG_FFA_SHARED_MM_BUF_ADDR=0x02000000
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_IGNORE_OSINDICATIONS=y
CONFIG_FWU_MULTI_BANK_UPDATE=y
diff --git a/configs/efi-x86_app32_defconfig b/configs/efi-x86_app32_defconfig
index 50975db..1bfc01f 100644
--- a/configs/efi-x86_app32_defconfig
+++ b/configs/efi-x86_app32_defconfig
@@ -2,7 +2,7 @@
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="efi-x86_app"
-CONFIG_DEBUG_UART_BASE=0
+CONFIG_DEBUG_UART_BASE=0x0
CONFIG_DEBUG_UART_CLOCK=0
CONFIG_VENDOR_EFI=y
CONFIG_TARGET_EFI_APP32=y
diff --git a/configs/efi-x86_app64_defconfig b/configs/efi-x86_app64_defconfig
index 0fc358d..46a1900 100644
--- a/configs/efi-x86_app64_defconfig
+++ b/configs/efi-x86_app64_defconfig
@@ -2,7 +2,7 @@
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="efi-x86_app"
-CONFIG_DEBUG_UART_BASE=0
+CONFIG_DEBUG_UART_BASE=0x0
CONFIG_DEBUG_UART_CLOCK=0
CONFIG_X86_RUN_64BIT=y
CONFIG_VENDOR_EFI=y
diff --git a/configs/endeavoru_defconfig b/configs/endeavoru_defconfig
new file mode 100644
index 0000000..38f26f2
--- /dev/null
+++ b/configs/endeavoru_defconfig
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x80110000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-htc-endeavoru"
+CONFIG_SPL_TEXT_BASE=0x80108000
+CONFIG_SYS_PROMPT="Tegra30 (Endeavoru) # "
+CONFIG_SPL_STACK=0x800ffffc
+CONFIG_TEGRA30=y
+CONFIG_TARGET_ENDEAVORU=y
+CONFIG_CMD_EBTUPDATE=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=0
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if run check_button; then bootmenu; fi; run bootcmd_mmc0; poweroff;"
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_PBSIZE=2084
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_SPL_DM=y
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x91000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_PWM_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="HTC"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0bb4
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0c02
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_VIDEO_LCD_ENDEAVORU=y
+CONFIG_VIDEO_DSI_TEGRA30=y
+CONFIG_TEGRA_BACKLIGHT_PWM=y
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 32e022f..9244654 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -45,7 +45,6 @@
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000000
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_CRC32=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_RAM_SUPPORT=y
@@ -121,6 +120,7 @@
CONFIG_SPL_SYSRESET=y
CONFIG_WDT=y
CONFIG_SHA384=y
+CONFIG_SPL_CRC32=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
CONFIG_PHANDLE_CHECK_SEQ=y
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 9dcd113..02254ef 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -15,7 +15,6 @@
CONFIG_SPL_TEXT_BASE=0x10081000
CONFIG_ROCKCHIP_RK3036=y
CONFIG_SPL_STACK_R_ADDR=0x80000
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x60800800
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index 73015f0..7469f3f 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -12,7 +12,6 @@
CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
CONFIG_SPL_TEXT_BASE=0x60000000
CONFIG_ROCKCHIP_RK322X=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_TARGET_EVB_RK3229=y
CONFIG_SPL_STACK_R_ADDR=0x60600000
CONFIG_DEBUG_UART_BASE=0x11030000
@@ -31,8 +30,6 @@
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x100000
-CONFIG_SPL_OPTEE_IMAGE=y
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
index a13a809..d1e7858 100644
--- a/configs/evb-rk3308_defconfig
+++ b/configs/evb-rk3308_defconfig
@@ -11,7 +11,6 @@
CONFIG_DEFAULT_DEVICE_TREE="rk3308-evb"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_EVB_RK3308=y
CONFIG_SPL_STACK_R_ADDR=0xc00000
diff --git a/configs/grouper_E1565.config b/configs/grouper_E1565.config
new file mode 100644
index 0000000..4d8d526
--- /dev/null
+++ b/configs/grouper_E1565.config
@@ -0,0 +1,2 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-E1565"
+CONFIG_GROUPER_MAX77663=y
diff --git a/configs/grouper_PM269.config b/configs/grouper_PM269.config
new file mode 100644
index 0000000..fc768b2
--- /dev/null
+++ b/configs/grouper_PM269.config
@@ -0,0 +1,2 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-PM269"
+CONFIG_GROUPER_TPS65911=y
diff --git a/configs/grouper_common_defconfig b/configs/grouper_common_defconfig
new file mode 100644
index 0000000..8dc8885
--- /dev/null
+++ b/configs/grouper_common_defconfig
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x80110000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-E1565"
+CONFIG_SPL_TEXT_BASE=0x80108000
+CONFIG_SYS_PROMPT="Tegra30 (Grouper) # "
+CONFIG_SPL_STACK=0x800ffffc
+CONFIG_TEGRA30=y
+CONFIG_TARGET_GROUPER=y
+CONFIG_CMD_EBTUPDATE=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=0
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if run check_button; then bootmenu; fi; run bootcmd_mmc0; poweroff;"
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_PBSIZE=2084
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_SPL_DM=y
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x91000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_GPIO_HOG=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_PWM_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="ASUS Google"
+CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4e41
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_VIDEO_TEGRA20=y
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig
index a811653..c44d43a 100644
--- a/configs/imx6q_bosch_acc_defconfig
+++ b/configs/imx6q_bosch_acc_defconfig
@@ -37,7 +37,6 @@
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xaa
-# CONFIG_SPL_CRC32 is not set
# CONFIG_SPL_CRYPTO is not set
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index 2814e2c..74733c4 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -86,7 +86,6 @@
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig
index 5dc4e14..e1b75d6 100644
--- a/configs/imx8mm_beacon_fspi_defconfig
+++ b/configs/imx8mm_beacon_fspi_defconfig
@@ -42,7 +42,6 @@
CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-CONFIG_SPL_CRC32=y
CONFIG_SPL_I2C=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_POWER=y
@@ -150,5 +149,6 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_IMX_WATCHDOG=y
+CONFIG_SPL_CRC32=y
CONFIG_FSPI_CONF_HEADER=y
CONFIG_FSPI_CONF_FILE="fspi_header.bin"
diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig
index f63eb4f..e2bca40 100644
--- a/configs/imx8mm_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
@@ -233,6 +233,5 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_SDP_LOADADDR=0x0
CONFIG_USB_FUNCTION_ACM=y
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig
index fab3ab1..975fcc2 100644
--- a/configs/imx8mn_beacon_2g_defconfig
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -142,4 +142,3 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_SDP_LOADADDR=0x0
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
index f810d4b..f4ecdc8 100644
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -149,5 +149,4 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_SDP_LOADADDR=0x0
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig
index 8705d9b..f5e57fb 100644
--- a/configs/imx8mn_beacon_fspi_defconfig
+++ b/configs/imx8mn_beacon_fspi_defconfig
@@ -149,7 +149,6 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_SDP_LOADADDR=0x0
CONFIG_IMX_WATCHDOG=y
CONFIG_FSPI_CONF_HEADER=y
CONFIG_FSPI_CONF_FILE="fspi_header.bin"
diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig
index 2570eb6..c6a3e35 100644
--- a/configs/imx8mp_beacon_defconfig
+++ b/configs/imx8mp_beacon_defconfig
@@ -172,7 +172,6 @@
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
-CONFIG_SDP_LOADADDR=0x0
CONFIG_USB_FUNCTION_ACM=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig
index 34a7f17..d3b629c 100644
--- a/configs/imx8mp_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mp_data_modul_edm_sbc_defconfig
@@ -95,7 +95,6 @@
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_SHA1SUM=y
CONFIG_SHA1SUM_VERIFY=y
-CONFIG_CMD_BIND=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
@@ -258,7 +257,6 @@
CONFIG_USB_GADGET_MANUFACTURER="Data Modul"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_SDP_LOADADDR=0x0
CONFIG_USB_FUNCTION_ACM=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig
index 60ab31b..24c87aa 100644
--- a/configs/imx8mp_dhcom_pdk2_defconfig
+++ b/configs/imx8mp_dhcom_pdk2_defconfig
@@ -90,7 +90,6 @@
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_SHA1SUM=y
CONFIG_SHA1SUM_VERIFY=y
-CONFIG_CMD_BIND=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
@@ -256,7 +255,6 @@
CONFIG_USB_GADGET_MANUFACTURER="DH electronics"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_SDP_LOADADDR=0x0
CONFIG_USB_FUNCTION_ACM=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig
index 6a98a90..3e89e0f 100644
--- a/configs/imx8mp_dhcom_pdk3_defconfig
+++ b/configs/imx8mp_dhcom_pdk3_defconfig
@@ -91,7 +91,6 @@
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_SHA1SUM=y
CONFIG_SHA1SUM_VERIFY=y
-CONFIG_CMD_BIND=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
@@ -259,7 +258,6 @@
CONFIG_USB_GADGET_MANUFACTURER="DH electronics"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_SDP_LOADADDR=0x0
CONFIG_USB_FUNCTION_ACM=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig
index a71de49..40210a5 100644
--- a/configs/imxrt1020-evk_defconfig
+++ b/configs/imxrt1020-evk_defconfig
@@ -29,7 +29,6 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
-# CONFIG_SPL_CRC32 is not set
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
# CONFIG_BOOTM_NETBSD is not set
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
index f451a0d..8f7a36f 100644
--- a/configs/imxrt1050-evk_defconfig
+++ b/configs/imxrt1050-evk_defconfig
@@ -32,7 +32,6 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
-# CONFIG_SPL_CRC32 is not set
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
# CONFIG_BOOTM_NETBSD is not set
diff --git a/configs/imxrt1170-evk_defconfig b/configs/imxrt1170-evk_defconfig
index c12ab1e..8320c09 100644
--- a/configs/imxrt1170-evk_defconfig
+++ b/configs/imxrt1170-evk_defconfig
@@ -31,7 +31,6 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
-# CONFIG_SPL_CRC32 is not set
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index c68d525..ba5914d 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -94,7 +94,6 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
@@ -115,6 +114,7 @@
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_GPIO_HOG=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
@@ -147,6 +147,7 @@
CONFIG_SPI_FLASH_MTD=y
CONFIG_MULTIPLEXER=y
CONFIG_MUX_MMIO=y
+CONFIG_PHY_TI_DP83869=y
CONFIG_PHY_FIXED=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_PHY=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 525f150..214fa8b 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -97,7 +97,6 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index d59f315..09addcb 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -95,7 +95,6 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig
index 8fe2798..21a3979 100644
--- a/configs/kontron_sl28_defconfig
+++ b/configs/kontron_sl28_defconfig
@@ -20,7 +20,6 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0x18009ff0
CONFIG_SPL_SIZE_LIMIT=0x20000
-CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3f0000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -130,7 +129,6 @@
CONFIG_WDT=y
CONFIG_WDT_SL28CPLD=y
CONFIG_WDT_SP805=y
-CONFIG_OF_LIBFDT_ASSUME_MASK=0x0
CONFIG_EFI_SET_TIME=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index d232f5c..1aab157 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -17,7 +17,6 @@
CONFIG_ROCKCHIP_RK3036=y
CONFIG_TARGET_KYLIN_RK3036=y
CONFIG_SPL_STACK_R_ADDR=0x80000
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x60800800
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index 7c55b3b..9c29eb6 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -10,7 +10,6 @@
CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion-haikou"
CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_ROCKCHIP_RK3368=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig
new file mode 100644
index 0000000..b01d3bd
--- /dev/null
+++ b/configs/lubancat-2-rk3568_defconfig
@@ -0,0 +1,85 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lubancat-2.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+# CONFIG_SPI_FLASH is not set
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
+CONFIG_EFI_VAR_BUF_SIZE=16384
diff --git a/configs/mt7988_rfb_defconfig b/configs/mt7988_rfb_defconfig
new file mode 100644
index 0000000..dc97bb3
--- /dev/null
+++ b/configs/mt7988_rfb_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_TEXT_BASE=0x41e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb"
+CONFIG_SYS_PROMPT="MT7988> "
+CONFIG_TARGET_MT7988=y
+CONFIG_DEBUG_UART_BASE=0x11000000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_DEBUG_UART=y
+# CONFIG_AUTOBOOT is not set
+CONFIG_DEFAULT_FDT_FILE="mt7988-rfb"
+CONFIG_LOGLEVEL=7
+CONFIG_LOG=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=1049
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_PWM=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SMC=y
+CONFIG_DOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_NETMASK=y
+CONFIG_NETMASK="255.255.255.0"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.2"
+CONFIG_PROT_TCP=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MTK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_FIXED=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT7988=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MTK=y
+CONFIG_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MTK_SPIM=y
+CONFIG_LZO=y
+CONFIG_HEXDUMP=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/mt7988_sd_rfb_defconfig b/configs/mt7988_sd_rfb_defconfig
new file mode 100644
index 0000000..421999d
--- /dev/null
+++ b/configs/mt7988_sd_rfb_defconfig
@@ -0,0 +1,71 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_TEXT_BASE=0x41e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="mt7988-sd-rfb"
+CONFIG_SYS_PROMPT="MT7988> "
+CONFIG_TARGET_MT7988=y
+CONFIG_DEBUG_UART_BASE=0x11000000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_DEBUG_UART=y
+# CONFIG_AUTOBOOT is not set
+CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb"
+CONFIG_LOGLEVEL=7
+CONFIG_LOG=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=1049
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_PWM=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SMC=y
+CONFIG_DOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_NETMASK=y
+CONFIG_NETMASK="255.255.255.0"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.2"
+CONFIG_PROT_TCP=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MTK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_PHY_FIXED=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT7988=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MTK=y
+CONFIG_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MTK_SPIM=y
+CONFIG_LZO=y
+CONFIG_HEXDUMP=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig
index 59a28e5..0ea45df 100644
--- a/configs/orangepi-r1-plus-lts-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
@@ -7,6 +7,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
CONFIG_DM_RESET=y
@@ -72,7 +73,6 @@
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig
index 3f62f05..e3d7f0b 100644
--- a/configs/orangepi-r1-plus-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
@@ -7,6 +7,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
CONFIG_DM_RESET=y
@@ -72,7 +73,6 @@
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
diff --git a/configs/p1801-t.config b/configs/p1801-t.config
new file mode 100644
index 0000000..fab2912
--- /dev/null
+++ b/configs/p1801-t.config
@@ -0,0 +1,2 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-p1801-t"
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4cb0
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
index 5b91631..7716655 100644
--- a/configs/p2371-2180_defconfig
+++ b/configs/p2371-2180_defconfig
@@ -29,6 +29,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig
index ae23505..3cdb1a7 100644
--- a/configs/p2771-0000-000_defconfig
+++ b/configs/p2771-0000-000_defconfig
@@ -24,6 +24,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig
index 0ea4719..41a108d 100644
--- a/configs/p2771-0000-500_defconfig
+++ b/configs/p2771-0000-500_defconfig
@@ -24,6 +24,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig
index b0d538f..febd82e 100644
--- a/configs/p3450-0000_defconfig
+++ b/configs/p3450-0000_defconfig
@@ -30,6 +30,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
diff --git a/configs/p880.config b/configs/p880.config
new file mode 100644
index 0000000..1a47b5f
--- /dev/null
+++ b/configs/p880.config
@@ -0,0 +1,4 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-lg-p880"
+CONFIG_DEVICE_P880=y
+CONFIG_SYS_PROMPT="Tegra30 (P880) # "
+CONFIG_VIDEO_LCD_RENESAS_R69328=y
diff --git a/configs/p895.config b/configs/p895.config
new file mode 100644
index 0000000..019a566
--- /dev/null
+++ b/configs/p895.config
@@ -0,0 +1,4 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-lg-p895"
+CONFIG_DEVICE_P895=y
+CONFIG_SYS_PROMPT="Tegra30 (P895) # "
+CONFIG_VIDEO_LCD_RENESAS_R61307=y
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index 9cf38a5..c6f3067 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -84,6 +84,10 @@
CONFIG_SYS_NS16550_PORT_MAPPED=y
CONFIG_SPI=y
CONFIG_USB_KEYBOARD=y
+CONFIG_SPL_VIDEO=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_USER=y
+CONFIG_FRAMEBUFFER_VESA_MODE=0x144
CONFIG_CONSOLE_SCROLL_LINES=5
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_GENERATE_ACPI_TABLE=y
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 95a6ff9..24682a5 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -5,10 +5,14 @@
CONFIG_ENV_SIZE=0x40000
CONFIG_MAX_CPUS=2
CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_DEBUG_UART=y
CONFIG_SMP=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_FIT=y
+CONFIG_BOOTSTD_FULL=y
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
@@ -16,6 +20,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_LOG=y
+CONFIG_LOGF_FUNC=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_PCI_INIT_R=y
@@ -23,11 +29,13 @@
CONFIG_CMD_CPU=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_MEM_SEARCH=y
CONFIG_CMD_IDE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_QFW=y
CONFIG_CMD_BOOTSTAGE=y
@@ -53,6 +61,9 @@
CONFIG_SYS_NS16550_PORT_MAPPED=y
CONFIG_SPI=y
CONFIG_USB_KEYBOARD=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_USER=y
+CONFIG_FRAMEBUFFER_VESA_MODE=0x144
CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_GENERATE_ACPI_TABLE=y
# CONFIG_GZIP is not set
diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig
index 94bd966..5fdf496 100644
--- a/configs/qemu_arm64_defconfig
+++ b/configs/qemu_arm64_defconfig
@@ -35,7 +35,6 @@
CONFIG_CMD_DFU=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
CONFIG_CMD_TPM=y
CONFIG_CMD_MTDPARTS=y
CONFIG_ENV_IS_IN_FLASH=y
@@ -68,7 +67,7 @@
CONFIG_SYSRESET_CMD_POWEROFF=y
CONFIG_SYSRESET_PSCI=y
CONFIG_TPM2_MMIO=y
-CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_PCI=y
+CONFIG_SEMIHOSTING=y
CONFIG_TPM=y
diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig
index 7cb1e9f..1347b86 100644
--- a/configs/qemu_arm_defconfig
+++ b/configs/qemu_arm_defconfig
@@ -36,7 +36,6 @@
CONFIG_CMD_DFU=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
CONFIG_CMD_TPM=y
CONFIG_CMD_MTDPARTS=y
CONFIG_ENV_IS_IN_FLASH=y
@@ -69,7 +68,6 @@
CONFIG_SYSRESET_CMD_POWEROFF=y
CONFIG_SYSRESET_PSCI=y
CONFIG_TPM2_MMIO=y
-CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_PCI=y
CONFIG_TPM=y
diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig
index 9a789b2..3f3c223 100644
--- a/configs/roc-cc-rk3308_defconfig
+++ b/configs/roc-cc-rk3308_defconfig
@@ -11,7 +11,6 @@
CONFIG_DEFAULT_DEVICE_TREE="rk3308-roc-cc"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_ROC_RK3308_CC=y
CONFIG_SPL_STACK_R_ADDR=0xc00000
diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig
index 82098f2..c0375be 100644
--- a/configs/rock-pi-e-rk3328_defconfig
+++ b/configs/rock-pi-e-rk3328_defconfig
@@ -79,7 +79,6 @@
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
@@ -102,7 +101,6 @@
CONFIG_SYSINFO_SMBIOS=y
CONFIG_SYSRESET=y
# CONFIG_TPL_SYSRESET is not set
-CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
@@ -112,6 +110,7 @@
CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_SPL_TINY_MEMSET=y
diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig
index cc3274a..8c13f7f 100644
--- a/configs/rock-pi-s-rk3308_defconfig
+++ b/configs/rock-pi-s-rk3308_defconfig
@@ -11,7 +11,6 @@
CONFIG_DEFAULT_DEVICE_TREE="rk3308-rock-pi-s"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_EVB_RK3308=y
CONFIG_SPL_STACK_R_ADDR=0xc00000
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
index 6cbd981..39e3525 100644
--- a/configs/rock5a-rk3588s_defconfig
+++ b/configs/rock5a-rk3588s_defconfig
@@ -11,7 +11,6 @@
CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x1000000
CONFIG_TARGET_ROCK5A_RK3588=y
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
index 5e36612..c2641f6 100644
--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
@@ -72,8 +72,11 @@
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index bf3ef0c..55a01b7 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -4,7 +4,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sandbox64"
CONFIG_DM_RESET=y
CONFIG_PRE_CON_BUF_ADDR=0x100000
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_PCI=y
CONFIG_SANDBOX64=y
@@ -21,7 +20,7 @@
CONFIG_BOOTSTAGE_STASH=y
CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_CONSOLE_RECORD=y
-CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
+CONFIG_CONSOLE_RECORD_OUT_SIZE=0x6000
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_CPU=y
@@ -124,10 +123,13 @@
CONFIG_SYS_ATA_ALT_OFFSET=2
CONFIG_SYS_ATA_IDE0_OFFSET=0
CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
CONFIG_BUTTON_GPIO=y
CONFIG_CLK=y
+CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_CLK_K210=y
CONFIG_CLK_K210_SET_RATE=y
+CONFIG_SANDBOX_CLK_CCF=y
CONFIG_CPU=y
CONFIG_DM_DEMO=y
CONFIG_DM_DEMO_SIMPLE=y
@@ -165,6 +167,7 @@
CONFIG_MMC_SANDBOX=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_SANDBOX=y
+CONFIG_BOOTDEV_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y
@@ -175,18 +178,21 @@
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_NVMXIP_QSPI=y
CONFIG_NVME_PCI=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCI_SANDBOX=y
CONFIG_PHY=y
CONFIG_PHY_SANDBOX=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_SANDBOX=y
+CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_SANDBOX_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_ACT8846=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_PMIC_MAX77686=y
+CONFIG_DM_PMIC_MC34708=y
CONFIG_PMIC_QCOM=y
CONFIG_PMIC_RK8XX=y
CONFIG_PMIC_S2MPS11=y
@@ -233,6 +239,7 @@
CONFIG_USB_EMUL=y
CONFIG_USB_KEYBOARD=y
CONFIG_VIDEO=y
+CONFIG_VIDEO_FONT_SUN12X22=y
CONFIG_CONSOLE_ROTATION=y
CONFIG_CONSOLE_TRUETYPE=y
CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
@@ -240,6 +247,8 @@
CONFIG_VIDEO_SANDBOX_SDL=y
CONFIG_OSD=y
CONFIG_SANDBOX_OSD=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
# CONFIG_WATCHDOG_AUTOSTART is not set
CONFIG_WDT=y
CONFIG_WDT_GPIO=y
@@ -260,3 +269,4 @@
CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
+CONFIG_ARM_FFA_TRANSPORT=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index b6c4f73..0f01471 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -4,7 +4,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_DM_RESET=y
CONFIG_PRE_CON_BUF_ADDR=0xf0000
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
@@ -65,7 +64,6 @@
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_UNZIP=y
-CONFIG_CMD_BIND=y
CONFIG_CMD_DEMO=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPIO_READ=y
@@ -233,6 +231,7 @@
CONFIG_NVME_PCI=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCI_SANDBOX=y
+CONFIG_PCI_FTPCI100=y
CONFIG_PHY=y
CONFIG_PHY_SANDBOX=y
CONFIG_PINCTRL=y
@@ -341,8 +340,10 @@
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_EFI_CAPSULE_AUTHENTICATE=y
+CONFIG_EFI_CAPSULE_ESL_FILE="board/sandbox/capsule_pub_esl_good.esl"
CONFIG_EFI_SECURE_BOOT=y
CONFIG_TEST_FDTDEC=y
CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
+CONFIG_ARM_FFA_TRANSPORT=y
diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig
index 8aa2956..db916e6 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -3,7 +3,6 @@
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_DM_RESET=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
@@ -227,6 +226,7 @@
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
CONFIG_EFI_CAPSULE_AUTHENTICATE=y
+CONFIG_EFI_CAPSULE_ESL_FILE="board/sandbox/capsule_pub_esl_good.esl"
CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig
index 2c6aab6..ee04fbb 100644
--- a/configs/sandbox_noinst_defconfig
+++ b/configs/sandbox_noinst_defconfig
@@ -10,7 +10,6 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_PCI=y
CONFIG_SANDBOX_SPL=y
@@ -237,6 +236,8 @@
CONFIG_LZ4=y
CONFIG_ZSTD=y
CONFIG_ERRNO_STR=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_UNIT_TEST=y
CONFIG_SPL_UNIT_TEST=y
CONFIG_UT_TIME=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index 8d50162..69b4133 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -10,7 +10,6 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_PCI=y
CONFIG_SANDBOX_SPL=y
@@ -245,6 +244,8 @@
CONFIG_ZSTD=y
CONFIG_ERRNO_STR=y
CONFIG_SPL_HEXDUMP=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_UNIT_TEST=y
CONFIG_SPL_UNIT_TEST=y
CONFIG_UT_TIME=y
diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig
index f3a0fd1..27354b8 100644
--- a/configs/sandbox_vpl_defconfig
+++ b/configs/sandbox_vpl_defconfig
@@ -15,7 +15,6 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_PCI=y
CONFIG_SANDBOX_SPL=y
@@ -256,6 +255,8 @@
CONFIG_ZSTD=y
# CONFIG_VPL_LZMA is not set
CONFIG_ERRNO_STR=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_UNIT_TEST=y
CONFIG_SPL_UNIT_TEST=y
CONFIG_UT_TIME=y
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
index ffae865..867611b 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -31,6 +31,7 @@
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ID_EEPROM=y
+CONFIG_PCI_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x100000
CONFIG_SPL_BSS_START_ADDR=0x85000000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index bb066a6..22ec8e5 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -29,6 +29,7 @@
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTMETH_CROS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SILENT_CONSOLE=y
CONFIG_BLOBLIST=y
diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig
index 0785157..ba0dbb8 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -39,7 +39,6 @@
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000
CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
-CONFIG_SPL_CRC32=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
@@ -92,3 +91,4 @@
CONFIG_WDT=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_PANIC_HANG=y
+CONFIG_SPL_CRC32=y
diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig
index 037597f..7c83ec9 100644
--- a/configs/socfpga_agilex_vab_defconfig
+++ b/configs/socfpga_agilex_vab_defconfig
@@ -40,7 +40,6 @@
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000
CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
-CONFIG_SPL_CRC32=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
@@ -93,3 +92,4 @@
CONFIG_WDT=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_PANIC_HANG=y
+CONFIG_SPL_CRC32=y
diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig
index f308239..78595c5 100644
--- a/configs/socfpga_n5x_atf_defconfig
+++ b/configs/socfpga_n5x_atf_defconfig
@@ -38,7 +38,6 @@
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000
CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
-CONFIG_SPL_CRC32=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
@@ -91,3 +90,4 @@
CONFIG_WDT=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_PANIC_HANG=y
+CONFIG_SPL_CRC32=y
diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig
index e82f6cd..e8c62d0 100644
--- a/configs/socfpga_n5x_vab_defconfig
+++ b/configs/socfpga_n5x_vab_defconfig
@@ -39,7 +39,6 @@
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000
CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
-CONFIG_SPL_CRC32=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
@@ -92,3 +91,4 @@
CONFIG_WDT=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_PANIC_HANG=y
+CONFIG_SPL_CRC32=y
diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig
index e3e8a63..2d4f705 100644
--- a/configs/socfpga_stratix10_atf_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -39,7 +39,6 @@
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000
CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
-CONFIG_SPL_CRC32=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
CONFIG_SPL_ATF=y
@@ -93,3 +92,4 @@
CONFIG_WDT=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_PANIC_HANG=y
+CONFIG_SPL_CRC32=y
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 75b7274..e9b63e5 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -6,6 +6,15 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000000
CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_ENV_SUPPORT=y
+CONFIG_SAVEENV=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE_AUTO=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xf0000
+CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2"
CONFIG_SPL_TEXT_BASE=0x8000000
@@ -19,6 +28,8 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_SYS_PCI_64BIT=y
+CONFIG_PCI=y
CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
CONFIG_SPL_OPENSBI_LOAD_ADDR=0x40000000
CONFIG_ARCH_RV64I=y
@@ -62,6 +73,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -92,6 +105,11 @@
CONFIG_DWC_ETH_QOS_STARFIVE=y
CONFIG_RGMII=y
CONFIG_RMII=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCIE_STARFIVE_JH7110=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
@@ -103,3 +121,7 @@
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_TIMER_EARLY=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_KEYBOARD=y
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index 424ae5d..9ea5aaa 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -171,6 +171,7 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
@@ -178,6 +179,8 @@
CONFIG_VIDEO_STM32_DSI=y
CONFIG_VIDEO_STM32_MAX_XRES=1280
CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig
index 2700b5c..4d0a81f 100644
--- a/configs/stm32mp15_defconfig
+++ b/configs/stm32mp15_defconfig
@@ -147,6 +147,7 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
@@ -154,6 +155,8 @@
CONFIG_VIDEO_STM32_DSI=y
CONFIG_VIDEO_STM32_MAX_XRES=1280
CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index 5b94e0c..0a7d862 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -147,6 +147,7 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
@@ -154,6 +155,8 @@
CONFIG_VIDEO_STM32_DSI=y
CONFIG_VIDEO_STM32_MAX_XRES=1280
CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 2a85c0d..81a8377 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -53,7 +53,6 @@
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20ba0000
CONFIG_SYS_SPL_MALLOC_SIZE=0x460000
-CONFIG_SPL_CRC32=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_RAW_ONLY=y
CONFIG_SPL_NAND_DRIVERS=y
@@ -119,4 +118,5 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_WDT=y
CONFIG_WDT_AT91=y
+CONFIG_SPL_CRC32=y
CONFIG_HEXDUMP=y
diff --git a/configs/ten64_tfa_defconfig b/configs/ten64_tfa_defconfig
index 9797a34..24282a6 100644
--- a/configs/ten64_tfa_defconfig
+++ b/configs/ten64_tfa_defconfig
@@ -17,12 +17,14 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_BOOTSTD_BOOTCOMMAND=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_LOGLEVEL=7
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -75,7 +77,7 @@
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_E1000=y
CONFIG_MII=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
@@ -94,6 +96,7 @@
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
+# CONFIG_WATCHDOG_AUTOSTART is not set
CONFIG_WDT=y
CONFIG_WDT_SP805=y
CONFIG_TPM=y
diff --git a/configs/tf201.config b/configs/tf201.config
new file mode 100644
index 0000000..296743b
--- /dev/null
+++ b/configs/tf201.config
@@ -0,0 +1,2 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf201"
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00
diff --git a/configs/tf300t.config b/configs/tf300t.config
new file mode 100644
index 0000000..32a92fe
--- /dev/null
+++ b/configs/tf300t.config
@@ -0,0 +1,2 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf300t"
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00
diff --git a/configs/tf300tg.config b/configs/tf300tg.config
new file mode 100644
index 0000000..1396294
--- /dev/null
+++ b/configs/tf300tg.config
@@ -0,0 +1,2 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf300tg"
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4c80
diff --git a/configs/tf300tl.config b/configs/tf300tl.config
new file mode 100644
index 0000000..3db033c
--- /dev/null
+++ b/configs/tf300tl.config
@@ -0,0 +1,2 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf300tl"
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00
diff --git a/configs/tf600t.config b/configs/tf600t.config
new file mode 100644
index 0000000..89d8db4
--- /dev/null
+++ b/configs/tf600t.config
@@ -0,0 +1,4 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf600t"
+CONFIG_TRANSFORMER_SPI_BOOT=y
+CONFIG_BOOTCOMMAND="setenv gpio_button 222; if run check_button; then poweroff; fi; setenv gpio_button 132; if run check_button; then echo Starting SPI flash update ...; run update_spi; fi; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;"
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00
diff --git a/configs/tf700t.config b/configs/tf700t.config
new file mode 100644
index 0000000..066c884
--- /dev/null
+++ b/configs/tf700t.config
@@ -0,0 +1,2 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf700t"
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4c90
diff --git a/configs/tilapia.config b/configs/tilapia.config
new file mode 100644
index 0000000..1fb0633
--- /dev/null
+++ b/configs/tilapia.config
@@ -0,0 +1,3 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-tilapia-E1565"
+CONFIG_GROUPER_MAX77663=y
+CONFIG_SYS_PROMPT="Tegra30 (Tilapia) # "
diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig
new file mode 100644
index 0000000..6fe6f25
--- /dev/null
+++ b/configs/transformer_t30_defconfig
@@ -0,0 +1,85 @@
+CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x80110000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf201"
+CONFIG_SPL_TEXT_BASE=0x80108000
+CONFIG_SYS_PROMPT="Tegra30 (Transformer) # "
+CONFIG_SPL_STACK=0x800ffffc
+CONFIG_TEGRA30=y
+CONFIG_TARGET_TRANSFORMER_T30=y
+CONFIG_CMD_EBTUPDATE=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=0
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv gpio_button 150; if run check_button; then poweroff; fi; setenv gpio_button 131; if run check_button; then bootmenu; fi; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;"
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_PBSIZE=2084
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_SPL_DM=y
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x91000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_GPIO_HOG=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_PWM_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="ASUS"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0b05
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_VIDEO_TEGRA20=y
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig
new file mode 100644
index 0000000..889b7e9
--- /dev/null
+++ b/configs/verdin-am62_a53_defconfig
@@ -0,0 +1,185 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_AM625=y
+CONFIG_K3_ATF_LOAD_ADDR=0x9e780000
+CONFIG_TARGET_VERDIN_AM62_A53=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am625-verdin-wifi-dev"
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_SYS_PROMPT="Verdin AM62 # "
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SIZE_LIMIT=0x40000
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SYS_LOAD_ADDR=0x88200000
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=1
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile k3-am625-verdin-${variant}-${fdt_board}.dtb"
+CONFIG_LOG=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x58000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80c80000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x40000000
+CONFIG_CMD_ADTIMG=y
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_BCB=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth0"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_GPIO_HOG=y
+CONFIG_SPL_GPIO_HOG=y
+CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SPL_I2C_EEPROM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_PHY_ETHERNET_ID=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_TPS65219=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_TPS65219=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_HEXDUMP=y
diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig
new file mode 100644
index 0000000..878195a
--- /dev/null
+++ b/configs/verdin-am62_r5_defconfig
@@ -0,0 +1,111 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SYS_MALLOC_LEN=0x08000000
+CONFIG_SYS_MALLOC_F_LEN=0x9000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_AM625=y
+CONFIG_TARGET_VERDIN_AM62_R5=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am625-verdin-r5"
+CONFIG_SPL_TEXT_BASE=0x43c00000
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000
+CONFIG_SPL_SIZE_LIMIT=0x3A7F0
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_MAX_SIZE=0x3B000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x43c3b000
+CONFIG_SPL_BSS_MAX_SIZE=0x3000
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_REMOTEPROC=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_SPL_MISC=y
+CONFIG_ESM_K3=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
diff --git a/configs/x3_t30_defconfig b/configs/x3_t30_defconfig
new file mode 100644
index 0000000..540c430
--- /dev/null
+++ b/configs/x3_t30_defconfig
@@ -0,0 +1,88 @@
+CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x80110000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-lg-p880"
+CONFIG_SPL_TEXT_BASE=0x80108000
+CONFIG_SYS_PROMPT="Tegra30 (x3) # "
+CONFIG_SPL_STACK=0x800ffffc
+CONFIG_TEGRA30=y
+CONFIG_TARGET_X3_T30=y
+CONFIG_TEGRA_ENABLE_UARTD=y
+CONFIG_CMD_EBTUPDATE=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=0
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if run check_button; then bootmenu; fi; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;"
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x10000
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_PBSIZE=2084
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_SPL_DM=y
+CONFIG_BUTTON=y
+CONFIG_EXTCON=y
+CONFIG_EXTCON_MAX14526=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x91000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_PWM_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA20_SLINK=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="LG"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1004
+CONFIG_USB_GADGET_PRODUCT_NUM=0x7100
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_BACKLIGHT_LM3533=y
+CONFIG_VIDEO_BRIDGE_SOLOMON_SSD2825=y
+CONFIG_VIDEO_TEGRA20=y
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig
index 97904bd..54ba0b7 100644
--- a/configs/xilinx_versal_net_virt_defconfig
+++ b/configs/xilinx_versal_net_virt_defconfig
@@ -77,7 +77,6 @@
CONFIG_ZYNQMP_IPI=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index c4bbde2..2626084 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -11,7 +11,6 @@
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_SPL_STACK=0xfffffffc
CONFIG_SPL_SIZE_LIMIT=0x2a000
-CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x1E80000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -63,7 +62,6 @@
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_SHA1SUM=y
-CONFIG_CMD_BIND=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FPGA_LOADBP=y
diff --git a/disk/disk-uclass.c b/disk/disk-uclass.c
index d32747e..efe4bf1 100644
--- a/disk/disk-uclass.c
+++ b/disk/disk-uclass.c
@@ -17,227 +17,110 @@
#include <dm/device-internal.h>
#include <dm/lists.h>
-int part_create_block_devices(struct udevice *blk_dev)
-{
- int part, count;
- struct blk_desc *desc = dev_get_uclass_plat(blk_dev);
- struct disk_partition info;
- struct disk_part *part_data;
- char devname[32];
- struct udevice *dev;
- int ret;
-
- if (!CONFIG_IS_ENABLED(PARTITIONS) || !blk_enabled())
- return 0;
-
- if (device_get_uclass_id(blk_dev) != UCLASS_BLK)
- return 0;
-
- /* Add devices for each partition */
- for (count = 0, part = 1; part <= MAX_SEARCH_PARTITIONS; part++) {
- if (part_get_info(desc, part, &info))
- continue;
- snprintf(devname, sizeof(devname), "%s:%d", blk_dev->name,
- part);
-
- ret = device_bind_driver(blk_dev, "blk_partition",
- strdup(devname), &dev);
- if (ret)
- return ret;
-
- part_data = dev_get_uclass_plat(dev);
- part_data->partnum = part;
- part_data->gpt_part_info = info;
- count++;
-
- ret = device_probe(dev);
- if (ret) {
- debug("Can't probe\n");
- count--;
- device_unbind(dev);
-
- continue;
- }
- }
- debug("%s: %d partitions found in %s\n", __func__, count,
- blk_dev->name);
-
- return 0;
-}
-
-static ulong part_blk_read(struct udevice *dev, lbaint_t start,
- lbaint_t blkcnt, void *buffer)
-{
- struct udevice *parent;
- struct disk_part *part;
- const struct blk_ops *ops;
-
- parent = dev_get_parent(dev);
- ops = blk_get_ops(parent);
- if (!ops->read)
- return -ENOSYS;
-
- part = dev_get_uclass_plat(dev);
- if (start >= part->gpt_part_info.size)
- return 0;
-
- if ((start + blkcnt) > part->gpt_part_info.size)
- blkcnt = part->gpt_part_info.size - start;
- start += part->gpt_part_info.start;
-
- return ops->read(parent, start, blkcnt, buffer);
-}
-
-static ulong part_blk_write(struct udevice *dev, lbaint_t start,
- lbaint_t blkcnt, const void *buffer)
+/**
+ * disk_blk_part_validate() - Check whether access to partition is within limits
+ *
+ * @dev: Device (partition udevice)
+ * @start: Start block for the access(from start of partition)
+ * @blkcnt: Number of blocks to access (within the partition)
+ * @return 0 on valid block range, or -ve on error.
+ */
+static int disk_blk_part_validate(struct udevice *dev, lbaint_t start, lbaint_t blkcnt)
{
- struct udevice *parent;
- struct disk_part *part;
- const struct blk_ops *ops;
+ struct disk_part *part = dev_get_uclass_plat(dev);
- parent = dev_get_parent(dev);
- ops = blk_get_ops(parent);
- if (!ops->write)
+ if (device_get_uclass_id(dev) != UCLASS_PARTITION)
return -ENOSYS;
- part = dev_get_uclass_plat(dev);
if (start >= part->gpt_part_info.size)
- return 0;
+ return -E2BIG;
if ((start + blkcnt) > part->gpt_part_info.size)
- blkcnt = part->gpt_part_info.size - start;
- start += part->gpt_part_info.start;
+ return -ERANGE;
- return ops->write(parent, start, blkcnt, buffer);
+ return 0;
}
-static ulong part_blk_erase(struct udevice *dev, lbaint_t start,
- lbaint_t blkcnt)
+/**
+ * disk_blk_part_offset() - Compute offset from start of block device
+ *
+ * @dev: Device (partition udevice)
+ * @start: Start block for the access (from start of partition)
+ * @return Start block for the access (from start of block device)
+ */
+static lbaint_t disk_blk_part_offset(struct udevice *dev, lbaint_t start)
{
- struct udevice *parent;
- struct disk_part *part;
- const struct blk_ops *ops;
+ struct disk_part *part = dev_get_uclass_plat(dev);
- parent = dev_get_parent(dev);
- ops = blk_get_ops(parent);
- if (!ops->erase)
- return -ENOSYS;
-
- part = dev_get_uclass_plat(dev);
- if (start >= part->gpt_part_info.size)
- return 0;
-
- if ((start + blkcnt) > part->gpt_part_info.size)
- blkcnt = part->gpt_part_info.size - start;
- start += part->gpt_part_info.start;
-
- return ops->erase(parent, start, blkcnt);
+ return start + part->gpt_part_info.start;
}
-static const struct blk_ops blk_part_ops = {
- .read = part_blk_read,
- .write = part_blk_write,
- .erase = part_blk_erase,
-};
-
-U_BOOT_DRIVER(blk_partition) = {
- .name = "blk_partition",
- .id = UCLASS_PARTITION,
- .ops = &blk_part_ops,
-};
-
/*
* BLOCK IO APIs
*/
-static struct blk_desc *dev_get_blk(struct udevice *dev)
-{
- struct blk_desc *desc;
-
- switch (device_get_uclass_id(dev)) {
- /*
- * We won't support UCLASS_BLK with dev_* interfaces.
- */
- case UCLASS_PARTITION:
- desc = dev_get_uclass_plat(dev_get_parent(dev));
- break;
- default:
- desc = NULL;
- break;
- }
-
- return desc;
-}
-
+/**
+ * disk_blk_read() - Read from a block device partition
+ *
+ * @dev: Device to read from (partition udevice)
+ * @start: Start block for the read (from start of partition)
+ * @blkcnt: Number of blocks to read (within the partition)
+ * @buffer: Place to put the data
+ * @return number of blocks read (which may be less than @blkcnt),
+ * or -ve on error. This never returns 0 unless @blkcnt is 0
+ */
unsigned long disk_blk_read(struct udevice *dev, lbaint_t start,
lbaint_t blkcnt, void *buffer)
{
- struct blk_desc *desc;
- const struct blk_ops *ops;
- struct disk_part *part;
- lbaint_t start_in_disk;
- ulong blks_read;
+ int ret = disk_blk_part_validate(dev, start, blkcnt);
- desc = dev_get_blk(dev);
- if (!desc)
- return -ENOSYS;
+ if (ret)
+ return ret;
- ops = blk_get_ops(dev);
- if (!ops->read)
- return -ENOSYS;
-
- start_in_disk = start;
- if (device_get_uclass_id(dev) == UCLASS_PARTITION) {
- part = dev_get_uclass_plat(dev);
- start_in_disk += part->gpt_part_info.start;
- }
-
- if (blkcache_read(desc->uclass_id, desc->devnum, start_in_disk, blkcnt,
- desc->blksz, buffer))
- return blkcnt;
- blks_read = ops->read(dev, start, blkcnt, buffer);
- if (blks_read == blkcnt)
- blkcache_fill(desc->uclass_id, desc->devnum, start_in_disk,
- blkcnt, desc->blksz, buffer);
-
- return blks_read;
+ return blk_read(dev_get_parent(dev), disk_blk_part_offset(dev, start),
+ blkcnt, buffer);
}
+/**
+ * disk_blk_write() - Write to a block device
+ *
+ * @dev: Device to write to (partition udevice)
+ * @start: Start block for the write (from start of partition)
+ * @blkcnt: Number of blocks to write (within the partition)
+ * @buffer: Data to write
+ * @return number of blocks written (which may be less than @blkcnt),
+ * or -ve on error. This never returns 0 unless @blkcnt is 0
+ */
unsigned long disk_blk_write(struct udevice *dev, lbaint_t start,
lbaint_t blkcnt, const void *buffer)
{
- struct blk_desc *desc;
- const struct blk_ops *ops;
+ int ret = disk_blk_part_validate(dev, start, blkcnt);
- desc = dev_get_blk(dev);
- if (!desc)
- return -ENOSYS;
+ if (ret)
+ return ret;
- ops = blk_get_ops(dev);
- if (!ops->write)
- return -ENOSYS;
-
- blkcache_invalidate(desc->uclass_id, desc->devnum);
-
- return ops->write(dev, start, blkcnt, buffer);
+ return blk_write(dev_get_parent(dev), disk_blk_part_offset(dev, start),
+ blkcnt, buffer);
}
+/**
+ * disk_blk_erase() - Erase part of a block device
+ *
+ * @dev: Device to erase (partition udevice)
+ * @start: Start block for the erase (from start of partition)
+ * @blkcnt: Number of blocks to erase (within the partition)
+ * @return number of blocks erased (which may be less than @blkcnt),
+ * or -ve on error. This never returns 0 unless @blkcnt is 0
+ */
unsigned long disk_blk_erase(struct udevice *dev, lbaint_t start,
lbaint_t blkcnt)
{
- struct blk_desc *desc;
- const struct blk_ops *ops;
+ int ret = disk_blk_part_validate(dev, start, blkcnt);
- desc = dev_get_blk(dev);
- if (!desc)
- return -ENOSYS;
+ if (ret)
+ return ret;
- ops = blk_get_ops(dev);
- if (!ops->erase)
- return -ENOSYS;
-
- blkcache_invalidate(desc->uclass_id, desc->devnum);
-
- return ops->erase(dev, start, blkcnt);
+ return blk_erase(dev_get_parent(dev), disk_blk_part_offset(dev, start),
+ blkcnt);
}
UCLASS_DRIVER(partition) = {
@@ -245,3 +128,15 @@
.per_device_plat_auto = sizeof(struct disk_part),
.name = "partition",
};
+
+static const struct blk_ops blk_part_ops = {
+ .read = disk_blk_read,
+ .write = disk_blk_write,
+ .erase = disk_blk_erase,
+};
+
+U_BOOT_DRIVER(blk_partition) = {
+ .name = "blk_partition",
+ .id = UCLASS_PARTITION,
+ .ops = &blk_part_ops,
+};
diff --git a/disk/part.c b/disk/part.c
index eec02f5..72241b7 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -26,6 +26,12 @@
/* Check all partition types */
#define PART_TYPE_ALL -1
+/**
+ * part_driver_get_type() - Get a driver given its type
+ *
+ * @part_type: Partition type to find the driver for
+ * Return: Driver for that type, or NULL if none
+ */
static struct part_driver *part_driver_get_type(int part_type)
{
struct part_driver *drv =
@@ -42,25 +48,41 @@
return NULL;
}
-static struct part_driver *part_driver_lookup_type(struct blk_desc *dev_desc)
+/**
+ * part_driver_lookup_type() - Look up the partition driver for a blk device
+ *
+ * If @desc->part_type is PART_TYPE_UNKNOWN, this checks each parition driver
+ * against the blk device to see if there is a valid partition table acceptable
+ * to that driver.
+ *
+ * If @desc->part_type is already set, it just returns the driver for that
+ * type, without testing if the driver can find a valid partition on the
+ * descriptor.
+ *
+ * On success it updates @desc->part_type if set to PART_TYPE_UNKNOWN on entry
+ *
+ * @dev_desc: Device descriptor
+ * Return: Driver found, or NULL if none
+ */
+static struct part_driver *part_driver_lookup_type(struct blk_desc *desc)
{
struct part_driver *drv =
ll_entry_start(struct part_driver, part_driver);
const int n_ents = ll_entry_count(struct part_driver, part_driver);
struct part_driver *entry;
- if (dev_desc->part_type == PART_TYPE_UNKNOWN) {
+ if (desc->part_type == PART_TYPE_UNKNOWN) {
for (entry = drv; entry != drv + n_ents; entry++) {
int ret;
- ret = entry->test(dev_desc);
+ ret = entry->test(desc);
if (!ret) {
- dev_desc->part_type = entry->part_type;
+ desc->part_type = entry->part_type;
return entry;
}
}
} else {
- return part_driver_get_type(dev_desc->part_type);
+ return part_driver_get_type(desc->part_type);
}
/* Not found */
@@ -83,27 +105,37 @@
return PART_TYPE_UNKNOWN;
}
+/**
+ * get_dev_hwpart() - Get the descriptor for a device with hardware partitions
+ *
+ * @ifname: Interface name (e.g. "ide", "scsi")
+ * @dev: Device number (0 for first device on that interface, 1 for
+ * second, etc.
+ * @hwpart: Hardware partition, or 0 if none (used for MMC)
+ * Return: pointer to the block device, or NULL if not available, or an
+ * error occurred.
+ */
static struct blk_desc *get_dev_hwpart(const char *ifname, int dev, int hwpart)
{
- struct blk_desc *dev_desc;
+ struct blk_desc *desc;
int ret;
if (!blk_enabled())
return NULL;
- dev_desc = blk_get_devnum_by_uclass_idname(ifname, dev);
- if (!dev_desc) {
+ desc = blk_get_devnum_by_uclass_idname(ifname, dev);
+ if (!desc) {
debug("%s: No device for iface '%s', dev %d\n", __func__,
ifname, dev);
return NULL;
}
- ret = blk_dselect_hwpart(dev_desc, hwpart);
+ ret = blk_dselect_hwpart(desc, hwpart);
if (ret) {
debug("%s: Failed to select h/w partition: err-%d\n", __func__,
ret);
return NULL;
}
- return dev_desc;
+ return desc;
}
struct blk_desc *blk_get_dev(const char *ifname, int dev)
@@ -140,29 +172,24 @@
return bc_quot * mul_by + ((bc_rem * mul_by) >> right_shift);
}
-void dev_print(struct blk_desc *dev_desc)
+void dev_print(struct blk_desc *desc)
{
lba512_t lba512; /* number of blocks if 512bytes block size */
- if (dev_desc->type == DEV_TYPE_UNKNOWN) {
+ if (desc->type == DEV_TYPE_UNKNOWN) {
puts ("not available\n");
return;
}
- switch (dev_desc->uclass_id) {
+ switch (desc->uclass_id) {
case UCLASS_SCSI:
- printf ("(%d:%d) Vendor: %s Prod.: %s Rev: %s\n",
- dev_desc->target,dev_desc->lun,
- dev_desc->vendor,
- dev_desc->product,
- dev_desc->revision);
+ printf("(%d:%d) Vendor: %s Prod.: %s Rev: %s\n", desc->target,
+ desc->lun, desc->vendor, desc->product, desc->revision);
break;
case UCLASS_IDE:
case UCLASS_AHCI:
- printf ("Model: %s Firm: %s Ser#: %s\n",
- dev_desc->vendor,
- dev_desc->revision,
- dev_desc->product);
+ printf("Model: %s Firm: %s Ser#: %s\n", desc->vendor,
+ desc->revision, desc->product);
break;
case UCLASS_MMC:
case UCLASS_USB:
@@ -171,27 +198,27 @@
case UCLASS_HOST:
case UCLASS_BLKMAP:
printf ("Vendor: %s Rev: %s Prod: %s\n",
- dev_desc->vendor,
- dev_desc->revision,
- dev_desc->product);
+ desc->vendor,
+ desc->revision,
+ desc->product);
break;
case UCLASS_VIRTIO:
- printf("%s VirtIO Block Device\n", dev_desc->vendor);
+ printf("%s VirtIO Block Device\n", desc->vendor);
break;
case UCLASS_EFI_MEDIA:
- printf("EFI media Block Device %d\n", dev_desc->devnum);
+ printf("EFI media Block Device %d\n", desc->devnum);
break;
case UCLASS_INVALID:
puts("device type unknown\n");
return;
default:
- printf("Unhandled device type: %i\n", dev_desc->uclass_id);
+ printf("Unhandled device type: %i\n", desc->uclass_id);
return;
}
puts (" Type: ");
- if (dev_desc->removable)
+ if (desc->removable)
puts ("Removable ");
- switch (dev_desc->type & 0x1F) {
+ switch (desc->type & 0x1F) {
case DEV_TYPE_HARDDISK:
puts ("Hard Disk");
break;
@@ -205,17 +232,17 @@
puts ("Tape");
break;
default:
- printf ("# %02X #", dev_desc->type & 0x1F);
+ printf("# %02X #", desc->type & 0x1F);
break;
}
puts ("\n");
- if (dev_desc->lba > 0L && dev_desc->blksz > 0L) {
+ if (desc->lba > 0L && desc->blksz > 0L) {
ulong mb, mb_quot, mb_rem, gb, gb_quot, gb_rem;
lbaint_t lba;
- lba = dev_desc->lba;
+ lba = desc->lba;
- lba512 = (lba * (dev_desc->blksz/512));
+ lba512 = lba * (desc->blksz / 512);
/* round to 1 digit */
/* 2048 = (1024 * 1024) / 512 MB */
mb = lba512_muldiv(lba512, 10, 11);
@@ -227,7 +254,7 @@
gb_quot = gb / 10;
gb_rem = gb - (10 * gb_quot);
#ifdef CONFIG_LBA48
- if (dev_desc->lba48)
+ if (desc->lba48)
printf (" Supports 48-bit addressing\n");
#endif
#if defined(CONFIG_SYS_64BIT_LBA)
@@ -235,42 +262,42 @@
mb_quot, mb_rem,
gb_quot, gb_rem,
lba,
- dev_desc->blksz);
+ desc->blksz);
#else
printf (" Capacity: %lu.%lu MB = %lu.%lu GB (%lu x %lu)\n",
mb_quot, mb_rem,
gb_quot, gb_rem,
(ulong)lba,
- dev_desc->blksz);
+ desc->blksz);
#endif
} else {
puts (" Capacity: not available\n");
}
}
-void part_init(struct blk_desc *dev_desc)
+void part_init(struct blk_desc *desc)
{
struct part_driver *drv =
ll_entry_start(struct part_driver, part_driver);
const int n_ents = ll_entry_count(struct part_driver, part_driver);
struct part_driver *entry;
- blkcache_invalidate(dev_desc->uclass_id, dev_desc->devnum);
+ blkcache_invalidate(desc->uclass_id, desc->devnum);
- dev_desc->part_type = PART_TYPE_UNKNOWN;
+ desc->part_type = PART_TYPE_UNKNOWN;
for (entry = drv; entry != drv + n_ents; entry++) {
int ret;
- ret = entry->test(dev_desc);
+ ret = entry->test(desc);
debug("%s: try '%s': ret=%d\n", __func__, entry->name, ret);
if (!ret) {
- dev_desc->part_type = entry->part_type;
+ desc->part_type = entry->part_type;
break;
}
}
}
-static void print_part_header(const char *type, struct blk_desc *dev_desc)
+static void print_part_header(const char *type, struct blk_desc *desc)
{
#if CONFIG_IS_ENABLED(MAC_PARTITION) || \
CONFIG_IS_ENABLED(DOS_PARTITION) || \
@@ -278,7 +305,7 @@
CONFIG_IS_ENABLED(AMIGA_PARTITION) || \
CONFIG_IS_ENABLED(EFI_PARTITION)
puts ("\nPartition Map for ");
- switch (dev_desc->uclass_id) {
+ switch (desc->uclass_id) {
case UCLASS_IDE:
puts ("IDE");
break;
@@ -314,50 +341,46 @@
break;
}
printf (" device %d -- Partition Type: %s\n\n",
- dev_desc->devnum, type);
+ desc->devnum, type);
#endif /* any CONFIG_..._PARTITION */
}
-void part_print(struct blk_desc *dev_desc)
+void part_print(struct blk_desc *desc)
{
struct part_driver *drv;
- drv = part_driver_lookup_type(dev_desc);
+ drv = part_driver_lookup_type(desc);
if (!drv) {
printf("## Unknown partition table type %x\n",
- dev_desc->part_type);
+ desc->part_type);
return;
}
PRINTF("## Testing for valid %s partition ##\n", drv->name);
- print_part_header(drv->name, dev_desc);
+ print_part_header(drv->name, desc);
if (drv->print)
- drv->print(dev_desc);
+ drv->print(desc);
}
-int part_get_info_by_type(struct blk_desc *dev_desc, int part, int part_type,
+int part_get_info_by_type(struct blk_desc *desc, int part, int part_type,
struct disk_partition *info)
{
struct part_driver *drv;
if (blk_enabled()) {
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
/* The common case is no UUID support */
- info->uuid[0] = 0;
-#endif
-#ifdef CONFIG_PARTITION_TYPE_GUID
- info->type_guid[0] = 0;
-#endif
+ disk_partition_clr_uuid(info);
+ disk_partition_clr_type_guid(info);
if (part_type == PART_TYPE_UNKNOWN) {
- drv = part_driver_lookup_type(dev_desc);
+ drv = part_driver_lookup_type(desc);
} else {
drv = part_driver_get_type(part_type);
}
if (!drv) {
debug("## Unknown partition table type %x\n",
- dev_desc->part_type);
+ desc->part_type);
return -EPROTONOSUPPORT;
}
if (!drv->get_info) {
@@ -365,7 +388,7 @@
drv->name);
return -ENOSYS;
}
- if (drv->get_info(dev_desc, part, info) == 0) {
+ if (drv->get_info(desc, part, info) == 0) {
PRINTF("## Valid %s partition found ##\n", drv->name);
return 0;
}
@@ -374,33 +397,29 @@
return -ENOENT;
}
-int part_get_info(struct blk_desc *dev_desc, int part,
+int part_get_info(struct blk_desc *desc, int part,
struct disk_partition *info)
{
- return part_get_info_by_type(dev_desc, part, PART_TYPE_UNKNOWN, info);
+ return part_get_info_by_type(desc, part, PART_TYPE_UNKNOWN, info);
}
-int part_get_info_whole_disk(struct blk_desc *dev_desc,
+int part_get_info_whole_disk(struct blk_desc *desc,
struct disk_partition *info)
{
info->start = 0;
- info->size = dev_desc->lba;
- info->blksz = dev_desc->blksz;
+ info->size = desc->lba;
+ info->blksz = desc->blksz;
info->bootable = 0;
strcpy((char *)info->type, BOOT_PART_TYPE);
strcpy((char *)info->name, "Whole Disk");
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- info->uuid[0] = 0;
-#endif
-#ifdef CONFIG_PARTITION_TYPE_GUID
- info->type_guid[0] = 0;
-#endif
+ disk_partition_clr_uuid(info);
+ disk_partition_clr_type_guid(info);
return 0;
}
int blk_get_device_by_str(const char *ifname, const char *dev_hwpart_str,
- struct blk_desc **dev_desc)
+ struct blk_desc **desc)
{
char *ep;
char *dup_str = NULL;
@@ -436,8 +455,8 @@
}
}
- *dev_desc = get_dev_hwpart(ifname, dev, hwpart);
- if (!(*dev_desc) || ((*dev_desc)->type == DEV_TYPE_UNKNOWN)) {
+ *desc = get_dev_hwpart(ifname, dev, hwpart);
+ if (!(*desc) || ((*desc)->type == DEV_TYPE_UNKNOWN)) {
debug("** Bad device %s %s **\n", ifname, dev_hwpart_str);
dev = -ENODEV;
goto cleanup;
@@ -449,8 +468,8 @@
* Always should be done, otherwise hw partition 0 will return
* stale data after displaying a non-zero hw partition.
*/
- if ((*dev_desc)->uclass_id == UCLASS_MMC)
- part_init(*dev_desc);
+ if ((*desc)->uclass_id == UCLASS_MMC)
+ part_init(*desc);
}
cleanup:
@@ -461,7 +480,7 @@
#define PART_UNSPECIFIED -2
#define PART_AUTO -1
int blk_get_device_part_str(const char *ifname, const char *dev_part_str,
- struct blk_desc **dev_desc,
+ struct blk_desc **desc,
struct disk_partition *info, int allow_whole_dev)
{
int ret;
@@ -474,7 +493,7 @@
int part;
struct disk_partition tmpinfo;
- *dev_desc = NULL;
+ *desc = NULL;
memset(info, 0, sizeof(*info));
#if IS_ENABLED(CONFIG_SANDBOX) || IS_ENABLED(CONFIG_SEMIHOSTING)
@@ -533,7 +552,7 @@
}
/* Look up the device */
- dev = blk_get_device_by_str(ifname, dev_str, dev_desc);
+ dev = blk_get_device_by_str(ifname, dev_str, desc);
if (dev < 0) {
printf("** Bad device specification %s %s **\n",
ifname, dev_str);
@@ -565,9 +584,8 @@
* No partition table on device,
* or user requested partition 0 (entire device).
*/
- if (((*dev_desc)->part_type == PART_TYPE_UNKNOWN) ||
- (part == 0)) {
- if (!(*dev_desc)->lba) {
+ if (((*desc)->part_type == PART_TYPE_UNKNOWN) || !part) {
+ if (!(*desc)->lba) {
printf("** Bad device size - %s %s **\n", ifname,
dev_str);
ret = -EINVAL;
@@ -586,9 +604,9 @@
goto cleanup;
}
- (*dev_desc)->log2blksz = LOG2((*dev_desc)->blksz);
+ (*desc)->log2blksz = LOG2((*desc)->blksz);
- part_get_info_whole_disk(*dev_desc, info);
+ part_get_info_whole_disk(*desc, info);
ret = 0;
goto cleanup;
@@ -606,7 +624,7 @@
* other than "auto", use that partition number directly.
*/
if (part != PART_AUTO) {
- ret = part_get_info(*dev_desc, part, info);
+ ret = part_get_info(*desc, part, info);
if (ret) {
printf("** Invalid partition %d **\n", part);
goto cleanup;
@@ -618,7 +636,7 @@
*/
part = 0;
for (p = 1; p <= MAX_SEARCH_PARTITIONS; p++) {
- ret = part_get_info(*dev_desc, p, info);
+ ret = part_get_info(*desc, p, info);
if (ret)
continue;
@@ -662,7 +680,7 @@
goto cleanup;
}
- (*dev_desc)->log2blksz = LOG2((*dev_desc)->blksz);
+ (*desc)->log2blksz = LOG2((*desc)->blksz);
ret = part;
goto cleanup;
@@ -672,14 +690,14 @@
return ret;
}
-int part_get_info_by_name(struct blk_desc *dev_desc, const char *name,
+int part_get_info_by_name(struct blk_desc *desc, const char *name,
struct disk_partition *info)
{
struct part_driver *part_drv;
int ret;
int i;
- part_drv = part_driver_lookup_type(dev_desc);
+ part_drv = part_driver_lookup_type(desc);
if (!part_drv)
return -1;
@@ -690,7 +708,7 @@
}
for (i = 1; i < part_drv->max_entries; i++) {
- ret = part_drv->get_info(dev_desc, i, info);
+ ret = part_drv->get_info(desc, i, info);
if (ret != 0) {
/* no more entries in table */
break;
@@ -710,18 +728,18 @@
* Parse a device number and partition name string in the form of
* "devicenum.hwpartnum#partition_name", for example "0.1#misc". devicenum and
* hwpartnum are both optional, defaulting to 0. If the partition is found,
- * sets dev_desc and part_info accordingly with the information of the
+ * sets desc and part_info accordingly with the information of the
* partition with the given partition_name.
*
* @param[in] dev_iface Device interface
* @param[in] dev_part_str Input string argument, like "0.1#misc"
- * @param[out] dev_desc Place to store the device description pointer
+ * @param[out] desc Place to store the device description pointer
* @param[out] part_info Place to store the partition information
* Return: 0 on success, or a negative on error
*/
static int part_get_info_by_dev_and_name(const char *dev_iface,
const char *dev_part_str,
- struct blk_desc **dev_desc,
+ struct blk_desc **desc,
struct disk_partition *part_info)
{
char *dup_str = NULL;
@@ -743,11 +761,11 @@
return -EINVAL;
}
- ret = blk_get_device_by_str(dev_iface, dev_str, dev_desc);
+ ret = blk_get_device_by_str(dev_iface, dev_str, desc);
if (ret < 0)
goto cleanup;
- ret = part_get_info_by_name(*dev_desc, part_str, part_info);
+ ret = part_get_info_by_name(*desc, part_str, part_info);
if (ret < 0)
printf("Could not find \"%s\" partition\n", part_str);
@@ -758,35 +776,35 @@
int part_get_info_by_dev_and_name_or_num(const char *dev_iface,
const char *dev_part_str,
- struct blk_desc **dev_desc,
+ struct blk_desc **desc,
struct disk_partition *part_info,
int allow_whole_dev)
{
int ret;
/* Split the part_name if passed as "$dev_num#part_name". */
- ret = part_get_info_by_dev_and_name(dev_iface, dev_part_str,
- dev_desc, part_info);
+ ret = part_get_info_by_dev_and_name(dev_iface, dev_part_str, desc,
+ part_info);
if (ret >= 0)
return ret;
/*
* Couldn't lookup by name, try looking up the partition description
* directly.
*/
- ret = blk_get_device_part_str(dev_iface, dev_part_str,
- dev_desc, part_info, allow_whole_dev);
+ ret = blk_get_device_part_str(dev_iface, dev_part_str, desc, part_info,
+ allow_whole_dev);
if (ret < 0)
printf("Couldn't find partition %s %s\n",
dev_iface, dev_part_str);
return ret;
}
-void part_set_generic_name(const struct blk_desc *dev_desc,
- int part_num, char *name)
+void part_set_generic_name(const struct blk_desc *desc, int part_num,
+ char *name)
{
char *devtype;
- switch (dev_desc->uclass_id) {
+ switch (desc->uclass_id) {
case UCLASS_IDE:
case UCLASS_AHCI:
devtype = "hd";
@@ -805,7 +823,7 @@
break;
}
- sprintf(name, "%s%c%d", devtype, 'a' + dev_desc->devnum, part_num);
+ sprintf(name, "%s%c%d", devtype, 'a' + desc->devnum, part_num);
}
int part_get_bootable(struct blk_desc *desc)
diff --git a/disk/part_amiga.c b/disk/part_amiga.c
index 45d3a70..65e30fe 100644
--- a/disk/part_amiga.c
+++ b/disk/part_amiga.c
@@ -125,7 +125,7 @@
* the ID AMIGA_ID_RDISK ('RDSK') and needs to have a valid
* sum-to-zero checksum
*/
-struct rigid_disk_block *get_rdisk(struct blk_desc *dev_desc)
+struct rigid_disk_block *get_rdisk(struct blk_desc *desc)
{
int i;
int limit;
@@ -139,7 +139,7 @@
for (i=0; i<limit; i++)
{
- ulong res = blk_dread(dev_desc, i, 1, (ulong *)block_buffer);
+ ulong res = blk_dread(desc, i, 1, (ulong *)block_buffer);
if (res == 1)
{
struct rigid_disk_block *trdb = (struct rigid_disk_block *)block_buffer;
@@ -165,7 +165,7 @@
* Ridgid disk block
*/
-struct bootcode_block *get_bootcode(struct blk_desc *dev_desc)
+struct bootcode_block *get_bootcode(struct blk_desc *desc)
{
int i;
int limit;
@@ -181,7 +181,7 @@
for (i = 0; i < limit; i++)
{
- ulong res = blk_dread(dev_desc, i, 1, (ulong *)block_buffer);
+ ulong res = blk_dread(desc, i, 1, (ulong *)block_buffer);
if (res == 1)
{
struct bootcode_block *boot = (struct bootcode_block *)block_buffer;
@@ -206,17 +206,17 @@
* Test if the given partition has an Amiga partition table/Rigid
* Disk block
*/
-static int part_test_amiga(struct blk_desc *dev_desc)
+static int part_test_amiga(struct blk_desc *desc)
{
struct rigid_disk_block *rdb;
struct bootcode_block *bootcode;
PRINTF("part_test_amiga: Testing for an Amiga RDB partition\n");
- rdb = get_rdisk(dev_desc);
+ rdb = get_rdisk(desc);
if (rdb)
{
- bootcode = get_bootcode(dev_desc);
+ bootcode = get_bootcode(desc);
if (bootcode)
PRINTF("part_test_amiga: bootable Amiga disk\n");
else
@@ -235,7 +235,7 @@
/*
* Find partition number partnum on the given drive.
*/
-static struct partition_block *find_partition(struct blk_desc *dev_desc,
+static struct partition_block *find_partition(struct blk_desc *desc,
int partnum)
{
struct rigid_disk_block *rdb;
@@ -243,7 +243,7 @@
u32 block;
PRINTF("Trying to find partition block %d\n", partnum);
- rdb = get_rdisk(dev_desc);
+ rdb = get_rdisk(desc);
if (!rdb)
{
PRINTF("find_partition: no rdb found\n");
@@ -257,7 +257,7 @@
while (block != 0xFFFFFFFF)
{
- ulong res = blk_dread(dev_desc, block, 1, (ulong *)block_buffer);
+ ulong res = blk_dread(desc, block, 1, (ulong *)block_buffer);
if (res == 1)
{
p = (struct partition_block *)block_buffer;
@@ -289,10 +289,10 @@
/*
* Get info about a partition
*/
-static int part_get_info_amiga(struct blk_desc *dev_desc, int part,
- struct disk_partition *info)
+static int part_get_info_amiga(struct blk_desc *desc, int part,
+ struct disk_partition *info)
{
- struct partition_block *p = find_partition(dev_desc, part-1);
+ struct partition_block *p = find_partition(desc, part - 1);
struct amiga_part_geometry *g;
u32 disk_type;
@@ -317,7 +317,7 @@
return 0;
}
-static void part_print_amiga(struct blk_desc *dev_desc)
+static void part_print_amiga(struct blk_desc *desc)
{
struct rigid_disk_block *rdb;
struct bootcode_block *boot;
@@ -325,7 +325,7 @@
u32 block;
int i = 1;
- rdb = get_rdisk(dev_desc);
+ rdb = get_rdisk(desc);
if (!rdb)
{
PRINTF("part_print_amiga: no rdb found\n");
@@ -353,7 +353,7 @@
PRINTF("Trying to load block #0x%X\n", block);
- res = blk_dread(dev_desc, block, 1, (ulong *)block_buffer);
+ res = blk_dread(desc, block, 1, (ulong *)block_buffer);
if (res == 1)
{
p = (struct partition_block *)block_buffer;
@@ -370,7 +370,7 @@
} else block = 0xFFFFFFFF;
}
- boot = get_bootcode(dev_desc);
+ boot = get_bootcode(desc);
if (boot)
{
printf("Disk is bootable\n");
diff --git a/disk/part_dos.c b/disk/part_dos.c
index 56e6188..3337438 100644
--- a/disk/part_dos.c
+++ b/disk/part_dos.c
@@ -98,27 +98,26 @@
return -1;
}
-static int part_test_dos(struct blk_desc *dev_desc)
+static int part_test_dos(struct blk_desc *desc)
{
#ifndef CONFIG_SPL_BUILD
ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, mbr,
- DIV_ROUND_UP(dev_desc->blksz, sizeof(legacy_mbr)));
+ DIV_ROUND_UP(desc->blksz, sizeof(legacy_mbr)));
- if (blk_dread(dev_desc, 0, 1, (ulong *)mbr) != 1)
+ if (blk_dread(desc, 0, 1, (ulong *)mbr) != 1)
return -1;
if (test_block_type((unsigned char *)mbr) != DOS_MBR)
return -1;
- if (dev_desc->sig_type == SIG_TYPE_NONE &&
- mbr->unique_mbr_signature != 0) {
- dev_desc->sig_type = SIG_TYPE_MBR;
- dev_desc->mbr_sig = mbr->unique_mbr_signature;
+ if (desc->sig_type == SIG_TYPE_NONE && mbr->unique_mbr_signature) {
+ desc->sig_type = SIG_TYPE_MBR;
+ desc->mbr_sig = mbr->unique_mbr_signature;
}
#else
- ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, desc->blksz);
- if (blk_dread(dev_desc, 0, 1, (ulong *)buffer) != 1)
+ if (blk_dread(desc, 0, 1, (ulong *)buffer) != 1)
return -1;
if (test_block_type(buffer) != DOS_MBR)
@@ -130,12 +129,12 @@
/* Print a partition that is relative to its Extended partition table
*/
-static void print_partition_extended(struct blk_desc *dev_desc,
+static void print_partition_extended(struct blk_desc *desc,
lbaint_t ext_part_sector,
lbaint_t relative,
int part_num, unsigned int disksig)
{
- ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, desc->blksz);
dos_partition_t *pt;
int i;
@@ -146,9 +145,9 @@
return;
}
- if (blk_dread(dev_desc, ext_part_sector, 1, (ulong *)buffer) != 1) {
+ if (blk_dread(desc, ext_part_sector, 1, (ulong *)buffer) != 1) {
printf ("** Can't read partition table on %d:" LBAFU " **\n",
- dev_desc->devnum, ext_part_sector);
+ desc->devnum, ext_part_sector);
return;
}
i=test_block_type(buffer);
@@ -189,9 +188,9 @@
lbaint_t lba_start
= get_unaligned_le32 (pt->start4) + relative;
- print_partition_extended(dev_desc, lba_start,
- ext_part_sector == 0 ? lba_start : relative,
- part_num, disksig);
+ print_partition_extended(desc, lba_start,
+ !ext_part_sector ? lba_start :
+ relative, part_num, disksig);
}
}
@@ -201,14 +200,15 @@
/* Print a partition that is relative to its Extended partition table
*/
-static int part_get_info_extended(struct blk_desc *dev_desc,
+static int part_get_info_extended(struct blk_desc *desc,
lbaint_t ext_part_sector, lbaint_t relative,
int part_num, int which_part,
struct disk_partition *info, uint disksig)
{
- ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, desc->blksz);
+ struct disk_partition wdinfo = { 0 };
dos_partition_t *pt;
- int i;
+ int i, ret;
int dos_type;
/* set a maximum recursion level */
@@ -218,9 +218,9 @@
return -1;
}
- if (blk_dread(dev_desc, ext_part_sector, 1, (ulong *)buffer) != 1) {
+ if (blk_dread(desc, ext_part_sector, 1, (ulong *)buffer) != 1) {
printf ("** Can't read partition table on %d:" LBAFU " **\n",
- dev_desc->devnum, ext_part_sector);
+ desc->devnum, ext_part_sector);
return -1;
}
if (buffer[DOS_PART_MAGIC_OFFSET] != 0x55 ||
@@ -231,10 +231,12 @@
return -1;
}
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- if (!ext_part_sector)
+ if (CONFIG_IS_ENABLED(PARTITION_UUIDS) && !ext_part_sector)
disksig = get_unaligned_le32(&buffer[DOS_PART_DISKSIG_OFFSET]);
-#endif
+
+ ret = part_get_info_whole_disk(desc, &wdinfo);
+ if (ret)
+ return ret;
/* Print all primary/logical partitions */
pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET);
@@ -247,18 +249,24 @@
(pt->sys_ind != 0) &&
(part_num == which_part) &&
(ext_part_sector == 0 || is_extended(pt->sys_ind) == 0)) {
- info->blksz = DOS_PART_DEFAULT_SECTOR;
+ if (wdinfo.blksz > DOS_PART_DEFAULT_SECTOR)
+ info->blksz = wdinfo.blksz;
+ else
+ info->blksz = DOS_PART_DEFAULT_SECTOR;
info->start = (lbaint_t)(ext_part_sector +
get_unaligned_le32(pt->start4));
info->size = (lbaint_t)get_unaligned_le32(pt->size4);
- part_set_generic_name(dev_desc, part_num,
+ part_set_generic_name(desc, part_num,
(char *)info->name);
/* sprintf(info->type, "%d, pt->sys_ind); */
strcpy((char *)info->type, "U-Boot");
info->bootable = get_bootable(pt);
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- sprintf(info->uuid, "%08x-%02x", disksig, part_num);
-#endif
+ if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) {
+ char str[12];
+
+ sprintf(str, "%08x-%02x", disksig, part_num);
+ disk_partition_set_uuid(info, str);
+ }
info->sys_ind = pt->sys_ind;
return 0;
}
@@ -277,7 +285,7 @@
lbaint_t lba_start
= get_unaligned_le32 (pt->start4) + relative;
- return part_get_info_extended(dev_desc, lba_start,
+ return part_get_info_extended(desc, lba_start,
ext_part_sector == 0 ? lba_start : relative,
part_num, which_part, info, disksig);
}
@@ -288,29 +296,30 @@
if (dos_type == DOS_PBR) {
info->start = 0;
- info->size = dev_desc->lba;
- info->blksz = DOS_PART_DEFAULT_SECTOR;
+ info->size = desc->lba;
+ if (wdinfo.blksz > DOS_PART_DEFAULT_SECTOR)
+ info->blksz = wdinfo.blksz;
+ else
+ info->blksz = DOS_PART_DEFAULT_SECTOR;
info->bootable = 0;
strcpy((char *)info->type, "U-Boot");
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- info->uuid[0] = 0;
-#endif
+ disk_partition_clr_uuid(info);
return 0;
}
return -1;
}
-static void __maybe_unused part_print_dos(struct blk_desc *dev_desc)
+static void __maybe_unused part_print_dos(struct blk_desc *desc)
{
printf("Part\tStart Sector\tNum Sectors\tUUID\t\tType\n");
- print_partition_extended(dev_desc, 0, 0, 1, 0);
+ print_partition_extended(desc, 0, 0, 1, 0);
}
-static int __maybe_unused part_get_info_dos(struct blk_desc *dev_desc, int part,
- struct disk_partition *info)
+static int __maybe_unused part_get_info_dos(struct blk_desc *desc, int part,
+ struct disk_partition *info)
{
- return part_get_info_extended(dev_desc, 0, 0, 1, part, info, 0);
+ return part_get_info_extended(desc, 0, 0, 1, part, info, 0);
}
int is_valid_dos_buf(void *buf)
@@ -490,20 +499,20 @@
}
#endif
-int write_mbr_sector(struct blk_desc *dev_desc, void *buf)
+int write_mbr_sector(struct blk_desc *desc, void *buf)
{
if (is_valid_dos_buf(buf))
return -1;
/* write MBR */
- if (blk_dwrite(dev_desc, 0, 1, buf) != 1) {
+ if (blk_dwrite(desc, 0, 1, buf) != 1) {
printf("%s: failed writing '%s' (1 blks at 0x0)\n",
__func__, "MBR");
return 1;
}
/* Update the partition table entries*/
- part_init(dev_desc);
+ part_init(desc);
return 0;
}
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 80a44dc..39382c5 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -9,6 +9,9 @@
* when CONFIG_SYS_64BIT_LBA is not defined, lbaint_t is 32 bits; this
* limits the maximum size of addressable storage to < 2 tebibytes
*/
+
+#define LOG_CATEGORY LOGC_FS
+
#include <common.h>
#include <blk.h>
#include <log.h>
@@ -51,12 +54,12 @@
static int pmbr_part_valid(struct partition *part);
static int is_pmbr_valid(legacy_mbr * mbr);
-static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba,
- gpt_header *pgpt_head, gpt_entry **pgpt_pte);
-static gpt_entry *alloc_read_gpt_entries(struct blk_desc *dev_desc,
+static int is_gpt_valid(struct blk_desc *desc, u64 lba, gpt_header *pgpt_head,
+ gpt_entry **pgpt_pte);
+static gpt_entry *alloc_read_gpt_entries(struct blk_desc *desc,
gpt_header *pgpt_head);
static int is_pte_valid(gpt_entry * pte);
-static int find_valid_gpt(struct blk_desc *dev_desc, gpt_header *gpt_head,
+static int find_valid_gpt(struct blk_desc *desc, gpt_header *gpt_head,
gpt_entry **pgpt_pte);
static char *print_efiname(gpt_entry *pte)
@@ -195,14 +198,14 @@
* UUID is displayed as 32 hexadecimal digits, in 5 groups,
* separated by hyphens, in the form 8-4-4-4-12 for a total of 36 characters
*/
-int get_disk_guid(struct blk_desc * dev_desc, char *guid)
+int get_disk_guid(struct blk_desc *desc, char *guid)
{
- ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz);
gpt_entry *gpt_pte = NULL;
unsigned char *guid_bin;
/* This function validates AND fills in the GPT header and PTE */
- if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1)
+ if (find_valid_gpt(desc, gpt_head, &gpt_pte) != 1)
return -EINVAL;
guid_bin = gpt_head->disk_guid.b;
@@ -213,15 +216,15 @@
return 0;
}
-void part_print_efi(struct blk_desc *dev_desc)
+void part_print_efi(struct blk_desc *desc)
{
- ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz);
gpt_entry *gpt_pte = NULL;
int i = 0;
unsigned char *uuid;
/* This function validates AND fills in the GPT header and PTE */
- if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1)
+ if (find_valid_gpt(desc, gpt_head, &gpt_pte) != 1)
return;
debug("%s: gpt-entry at %p\n", __func__, gpt_pte);
@@ -255,10 +258,10 @@
return;
}
-int part_get_info_efi(struct blk_desc *dev_desc, int part,
+int part_get_info_efi(struct blk_desc *desc, int part,
struct disk_partition *info)
{
- ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz);
gpt_entry *gpt_pte = NULL;
/* "part" argument must be at least 1 */
@@ -268,7 +271,7 @@
}
/* This function validates AND fills in the GPT header and PTE */
- if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1)
+ if (find_valid_gpt(desc, gpt_head, &gpt_pte) != 1)
return -EINVAL;
if (part > le32_to_cpu(gpt_head->num_partition_entries) ||
@@ -283,20 +286,22 @@
/* The ending LBA is inclusive, to calculate size, add 1 to it */
info->size = (lbaint_t)le64_to_cpu(gpt_pte[part - 1].ending_lba) + 1
- info->start;
- info->blksz = dev_desc->blksz;
+ info->blksz = desc->blksz;
snprintf((char *)info->name, sizeof(info->name), "%s",
print_efiname(&gpt_pte[part - 1]));
strcpy((char *)info->type, "U-Boot");
info->bootable = get_bootable(&gpt_pte[part - 1]);
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, info->uuid,
- UUID_STR_FORMAT_GUID);
-#endif
-#ifdef CONFIG_PARTITION_TYPE_GUID
- uuid_bin_to_str(gpt_pte[part - 1].partition_type_guid.b,
- info->type_guid, UUID_STR_FORMAT_GUID);
-#endif
+ if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) {
+ uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b,
+ (char *)disk_partition_uuid(info),
+ UUID_STR_FORMAT_GUID);
+ }
+ if (IS_ENABLED(CONFIG_PARTITION_TYPE_GUID)) {
+ uuid_bin_to_str(gpt_pte[part - 1].partition_type_guid.b,
+ (char *)disk_partition_type_uuid(info),
+ UUID_STR_FORMAT_GUID);
+ }
log_debug("start 0x" LBAF ", size 0x" LBAF ", name %s\n", info->start,
info->size, info->name);
@@ -306,12 +311,12 @@
return 0;
}
-static int part_test_efi(struct blk_desc *dev_desc)
+static int part_test_efi(struct blk_desc *desc)
{
- ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, legacymbr, 1, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, legacymbr, 1, desc->blksz);
/* Read legacy MBR from block 0 and validate it */
- if ((blk_dread(dev_desc, 0, 1, (ulong *)legacymbr) != 1)
+ if ((blk_dread(desc, 0, 1, (ulong *)legacymbr) != 1)
|| (is_pmbr_valid(legacymbr) != 1)) {
return -1;
}
@@ -320,23 +325,23 @@
/**
* set_protective_mbr(): Set the EFI protective MBR
- * @param dev_desc - block device descriptor
+ * @param desc - block device descriptor
*
* Return: - zero on success, otherwise error
*/
-static int set_protective_mbr(struct blk_desc *dev_desc)
+static int set_protective_mbr(struct blk_desc *desc)
{
/* Setup the Protective MBR */
- ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, p_mbr, 1, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, p_mbr, 1, desc->blksz);
if (p_mbr == NULL) {
log_debug("calloc failed!\n");
return -ENOMEM;
}
/* Read MBR to backup boot code if it exists */
- if (blk_dread(dev_desc, 0, 1, p_mbr) != 1) {
+ if (blk_dread(desc, 0, 1, p_mbr) != 1) {
log_debug("** Can't read from device %d **\n",
- dev_desc->devnum);
+ desc->devnum);
return -EIO;
}
@@ -348,27 +353,26 @@
p_mbr->signature = MSDOS_MBR_SIGNATURE;
p_mbr->partition_record[0].sys_ind = EFI_PMBR_OSTYPE_EFI_GPT;
p_mbr->partition_record[0].start_sect = 1;
- p_mbr->partition_record[0].nr_sects = (u32) dev_desc->lba - 1;
+ p_mbr->partition_record[0].nr_sects = (u32)desc->lba - 1;
/* Write MBR sector to the MMC device */
- if (blk_dwrite(dev_desc, 0, 1, p_mbr) != 1) {
- log_debug("** Can't write to device %d **\n", dev_desc->devnum);
+ if (blk_dwrite(desc, 0, 1, p_mbr) != 1) {
+ log_debug("** Can't write to device %d **\n", desc->devnum);
return -EIO;
}
return 0;
}
-int write_gpt_table(struct blk_desc *dev_desc,
- gpt_header *gpt_h, gpt_entry *gpt_e)
+int write_gpt_table(struct blk_desc *desc, gpt_header *gpt_h, gpt_entry *gpt_e)
{
const int pte_blk_cnt = BLOCK_CNT((gpt_h->num_partition_entries
- * sizeof(gpt_entry)), dev_desc);
+ * sizeof(gpt_entry)), desc);
u32 calc_crc32;
- debug("max lba: %x\n", (u32) dev_desc->lba);
+ debug("max lba: %x\n", (u32)desc->lba);
/* Setup the Protective MBR */
- if (set_protective_mbr(dev_desc) < 0)
+ if (set_protective_mbr(desc) < 0)
goto err;
/* Generate CRC for the Primary GPT Header */
@@ -382,20 +386,20 @@
gpt_h->header_crc32 = cpu_to_le32(calc_crc32);
/* Write the First GPT to the block right after the Legacy MBR */
- if (blk_dwrite(dev_desc, 1, 1, gpt_h) != 1)
+ if (blk_dwrite(desc, 1, 1, gpt_h) != 1)
goto err;
- if (blk_dwrite(dev_desc, le64_to_cpu(gpt_h->partition_entry_lba),
+ if (blk_dwrite(desc, le64_to_cpu(gpt_h->partition_entry_lba),
pte_blk_cnt, gpt_e) != pte_blk_cnt)
goto err;
prepare_backup_gpt_header(gpt_h);
- if (blk_dwrite(dev_desc, (lbaint_t)le64_to_cpu(gpt_h->last_usable_lba)
+ if (blk_dwrite(desc, (lbaint_t)le64_to_cpu(gpt_h->last_usable_lba)
+ 1, pte_blk_cnt, gpt_e) != pte_blk_cnt)
goto err;
- if (blk_dwrite(dev_desc, (lbaint_t)le64_to_cpu(gpt_h->my_lba), 1,
+ if (blk_dwrite(desc, (lbaint_t)le64_to_cpu(gpt_h->my_lba), 1,
gpt_h) != 1)
goto err;
@@ -403,11 +407,11 @@
return 0;
err:
- log_debug("** Can't write to device %d **\n", dev_desc->devnum);
+ log_debug("** Can't write to device %d **\n", desc->devnum);
return -EIO;
}
-int gpt_fill_pte(struct blk_desc *dev_desc,
+int gpt_fill_pte(struct blk_desc *desc,
gpt_header *gpt_h, gpt_entry *gpt_e,
struct disk_partition *partitions, int parts)
{
@@ -416,10 +420,7 @@
le64_to_cpu(gpt_h->last_usable_lba);
int i, k;
size_t efiname_len, dosname_len;
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- char *str_uuid;
unsigned char *bin_uuid;
-#endif
#ifdef CONFIG_PARTITION_TYPE_GUID
char *str_type_guid;
unsigned char *bin_type_guid;
@@ -430,7 +431,7 @@
size_t pte_start = gpt_h->partition_entry_lba;
size_t pte_end = pte_start +
gpt_h->num_partition_entries * gpt_h->sizeof_partition_entry /
- dev_desc->blksz;
+ desc->blksz;
for (i = 0; i < parts; i++) {
/* partition starting lba */
@@ -488,16 +489,19 @@
&partition_basic_data_guid, 16);
#endif
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- str_uuid = partitions[i].uuid;
- bin_uuid = gpt_e[i].unique_partition_guid.b;
+ if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) {
+ const char *str_uuid;
- if (uuid_str_to_bin(str_uuid, bin_uuid, UUID_STR_FORMAT_GUID)) {
- log_debug("Partition no. %d: invalid guid: %s\n",
- i, str_uuid);
- return -EINVAL;
+ str_uuid = disk_partition_uuid(&partitions[i]);
+ bin_uuid = gpt_e[i].unique_partition_guid.b;
+
+ if (uuid_str_to_bin(str_uuid, bin_uuid,
+ UUID_STR_FORMAT_GUID)) {
+ log_debug("Partition no. %d: invalid guid: %s\n",
+ i, str_uuid);
+ return -EINVAL;
+ }
}
-#endif
/* partition attributes */
memset(&gpt_e[i].attributes, 0,
@@ -527,7 +531,7 @@
return 0;
}
-static uint32_t partition_entries_offset(struct blk_desc *dev_desc)
+static uint32_t partition_entries_offset(struct blk_desc *desc)
{
uint32_t offset_blks = 2;
uint32_t __maybe_unused offset_bytes;
@@ -543,8 +547,8 @@
* CONFIG_EFI_PARTITION_ENTRIES_OFF.
*/
offset_bytes =
- PAD_TO_BLOCKSIZE(CONFIG_EFI_PARTITION_ENTRIES_OFF, dev_desc);
- offset_blks = offset_bytes / dev_desc->blksz;
+ PAD_TO_BLOCKSIZE(CONFIG_EFI_PARTITION_ENTRIES_OFF, desc);
+ offset_blks = offset_bytes / desc->blksz;
#endif
#if defined(CONFIG_OF_CONTROL)
@@ -556,8 +560,8 @@
config_offset = ofnode_conf_read_int(
"u-boot,efi-partition-entries-offset", -EINVAL);
if (config_offset != -EINVAL) {
- offset_bytes = PAD_TO_BLOCKSIZE(config_offset, dev_desc);
- offset_blks = offset_bytes / dev_desc->blksz;
+ offset_bytes = PAD_TO_BLOCKSIZE(config_offset, desc);
+ offset_blks = offset_bytes / desc->blksz;
}
#endif
@@ -573,17 +577,17 @@
return offset_blks;
}
-int gpt_fill_header(struct blk_desc *dev_desc, gpt_header *gpt_h,
- char *str_guid, int parts_count)
+int gpt_fill_header(struct blk_desc *desc, gpt_header *gpt_h, char *str_guid,
+ int parts_count)
{
gpt_h->signature = cpu_to_le64(GPT_HEADER_SIGNATURE_UBOOT);
gpt_h->revision = cpu_to_le32(GPT_HEADER_REVISION_V1);
gpt_h->header_size = cpu_to_le32(sizeof(gpt_header));
gpt_h->my_lba = cpu_to_le64(1);
- gpt_h->alternate_lba = cpu_to_le64(dev_desc->lba - 1);
- gpt_h->last_usable_lba = cpu_to_le64(dev_desc->lba - 34);
+ gpt_h->alternate_lba = cpu_to_le64(desc->lba - 1);
+ gpt_h->last_usable_lba = cpu_to_le64(desc->lba - 34);
gpt_h->partition_entry_lba =
- cpu_to_le64(partition_entries_offset(dev_desc));
+ cpu_to_le64(partition_entries_offset(desc));
gpt_h->first_usable_lba =
cpu_to_le64(le64_to_cpu(gpt_h->partition_entry_lba) + 32);
gpt_h->num_partition_entries = cpu_to_le32(GPT_ENTRY_NUMBERS);
@@ -597,14 +601,14 @@
return 0;
}
-int gpt_restore(struct blk_desc *dev_desc, char *str_disk_guid,
+int gpt_restore(struct blk_desc *desc, char *str_disk_guid,
struct disk_partition *partitions, int parts_count)
{
gpt_header *gpt_h;
gpt_entry *gpt_e;
int ret, size;
- size = PAD_TO_BLOCKSIZE(sizeof(gpt_header), dev_desc);
+ size = PAD_TO_BLOCKSIZE(sizeof(gpt_header), desc);
gpt_h = malloc_cache_aligned(size);
if (gpt_h == NULL) {
log_debug("calloc failed!\n");
@@ -613,7 +617,7 @@
memset(gpt_h, 0, size);
size = PAD_TO_BLOCKSIZE(GPT_ENTRY_NUMBERS * sizeof(gpt_entry),
- dev_desc);
+ desc);
gpt_e = malloc_cache_aligned(size);
if (gpt_e == NULL) {
log_debug("calloc failed!\n");
@@ -623,17 +627,17 @@
memset(gpt_e, 0, size);
/* Generate Primary GPT header (LBA1) */
- ret = gpt_fill_header(dev_desc, gpt_h, str_disk_guid, parts_count);
+ ret = gpt_fill_header(desc, gpt_h, str_disk_guid, parts_count);
if (ret)
goto err;
/* Generate partition entries */
- ret = gpt_fill_pte(dev_desc, gpt_h, gpt_e, partitions, parts_count);
+ ret = gpt_fill_pte(desc, gpt_h, gpt_e, partitions, parts_count);
if (ret)
goto err;
/* Write GPT partition table */
- ret = write_gpt_table(dev_desc, gpt_h, gpt_e);
+ ret = write_gpt_table(desc, gpt_h, gpt_e);
err:
free(gpt_e);
@@ -664,14 +668,14 @@
}
}
-int gpt_verify_headers(struct blk_desc *dev_desc, gpt_header *gpt_head,
+int gpt_verify_headers(struct blk_desc *desc, gpt_header *gpt_head,
gpt_entry **gpt_pte)
{
/*
* This function validates AND
* fills in the GPT header and PTE
*/
- if (is_gpt_valid(dev_desc,
+ if (is_gpt_valid(desc,
GPT_PRIMARY_PARTITION_TABLE_LBA,
gpt_head, gpt_pte) != 1) {
log_debug("Invalid GPT\n");
@@ -684,12 +688,12 @@
/*
* Check that the alternate_lba entry points to the last LBA
*/
- if (le64_to_cpu(gpt_head->alternate_lba) != (dev_desc->lba - 1)) {
+ if (le64_to_cpu(gpt_head->alternate_lba) != (desc->lba - 1)) {
log_debug("Misplaced Backup GPT\n");
return -1;
}
- if (is_gpt_valid(dev_desc, (dev_desc->lba - 1),
+ if (is_gpt_valid(desc, (desc->lba - 1),
gpt_head, gpt_pte) != 1) {
log_debug("Invalid Backup GPT\n");
return -1;
@@ -698,7 +702,7 @@
return 0;
}
-static void restore_primary_gpt_header(gpt_header *gpt_h, struct blk_desc *dev_desc)
+static void restore_primary_gpt_header(gpt_header *gpt_h, struct blk_desc *desc)
{
u32 calc_crc32;
u64 val;
@@ -707,7 +711,7 @@
val = le64_to_cpu(gpt_h->my_lba);
gpt_h->my_lba = gpt_h->alternate_lba;
gpt_h->alternate_lba = cpu_to_le64(val);
- gpt_h->partition_entry_lba = cpu_to_le64(partition_entries_offset(dev_desc));
+ gpt_h->partition_entry_lba = cpu_to_le64(partition_entries_offset(desc));
gpt_h->header_crc32 = 0;
@@ -716,22 +720,22 @@
gpt_h->header_crc32 = cpu_to_le32(calc_crc32);
}
-static int write_one_gpt_table(struct blk_desc *dev_desc,
- gpt_header *gpt_h, gpt_entry *gpt_e)
+static int write_one_gpt_table(struct blk_desc *desc, gpt_header *gpt_h,
+ gpt_entry *gpt_e)
{
const int pte_blk_cnt = BLOCK_CNT((gpt_h->num_partition_entries
- * sizeof(gpt_entry)), dev_desc);
+ * sizeof(gpt_entry)), desc);
lbaint_t start;
int ret = 0;
start = le64_to_cpu(gpt_h->my_lba);
- if (blk_dwrite(dev_desc, start, 1, gpt_h) != 1) {
+ if (blk_dwrite(desc, start, 1, gpt_h) != 1) {
ret = -1;
goto out;
}
start = le64_to_cpu(gpt_h->partition_entry_lba);
- if (blk_dwrite(dev_desc, start, pte_blk_cnt, gpt_e) != pte_blk_cnt) {
+ if (blk_dwrite(desc, start, pte_blk_cnt, gpt_e) != pte_blk_cnt) {
ret = -1;
goto out;
}
@@ -740,17 +744,17 @@
return ret;
}
-int gpt_repair_headers(struct blk_desc *dev_desc)
+int gpt_repair_headers(struct blk_desc *desc)
{
- ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_h1, 1, dev_desc->blksz);
- ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_h2, 1, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_h1, 1, desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_h2, 1, desc->blksz);
gpt_entry *gpt_e1 = NULL, *gpt_e2 = NULL;
int is_gpt1_valid, is_gpt2_valid;
int ret = -1;
- is_gpt1_valid = is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
+ is_gpt1_valid = is_gpt_valid(desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
gpt_h1, &gpt_e1);
- is_gpt2_valid = is_gpt_valid(dev_desc, dev_desc->lba - 1,
+ is_gpt2_valid = is_gpt_valid(desc, desc->lba - 1,
gpt_h2, &gpt_e2);
if (is_gpt1_valid && is_gpt2_valid) {
@@ -760,13 +764,13 @@
if (is_gpt1_valid && !is_gpt2_valid) {
prepare_backup_gpt_header(gpt_h1);
- ret = write_one_gpt_table(dev_desc, gpt_h1, gpt_e1);
+ ret = write_one_gpt_table(desc, gpt_h1, gpt_e1);
goto out;
}
if (!is_gpt1_valid && is_gpt2_valid) {
- restore_primary_gpt_header(gpt_h2, dev_desc);
- ret = write_one_gpt_table(dev_desc, gpt_h2, gpt_e2);
+ restore_primary_gpt_header(gpt_h2, desc);
+ ret = write_one_gpt_table(desc, gpt_h2, gpt_e2);
goto out;
}
@@ -784,7 +788,7 @@
return ret;
}
-int gpt_verify_partitions(struct blk_desc *dev_desc,
+int gpt_verify_partitions(struct blk_desc *desc,
struct disk_partition *partitions, int parts,
gpt_header *gpt_head, gpt_entry **gpt_pte)
{
@@ -793,7 +797,7 @@
gpt_entry *gpt_e;
int ret, i;
- ret = gpt_verify_headers(dev_desc, gpt_head, gpt_pte);
+ ret = gpt_verify_headers(desc, gpt_head, gpt_pte);
if (ret)
return ret;
@@ -862,28 +866,27 @@
return 0;
}
-int is_valid_gpt_buf(struct blk_desc *dev_desc, void *buf)
+int is_valid_gpt_buf(struct blk_desc *desc, void *buf)
{
gpt_header *gpt_h;
gpt_entry *gpt_e;
/* determine start of GPT Header in the buffer */
- gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA *
- dev_desc->blksz);
+ gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA * desc->blksz);
if (validate_gpt_header(gpt_h, GPT_PRIMARY_PARTITION_TABLE_LBA,
- dev_desc->lba))
+ desc->lba))
return -1;
/* determine start of GPT Entries in the buffer */
gpt_e = buf + (le64_to_cpu(gpt_h->partition_entry_lba) *
- dev_desc->blksz);
+ desc->blksz);
if (validate_gpt_entries(gpt_h, gpt_e))
return -1;
return 0;
}
-int write_mbr_and_gpt_partitions(struct blk_desc *dev_desc, void *buf)
+int write_mbr_and_gpt_partitions(struct blk_desc *desc, void *buf)
{
gpt_header *gpt_h;
gpt_entry *gpt_e;
@@ -891,24 +894,22 @@
lbaint_t lba;
int cnt;
- if (is_valid_gpt_buf(dev_desc, buf))
+ if (is_valid_gpt_buf(desc, buf))
return -1;
/* determine start of GPT Header in the buffer */
- gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA *
- dev_desc->blksz);
+ gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA * desc->blksz);
/* determine start of GPT Entries in the buffer */
- gpt_e = buf + (le64_to_cpu(gpt_h->partition_entry_lba) *
- dev_desc->blksz);
+ gpt_e = buf + (le64_to_cpu(gpt_h->partition_entry_lba) * desc->blksz);
gpt_e_blk_cnt = BLOCK_CNT((le32_to_cpu(gpt_h->num_partition_entries) *
le32_to_cpu(gpt_h->sizeof_partition_entry)),
- dev_desc);
+ desc);
/* write MBR */
lba = 0; /* MBR is always at 0 */
cnt = 1; /* MBR (1 block) */
- if (blk_dwrite(dev_desc, lba, cnt, buf) != cnt) {
+ if (blk_dwrite(desc, lba, cnt, buf) != cnt) {
log_debug("failed writing '%s' (%d blks at 0x" LBAF ")\n",
"MBR", cnt, lba);
return 1;
@@ -917,7 +918,7 @@
/* write Primary GPT */
lba = GPT_PRIMARY_PARTITION_TABLE_LBA;
cnt = 1; /* GPT Header (1 block) */
- if (blk_dwrite(dev_desc, lba, cnt, gpt_h) != cnt) {
+ if (blk_dwrite(desc, lba, cnt, gpt_h) != cnt) {
log_debug("failed writing '%s' (%d blks at 0x" LBAF ")\n",
"Primary GPT Header", cnt, lba);
return 1;
@@ -925,7 +926,7 @@
lba = le64_to_cpu(gpt_h->partition_entry_lba);
cnt = gpt_e_blk_cnt;
- if (blk_dwrite(dev_desc, lba, cnt, gpt_e) != cnt) {
+ if (blk_dwrite(desc, lba, cnt, gpt_e) != cnt) {
log_debug("failed writing '%s' (%d blks at 0x" LBAF ")\n",
"Primary GPT Entries", cnt, lba);
return 1;
@@ -936,7 +937,7 @@
/* write Backup GPT */
lba = le64_to_cpu(gpt_h->partition_entry_lba);
cnt = gpt_e_blk_cnt;
- if (blk_dwrite(dev_desc, lba, cnt, gpt_e) != cnt) {
+ if (blk_dwrite(desc, lba, cnt, gpt_e) != cnt) {
log_debug("failed writing '%s' (%d blks at 0x" LBAF ")\n",
"Backup GPT Entries", cnt, lba);
return 1;
@@ -944,14 +945,14 @@
lba = le64_to_cpu(gpt_h->my_lba);
cnt = 1; /* GPT Header (1 block) */
- if (blk_dwrite(dev_desc, lba, cnt, gpt_h) != cnt) {
+ if (blk_dwrite(desc, lba, cnt, gpt_h) != cnt) {
log_debug("failed writing '%s' (%d blks at 0x" LBAF ")\n",
"Backup GPT Header", cnt, lba);
return 1;
}
/* Update the partition table entries*/
- part_init(dev_desc);
+ part_init(desc);
return 0;
}
@@ -978,17 +979,23 @@
/*
* is_pmbr_valid(): test Protective MBR for validity
*
+ * @mbr: Pointer to Master Boot-Record data
+ *
* Returns: 1 if PMBR is valid, 0 otherwise.
* Validity depends on two things:
* 1) MSDOS signature is in the last two bytes of the MBR
* 2) One partition of type 0xEE is found, checked by pmbr_part_valid()
*/
-static int is_pmbr_valid(legacy_mbr * mbr)
+static int is_pmbr_valid(legacy_mbr *mbr)
{
+ uint sig = le16_to_cpu(mbr->signature);
int i = 0;
- if (!mbr || le16_to_cpu(mbr->signature) != MSDOS_MBR_SIGNATURE)
+ if (sig != MSDOS_MBR_SIGNATURE) {
+ log_debug("Invalid signature %x\n", sig);
return 0;
+ }
+ log_debug("Signature %x valid\n", sig);
for (i = 0; i < 4; i++) {
if (pmbr_part_valid(&mbr->partition_record[i])) {
@@ -1008,25 +1015,25 @@
* Description: returns 1 if valid, 0 on error, 2 if ignored header
* If valid, returns pointers to PTEs.
*/
-static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba,
- gpt_header *pgpt_head, gpt_entry **pgpt_pte)
+static int is_gpt_valid(struct blk_desc *desc, u64 lba, gpt_header *pgpt_head,
+ gpt_entry **pgpt_pte)
{
/* Confirm valid arguments prior to allocation. */
- if (!dev_desc || !pgpt_head) {
+ if (!desc || !pgpt_head) {
log_debug("Invalid Argument(s)\n");
return 0;
}
- ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, mbr, 1, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, mbr, 1, desc->blksz);
/* Read MBR Header from device */
- if (blk_dread(dev_desc, 0, 1, (ulong *)mbr) != 1) {
+ if (blk_dread(desc, 0, 1, (ulong *)mbr) != 1) {
log_debug("Can't read MBR header\n");
return 0;
}
/* Read GPT Header from device */
- if (blk_dread(dev_desc, (lbaint_t)lba, 1, pgpt_head) != 1) {
+ if (blk_dread(desc, (lbaint_t)lba, 1, pgpt_head) != 1) {
log_debug("Can't read GPT header\n");
return 0;
}
@@ -1037,23 +1044,23 @@
return 2;
}
- if (validate_gpt_header(pgpt_head, (lbaint_t)lba, dev_desc->lba))
+ if (validate_gpt_header(pgpt_head, (lbaint_t)lba, desc->lba))
return 0;
- if (dev_desc->sig_type == SIG_TYPE_NONE) {
+ if (desc->sig_type == SIG_TYPE_NONE) {
efi_guid_t empty = {};
if (memcmp(&pgpt_head->disk_guid, &empty, sizeof(empty))) {
- dev_desc->sig_type = SIG_TYPE_GUID;
- memcpy(&dev_desc->guid_sig, &pgpt_head->disk_guid,
- sizeof(empty));
+ desc->sig_type = SIG_TYPE_GUID;
+ memcpy(&desc->guid_sig, &pgpt_head->disk_guid,
+ sizeof(empty));
} else if (mbr->unique_mbr_signature != 0) {
- dev_desc->sig_type = SIG_TYPE_MBR;
- dev_desc->mbr_sig = mbr->unique_mbr_signature;
+ desc->sig_type = SIG_TYPE_MBR;
+ desc->mbr_sig = mbr->unique_mbr_signature;
}
}
/* Read and allocate Partition Table Entries */
- *pgpt_pte = alloc_read_gpt_entries(dev_desc, pgpt_head);
+ *pgpt_pte = alloc_read_gpt_entries(desc, pgpt_head);
if (!*pgpt_pte)
return 0;
@@ -1075,20 +1082,20 @@
* Description: returns 1 if found a valid gpt, 0 on error.
* If valid, returns pointers to PTEs.
*/
-static int find_valid_gpt(struct blk_desc *dev_desc, gpt_header *gpt_head,
+static int find_valid_gpt(struct blk_desc *desc, gpt_header *gpt_head,
gpt_entry **pgpt_pte)
{
int r;
- r = is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, gpt_head,
+ r = is_gpt_valid(desc, GPT_PRIMARY_PARTITION_TABLE_LBA, gpt_head,
pgpt_pte);
if (r != 1) {
if (r != 2)
log_debug("Invalid GPT\n");
- if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), gpt_head,
- pgpt_pte) != 1) {
+ if (is_gpt_valid(desc, desc->lba - 1, gpt_head, pgpt_pte)
+ != 1) {
log_debug("Invalid Backup GPT\n");
return 0;
}
@@ -1100,21 +1107,21 @@
/**
* alloc_read_gpt_entries(): reads partition entries from disk
- * @dev_desc
+ * @desc
* @gpt - GPT header
*
* Description: Returns ptes on success, NULL on error.
* Allocates space for PTEs based on information found in @gpt.
* Notes: remember to free pte when you're done!
*/
-static gpt_entry *alloc_read_gpt_entries(struct blk_desc *dev_desc,
+static gpt_entry *alloc_read_gpt_entries(struct blk_desc *desc,
gpt_header *pgpt_head)
{
size_t count = 0, blk_cnt;
lbaint_t blk;
gpt_entry *pte = NULL;
- if (!dev_desc || !pgpt_head) {
+ if (!desc || !pgpt_head) {
log_debug("Invalid Argument(s)\n");
return NULL;
}
@@ -1130,7 +1137,7 @@
/* Allocate memory for PTE, remember to FREE */
if (count != 0) {
pte = memalign(ARCH_DMA_MINALIGN,
- PAD_TO_BLOCKSIZE(count, dev_desc));
+ PAD_TO_BLOCKSIZE(count, desc));
}
if (count == 0 || pte == NULL) {
@@ -1141,8 +1148,8 @@
/* Read GPT Entries from device */
blk = le64_to_cpu(pgpt_head->partition_entry_lba);
- blk_cnt = BLOCK_CNT(count, dev_desc);
- if (blk_dread(dev_desc, blk, (lbaint_t)blk_cnt, pte) != blk_cnt) {
+ blk_cnt = BLOCK_CNT(count, desc);
+ if (blk_dread(desc, blk, (lbaint_t)blk_cnt, pte) != blk_cnt) {
log_debug("Can't read GPT Entries\n");
free(pte);
return NULL;
diff --git a/disk/part_iso.c b/disk/part_iso.c
index 4cd619b..6ac6d95 100644
--- a/disk/part_iso.c
+++ b/disk/part_iso.c
@@ -46,7 +46,7 @@
}
/* only boot records will be listed as valid partitions */
-int part_get_info_iso_verb(struct blk_desc *dev_desc, int part_num,
+int part_get_info_iso_verb(struct blk_desc *desc, int part_num,
struct disk_partition *info, int verb)
{
int i,offset,entry_num;
@@ -58,23 +58,23 @@
iso_val_entry_t *pve = (iso_val_entry_t *)tmpbuf;
iso_init_def_entry_t *pide;
- if ((dev_desc->blksz != CD_SECTSIZE) && (dev_desc->blksz != 512))
+ if (desc->blksz != CD_SECTSIZE && desc->blksz != 512)
return -1;
/* the first sector (sector 0x10) must be a primary volume desc */
blkaddr=PVD_OFFSET;
- if (iso_dread(dev_desc, PVD_OFFSET, 1, (ulong *)tmpbuf) != 1)
+ if (iso_dread(desc, PVD_OFFSET, 1, (ulong *)tmpbuf) != 1)
return -1;
if(ppr->desctype!=0x01) {
if(verb)
printf ("** First descriptor is NOT a primary desc on %d:%d **\n",
- dev_desc->devnum, part_num);
+ desc->devnum, part_num);
return (-1);
}
if(strncmp((char *)ppr->stand_ident,"CD001",5)!=0) {
if(verb)
printf ("** Wrong ISO Ident: %s on %d:%d **\n",
- ppr->stand_ident, dev_desc->devnum, part_num);
+ ppr->stand_ident, desc->devnum, part_num);
return (-1);
}
lastsect = le32_to_cpu(ppr->firstsek_LEpathtab1_LE);
@@ -83,14 +83,14 @@
PRINTF(" Lastsect:%08lx\n",lastsect);
for(i=blkaddr;i<lastsect;i++) {
PRINTF("Reading block %d\n", i);
- if (iso_dread(dev_desc, i, 1, (ulong *)tmpbuf) != 1)
+ if (iso_dread(desc, i, 1, (ulong *)tmpbuf) != 1)
return -1;
if(ppr->desctype==0x00)
break; /* boot entry found */
if(ppr->desctype==0xff) {
if(verb)
printf ("** No valid boot catalog found on %d:%d **\n",
- dev_desc->devnum, part_num);
+ desc->devnum, part_num);
return (-1);
}
}
@@ -98,15 +98,15 @@
if(strncmp(pbr->ident_str,"EL TORITO SPECIFICATION",23)!=0) {
if(verb)
printf ("** Wrong El Torito ident: %s on %d:%d **\n",
- pbr->ident_str, dev_desc->devnum, part_num);
+ pbr->ident_str, desc->devnum, part_num);
return (-1);
}
bootaddr = get_unaligned_le32(pbr->pointer);
PRINTF(" Boot Entry at: %08lX\n",bootaddr);
- if (iso_dread(dev_desc, bootaddr, 1, (ulong *)tmpbuf) != 1) {
+ if (iso_dread(desc, bootaddr, 1, (ulong *)tmpbuf) != 1) {
if(verb)
printf ("** Can't read Boot Entry at %lX on %d:%d **\n",
- bootaddr, dev_desc->devnum, part_num);
+ bootaddr, desc->devnum, part_num);
return (-1);
}
chksum=0;
@@ -116,20 +116,20 @@
if(chksum!=0) {
if(verb)
printf("** Checksum Error in booting catalog validation entry on %d:%d **\n",
- dev_desc->devnum, part_num);
+ desc->devnum, part_num);
return (-1);
}
if((pve->key[0]!=0x55)||(pve->key[1]!=0xAA)) {
if(verb)
printf ("** Key 0x55 0xAA error on %d:%d **\n",
- dev_desc->devnum, part_num);
+ desc->devnum, part_num);
return(-1);
}
#ifdef CHECK_FOR_POWERPC_PLATTFORM
if(pve->platform!=0x01) {
if(verb)
printf ("** No PowerPC platform CD on %d:%d **\n",
- dev_desc->devnum, part_num);
+ desc->devnum, part_num);
return(-1);
}
#endif
@@ -137,7 +137,7 @@
entry_num=1;
offset=0x20;
strcpy((char *)info->type, "U-Boot");
- part_set_generic_name(dev_desc, part_num, (char *)info->name);
+ part_set_generic_name(desc, part_num, (char *)info->name);
/* the bootcatalog (including validation Entry) is limited to 2048Bytes
* (63 boot entries + validation entry) */
while(offset<2048) {
@@ -159,7 +159,7 @@
else {
if(verb)
printf ("** Partition %d not found on device %d **\n",
- part_num, dev_desc->devnum);
+ part_num, desc->devnum);
return(-1);
}
}
@@ -167,13 +167,13 @@
* searched w/o succsess */
if(verb)
printf ("** Partition %d not found on device %d **\n",
- part_num, dev_desc->devnum);
+ part_num, desc->devnum);
return(-1);
found:
if(pide->boot_ind!=0x88) {
if(verb)
printf("** Partition %d is not bootable on device %d **\n",
- part_num, dev_desc->devnum);
+ part_num, desc->devnum);
return (-1);
}
switch(pide->boot_media) {
@@ -189,7 +189,7 @@
newblkaddr = get_unaligned_le32(pide->rel_block_addr);
info->start=newblkaddr;
- if (dev_desc->blksz == 512) {
+ if (desc->blksz == 512) {
info->size *= 4;
info->start *= 4;
info->blksz = 512;
@@ -199,20 +199,20 @@
return 0;
}
-static int part_get_info_iso(struct blk_desc *dev_desc, int part_num,
+static int part_get_info_iso(struct blk_desc *desc, int part_num,
struct disk_partition *info)
{
- return part_get_info_iso_verb(dev_desc, part_num, info, 0);
+ return part_get_info_iso_verb(desc, part_num, info, 0);
}
-static void part_print_iso(struct blk_desc *dev_desc)
+static void part_print_iso(struct blk_desc *desc)
{
struct disk_partition info;
int i;
- if (part_get_info_iso_verb(dev_desc, 1, &info, 0) == -1) {
+ if (part_get_info_iso_verb(desc, 1, &info, 0) == -1) {
printf("** No boot partition found on device %d **\n",
- dev_desc->devnum);
+ desc->devnum);
return;
}
printf("Part Start Sect x Size Type\n");
@@ -221,14 +221,14 @@
printf(" %2d %8" LBAFlength "u %8" LBAFlength "u %6ld %.32s\n",
i, info.start, info.size, info.blksz, info.type);
i++;
- } while (part_get_info_iso_verb(dev_desc, i, &info, 0) != -1);
+ } while (part_get_info_iso_verb(desc, i, &info, 0) != -1);
}
-static int part_test_iso(struct blk_desc *dev_desc)
+static int part_test_iso(struct blk_desc *desc)
{
struct disk_partition info;
- return part_get_info_iso_verb(dev_desc, 1, &info, 0);
+ return part_get_info_iso_verb(desc, 1, &info, 0);
}
U_BOOT_PART_TYPE(iso) = {
diff --git a/disk/part_mac.c b/disk/part_mac.c
index ae8263f..db5e203 100644
--- a/disk/part_mac.c
+++ b/disk/part_mac.c
@@ -31,21 +31,20 @@
#endif
-static int part_mac_read_ddb(struct blk_desc *dev_desc,
- mac_driver_desc_t *ddb_p);
-static int part_mac_read_pdb(struct blk_desc *dev_desc, int part,
+static int part_mac_read_ddb(struct blk_desc *desc, mac_driver_desc_t *ddb_p);
+static int part_mac_read_pdb(struct blk_desc *desc, int part,
mac_partition_t *pdb_p);
/*
* Test for a valid MAC partition
*/
-static int part_test_mac(struct blk_desc *dev_desc)
+static int part_test_mac(struct blk_desc *desc)
{
ALLOC_CACHE_ALIGN_BUFFER(mac_driver_desc_t, ddesc, 1);
ALLOC_CACHE_ALIGN_BUFFER(mac_partition_t, mpart, 1);
ulong i, n;
- if (part_mac_read_ddb (dev_desc, ddesc)) {
+ if (part_mac_read_ddb(desc, ddesc)) {
/*
* error reading Driver Descriptor Block,
* or no valid Signature
@@ -55,8 +54,8 @@
n = 1; /* assuming at least one partition */
for (i=1; i<=n; ++i) {
- if ((blk_dread(dev_desc, i, 1, (ulong *)mpart) != 1) ||
- (mpart->signature != MAC_PARTITION_MAGIC) ) {
+ if ((blk_dread(desc, i, 1, (ulong *)mpart) != 1) ||
+ mpart->signature != MAC_PARTITION_MAGIC) {
return (-1);
}
/* update partition count */
@@ -65,14 +64,14 @@
return (0);
}
-static void part_print_mac(struct blk_desc *dev_desc)
+static void part_print_mac(struct blk_desc *desc)
{
ulong i, n;
ALLOC_CACHE_ALIGN_BUFFER(mac_driver_desc_t, ddesc, 1);
ALLOC_CACHE_ALIGN_BUFFER(mac_partition_t, mpart, 1);
ldiv_t mb, gb;
- if (part_mac_read_ddb (dev_desc, ddesc)) {
+ if (part_mac_read_ddb(desc, ddesc)) {
/*
* error reading Driver Descriptor Block,
* or no valid Signature
@@ -110,15 +109,15 @@
char c;
printf ("%4ld: ", i);
- if (blk_dread(dev_desc, i, 1, (ulong *)mpart) != 1) {
+ if (blk_dread(desc, i, 1, (ulong *)mpart) != 1) {
printf ("** Can't read Partition Map on %d:%ld **\n",
- dev_desc->devnum, i);
+ desc->devnum, i);
return;
}
if (mpart->signature != MAC_PARTITION_MAGIC) {
printf("** Bad Signature on %d:%ld - expected 0x%04x, got 0x%04x\n",
- dev_desc->devnum, i, MAC_PARTITION_MAGIC,
+ desc->devnum, i, MAC_PARTITION_MAGIC,
mpart->signature);
return;
}
@@ -154,10 +153,9 @@
/*
* Read Device Descriptor Block
*/
-static int part_mac_read_ddb(struct blk_desc *dev_desc,
- mac_driver_desc_t *ddb_p)
+static int part_mac_read_ddb(struct blk_desc *desc, mac_driver_desc_t *ddb_p)
{
- if (blk_dread(dev_desc, 0, 1, (ulong *)ddb_p) != 1) {
+ if (blk_dread(desc, 0, 1, (ulong *)ddb_p) != 1) {
debug("** Can't read Driver Descriptor Block **\n");
return (-1);
}
@@ -171,7 +169,7 @@
/*
* Read Partition Descriptor Block
*/
-static int part_mac_read_pdb(struct blk_desc *dev_desc, int part,
+static int part_mac_read_pdb(struct blk_desc *desc, int part,
mac_partition_t *pdb_p)
{
int n = 1;
@@ -182,15 +180,15 @@
* partition 1 first since this is the only way to
* know how many partitions we have.
*/
- if (blk_dread(dev_desc, n, 1, (ulong *)pdb_p) != 1) {
- printf ("** Can't read Partition Map on %d:%d **\n",
- dev_desc->devnum, n);
+ if (blk_dread(desc, n, 1, (ulong *)pdb_p) != 1) {
+ printf("** Can't read Partition Map on %d:%d **\n",
+ desc->devnum, n);
return (-1);
}
if (pdb_p->signature != MAC_PARTITION_MAGIC) {
printf("** Bad Signature on %d:%d: expected 0x%04x, got 0x%04x\n",
- dev_desc->devnum, n, MAC_PARTITION_MAGIC,
+ desc->devnum, n, MAC_PARTITION_MAGIC,
pdb_p->signature);
return (-1);
}
@@ -199,10 +197,9 @@
return (0);
if ((part < 1) || (part > pdb_p->map_count)) {
- printf ("** Invalid partition %d:%d [%d:1...%d:%d only]\n",
- dev_desc->devnum, part,
- dev_desc->devnum,
- dev_desc->devnum, pdb_p->map_count);
+ printf("** Invalid partition %d:%d [%d:1...%d:%d only]\n",
+ desc->devnum, part, desc->devnum, desc->devnum,
+ pdb_p->map_count);
return (-1);
}
@@ -213,21 +210,19 @@
/* NOTREACHED */
}
-static int part_get_info_mac(struct blk_desc *dev_desc, int part,
- struct disk_partition *info)
+static int part_get_info_mac(struct blk_desc *desc, int part,
+ struct disk_partition *info)
{
ALLOC_CACHE_ALIGN_BUFFER(mac_driver_desc_t, ddesc, 1);
ALLOC_CACHE_ALIGN_BUFFER(mac_partition_t, mpart, 1);
- if (part_mac_read_ddb (dev_desc, ddesc)) {
- return (-1);
- }
+ if (part_mac_read_ddb(desc, ddesc))
+ return -1;
info->blksz = ddesc->blk_size;
- if (part_mac_read_pdb (dev_desc, part, mpart)) {
- return (-1);
- }
+ if (part_mac_read_pdb(desc, part, mpart))
+ return -1;
info->start = mpart->start_block;
info->size = mpart->block_count;
diff --git a/doc/README.falcon b/doc/README.falcon
deleted file mode 100644
index 88218d3..0000000
--- a/doc/README.falcon
+++ /dev/null
@@ -1,232 +0,0 @@
-U-Boot Falcon Mode
-====================
-
-Introduction
-------------
-
-This document provides an overview of how to add support for Falcon Mode
-to a board.
-
-Falcon Mode is introduced to speed up the booting process, allowing
-to boot a Linux kernel (or whatever image) without a full blown U-Boot.
-
-Falcon Mode relies on the SPL framework. In fact, to make booting faster,
-U-Boot is split into two parts: the SPL (Secondary Program Loader) and U-Boot
-image. In most implementations, SPL is used to start U-Boot when booting from
-a mass storage, such as NAND or SD-Card. SPL has now support for other media,
-and can generally be seen as a way to start an image performing the minimum
-required initialization. SPL mainly initializes the RAM controller, and then
-copies U-Boot image into the memory.
-
-The Falcon Mode extends this way allowing to start the Linux kernel directly
-from SPL. A new command is added to U-Boot to prepare the parameters that SPL
-must pass to the kernel, using ATAGS or Device Tree.
-
-In normal mode, these parameters are generated each time before
-loading the kernel, passing to Linux the address in memory where
-the parameters can be read.
-With Falcon Mode, this snapshot can be saved into persistent storage and SPL is
-informed to load it before running the kernel.
-
-To boot the kernel, these steps under a Falcon-aware U-Boot are required:
-
-1. Boot the board into U-Boot.
-After loading the desired legacy-format kernel image into memory (and DT as
-well, if used), use the "spl export" command to generate the kernel parameters
-area or the DT. U-Boot runs as when it boots the kernel, but stops before
-passing the control to the kernel.
-
-2. Save the prepared snapshot into persistent media.
-The address where to save it must be configured into board configuration
-file (CONFIG_CMD_SPL_NAND_OFS for NAND).
-
-3. Boot the board into Falcon Mode. SPL will load the kernel and copy
-the parameters which are saved in the persistent area to the required address.
-If a valid uImage is not found at the defined location, U-Boot will be
-booted instead.
-
-It is required to implement a custom mechanism to select if SPL loads U-Boot
-or another image.
-
-The value of a GPIO is a simple way to operate the selection, as well as
-reading a character from the SPL console if CONFIG_SPL_CONSOLE is set.
-
-Falcon Mode is generally activated by setting CONFIG_SPL_OS_BOOT. This tells
-SPL that U-Boot is not the only available image that SPL is able to start.
-
-Configuration
-----------------------------
-CONFIG_CMD_SPL Enable the "spl export" command.
- The command "spl export" is then available in U-Boot
- mode
-CONFIG_SYS_SPL_ARGS_ADDR Address in RAM where the parameters must be
- copied by SPL.
- In most cases, it is <start_of_ram> + 0x100
-
-CONFIG_SYS_NAND_SPL_KERNEL_OFFS Offset in NAND where the kernel is stored
-
-CONFIG_CMD_SPL_NAND_OFS Offset in NAND where the parameters area was saved.
-
-CONFIG_CMD_SPL_NOR_OFS Offset in NOR where the parameters area was saved.
-
-CONFIG_CMD_SPL_WRITE_SIZE Size of the parameters area to be copied
-
-CONFIG_SPL_OS_BOOT Activate Falcon Mode.
-
-Function that a board must implement
-------------------------------------
-
-void spl_board_prepare_for_linux(void) : optional
- Called from SPL before starting the kernel
-
-spl_start_uboot() : required
- Returns "0" if SPL should start the kernel, "1" if U-Boot
- must be started.
-
-Environment variables
----------------------
-
-A board may chose to look at the environment for decisions about falcon
-mode. In this case the following variables may be supported:
-
-boot_os : Set to yes/Yes/true/True/1 to enable booting to OS,
- any other value to fall back to U-Boot (including
- unset)
-falcon_args_file : Filename to load as the 'args' portion of falcon mode
- rather than the hard-coded value.
-falcon_image_file : Filename to load as the OS image portion of falcon
- mode rather than the hard-coded value.
-
-Using spl command
------------------
-
-spl - SPL configuration
-
-Usage:
-
-spl export <img=atags|fdt> [kernel_addr] [initrd_addr] [fdt_addr ]
-
-img : "atags" or "fdt"
-kernel_addr : kernel is loaded as part of the boot process, but it is not started.
- This is the address where a kernel image is stored.
-initrd_addr : Address of initial ramdisk
- can be set to "-" if fdt_addr without initrd_addr is used
-fdt_addr : in case of fdt, the address of the device tree.
-
-The spl export command does not write to a storage media. The user is
-responsible to transfer the gathered information (assembled ATAGS list
-or prepared FDT) from temporary storage in RAM into persistant storage
-after each run of 'spl export'. Unfortunately the position of temporary
-storage can not be predicted nor provided at commandline, it depends
-highly on your system setup and your provided data (ATAGS or FDT).
-However at the end of an succesful 'spl export' run it will print the
-RAM address of temporary storage. The RAM address of FDT will also be
-set in the environment variable 'fdtargsaddr', the new length of the
-prepared FDT will be set in the environment variable 'fdtargslen'.
-These environment variables can be used in scripts for writing updated
-FDT to persistent storage.
-
-Now the user have to save the generated BLOB from that printed address
-to the pre-defined address in persistent storage
-(CONFIG_CMD_SPL_NAND_OFS in case of NAND).
-The following example shows how to prepare the data for Falcon Mode on
-twister board with ATAGS BLOB.
-
-The "spl export" command is prepared to work with ATAGS and FDT. However,
-using FDT is at the moment untested. The ppc port (see a3m071 example
-later) prepares the fdt blob with the fdt command instead.
-
-
-Usage on the twister board:
---------------------------------
-
-Using mtd names with the following (default) configuration
-for mtdparts:
-
-device nand0 <omap2-nand.0>, # parts = 9
- #: name size offset mask_flags
- 0: MLO 0x00080000 0x00000000 0
- 1: u-boot 0x00100000 0x00080000 0
- 2: env1 0x00040000 0x00180000 0
- 3: env2 0x00040000 0x001c0000 0
- 4: kernel 0x00600000 0x00200000 0
- 5: bootparms 0x00040000 0x00800000 0
- 6: splashimg 0x00200000 0x00840000 0
- 7: mini 0x02800000 0x00a40000 0
- 8: rootfs 0x1cdc0000 0x03240000 0
-
-
-twister => nand read 82000000 kernel
-
-NAND read: device 0 offset 0x200000, size 0x600000
- 6291456 bytes read: OK
-
-Now the kernel is in RAM at address 0x82000000
-
-twister => spl export atags 0x82000000
-## Booting kernel from Legacy Image at 82000000 ...
- Image Name: Linux-3.5.0-rc4-14089-gda0b7f4
- Image Type: ARM Linux Kernel Image (uncompressed)
- Data Size: 3654808 Bytes = 3.5 MiB
- Load Address: 80008000
- Entry Point: 80008000
- Verifying Checksum ... OK
- Loading Kernel Image ... OK
-OK
-cmdline subcommand not supported
-bdt subcommand not supported
-Argument image is now in RAM at: 0x80000100
-
-The result can be checked at address 0x80000100:
-
-twister => md 0x80000100
-80000100: 00000005 54410001 00000000 00000000 ......AT........
-80000110: 00000000 00000067 54410009 746f6f72 ....g.....ATroot
-80000120: 65642f3d 666e2f76 77722073 73666e20 =/dev/nfs rw nfs
-
-The parameters generated with this step can be saved into NAND at the offset
-0x800000 (value for twister for CONFIG_CMD_SPL_NAND_OFS)
-
-nand erase.part bootparms
-nand write 0x80000100 bootparms 0x4000
-
-Now the parameters are stored into the NAND flash at the address
-CONFIG_CMD_SPL_NAND_OFS (=0x800000).
-
-Next time, the board can be started into Falcon Mode moving the
-setting the gpio (on twister gpio 55 is used) to kernel mode.
-
-The kernel is loaded directly by the SPL without passing through U-Boot.
-
-Example with FDT: a3m071 board
--------------------------------
-
-To boot the Linux kernel from the SPL, the DT blob (fdt) needs to get
-prepard/patched first. U-Boot usually inserts some dynamic values into
-the DT binary (blob), e.g. autodetected memory size, MAC addresses,
-clocks speeds etc. To generate this patched DT blob, you can use
-the following command:
-
-1. Load fdt blob to SDRAM:
-=> tftp 1800000 a3m071/a3m071.dtb
-
-2. Set bootargs as desired for Linux booting (e.g. flash_mtd):
-=> run mtdargs addip2 addtty
-
-3. Use "fdt" commands to patch the DT blob:
-=> fdt addr 1800000
-=> fdt boardsetup
-=> fdt chosen
-
-4. Display patched DT blob (optional):
-=> fdt print
-
-5. Save fdt to NOR flash:
-=> erase fc060000 fc07ffff
-=> cp.b 1800000 fc060000 10000
-...
-
-
-Falcon Mode was presented at the RMLL 2012. Slides are available at:
-
-http://schedule2012.rmll.info/IMG/pdf/LSM2012_UbootFalconMode_Babic.pdf
diff --git a/doc/api/index.rst b/doc/api/index.rst
index a9338cf..3a80ae0 100644
--- a/doc/api/index.rst
+++ b/doc/api/index.rst
@@ -15,6 +15,7 @@
lmb
logging
nvmem
+ part
pinctrl
rng
sandbox
diff --git a/doc/api/part.rst b/doc/api/part.rst
new file mode 100644
index 0000000..d1df1d8
--- /dev/null
+++ b/doc/api/part.rst
@@ -0,0 +1,6 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Partition API
+=============
+
+.. kernel-doc:: include/part.h
diff --git a/doc/arch/arm64.ffa.rst b/doc/arch/arm64.ffa.rst
new file mode 100644
index 0000000..4ecdc31
--- /dev/null
+++ b/doc/arch/arm64.ffa.rst
@@ -0,0 +1,261 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Arm FF-A Support
+================
+
+Summary
+-------
+
+FF-A stands for Firmware Framework for Arm A-profile processors.
+
+FF-A specifies interfaces that enable a pair of software execution environments aka partitions to
+communicate with each other. A partition could be a VM in the Normal or Secure world, an
+application in S-EL0, or a Trusted OS in S-EL1.
+
+The U-Boot FF-A support (the bus) implements the interfaces to communicate
+with partitions in the Secure world aka Secure partitions (SPs).
+
+The FF-A support specifically focuses on communicating with SPs that
+isolate portions of EFI runtime services that must run in a protected
+environment which is inaccessible by the Host OS or Hypervisor.
+Examples of such services are set/get variables.
+
+The FF-A support uses the SMC ABIs defined by the FF-A specification to:
+
+- Discover the presence of SPs of interest
+- Access an SP's service through communication protocols
+ e.g. EFI MM communication protocol
+
+At this stage of development only EFI boot-time services are supported.
+Runtime support will be added in future developments.
+
+The U-Boot FF-A support provides the following parts:
+
+- A Uclass driver providing generic FF-A methods.
+- An Arm FF-A device driver providing Arm-specific methods and reusing the Uclass methods.
+- A sandbox emulator for Arm FF-A, emulates the FF-A side of the Secure World and provides
+ FF-A ABIs inspection methods.
+- An FF-A sandbox device driver for FF-A communication with the emulated Secure World.
+ The driver leverages the FF-A Uclass to establish FF-A communication.
+- Sandbox FF-A test cases.
+
+FF-A and SMC specifications
+-------------------------------------------
+
+The current implementation of the U-Boot FF-A support relies on
+`FF-A v1.0 specification`_ and uses SMC32 calling convention which
+means using the first 32-bit data of the Xn registers.
+
+At this stage we only need the FF-A v1.0 features.
+
+The FF-A support has been tested with OP-TEE which supports SMC32 calling
+convention.
+
+Hypervisors are supported if they are configured to trap SMC calls.
+
+The FF-A support uses 64-bit registers as per `SMC Calling Convention v1.2 specification`_.
+
+Supported hardware
+--------------------------------
+
+Aarch64 plaforms
+
+Configuration
+----------------------
+
+CONFIG_ARM_FFA_TRANSPORT
+ Enables the FF-A support. Turn this on if you want to use FF-A
+ communication.
+ When using an Arm 64-bit platform, the Arm FF-A driver will be used.
+ When using sandbox, the sandbox FF-A emulator and FF-A sandbox driver will be used.
+
+FF-A ABIs under the hood
+---------------------------------------
+
+Invoking an FF-A ABI involves providing to the secure world/hypervisor the
+expected arguments from the ABI.
+
+On an Arm 64-bit platform, the ABI arguments are stored in x0 to x7 registers.
+Then, an SMC instruction is executed.
+
+At the secure side level or hypervisor the ABI is handled at a higher exception
+level and the arguments are read and processed.
+
+The response is put back through x0 to x7 registers and control is given back
+to the U-Boot Arm FF-A driver (non-secure world).
+
+The driver reads the response and processes it accordingly.
+
+This methodology applies to all the FF-A ABIs.
+
+FF-A bus discovery on Arm 64-bit platforms
+---------------------------------------------
+
+When CONFIG_ARM_FFA_TRANSPORT is enabled, the FF-A bus is considered as
+an architecture feature and discovered using ARM_SMCCC_FEATURES mechanism.
+This discovery mechanism is performed by the PSCI driver.
+
+The PSCI driver comes with a PSCI device tree node which is the root node for all
+architecture features including FF-A bus.
+
+::
+
+ => dm tree
+
+ Class Index Probed Driver Name
+ -----------------------------------------------------------
+ firmware 0 [ + ] psci |-- psci
+ ffa 0 [ ] arm_ffa | `-- arm_ffa
+
+The PSCI driver is bound to the PSCI device and when probed it tries to discover
+the architecture features by calling a callback the features drivers provide.
+
+In case of FF-A, the callback is arm_ffa_is_supported() which tries to discover the
+FF-A framework by querying the FF-A framework version from secure world using
+FFA_VERSION ABI. When discovery is successful, the ARM_SMCCC_FEATURES
+mechanism creates a U-Boot device for the FF-A bus and binds the Arm FF-A driver
+with the device using device_bind_driver().
+
+At this stage the FF-A bus is registered with the DM and can be interacted with using
+the DM APIs.
+
+Clients are able to probe then use the FF-A bus by calling uclass_first_device().
+Please refer to the armffa command implementation as an example of how to probe
+and interact with the FF-A bus.
+
+When calling uclass_first_device(), the FF-A driver is probed and ends up calling
+ffa_do_probe() provided by the Uclass which does the following:
+
+ - saving the FF-A framework version in uc_priv
+ - querying from secure world the u-boot endpoint ID
+ - querying from secure world the supported features of FFA_RXTX_MAP
+ - mapping the RX/TX buffers
+ - querying from secure world all the partitions information
+
+When one of the above actions fails, probing fails and the driver stays not active
+and can be probed again if needed.
+
+Requirements for clients
+-------------------------------------
+
+When using the FF-A bus with EFI, clients must query the SPs they are looking for
+during EFI boot-time mode using the service UUID.
+
+The RX/TX buffers are only available at EFI boot-time. Querying partitions is
+done at boot time and data is cached for future use.
+
+RX/TX buffers should be unmapped before EFI runtime mode starts.
+The driver provides a bus operation for that called ffa_rxtx_unmap().
+
+The user should call ffa_rxtx_unmap() to unmap the RX/TX buffers when required
+(e.g: at efi_exit_boot_services()).
+
+The Linux kernel allocates its own RX/TX buffers. To be able to register these kernel buffers
+with secure world, the U-Boot's RX/TX buffers should be unmapped before EFI runtime starts.
+
+When invoking FF-A direct messaging, clients should specify which ABI protocol
+they want to use (32-bit vs 64-bit). Selecting the protocol means using
+the 32-bit or 64-bit version of FFA_MSG_SEND_DIRECT_{REQ, RESP}.
+The calling convention between U-Boot and the secure world stays the same: SMC32.
+
+Requirements for user drivers
+-------------------------------------
+
+Users who want to implement their custom FF-A device driver while reusing the FF-A Uclass can do so
+by implementing their own invoke_ffa_fn() in the user driver.
+
+The bus driver layer
+------------------------------
+
+FF-A support comes on top of the SMCCC layer and is implemented by the FF-A Uclass drivers/firmware/arm-ffa/arm-ffa-uclass.c
+
+The following features are provided:
+
+- Support for the 32-bit version of the following ABIs:
+
+ - FFA_VERSION
+ - FFA_ID_GET
+ - FFA_FEATURES
+ - FFA_PARTITION_INFO_GET
+ - FFA_RXTX_UNMAP
+ - FFA_RX_RELEASE
+ - FFA_RUN
+ - FFA_ERROR
+ - FFA_SUCCESS
+ - FFA_INTERRUPT
+ - FFA_MSG_SEND_DIRECT_REQ
+ - FFA_MSG_SEND_DIRECT_RESP
+
+- Support for the 64-bit version of the following ABIs:
+
+ - FFA_RXTX_MAP
+ - FFA_MSG_SEND_DIRECT_REQ
+ - FFA_MSG_SEND_DIRECT_RESP
+
+- Processing the received data from the secure world/hypervisor and caching it
+
+- Hiding from upper layers the FF-A protocol and registers details. Upper
+ layers focus on exchanged data, FF-A support takes care of how to transport
+ that to the secure world/hypervisor using FF-A
+
+- FF-A support provides driver operations to be used by upper layers:
+
+ - ffa_partition_info_get
+ - ffa_sync_send_receive
+ - ffa_rxtx_unmap
+
+- FF-A bus discovery makes sure FF-A framework is responsive and compatible
+ with the driver
+
+- FF-A bus can be compiled and used without EFI
+
+Relationship between the sandbox emulator and the FF-A device
+---------------------------------------------------------------
+
+::
+
+ => dm tree
+
+ Class Index Probed Driver Name
+ -----------------------------------------------------------
+ ffa_emul 0 [ + ] sandbox_ffa_emul `-- arm-ffa-emul
+ ffa 0 [ ] sandbox_arm_ffa `-- sandbox-arm-ffa
+
+The armffa command
+-----------------------------------
+
+armffa is a command showcasing how to use the FF-A bus and how to invoke the driver operations.
+
+Please refer the command documentation at :doc:`../usage/cmd/armffa`
+
+Example of boot logs with FF-A enabled
+--------------------------------------
+
+For example, when using FF-A with Corstone-1000, debug logs enabled, the output is as follows:
+
+::
+
+ U-Boot 2023.01 (May 10 2023 - 11:08:07 +0000) corstone1000 aarch64
+
+ DRAM: 2 GiB
+ Arm FF-A framework discovery
+ FF-A driver 1.0
+ FF-A framework 1.0
+ FF-A versions are compatible
+ ...
+ FF-A driver 1.0
+ FF-A framework 1.0
+ FF-A versions are compatible
+ EFI: MM partition ID 0x8003
+ ...
+ EFI stub: Booting Linux Kernel...
+ ...
+ Linux version 6.1.9-yocto-standard (oe-user@oe-host) (aarch64-poky-linux-musl-gcc (GCC) 12.2.0, GNU ld (GNU Binutils) 2.40.202301193
+ Machine model: ARM Corstone1000 FPGA MPS3 board
+
+Contributors
+------------
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+
+.. _`FF-A v1.0 specification`: https://documentation-service.arm.com/static/5fb7e8a6ca04df4095c1d65e
+.. _`SMC Calling Convention v1.2 specification`: https://documentation-service.arm.com/static/5f8edaeff86e16515cdbe4c6
diff --git a/doc/arch/index.rst b/doc/arch/index.rst
index b8da4b8..2f916f4 100644
--- a/doc/arch/index.rst
+++ b/doc/arch/index.rst
@@ -8,6 +8,7 @@
arc
arm64
+ arm64.ffa
m68k
mips
nios2
diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst
index 77ca6bc..a3631de 100644
--- a/doc/arch/sandbox/sandbox.rst
+++ b/doc/arch/sandbox/sandbox.rst
@@ -200,6 +200,7 @@
U-Boot sandbox supports these emulations:
+- Arm FF-A
- Block devices
- Chrome OS EC
- GPIO
diff --git a/doc/board/asus/grouper_common.rst b/doc/board/asus/grouper_common.rst
new file mode 100644
index 0000000..2e4450b
--- /dev/null
+++ b/doc/board/asus/grouper_common.rst
@@ -0,0 +1,94 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the ASUS/Google Nexus 7 (2012)
+=========================================
+
+``DISCLAMER!`` Moving your ASUS/Google Nexus 7 (2012) to use
+U-Boot assumes replacement of the vendor ASUS bootloader. Vendor
+android firmwares will no longer be able to run on the device.
+This replacement IS reversible.
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Pack U-Boot into repart-block
+- Flash repart-block into the eMMC
+- Boot
+- Self Upgrading
+
+Build U-Boot
+------------
+
+Device support is implemented by applying config fragment to a generic
+board defconfig. Valid fragments are ``grouper_E1565.config``,
+``grouper_PM269.config`` and ``tilapia.config``.
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=arm-linux-gnueabi-
+ $ make grouper_common_defconfig grouper_E1565.config # For maxim based grouper
+ $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+image, ready for flashing (but check the next section for additional
+adjustments).
+
+Pack U-Boot into repar-block
+----------------------------
+
+``DISCLAMER!`` All questions related to re-crypt work should be asked
+in re-crypt repo issues. NOT HERE!
+
+re-crypt is a small script which packs ``u-boot-dtb-tegra.bin`` in
+form usable by device. This process is required only on the first
+installation or to recover the device in case of a failed update.
+You need to know your tablet's individual SBK to continue.
+
+.. code-block:: bash
+
+ $ git clone https://github.com/clamor-s/re-crypt.git
+ $ cd re-crypt # place your u-boot-dtb-regra.bin here
+ $ ./re-crypt.sh -d grouper -k deadbeefdeadc0dedeadd00dfee1dead
+
+Script will produce you a ``repart-block.bin`` ready to flash.
+
+Flash repart-block into the eMMC
+--------------------------------
+
+``DISCLAMER!`` All questions related to NvFlash should be asked
+in the proper place. NOT HERE! Flashing repart-block will erase
+all your eMMC, so make a backup before!
+
+``repart-block.bin`` contains BCT and bootloader in encrypted state
+in form which can just be written RAW at the start of eMMC.
+
+.. code-block:: bash
+
+ $ wheelie --blob blob.bin
+ $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+
+Boot
+----
+
+After flashing ``repart-block.bin`` the device should reboot and turn
+itself off. This is normal behavior if no boot configuration is
+found.
+
+To boot Linux, U-Boot will look for an ``extlinux.conf`` configuration
+on eMMC. Additionally if Volume Down button is pressed while booting
+device will enter bootmenu. Bootmenu contains entries to mount eMMC as
+mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot
+console and update bootloader (check next chapter).
+
+Flashing ``repart-block.bin`` eliminates vendor restriction on eMMC
+and allows the user to use/partition it in any way the user desires.
+
+Self Upgrading
+--------------
+
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the
+eMMC (using ability of u-boot to mount it). Enter bootmenu, choose
+update bootloader option with Power button and U-Boot should update
+itself. Once the process is completed, U-Boot will ask to press any
+button to reboot.
diff --git a/doc/board/asus/index.rst b/doc/board/asus/index.rst
new file mode 100644
index 0000000..87e535f
--- /dev/null
+++ b/doc/board/asus/index.rst
@@ -0,0 +1,10 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+ASUS
+====
+
+.. toctree::
+ :maxdepth: 2
+
+ grouper_common
+ transformer_t30
diff --git a/doc/board/asus/transformer_t30.rst b/doc/board/asus/transformer_t30.rst
new file mode 100644
index 0000000..b6b6101
--- /dev/null
+++ b/doc/board/asus/transformer_t30.rst
@@ -0,0 +1,116 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the ASUS Transformer device family
+=============================================
+
+``DISCLAMER!`` Moving your ASUS Transformer to use U-Boot
+assumes replacement of the vendor ASUS bootloader. Vendor
+android firmwares will no longer be able to run on the device.
+This replacement IS reversible.
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Pack U-Boot into repart-block
+- Flash repart-block into the eMMC
+- Flash repart-block into TF600T SPI flash
+- Boot
+- Self Upgrading
+
+Build U-Boot
+------------
+
+Device support is implemented by applying config fragment
+to a generic board defconfig. Valid fragments are ``tf201.config``,
+``tf300t.config``, ``tf300tg.config``, ``tf300tl.config``,
+``tf700t.config``, ``tf600t.config`` and ``p1801-t.config``.
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=arm-linux-gnueabi-
+ $ make transformer_t30_defconfig tf201.config # For TF201
+ $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+image, ready for flashing (but check the next section for additional
+adjustments).
+
+Pack U-Boot into repar-block
+----------------------------
+
+``DISCLAMER!`` All questions related to re-crypt work should be asked
+in re-crypt repo issues. NOT HERE!
+
+re-crypt is a small script which packs ``u-boot-dtb-tegra.bin`` in
+form usable by device. This process is required only on the first
+installation or to recover the device in case of a failed update.
+You need to know your tablet's individual SBK to continue.
+
+.. code-block:: bash
+
+ $ git clone https://github.com/clamor-s/re-crypt.git
+ $ cd re-crypt # place your u-boot-dtb-regra.bin here
+ $ ./re-crypt.sh -d tf201 -k deadbeefdeadc0dedeadd00dfee1dead
+
+Script will produce you a `repart-block.bin` ready to flash.
+
+Flash repart-block into the eMMC
+--------------------------------
+
+``DISCLAMER!`` All questions related to NvFlash should be asked
+in the proper place. NOT HERE! Flashing repart-block will erase
+all your eMMC, so make a backup before!
+
+``repart-block.bin`` contains BCT and bootloader in encrypted state
+in form which can just be written RAW at the start of eMMC.
+
+.. code-block:: bash
+
+ $ wheelie --blob blob.bin
+ $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+
+Flash repart-block into TF600T SPI flash
+----------------------------------------
+
+Unlike other transformers TF600T uses separate 4 MB SPI flash which
+contains all data required for boot. It is flashed from within u-boot
+itself preloaded into RAM using fusee gelee. After creating your
+``repart-block.bin`` you have to place it on a 1st partition of microSD
+card formated in fat. Then insert this microSD card into your tablet
+and boot it using fusee gelee and u-boot which was included into
+repart-block.bin, while booting you must hold volume down button.
+Process should take less then a minute, if everything goes correct,
+on microSD will appear ``spi-flash-backup.bin`` file, which is dump of
+your spi flash content and can be used to restore UEFI, do not loose it,
+tablet will power itself off.
+
+Self-updating of u-boot is performed by placing ``u-boot-dtb-tegra.bin``
+on 1st partition of microSD, inserting it into tablet and booting with
+pressed volume down button.
+
+Boot
+----
+
+After flashing ``repart-block.bin`` the device should reboot and turn
+itself off. This is normal behavior if no boot configuration is
+found.
+
+To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD
+and then on eMMC. Additionally if Volume Down button is pressed
+while booting device will enter bootmenu. Bootmenu contains entries
+to mount MicroSD and eMMC as mass storage, fastboot, reboot, reboot
+RCM, poweroff, enter U-Boot console and update bootloader (check next
+chapter).
+
+Flashing ``repart-block.bin`` eliminates vendor restriction on eMMC
+and allows the user to use/partition it in any way the user desires.
+
+Self Upgrading
+--------------
+
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the
+MicroSD card and insert it into the tablet. Enter bootmenu, choose
+update bootloader option with Power button and U-Boot should update
+itself. Once the process is completed, U-Boot will ask to press any
+button to reboot.
diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst
index 0fe95af..d660a22 100644
--- a/doc/board/coreboot/coreboot.rst
+++ b/doc/board/coreboot/coreboot.rst
@@ -51,6 +51,40 @@
This has only been lightly tested.
+CBFS access
+-----------
+
+You can use the 'cbfs' commands to access the Coreboot filesystem::
+
+ => cbfsinit
+ => cbfsinfo
+
+ CBFS version: 0x31313132
+ ROM size: 0x100000
+ Boot block size: 0x4
+ CBFS size: 0xffdfc
+ Alignment: 64
+ Offset: 0x200
+
+ => cbfsls
+ size type name
+ ------------------------------------------
+ 32 cbfs header cbfs master header
+ 16720 17 fallback/romstage
+ 53052 17 fallback/ramstage
+ 398 raw config
+ 715 raw revision
+ 117 raw build_info
+ 4044 raw fallback/dsdt.aml
+ 640 cmos layout cmos_layout.bin
+ 17804 17 fallback/postcar
+ 335797 payload fallback/payload
+ 607000 null (empty)
+ 10752 bootblock bootblock
+
+ 12 file(s)
+
+ =>
Memory map
----------
@@ -100,3 +134,23 @@
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
+
+coreboot in CI
+--------------
+
+CI runs tests using a pre-built coreboot image. This ensures that U-Boot can
+boot as a coreboot payload, based on a known-good build of coreboot.
+
+To update the `coreboot.rom` file which is used:
+
+#. Build coreboot with `CONFIG_LINEAR_FRAMEBUFFER=y`. If using `make menuconfig`
+ this is under
+ `Devices ->Display->Framebuffer mode->Linear "high resolution" framebuffer`.
+
+#. Compress the resulting `coreboot.rom`::
+
+ xz -c /path/to/coreboot/build/coreboot.rom >coreboot.rom.xz
+
+#. Upload the file to Google drive
+
+#. Send a patch to change the file ID used by wget in the CI yaml files.
diff --git a/doc/board/emulation/blkdev.rst b/doc/board/emulation/blkdev.rst
index dc83a00..f187ff2 100644
--- a/doc/board/emulation/blkdev.rst
+++ b/doc/board/emulation/blkdev.rst
@@ -11,8 +11,8 @@
.. code-block:: bash
-device sdhci-pci,sd-spec-version=3 \
- -device sd-card,drive=MMC1 \
- -drive if=none,file=disk.img,format=raw,id=MMC1
+ -drive if=none,file=disk.img,format=raw,id=MMC1 \
+ -device sd-card,drive=MMC1
* NVMe
@@ -36,3 +36,13 @@
-device qemu-xhci \
-drive if=none,file=disk.img,format=raw,id=USB1 \
-device usb-storage,drive=USB1
+
+* Virtio
+
+ .. code-block:: bash
+
+ -drive if=none,file=disk.img,format=raw,id=VIRTIO1 \
+ -device virtio-blk,drive=VIRTIO1
+
+ .. note::
+ As of v2023.07 U-Boot does not have a driver for virtio-scsi-pci.
diff --git a/doc/board/emulation/qemu-arm.rst b/doc/board/emulation/qemu-arm.rst
index b42d924..78bcc3e 100644
--- a/doc/board/emulation/qemu-arm.rst
+++ b/doc/board/emulation/qemu-arm.rst
@@ -67,6 +67,10 @@
Additional peripherals that have been tested to work in both U-Boot and Linux
can be enabled with the following command line parameters:
+- To add a video console, remove "-nographic" and add e.g.::
+
+ -serial stdio -device VGA
+
- To add a Serial ATA disk via an Intel ICH9 AHCI controller, pass e.g.::
-drive if=none,file=disk.img,format=raw,id=mydisk \
@@ -80,6 +84,10 @@
-device usb-ehci,id=ehci
+- To add a USB keyboard attached to an emulated xHCI controller, pass e.g.::
+
+ -device qemu-xhci,id=xhci -device usb-kbd,bus=xhci.0
+
- To add an NVMe disk, pass e.g.::
-drive if=none,file=disk.img,id=mydisk -device nvme,drive=mydisk,serial=foo
@@ -90,6 +98,74 @@
These have been tested in QEMU 2.9.0 but should work in at least 2.5.0 as well.
+Booting distros
+---------------
+
+It is possible to install and boot a standard Linux distribution using
+qemu_arm64 by setting up a root disk::
+
+ qemu-img create root.img 20G
+
+then using the installer to install. For example, with Debian 12::
+
+ qemu-system-aarch64 \
+ -machine virt -cpu cortex-a53 -m 4G -smp 4 \
+ -bios u-boot.bin \
+ -serial stdio -device VGA \
+ -nic user,model=virtio-net-pci \
+ -device virtio-rng-pci \
+ -device qemu-xhci,id=xhci \
+ -device usb-kbd -device usb-tablet \
+ -drive if=virtio,file=debian-12.0.0-arm64-netinst.iso,format=raw,readonly=on,media=cdrom \
+ -drive if=virtio,file=root.img,format=raw,media=disk
+
+The output will be something like this::
+
+ U-Boot 2023.10-rc2-00075-gbe8fbe718e35 (Aug 11 2023 - 08:38:49 +0000)
+
+ DRAM: 4 GiB
+ Core: 51 devices, 14 uclasses, devicetree: board
+ Flash: 64 MiB
+ Loading Environment from Flash... *** Warning - bad CRC, using default environment
+
+ In: serial,usbkbd
+ Out: serial,vidconsole
+ Err: serial,vidconsole
+ Bus xhci_pci: Register 8001040 NbrPorts 8
+ Starting the controller
+ USB XHCI 1.00
+ scanning bus xhci_pci for devices... 3 USB Device(s) found
+ Net: eth0: virtio-net#32
+ Hit any key to stop autoboot: 0
+ Scanning for bootflows in all bootdevs
+ Seq Method State Uclass Part Name Filename
+ --- ----------- ------ -------- ---- ------------------------ ----------------
+ Scanning global bootmeth 'efi_mgr':
+ Scanning bootdev 'fw-cfg@9020000.bootdev':
+ fatal: no kernel available
+ scanning bus for devices...
+ Scanning bootdev 'virtio-blk#34.bootdev':
+ 0 efi ready virtio 2 virtio-blk#34.bootdev.par efi/boot/bootaa64.efi
+ ** Booting bootflow 'virtio-blk#34.bootdev.part_2' with efi
+ Using prior-stage device tree
+ Failed to load EFI variables
+ Error: writing contents
+ ** Unable to write file ubootefi.var **
+ Failed to persist EFI variables
+ Missing TPMv2 device for EFI_TCG_PROTOCOL
+ Booting /efi\boot\bootaa64.efi
+ Error: writing contents
+ ** Unable to write file ubootefi.var **
+ Failed to persist EFI variables
+ Welcome to GRUB!
+
+Standard boot looks through various available devices and finds the virtio
+disks, then boots from the first one. After a second or so the grub menu appears
+and you can work through the installer flow normally.
+
+After the installation, you can boot into the installed system by running QEMU
+again without the drive argument corresponding to the installer CD image.
+
Enabling TPMv2 support
----------------------
diff --git a/doc/board/emulation/qemu-riscv.rst b/doc/board/emulation/qemu-riscv.rst
index 509bf7c..61137bc 100644
--- a/doc/board/emulation/qemu-riscv.rst
+++ b/doc/board/emulation/qemu-riscv.rst
@@ -133,6 +133,16 @@
You will have to run 'scsi scan' to use it.
+A video console can be emulated in RISC-V virt machine by removing "-nographic"
+and adding::
+
+ -serial stdio -device VGA
+
+In addition, a usb keyboard can be attached to an emulated xHCI controller in
+RISC-V virt machine as an option of input devices by adding::
+
+ -device qemu-xhci,id=xhci -device usb-kbd,bus=xhci.0
+
Running with KVM
----------------
diff --git a/doc/board/emulation/qemu-x86.rst b/doc/board/emulation/qemu-x86.rst
index e7dd4e9..15f56b6 100644
--- a/doc/board/emulation/qemu-x86.rst
+++ b/doc/board/emulation/qemu-x86.rst
@@ -113,7 +113,87 @@
'-cpu pentium' won't work for obvious reasons that the processor only
supports 32-bit.
-Note 64-bit support is very preliminary at this point. Lots of features
-are missing in the 64-bit world. One notable feature is the VGA console
-support which is currently missing, so that you must specify '-nographic'
-to get 64-bit U-Boot up and running.
+Booting distros
+---------------
+
+It is possible to install and boot a standard Linux distribution using
+qemu-x86_64 by setting up a root disk::
+
+ qemu-img create root.img 10G
+
+then using the installer to install. For example, with Ubuntu 2023.04::
+
+ qemu-system-x86_64 -m 8G -smp 4 -bios /tmp/b/qemu-x86_64/u-boot.rom \
+ -drive file=root.img,if=virtio,driver=raw \
+ -drive file=ubuntu-23.04-desktop-amd64.iso,if=virtio,driver=raw
+
+You can also add `-serial mon:stdio` if you want the serial console to show as
+well as the video.
+
+The output will be something like this::
+
+ U-Boot SPL 2023.07 (Jul 23 2023 - 08:00:12 -0600)
+ Trying to boot from SPI
+ Jumping to 64-bit U-Boot: Note many features are missing
+
+
+ U-Boot 2023.07 (Jul 23 2023 - 08:00:12 -0600)
+
+ CPU: QEMU Virtual CPU version 2.5+
+ DRAM: 8 GiB
+ Core: 20 devices, 13 uclasses, devicetree: separate
+ Loading Environment from nowhere... OK
+ Model: QEMU x86 (I440FX)
+ Net: e1000: 52:54:00:12:34:56
+ eth0: e1000#0
+ Hit any key to stop autoboot: 0
+ Scanning for bootflows in all bootdevs
+ Seq Method State Uclass Part Name Filename
+ --- ----------- ------ -------- ---- ------------------------ ----------------
+ Scanning global bootmeth 'efi_mgr':
+ Hunting with: nvme
+ Hunting with: qfw
+ Hunting with: scsi
+ scanning bus for devices...
+ Hunting with: virtio
+ Scanning bootdev 'qfw_pio.bootdev':
+ fatal: no kernel available
+ Scanning bootdev 'virtio-blk#0.bootdev':
+ Scanning bootdev 'virtio-blk#1.bootdev':
+ 0 efi ready virtio 2 virtio-blk#1.bootdev.part efi/boot/bootx64.efi
+ ** Booting bootflow 'virtio-blk#1.bootdev.part_2' with efi
+ EFI using ACPI tables at f0060
+ efi_install_fdt() WARNING: Can't have ACPI table and device tree - ignoring DT.
+ efi_run_image() Booting /efi\boot\bootx64.efi
+ error: file `/boot/' not found.
+
+Standard boot looks through various available devices and finds the virtio
+disks, then boots from the first one. After a second or so the grub menu appears
+and you can work through the installer flow normally.
+
+Note that standard boot will not find 32-bit distros, since it looks for a
+different filename.
+
+Current limitations
+-------------------
+
+Only qemu-x86-64 can be used for booting distros, since qemu-x86 (the 32-bit
+version of U-Boot) seems to have an EFI bug leading to the boot handing after
+Linux is selected from grub, e.g. with `debian-12.1.0-i386-netinst.iso`::
+
+ ** Booting bootflow 'virtio-blk#1.bootdev.part_2' with efi
+ EFI using ACPI tables at f0180
+ efi_install_fdt() WARNING: Can't have ACPI table and device tree - ignoring DT.
+ efi_run_image() Booting /efi\boot\bootia32.efi
+ Failed to open efi\boot\root=/dev/sdb3 - Not Found
+ Failed to load image 큀緃: Not Found
+ start_image() returned Not Found, falling back to default loader
+ Welcome to GRUB!
+
+The bochs video driver also seems to cause problems before the OS is able to
+show a display.
+
+Finally, the use of `-M accel=kvm` is intended to use the native CPU's
+virtual-machine features to accelerate operation, but this causes U-Boot to hang
+when jumping 64-bit mode, at least on AMD machines. This may be a bug in U-Boot
+or something else.
diff --git a/doc/board/htc/endeavoru.rst b/doc/board/htc/endeavoru.rst
new file mode 100644
index 0000000..950c713
--- /dev/null
+++ b/doc/board/htc/endeavoru.rst
@@ -0,0 +1,89 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the HTC One X (endeavoru)
+====================================
+
+``DISCLAMER!`` Moving your HTC ONe X to use U-Boot assumes
+replacement of the vendor hboot. Vendor android firmwares
+will no longer be able to run on the device.
+This replacement IS reversible.
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Pack U-Boot into repart-block
+- Flash repart-block into the eMMC
+- Boot
+- Self Upgrading
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=arm-linux-gnueabi-
+ $ make endeavoru_defconfig
+ $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+image, ready for flashing (but check the next section for additional
+adjustments).
+
+Pack U-Boot into repar-block
+----------------------------
+
+``DISCLAMER!`` All questions related to re-crypt work should be
+asked in re-crypt repo issues. NOT HERE!
+
+re-crypt is a small script which packs ``u-boot-dtb-tegra.bin`` in
+form usable by device. This process is required only on the first
+installation or to recover the device in case of a failed update.
+
+.. code-block:: bash
+
+ $ git clone https://github.com/clamor-s/re-crypt.git
+ $ cd re-crypt # place your u-boot-dtb-regra.bin here
+ $ ./re-crypt.sh -d endeavoru
+
+Script will produce you a ``repart-block.bin`` ready to flash.
+
+Flash repart-block into the eMMC
+--------------------------------
+
+``DISCLAMER!`` All questions related to NvFlash should be asked
+in the proper place. NOT HERE! Flashing repart-block will erase
+all your eMMC, so make a backup before!
+
+``repart-block.bin`` contains BCT and bootloader in encrypted state
+in form which can just be written RAW at the start of eMMC.
+
+.. code-block:: bash
+
+ $ wheelie --blob blob.bin
+ $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+
+Boot
+----
+
+After flashing ``repart-block.bin`` the device should reboot and turn
+itself off. This is normal behavior if no boot configuration is
+found.
+
+To boot Linux, U-Boot will look for an ``extlinux.conf`` configuration
+on eMMC. Additionally if Volume Down button is pressed while booting
+device will enter bootmenu. Bootmenu contains entries to mount eMMC as
+mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot
+console and update bootloader (check next chapter).
+
+Flashing ``repart-block.bin`` eliminates vendor restriction on eMMC
+and allows the user to use/partition it in any way the user desires.
+
+Self Upgrading
+--------------
+
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the
+eMMC (using ability of u-boot to mount it). Enter bootmenu, choose
+update bootloader option with Power button and U-Boot should update
+itself. Once the process is completed, U-Boot will ask to press any
+button to reboot.
diff --git a/doc/board/htc/index.rst b/doc/board/htc/index.rst
new file mode 100644
index 0000000..955c9b9
--- /dev/null
+++ b/doc/board/htc/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+HTC
+===
+
+.. toctree::
+ :maxdepth: 2
+
+ endeavoru
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 84aa8c1..0194f0a 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -14,6 +14,7 @@
anbernic/index
apple/index
armltd/index
+ asus/index
atmel/index
beacon/index
broadcom/index
@@ -25,8 +26,10 @@
gateworks/index
google/index
highbank/index
+ htc/index
intel/index
kontron/index
+ lg/index
mediatek/index
microchip/index
nokia/index
diff --git a/doc/board/lg/index.rst b/doc/board/lg/index.rst
new file mode 100644
index 0000000..3af3681
--- /dev/null
+++ b/doc/board/lg/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+LG
+==
+
+.. toctree::
+ :maxdepth: 2
+
+ x3_t30
diff --git a/doc/board/lg/x3_t30.rst b/doc/board/lg/x3_t30.rst
new file mode 100644
index 0000000..5c564aa
--- /dev/null
+++ b/doc/board/lg/x3_t30.rst
@@ -0,0 +1,93 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the LG X3 T30 device family
+======================================
+
+``DISCLAMER!`` Moving your LG P880 or P895 to use U-Boot
+assumes replacement of the vendor LG bootloader. Vendor
+android firmwares will no longer be able to run on the
+device. This replacement IS reversible.
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Pack U-Boot into repart-block
+- Flash repart-block into the eMMC
+- Boot
+- Self Upgrading
+
+Build U-Boot
+------------
+
+Device support is implemented by applying config fragment to a generic
+board defconfig. Valid fragments are ``p880.config`` and ``p895.config``.
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=arm-linux-gnueabi-
+ $ make x3_t30_defconfig p895.config # For LG Optimus Vu
+ $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+image, ready for flashing (but check the next section for additional
+adjustments).
+
+Pack U-Boot into repar-block
+----------------------------
+
+``DISCLAMER!`` All questions related to re-crypt work should be
+asked in re-crypt repo issues. NOT HERE!
+
+re-crypt is a small script which packs ``u-boot-dtb-tegra.bin`` in
+form usable by device. This process is required only on the first
+installation or to recover the device in case of a failed update.
+
+.. code-block:: bash
+
+ $ git clone https://github.com/clamor-s/re-crypt.git
+ $ cd re-crypt # place your u-boot-dtb-regra.bin here
+ $ ./re-crypt.sh -d p895
+
+Script will produce you a ``repart-block.bin`` ready to flash.
+
+Flash repart-block into the eMMC
+--------------------------------
+
+``DISCLAMER!`` All questions related to NvFlash should be asked
+in the proper place. NOT HERE! Flashing repart-block will erase
+all your eMMC, so make a backup before!
+
+``repart-block.bin`` contains BCT and bootloader in encrypted state
+in form which can just be written RAW at the start of eMMC.
+
+.. code-block:: bash
+
+ $ wheelie --blob blob.bin
+ $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+
+Boot
+----
+
+After flashing ``repart-block.bin`` the device should reboot and turn
+itself off. This is normal behavior if no boot configuration is
+found.
+
+To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD
+and then on eMMC. Additionally if Volume Down button is pressed
+while booting device will enter bootmenu. Bootmenu contains entries
+to mount MicroSD and eMMC as mass storage, fastboot, reboot, reboot
+RCM, poweroff, enter U-Boot console and update bootloader (check next
+chapter).
+
+Flashing ``repart-block.bin`` eliminates vendor restriction on eMMC
+and allows the user to use/partition it in any way the user desires.
+
+Self Upgrading
+--------------
+
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the
+eMMC (using ability of u-boot to mount it). Enter bootmenu, choose
+update bootloader option with Power button and U-Boot should update
+itself. Once the process is completed, U-Boot will ask to press any
+button to reboot.
diff --git a/doc/board/nxp/imx8mp_evk.rst b/doc/board/nxp/imx8mp_evk.rst
index e7cc7b3..72175db 100644
--- a/doc/board/nxp/imx8mp_evk.rst
+++ b/doc/board/nxp/imx8mp_evk.rst
@@ -37,21 +37,22 @@
.. code-block:: bash
+Note: builddir is U-Boot build directory (source directory for in-tree builds).
+
$ export CROSS_COMPILE=aarch64-poky-linux-
$ make O=build imx8mp_evk_defconfig
- $ cp ../imx-atf/build/imx8mp/release/bl31.bin ./build/bl31.bin
- $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_202006.bin ./build/
- $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_202006.bin ./build/
- $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_202006.bin ./build/
- $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_202006.bin ./build/
- $ export ATF_LOAD_ADDR=0x970000
- $ make O=build
+ $ cp ../imx-atf/build/imx8mp/release/bl31.bin $(builddir)
+ $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_202006.bin $(builddir)
+ $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_202006.bin $(builddir)
+ $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_202006.bin $(builddir)
+ $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_202006.bin $(builddir)
+ $ make
Burn the flash.bin to the MicroSD card at offset 32KB:
.. code-block:: bash
- $sudo dd if=build/flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync
+ $ sudo dd if=flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync
Boot
----
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 49a0c57..de9fe8e 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -91,17 +91,22 @@
- Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399)
* rk3566
- - Anbernic RGxx3 (rgxx3-rk3566)
+ - Anbernic RGxx3 (anbernic-rgxx3-rk3566)
+ - Pine64 Quartz64-A Board (quartz64-a-rk3566)
+ - Pine64 Quartz64-B Board (quartz64-b-rk3566)
+ - Pine64 SOQuartz on Blade (soquartz-blade-rk3566)
+ - Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566)
+ - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566)
+ - Radxa CM3 IO Board (radxa-cm3-io-rk3566)
* rk3568
- Rockchip Evb-RK3568 (evb-rk3568)
+ - EmbedFire LubanCat 2 (lubancat-2-rk3568)
+ - FriendlyElec NanoPi R5C (nanopi-r5c-rk3568)
+ - FriendlyElec NanoPi R5S (nanopi-r5s-rk3568)
- Hardkernel ODROID-M1 (odroid-m1-rk3568)
- - Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig)
- - Pine64 Quartz64-B Board (quartz64-b-rk3566_defconfig)
- - Pine64 SOQuartz on Blade (soquartz-blade-rk3566_defconfig)
- - Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566_defconfig)
- - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig)
- - Radxa E25 Carrier Board (radxa-e25-rk3568_defconfig)
+ - Radxa E25 Carrier Board (radxa-e25-rk3568)
+ - Radxa ROCK 3 Model A (rock-3a-rk3568)
* rk3588
- Rockchip EVB (evb-rk3588)
diff --git a/doc/board/ti/am335x_evm.rst b/doc/board/ti/am335x_evm.rst
index ee4faec..3332d51 100644
--- a/doc/board/ti/am335x_evm.rst
+++ b/doc/board/ti/am335x_evm.rst
@@ -201,3 +201,65 @@
U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
U-Boot # nand erase.part u-boot-spl-os
U-Boot # nand write ${fdtaddr} u-boot-spl-os
+
+USB device
+----------
+
+The platform code for am33xx based designs is legacy in the sense that
+it is not fully compliant with the driver model in its management of the
+various resources. This is particularly true for the USB Ethernet gadget
+which will automatically be bound to the first USB Device Controller
+(UDC). This make the USB Ethernet gadget work out of the box on common
+boards like the Beagle Bone Blacks and by default will prevents other
+gadgets to be used.
+
+The output of the 'dm tree' command shows which driver is bound to which
+device, so the user can easily configure their platform differently from
+the command line:
+
+.. code-block:: text
+
+ => dm tree
+ Class Index Probed Driver Name
+ -----------------------------------------------------------
+ [...]
+ misc 0 [ + ] ti-musb-wrapper | |-- usb@47400000
+ usb 0 [ + ] ti-musb-peripheral | | |-- usb@47401000
+ ethernet 1 [ + ] usb_ether | | | `-- usb_ether
+ bootdev 3 [ ] eth_bootdev | | | `-- usb_ether.bootdev
+ usb 0 [ ] ti-musb-host | | `-- usb@47401800
+
+Typically here any network command performed using the usb_ether
+interface would work, while using other gadgets would fail:
+
+.. code-block:: text
+
+ => fastboot usb 0
+ All UDC in use (1 available), use the unbind command
+ g_dnl_register: failed!, error: -19
+ exit not allowed from main input shell.
+
+As hinted by the primary error message, the only controller available
+(usb@47401000) is currently bound to the usb_ether driver, which makes
+it impossible for the fastboot command to bind with this device (at
+least from a bootloader point of view). The solution here would be to
+use the unbind command specifying the class and index parameters (as
+shown above in the 'dm tree' output) to target the driver to unbind:
+
+.. code-block:: text
+
+ => unbind ethernet 1
+
+The output of the 'dm tree' command now shows the availability of the
+first USB device controller, the fastboot gadget will now be able to
+bind with it:
+
+.. code-block:: text
+
+ => dm tree
+ Class Index Probed Driver Name
+ -----------------------------------------------------------
+ [...]
+ misc 0 [ + ] ti-musb-wrapper | |-- usb@47400000
+ usb 0 [ ] ti-musb-peripheral | | |-- usb@47401000
+ usb 0 [ ] ti-musb-host | | `-- usb@47401800
diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst
index 637985c..5ed17c0 100644
--- a/doc/board/ti/am62x_sk.rst
+++ b/doc/board/ti/am62x_sk.rst
@@ -54,7 +54,7 @@
Sources:
--------
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_boot_sources
:end-before: .. k3_rst_include_end_boot_sources
@@ -62,17 +62,17 @@
----------------
0. Setup the environment variables:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_desc
:end-before: .. k3_rst_include_end_common_env_vars_desc
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_board_env_vars_desc
:end-before: .. k3_rst_include_end_board_env_vars_desc
Set the variables corresponding to this platform:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
.. code-block:: bash
@@ -89,14 +89,14 @@
1. Trusted Firmware-A:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_tfa
:end-before: .. k3_rst_include_end_build_steps_tfa
2. OP-TEE:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_optee
:end-before: .. k3_rst_include_end_build_steps_optee
@@ -104,13 +104,13 @@
* 4.1 R5:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_spl_r5
:end-before: .. k3_rst_include_end_build_steps_spl_r5
* 4.2 A53:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_uboot
:end-before: .. k3_rst_include_end_build_steps_uboot
.. am62x_evm_rst_include_end_build_steps
@@ -246,3 +246,27 @@
- 11001010
For SW2 and SW1, the switch state in the "ON" position = 1.
+
+Debugging U-Boot
+----------------
+
+See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
+detailed setup information.
+
+.. warning::
+
+ **OpenOCD support since**: v0.12.0
+
+ If the default package version of OpenOCD in your development
+ environment's distribution needs to be updated, it might be necessary to
+ build OpenOCD from the source.
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_openocd_connect_XDS110
+ :end-before: .. k3_rst_include_end_openocd_connect_XDS110
+
+To start OpenOCD and connect to the board
+
+.. code-block:: bash
+
+ openocd -f board/ti_am625evm.cfg
diff --git a/doc/board/ti/am64x_evm.rst b/doc/board/ti/am64x_evm.rst
new file mode 100644
index 0000000..8d3795e
--- /dev/null
+++ b/doc/board/ti/am64x_evm.rst
@@ -0,0 +1,197 @@
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Nishanth Menon <nm@ti.com>
+
+AM64 Platforms
+==============
+
+Introduction:
+-------------
+The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
+providing advanced system integration to enable applications such as
+Motor Drives, PLC, Remote IO and IoT Gateways.
+
+Some highlights of this SoC are:
+
+* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
+ MCUs, and a single Cortex-M4F.
+* Two Gigabit Industrial Communication Subsystems (ICSSG).
+* Integrated Ethernet switch supporting up to a total of two external
+ ports.
+* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
+ controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
+ peripherals.
+* Centralized System Controller for Security, Power, and Resource
+ Management (DMSC).
+
+More details can be found in the Technical Reference Manual:
+ https://www.ti.com/lit/pdf/spruim2
+
+Platform information:
+
+* AM64-EVM: https://www.ti.com/tool/TMDS64EVM
+* AM64-SK: https://www.ti.com/tool/SK-AM64B
+
+Boot Flow:
+----------
+Below is the pictorial representation of boot flow:
+
+.. image:: img/boot_diagram_am64.svg
+
+- Here TIFS acts as master and provides all the critical services. R5/A53
+ requests TIFS to get these services done as shown in the above diagram.
+
+Sources:
+--------
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_boot_sources
+ :end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure:
+----------------
+0. Setup the environment variables:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_desc
+ :end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_board_env_vars_desc
+ :end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_defn
+ :end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=am64x_evm_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=am64x_evm_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ # we dont use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-am64x
+ $ # we dont use any extra TFA parameters
+ $ unset OPTEE_EXTRA_ARGS
+
+.. am64x_evm_rst_include_start_build_steps
+
+1. Trusted Firmware-A:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_tfa
+ :end-before: .. k3_rst_include_end_build_steps_tfa
+
+
+2. OP-TEE:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_optee
+ :end-before: .. k3_rst_include_end_build_steps_optee
+
+3. U-Boot:
+
+* 4.1 R5:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_spl_r5
+ :end-before: .. k3_rst_include_end_build_steps_spl_r5
+
+* 4.2 A53:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_uboot
+ :end-before: .. k3_rst_include_end_build_steps_uboot
+.. am64x_evm_rst_include_end_build_steps
+
+Target Images
+--------------
+In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
+variant (GP, HS-FS, HS-SE) requires a different source for these files.
+
+ - GP
+
+ * tiboot3-am64x-gp-evm.bin from step 3.1
+ * tispl.bin_unsigned, u-boot.img_unsigned from step 3.2
+
+ - HS-FS
+
+ * tiboot3-am64x-hs-fs-evm.bin from step 3.1
+ * tispl.bin, u-boot.img from step 3.2
+
+ - HS-SE
+
+ * tiboot3-am64x-hs-evm.bin from step 3.1
+ * tispl.bin, u-boot.img from step 3.2
+
+Image formats:
+--------------
+
+- tiboot3.bin
+
+.. image:: img/multi_cert_tiboot3.bin.svg
+
+- tispl.bin
+
+.. image:: img/nodm_tispl.bin.svg
+
+Switch Setting for Boot Mode
+----------------------------
+
+Boot Mode pins provide means to select the boot mode and options before the
+device is powered up. After every POR, they are the main source to populate
+the Boot Parameter Tables.
+
+The following table shows some common boot modes used on AM64 platform. More
+details can be found in the Technical Reference Manual:
+https://www.ti.com/lit/pdf/spruim2 under the `Boot Mode Pins` section.
+
+.. list-table:: Boot Modes for AM64x-EVM
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Switch Label
+ - SW2: 12345678
+ - SW3: 12345678
+
+ * - SD/MMC
+ - 11000010
+ - 01000000
+
+ * - xSPI/SFDP (OSPI)
+ - 11001110
+ - 01000000
+
+ * - UART
+ - 11011100
+ - 00000000
+
+.. note ::
+
+ For SW2 and SW3, the switch state in the "ON" position = 1.
+
+.. list-table:: Boot Modes for AM64x-SK
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Switch Label
+ - SW2: 12345678
+ - SW3: 12345678
+
+ * - SD/MMC
+ - 00000010
+ - 01000011
+
+ * - xSPI/SFDP (OSPI)
+ - 00000010
+ - 01110011
+
+ * - UART
+ - 00000000
+ - 00111011
+
+.. note ::
+
+ For SW2 and SW3, the switch state in the "ON" position = 1.
+ Boot bits on SK is reversed bits to the bootmode signals
diff --git a/doc/board/ti/am65x_evm.rst b/doc/board/ti/am65x_evm.rst
index 0129235..5f3c46c 100644
--- a/doc/board/ti/am65x_evm.rst
+++ b/doc/board/ti/am65x_evm.rst
@@ -287,3 +287,27 @@
sb --ymodem tispl.bin > $MAIN_DEV < $MAIN_DEV
sleep 1
sb --xmodem u-boot.img > $MAIN_DEV < $MAIN_DEV
+
+Debugging U-Boot
+----------------
+
+See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
+detailed setup information.
+
+.. warning::
+
+ **OpenOCD support since**: v0.12.0
+
+ If the default package version of OpenOCD in your development
+ environment's distribution needs to be updated, it might be necessary to
+ build OpenOCD from the source.
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_openocd_connect_XDS110
+ :end-before: .. k3_rst_include_end_openocd_connect_XDS110
+
+To start OpenOCD and connect to the board
+
+.. code-block:: bash
+
+ openocd -f board/ti_am654evm.cfg
diff --git a/doc/board/ti/img/boot_diagram_am64.svg b/doc/board/ti/img/boot_diagram_am64.svg
new file mode 100644
index 0000000..9c922a5
--- /dev/null
+++ b/doc/board/ti/img/boot_diagram_am64.svg
@@ -0,0 +1,1702 @@
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diff --git a/doc/board/ti/img/boot_diagram_am65.svg b/doc/board/ti/img/boot_diagram_am65.svg
index fe5533a..79c65e1 100644
--- a/doc/board/ti/img/boot_diagram_am65.svg
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@@ -1,4 +1,8 @@
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diff --git a/doc/board/ti/img/boot_diagram_k3_current.svg b/doc/board/ti/img/boot_diagram_k3_current.svg
index 995afd8..e38a42a 100644
--- a/doc/board/ti/img/boot_diagram_k3_current.svg
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@@ -1,4 +1,8 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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@@ -1,4 +1,8 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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index b77d679..d8e4f87 100644
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git a/doc/board/ti/img/emmc_am65x_evm_boot0.svg b/doc/board/ti/img/emmc_am65x_evm_boot0.svg
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--- a/doc/board/ti/img/emmc_j7200_evm_udafs.svg
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+</svg>
diff --git a/doc/board/ti/img/ospi_sysfw.svg b/doc/board/ti/img/ospi_sysfw.svg
index e7a0fd2..648f6fd 100644
--- a/doc/board/ti/img/ospi_sysfw.svg
+++ b/doc/board/ti/img/ospi_sysfw.svg
@@ -1,4 +1,8 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!--SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause-->
+
+<!--Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/-->
+
<svg
version="1.1"
width="321px"
diff --git a/doc/board/ti/img/sysfw.itb.svg b/doc/board/ti/img/sysfw.itb.svg
index 2d6640a..1be2b61 100644
--- a/doc/board/ti/img/sysfw.itb.svg
+++ b/doc/board/ti/img/sysfw.itb.svg
@@ -1,4 +1,8 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!--SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause-->
+
+<!--Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/-->
+
<svg
version="1.1"
width="231px"
diff --git a/doc/board/ti/j7200_evm.rst b/doc/board/ti/j7200_evm.rst
index 69abc55..2e60e22 100644
--- a/doc/board/ti/j7200_evm.rst
+++ b/doc/board/ti/j7200_evm.rst
@@ -201,3 +201,27 @@
In case of booting from eMMC, write above images into raw or UDA FS.
and set mmc partconf accordingly.
+
+Debugging U-Boot
+----------------
+
+See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
+detailed setup information.
+
+.. warning::
+
+ **OpenOCD support since**: v0.12.0
+
+ If the default package version of OpenOCD in your development
+ environment's distribution needs to be updated, it might be necessary to
+ build OpenOCD from the source.
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_openocd_connect_XDS110
+ :end-before: .. k3_rst_include_end_openocd_connect_XDS110
+
+To start OpenOCD and connect to the board
+
+.. code-block:: bash
+
+ openocd -f board/ti_j7200evm.cfg
diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst
index f4b4c19..d2a214f 100644
--- a/doc/board/ti/j721e_evm.rst
+++ b/doc/board/ti/j721e_evm.rst
@@ -228,3 +228,27 @@
PHY in the card has to be reset before it can be used for data transfer.
"do_main_cpsw0_qsgmii_phyinit" env variable has to be set for the U-BOOT to
configure this PHY.
+
+Debugging U-Boot
+----------------
+
+See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
+detailed setup information.
+
+.. warning::
+
+ **OpenOCD support since**: v0.12.0
+
+ If the default package version of OpenOCD in your development
+ environment's distribution needs to be updated, it might be necessary to
+ build OpenOCD from the source.
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_openocd_connect_XDS110
+ :end-before: .. k3_rst_include_end_openocd_connect_XDS110
+
+To start OpenOCD and connect to the board
+
+.. code-block:: bash
+
+ openocd -f board/ti_j721eevm.cfg
diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
index 9d40675..5f9bd4d 100644
--- a/doc/board/ti/k3.rst
+++ b/doc/board/ti/k3.rst
@@ -31,6 +31,8 @@
:maxdepth: 1
am62x_sk
+ ../toradex/verdin-am62
+ am64x_evm
am65x_evm
j7200_evm
j721e_evm
@@ -467,3 +469,517 @@
=> fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}
=> env import -t ${loadaddr} ${filesize}
+
+.. _k3_rst_refer_openocd:
+
+Common Debugging environment - OpenOCD
+--------------------------------------
+
+This section will show you how to connect a board to `OpenOCD
+<https://openocd.org/>`_ and load the SPL symbols for debugging with
+a K3 generation device. To follow this guide, you must build custom
+u-boot binaries, start your board from a boot media such as an SD
+card, and use an OpenOCD environment. This section uses generic
+examples, though you can apply these instructions to any supported K3
+generation device.
+
+The overall structure of this setup is in the following figure.
+
+.. image:: img/openocd-overview.svg
+
+.. note::
+
+ If you find these instructions useful, please consider `donating
+ <https://openocd.org/pages/donations.html>`_ to OpenOCD.
+
+Step 1: Download and install OpenOCD
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+To get started, it is more convenient if the distribution you
+use supports OpenOCD by default. Follow the instructions in the
+`getting OpenOCD <https://openocd.org/pages/getting-openocd.html>`_
+documentation to pick the installation steps appropriate to your
+environment. Some references to OpenOCD documentation:
+
+* `OpenOCD User Guide <https://openocd.org/doc/html/index.html>`_
+* `OpenOCD Developer's Guide <https://openocd.org/doc/doxygen/html/index.html>`_
+
+Refer to the release notes corresponding to the `OpenOCD version
+<https://github.com/openocd-org/openocd/releases>`_ to ensure
+
+* Processor support: In general, processor support shouldn't present
+ any difficulties since OpenOCD provides solid support for both ARMv8
+ and ARMv7.
+* SoC support: When working with System-on-a-Chip (SoC), the support
+ usually comes as a TCL config file. It is vital to ensure the correct
+ version of OpenOCD or to use the TCL files from the latest release or
+ the one mentioned.
+* Board or the JTAG adapter support: In most cases, board support is
+ a relatively easy problem if the board has a JTAG pin header. All
+ you need to do is ensure that the adapter you select is compatible
+ with OpenOCD. Some boards come with an onboard JTAG adapter that
+ requires a USB cable to be plugged into the board, in which case, it
+ is vital to ensure that the JTAG adapter is supported. Fortunately,
+ almost all TI K3 SK/EVMs come with TI's XDS110, which has out of the
+ box support by OpenOCD. The board-specific documentation will
+ cover the details and any adapter/dongle recommendations.
+
+.. code-block:: bash
+
+ openocd -v
+
+.. note::
+
+ OpenOCD version 0.12.0 is usually required to connect to most K3
+ devices. If your device is only supported by a newer version than the
+ one provided by your distribution, you may need to build it from the source.
+
+Building OpenOCD from source
+""""""""""""""""""""""""""""
+
+The dependency package installation instructions below are for Debian
+systems, but equivalent instructions should exist for systems with
+other package managers. Please refer to the `OpenOCD Documentation
+<https://openocd.org/>`_ for more recent installation steps.
+
+.. code-block:: bash
+
+ $ # Check the packages to be installed: needs deb-src in sources.list
+ $ sudo apt build-dep openocd
+ $ # The following list is NOT complete - please check the latest
+ $ sudo apt-get install libtool pkg-config texinfo libusb-dev \
+ libusb-1.0.0-dev libftdi-dev libhidapi-dev autoconf automake
+ $ git clone https://github.com/openocd-org/openocd.git openocd
+ $ cd openocd
+ $ git submodule init
+ $ git submodule update
+ $ ./bootstrap
+ $ ./configure --prefix=/usr/local/
+ $ make -j`nproc`
+ $ sudo make install
+
+.. note::
+
+ The example above uses the GitHub mirror site. See
+ `git repo information <https://openocd.org/doc/html/Developers.html#OpenOCD-Git-Repository>`_
+ information to pick the official git repo.
+ If a specific version is desired, select the version using `git checkout tag`.
+
+Installing OpenOCD udev rules
+"""""""""""""""""""""""""""""
+
+The step is not necessary if the distribution supports the OpenOCD, but
+if building from a source, ensure that the udev rules are installed
+correctly to ensure a sane system.
+
+.. code-block:: bash
+
+ # Go to the OpenOCD source directory
+ $ cd openocd
+ # Copy the udev rules to the correct system location
+ $ sudo cp ./contrib/60-openocd.rules \
+ ./src/JTAG/drivers/libjaylink/contrib/99-libjaylink.rules \
+ /etc/udev/rules.d/
+ # Get Udev to load the new rules up
+ $ sudo udevadm control --reload-rules
+ # Use the new rules on existing connected devices
+ $ sudo udevadm trigger
+
+Step 2: Setup GDB
+^^^^^^^^^^^^^^^^^
+
+Most systems come with gdb-multiarch package.
+
+.. code-block:: bash
+
+ # Install gdb-multiarch package
+ $ sudo apt-get install gdb-multiarch
+
+Though using GDB natively is normal, developers with interest in using IDE
+may find a few of these interesting:
+
+* `gdb-dashboard <https://github.com/cyrus-and/gdb-dashboard>`_
+* `gef <https://github.com/hugsy/gef>`_
+* `peda <https://github.com/longld/peda>`_
+* `pwndbg <https://github.com/pwndbg/pwndbg>`_
+* `voltron <https://github.com/snare/voltron>`_
+* `ddd <https://www.gnu.org/software/ddd/>`_
+* `vscode <https://www.justinmklam.com/posts/2017/10/vscode-debugger-setup/>`_
+* `vim conque-gdb <https://github.com/vim-scripts/Conque-GDB>`_
+* `emacs realgud <https://github.com/realgud/realgud/wiki/gdb-notes>`_
+* `Lauterbach IDE <https://www2.lauterbach.com/pdf/backend_gdb.pdf>`_
+
+.. warning::
+ LLDB support for OpenOCD is still a work in progress as of this writing.
+ Using GDB is probably the safest option at this point in time.
+
+Step 3: Connect board to PC
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+There are few patterns of boards in the ecosystem
+
+.. k3_rst_include_start_openocd_connect_XDS110
+
+**Integrated JTAG adapter/dongle**: The board has a micro-USB connector labelled
+XDS110 USB or JTAG. Connect a USB cable to the board to the mentioned port.
+
+.. note::
+
+ There are multiple USB ports on a typical board, So, ensure you have read
+ the user guide for the board and confirmed the silk screen label to ensure
+ connecting to the correct port.
+
+.. k3_rst_include_end_openocd_connect_XDS110
+
+.. k3_rst_include_start_openocd_connect_cti20
+
+**cTI20 connector**: The TI's `cTI20
+<https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_JTAG_connectors.html#cti-20-pin-header-information>`_ connector
+is probably the most prevelant on TI platforms. Though many
+TI boards have an onboard XDS110, cTI20 connector is usually
+provided as an alternate scheme to connect alternatives such
+as `Lauterbach <https://www.lauterbach.com/>`_ or `XDS560
+<https://www.ti.com/tool/TMDSEMU560V2STM-U>`_.
+
+To debug on these boards, the following combinations is suggested:
+
+* `TUMPA <https://www.diygadget.com/JTAG-cables-and-microcontroller-programmers/tiao-usb-multi-protocol-adapter-JTAG-spi-i2c-serial>`_
+ or `equivalent dongles supported by OpenOCD. <https://openocd.org/doc/html/Debug-Adapter-Hardware.html#Debug-Adapter-Hardware>`_
+* Cable such as `Tag-connect ribbon cable <https://www.tag-connect.com/product/20-pin-cortex-ribbon-cable-4-length-with-50-mil-connectors>`_
+* Adapter to convert cTI20 to ARM20 such as those from
+ `Segger <https://www.segger.com/products/debug-probes/j-link/accessories/adapters/ti-cti-20-adapter/>`_
+ or `Lauterbach LA-3780 <https://www.lauterbach.com/ad3780.html>`_
+ Or optionally, if you have manufacturing capability then you could try
+ `BeagleBone JTAG Adapter <https://github.com/mmorawiec/BeagleBone-Black-JTAG-Adapters>`_
+
+.. warning::
+ XDS560 and Lauterbach are proprietary solutions and is not supported by
+ OpenOCD.
+ When purchasing an off the shelf adapter/dongle, you do want to be careful
+ about the signalling though. Please
+ `read for additional info <https://software-dl.ti.com/ccs/esd/xdsdebugprobes/emu_JTAG_connectors.html>`_.
+
+.. k3_rst_include_end_openocd_connect_cti20
+
+.. k3_rst_include_start_openocd_connect_tag_connect
+
+**Tag-Connect**: `Tag-Connect <https://www.tag-connect.com/>`_
+pads on the boards which require special cable. Please check the documentation
+to `identify <https://www.tag-connect.com/info/legs-or-no-legs>`_ if "legged"
+or "no-leg" version of the cable is appropriate for the board.
+
+To debug on these boards, you will need:
+
+* `TUMPA <https://www.diygadget.com/JTAG-cables-and-microcontroller-programmers/tiao-usb-multi-protocol-adapter-JTAG-spi-i2c-serial>`_
+ or `equivalent dongles supported by OpenOCD <https://openocd.org/doc/html/Debug-Adapter-Hardware.html#Debug-Adapter-Hardware>`_.
+* Tag-Connect cable appropriate to the board such as
+ `TC2050-IDC-NL <https://www.tag-connect.com/product/TC2050-IDC-NL-10-pin-no-legs-cable-with-ribbon-connector>`_
+* In case of no-leg, version, a
+ `retaining clip <https://www.tag-connect.com/product/tc2050-clip-3pack-retaining-clip>`_
+* Tag-Connect to ARM20
+ `adapter <https://www.tag-connect.com/product/tc2050-arm2010-arm-20-pin-to-tc2050-adapter>`_
+
+.. note::
+ You can optionally use a 3d printed solution such as
+ `Protective cap <https://www.thingiverse.com/thing:3025584>`_ or
+ `clip <https://www.thingiverse.com/thing:3035278>`_ to replace
+ the retaining clip.
+
+.. warning::
+ With the Tag-Connect to ARM20 adapter, Please solder the "Trst" signal for
+ connection to work.
+
+.. k3_rst_include_end_openocd_connect_tag_connect
+
+Debugging with OpenOCD
+^^^^^^^^^^^^^^^^^^^^^^
+
+Debugging U-Boot is different from debugging regular user space
+applications. The bootloader initialization process involves many boot
+media and hardware configuration operations. For K3 devices, there
+are also interactions with security firmware. While reloading the
+"elf" file works through GDB, developers must be mindful of cascading
+initialization's potential consequences.
+
+Consider the following code change:
+
+.. code-block:: diff
+
+ --- a/file.c 2023-07-29 10:55:29.647928811 -0500
+ +++ b/file.c 2023-07-29 10:55:46.091856816 -0500
+ @@ -1,3 +1,3 @@
+ val = readl(reg);
+ -val |= 0x2;
+ +val |= 0x1;
+ writel(val, reg);
+
+Re-running the elf file with the above change will result in the
+register setting 0x3 instead of the intended 0x1. There are other
+hardware blocks which may not behave very well with a re-initialization
+without proper shutdown.
+
+To help narrow the debug down, it is usually simpler to use the
+standard boot media to get to the bootloader and debug only in the area
+of interest.
+
+In general, to debug u-boot spl/u-boot with OpenOCD there are three steps:
+
+* Modify the code adding a loop to allow the debugger to attach
+ near the point of interest. Boot up normally to stop at the loop.
+* Connect with OpenOCD and step out of the loop.
+* Step through the code to find the root of issue.
+
+Typical debugging involves a few iterations of the above sequence.
+Though most bootloader developers like to use printf to debug,
+debug with JTAG tends to be most efficient since it is possible to
+investigate the code flow and inspect hardware registers without
+repeated iterations.
+
+Code modification
+"""""""""""""""""
+
+* **start.S**: Adding an infinite while loop at the very entry of
+ U-Boot. For this, look for the corresponding start.S entry file.
+ This is usually only required when debugging some core SoC or
+ processor related function. For example: arch/arm/cpu/armv8/start.S or
+ arch/arm/cpu/armv7/start.S
+
+.. code-block:: diff
+
+ diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
+ index 69e281b086..744929e825 100644
+ --- a/arch/arm/cpu/armv7/start.S
+ +++ b/arch/arm/cpu/armv7/start.S
+ @@ -37,6 +37,8 @@
+ #endif
+
+ reset:
+ +dead_loop:
+ + b dead_loop
+ /* Allow the board to save important registers */
+ b save_boot_params
+ save_boot_params_ret:
+
+* **board_init_f**: Adding an infinite while loop at the board entry
+ function. In many cases, it is important to debug the boot process if
+ any changes are made for board-specific applications. Below is a step
+ by step process for debugging the boot SPL or Armv8 SPL:
+
+ To debug the boot process in either domain, we will first
+ add a modification to the code we would like to debug.
+ In this example, we will debug ``board_init_f`` inside
+ ``arch/arm/mach-k3/{soc}_init.c``. Since some sections of U-Boot
+ will be executed multiple times during the bootup process of K3
+ devices, we will need to include either ``CONFIG_CPU_ARM64`` or
+ ``CONFIG_CPU_V7R`` to catch the CPU at the desired place during the
+ bootup process (Main or Wakeup domains). For example, modify the
+ file as follows (depending on need):
+
+.. code-block:: c
+
+ void board_init_f(ulong dummy)
+ {
+ .
+ .
+ /* Code to run on the R5F (Wakeup/Boot Domain) */
+ if (IS_ENABLED(CONFIG_CPU_V7R)) {
+ volatile int x = 1;
+ while(x) {};
+ }
+ ...
+ /* Code to run on the ARMV8 (Main Domain) */
+ if (IS_ENABLED(CONFIG_CPU_ARM64)) {
+ volatile int x = 1;
+ while(x) {};
+ }
+ .
+ .
+ }
+
+Connecting with OpenOCD for a debug session
+"""""""""""""""""""""""""""""""""""""""""""
+
+Startup OpenOCD to debug the platform as follows:
+
+* **Integrated JTAG interface**: If the evm has a debugger such as
+ XDS110 inbuilt, there is typically an evm board support added and a
+ cfg file will be available.
+
+.. k3_rst_include_start_openocd_cfg_XDS110
+
+.. code-block:: bash
+
+ openocd -f board/{board_of_choice}.cfg
+
+.. k3_rst_include_end_openocd_cfg_XDS110
+
+.. k3_rst_include_start_openocd_cfg_external_intro
+
+* **External JTAG adapter/interface**: In other cases, where an
+ adapter/dongle is used, a simple cfg file can be created to integrate the
+ SoC and adapter information. See `supported TI K3 SoCs
+ <https://github.com/openocd-org/openocd/blob/master/tcl/target/ti_k3.cfg#L59>`_
+ to decide if the SoC is supported or not.
+
+.. code-block:: bash
+
+ openocd -f openocd_connect.cfg
+
+.. k3_rst_include_end_openocd_cfg_external_intro
+
+ For example, with BeaglePlay (AM62X platform), the openocd_connect.cfg:
+
+.. code-block:: tcl
+
+ # TUMPA example:
+ # http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User's_Manual
+ source [find interface/ftdi/tumpa.cfg]
+
+ transport select jtag
+
+ # default JTAG configuration has only SRST and no TRST
+ reset_config srst_only srst_push_pull
+
+ # delay after SRST goes inactive
+ adapter srst delay 20
+
+ if { ![info exists SOC] } {
+ # Set the SoC of interest
+ set SOC am625
+ }
+
+ source [find target/ti_k3.cfg]
+
+ ftdi tdo_sample_edge falling
+
+ # Speeds for FT2232H are in multiples of 2, and 32MHz is tops
+ # max speed we seem to achieve is ~20MHz.. so we pick 16MHz
+ adapter speed 16000
+
+Below is an example of the output of this command:
+
+.. code-block:: console
+
+ Info : Listening on port 6666 for tcl connections
+ Info : Listening on port 4444 for telnet connections
+ Info : XDS110: connected
+ Info : XDS110: vid/pid = 0451/bef3
+ Info : XDS110: firmware version = 3.0.0.20
+ Info : XDS110: hardware version = 0x002f
+ Info : XDS110: connected to target via JTAG
+ Info : XDS110: TCK set to 2500 kHz
+ Info : clock speed 2500 kHz
+ Info : JTAG tap: am625.cpu tap/device found: 0x0bb7e02f (mfg: 0x017 (Texas Instruments), part: 0xbb7e, ver: 0x0)
+ Info : starting gdb server for am625.cpu.sysctrl on 3333
+ Info : Listening on port 3333 for gdb connections
+ Info : starting gdb server for am625.cpu.a53.0 on 3334
+ Info : Listening on port 3334 for gdb connections
+ Info : starting gdb server for am625.cpu.a53.1 on 3335
+ Info : Listening on port 3335 for gdb connections
+ Info : starting gdb server for am625.cpu.a53.2 on 3336
+ Info : Listening on port 3336 for gdb connections
+ Info : starting gdb server for am625.cpu.a53.3 on 3337
+ Info : Listening on port 3337 for gdb connections
+ Info : starting gdb server for am625.cpu.main0_r5.0 on 3338
+ Info : Listening on port 3338 for gdb connections
+ Info : starting gdb server for am625.cpu.gp_mcu on 3339
+ Info : Listening on port 3339 for gdb connections
+
+.. note::
+ Notice the default configuration is non-SMP configuration allowing
+ for each of the core to be attached and debugged simultaneously.
+ ARMv8 SPL/U-Boot starts up on cpu0 of a53/a72.
+
+.. k3_rst_include_start_openocd_cfg_external_gdb
+
+To debug using this server, use GDB directly or your preferred
+GDB-based IDE. To start up GDB in the terminal, run the following
+command.
+
+.. code-block:: bash
+
+ gdb-multiarch
+
+To connect to your desired core, run the following command within GDB:
+
+.. code-block:: bash
+
+ target extended-remote localhost:{port for desired core}
+
+To load symbols:
+
+.. warning::
+
+ SPL and U-Boot does a re-location of address compared to where it
+ is loaded originally. This step takes place after the DDR size is
+ determined from dt parsing. So, debugging can be split into either
+ "before re-location" or "after re-location". Please refer to the
+ file ''doc/README.arm-relocation'' to see how to grab the relocation
+ address.
+
+* Prior to relocation:
+
+.. code-block:: bash
+
+ symbol-file {path to elf file}
+
+* After relocation:
+
+.. code-block:: bash
+
+ # Drop old symbol file
+ symbol-file
+ # Pick up new relocaddr
+ add-symbol-file {path to elf file} {relocaddr}
+
+.. k3_rst_include_end_openocd_cfg_external_gdb
+
+In the above example of AM625,
+
+.. code-block:: bash
+
+ target extended-remote localhost:3338 <- R5F (Wakeup Domain)
+ target extended-remote localhost:3334 <- A53 (Main Domain)
+
+The core can now be debugged directly within GDB using GDB commands or
+if using IDE, as appropriate to the IDE.
+
+Stepping through the code
+"""""""""""""""""""""""""
+
+`GDB TUI Commands
+<https://sourceware.org/gdb/onlinedocs/gdb/TUI-Commands.html>`_ can
+help set up the display more sensible for debug. Provide the name
+of the layout that can be used to debug. For example, use the GDB
+command ``layout src`` after loading the symbols to see the code and
+breakpoints. To exit the debug loop added above, add any breakpoints
+needed and run the following GDB commands to step out of the debug
+loop set in the ``board_init_f`` function.
+
+.. code-block:: bash
+
+ set x = 0
+ continue
+
+The platform has now been successfully setup to debug with OpenOCD
+using GDB commands or a GDB-based IDE. See `OpenOCD documentation for
+GDB <https://openocd.org/doc/html/GDB-and-OpenOCD.html>`_ for further
+information.
+
+.. warning::
+
+ On the K3 family of devices, a watchdog timer within the DMSC is
+ enabled by default by the ROM bootcode with a timeout of 3 minutes.
+ The watchdog timer is serviced by System Firmware (SYSFW) or TI
+ Foundational Security (TIFS) during normal operation. If debugging
+ the SPL before the SYSFW is loaded, the watchdog timer will not get
+ serviced automatically and the debug session will reset after 3
+ minutes. It is recommended to start debugging SPL code only after
+ the startup of SYSFW to avoid running into the watchdog timer reset.
+
+Miscellaneous notes with OpenOCD
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Currently, OpenOCD does not support tracing for K3 platforms. Tracing
+function could be beneficial if the bug in code occurs deep within
+nested function and can optionally save developers major trouble of
+stepping through a large quantity of code.
diff --git a/doc/board/toradex/index.rst b/doc/board/toradex/index.rst
index ead5efb..89fbdcb 100644
--- a/doc/board/toradex/index.rst
+++ b/doc/board/toradex/index.rst
@@ -9,5 +9,6 @@
apalis-imx8
colibri_imx7
colibri-imx8x
+ verdin-am62
verdin-imx8mm
verdin-imx8mp
diff --git a/doc/board/toradex/verdin-am62.rst b/doc/board/toradex/verdin-am62.rst
new file mode 100644
index 0000000..36db149
--- /dev/null
+++ b/doc/board/toradex/verdin-am62.rst
@@ -0,0 +1,133 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+.. sectionauthor:: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+
+Verdin AM62 Module
+==================
+
+- SoM: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
+- Carrier board: https://www.toradex.com/products/carrier-board/verdin-development-board-kit
+
+Quick Start
+-----------
+
+- Get the binary-only SYSFW
+- Get binary-only TI Linux firmware
+- Build the ARM trusted firmware binary
+- Build the OPTEE binary
+- Build U-Boot for the R5
+- Build U-Boot for the A53
+- Flash to eMMC
+- Boot
+
+For an overview of the TI AM62 SoC boot flow please head over to:
+:doc:`../ti/am62x_sk`
+
+Sources:
+--------
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_boot_sources
+ :end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure:
+----------------
+0. Setup the environment variables:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_desc
+ :end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_board_env_vars_desc
+ :end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_defn
+ :end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=verdin-am62_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=verdin-am62_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ # we dont use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-am62x
+ $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+
+.. include:: ../ti/am62x_sk.rst
+ :start-after: .. am62x_evm_rst_include_start_build_steps
+ :end-before: .. am62x_evm_rst_include_end_build_steps
+
+Flash to eMMC
+-------------
+
+.. code-block:: bash
+
+ => mmc dev 0 1
+ => fatload mmc 1 ${loadaddr} tiboot3.bin
+ => mmc write ${loadaddr} 0x0 0x400
+ => fatload mmc 1 ${loadaddr} tispl.bin
+ => mmc write ${loadaddr} 0x400 0x1000
+ => fatload mmc 1 ${loadaddr} u-boot.img
+ => mmc write ${loadaddr} 0x1400 0x2000
+
+Boot
+----
+
+Output:
+
+.. code-block:: none
+
+ U-Boot SPL 2023.10-rc1-00210-gb678170a34c (Aug 03 2023 - 00:09:14 +0200)
+ SYSFW ABI: 3.1 (firmware rev 0x0009 '9.0.1--v09.00.01 (Kool Koala)')
+ SPL initial stack usage: 13368 bytes
+ Trying to boot from MMC1
+ Authentication passed
+ Authentication passed
+ Authentication passed
+ Authentication passed
+ Authentication passed
+ Starting ATF on ARM64 core...
+
+ NOTICE: BL31: v2.9(release):v2.9.0-73-g463655cc8
+ NOTICE: BL31: Built : 14:51:42, Jun 5 2023
+ I/TC:
+ I/TC: OP-TEE version: 3.21.0-168-g322cf9e33 (gcc version 12.2.1 20221205 (Arm GNU Toolchain 12.2.Rel1 (Build arm-12.24))) #2 Mon Jun 5 13:04:15 UTC 2023 aarch64
+ I/TC: WARNING: This OP-TEE configuration might be insecure!
+ I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
+ I/TC: Primary CPU initializing
+ I/TC: SYSFW ABI: 3.1 (firmware rev 0x0009 '9.0.1--v09.00.01 (Kool Koala)')
+ I/TC: HUK Initialized
+ I/TC: Primary CPU switching to normal world boot
+
+ U-Boot SPL 2023.10-rc1-00210-gb678170a34c (Aug 03 2023 - 00:09:41 +0200)
+ SYSFW ABI: 3.1 (firmware rev 0x0009 '9.0.1--v09.00.01 (Kool Koala)')
+ SPL initial stack usage: 1840 bytes
+ Trying to boot from MMC1
+ Authentication passed
+ Authentication passed
+
+
+ U-Boot 2023.10-rc1-00210-gb678170a34c (Aug 03 2023 - 00:09:41 +0200)
+
+ SoC: AM62X SR1.0 HS-FS
+ DRAM: 2 GiB
+ Core: 136 devices, 28 uclasses, devicetree: separate
+ MMC: mmc@fa10000: 0, mmc@fa00000: 1
+ Loading Environment from MMC... OK
+ In: serial@2800000
+ Out: serial@2800000
+ Err: serial@2800000
+ Model: Toradex 0076 Verdin AM62 Quad 2GB WB IT V1.0A
+ Serial#: 15037380
+ Carrier: Toradex Verdin Development Board V1.1A, Serial# 10754333
+ am65_cpsw_nuss ethernet@8000000: K3 CPSW: nuss_ver: 0x6BA01103 cpsw_ver: 0x6BA81103 ale_ver: 0x00290105 Ports:2 mdio_freq:1000000
+ Setting variant to wifi
+ Net:
+ Warning: ethernet@8000000port@1 MAC addresses don't match:
+ Address in ROM is 1c:63:49:22:5f:f9
+ Address in environment is 00:14:2d:e5:73:c4
+ eth0: ethernet@8000000port@1 [PRIME], eth1: ethernet@8000000port@2
+ Hit any key to stop autoboot: 0
+ Verdin AM62 #
diff --git a/doc/board/toradex/verdin-imx8mm.rst b/doc/board/toradex/verdin-imx8mm.rst
index 439128a..cc39030 100644
--- a/doc/board/toradex/verdin-imx8mm.rst
+++ b/doc/board/toradex/verdin-imx8mm.rst
@@ -1,8 +1,12 @@
-.. SPDX-License-Identifier: GPL-2.0+
+.. SPDX-License-Identifier: GPL-2.0-or-later
+.. sectionauthor:: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Verdin iMX8M Mini Module
========================
+- SoM: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini-nano
+- Carrier board: https://www.toradex.com/products/carrier-board/verdin-development-board-kit
+
Quick Start
-----------
@@ -25,6 +29,7 @@
.. code-block:: bash
+ $ export CROSS_COMPILE=aarch64-linux-gnu-
$ make PLAT=imx8mm IMX_BOOT_UART_BASE=0x30860000 bl31
$ cp build/imx8mm/release/bl31.bin ../
@@ -75,30 +80,30 @@
Output:
-.. code-block:: bash
+.. code-block:: none
-U-Boot SPL 2021.10-rc2-00028-gee010ba1129 (Aug 23 2021 - 16:56:02 +0200)
-Normal Boot
-WDT: Started with servicing (60s timeout)
-Trying to boot from MMC1
-NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.2_rc1-5-g835a8f67b
-NOTICE: BL31: Built : 18:02:12, Aug 16 2021
+ U-Boot SPL 2021.10-rc2-00028-gee010ba1129 (Aug 23 2021 - 16:56:02 +0200)
+ Normal Boot
+ WDT: Started with servicing (60s timeout)
+ Trying to boot from MMC1
+ NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.2_rc1-5-g835a8f67b
+ NOTICE: BL31: Built : 18:02:12, Aug 16 2021
-U-Boot 2021.10-rc2-00028-gee010ba1129 (Aug 23 2021 - 16:56:02 +0200)
+ U-Boot 2021.10-rc2-00028-gee010ba1129 (Aug 23 2021 - 16:56:02 +0200)
-CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
-Reset cause: POR
-DRAM: 2 GiB
-WDT: Started with servicing (60s timeout)
-MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
-Loading Environment from MMC... OK
-In: serial
-Out: serial
-Err: serial
-Model: Toradex Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT V1.1A, Serial# 06760554
-Carrier: Toradex Verdin Development Board V1.1A, Serial# 10754333
-Setting variant to wifi
-Net: eth0: ethernet@30be0000
-Hit any key to stop autoboot: 0
-Verdin iMX8MM #
+ CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
+ Reset cause: POR
+ DRAM: 2 GiB
+ WDT: Started with servicing (60s timeout)
+ MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
+ Loading Environment from MMC... OK
+ In: serial
+ Out: serial
+ Err: serial
+ Model: Toradex Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT V1.1A, Serial# 06760554
+ Carrier: Toradex Verdin Development Board V1.1A, Serial# 10754333
+ Setting variant to wifi
+ Net: eth0: ethernet@30be0000
+ Hit any key to stop autoboot: 0
+ Verdin iMX8MM #
diff --git a/doc/board/toradex/verdin-imx8mp.rst b/doc/board/toradex/verdin-imx8mp.rst
index 482f693..bdc4d0c 100644
--- a/doc/board/toradex/verdin-imx8mp.rst
+++ b/doc/board/toradex/verdin-imx8mp.rst
@@ -1,8 +1,12 @@
.. SPDX-License-Identifier: GPL-2.0-or-later
+.. sectionauthor:: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Verdin iMX8M Plus Module
========================
+- SoM: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus
+- Carrier board: https://www.toradex.com/products/carrier-board/verdin-development-board-kit
+
Quick Start
-----------
@@ -76,36 +80,36 @@
Output:
-.. code-block:: bash
+.. code-block:: none
-U-Boot SPL 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)
-Quad die, dual rank failed, attempting dual die, single rank configuration.
-Normal Boot
-WDT: Started watchdog@30280000 with servicing (60s timeout)
-Trying to boot from BOOTROM
-Find img info 0x&48025a00, size 872
-Need continue download 1024
-Download 779264, Total size 780424
-NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.2_rc1-5-g835a8f67b
-NOTICE: BL31: Built : 16:52:37, Aug 26 2021
+ U-Boot SPL 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)
+ Quad die, dual rank failed, attempting dual die, single rank configuration.
+ Normal Boot
+ WDT: Started watchdog@30280000 with servicing (60s timeout)
+ Trying to boot from BOOTROM
+ Find img info 0x&48025a00, size 872
+ Need continue download 1024
+ Download 779264, Total size 780424
+ NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.2_rc1-5-g835a8f67b
+ NOTICE: BL31: Built : 16:52:37, Aug 26 2021
-U-Boot 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)
+ U-Boot 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)
-CPU: Freescale i.MX8MP[8] rev1.1 at 1200 MHz
-Reset cause: POR
-DRAM: 8 GiB
-Core: 78 devices, 18 uclasses, devicetree: separate
-WDT: Started watchdog@30280000 with servicing (60s timeout)
-MMC: FSL_SDHC: 1, FSL_SDHC: 2
-Loading Environment from MMC... OK
-In: serial
-Out: serial
-Err: serial
-Model: Toradex Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT V1.0B, Serial# 06817281
-Carrier: Toradex Verdin Development Board V1.1A, Serial# 10807609
-Setting variant to wifi
-Net: Hard-coding pdata->enetaddr
-eth1: ethernet@30be0000, eth0: ethernet@30bf0000 [PRIME]
-Hit any key to stop autoboot: 0
-Verdin iMX8MP #
+ CPU: Freescale i.MX8MP[8] rev1.1 at 1200 MHz
+ Reset cause: POR
+ DRAM: 8 GiB
+ Core: 78 devices, 18 uclasses, devicetree: separate
+ WDT: Started watchdog@30280000 with servicing (60s timeout)
+ MMC: FSL_SDHC: 1, FSL_SDHC: 2
+ Loading Environment from MMC... OK
+ In: serial
+ Out: serial
+ Err: serial
+ Model: Toradex Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT V1.0B, Serial# 06817281
+ Carrier: Toradex Verdin Development Board V1.1A, Serial# 10807609
+ Setting variant to wifi
+ Net: Hard-coding pdata->enetaddr
+ eth1: ethernet@30be0000, eth0: ethernet@30bf0000 [PRIME]
+ Hit any key to stop autoboot: 0
+ Verdin iMX8MP #
diff --git a/doc/develop/board_best_practices.rst b/doc/develop/board_best_practices.rst
new file mode 100644
index 0000000..f44401e
--- /dev/null
+++ b/doc/develop/board_best_practices.rst
@@ -0,0 +1,26 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+Best Practices for Board Ports
+==============================
+
+In addition to the regular best practices such as using :doc:`checkpatch` and
+following the :doc:`docstyle` and the :doc:`codingstyle` there are some things
+which are specific to creating a new board port.
+
+* Implement :doc:`bootstd` to ensure that most operating systems will be
+ supported by the platform.
+
+* The platform defconfig file must be generated via `make savedefconfig`.
+
+* The Kconfig and Kbuild infrastructure supports using "fragments" that can be
+ used to apply changes on top of a defconfig file. These can be useful for
+ many things such as:
+
+ * Supporting different firmware locations (e.g. eMMC, SD, QSPI).
+
+ * Multiple board variants when runtime detection is not desired.
+
+ * Supporting different build types such as production and development.
+
+ Kconfig fragments should reside in the board directory itself rather than in
+ the top-level `configs/` directory.
diff --git a/doc/develop/bootstd.rst b/doc/develop/bootstd.rst
index 7a2a69f..c01e097 100644
--- a/doc/develop/bootstd.rst
+++ b/doc/develop/bootstd.rst
@@ -306,7 +306,7 @@
The bootdev device is typically created automatically in the media uclass'
`post_bind()` method by calling `bootdev_setup_for_dev()` or
-`bootdev_setup_sibling_blk()`. The code typically something like this::
+`bootdev_setup_for_sibling_blk()`. The code typically something like this::
/* dev is the Ethernet device */
ret = bootdev_setup_for_dev(dev, "eth_bootdev");
@@ -316,7 +316,7 @@
or::
/* blk is the block device (child of MMC device)
- ret = bootdev_setup_sibling_blk(blk, "mmc_bootdev");
+ ret = bootdev_setup_for_sibling_blk(blk, "mmc_bootdev");
if (ret)
return log_msg_ret("bootdev", ret);
@@ -677,11 +677,12 @@
partition. If that works it tries to detect a file system. If that works then it
calls the bootmeth device once more, this time to read the bootflow.
-Note: At present a filesystem is needed for the bootmeth to be called on block
-devices, simply because we don't have any examples where this is not the case.
-This feature can be added as needed. Note that sandbox is a special case, since
-in that case the host filesystem can be accessed even though the block device
-is NULL.
+Note: Normally a filesystem is needed for the bootmeth to be called on block
+devices, but bootmeths which don't need that can set the BOOTMETHF_ANY_PART
+flag to indicate that they can scan any partition. An example is the ChromiumOS
+bootmeth which can store a kernel in a raw partition. Note also that sandbox is
+a special case, since in that case the host filesystem can be accessed even
+though the block device is NULL.
If we take the example of the `bootmeth_extlinux` driver, this call ends up at
`extlinux_read_bootflow()`. It has the filesystem ready, so tries various
diff --git a/doc/develop/cedit.rst b/doc/develop/cedit.rst
new file mode 100644
index 0000000..63dff9d
--- /dev/null
+++ b/doc/develop/cedit.rst
@@ -0,0 +1,169 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Configuration Editor
+====================
+
+Introduction
+------------
+
+U-Boot provides a configuration editor which allows settings to be changed in
+a GUI or text environment.
+
+
+This feature is still in development and has a number of limitations. For
+example, cedit only supports menu items (there is no numeric or text entry),
+provides no support for colour text and does not support scrolling. Still it is
+possible to use it for simple applications.
+
+
+Overview
+--------
+
+The configuration editor makes use of :doc:`expo` to build a description of the
+configuration screens and allow user to interact with it.
+
+To create a single-scene cedit for your application:
+
+#. Design the scene, i.e. the objects that need to be present and what their
+ possible values are
+
+#. Enter this in .dts format
+
+#. Create a header file containing the IDs
+
+#. Run the 'expo.py' tool to generate a .dtb file containing the layout, which
+ can be used by U-Boot
+
+#. Use the :doc:`../usage/cmd/cedit` to create the cedit, read the settings,
+ present the cedit to the user and save the settings afterwards.
+
+Each of these is described in a separate section. See :ref:`expo_example` for
+an example file.
+
+
+Design a scene
+--------------
+
+Using a piece of paper or a drawing tool, lay out the objects you want in your
+scene. Typically you will use the default layout engine, which simply puts items
+one after the other from top to bottom. So use a single column and show the
+prompt and value for each object.
+
+For menu items, show one of the values, but keep in mind what else you need.
+
+
+Create an expo-format file
+--------------------------
+
+The description is in the form of a devicetree file, as documented at
+:ref:`expo_format`. Since everything in an expo has an ID number (an integer
+greater than 1) the description is written terms of these IDs. They each have
+an enum value. which is typically taken care of by the `expo.py` tool.
+
+The expo should have a `scenes` node with a named scene as a subnode. Within the
+scene, add properties for the scene, then a subnode for each object in the
+scene.
+
+All object nodes require an `id` value and a `type` property. Other properties
+depend on the type. For example, a menu has a `title` and an `item-label` list
+proving the text for the menu items, as well as an `item-id` list providing the
+ID of each menu item, so it can be selected.
+
+Text properties may have two variants. For example `title` specifies the title
+of a menu, but you can instead use `title-id` to specify the string ID to use as
+the title. String are defined in a separate area, common to the whole expo,
+which contains a subnode for each string. Within that subnode are the ID and the
+`value` (i.e. the text). For now only English is supported, but in future it may
+be possible to append a language identifier to provide other values (e.g.
+'value-es' for Spanish).
+
+
+Create an ID header-file
+------------------------
+
+Expo needs to know the integer value to use for every ID referenced in your
+expo-format file. For example, if you have defined a `cpu-speed` node with an
+id of `ID_CPU_SPEED`, then Expo needs to know the value of `ID_CPU_SPEED`.
+
+When you write C code to use the expo, you may need to know the IDs. For
+example, to find which value the user selected in `cpu-speed` menu, you must
+use the `ID_CPU_SPEED` ID. The ID is the only way to refer to anything in Expo.
+
+Since we need a shared set of IDs, it is best to have a header file containing
+them. Expo supports doing this with an enum, where every ID is listed in the
+enum::
+
+ enum {
+ ZERO,
+
+ ID_PROMPT,
+
+ ID_SCENE1,
+ ID_SCENE1_TITLE,
+ ...
+ };
+
+The C compiler can parse this directly. The `expo.py` tool parses it for expo.
+
+Create a header file containing every ID mentioned in your expo. Try to group
+related things together.
+
+
+Build the expo layout
+---------------------
+
+Use the `expo.py` tool to build a .dtb for your expo::
+
+ ./tools/expo.py -e expo_ids.h -l expo_layout.dts -o expo.dtb
+
+This uses the enum in the provided header file to get the ID numbers, grabs
+the `.dts` file, inserts the ID numbers and then uses the devicetree compiler to
+build a `.dtb` file.
+
+If you get an error::
+
+ Devicetree compiler error:
+ Error: <stdin>:9.19-20 syntax error
+ FATAL ERROR: Unable to parse input tree
+
+that means that something is wrong with your syntax, or perhaps you have an ID
+in the `.dts` file that is not mentioned in your enum. Check both files and try
+again.
+
+
+Use the command interface
+-------------------------
+
+See the :doc:`../usage/cmd/cedit` command for information on available commands.
+Typically you will use `cedit load` to load the `.dtb` file and `cedit run` to
+let the user interact with it.
+
+
+Multiple scenes
+---------------
+
+Expo supports multiple scenes but has no pre-determined way of moving between
+them. You could use selection of a menu item as a signal to change the scene,
+but this is not currently implemented in the cedit code (see `cedit_run()`).
+
+
+Themes
+------
+
+The configuration editor uses simple expo themes. The theme is read from
+`/bootstd/cedit-theme` in the devicetree.
+
+
+Reading and writing settings
+----------------------------
+
+Cedit provides several options for persistent settings:
+
+- Writing an FDT file to a filesystem
+- Writing to U-Boot's environment variables, which are then typically stored in
+ a persistent manner
+- Writing to CMOS RAM registers (common on x86 machines)
+
+For now, reading and writing settings is not automatic. See the
+:doc:`../usage/cmd/cedit` for how to do this on the command line or in a
+script.
diff --git a/doc/develop/expo.rst b/doc/develop/expo.rst
index 2ac4af2..f137619 100644
--- a/doc/develop/expo.rst
+++ b/doc/develop/expo.rst
@@ -317,6 +317,18 @@
Specifies the ID of the object. This is used when referring to the object.
+Where CMOS RAM is used for reading and writing settings, the following
+additional properties are required:
+
+start-bit
+ Specifies the first bit in the CMOS RAM to use for this setting. For a RAM
+ with 0x100 bytes, there are 0x800 bit locations. For example, register 0x80
+ holds bits 0x400 to 0x407.
+
+bit-length
+ Specifies the number of CMOS RAM bits to use for this setting. The bits
+ extend from `start-bit` to `start-bit + bit-length - 1`. Note that the bits
+ must be contiguous.
Menu nodes have the following additional properties:
@@ -358,6 +370,9 @@
suitable manner. For each scene it puts the title at the top, the prompt at the
bottom and the objects in order from top to bottom.
+
+.. _expo_example:
+
Expo format example
~~~~~~~~~~~~~~~~~~~
@@ -367,22 +382,27 @@
::
- #define ID_PROMPT 1
- #define ID_SCENE1 2
- #define ID_SCENE1_TITLE 3
+ /* this comment is parsed by the expo.py tool to insert the values below
- #define ID_CPU_SPEED 4
- #define ID_CPU_SPEED_TITLE 5
- #define ID_CPU_SPEED_1 6
- #define ID_CPU_SPEED_2 7
- #define ID_CPU_SPEED_3 8
+ enum {
+ ZERO,
+ ID_PROMPT,
+ ID_SCENE1,
+ ID_SCENE1_TITLE,
- #define ID_POWER_LOSS 9
- #define ID_AC_OFF 10
- #define ID_AC_ON 11
- #define ID_AC_MEMORY 12
+ ID_CPU_SPEED,
+ ID_CPU_SPEED_TITLE,
+ ID_CPU_SPEED_1,
+ ID_CPU_SPEED_2,
+ ID_CPU_SPEED_3,
- #define ID_DYNAMIC_START 13
+ ID_POWER_LOSS,
+ ID_AC_OFF,
+ ID_AC_ON,
+ ID_AC_MEMORY,
+
+ ID_DYNAMIC_START,
+ */
&cedit {
dynamic-start = <ID_DYNAMIC_START>;
@@ -465,7 +485,7 @@
- Support unicode
- Support curses for proper serial-terminal menus
- Add support for large menus which need to scroll
-- Add support for reading and writing configuration settings with cedit
+- Update expo.py tool to check for overlapping names and CMOS locations
.. Simon Glass <sjg@chromium.org>
.. 7-Oct-22
diff --git a/doc/develop/falcon.rst b/doc/develop/falcon.rst
new file mode 100644
index 0000000..a569d1a
--- /dev/null
+++ b/doc/develop/falcon.rst
@@ -0,0 +1,258 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+Falcon Mode
+===========
+
+Introduction
+------------
+
+This document provides an overview of how to add support for Falcon Mode
+to a board.
+
+Falcon Mode is introduced to speed up the booting process, allowing
+to boot a Linux kernel (or whatever image) without a full blown U-Boot.
+
+Falcon Mode relies on the SPL framework. In fact, to make booting faster,
+U-Boot is split into two parts: the SPL (Secondary Program Loader) and U-Boot
+image. In most implementations, SPL is used to start U-Boot when booting from
+a mass storage, such as NAND or SD-Card. SPL has now support for other media,
+and can generally be seen as a way to start an image performing the minimum
+required initialization. SPL mainly initializes the RAM controller, and then
+copies U-Boot image into the memory.
+
+The Falcon Mode extends this way allowing to start the Linux kernel directly
+from SPL. A new command is added to U-Boot to prepare the parameters that SPL
+must pass to the kernel, using ATAGS or Device Tree.
+
+In normal mode, these parameters are generated each time before
+loading the kernel, passing to Linux the address in memory where
+the parameters can be read.
+With Falcon Mode, this snapshot can be saved into persistent storage and SPL is
+informed to load it before running the kernel.
+
+To boot the kernel, these steps under a Falcon-aware U-Boot are required:
+
+1. Boot the board into U-Boot.
+ After loading the desired legacy-format kernel image into memory (and DT as
+ well, if used), use the "spl export" command to generate the kernel
+ parameters area or the DT. U-Boot runs as when it boots the kernel, but
+ stops before passing the control to the kernel.
+
+2. Save the prepared snapshot into persistent media.
+ The address where to save it must be configured into board configuration
+ file (CONFIG_CMD_SPL_NAND_OFS for NAND).
+
+3. Boot the board into Falcon Mode. SPL will load the kernel and copy
+ the parameters which are saved in the persistent area to the required
+ address. If a valid uImage is not found at the defined location, U-Boot
+ will be booted instead.
+
+It is required to implement a custom mechanism to select if SPL loads U-Boot
+or another image.
+
+The value of a GPIO is a simple way to operate the selection, as well as
+reading a character from the SPL console if CONFIG_SPL_CONSOLE is set.
+
+Falcon Mode is generally activated by setting CONFIG_SPL_OS_BOOT. This tells
+SPL that U-Boot is not the only available image that SPL is able to start.
+
+Configuration
+-------------
+
+CONFIG_CMD_SPL
+ Enable the "spl export" command.
+ The command "spl export" is then available in U-Boot mode.
+
+CONFIG_SYS_SPL_ARGS_ADDR
+ Address in RAM where the parameters must be copied by SPL.
+ In most cases, it is <start_of_ram> + 0x100.
+
+CONFIG_SYS_NAND_SPL_KERNEL_OFFS
+ Offset in NAND where the kernel is stored
+
+CONFIG_CMD_SPL_NAND_OFS
+ Offset in NAND where the parameters area was saved.
+
+CONFIG_CMD_SPL_NOR_OFS
+ Offset in NOR where the parameters area was saved.
+
+CONFIG_CMD_SPL_WRITE_SIZE
+ Size of the parameters area to be copied
+
+CONFIG_SPL_OS_BOOT
+ Activate Falcon Mode.
+
+Function that a board must implement
+------------------------------------
+
+void spl_board_prepare_for_linux(void)
+ optional, called from SPL before starting the kernel
+
+spl_start_uboot()
+ required, returns "0" if SPL should start the kernel, "1" if U-Boot
+ must be started.
+
+Environment variables
+---------------------
+
+A board may chose to look at the environment for decisions about falcon
+mode. In this case the following variables may be supported:
+
+boot_os
+ Set to yes/Yes/true/True/1 to enable booting to OS,
+ any other value to fall back to U-Boot (including unset)
+
+falcon_args_file
+ Filename to load as the 'args' portion of falcon mode rather than the
+ hard-coded value.
+
+falcon_image_file
+ Filename to load as the OS image portion of falcon mode rather than the
+ hard-coded value.
+
+Using spl command
+-----------------
+
+spl - SPL configuration
+
+Usage::
+
+ spl export <img=atags|fdt> [kernel_addr] [initrd_addr] [fdt_addr ]
+
+img
+ "atags" or "fdt"
+
+kernel_addr
+ kernel is loaded as part of the boot process, but it is not started.
+ This is the address where a kernel image is stored.
+
+initrd_addr
+ Address of initial ramdisk
+ can be set to "-" if fdt_addr without initrd_addr is used
+
+fdt_addr
+ in case of fdt, the address of the device tree.
+
+The *spl export* command does not write to a storage media. The user is
+responsible to transfer the gathered information (assembled ATAGS list
+or prepared FDT) from temporary storage in RAM into persistent storage
+after each run of *spl export*. Unfortunately the position of temporary
+storage can not be predicted nor provided at command line, it depends
+highly on your system setup and your provided data (ATAGS or FDT).
+However at the end of an successful *spl export* run it will print the
+RAM address of temporary storage. The RAM address of FDT will also be
+set in the environment variable *fdtargsaddr*, the new length of the
+prepared FDT will be set in the environment variable *fdtargslen*.
+These environment variables can be used in scripts for writing updated
+FDT to persistent storage.
+
+Now the user have to save the generated BLOB from that printed address
+to the pre-defined address in persistent storage
+(CONFIG_CMD_SPL_NAND_OFS in case of NAND).
+The following example shows how to prepare the data for Falcon Mode on
+twister board with ATAGS BLOB.
+
+The *spl export* command is prepared to work with ATAGS and FDT. However,
+using FDT is at the moment untested. The ppc port (see a3m071 example
+later) prepares the fdt blob with the fdt command instead.
+
+
+Usage on the twister board
+--------------------------
+
+Using mtd names with the following (default) configuration
+for mtdparts::
+
+ device nand0 <omap2-nand.0>, # parts = 9
+ #: name size offset mask_flags
+ 0: MLO 0x00080000 0x00000000 0
+ 1: u-boot 0x00100000 0x00080000 0
+ 2: env1 0x00040000 0x00180000 0
+ 3: env2 0x00040000 0x001c0000 0
+ 4: kernel 0x00600000 0x00200000 0
+ 5: bootparms 0x00040000 0x00800000 0
+ 6: splashimg 0x00200000 0x00840000 0
+ 7: mini 0x02800000 0x00a40000 0
+ 8: rootfs 0x1cdc0000 0x03240000 0
+
+::
+
+ twister => nand read 82000000 kernel
+
+ NAND read: device 0 offset 0x200000, size 0x600000
+ 6291456 bytes read: OK
+
+Now the kernel is in RAM at address 0x82000000::
+
+ twister => spl export atags 0x82000000
+ ## Booting kernel from Legacy Image at 82000000 ...
+ Image Name: Linux-3.5.0-rc4-14089-gda0b7f4
+ Image Type: ARM Linux Kernel Image (uncompressed)
+ Data Size: 3654808 Bytes = 3.5 MiB
+ Load Address: 80008000
+ Entry Point: 80008000
+ Verifying Checksum ... OK
+ Loading Kernel Image ... OK
+ OK
+ cmdline subcommand not supported
+ bdt subcommand not supported
+ Argument image is now in RAM at: 0x80000100
+
+The result can be checked at address 0x80000100::
+
+ twister => md 0x80000100
+ 80000100: 00000005 54410001 00000000 00000000 ......AT........
+ 80000110: 00000000 00000067 54410009 746f6f72 ....g.....ATroot
+ 80000120: 65642f3d 666e2f76 77722073 73666e20 =/dev/nfs rw nfs
+
+The parameters generated with this step can be saved into NAND at the offset
+0x800000 (value for twister for CONFIG_CMD_SPL_NAND_OFS)::
+
+ nand erase.part bootparms
+ nand write 0x80000100 bootparms 0x4000
+
+Now the parameters are stored into the NAND flash at the address
+CONFIG_CMD_SPL_NAND_OFS (=0x800000).
+
+Next time, the board can be started into Falcon Mode moving the
+setting the GPIO (on twister GPIO 55 is used) to kernel mode.
+
+The kernel is loaded directly by the SPL without passing through U-Boot.
+
+Example with FDT: a3m071 board
+-------------------------------
+
+To boot the Linux kernel from the SPL, the DT blob (fdt) needs to get
+prepared/patched first. U-Boot usually inserts some dynamic values into
+the DT binary (blob), e.g. autodetected memory size, MAC addresses,
+clocks speeds etc. To generate this patched DT blob, you can use
+the following command:
+
+1. Load fdt blob to SDRAM::
+
+ => tftp 1800000 a3m071/a3m071.dtb
+
+2. Set bootargs as desired for Linux booting (e.g. flash_mtd)::
+
+ => run mtdargs addip2 addtty
+
+3. Use "fdt" commands to patch the DT blob::
+
+ => fdt addr 1800000
+ => fdt boardsetup
+ => fdt chosen
+
+4. Display patched DT blob (optional)::
+
+ => fdt print
+
+5. Save fdt to NOR flash::
+
+ => erase fc060000 fc07ffff
+ => cp.b 1800000 fc060000 10000
+ ...
+
+
+Falcon Mode was presented at the RMLL 2012. Slides are available at:
+
+http://schedule2012.rmll.info/IMG/pdf/LSM2012_UbootFalconMode_Babic.pdf
diff --git a/doc/develop/index.rst b/doc/develop/index.rst
index ddbf8da..0d12484 100644
--- a/doc/develop/index.rst
+++ b/doc/develop/index.rst
@@ -9,6 +9,7 @@
.. toctree::
:maxdepth: 1
+ board_best_practices
codingstyle
designprinciples
docstyle
@@ -37,6 +38,7 @@
driver-model/index
environment
expo
+ cedit
event
global_data
logging
@@ -45,6 +47,7 @@
printf
smbios
spl
+ falcon
uefi/index
vbe
version
diff --git a/doc/develop/printf.rst b/doc/develop/printf.rst
index 7b9aea0..99d0506 100644
--- a/doc/develop/printf.rst
+++ b/doc/develop/printf.rst
@@ -105,19 +105,19 @@
=================== ==================
Type Format specifier
=================== ==================
-bool %d, %x
+bool %d, %x
char %d, %x
unsigned char %u, %x
short %d, %x
unsigned short %u, %x
int %d, %x
-unsigned int %d, %x
+unsigned int %u, %x
long %ld, %lx
unsigned long %lu, %lx
long long %lld, %llx
unsigned long long %llu, %llx
off_t %llu, %llx
-ptr_diff_t %td, %tx
+ptr_diff_t %td, %tx
fdt_addr_t %pa, see pointers
fdt_size_t %pa, see pointers
phys_addr_t %pa, see pointers
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 46bc200..50d33df 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -52,7 +52,7 @@
* The Merge Window for the next release (v2023.10) is **closed**.
-* The next branch is now **closed**.
+* The next branch is now **open**.
* Release "v2023.10" is scheduled for 02 October 2023.
@@ -66,9 +66,9 @@
* U-Boot v2023.10-rc1 was released on Tue 25 July 2023.
-.. * U-Boot v2023.10-rc2 was released on Mon 07 August 2023.
+* U-Boot v2023.10-rc2 was released on Mon 07 August 2023.
-.. * U-Boot v2023.10-rc3 was released on Mon 21 August 2023.
+* U-Boot v2023.10-rc3 was released on Mon 21 August 2023.
.. * U-Boot v2023.10-rc4 was released on Mon 04 September 2023.
diff --git a/doc/develop/spl.rst b/doc/develop/spl.rst
index a1515a7..76e87f0 100644
--- a/doc/develop/spl.rst
+++ b/doc/develop/spl.rst
@@ -77,10 +77,11 @@
This checks CONFIG_CLK for the main build, CONFIG_SPL_CLK for the SPL build,
CONFIG_TPL_CLK for the TPL build, etc.
-U-Boot Phases
--------------
+U-Boot Boot Phases
+------------------
-U-Boot boots through the following phases:
+U-Boot goes through the following boot phases where TPL, VPL, SPL are optional.
+While many boards use SPL, less use TPL.
TPL
Very early init, as tiny as possible. This loads SPL (or VPL if enabled).
@@ -97,6 +98,12 @@
U-Boot
U-Boot proper, containing the command line and boot logic.
+Further usages of U-Boot SPL comprise:
+
+* Launching BL31 of ARM Trusted Firmware which invokes main U-Boot as BL33
+* launching EDK II
+* launching Linux kernel
+* launching RISC-V OpenSBI which invokes main U-Boot
Checking the boot phase
-----------------------
diff --git a/doc/develop/trace.rst b/doc/develop/trace.rst
index 9bbe134..5468620 100644
--- a/doc/develop/trace.rst
+++ b/doc/develop/trace.rst
@@ -139,7 +139,7 @@
.. code-block:: console
- $ ./sandbox/tools/proftool -m sandbox/System.map -t trace -f funcgraph dump-ftrace >trace.dat
+ $ ./sandbox/tools/proftool -m sandbox/System.map -t trace -f funcgraph dump-ftrace -o trace.dat
Again, you can use kernelshark or trace-cmd to look at the output. In this case
you will see the time taken by each function shown against its exit record.
@@ -171,7 +171,7 @@
.. code-block:: console
- $ ./sandbox/tools/proftool -m sandbox/System.map -t trace dump-flamegraph >trace.fg
+ $ ./sandbox/tools/proftool -m sandbox/System.map -t trace dump-flamegraph -o trace.fg
$ flamegraph.pl trace.fg >trace.svg
You can load the .svg file into a viewer. If you use Chrome (and some other
@@ -191,7 +191,7 @@
.. code-block:: console
- $ ./sandbox/tools/proftool -m sandbox/System.map -t trace dump-flamegraph -f timing >trace.fg
+ $ ./sandbox/tools/proftool -m sandbox/System.map -t trace dump-flamegraph -f timing -o trace.fg
$ flamegraph.pl trace.fg >trace.svg
Note that trace collection does slow down execution so the timings will be
diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
index a7a41f2..68f9b33 100644
--- a/doc/develop/uefi/uefi.rst
+++ b/doc/develop/uefi/uefi.rst
@@ -318,6 +318,9 @@
--guid <image GUID> \
<capsule_file_name>
+Capsule with firmware version
+*****************************
+
The UEFI specification does not define the firmware versioning mechanism.
EDK II reference implementation inserts the FMP Payload Header right before
the payload. It coutains the fw_version and lowest supported version,
@@ -345,6 +348,43 @@
If the --fw-version option is not set, FMP Payload Header is not inserted
and fw_version is set as 0.
+Capsule Generation through binman
+*********************************
+
+Support has also been added to generate capsules during U-Boot build
+through binman. This requires the platform's DTB to be populated with
+the capsule entry nodes for binman. The capsules then can be generated
+by specifying the capsule parameters as properties in the capsule
+entry node.
+
+Check the test/py/tests/test_efi_capsule/capsule_gen_binman.dts file
+as reference for how a typical binman node for capsule generation
+looks like. For generating capsules as part of the platform's build, a
+capsule node would then have to be included into the platform's
+devicetree.
+
+A typical binman node for generating a capsule would look like::
+
+ capsule {
+ filename = "u-boot.capsule";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = "09d7cf52-0720-4710-91d1-08469b7fe9c8";
+
+ u-boot {
+ };
+ };
+ };
+
+In the above example, a capsule file named u-boot.capsule will be
+generated with u-boot.bin as it's input payload. The capsule
+generation parameters like image-index and image-guid are being
+specified as properties. Similarly, other properties like the private
+and public key certificate can be specified for generating signed
+capsules. Refer :ref:`etype_efi_capsule` for documentation about the
+efi-capsule binman entry type, which describes all the properties that
+can be specified.
+
Performing the update
*********************
@@ -522,20 +562,11 @@
...
}
-You can do step-4 manually with
-
-.. code-block:: console
-
- $ dtc -@ -I dts -O dtb -o signature.dtbo signature.dts
- $ fdtoverlay -i orig.dtb -o new.dtb -v signature.dtbo
-
-where signature.dts looks like::
-
- &{/} {
- signature {
- capsule-key = /incbin/("CRT.esl");
- };
- };
+You can perform step-4 through the Kconfig symbol
+CONFIG_EFI_CAPSULE_ESL_FILE. This symbol points to the esl file
+generated in step-2. Once the symbol has been populated with the path
+to the esl file, it will automatically get embedded into the
+platform's dtb as part of U-Boot build.
Anti-rollback Protection
************************
diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
index da210bf..1381bdc 100644
--- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
+++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
@@ -41,3 +41,6 @@
resets = <&rst FPGAMGR_RESET>;
altr,bitstream = "fit_spl_fpga.itb";
};
+
+- The .its related documentations can be found here
+ - Appendix - Reducing Arria 10 Fabric Configuration Time - https://rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf.sh b/doc/imx/habv4/csf_examples/mx8m/csf.sh
index d87015f..65c1430 100644
--- a/doc/imx/habv4/csf_examples/mx8m/csf.sh
+++ b/doc/imx/habv4/csf_examples/mx8m/csf.sh
@@ -11,7 +11,6 @@
# 1) Build U-Boot (e.g. for i.MX8MM)
#
-# export ATF_LOAD_ADDR=0x920000
# cp -Lv /path/to/arm-trusted-firmware/build/imx8mm/release/bl31.bin .
# cp -Lv /path/to/firmware-imx-8.14/firmware/ddr/synopsys/ddr3* .
# make -j imx8mm_board_defconfig
diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt
index b74661a..4f411f7 100644
--- a/doc/sphinx/requirements.txt
+++ b/doc/sphinx/requirements.txt
@@ -1,6 +1,6 @@
alabaster==0.7.12
Babel==2.9.1
-certifi==2023.5.7
+certifi==2023.07.22
charset-normalizer==2.0.12
docutils==0.16
idna==3.3
diff --git a/doc/usage/cmd/armffa.rst b/doc/usage/cmd/armffa.rst
new file mode 100644
index 0000000..13fa90c
--- /dev/null
+++ b/doc/usage/cmd/armffa.rst
@@ -0,0 +1,94 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+
+armffa command
+==============
+
+Synopsis
+--------
+
+::
+
+ armffa [sub-command] [arguments]
+
+ sub-commands:
+
+ getpart [partition UUID]
+
+ lists the partition(s) info
+
+ ping [partition ID]
+
+ sends a data pattern to the specified partition
+
+ devlist
+
+ displays information about the FF-A device/driver
+
+Description
+-----------
+
+armffa is a command showcasing how to use the FF-A bus and how to invoke its operations.
+
+This provides a guidance to the client developers on how to call the FF-A bus interfaces.
+
+The command also allows to gather secure partitions information and ping these partitions.
+
+The command is also helpful in testing the communication with secure partitions.
+
+Example
+-------
+
+The following examples are run on Corstone-1000 platform.
+
+* ping
+
+::
+
+ corstone1000# armffa ping 0x8003
+ SP response:
+ [LSB]
+ fffffffe
+ 0
+ 0
+ 0
+ 0
+
+* ping (failure case)
+
+::
+
+ corstone1000# armffa ping 0
+ Sending direct request error (-22)
+
+* getpart
+
+::
+
+ corstone1000# armffa getpart 33d532ed-e699-0942-c09c-a798d9cd722d
+ Partition: id = 8003 , exec_ctxt 1 , properties 3
+
+* getpart (failure case)
+
+::
+
+ corstone1000# armffa getpart 33d532ed-e699-0942-c09c-a798d9cd7221
+ INVALID_PARAMETERS: Unrecognized UUID
+ Failure in querying partitions count (error code: -22)
+
+* devlist
+
+::
+
+ corstone1000# armffa devlist
+ device name arm_ffa, dev 00000000fdf41c30, driver name arm_ffa, ops 00000000fffc0e98
+
+Configuration
+-------------
+
+The command is available if CONFIG_CMD_ARMFFA=y and CONFIG_ARM_FFA_TRANSPORT=y.
+
+Return value
+------------
+
+The return value $? is 0 (true) on success, 1 (false) on failure.
diff --git a/doc/usage/cmd/bootflow.rst b/doc/usage/cmd/bootflow.rst
index a8af1f8..ead493d 100644
--- a/doc/usage/cmd/bootflow.rst
+++ b/doc/usage/cmd/bootflow.rst
@@ -11,7 +11,8 @@
bootflow scan [-abelGH] [bootdev]
bootflow list [-e]
bootflow select [<num|name>]
- bootflow info [-d]
+ bootflow info [-ds]
+ bootflow read
bootflow boot
bootflow cmdline [set|get|clear|delete|auto] <param> [<value>]
@@ -191,11 +192,29 @@
Use the `-d` flag to dump out the contents of the bootfile file.
+The `-s` flag shows any x86 setup block, instead of the above.
+
+
+bootflow read
+~~~~~~~~~~~~~
+
+This reads any files related to the bootflow. Some bootflows with large files
+avoid doing this when the bootflow is scanned, since it uses a lot of memory
+and takes extra time. The files are then automatically read when `bootflow boot`
+is used.
+
+This command reads these files immediately. Typically this fills in the bootflow
+`buf` property, which can be used to examine the bootflow.
+
+Note that reading the files does not result in any extra parsing, nor loading of
+images in the files. This is purely used to read in the data ready for
+booting, or examination.
+
bootflow boot
~~~~~~~~~~~~~
-This boots the current bootflow.
+This boots the current bootflow, reading any required files first.
bootflow cmdline
@@ -522,6 +541,122 @@
[ 0.000000] Command line: loglevel=7 ... usb-storage.quirks=13fe:6500:u earlycon=uart8250,mmio32,0xfe03e000,115200n8
[ 0.000000] x86/split lock detection: warning about user-space split_locks
+This shows looking at x86 setup information::
+
+ => bootfl sel 0
+ => bootfl i -s
+ Setup located at 77b56010:
+
+ ACPI RSDP addr : 0
+ E820: 2 entries
+ Addr Size Type
+ 0 1000 RAM
+ fffff000 1000 Reserved
+ Setup sectors : 1e
+ Root flags : 1
+ Sys size : 63420
+ RAM size : 0
+ Video mode : ffff
+ Root dev : 0
+ Boot flag : 0
+ Jump : 66eb
+ Header : 53726448
+ Kernel V2
+ Version : 20d
+ Real mode switch : 0
+ Start sys seg : 1000
+ Kernel version : 38cc
+ @00003acc:
+ Type of loader : ff
+ unknown
+ Load flags : 1
+ : loaded-high
+ Setup move size : 8000
+ Code32 start : 100000
+ Ramdisk image : 0
+ Ramdisk size : 0
+ Bootsect kludge : 0
+ Heap end ptr : 5160
+ Ext loader ver : 0
+ Ext loader type : 0
+ Command line ptr : 735000
+ Initrd addr max : 7fffffff
+ Kernel alignment : 200000
+ Relocatable kernel : 1
+ Min alignment : 15
+ : 200000
+ Xload flags : 3
+ : 64-bit-entry can-load-above-4gb
+ Cmdline size : 7ff
+ Hardware subarch : 0
+ HW subarch data : 0
+ Payload offset : 26e
+ Payload length : 612045
+ Setup data : 0
+ Pref address : 1000000
+ Init size : 1383000
+ Handover offset : 0
+
+This shows reading a bootflow to examine the kernel::
+
+ => bootfl i 0
+ Name:
+ Device: emmc@1c,0.bootdev
+ Block dev: emmc@1c,0.blk
+ Method: cros
+ State: ready
+ Partition: 2
+ Subdir: (none)
+ Filename: <NULL>
+ Buffer: 0
+ Size: 63ee00 (6548992 bytes)
+ OS: ChromeOS
+ Cmdline: console= loglevel=7 init=/sbin/init cros_secure oops=panic panic=-1 root=PARTUUID=35c775e7-3735-d745-93e5-d9e0238f7ed0/PARTNROFF=1 rootwait rw dm_verity.error_behavior=3 dm_verity.max_bios=-1 dm_verity.dev_wait=0 dm="1 vroot none rw 1,0 3788800 verity payload=ROOT_DEV hashtree=HASH_DEV hashstart=3788800 alg=sha1 root_hexdigest=55052b629d3ac889f25a9583ea12cdcd3ea15ff8 salt=a2d4d9e574069f4fed5e3961b99054b7a4905414b60a25d89974a7334021165c" noinitrd vt.global_cursor_default=0 kern_guid=35c775e7-3735-d745-93e5-d9e0238f7ed0 add_efi_memmap boot=local noresume noswap i915.modeset=1 tpm_tis.force=1 tpm_tis.interrupts=0 nmi_watchdog=panic,lapic disablevmx=off
+ X86 setup: 77b56010
+ Logo: (none)
+ FDT: <NULL>
+ Error: 0
+
+Note that `Buffer` is 0 so it has not be read yet. Using `bootflow read`::
+
+ => bootfl read
+ => bootfl info
+ Name:
+ Device: emmc@1c,0.bootdev
+ Block dev: emmc@1c,0.blk
+ Method: cros
+ State: ready
+ Partition: 2
+ Subdir: (none)
+ Filename: <NULL>
+ Buffer: 77b7e400
+ Size: 63ee00 (6548992 bytes)
+ OS: ChromeOS
+ Cmdline: console= loglevel=7 init=/sbin/init cros_secure oops=panic panic=-1 root=PARTUUID=35c775e7-3735-d745-93e5-d9e0238f7ed0/PARTNROFF=1 rootwait rw dm_verity.error_behavior=3 dm_verity.max_bios=-1 dm_verity.dev_wait=0 dm="1 vroot none rw 1,0 3788800 verity payload=ROOT_DEV hashtree=HASH_DEV hashstart=3788800 alg=sha1 root_hexdigest=55052b629d3ac889f25a9583ea12cdcd3ea15ff8 salt=a2d4d9e574069f4fed5e3961b99054b7a4905414b60a25d89974a7334021165c" noinitrd vt.global_cursor_default=0 kern_guid=35c775e7-3735-d745-93e5-d9e0238f7ed0 add_efi_memmap boot=local noresume noswap i915.modeset=1 tpm_tis.force=1 tpm_tis.interrupts=0 nmi_watchdog=panic,lapic disablevmx=off
+ X86 setup: 781b4400
+ Logo: (none)
+ FDT: <NULL>
+ Error: 0
+
+Now the buffer can be accessed::
+
+ => md 77b7e400
+ 77b7e400: 1186f6fc 40000002 b8fa0c75 00000018 .......@u.......
+ 77b7e410: c08ed88e a68dd08e 000001e8 000000e8 ................
+ 77b7e420: ed815d00 00000021 62c280b8 89e80100 .]..!......b....
+ 77b7e430: 22f7e8c4 c0850061 22ec850f eb890061 ..."a......"a...
+ 77b7e440: 0230868b 01480000 21d0f7c3 00fb81c3 ..0...H....!....
+ 77b7e450: 7d010000 0000bb05 c3810100 00d4f000 ...}............
+ 77b7e460: 8130858d 85890061 00618132 3095010f ..0.a...2.a....0
+ 77b7e470: 0f006181 c883e020 e0220f20 e000bb8d .a.. ... .".....
+ 77b7e480: c0310062 001800b9 8dabf300 62e000bb b.1............b
+ 77b7e490: 07878d00 89000010 00bb8d07 8d0062f0 .............b..
+ 77b7e4a0: 00100787 0004b900 07890000 00100005 ................
+ 77b7e4b0: 08c78300 8df37549 630000bb 0183b800 ....Iu.....c....
+ 77b7e4c0: 00b90000 89000008 00000507 c7830020 ............ ...
+ 77b7e4d0: f3754908 e000838d 220f0062 0080b9d8 .Iu.....b.."....
+ 77b7e4e0: 320fc000 08e8ba0f c031300f b8d0000f ...2.....01.....
+ 77b7e4f0: 00000020 6ad8000f 00858d10 50000002 ......j.......P
Return value
diff --git a/doc/usage/cmd/cedit.rst b/doc/usage/cmd/cedit.rst
index 8e1110c..f415b48 100644
--- a/doc/usage/cmd/cedit.rst
+++ b/doc/usage/cmd/cedit.rst
@@ -10,6 +10,11 @@
cedit load <interface> <dev[:part]> <filename>
cedit run
+ cedit write_fdt <dev[:part]> <filename>
+ cedit read_fdt <dev[:part]> <filename>
+ cedit write_env [-v]
+ cedit read_env [-v]
+ cedit write_cmos [-v] [dev]
Description
-----------
@@ -22,6 +27,69 @@
The description is in the form of a devicetree file, as documented at
:ref:`expo_format`.
+See :doc:`../../develop/cedit` for information about the configuration editor.
+
+cedit load
+~~~~~~~~~~
+
+Loads a configuration-editor description from a file. It creates a new cedit
+structure ready for use. Initially no settings are read, so default values are
+used for each object.
+
+cedit run
+~~~~~~~~~
+
+Runs the default configuration-editor event loop. This is very simple, just
+accepting character input and moving through the objects under user control.
+The implementation is at `cedit_run()`.
+
+cedit write_fdt
+~~~~~~~~~~~~~~~
+
+Writes the current user settings to a devicetree file. For each menu item the
+selected ID and its text string are written.
+
+cedit read_fdt
+~~~~~~~~~~~~~~
+
+Reads the user settings from a devicetree file and updates the cedit with those
+settings.
+
+cedit read_env
+~~~~~~~~~~~~~~
+
+Reads the settings from the environment variables. For each menu item `<name>`,
+cedit looks for a variable called `c.<name>` with the ID of the selected menu
+item.
+
+The `-v` flag enables verbose mode, where each variable is printed after it is
+read.
+
+cedit write_env
+~~~~~~~~~~~~~~~
+
+Writes the settings to environment variables. For each menu item the selected
+ID and its text string are written, similar to:
+
+ setenv c.<name> <selected_id>
+ setenv c.<name>-str <selected_id's text string>
+
+The `-v` flag enables verbose mode, where each variable is printed before it is
+set.
+
+cedit write_cmos
+~~~~~~~~~~~~~~~~
+
+Writes the settings to locations in the CMOS RAM. The locations used are
+specified by the schema. See `expo_format_`.
+
+The `-v` flag enables verbose mode, which shows which CMOS locations were
+updated.
+
+Normally the first RTC device is used to hold the data. You can specify a
+different device by name using the `dev` parameter.
+
+
Example
-------
@@ -29,3 +97,52 @@
=> cedit load hostfs - fred.dtb
=> cedit run
+ => cedit write_fdt hostfs - settings.dtb
+
+That results in::
+
+ / {
+ cedit-values {
+ cpu-speed = <0x00000006>;
+ cpu-speed-str = "2 GHz";
+ power-loss = <0x0000000a>;
+ power-loss-str = "Always Off";
+ };
+ }
+
+ => cedit read_fdt hostfs - settings.dtb
+
+This shows settings being stored in the environment::
+
+ => cedit write_env -v
+ c.cpu-speed=7
+ c.cpu-speed-str=2.5 GHz
+ c.power-loss=12
+ c.power-loss-str=Memory
+ => print
+ ...
+ c.cpu-speed=6
+ c.cpu-speed-str=2 GHz
+ c.power-loss=10
+ c.power-loss-str=Always Off
+ ...
+
+ => cedit read_env -v
+ c.cpu-speed=7
+ c.power-loss=12
+
+This shows writing to CMOS RAM. Notice that the bytes at 80 and 84 change::
+
+ => rtc read 80 8
+ 00000080: 00 00 00 00 00 2f 2a 08 ...../*.
+ => cedit write_cmos -v
+ Write 2 bytes from offset 80 to 84
+ => rtc read 80 8
+ 00000080: 01 00 00 00 08 2f 2a 08 ...../*.
+ => cedit read_cmos -v
+ Read 2 bytes from offset 80 to 84
+
+Here is an example with the device specified::
+
+ => cedit write_cmos rtc@43
+ =>
diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst
index 2c44e5d..c6439dd 100644
--- a/doc/usage/environment.rst
+++ b/doc/usage/environment.rst
@@ -81,6 +81,12 @@
echo CONFIG_SYS_BOARD boot failed - please check your image
echo Load address is CONFIG_SYS_LOAD_ADDR
+Settings which are common to a group of boards can use #include to bring in
+a common file in the `include/env` directory, containing environment
+settings. For example::
+
+ #include <env/ti/mmc.env>
+
If CONFIG_ENV_SOURCE_FILE is empty and the default filename is not present, then
the old-style C environment is used instead. See below.
@@ -94,7 +100,7 @@
Board maintainers are encouraged to migrate to the text-based environment as it
is easier to maintain. The distro-board script still requires the old-style
-environment but work is underway to address this.
+environments, so use :doc:`../develop/bootstd` instead.
List of environment variables
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index 072db53..3326ec8 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -22,6 +22,7 @@
cmd/acpi
cmd/addrmap
+ cmd/armffa
cmd/askenv
cmd/base
cmd/bdinfo
diff --git a/drivers/Makefile b/drivers/Makefile
index 3bc6d27..efc2a4a 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -39,6 +39,8 @@
obj-$(CONFIG_$(SPL_)NVME) += nvme/
obj-$(CONFIG_XEN) += xen/
obj-$(CONFIG_$(SPL_)FPGA) += fpga/
+obj-$(CONFIG_$(SPL_)VIDEO) += video/
+
obj-y += bus/
ifndef CONFIG_TPL_BUILD
@@ -64,7 +66,6 @@
obj-$(CONFIG_SPL_SATA) += ata/ scsi/
obj-$(CONFIG_SPL_LEGACY_BLOCK) += block/
obj-$(CONFIG_SPL_THERMAL) += thermal/
-obj-$(CONFIG_SPL_VIDEO) +=video/
endif
endif
@@ -99,7 +100,6 @@
obj-y += scsi/
obj-y += sound/
obj-y += spmi/
-obj-y += video/
obj-y += watchdog/
obj-$(CONFIG_QE) += qe/
obj-$(CONFIG_U_QE) += qe/
@@ -115,6 +115,7 @@
obj-y += smem/
obj-y += thermal/
obj-$(CONFIG_TEE) += tee/
+obj-$(CONFIG_ARM_FFA_TRANSPORT) += firmware/arm-ffa/
obj-y += axi/
obj-y += ufs/
obj-$(CONFIG_W1) += w1/
diff --git a/drivers/adc/adc-uclass.c b/drivers/adc/adc-uclass.c
index 9646e4d..6074ecc 100644
--- a/drivers/adc/adc-uclass.c
+++ b/drivers/adc/adc-uclass.c
@@ -51,23 +51,21 @@
static int adc_supply_enable(struct udevice *dev)
{
struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
- const char *supply_type;
- int ret = 0;
+ int ret;
- if (uc_pdata->vdd_supply) {
- supply_type = "vdd";
- ret = regulator_set_enable(uc_pdata->vdd_supply, true);
+ ret = regulator_set_enable_if_allowed(uc_pdata->vdd_supply, true);
+ if (ret && ret != -ENOSYS) {
+ pr_err("%s: can't enable vdd-supply!", dev->name);
+ return ret;
}
- if (!ret && uc_pdata->vss_supply) {
- supply_type = "vss";
- ret = regulator_set_enable(uc_pdata->vss_supply, true);
+ ret = regulator_set_enable_if_allowed(uc_pdata->vss_supply, true);
+ if (ret && ret != -ENOSYS) {
+ pr_err("%s: can't enable vss-supply!", dev->name);
+ return ret;
}
- if (ret)
- pr_err("%s: can't enable %s-supply!", dev->name, supply_type);
-
- return ret;
+ return 0;
}
int adc_data_mask(struct udevice *dev, unsigned int *data_mask)
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 6baaa6f..1abea3f 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -167,7 +167,7 @@
config SYS_ATA_BASE_ADDR
hex "Base address of IDE controller"
- default 0
+ default 0x0
help
This is the address of the IDE controller, from which other addresses
are calculated. Each bus is at a fixed offset from this address,
diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index 614b975..8855138 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -17,6 +17,8 @@
#include <dm/uclass-internal.h>
#include <linux/err.h>
+#define blk_get_ops(dev) ((struct blk_ops *)(dev)->driver->ops)
+
static struct {
enum uclass_id id;
const char *name;
@@ -444,6 +446,26 @@
return device_probe(*devp);
}
+struct blk_bounce_buffer {
+ struct udevice *dev;
+ struct bounce_buffer state;
+};
+
+static int blk_buffer_aligned(struct bounce_buffer *state)
+{
+#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
+ struct blk_bounce_buffer *bbstate =
+ container_of(state, struct blk_bounce_buffer, state);
+ struct udevice *dev = bbstate->dev;
+ const struct blk_ops *ops = blk_get_ops(dev);
+
+ if (ops->buffer_aligned)
+ return ops->buffer_aligned(dev, state);
+#endif /* CONFIG_BOUNCE_BUFFER */
+
+ return 1; /* Default, any buffer is OK */
+}
+
long blk_read(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *buf)
{
struct blk_desc *desc = dev_get_uclass_plat(dev);
@@ -456,7 +478,25 @@
if (blkcache_read(desc->uclass_id, desc->devnum,
start, blkcnt, desc->blksz, buf))
return blkcnt;
- blks_read = ops->read(dev, start, blkcnt, buf);
+
+ if (IS_ENABLED(CONFIG_BOUNCE_BUFFER)) {
+ struct blk_bounce_buffer bbstate = { .dev = dev };
+ int ret;
+
+ ret = bounce_buffer_start_extalign(&bbstate.state, buf,
+ blkcnt * desc->blksz,
+ GEN_BB_WRITE, desc->blksz,
+ blk_buffer_aligned);
+ if (ret)
+ return ret;
+
+ blks_read = ops->read(dev, start, blkcnt, bbstate.state.bounce_buffer);
+
+ bounce_buffer_stop(&bbstate.state);
+ } else {
+ blks_read = ops->read(dev, start, blkcnt, buf);
+ }
+
if (blks_read == blkcnt)
blkcache_fill(desc->uclass_id, desc->devnum, start, blkcnt,
desc->blksz, buf);
@@ -469,13 +509,33 @@
{
struct blk_desc *desc = dev_get_uclass_plat(dev);
const struct blk_ops *ops = blk_get_ops(dev);
+ long blks_written;
if (!ops->write)
return -ENOSYS;
blkcache_invalidate(desc->uclass_id, desc->devnum);
+ if (IS_ENABLED(CONFIG_BOUNCE_BUFFER)) {
+ struct blk_bounce_buffer bbstate = { .dev = dev };
+ int ret;
+
+ ret = bounce_buffer_start_extalign(&bbstate.state, (void *)buf,
+ blkcnt * desc->blksz,
+ GEN_BB_READ, desc->blksz,
+ blk_buffer_aligned);
+ if (ret)
+ return ret;
+
+ blks_written = ops->write(dev, start, blkcnt,
+ bbstate.state.bounce_buffer);
+
+ bounce_buffer_stop(&bbstate.state);
+ } else {
+ blks_written = ops->write(dev, start, blkcnt, buf);
+ }
+
- return ops->write(dev, start, blkcnt, buf);
+ return blks_written;
}
long blk_erase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt)
@@ -762,6 +822,54 @@
return ret;
}
}
+
+ return 0;
+}
+
+static int part_create_block_devices(struct udevice *blk_dev)
+{
+ int part, count;
+ struct blk_desc *desc = dev_get_uclass_plat(blk_dev);
+ struct disk_partition info;
+ struct disk_part *part_data;
+ char devname[32];
+ struct udevice *dev;
+ int ret;
+
+ if (!CONFIG_IS_ENABLED(PARTITIONS) || !blk_enabled())
+ return 0;
+
+ if (device_get_uclass_id(blk_dev) != UCLASS_BLK)
+ return 0;
+
+ /* Add devices for each partition */
+ for (count = 0, part = 1; part <= MAX_SEARCH_PARTITIONS; part++) {
+ if (part_get_info(desc, part, &info))
+ continue;
+ snprintf(devname, sizeof(devname), "%s:%d", blk_dev->name,
+ part);
+
+ ret = device_bind_driver(blk_dev, "blk_partition",
+ strdup(devname), &dev);
+ if (ret)
+ return ret;
+
+ part_data = dev_get_uclass_plat(dev);
+ part_data->partnum = part;
+ part_data->gpt_part_info = info;
+ count++;
+
+ ret = device_probe(dev);
+ if (ret) {
+ debug("Can't probe\n");
+ count--;
+ device_unbind(dev);
+
+ continue;
+ }
+ }
+ debug("%s: %d partitions found in %s\n", __func__, count,
+ blk_dev->name);
return 0;
}
diff --git a/drivers/block/ide.c b/drivers/block/ide.c
index 89201dd..c698f9c 100644
--- a/drivers/block/ide.c
+++ b/drivers/block/ide.c
@@ -1059,9 +1059,9 @@
desc->lba48 = pdesc.lba48;
desc->type = pdesc.type;
- ret = bootdev_setup_for_dev(udev, "ide_bootdev");
+ ret = bootdev_setup_for_sibling_blk(blk, "ide_bootdev");
if (ret)
- return log_msg_ret("bootdev", ret);
+ return log_msg_ret("bd", ret);
}
return 0;
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 1decf31..e74c6f9 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -9,6 +9,7 @@
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o
obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o
+obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o
obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
new file mode 100644
index 0000000..34e7b2d
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -0,0 +1,1123 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT7988 SoC
+ *
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <dm.h>
+#include <log.h>
+#include <asm/arch-mediatek/reset.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt7988-clk.h>
+#include <linux/bitops.h>
+
+#include "clk-mtk.h"
+
+#define MT7988_CLK_PDN 0x250
+#define MT7988_CLK_PDN_EN_WRITE BIT(31)
+
+#define MT7988_ETHDMA_RST_CTRL_OFS 0x34
+#define MT7988_ETHWARP_RST_CTRL_OFS 0x8
+
+#define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL)
+
+#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define TOP_FACTOR(_id, _name, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS)
+
+/* FIXED PLLS */
+static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
+ FIXED_CLK(CK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000),
+ FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
+ FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000),
+ FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
+ FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
+ FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
+ FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
+ FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
+ FIXED_CLK(CK_APMIXED_ARM_B, CLK_XTAL, 1500000000),
+ FIXED_CLK(CK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000),
+ FIXED_CLK(CK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000),
+ FIXED_CLK(CK_APMIXED_MSDCPLL, CLK_XTAL, 400000000),
+};
+
+/* TOPCKGEN FIXED DIV */
+static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
+ XTAL_FACTOR(CK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1),
+ PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
+ PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
+ PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
+ PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
+ PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1),
+ PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
+ PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15),
+ PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
+ PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12),
+ PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
+ PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
+ 1),
+ PLL_FACTOR(CK_TOP_CB_APLL2_D4, "cb_apll2_d4", CK_APMIXED_APLL2, 1, 4),
+ PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
+ PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
+ PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
+ PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
+ PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8),
+ PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
+ PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
+ PLL_FACTOR(CK_TOP_NET1_D8_D8, "net1_d8_d8", CK_APMIXED_NET1PLL, 1, 64),
+ PLL_FACTOR(CK_TOP_NET1_D8_D16, "net1_d8_d16", CK_APMIXED_NET1PLL, 1,
+ 128),
+ PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
+ 1),
+ PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2),
+ PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
+ PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
+ PLL_FACTOR(CK_TOP_NET2_D4_D8, "net2_d4_d8", CK_APMIXED_NET2PLL, 1, 32),
+ PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6),
+ PLL_FACTOR(CK_TOP_CB_NET2_D8, "cb_net2_d8", CK_APMIXED_NET2PLL, 1, 8),
+ PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m",
+ CK_APMIXED_WEDMCUPLL, 1, 1),
+ PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
+ PLL_FACTOR(CK_TOP_CB_NETSYS_850M, "cb_netsys_850m",
+ CK_APMIXED_NETSYSPLL, 1, 1),
+ PLL_FACTOR(CK_TOP_CB_MSDC_400M, "cb_msdc_400m", CK_APMIXED_MSDCPLL, 1,
+ 1),
+ TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2),
+ TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
+ 1250),
+ TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
+ 1220),
+ TOP_FACTOR(CK_TOP_INFRA_F32K, "csw_infra_f32k", CK_TOP_CB_RTC_32P7K, 1,
+ 1),
+ XTAL_FACTOR(CK_TOP_CKSQ_SRC, "cksq_src", CLK_XTAL, 1, 1),
+ TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_NETSYS_GSW, "netsys_gsw", CK_TOP_NETSYS_GSW_SEL, 1,
+ 1),
+ TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
+ CK_TOP_NETSYS_MCU_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_EIP197, "eip197", CK_TOP_EIP197_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_USB_SYS, "usb_sys", CK_TOP_USB_SYS_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_USB_SYS_P1, "usb_sys_p1", CK_TOP_USB_SYS_P1_SEL, 1,
+ 1),
+ TOP_FACTOR(CK_TOP_USB_XHCI, "usb_xhci", CK_TOP_USB_XHCI_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_USB_XHCI_P1, "usb_xhci_p1", CK_TOP_USB_XHCI_P1_SEL, 1,
+ 1),
+ TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1,
+ 1),
+ TOP_FACTOR(CK_TOP_USB_FRMCNT_P1, "usb_frmcnt_p1",
+ CK_TOP_USB_FRMCNT_P1_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_AUD_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
+ TOP_FACTOR(CK_TOP_INFRA_F26M, "csw_infra_f26m", CK_TOP_INFRA_F26M_SEL,
+ 1, 1),
+ TOP_FACTOR(CK_TOP_USB_REF, "usb_ref", CK_TOP_CKSQ_SRC, 1, 1),
+ TOP_FACTOR(CK_TOP_USB_CK_P1, "usb_ck_p1", CK_TOP_CKSQ_SRC, 1, 1),
+};
+
+/* TOPCKGEN MUX PARENTS */
+static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2,
+ CK_TOP_CB_MM_D2 };
+
+static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
+ CK_TOP_CB_NET1_D5,
+ CK_TOP_NET1_D5_D2 };
+
+static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
+ CK_TOP_CB_NET2_800M,
+ CK_TOP_CB_MM_720M };
+
+static const int netsys_gsw_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D4,
+ CK_TOP_CB_NET1_D5 };
+
+static const int eth_gmii_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
+
+static const int netsys_mcu_parents[] = {
+ CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M, CK_TOP_CB_MM_720M,
+ CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5, CK_TOP_CB_M_416M
+};
+
+static const int eip197_parents[] = {
+ CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NETSYS_850M, CK_TOP_CB_NET2_800M,
+ CK_TOP_CB_MM_720M, CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5
+};
+
+static const int axi_infra_parents[] = { CK_TOP_CB_CKSQ_40M,
+ CK_TOP_NET1_D8_D2 };
+
+static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
+ CK_TOP_M_D8_D2 };
+
+static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D2,
+ CK_TOP_CB_MM_D4 };
+
+static const int emmc_400m_parents[] = {
+ CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MSDC_400M, CK_TOP_CB_MM_D2,
+ CK_TOP_CB_M_D2, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2
+};
+
+static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
+ CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2,
+ CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4,
+ CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
+
+static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4,
+ CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6,
+ CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8,
+ CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 };
+
+static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M,
+ CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
+ CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4,
+ CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 };
+
+static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
+ CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
+ CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
+
+static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
+ CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
+
+static const int pcie_mbist_250m_parents[] = { CK_TOP_CB_CKSQ_40M,
+ CK_TOP_NET1_D5_D2 };
+
+static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
+ CK_TOP_CB_NET2_D6, CK_TOP_CB_MM_D8,
+ CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
+
+static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M,
+ CK_TOP_CB_MM_D3_D5 };
+
+static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M };
+
+static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_D4 };
+
+static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
+ CK_TOP_M_D8_D2 };
+
+static const int sspxtp_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 };
+
+static const int usxgmii_sbus_0_parents[] = { CK_TOP_CB_CKSQ_40M,
+ CK_TOP_NET1_D8_D4 };
+
+static const int sgm_0_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M };
+
+static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 };
+
+static const int eth_refck_50m_parents[] = { CK_TOP_CB_CKSQ_40M,
+ CK_TOP_NET2_D4_D4 };
+
+static const int eth_sys_200m_parents[] = { CK_TOP_CB_CKSQ_40M,
+ CK_TOP_CB_NET2_D4 };
+
+static const int eth_xgmii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET1_D8_D8,
+ CK_TOP_NET1_D8_D16 };
+
+static const int bus_tops_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,
+ CK_TOP_CB_NET2_D2 };
+
+static const int npu_tops_parents[] = { CK_TOP_CB_CKSQ_40M,
+ CK_TOP_CB_NET2_800M };
+
+static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
+ CK_TOP_CB_WEDMCU_208M };
+
+static const int da_xtp_glb_p0_parents[] = { CK_TOP_CB_CKSQ_40M,
+ CK_TOP_CB_NET2_D8 };
+
+static const int mcusys_backup_625m_parents[] = { CK_TOP_CB_CKSQ_40M,
+ CK_TOP_CB_NET1_D4 };
+
+static const int macsec_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M,
+ CK_TOP_CB_NET1_D8 };
+
+static const int netsys_tops_400m_parents[] = { CK_TOP_CB_CKSQ_40M,
+ CK_TOP_CB_NET2_D2 };
+
+static const int eth_mii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET2_D4_D8 };
+
+#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
+ _shift, _width, _gate, _upd_ofs, _upd) \
+ { \
+ .id = _id, .mux_reg = _mux_ofs, .mux_set_reg = _mux_set_ofs, \
+ .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \
+ .upd_shift = _upd, .mux_shift = _shift, \
+ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \
+ .gate_shift = _gate, .parent = _parents, \
+ .num_parents = ARRAY_SIZE(_parents), \
+ .flags = CLK_MUX_SETCLR_UPD, \
+ }
+
+/* TOPCKGEN MUX_GATE */
+static const struct mtk_composite topckgen_mtk_muxes[] = {
+ TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8,
+ 0, 2, 7, 0x1c0, 0),
+ TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
+ 0x0, 0x4, 0x8, 8, 2, 15, 0x1c0, 1),
+ TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0,
+ 0x4, 0x8, 16, 2, 23, 0x1c0, 2),
+ TOP_MUX(CK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents,
+ 0x0, 0x4, 0x8, 24, 2, 31, 0x1c0, 3),
+ TOP_MUX(CK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10,
+ 0x14, 0x18, 0, 1, 7, 0x1c0, 4),
+ TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
+ 0x10, 0x14, 0x18, 8, 3, 15, 0x1c0, 5),
+ TOP_MUX(CK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
+ netsys_mcu_parents, 0x10, 0x14, 0x18, 16, 3, 23, 0x1c0, 6),
+ TOP_MUX(CK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14,
+ 0x18, 24, 3, 31, 0x1c0, 7),
+ TOP_MUX(CK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20,
+ 0x24, 0x28, 0, 1, 7, 0x1c0, 8),
+ TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8,
+ 2, 15, 0x1c0, 9),
+ TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20,
+ 0x24, 0x28, 16, 2, 23, 0x1c0, 10),
+ TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
+ 0x24, 0x28, 24, 3, 31, 0x1c0, 11),
+ TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3,
+ 7, 0x1c0, 12),
+ TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34,
+ 0x38, 8, 3, 15, 0x1c0, 13),
+ TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38,
+ 16, 3, 23, 0x1c0, 14),
+ TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34,
+ 0x38, 24, 3, 31, 0x1c0, 15),
+ TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3,
+ 7, 0x1c0, 16),
+ TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2,
+ 15, 0x1c0, 17),
+ TOP_MUX(CK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
+ pcie_mbist_250m_parents, 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0,
+ 18),
+ TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
+ 0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19),
+ TOP_MUX(CK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel",
+ pextp_tl_ck_parents, 0x50, 0x54, 0x58, 0, 3, 7, 0x1c0, 20),
+ TOP_MUX(CK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel",
+ pextp_tl_ck_parents, 0x50, 0x54, 0x58, 8, 3, 15, 0x1c0, 21),
+ TOP_MUX(CK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel",
+ pextp_tl_ck_parents, 0x50, 0x54, 0x58, 16, 3, 23, 0x1c0, 22),
+ TOP_MUX(CK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54,
+ 0x58, 24, 1, 31, 0x1c0, 23),
+ TOP_MUX(CK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60,
+ 0x64, 0x68, 0, 1, 7, 0x1c0, 24),
+ TOP_MUX(CK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60,
+ 0x64, 0x68, 8, 1, 15, 0x1c0, 25),
+ TOP_MUX(CK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents,
+ 0x60, 0x64, 0x68, 16, 1, 23, 0x1c0, 26),
+ TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
+ 0x60, 0x64, 0x68, 24, 1, 31, 0x1c0, 27),
+ TOP_MUX(CK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
+ usb_frmcnt_parents, 0x70, 0x74, 0x78, 0, 1, 7, 0x1c0, 28),
+ TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1,
+ 15, 0x1c0, 29),
+ TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78,
+ 16, 1, 23, 0x1c0, 30),
+ TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78,
+ 24, 2, 31, 0x1c4, 0),
+ TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84,
+ 0x88, 0, 1, 7, 0x1c4, 1),
+ TOP_MUX(CK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84,
+ 0x88, 8, 1, 15, 0x1c4, 2),
+ TOP_MUX(CK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84,
+ 0x88, 16, 1, 23, 0x1c4, 3),
+ TOP_MUX(CK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
+ usxgmii_sbus_0_parents, 0x80, 0x84, 0x88, 24, 1, 31, 0x1c4, 4),
+ TOP_MUX(CK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
+ usxgmii_sbus_0_parents, 0x90, 0x94, 0x98, 0, 1, 7, 0x1c4, 5),
+ TOP_MUX(CK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98,
+ 8, 1, 15, 0x1c4, 6),
+ TOP_MUX(CK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
+ 0x90, 0x94, 0x98, 16, 1, 23, 0x1c4, 7),
+ TOP_MUX(CK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98,
+ 24, 1, 31, 0x1c4, 8),
+ TOP_MUX(CK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
+ 0xa0, 0xa4, 0xa8, 0, 1, 7, 0x1c4, 9),
+ TOP_MUX(CK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
+ 0xa0, 0xa4, 0xa8, 8, 1, 15, 0x1c4, 10),
+ TOP_MUX(CK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
+ 0xa0, 0xa4, 0xa8, 16, 1, 23, 0x1c4, 11),
+ TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4,
+ 0xa8, 24, 1, 31, 0x1c4, 12),
+ TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4,
+ 0xb8, 0, 1, 7, 0x1c4, 13),
+ TOP_MUX(CK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
+ eth_refck_50m_parents, 0xb0, 0xb4, 0xb8, 8, 1, 15, 0x1c4, 14),
+ TOP_MUX(CK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
+ eth_sys_200m_parents, 0xb0, 0xb4, 0xb8, 16, 1, 23, 0x1c4, 15),
+ TOP_MUX(CK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents,
+ 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x1c4, 16),
+ TOP_MUX(CK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0,
+ 0xc4, 0xc8, 0, 2, 7, 0x1c4, 17),
+ TOP_MUX(CK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0,
+ 0xc4, 0xc8, 8, 2, 15, 0x1c4, 18),
+ TOP_MUX(CK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0,
+ 0xc4, 0xc8, 16, 1, 23, 0x1c4, 19),
+ TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8,
+ 24, 1, 31, 0x1c4, 20),
+ TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
+ 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x1c4, 21),
+ TOP_MUX(CK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
+ 0xd0, 0xd4, 0xd8, 8, 1, 15, 0x1c4, 22),
+ TOP_MUX(CK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4,
+ 0xd8, 16, 1, 23, 0x1c4, 23),
+ TOP_MUX(CK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4,
+ 0xd8, 24, 1, 31, 0x1c4, 24),
+ TOP_MUX(CK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4,
+ 0xe8, 0, 1, 7, 0x1c4, 25),
+ TOP_MUX(CK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4,
+ 0xe8, 8, 1, 15, 0x1c4, 26),
+ TOP_MUX(CK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
+ da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 16, 1, 23, 0x1c4, 27),
+ TOP_MUX(CK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
+ da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 24, 1, 31, 0x1c4, 28),
+ TOP_MUX(CK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
+ da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x1c4, 29),
+ TOP_MUX(CK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
+ da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 8, 1, 15, 0x1c4, 30),
+ TOP_MUX(CK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16,
+ 1, 23, 0x1c8, 0),
+ TOP_MUX(CK_TOP_DA_SELM_XTAL_SEL, "da_selm_xtal_sel", sspxtp_parents,
+ 0xf0, 0xf4, 0xf8, 24, 1, 31, 0x1c8, 1),
+ TOP_MUX(CK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104,
+ 0x108, 0, 1, 7, 0x1c8, 2),
+ TOP_MUX(CK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents,
+ 0x100, 0x104, 0x108, 8, 1, 15, 0x1c8, 3),
+ TOP_MUX(CK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
+ mcusys_backup_625m_parents, 0x100, 0x104, 0x108, 16, 1, 23,
+ 0x1c8, 4),
+ TOP_MUX(CK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
+ pcie_mbist_250m_parents, 0x100, 0x104, 0x108, 24, 1, 31, 0x1c8,
+ 5),
+ TOP_MUX(CK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114,
+ 0x118, 0, 2, 7, 0x1c8, 6),
+ TOP_MUX(CK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
+ netsys_tops_400m_parents, 0x110, 0x114, 0x118, 8, 1, 15, 0x1c8,
+ 7),
+ TOP_MUX(CK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
+ pcie_mbist_250m_parents, 0x110, 0x114, 0x118, 16, 1, 23, 0x1c8,
+ 8),
+ TOP_MUX(CK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents,
+ 0x110, 0x114, 0x118, 24, 2, 31, 0x1c8, 9),
+ TOP_MUX(CK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120,
+ 0x124, 0x128, 0, 1, 7, 0x1c8, 10),
+ TOP_MUX(CK_TOP_CK_NPU_SEL_CM_TOPS_SEL, "ck_npu_sel_cm_tops_sel",
+ netsys_2x_parents, 0x120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
+};
+
+/* INFRA FIXED DIV */
+static const struct mtk_fixed_factor infracfg_mtk_fixed_factor[] = {
+ TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_INFRA_F26M_SEL, 1,
+ 1),
+ TOP_FACTOR(CK_INFRA_PWM_O, "infra_pwm_o", CK_TOP_PWM_SEL, 1, 1),
+ TOP_FACTOR(CK_INFRA_PCIE_OCC_P0, "infra_pcie_ck_occ_p0",
+ CK_TOP_PEXTP_TL_SEL, 1, 1),
+ TOP_FACTOR(CK_INFRA_PCIE_OCC_P1, "infra_pcie_ck_occ_p1",
+ CK_TOP_PEXTP_TL_P1_SEL, 1, 1),
+ TOP_FACTOR(CK_INFRA_PCIE_OCC_P2, "infra_pcie_ck_occ_p2",
+ CK_TOP_PEXTP_TL_P2_SEL, 1, 1),
+ TOP_FACTOR(CK_INFRA_PCIE_OCC_P3, "infra_pcie_ck_occ_p3",
+ CK_TOP_PEXTP_TL_P3_SEL, 1, 1),
+ TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
+ INFRA_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_INFRA_133M_HCK,
+ 1, 1),
+ INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
+ 1),
+ TOP_FACTOR(CK_INFRA_FAUD_L_O, "infra_faud_l_o", CK_TOP_AUD_L, 1, 1),
+ TOP_FACTOR(CK_INFRA_FAUD_AUD_O, "infra_faud_aud_o", CK_TOP_A1SYS, 1, 1),
+ TOP_FACTOR(CK_INFRA_FAUD_EG2_O, "infra_faud_eg2_o", CK_TOP_A_TUNER, 1,
+ 1),
+ TOP_FACTOR(CK_INFRA_I2C_O, "infra_i2c_o", CK_TOP_I2C_BCK, 1, 1),
+ TOP_FACTOR(CK_INFRA_UART_O0, "infra_uart_o0", CK_TOP_UART_SEL, 1, 1),
+ TOP_FACTOR(CK_INFRA_UART_O1, "infra_uart_o1", CK_TOP_UART_SEL, 1, 1),
+ TOP_FACTOR(CK_INFRA_UART_O2, "infra_uart_o2", CK_TOP_UART_SEL, 1, 1),
+ TOP_FACTOR(CK_INFRA_NFI_O, "infra_nfi_o", CK_TOP_NFI1X, 1, 1),
+ TOP_FACTOR(CK_INFRA_SPINFI_O, "infra_spinfi_o", CK_TOP_SPINFI_BCK, 1,
+ 1),
+ TOP_FACTOR(CK_INFRA_SPI0_O, "infra_spi0_o", CK_TOP_SPI, 1, 1),
+ TOP_FACTOR(CK_INFRA_SPI1_O, "infra_spi1_o", CK_TOP_SPIM_MST, 1, 1),
+ INFRA_FACTOR(CK_INFRA_LB_MUX_FRTC, "infra_lb_mux_frtc", CK_INFRA_FRTC,
+ 1, 1),
+ TOP_FACTOR(CK_INFRA_FRTC, "infra_frtc", CK_TOP_CB_RTC_32K, 1, 1),
+ TOP_FACTOR(CK_INFRA_FMSDC400_O, "infra_fmsdc400_o", CK_TOP_EMMC_400M, 1,
+ 1),
+ TOP_FACTOR(CK_INFRA_FMSDC2_HCK_OCC, "infra_fmsdc2_hck_occ",
+ CK_TOP_EMMC_250M, 1, 1),
+ TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
+ TOP_FACTOR(CK_INFRA_USB_O, "infra_usb_o", CK_TOP_USB_REF, 1, 1),
+ TOP_FACTOR(CK_INFRA_USB_O_P1, "infra_usb_o_p1", CK_TOP_USB_CK_P1, 1, 1),
+ TOP_FACTOR(CK_INFRA_USB_FRMCNT_O, "infra_usb_frmcnt_o",
+ CK_TOP_USB_FRMCNT, 1, 1),
+ TOP_FACTOR(CK_INFRA_USB_FRMCNT_O_P1, "infra_usb_frmcnt_o_p1",
+ CK_TOP_USB_FRMCNT_P1, 1, 1),
+ TOP_FACTOR(CK_INFRA_USB_XHCI_O, "infra_usb_xhci_o", CK_TOP_USB_XHCI, 1,
+ 1),
+ TOP_FACTOR(CK_INFRA_USB_XHCI_O_P1, "infra_usb_xhci_o_p1",
+ CK_TOP_USB_XHCI_P1, 1, 1),
+ XTAL_FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", CLK_XTAL, 1, 1),
+ XTAL_FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", CLK_XTAL, 1,
+ 1),
+ XTAL_FACTOR(CK_INFRA_USB_UTMI_O, "infra_usb_utmi_o", CLK_XTAL, 1, 1),
+ XTAL_FACTOR(CK_INFRA_USB_UTMI_O_P1, "infra_usb_utmi_o_p1", CLK_XTAL, 1,
+ 1),
+ XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P0, "infra_pcie_pipe_ck_occ_p0",
+ CLK_XTAL, 1, 1),
+ XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P1, "infra_pcie_pipe_ck_occ_p1",
+ CLK_XTAL, 1, 1),
+ XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P2, "infra_pcie_pipe_ck_occ_p2",
+ CLK_XTAL, 1, 1),
+ XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P3, "infra_pcie_pipe_ck_occ_p3",
+ CLK_XTAL, 1, 1),
+ TOP_FACTOR(CK_INFRA_F26M_O0, "infra_f26m_o0", CK_TOP_INFRA_F26M, 1, 1),
+ TOP_FACTOR(CK_INFRA_F26M_O1, "infra_f26m_o1", CK_TOP_INFRA_F26M, 1, 1),
+ TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1),
+ TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI, 1, 1),
+ TOP_FACTOR(CK_INFRA_PERI_66M_O, "infra_peri_66m_o", CK_TOP_SYSAXI, 1,
+ 1),
+ TOP_FACTOR(CK_INFRA_USB_SYS_O, "infra_usb_sys_o", CK_TOP_USB_SYS, 1, 1),
+ TOP_FACTOR(CK_INFRA_USB_SYS_O_P1, "infra_usb_sys_o_p1",
+ CK_TOP_USB_SYS_P1, 1, 1),
+};
+
+/* INFRASYS MUX PARENTS */
+static const int infra_mux_uart0_parents[] = { CK_INFRA_CK_F26M,
+ CK_INFRA_UART_O0 };
+
+static const int infra_mux_uart1_parents[] = { CK_INFRA_CK_F26M,
+ CK_INFRA_UART_O1 };
+
+static const int infra_mux_uart2_parents[] = { CK_INFRA_CK_F26M,
+ CK_INFRA_UART_O2 };
+
+static const int infra_mux_spi0_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI0_O };
+
+static const int infra_mux_spi1_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI1_O };
+
+static const int infra_pwm_bck_parents[] = { CK_TOP_INFRA_F32K,
+ CK_INFRA_CK_F26M, CK_INFRA_66M_MCK,
+ CK_INFRA_PWM_O };
+
+static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = {
+ CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
+ CK_INFRA_PCIE_OCC_P0
+};
+
+static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = {
+ CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
+ CK_INFRA_PCIE_OCC_P1
+};
+
+static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = {
+ CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
+ CK_INFRA_PCIE_OCC_P2
+};
+
+static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
+ CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
+ CK_INFRA_PCIE_OCC_P3
+};
+
+#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
+ { \
+ .id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \
+ .mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \
+ .mux_mask = BIT(_width) - 1, .parent = _parents, \
+ .num_parents = ARRAY_SIZE(_parents), \
+ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \
+ }
+
+/* INFRA MUX */
+static const struct mtk_composite infracfg_mtk_mux[] = {
+ INFRA_MUX(CK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
+ infra_mux_uart0_parents, 0x10, 0, 1),
+ INFRA_MUX(CK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
+ infra_mux_uart1_parents, 0x10, 1, 1),
+ INFRA_MUX(CK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
+ infra_mux_uart2_parents, 0x10, 2, 1),
+ INFRA_MUX(CK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
+ infra_mux_spi0_parents, 0x10, 4, 1),
+ INFRA_MUX(CK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
+ infra_mux_spi1_parents, 0x10, 5, 1),
+ INFRA_MUX(CK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
+ infra_mux_spi0_parents, 0x10, 6, 1),
+ INFRA_MUX(CK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents,
+ 0x10, 14, 2),
+ INFRA_MUX(CK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
+ infra_pwm_bck_parents, 0x10, 16, 2),
+ INFRA_MUX(CK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
+ infra_pwm_bck_parents, 0x10, 18, 2),
+ INFRA_MUX(CK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
+ infra_pwm_bck_parents, 0x10, 20, 2),
+ INFRA_MUX(CK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
+ infra_pwm_bck_parents, 0x10, 22, 2),
+ INFRA_MUX(CK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
+ infra_pwm_bck_parents, 0x10, 24, 2),
+ INFRA_MUX(CK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
+ infra_pwm_bck_parents, 0x10, 26, 2),
+ INFRA_MUX(CK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
+ infra_pwm_bck_parents, 0x10, 28, 2),
+ INFRA_MUX(CK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
+ infra_pwm_bck_parents, 0x10, 30, 2),
+ INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
+ "infra_pcie_gfmux_tl_o_p0_sel",
+ infra_pcie_gfmux_tl_ck_o_p0_parents, 0x20, 0, 2),
+ INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
+ "infra_pcie_gfmux_tl_o_p1_sel",
+ infra_pcie_gfmux_tl_ck_o_p1_parents, 0x20, 2, 2),
+ INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
+ "infra_pcie_gfmux_tl_o_p2_sel",
+ infra_pcie_gfmux_tl_ck_o_p2_parents, 0x20, 4, 2),
+ INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
+ "infra_pcie_gfmux_tl_o_p3_sel",
+ infra_pcie_gfmux_tl_ck_o_p3_parents, 0x20, 6, 2),
+};
+
+static const struct mtk_gate_regs infra_0_cg_regs = {
+ .set_ofs = 0x10,
+ .clr_ofs = 0x14,
+ .sta_ofs = 0x18,
+};
+
+static const struct mtk_gate_regs infra_1_cg_regs = {
+ .set_ofs = 0x40,
+ .clr_ofs = 0x44,
+ .sta_ofs = 0x48,
+};
+
+static const struct mtk_gate_regs infra_2_cg_regs = {
+ .set_ofs = 0x50,
+ .clr_ofs = 0x54,
+ .sta_ofs = 0x58,
+};
+
+static const struct mtk_gate_regs infra_3_cg_regs = {
+ .set_ofs = 0x60,
+ .clr_ofs = 0x64,
+ .sta_ofs = 0x68,
+};
+
+#define GATE_INFRA0(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ }
+
+#define GATE_INFRA1(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ }
+
+#define GATE_INFRA2(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ }
+
+#define GATE_INFRA3(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .parent = _parent, .regs = &infra_3_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ }
+
+/* INFRA GATE */
+static const struct mtk_gate infracfg_mtk_gates[] = {
+ GATE_INFRA1(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
+ CK_INFRA_66M_MCK, 0),
+ GATE_INFRA1(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
+ CK_INFRA_66M_MCK, 1),
+ GATE_INFRA1(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
+ CK_INFRA_PWM_SEL, 2),
+ GATE_INFRA1(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
+ CK_INFRA_PWM_CK1_SEL, 3),
+ GATE_INFRA1(CK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
+ CK_INFRA_PWM_CK2_SEL, 4),
+ GATE_INFRA1(CK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
+ CK_INFRA_PWM_CK3_SEL, 5),
+ GATE_INFRA1(CK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
+ CK_INFRA_PWM_CK4_SEL, 6),
+ GATE_INFRA1(CK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
+ CK_INFRA_PWM_CK5_SEL, 7),
+ GATE_INFRA1(CK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
+ CK_INFRA_PWM_CK6_SEL, 8),
+ GATE_INFRA1(CK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
+ CK_INFRA_PWM_CK7_SEL, 9),
+ GATE_INFRA1(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
+ CK_INFRA_PWM_CK8_SEL, 10),
+ GATE_INFRA1(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
+ CK_INFRA_133M_MCK, 12),
+ GATE_INFRA1(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
+ CK_INFRA_66M_PHCK, 13),
+ GATE_INFRA1(CK_INFRA_AUD_26M, "infra_f_faud_26m", CK_INFRA_CK_F26M, 14),
+ GATE_INFRA1(CK_INFRA_AUD_L, "infra_f_faud_l", CK_INFRA_FAUD_L_O, 15),
+ GATE_INFRA1(CK_INFRA_AUD_AUD, "infra_f_aud_aud", CK_INFRA_FAUD_AUD_O,
+ 16),
+ GATE_INFRA1(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", CK_INFRA_FAUD_EG2_O,
+ 18),
+ GATE_INFRA1(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CK_INFRA_CK_F26M,
+ 19),
+ GATE_INFRA1(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
+ CK_INFRA_133M_MCK, 20),
+ GATE_INFRA1(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
+ CK_INFRA_66M_MCK, 21),
+ GATE_INFRA1(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
+ CK_INFRA_66M_MCK, 29),
+ GATE_INFRA1(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
+ CK_INFRA_CK_F26M, 30),
+ GATE_INFRA1(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_INFRA_PERI_66M_O,
+ 31),
+ GATE_INFRA2(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
+ CK_INFRA_CK_F26M, 0),
+ GATE_INFRA2(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_INFRA_I2C_O, 1),
+ GATE_INFRA2(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
+ CK_INFRA_66M_MCK, 3),
+ GATE_INFRA2(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
+ CK_INFRA_66M_MCK, 4),
+ GATE_INFRA2(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
+ CK_INFRA_66M_MCK, 5),
+ GATE_INFRA2(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
+ CK_INFRA_MUX_UART0_SEL, 3),
+ GATE_INFRA2(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
+ CK_INFRA_MUX_UART1_SEL, 4),
+ GATE_INFRA2(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
+ CK_INFRA_MUX_UART2_SEL, 5),
+ GATE_INFRA2(CK_INFRA_NFI, "infra_f_fnfi", CK_INFRA_NFI_O, 9),
+ GATE_INFRA2(CK_INFRA_SPINFI, "infra_f_fspinfi", CK_INFRA_SPINFI_O, 10),
+ GATE_INFRA2(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
+ CK_INFRA_66M_MCK, 11),
+ GATE_INFRA2(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
+ CK_INFRA_MUX_SPI0_SEL, 12),
+ GATE_INFRA2(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
+ CK_INFRA_MUX_SPI1_SEL, 13),
+ GATE_INFRA2(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
+ CK_INFRA_MUX_SPI2_SEL, 14),
+ GATE_INFRA2(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
+ CK_INFRA_66M_MCK, 15),
+ GATE_INFRA2(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
+ CK_INFRA_66M_MCK, 16),
+ GATE_INFRA2(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
+ CK_INFRA_66M_MCK, 17),
+ GATE_INFRA2(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
+ CK_INFRA_66M_MCK, 18),
+ GATE_INFRA2(CK_INFRA_RTC, "infra_f_frtc", CK_INFRA_LB_MUX_FRTC, 19),
+ GATE_INFRA2(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
+ CK_INFRA_F26M_O1, 20),
+ GATE_INFRA2(CK_INFRA_RC_ADC, "infra_f_frc_adc", CK_INFRA_26M_ADC_BCK,
+ 21),
+ GATE_INFRA2(CK_INFRA_MSDC400, "infra_f_fmsdc400", CK_INFRA_FMSDC400_O,
+ 22),
+ GATE_INFRA2(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
+ CK_INFRA_FMSDC2_HCK_OCC, 23),
+ GATE_INFRA2(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
+ CK_INFRA_PERI_133M, 24),
+ GATE_INFRA2(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
+ CK_INFRA_66M_PHCK, 25),
+ GATE_INFRA2(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
+ CK_INFRA_133M_MCK, 26),
+ GATE_INFRA2(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CK_INFRA_NFI_O,
+ 27),
+ GATE_INFRA2(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
+ CK_INFRA_133M_MCK, 29),
+ GATE_INFRA2(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
+ CK_INFRA_66M_PHCK, 31),
+ GATE_INFRA3(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
+ CK_INFRA_133M_PHCK, 0),
+ GATE_INFRA3(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
+ CK_INFRA_133M_PHCK, 1),
+ GATE_INFRA3(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck",
+ CK_INFRA_66M_PHCK, 2),
+ GATE_INFRA3(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
+ CK_INFRA_66M_PHCK, 3),
+ GATE_INFRA3(CK_INFRA_USB_SYS, "infra_usb_sys", CK_INFRA_USB_SYS_O, 4),
+ GATE_INFRA3(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
+ CK_INFRA_USB_SYS_O_P1, 5),
+ GATE_INFRA3(CK_INFRA_USB_REF, "infra_usb_ref", CK_INFRA_USB_O, 6),
+ GATE_INFRA3(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CK_INFRA_USB_O_P1,
+ 7),
+ GATE_INFRA3(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
+ CK_INFRA_USB_FRMCNT_O, 8),
+ GATE_INFRA3(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
+ CK_INFRA_USB_FRMCNT_O_P1, 9),
+ GATE_INFRA3(CK_INFRA_USB_PIPE, "infra_usb_pipe", CK_INFRA_USB_PIPE_O,
+ 10),
+ GATE_INFRA3(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
+ CK_INFRA_USB_PIPE_O_P1, 11),
+ GATE_INFRA3(CK_INFRA_USB_UTMI, "infra_usb_utmi", CK_INFRA_USB_UTMI_O,
+ 12),
+ GATE_INFRA3(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
+ CK_INFRA_USB_UTMI_O_P1, 13),
+ GATE_INFRA3(CK_INFRA_USB_XHCI, "infra_usb_xhci", CK_INFRA_USB_XHCI_O,
+ 14),
+ GATE_INFRA3(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
+ CK_INFRA_USB_XHCI_O_P1, 15),
+ GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
+ CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20),
+ GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
+ CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21),
+ GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
+ CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22),
+ GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
+ CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23),
+ GATE_INFRA3(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
+ CK_INFRA_PCIE_PIPE_OCC_P0, 24),
+ GATE_INFRA3(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
+ CK_INFRA_PCIE_PIPE_OCC_P1, 25),
+ GATE_INFRA3(CK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
+ CK_INFRA_PCIE_PIPE_OCC_P2, 26),
+ GATE_INFRA3(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
+ CK_INFRA_PCIE_PIPE_OCC_P3, 27),
+ GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
+ CK_INFRA_133M_PHCK, 28),
+ GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
+ CK_INFRA_133M_PHCK, 29),
+ GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
+ CK_INFRA_133M_PHCK, 30),
+ GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
+ CK_INFRA_133M_PHCK, 31),
+ GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P0,
+ "infra_pcie_peri_ck_26m_ck_p0", CK_INFRA_F26M_O0, 7),
+ GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1,
+ "infra_pcie_peri_ck_26m_ck_p1", CK_INFRA_F26M_O0, 8),
+ GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P2,
+ "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_F26M_O0, 9),
+ GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P3,
+ "infra_pcie_peri_ck_26m_ck_p3", CK_INFRA_F26M_O0, 10),
+};
+
+static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
+ .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls),
+ .fclks = apmixedsys_mtk_plls,
+ .xtal_rate = 40 * MHZ,
+};
+
+static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
+ .fdivs_offs = CK_TOP_CB_CKSQ_40M,
+ .muxes_offs = CK_TOP_NETSYS_SEL,
+ .fdivs = topckgen_mtk_fixed_factors,
+ .muxes = topckgen_mtk_muxes,
+ .flags = CLK_BYPASS_XTAL,
+ .xtal_rate = 40 * MHZ,
+};
+
+static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
+ .fdivs_offs = CK_INFRA_CK_F26M,
+ .muxes_offs = CK_INFRA_MUX_UART0_SEL,
+ .fdivs = infracfg_mtk_fixed_factor,
+ .muxes = infracfg_mtk_mux,
+ .flags = CLK_BYPASS_XTAL,
+ .xtal_rate = 40 * MHZ,
+};
+
+static const struct udevice_id mt7988_fixed_pll_compat[] = {
+ { .compatible = "mediatek,mt7988-fixed-plls" },
+ {}
+};
+
+static const struct udevice_id mt7988_topckgen_compat[] = {
+ { .compatible = "mediatek,mt7988-topckgen" },
+ {}
+};
+
+static int mt7988_fixed_pll_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt7988_fixed_pll_clk_tree);
+}
+
+static int mt7988_topckgen_probe(struct udevice *dev)
+{
+ struct mtk_clk_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+
+ writel(MT7988_CLK_PDN_EN_WRITE, priv->base + MT7988_CLK_PDN);
+ return mtk_common_clk_init(dev, &mt7988_topckgen_clk_tree);
+}
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ .name = "mt7988-clock-fixed-pll",
+ .id = UCLASS_CLK,
+ .of_match = mt7988_fixed_pll_compat,
+ .probe = mt7988_fixed_pll_probe,
+ .priv_auto = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_topckgen_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+ .name = "mt7988-clock-topckgen",
+ .id = UCLASS_CLK,
+ .of_match = mt7988_topckgen_compat,
+ .probe = mt7988_topckgen_probe,
+ .priv_auto = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_topckgen_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+static const struct udevice_id mt7988_infracfg_compat[] = {
+ { .compatible = "mediatek,mt7988-infracfg" },
+ {}
+};
+
+static const struct udevice_id mt7988_infracfg_ao_cgs_compat[] = {
+ { .compatible = "mediatek,mt7988-infracfg_ao_cgs" },
+ {}
+};
+
+static int mt7988_infracfg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt7988_infracfg_clk_tree);
+}
+
+static int mt7988_infracfg_ao_cgs_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7988_infracfg_clk_tree,
+ infracfg_mtk_gates);
+}
+
+U_BOOT_DRIVER(mtk_clk_infracfg) = {
+ .name = "mt7988-clock-infracfg",
+ .id = UCLASS_CLK,
+ .of_match = mt7988_infracfg_compat,
+ .probe = mt7988_infracfg_probe,
+ .priv_auto = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_infrasys_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_infracfg_ao_cgs) = {
+ .name = "mt7988-clock-infracfg_ao_cgs",
+ .id = UCLASS_CLK,
+ .of_match = mt7988_infracfg_ao_cgs_compat,
+ .probe = mt7988_infracfg_ao_cgs_probe,
+ .priv_auto = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+/* ETHDMA */
+
+static const struct mtk_gate_regs ethdma_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+#define GATE_ETHDMA(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .parent = _parent, .regs = ðdma_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate ethdma_mtk_gate[] = {
+ GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", CK_TOP_NETSYS_2X, 6),
+};
+
+static int mt7988_ethdma_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
+ ethdma_mtk_gate);
+}
+
+static int mt7988_ethdma_bind(struct udevice *dev)
+{
+ int ret = 0;
+
+ if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
+ ret = mediatek_reset_bind(dev, MT7988_ETHDMA_RST_CTRL_OFS, 1);
+ if (ret)
+ debug("Warning: failed to bind reset controller\n");
+ }
+
+ return ret;
+}
+
+static const struct udevice_id mt7988_ethdma_compat[] = {
+ {
+ .compatible = "mediatek,mt7988-ethdma",
+ },
+ {}
+};
+
+U_BOOT_DRIVER(mtk_clk_ethdma) = {
+ .name = "mt7988-clock-ethdma",
+ .id = UCLASS_CLK,
+ .of_match = mt7988_ethdma_compat,
+ .probe = mt7988_ethdma_probe,
+ .bind = mt7988_ethdma_bind,
+ .priv_auto = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
+
+/* SGMIISYS_0 */
+
+static const struct mtk_gate_regs sgmii0_cg_regs = {
+ .set_ofs = 0xE4,
+ .clr_ofs = 0xE4,
+ .sta_ofs = 0xE4,
+};
+
+#define GATE_SGMII0(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .parent = _parent, .regs = &sgmii0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate sgmiisys_0_mtk_gate[] = {
+ /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
+ GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", CK_TOP_CB_CKSQ_40M, 2),
+ /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
+ GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", CK_TOP_CB_CKSQ_40M, 3),
+};
+
+static int mt7988_sgmiisys_0_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
+ sgmiisys_0_mtk_gate);
+}
+
+static const struct udevice_id mt7988_sgmiisys_0_compat[] = {
+ {
+ .compatible = "mediatek,mt7988-sgmiisys_0",
+ },
+ {}
+};
+
+U_BOOT_DRIVER(mtk_clk_sgmiisys_0) = {
+ .name = "mt7988-clock-sgmiisys_0",
+ .id = UCLASS_CLK,
+ .of_match = mt7988_sgmiisys_0_compat,
+ .probe = mt7988_sgmiisys_0_probe,
+ .priv_auto = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
+
+/* SGMIISYS_1 */
+
+static const struct mtk_gate_regs sgmii1_cg_regs = {
+ .set_ofs = 0xE4,
+ .clr_ofs = 0xE4,
+ .sta_ofs = 0xE4,
+};
+
+#define GATE_SGMII1(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .parent = _parent, .regs = &sgmii1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate sgmiisys_1_mtk_gate[] = {
+ /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
+ GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", CK_TOP_CB_CKSQ_40M, 2),
+ /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
+ GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", CK_TOP_CB_CKSQ_40M, 3),
+};
+
+static int mt7988_sgmiisys_1_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
+ sgmiisys_1_mtk_gate);
+}
+
+static const struct udevice_id mt7988_sgmiisys_1_compat[] = {
+ {
+ .compatible = "mediatek,mt7988-sgmiisys_1",
+ },
+ {}
+};
+
+U_BOOT_DRIVER(mtk_clk_sgmiisys_1) = {
+ .name = "mt7988-clock-sgmiisys_1",
+ .id = UCLASS_CLK,
+ .of_match = mt7988_sgmiisys_1_compat,
+ .probe = mt7988_sgmiisys_1_probe,
+ .priv_auto = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
+
+/* ETHWARP */
+
+static const struct mtk_gate_regs ethwarp_cg_regs = {
+ .set_ofs = 0x14,
+ .clr_ofs = 0x14,
+ .sta_ofs = 0x14,
+};
+
+#define GATE_ETHWARP(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .parent = _parent, .regs = ðwarp_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate ethwarp_mtk_gate[] = {
+ GATE_ETHWARP(CK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
+ CK_TOP_NETSYS_WED_MCU, 13),
+ GATE_ETHWARP(CK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
+ CK_TOP_NETSYS_WED_MCU, 14),
+ GATE_ETHWARP(CK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
+ CK_TOP_NETSYS_WED_MCU, 15),
+};
+
+static int mt7988_ethwarp_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
+ ethwarp_mtk_gate);
+}
+
+static int mt7988_ethwarp_bind(struct udevice *dev)
+{
+ int ret = 0;
+
+ if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
+ ret = mediatek_reset_bind(dev, MT7988_ETHWARP_RST_CTRL_OFS, 2);
+ if (ret)
+ debug("Warning: failed to bind reset controller\n");
+ }
+
+ return ret;
+}
+
+static const struct udevice_id mt7988_ethwarp_compat[] = {
+ {
+ .compatible = "mediatek,mt7988-ethwarp",
+ },
+ {}
+};
+
+U_BOOT_DRIVER(mtk_clk_ethwarp) = {
+ .name = "mt7988-clock-ethwarp",
+ .id = UCLASS_CLK,
+ .of_match = mt7988_ethwarp_compat,
+ .probe = mt7988_ethwarp_probe,
+ .bind = mt7988_ethwarp_bind,
+ .priv_auto = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index c8a5512..0d274bb 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -526,6 +526,7 @@
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
+ .flags = DM_FLAG_OS_PREPARE | DM_FLAG_VITAL,
};
static int gen3_reset_assert(struct reset_ctl *reset_ctl)
@@ -565,6 +566,7 @@
.name = "rst_gen3",
.id = UCLASS_RESET,
.ops = &rst_gen3_ops,
+ .flags = DM_FLAG_OS_PREPARE | DM_FLAG_VITAL,
};
int gen3_cpg_bind(struct udevice *parent)
diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c
index 64f3358..d0a3f65 100644
--- a/drivers/clk/rockchip/clk_rk3308.c
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -150,7 +150,7 @@
}
con = readl(&cru->clksel_con[con_id]);
- div = con >> CLK_I2C_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
+ div = (con & CLK_I2C_DIV_CON_MASK) >> CLK_I2C_DIV_CON_SHIFT;
return DIV_TO_RATE(priv->dpll_hz, div);
}
@@ -314,7 +314,7 @@
u32 div, con;
con = readl(&cru->clksel_con[34]);
- div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK;
+ div = (con & CLK_SARADC_DIV_CON_MASK) >> CLK_SARADC_DIV_CON_SHIFT;
return DIV_TO_RATE(OSC_HZ, div);
}
@@ -342,7 +342,7 @@
u32 div, con;
con = readl(&cru->clksel_con[33]);
- div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK;
+ div = (con & CLK_SARADC_DIV_CON_MASK) >> CLK_SARADC_DIV_CON_SHIFT;
return DIV_TO_RATE(OSC_HZ, div);
}
@@ -385,7 +385,7 @@
}
con = readl(&cru->clksel_con[con_id]);
- div = con >> CLK_SPI_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK;
+ div = (con & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT;
return DIV_TO_RATE(priv->dpll_hz, div);
}
@@ -429,7 +429,7 @@
u32 div, con;
con = readl(&cru->clksel_con[29]);
- div = con >> CLK_PWM_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK;
+ div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT;
return DIV_TO_RATE(priv->dpll_hz, div);
}
@@ -451,6 +451,58 @@
return rk3308_pwm_get_clk(clk);
}
+static ulong rk3308_uart_get_clk(struct clk *clk)
+{
+ struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk3308_cru *cru = priv->cru;
+ u32 div, pll_sel, con, con_id, parent;
+
+ switch (clk->id) {
+ case SCLK_UART0:
+ con_id = 10;
+ break;
+ case SCLK_UART1:
+ con_id = 13;
+ break;
+ case SCLK_UART2:
+ con_id = 16;
+ break;
+ case SCLK_UART3:
+ con_id = 19;
+ break;
+ case SCLK_UART4:
+ con_id = 22;
+ break;
+ default:
+ printf("do not support this uart interface\n");
+ return -EINVAL;
+ }
+
+ con = readl(&cru->clksel_con[con_id]);
+ pll_sel = (con & CLK_UART_PLL_SEL_MASK) >> CLK_UART_PLL_SEL_SHIFT;
+ div = (con & CLK_UART_DIV_CON_MASK) >> CLK_UART_DIV_CON_SHIFT;
+
+ switch (pll_sel) {
+ case CLK_UART_PLL_SEL_DPLL:
+ parent = priv->dpll_hz;
+ break;
+ case CLK_UART_PLL_SEL_VPLL0:
+ parent = priv->vpll0_hz;
+ break;
+ case CLK_UART_PLL_SEL_VPLL1:
+ parent = priv->vpll0_hz;
+ break;
+ case CLK_UART_PLL_SEL_24M:
+ parent = OSC_HZ;
+ break;
+ default:
+ printf("do not support this uart pll sel\n");
+ return -EINVAL;
+ }
+
+ return DIV_TO_RATE(parent, div);
+}
+
static ulong rk3308_vop_get_clk(struct clk *clk)
{
struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
@@ -813,6 +865,13 @@
case SCLK_EMMC_SAMPLE:
rate = rk3308_mmc_get_clk(clk);
break;
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_UART3:
+ case SCLK_UART4:
+ rate = rk3308_uart_get_clk(clk);
+ break;
case SCLK_I2C0:
case SCLK_I2C1:
case SCLK_I2C2:
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
index 0df82f5..599b7b1 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -702,7 +702,10 @@
}
div = DIV_ROUND_UP(priv->cpll_hz, rate);
- assert(div - 1 <= 31);
+ if (clk_id == CPLL_25M)
+ assert(div - 1 <= 63);
+ else
+ assert(div - 1 <= 31);
rk_clrsetreg(&cru->clksel_con[con],
mask, (div - 1) << shift);
return rk3568_cpll_div_get_rate(priv, clk_id);
@@ -1142,7 +1145,7 @@
switch (clk_id) {
case CLK_PWM1:
- sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;
+ sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;
break;
case CLK_PWM2:
sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;
@@ -2186,6 +2189,7 @@
return rk3568_rkvdec_get_clk(priv, clk_id);
}
+#endif
static ulong rk3568_uart_get_rate(struct rk3568_clk_priv *priv, ulong clk_id)
{
@@ -2321,7 +2325,6 @@
return rk3568_uart_get_rate(priv, clk_id);
}
-#endif
static ulong rk3568_clk_get_rate(struct clk *clk)
{
@@ -2460,6 +2463,7 @@
case TCLK_WDT_NS:
rate = OSC_HZ;
break;
+#endif
case SCLK_UART1:
case SCLK_UART2:
case SCLK_UART3:
@@ -2471,7 +2475,6 @@
case SCLK_UART9:
rate = rk3568_uart_get_rate(priv, clk->id);
break;
-#endif
case ACLK_SECURE_FLASH:
case ACLK_CRYPTO_NS:
case HCLK_SECURE_FLASH:
@@ -2645,6 +2648,7 @@
case TCLK_WDT_NS:
ret = OSC_HZ;
break;
+#endif
case SCLK_UART1:
case SCLK_UART2:
case SCLK_UART3:
@@ -2656,7 +2660,6 @@
case SCLK_UART9:
ret = rk3568_uart_set_rate(priv, clk->id, rate);
break;
-#endif
case ACLK_SECURE_FLASH:
case ACLK_CRYPTO_NS:
case HCLK_SECURE_FLASH:
@@ -2840,6 +2843,10 @@
case CLK_RKVDEC_CORE:
return rk3568_rkvdec_set_parent(clk, parent);
case I2S1_MCLKOUT_TX:
+ case SCLK_GMAC0_RGMII_SPEED:
+ case SCLK_GMAC0_RMII_SPEED:
+ case SCLK_GMAC1_RGMII_SPEED:
+ case SCLK_GMAC1_RMII_SPEED:
break;
default:
return -ENOENT;
diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c
index 4f4524f..6150287 100644
--- a/drivers/clk/stm32/clk-stm32mp1.c
+++ b/drivers/clk/stm32/clk-stm32mp1.c
@@ -881,7 +881,8 @@
return sel[s].parent[p];
}
- log_err("no parents defined for clk id %d\n", (u32)id);
+ /* clock is DISABLED when the clock src is not in clk_parent[] range */
+ log_debug("no parents defined for clk id %d\n", (u32)id);
return -EINVAL;
}
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 6e26b64..60f8d67 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -598,9 +598,10 @@
ret = device_notify(dev, EVT_DM_POST_PROBE);
if (ret)
- return ret;
+ goto fail_event;
return 0;
+fail_event:
fail_uclass:
if (device_remove(dev, DM_REMOVE_NORMAL)) {
dm_warn("%s: Device '%s' failed to remove on error path\n",
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 8df16e5..a4dc9bd 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -103,7 +103,7 @@
if (gd->flags & GD_FLG_RELOC) {
uint i = OFTREE_TREE_ID(node.of_offset);
- if (i > oftree_count) {
+ if (i >= oftree_count) {
log_debug("Invalid tree ID %x\n", i);
return NULL;
}
diff --git a/drivers/ddr/imx/phy/helper.c b/drivers/ddr/imx/phy/helper.c
index 8cd4387..855a874 100644
--- a/drivers/ddr/imx/phy/helper.c
+++ b/drivers/ddr/imx/phy/helper.c
@@ -46,13 +46,13 @@
u32 error = 0;
unsigned long pr_to32, pr_from32;
uint32_t fw_offset = type ? IMEM_2D_OFFSET : 0;
- unsigned long imem_start = (unsigned long)&_end + fw_offset;
+ unsigned long imem_start = (unsigned long)_end + fw_offset;
unsigned long dmem_start;
unsigned long imem_len = IMEM_LEN, dmem_len = DMEM_LEN;
#ifdef CONFIG_SPL_OF_CONTROL
if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) {
- imem_start = roundup((unsigned long)&_end +
+ imem_start = roundup((unsigned long)_end +
fdt_totalsize(gd->fdt_blob), 4) +
fw_offset;
}
diff --git a/drivers/dma/ti/k3-psil-j721e.c b/drivers/dma/ti/k3-psil-j721e.c
index 105ffd9..8e57e86 100644
--- a/drivers/dma/ti/k3-psil-j721e.c
+++ b/drivers/dma/ti/k3-psil-j721e.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019-2023 Texas Instruments Incorporated - https://www.ti.com
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*/
@@ -21,13 +21,15 @@
/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
static struct psil_ep j721e_src_ep_map[] = {
- /* CPSW0 */
+ /* MCU_CPSW0 */
PSIL_ETHERNET(0x7000),
+ /* MAIN_CPSW0 */
+ PSIL_ETHERNET(0x4a00),
};
/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
static struct psil_ep j721e_dst_ep_map[] = {
- /* CPSW0 */
+ /* MCU_CPSW0 */
PSIL_ETHERNET(0xf000),
PSIL_ETHERNET(0xf001),
PSIL_ETHERNET(0xf002),
@@ -36,6 +38,15 @@
PSIL_ETHERNET(0xf005),
PSIL_ETHERNET(0xf006),
PSIL_ETHERNET(0xf007),
+ /* MAIN_CPSW0 */
+ PSIL_ETHERNET(0xca00),
+ PSIL_ETHERNET(0xca01),
+ PSIL_ETHERNET(0xca02),
+ PSIL_ETHERNET(0xca03),
+ PSIL_ETHERNET(0xca04),
+ PSIL_ETHERNET(0xca05),
+ PSIL_ETHERNET(0xca06),
+ PSIL_ETHERNET(0xca07),
};
struct psil_ep_map j721e_ep_map = {
diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
index a3df9aa..837c6f1 100644
--- a/drivers/fastboot/Kconfig
+++ b/drivers/fastboot/Kconfig
@@ -56,7 +56,7 @@
ROCKCHIP_RK3399
default 0x280000 if ROCKCHIP_RK3368
default 0x100000 if ARCH_ZYNQMP
- default 0 if SANDBOX
+ default 0x0 if SANDBOX
help
The fastboot protocol requires a large memory buffer for
downloads. Define this to the starting RAM address to use for
diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c
index dd3475e..d9f0f07 100644
--- a/drivers/fastboot/fb_getvar.c
+++ b/drivers/fastboot/fb_getvar.c
@@ -183,7 +183,7 @@
/* part_name_wslot = part_name + "_a" */
len = strlcpy(part_name_wslot, part_name, PART_NAME_LEN - 3);
- if (len > PART_NAME_LEN - 3)
+ if (len >= PART_NAME_LEN - 3)
goto fail;
strcat(part_name_wslot, "_a");
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
index eae1c8d..8789b1e 100644
--- a/drivers/firmware/Kconfig
+++ b/drivers/firmware/Kconfig
@@ -45,4 +45,5 @@
the PSCI driver is always probed and binds dirvers registered to the Arm SMCCC
services if any and reported as supported by the SMCCC firmware.
+source "drivers/firmware/arm-ffa/Kconfig"
source "drivers/firmware/scmi/Kconfig"
diff --git a/drivers/firmware/arm-ffa/Kconfig b/drivers/firmware/arm-ffa/Kconfig
new file mode 100644
index 0000000..d75f8b5
--- /dev/null
+++ b/drivers/firmware/arm-ffa/Kconfig
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config ARM_FFA_TRANSPORT
+ bool "Enable Arm Firmware Framework for Armv8-A driver"
+ depends on DM && (ARM64 || SANDBOX)
+ select ARM_SMCCC if !SANDBOX
+ select ARM_SMCCC_FEATURES if !SANDBOX
+ imply CMD_ARMFFA
+ select LIB_UUID
+ select DEVRES
+ help
+ The Firmware Framework for Arm A-profile processors (FF-A)
+ describes interfaces (ABIs) that standardize communication
+ between the Secure World and Normal World leveraging TrustZone
+ technology.
+
+ The FF-A support in U-Boot is based on FF-A specification v1.0 and uses SMC32
+ calling convention.
+
+ FF-A specification:
+
+ https://developer.arm.com/documentation/den0077/a/?lang=en
+
+ In U-Boot FF-A design, FF-A is considered as a discoverable bus.
+ FF-A bus is discovered using ARM_SMCCC_FEATURES mechanism performed
+ by the PSCI driver.
+ The Secure World is considered as one entity to communicate with
+ using the FF-A bus.
+ FF-A communication is handled by one device and one instance (the bus).
+ The FF-A support on U-Boot takes care of all the interactions between Normal
+ world and Secure World.
+
+ Generic FF-A methods are implemented in the Uclass (arm-ffa-uclass.c).
+ Arm specific methods are implemented in the Arm driver (arm-ffa.c).
+
+ FF-A sandbox is provided to run FF-A under sandbox and allows to test the FF-A Uclass.
+ Sandbox support includes an emulator for Arm FF-A which emulates the FF-A side of
+ the Secure World and provides FF-A ABIs inspection methods (ffa-emul-uclass.c).
+ An FF-A sandbox driver is also provided for FF-A communication with the emulated
+ Secure World (sandbox_ffa.c).
+
+ For more details about the FF-A support, please refer to doc/arch/arm64.ffa.rst
diff --git a/drivers/firmware/arm-ffa/Makefile b/drivers/firmware/arm-ffa/Makefile
new file mode 100644
index 0000000..318123a
--- /dev/null
+++ b/drivers/firmware/arm-ffa/Makefile
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+#
+# Authors:
+# Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+
+# build the generic FF-A methods
+obj-y += arm-ffa-uclass.o
+ifeq ($(CONFIG_SANDBOX),y)
+# build the FF-A sandbox emulator and driver
+obj-y += ffa-emul-uclass.o sandbox_ffa.o
+else
+# build the Arm64 FF-A driver
+obj-y += arm-ffa.o
+endif
diff --git a/drivers/firmware/arm-ffa/arm-ffa-uclass.c b/drivers/firmware/arm-ffa/arm-ffa-uclass.c
new file mode 100644
index 0000000..8c17b19
--- /dev/null
+++ b/drivers/firmware/arm-ffa/arm-ffa-uclass.c
@@ -0,0 +1,1065 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+#include <common.h>
+#include <arm_ffa.h>
+#include <arm_ffa_priv.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <string.h>
+#include <uuid.h>
+#include <asm/global_data.h>
+#include <dm/device-internal.h>
+#include <dm/devres.h>
+#include <dm/root.h>
+#include <linux/errno.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Error mapping declarations */
+
+int ffa_to_std_errmap[MAX_NUMBER_FFA_ERR] = {
+ [NOT_SUPPORTED] = -EOPNOTSUPP,
+ [INVALID_PARAMETERS] = -EINVAL,
+ [NO_MEMORY] = -ENOMEM,
+ [BUSY] = -EBUSY,
+ [INTERRUPTED] = -EINTR,
+ [DENIED] = -EACCES,
+ [RETRY] = -EAGAIN,
+ [ABORTED] = -ECANCELED,
+};
+
+static struct ffa_abi_errmap err_msg_map[FFA_ERRMAP_COUNT] = {
+ [FFA_ID_TO_ERRMAP_ID(FFA_VERSION)] = {
+ {
+ [NOT_SUPPORTED] =
+ "NOT_SUPPORTED: A Firmware Framework implementation does not exist",
+ },
+ },
+ [FFA_ID_TO_ERRMAP_ID(FFA_ID_GET)] = {
+ {
+ [NOT_SUPPORTED] =
+ "NOT_SUPPORTED: This function is not implemented at this FF-A instance",
+ },
+ },
+ [FFA_ID_TO_ERRMAP_ID(FFA_FEATURES)] = {
+ {
+ [NOT_SUPPORTED] =
+ "NOT_SUPPORTED: FFA_RXTX_MAP is not implemented at this FF-A instance",
+ },
+ },
+ [FFA_ID_TO_ERRMAP_ID(FFA_PARTITION_INFO_GET)] = {
+ {
+ [NOT_SUPPORTED] =
+ "NOT_SUPPORTED: This function is not implemented at this FF-A instance",
+ [INVALID_PARAMETERS] =
+ "INVALID_PARAMETERS: Unrecognized UUID",
+ [NO_MEMORY] =
+ "NO_MEMORY: Results cannot fit in RX buffer of the caller",
+ [BUSY] =
+ "BUSY: RX buffer of the caller is not free",
+ [DENIED] =
+ "DENIED: Callee is not in a state to handle this request",
+ },
+ },
+ [FFA_ID_TO_ERRMAP_ID(FFA_RXTX_UNMAP)] = {
+ {
+ [NOT_SUPPORTED] =
+ "NOT_SUPPORTED: FFA_RXTX_UNMAP is not implemented at this FF-A instance",
+ [INVALID_PARAMETERS] =
+ "INVALID_PARAMETERS: No buffer pair registered on behalf of the caller",
+ },
+ },
+ [FFA_ID_TO_ERRMAP_ID(FFA_RX_RELEASE)] = {
+ {
+ [NOT_SUPPORTED] =
+ "NOT_SUPPORTED: FFA_RX_RELEASE is not implemented at this FF-A instance",
+ [DENIED] =
+ "DENIED: Caller did not have ownership of the RX buffer",
+ },
+ },
+ [FFA_ID_TO_ERRMAP_ID(FFA_RXTX_MAP)] = {
+ {
+ [NOT_SUPPORTED] =
+ "NOT_SUPPORTED: This function is not implemented at this FF-A instance",
+ [INVALID_PARAMETERS] =
+ "INVALID_PARAMETERS: Field(s) in input parameters incorrectly encoded",
+ [NO_MEMORY] =
+ "NO_MEMORY: Not enough memory",
+ [DENIED] =
+ "DENIED: Buffer pair already registered",
+ },
+ },
+};
+
+/**
+ * ffa_to_std_errno() - convert FF-A error code to standard error code
+ * @ffa_errno: Error code returned by the FF-A ABI
+ *
+ * Map the given FF-A error code as specified
+ * by the spec to a u-boot standard error code.
+ *
+ * Return:
+ *
+ * The standard error code on success. . Otherwise, failure
+ */
+static int ffa_to_std_errno(int ffa_errno)
+{
+ int err_idx = -ffa_errno;
+
+ /* Map the FF-A error code to the standard u-boot error code */
+ if (err_idx > 0 && err_idx < MAX_NUMBER_FFA_ERR)
+ return ffa_to_std_errmap[err_idx];
+ return -EINVAL;
+}
+
+/**
+ * ffa_print_error_log() - print the error log corresponding to the selected FF-A ABI
+ * @ffa_id: FF-A ABI ID
+ * @ffa_errno: Error code returned by the FF-A ABI
+ *
+ * Map the FF-A error code to the error log relevant to the
+ * selected FF-A ABI. Then the error log is printed.
+ *
+ * Return:
+ *
+ * 0 on success. . Otherwise, failure
+ */
+static int ffa_print_error_log(u32 ffa_id, int ffa_errno)
+{
+ int err_idx = -ffa_errno, abi_idx = 0;
+
+ /* Map the FF-A error code to the corresponding error log */
+
+ if (err_idx <= 0 || err_idx >= MAX_NUMBER_FFA_ERR)
+ return -EINVAL;
+
+ if (ffa_id < FFA_FIRST_ID || ffa_id > FFA_LAST_ID)
+ return -EINVAL;
+
+ abi_idx = FFA_ID_TO_ERRMAP_ID(ffa_id);
+ if (abi_idx < 0 || abi_idx >= FFA_ERRMAP_COUNT)
+ return -EINVAL;
+
+ if (!err_msg_map[abi_idx].err_str[err_idx])
+ return -EINVAL;
+
+ log_err("%s\n", err_msg_map[abi_idx].err_str[err_idx]);
+
+ return 0;
+}
+
+/* FF-A ABIs implementation (U-Boot side) */
+
+/**
+ * invoke_ffa_fn() - SMC wrapper
+ * @args: FF-A ABI arguments to be copied to Xn registers
+ * @res: FF-A ABI return data to be copied from Xn registers
+ *
+ * Calls low level SMC implementation.
+ * This function should be implemented by the user driver.
+ */
+void __weak invoke_ffa_fn(ffa_value_t args, ffa_value_t *res)
+{
+}
+
+/**
+ * ffa_get_version_hdlr() - FFA_VERSION handler function
+ * @dev: The FF-A bus device
+ *
+ * Implement FFA_VERSION FF-A function
+ * to get from the secure world the FF-A framework version
+ * FFA_VERSION is used to discover the FF-A framework.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int ffa_get_version_hdlr(struct udevice *dev)
+{
+ u16 major, minor;
+ ffa_value_t res = {0};
+ int ffa_errno;
+ struct ffa_priv *uc_priv;
+
+ invoke_ffa_fn((ffa_value_t){
+ .a0 = FFA_SMC_32(FFA_VERSION), .a1 = FFA_VERSION_1_0,
+ }, &res);
+
+ ffa_errno = res.a0;
+ if (ffa_errno < 0) {
+ ffa_print_error_log(FFA_VERSION, ffa_errno);
+ return ffa_to_std_errno(ffa_errno);
+ }
+
+ major = GET_FFA_MAJOR_VERSION(res.a0);
+ minor = GET_FFA_MINOR_VERSION(res.a0);
+
+ log_debug("FF-A driver %d.%d\nFF-A framework %d.%d\n",
+ FFA_MAJOR_VERSION, FFA_MINOR_VERSION, major, minor);
+
+ if (major == FFA_MAJOR_VERSION && minor >= FFA_MINOR_VERSION) {
+ log_debug("FF-A versions are compatible\n");
+
+ if (dev) {
+ uc_priv = dev_get_uclass_priv(dev);
+ if (uc_priv)
+ uc_priv->fwk_version = res.a0;
+ }
+
+ return 0;
+ }
+
+ log_err("versions are incompatible\nExpected: %d.%d , Found: %d.%d\n",
+ FFA_MAJOR_VERSION, FFA_MINOR_VERSION, major, minor);
+
+ return -EPROTONOSUPPORT;
+}
+
+/**
+ * ffa_get_endpoint_id() - FFA_ID_GET handler function
+ * @dev: The FF-A bus device
+ *
+ * Implement FFA_ID_GET FF-A function
+ * to get from the secure world u-boot endpoint ID
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int ffa_get_endpoint_id(struct udevice *dev)
+{
+ ffa_value_t res = {0};
+ int ffa_errno;
+ struct ffa_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ invoke_ffa_fn((ffa_value_t){
+ .a0 = FFA_SMC_32(FFA_ID_GET),
+ }, &res);
+
+ if (res.a0 == FFA_SMC_32(FFA_SUCCESS)) {
+ uc_priv->id = GET_SELF_ENDPOINT_ID((u32)res.a2);
+ log_debug("FF-A endpoint ID is %u\n", uc_priv->id);
+
+ return 0;
+ }
+
+ ffa_errno = res.a2;
+
+ ffa_print_error_log(FFA_ID_GET, ffa_errno);
+
+ return ffa_to_std_errno(ffa_errno);
+}
+
+/**
+ * ffa_set_rxtx_buffers_pages_cnt() - set the minimum number of pages in each of the RX/TX buffers
+ * @dev: The FF-A bus device
+ * @prop_field: properties field obtained from FFA_FEATURES ABI
+ *
+ * Set the minimum number of pages in each of the RX/TX buffers in uc_priv
+ *
+ * Return:
+ *
+ * rxtx_min_pages field contains the returned number of pages
+ * 0 on success. Otherwise, failure
+ */
+static int ffa_set_rxtx_buffers_pages_cnt(struct udevice *dev, u32 prop_field)
+{
+ struct ffa_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ switch (prop_field) {
+ case RXTX_4K:
+ uc_priv->pair.rxtx_min_pages = 1;
+ break;
+ case RXTX_16K:
+ uc_priv->pair.rxtx_min_pages = 4;
+ break;
+ case RXTX_64K:
+ uc_priv->pair.rxtx_min_pages = 16;
+ break;
+ default:
+ log_err("RX/TX buffer size not supported\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * ffa_get_rxtx_map_features_hdlr() - FFA_FEATURES handler function with FFA_RXTX_MAP argument
+ * @dev: The FF-A bus device
+ *
+ * Implement FFA_FEATURES FF-A function to retrieve the FFA_RXTX_MAP features
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int ffa_get_rxtx_map_features_hdlr(struct udevice *dev)
+{
+ ffa_value_t res = {0};
+ int ffa_errno;
+
+ invoke_ffa_fn((ffa_value_t){
+ .a0 = FFA_SMC_32(FFA_FEATURES),
+ .a1 = FFA_SMC_64(FFA_RXTX_MAP),
+ }, &res);
+
+ if (res.a0 == FFA_SMC_32(FFA_SUCCESS))
+ return ffa_set_rxtx_buffers_pages_cnt(dev, res.a2);
+
+ ffa_errno = res.a2;
+ ffa_print_error_log(FFA_FEATURES, ffa_errno);
+
+ return ffa_to_std_errno(ffa_errno);
+}
+
+/**
+ * ffa_free_rxtx_buffers() - free the RX/TX buffers
+ * @dev: The FF-A bus device
+ *
+ * Free the RX/TX buffers
+ */
+static void ffa_free_rxtx_buffers(struct udevice *dev)
+{
+ struct ffa_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ log_debug("Freeing FF-A RX/TX buffers\n");
+
+ if (uc_priv->pair.rxbuf) {
+ free(uc_priv->pair.rxbuf);
+ uc_priv->pair.rxbuf = NULL;
+ }
+
+ if (uc_priv->pair.txbuf) {
+ free(uc_priv->pair.txbuf);
+ uc_priv->pair.txbuf = NULL;
+ }
+}
+
+/**
+ * ffa_alloc_rxtx_buffers() - allocate the RX/TX buffers
+ * @dev: The FF-A bus device
+ *
+ * Used by ffa_map_rxtx_buffers to allocate
+ * the RX/TX buffers before mapping them. The allocated memory is physically
+ * contiguous since memalign ends up calling malloc which allocates
+ * contiguous memory in u-boot.
+ * The size of the memory allocated is the minimum allowed.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int ffa_alloc_rxtx_buffers(struct udevice *dev)
+{
+ u64 bytes;
+ struct ffa_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ log_debug("Using %lu 4KB page(s) for FF-A RX/TX buffers size\n",
+ uc_priv->pair.rxtx_min_pages);
+
+ bytes = uc_priv->pair.rxtx_min_pages * SZ_4K;
+
+ /*
+ * The alignment of the RX and TX buffers must be equal
+ * to the larger translation granule size
+ * Assumption: Memory allocated with memalign is always physically contiguous
+ */
+
+ uc_priv->pair.rxbuf = memalign(bytes, bytes);
+ if (!uc_priv->pair.rxbuf) {
+ log_err("failure to allocate RX buffer\n");
+ return -ENOBUFS;
+ }
+
+ log_debug("FF-A RX buffer at virtual address %p\n", uc_priv->pair.rxbuf);
+
+ uc_priv->pair.txbuf = memalign(bytes, bytes);
+ if (!uc_priv->pair.txbuf) {
+ free(uc_priv->pair.rxbuf);
+ uc_priv->pair.rxbuf = NULL;
+ log_err("failure to allocate the TX buffer\n");
+ return -ENOBUFS;
+ }
+
+ log_debug("FF-A TX buffer at virtual address %p\n", uc_priv->pair.txbuf);
+
+ /* Make sure the buffers are cleared before use */
+ memset(uc_priv->pair.rxbuf, 0, bytes);
+ memset(uc_priv->pair.txbuf, 0, bytes);
+
+ return 0;
+}
+
+/**
+ * ffa_map_rxtx_buffers_hdlr() - FFA_RXTX_MAP handler function
+ * @dev: The FF-A bus device
+ *
+ * Implement FFA_RXTX_MAP FF-A function to map the RX/TX buffers
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int ffa_map_rxtx_buffers_hdlr(struct udevice *dev)
+{
+ int ret;
+ ffa_value_t res = {0};
+ int ffa_errno;
+ struct ffa_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ ret = ffa_alloc_rxtx_buffers(dev);
+ if (ret)
+ return ret;
+
+ /*
+ * we need to pass the physical addresses of the RX/TX buffers
+ * in u-boot physical/virtual mapping is 1:1
+ * no need to convert from virtual to physical
+ */
+
+ invoke_ffa_fn((ffa_value_t){
+ .a0 = FFA_SMC_64(FFA_RXTX_MAP),
+ .a1 = map_to_sysmem(uc_priv->pair.txbuf),
+ .a2 = map_to_sysmem(uc_priv->pair.rxbuf),
+ .a3 = uc_priv->pair.rxtx_min_pages,
+ }, &res);
+
+ if (res.a0 == FFA_SMC_32(FFA_SUCCESS)) {
+ log_debug("FF-A RX/TX buffers mapped\n");
+ return 0;
+ }
+
+ ffa_errno = res.a2;
+ ffa_print_error_log(FFA_RXTX_MAP, ffa_errno);
+
+ ffa_free_rxtx_buffers(dev);
+
+ return ffa_to_std_errno(ffa_errno);
+}
+
+/**
+ * ffa_unmap_rxtx_buffers_hdlr() - FFA_RXTX_UNMAP handler function
+ * @dev: The FF-A bus device
+ *
+ * Implement FFA_RXTX_UNMAP FF-A function to unmap the RX/TX buffers
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int ffa_unmap_rxtx_buffers_hdlr(struct udevice *dev)
+{
+ ffa_value_t res = {0};
+ int ffa_errno;
+ struct ffa_priv *uc_priv;
+
+ log_debug("unmapping FF-A RX/TX buffers\n");
+
+ uc_priv = dev_get_uclass_priv(dev);
+
+ invoke_ffa_fn((ffa_value_t){
+ .a0 = FFA_SMC_32(FFA_RXTX_UNMAP),
+ .a1 = PREP_SELF_ENDPOINT_ID(uc_priv->id),
+ }, &res);
+
+ if (res.a0 == FFA_SMC_32(FFA_SUCCESS)) {
+ ffa_free_rxtx_buffers(dev);
+ return 0;
+ }
+
+ ffa_errno = res.a2;
+ ffa_print_error_log(FFA_RXTX_UNMAP, ffa_errno);
+
+ return ffa_to_std_errno(ffa_errno);
+}
+
+/**
+ * ffa_release_rx_buffer_hdlr() - FFA_RX_RELEASE handler function
+ * @dev: The FF-A bus device
+ *
+ * Invoke FFA_RX_RELEASE FF-A function to release the ownership of the RX buffer
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int ffa_release_rx_buffer_hdlr(struct udevice *dev)
+{
+ ffa_value_t res = {0};
+ int ffa_errno;
+
+ invoke_ffa_fn((ffa_value_t){
+ .a0 = FFA_SMC_32(FFA_RX_RELEASE),
+ }, &res);
+
+ if (res.a0 == FFA_SMC_32(FFA_SUCCESS))
+ return 0;
+
+ ffa_errno = res.a2;
+ ffa_print_error_log(FFA_RX_RELEASE, ffa_errno);
+
+ return ffa_to_std_errno(ffa_errno);
+}
+
+/**
+ * ffa_uuid_are_identical() - check whether two given UUIDs are identical
+ * @uuid1: first UUID
+ * @uuid2: second UUID
+ *
+ * Used by ffa_read_partitions_info to search for a UUID in the partitions descriptors table
+ *
+ * Return:
+ *
+ * 1 when UUIDs match. Otherwise, 0
+ */
+static bool ffa_uuid_are_identical(const struct ffa_partition_uuid *uuid1,
+ const struct ffa_partition_uuid *uuid2)
+{
+ if (!uuid1 || !uuid2)
+ return 0;
+
+ return !memcmp(uuid1, uuid2, sizeof(struct ffa_partition_uuid));
+}
+
+/**
+ * ffa_read_partitions_info() - read queried partition data
+ * @dev: The FF-A bus device
+ * @count: The number of partitions queried
+ * @part_uuid: Pointer to the partition(s) UUID
+ *
+ * Read the partitions information returned by the FFA_PARTITION_INFO_GET and saves it in uc_priv
+ *
+ * Return:
+ *
+ * uc_priv is updated with the partition(s) information
+ * 0 is returned on success. Otherwise, failure
+ */
+static int ffa_read_partitions_info(struct udevice *dev, u32 count,
+ struct ffa_partition_uuid *part_uuid)
+{
+ struct ffa_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ if (!count) {
+ log_err("no partition detected\n");
+ return -ENODATA;
+ }
+
+ log_debug("Reading FF-A partitions data from the RX buffer\n");
+
+ if (!part_uuid) {
+ /* Querying information of all partitions */
+ u64 buf_bytes;
+ u64 data_bytes;
+ u32 desc_idx;
+ struct ffa_partition_info *parts_info;
+
+ data_bytes = count * sizeof(struct ffa_partition_desc);
+
+ buf_bytes = uc_priv->pair.rxtx_min_pages * SZ_4K;
+
+ if (data_bytes > buf_bytes) {
+ log_err("partitions data size exceeds the RX buffer size:\n");
+ log_err(" sizes in bytes: data %llu , RX buffer %llu\n",
+ data_bytes,
+ buf_bytes);
+
+ return -ENOMEM;
+ }
+
+ uc_priv->partitions.descs = devm_kmalloc(dev, data_bytes, __GFP_ZERO);
+ if (!uc_priv->partitions.descs) {
+ log_err("cannot allocate partitions data buffer\n");
+ return -ENOMEM;
+ }
+
+ parts_info = uc_priv->pair.rxbuf;
+
+ for (desc_idx = 0 ; desc_idx < count ; desc_idx++) {
+ uc_priv->partitions.descs[desc_idx].info =
+ parts_info[desc_idx];
+
+ log_debug("FF-A partition ID %x : info cached\n",
+ uc_priv->partitions.descs[desc_idx].info.id);
+ }
+
+ uc_priv->partitions.count = count;
+
+ log_debug("%d FF-A partition(s) found and cached\n", count);
+
+ } else {
+ u32 rx_desc_idx, cached_desc_idx;
+ struct ffa_partition_info *parts_info;
+ u8 desc_found;
+
+ parts_info = uc_priv->pair.rxbuf;
+
+ /*
+ * Search for the SP IDs read from the RX buffer
+ * in the already cached SPs.
+ * Update the UUID when ID found.
+ */
+ for (rx_desc_idx = 0; rx_desc_idx < count ; rx_desc_idx++) {
+ desc_found = 0;
+
+ /* Search the current ID in the cached partitions */
+ for (cached_desc_idx = 0;
+ cached_desc_idx < uc_priv->partitions.count;
+ cached_desc_idx++) {
+ /* Save the UUID */
+ if (uc_priv->partitions.descs[cached_desc_idx].info.id ==
+ parts_info[rx_desc_idx].id) {
+ uc_priv->partitions.descs[cached_desc_idx].sp_uuid =
+ *part_uuid;
+
+ desc_found = 1;
+ break;
+ }
+ }
+
+ if (!desc_found)
+ return -ENODATA;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * ffa_query_partitions_info() - invoke FFA_PARTITION_INFO_GET and save partitions data
+ * @dev: The FF-A bus device
+ * @part_uuid: Pointer to the partition(s) UUID
+ * @pcount: Pointer to the number of partitions variable filled when querying
+ *
+ * Execute the FFA_PARTITION_INFO_GET to query the partitions data.
+ * Then, call ffa_read_partitions_info to save the data in uc_priv.
+ *
+ * After reading the data the RX buffer is released using ffa_release_rx_buffer
+ *
+ * Return:
+ *
+ * When part_uuid is NULL, all partitions data are retrieved from secure world
+ * When part_uuid is non NULL, data for partitions matching the given UUID are
+ * retrieved and the number of partitions is returned
+ * 0 is returned on success. Otherwise, failure
+ */
+static int ffa_query_partitions_info(struct udevice *dev, struct ffa_partition_uuid *part_uuid,
+ u32 *pcount)
+{
+ struct ffa_partition_uuid query_uuid = {0};
+ ffa_value_t res = {0};
+ int ffa_errno;
+
+ /*
+ * If a UUID is specified. Information for one or more
+ * partitions in the system is queried. Otherwise, information
+ * for all installed partitions is queried
+ */
+
+ if (part_uuid) {
+ if (!pcount)
+ return -EINVAL;
+
+ query_uuid = *part_uuid;
+ } else if (pcount) {
+ return -EINVAL;
+ }
+
+ invoke_ffa_fn((ffa_value_t){
+ .a0 = FFA_SMC_32(FFA_PARTITION_INFO_GET),
+ .a1 = query_uuid.a1,
+ .a2 = query_uuid.a2,
+ .a3 = query_uuid.a3,
+ .a4 = query_uuid.a4,
+ }, &res);
+
+ if (res.a0 == FFA_SMC_32(FFA_SUCCESS)) {
+ int ret;
+
+ /*
+ * res.a2 contains the count of partition information descriptors
+ * populated in the RX buffer
+ */
+ if (res.a2) {
+ ret = ffa_read_partitions_info(dev, (u32)res.a2, part_uuid);
+ if (ret) {
+ log_err("failed reading SP(s) data , err (%d)\n", ret);
+ ffa_release_rx_buffer_hdlr(dev);
+ return -EINVAL;
+ }
+ }
+
+ /* Return the SP count (when querying using a UUID) */
+ if (pcount)
+ *pcount = (u32)res.a2;
+
+ /*
+ * After calling FFA_PARTITION_INFO_GET the buffer ownership
+ * is assigned to the consumer (u-boot). So, we need to give
+ * the ownership back to the SPM or hypervisor
+ */
+ ret = ffa_release_rx_buffer_hdlr(dev);
+
+ return ret;
+ }
+
+ ffa_errno = res.a2;
+ ffa_print_error_log(FFA_PARTITION_INFO_GET, ffa_errno);
+
+ return ffa_to_std_errno(ffa_errno);
+}
+
+/**
+ * ffa_get_partitions_info_hdlr() - FFA_PARTITION_INFO_GET handler function
+ * @uuid_str: pointer to the UUID string
+ * @sp_count: address of the variable containing the number of partitions matching the UUID
+ * The variable is set by the driver
+ * @sp_descs: address of the descriptors of the partitions matching the UUID
+ * The address is set by the driver
+ *
+ * Return the number of partitions and their descriptors matching the UUID
+ *
+ * Query the secure partition data from uc_priv.
+ * If not found, invoke FFA_PARTITION_INFO_GET FF-A function to query the partition information
+ * from secure world.
+ *
+ * A client of the FF-A driver should know the UUID of the service it wants to
+ * access. It should use the UUID to request the FF-A driver to provide the
+ * partition(s) information of the service. The FF-A driver uses
+ * PARTITION_INFO_GET to obtain this information. This is implemented through
+ * ffa_get_partitions_info_hdlr() function.
+ * If the partition(s) matching the UUID found, the partition(s) information and the
+ * number are returned.
+ * If no partition matching the UUID is found in the cached area, a new FFA_PARTITION_INFO_GET
+ * call is issued.
+ * If not done yet, the UUID is updated in the cached area.
+ * This assumes that partitions data does not change in the secure world.
+ * Otherwise u-boot will have an outdated partition data. The benefit of caching
+ * the information in the FF-A driver is to accommodate discovery after
+ * ExitBootServices().
+ *
+ * Return:
+ *
+ * @sp_count: the number of partitions
+ * @sp_descs: address of the partitions descriptors
+ *
+ * On success 0 is returned. Otherwise, failure
+ */
+int ffa_get_partitions_info_hdlr(struct udevice *dev, const char *uuid_str,
+ u32 *sp_count, struct ffa_partition_desc **sp_descs)
+{
+ u32 i;
+ struct ffa_partition_uuid part_uuid = {0};
+ struct ffa_priv *uc_priv;
+ struct ffa_partition_desc *rx_descs;
+
+ uc_priv = dev_get_uclass_priv(dev);
+
+ if (!uc_priv->partitions.count || !uc_priv->partitions.descs) {
+ log_err("no partition installed\n");
+ return -EINVAL;
+ }
+
+ if (!uuid_str) {
+ log_err("no UUID provided\n");
+ return -EINVAL;
+ }
+
+ if (!sp_count) {
+ log_err("no count argument provided\n");
+ return -EINVAL;
+ }
+
+ if (!sp_descs) {
+ log_err("no info argument provided\n");
+ return -EINVAL;
+ }
+
+ if (uuid_str_to_le_bin(uuid_str, (unsigned char *)&part_uuid)) {
+ log_err("invalid UUID\n");
+ return -EINVAL;
+ }
+
+ log_debug("Searching FF-A partitions using the provided UUID\n");
+
+ *sp_count = 0;
+ *sp_descs = uc_priv->pair.rxbuf;
+ rx_descs = *sp_descs;
+
+ /* Search in the cached partitions */
+ for (i = 0; i < uc_priv->partitions.count; i++)
+ if (ffa_uuid_are_identical(&uc_priv->partitions.descs[i].sp_uuid,
+ &part_uuid)) {
+ log_debug("FF-A partition ID %x matches the provided UUID\n",
+ uc_priv->partitions.descs[i].info.id);
+
+ (*sp_count)++;
+ *rx_descs++ = uc_priv->partitions.descs[i];
+ }
+
+ if (!(*sp_count)) {
+ int ret;
+
+ log_debug("No FF-A partition found. Querying framework ...\n");
+
+ ret = ffa_query_partitions_info(dev, &part_uuid, sp_count);
+
+ if (!ret) {
+ log_debug("Number of FF-A partition(s) matching the UUID: %d\n", *sp_count);
+
+ if (*sp_count)
+ ret = ffa_get_partitions_info_hdlr(dev, uuid_str, sp_count,
+ sp_descs);
+ else
+ ret = -ENODATA;
+ }
+
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * ffa_cache_partitions_info() - Query and saves all secure partitions data
+ * @dev: The FF-A bus device
+ *
+ * Invoke FFA_PARTITION_INFO_GET FF-A function to query from secure world
+ * all partitions information.
+ *
+ * The FFA_PARTITION_INFO_GET call is issued with nil UUID as an argument.
+ * All installed partitions information are returned. We cache them in uc_priv
+ * and we keep the UUID field empty (in FF-A 1.0 UUID is not provided by the partition descriptor)
+ *
+ * Called at the device probing level.
+ * ffa_cache_partitions_info uses ffa_query_partitions_info to get the data
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int ffa_cache_partitions_info(struct udevice *dev)
+{
+ return ffa_query_partitions_info(dev, NULL, NULL);
+}
+
+/**
+ * ffa_msg_send_direct_req_hdlr() - FFA_MSG_SEND_DIRECT_{REQ,RESP} handler function
+ * @dev: The FF-A bus device
+ * @dst_part_id: destination partition ID
+ * @msg: pointer to the message data preallocated by the client (in/out)
+ * @is_smc64: select 64-bit or 32-bit FF-A ABI
+ *
+ * Implement FFA_MSG_SEND_DIRECT_{REQ,RESP}
+ * FF-A functions.
+ *
+ * FFA_MSG_SEND_DIRECT_REQ is used to send the data to the secure partition.
+ * The response from the secure partition is handled by reading the
+ * FFA_MSG_SEND_DIRECT_RESP arguments.
+ *
+ * The maximum size of the data that can be exchanged is 40 bytes which is
+ * sizeof(struct ffa_send_direct_data) as defined by the FF-A specification 1.0
+ * in the section relevant to FFA_MSG_SEND_DIRECT_{REQ,RESP}
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int ffa_msg_send_direct_req_hdlr(struct udevice *dev, u16 dst_part_id,
+ struct ffa_send_direct_data *msg, bool is_smc64)
+{
+ ffa_value_t res = {0};
+ int ffa_errno;
+ u64 req_mode, resp_mode;
+ struct ffa_priv *uc_priv;
+
+ uc_priv = dev_get_uclass_priv(dev);
+
+ /* No partition installed */
+ if (!uc_priv->partitions.count || !uc_priv->partitions.descs)
+ return -ENODEV;
+
+ if (is_smc64) {
+ req_mode = FFA_SMC_64(FFA_MSG_SEND_DIRECT_REQ);
+ resp_mode = FFA_SMC_64(FFA_MSG_SEND_DIRECT_RESP);
+ } else {
+ req_mode = FFA_SMC_32(FFA_MSG_SEND_DIRECT_REQ);
+ resp_mode = FFA_SMC_32(FFA_MSG_SEND_DIRECT_RESP);
+ }
+
+ invoke_ffa_fn((ffa_value_t){
+ .a0 = req_mode,
+ .a1 = PREP_SELF_ENDPOINT_ID(uc_priv->id) |
+ PREP_PART_ENDPOINT_ID(dst_part_id),
+ .a2 = 0,
+ .a3 = msg->data0,
+ .a4 = msg->data1,
+ .a5 = msg->data2,
+ .a6 = msg->data3,
+ .a7 = msg->data4,
+ }, &res);
+
+ while (res.a0 == FFA_SMC_32(FFA_INTERRUPT))
+ invoke_ffa_fn((ffa_value_t){
+ .a0 = FFA_SMC_32(FFA_RUN),
+ .a1 = res.a1,
+ }, &res);
+
+ if (res.a0 == FFA_SMC_32(FFA_SUCCESS)) {
+ /* Message sent with no response */
+ return 0;
+ }
+
+ if (res.a0 == resp_mode) {
+ /* Message sent with response extract the return data */
+ msg->data0 = res.a3;
+ msg->data1 = res.a4;
+ msg->data2 = res.a5;
+ msg->data3 = res.a6;
+ msg->data4 = res.a7;
+
+ return 0;
+ }
+
+ ffa_errno = res.a2;
+ return ffa_to_std_errno(ffa_errno);
+}
+
+/* FF-A driver operations (used by clients for communicating with FF-A)*/
+
+/**
+ * ffa_partition_info_get() - FFA_PARTITION_INFO_GET driver operation
+ * @uuid_str: pointer to the UUID string
+ * @sp_count: address of the variable containing the number of partitions matching the UUID
+ * The variable is set by the driver
+ * @sp_descs: address of the descriptors of the partitions matching the UUID
+ * The address is set by the driver
+ *
+ * Driver operation for FFA_PARTITION_INFO_GET.
+ * Please see ffa_get_partitions_info_hdlr() description for more details.
+ *
+ * Return:
+ *
+ * @sp_count: the number of partitions
+ * @sp_descs: address of the partitions descriptors
+ *
+ * On success 0 is returned. Otherwise, failure
+ */
+int ffa_partition_info_get(struct udevice *dev, const char *uuid_str,
+ u32 *sp_count, struct ffa_partition_desc **sp_descs)
+{
+ struct ffa_bus_ops *ops = ffa_get_ops(dev);
+
+ if (!ops->partition_info_get)
+ return -ENOSYS;
+
+ return ops->partition_info_get(dev, uuid_str, sp_count, sp_descs);
+}
+
+/**
+ * ffa_sync_send_receive() - FFA_MSG_SEND_DIRECT_{REQ,RESP} driver operation
+ * @dev: The FF-A bus device
+ * @dst_part_id: destination partition ID
+ * @msg: pointer to the message data preallocated by the client (in/out)
+ * @is_smc64: select 64-bit or 32-bit FF-A ABI
+ *
+ * Driver operation for FFA_MSG_SEND_DIRECT_{REQ,RESP}.
+ * Please see ffa_msg_send_direct_req_hdlr() description for more details.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int ffa_sync_send_receive(struct udevice *dev, u16 dst_part_id,
+ struct ffa_send_direct_data *msg, bool is_smc64)
+{
+ struct ffa_bus_ops *ops = ffa_get_ops(dev);
+
+ if (!ops->sync_send_receive)
+ return -ENOSYS;
+
+ return ops->sync_send_receive(dev, dst_part_id, msg, is_smc64);
+}
+
+/**
+ * ffa_rxtx_unmap() - FFA_RXTX_UNMAP driver operation
+ * @dev: The FF-A bus device
+ *
+ * Driver operation for FFA_RXTX_UNMAP.
+ * Please see ffa_unmap_rxtx_buffers_hdlr() description for more details.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int ffa_rxtx_unmap(struct udevice *dev)
+{
+ struct ffa_bus_ops *ops = ffa_get_ops(dev);
+
+ if (!ops->rxtx_unmap)
+ return -ENOSYS;
+
+ return ops->rxtx_unmap(dev);
+}
+
+/**
+ * ffa_do_probe() - probing FF-A framework
+ * @dev: the FF-A bus device (arm_ffa)
+ *
+ * Probing is triggered on demand by clients searching for the uclass.
+ * At probe level the following actions are done:
+ * - saving the FF-A framework version in uc_priv
+ * - querying from secure world the u-boot endpoint ID
+ * - querying from secure world the supported features of FFA_RXTX_MAP
+ * - mapping the RX/TX buffers
+ * - querying from secure world all the partitions information
+ *
+ * All data queried from secure world is saved in uc_priv.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int ffa_do_probe(struct udevice *dev)
+{
+ int ret;
+
+ ret = ffa_get_version_hdlr(dev);
+ if (ret)
+ return ret;
+
+ ret = ffa_get_endpoint_id(dev);
+ if (ret)
+ return ret;
+
+ ret = ffa_get_rxtx_map_features_hdlr(dev);
+ if (ret)
+ return ret;
+
+ ret = ffa_map_rxtx_buffers_hdlr(dev);
+ if (ret)
+ return ret;
+
+ ret = ffa_cache_partitions_info(dev);
+ if (ret) {
+ ffa_unmap_rxtx_buffers_hdlr(dev);
+ return ret;
+ }
+
+ return 0;
+}
+
+UCLASS_DRIVER(ffa) = {
+ .name = "ffa",
+ .id = UCLASS_FFA,
+ .pre_probe = ffa_do_probe,
+ .pre_remove = ffa_unmap_rxtx_buffers_hdlr,
+ .per_device_auto = sizeof(struct ffa_priv)
+};
diff --git a/drivers/firmware/arm-ffa/arm-ffa.c b/drivers/firmware/arm-ffa/arm-ffa.c
new file mode 100644
index 0000000..ee0bf9a
--- /dev/null
+++ b/drivers/firmware/arm-ffa/arm-ffa.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#include <common.h>
+#include <arm_ffa.h>
+#include <arm_ffa_priv.h>
+#include <dm.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <dm/device-internal.h>
+#include <linux/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * invoke_ffa_fn() - SMC wrapper
+ * @args: FF-A ABI arguments to be copied to Xn registers
+ * @res: FF-A ABI return data to be copied from Xn registers
+ *
+ * Calls low level SMC assembly function
+ */
+void invoke_ffa_fn(ffa_value_t args, ffa_value_t *res)
+{
+ arm_smccc_1_2_smc(&args, res);
+}
+
+/**
+ * arm_ffa_discover() - perform FF-A discovery
+ * @dev: The Arm FF-A bus device (arm_ffa)
+ * Try to discover the FF-A framework. Discovery is performed by
+ * querying the FF-A framework version from secure world using the FFA_VERSION ABI.
+ * Return:
+ *
+ * true on success. Otherwise, false.
+ */
+static bool arm_ffa_discover(struct udevice *dev)
+{
+ int ret;
+
+ log_debug("Arm FF-A framework discovery\n");
+
+ ret = ffa_get_version_hdlr(dev);
+ if (ret)
+ return false;
+
+ return true;
+}
+
+/**
+ * arm_ffa_is_supported() - FF-A bus discovery callback
+ * @invoke_fn: legacy SMC invoke function (not used)
+ *
+ * Perform FF-A discovery by calling arm_ffa_discover().
+ * Discovery is performed by querying the FF-A framework version from
+ * secure world using the FFA_VERSION ABI.
+ *
+ * The FF-A driver is registered as an SMCCC feature driver. So, features discovery
+ * callbacks are called by the PSCI driver (PSCI device is the SMCCC features
+ * root device).
+ *
+ * The FF-A driver supports the SMCCCv1.2 extended input/output registers.
+ * So, the legacy SMC invocation is not used.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static bool arm_ffa_is_supported(void (*invoke_fn)(ulong a0, ulong a1,
+ ulong a2, ulong a3,
+ ulong a4, ulong a5,
+ ulong a6, ulong a7,
+ struct arm_smccc_res *res))
+{
+ return arm_ffa_discover(NULL);
+}
+
+/* Arm FF-A driver operations */
+
+static const struct ffa_bus_ops ffa_ops = {
+ .partition_info_get = ffa_get_partitions_info_hdlr,
+ .sync_send_receive = ffa_msg_send_direct_req_hdlr,
+ .rxtx_unmap = ffa_unmap_rxtx_buffers_hdlr,
+};
+
+/* Registering the FF-A driver as an SMCCC feature driver */
+
+ARM_SMCCC_FEATURE_DRIVER(arm_ffa) = {
+ .driver_name = FFA_DRV_NAME,
+ .is_supported = arm_ffa_is_supported,
+};
+
+/* Declaring the FF-A driver under UCLASS_FFA */
+
+U_BOOT_DRIVER(arm_ffa) = {
+ .name = FFA_DRV_NAME,
+ .id = UCLASS_FFA,
+ .flags = DM_REMOVE_OS_PREPARE,
+ .ops = &ffa_ops,
+};
diff --git a/drivers/firmware/arm-ffa/ffa-emul-uclass.c b/drivers/firmware/arm-ffa/ffa-emul-uclass.c
new file mode 100644
index 0000000..4bf9f60
--- /dev/null
+++ b/drivers/firmware/arm-ffa/ffa-emul-uclass.c
@@ -0,0 +1,720 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+#include <common.h>
+#include <dm.h>
+#include <mapmem.h>
+#include <string.h>
+#include <asm/global_data.h>
+#include <asm/sandbox_arm_ffa.h>
+#include <asm/sandbox_arm_ffa_priv.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/root.h>
+#include <linux/errno.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* The partitions (SPs) table */
+static struct ffa_partition_desc sandbox_partitions[SANDBOX_PARTITIONS_CNT] = {
+ {
+ .info = { .id = SANDBOX_SP1_ID, .exec_ctxt = 0x5687, .properties = 0x89325621 },
+ .sp_uuid = {
+ .a1 = SANDBOX_SERVICE1_UUID_A1,
+ .a2 = SANDBOX_SERVICE1_UUID_A2,
+ .a3 = SANDBOX_SERVICE1_UUID_A3,
+ .a4 = SANDBOX_SERVICE1_UUID_A4,
+ }
+ },
+ {
+ .info = { .id = SANDBOX_SP3_ID, .exec_ctxt = 0x7687, .properties = 0x23325621 },
+ .sp_uuid = {
+ .a1 = SANDBOX_SERVICE2_UUID_A1,
+ .a2 = SANDBOX_SERVICE2_UUID_A2,
+ .a3 = SANDBOX_SERVICE2_UUID_A3,
+ .a4 = SANDBOX_SERVICE2_UUID_A4,
+ }
+ },
+ {
+ .info = { .id = SANDBOX_SP2_ID, .exec_ctxt = 0x9587, .properties = 0x45325621 },
+ .sp_uuid = {
+ .a1 = SANDBOX_SERVICE1_UUID_A1,
+ .a2 = SANDBOX_SERVICE1_UUID_A2,
+ .a3 = SANDBOX_SERVICE1_UUID_A3,
+ .a4 = SANDBOX_SERVICE1_UUID_A4,
+ }
+ },
+ {
+ .info = { .id = SANDBOX_SP4_ID, .exec_ctxt = 0x1487, .properties = 0x70325621 },
+ .sp_uuid = {
+ .a1 = SANDBOX_SERVICE2_UUID_A1,
+ .a2 = SANDBOX_SERVICE2_UUID_A2,
+ .a3 = SANDBOX_SERVICE2_UUID_A3,
+ .a4 = SANDBOX_SERVICE2_UUID_A4,
+ }
+ }
+
+};
+
+/* The emulator functions */
+
+/**
+ * sandbox_ffa_version() - Emulated FFA_VERSION handler function
+ * @emul: The sandbox FF-A emulator device
+ * @pargs: The SMC call input arguments a0-a7
+ * @res: The SMC return data
+ *
+ * Emulate FFA_VERSION FF-A function.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+
+static int sandbox_ffa_version(struct udevice *emul, ffa_value_t *pargs, ffa_value_t *res)
+{
+ struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+ priv->fwk_version = FFA_VERSION_1_0;
+ res->a0 = priv->fwk_version;
+
+ /* x1-x7 MBZ */
+ memset(FFA_X1X7_MBZ_REG_START, 0, FFA_X1X7_MBZ_CNT * sizeof(ulong));
+
+ return 0;
+}
+
+/**
+ * sandbox_ffa_id_get() - Emulated FFA_ID_GET handler function
+ * @emul: The sandbox FF-A emulator device
+ * @pargs: The SMC call input arguments a0-a7
+ * @res: The SMC return data
+ *
+ * Emulate FFA_ID_GET FF-A function.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_id_get(struct udevice *emul, ffa_value_t *pargs, ffa_value_t *res)
+{
+ struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+ res->a0 = FFA_SMC_32(FFA_SUCCESS);
+ res->a1 = 0;
+
+ priv->id = NS_PHYS_ENDPOINT_ID;
+ res->a2 = priv->id;
+
+ /* x3-x7 MBZ */
+ memset(FFA_X3_MBZ_REG_START, 0, FFA_X3X7_MBZ_CNT * sizeof(ulong));
+
+ return 0;
+}
+
+/**
+ * sandbox_ffa_features() - Emulated FFA_FEATURES handler function
+ * @pargs: The SMC call input arguments a0-a7
+ * @res: The SMC return data
+ *
+ * Emulate FFA_FEATURES FF-A function.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_features(ffa_value_t *pargs, ffa_value_t *res)
+{
+ res->a1 = 0;
+
+ if (pargs->a1 == FFA_SMC_64(FFA_RXTX_MAP)) {
+ res->a0 = FFA_SMC_32(FFA_SUCCESS);
+ res->a2 = RXTX_BUFFERS_MIN_SIZE;
+ res->a3 = 0;
+ /* x4-x7 MBZ */
+ memset(FFA_X4X7_MBZ_REG_START, 0, FFA_X4X7_MBZ_CNT * sizeof(ulong));
+ return 0;
+ }
+
+ res->a0 = FFA_SMC_32(FFA_ERROR);
+ res->a2 = -NOT_SUPPORTED;
+ /* x3-x7 MBZ */
+ memset(FFA_X3_MBZ_REG_START, 0, FFA_X3X7_MBZ_CNT * sizeof(ulong));
+ log_err("FF-A interface %lx not implemented\n", pargs->a1);
+
+ return ffa_to_std_errmap[NOT_SUPPORTED];
+}
+
+/**
+ * sandbox_ffa_partition_info_get() - Emulated FFA_PARTITION_INFO_GET handler
+ * @emul: The sandbox FF-A emulator device
+ * @pargs: The SMC call input arguments a0-a7
+ * @res: The SMC return data
+ *
+ * Emulate FFA_PARTITION_INFO_GET FF-A function.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_partition_info_get(struct udevice *emul, ffa_value_t *pargs,
+ ffa_value_t *res)
+{
+ struct ffa_partition_info *rxbuf_desc_info = NULL;
+ u32 descs_cnt;
+ u32 descs_size_bytes;
+ int ret;
+ struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+ res->a0 = FFA_SMC_32(FFA_ERROR);
+
+ if (!priv->pair.rxbuf) {
+ res->a2 = -DENIED;
+ ret = ffa_to_std_errmap[DENIED];
+ goto cleanup;
+ }
+
+ if (priv->pair_info.rxbuf_owned) {
+ res->a2 = -BUSY;
+ ret = ffa_to_std_errmap[BUSY];
+ goto cleanup;
+ }
+
+ if (!priv->partitions.descs) {
+ priv->partitions.descs = sandbox_partitions;
+ priv->partitions.count = SANDBOX_PARTITIONS_CNT;
+ }
+
+ descs_size_bytes = SANDBOX_PARTITIONS_CNT *
+ sizeof(struct ffa_partition_desc);
+
+ /* Abort if the RX buffer size is smaller than the descs buffer size */
+ if ((priv->pair_info.rxtx_buf_size * SZ_4K) < descs_size_bytes) {
+ res->a2 = -NO_MEMORY;
+ ret = ffa_to_std_errmap[NO_MEMORY];
+ goto cleanup;
+ }
+
+ rxbuf_desc_info = priv->pair.rxbuf;
+
+ /* No UUID specified. Return the information of all partitions */
+ if (!pargs->a1 && !pargs->a2 && !pargs->a3 && !pargs->a4) {
+ for (descs_cnt = 0; descs_cnt < SANDBOX_PARTITIONS_CNT; descs_cnt++)
+ *(rxbuf_desc_info++) = priv->partitions.descs[descs_cnt].info;
+
+ res->a0 = FFA_SMC_32(FFA_SUCCESS);
+ res->a2 = SANDBOX_PARTITIONS_CNT;
+ /* Transfer ownership to the consumer: the non secure world */
+ priv->pair_info.rxbuf_owned = 1;
+ ret = 0;
+
+ goto cleanup;
+ }
+
+ /* A UUID specified. Return the info of all SPs matching the UUID */
+
+ for (descs_cnt = 0 ; descs_cnt < SANDBOX_PARTITIONS_CNT ; descs_cnt++)
+ if (pargs->a1 == priv->partitions.descs[descs_cnt].sp_uuid.a1 &&
+ pargs->a2 == priv->partitions.descs[descs_cnt].sp_uuid.a2 &&
+ pargs->a3 == priv->partitions.descs[descs_cnt].sp_uuid.a3 &&
+ pargs->a4 == priv->partitions.descs[descs_cnt].sp_uuid.a4) {
+ *(rxbuf_desc_info++) = priv->partitions.descs[descs_cnt].info;
+ }
+
+ if (rxbuf_desc_info != priv->pair.rxbuf) {
+ res->a0 = FFA_SMC_32(FFA_SUCCESS);
+ /* Store the partitions count */
+ res->a2 = (ulong)
+ (rxbuf_desc_info - (struct ffa_partition_info *)
+ priv->pair.rxbuf);
+ ret = 0;
+
+ /* Transfer ownership to the consumer: the non secure world */
+ priv->pair_info.rxbuf_owned = 1;
+ } else {
+ /* Unrecognized UUID */
+ res->a2 = -INVALID_PARAMETERS;
+ ret = ffa_to_std_errmap[INVALID_PARAMETERS];
+ }
+
+cleanup:
+
+ log_err("FFA_PARTITION_INFO_GET (%ld)\n", res->a2);
+
+ res->a1 = 0;
+
+ /* x3-x7 MBZ */
+ memset(FFA_X3_MBZ_REG_START, 0, FFA_X3X7_MBZ_CNT * sizeof(ulong));
+
+ return ret;
+}
+
+/**
+ * sandbox_ffa_rxtx_map() - Emulated FFA_RXTX_MAP handler
+ * @emul: The sandbox FF-A emulator device
+ * @pargs: The SMC call input arguments a0-a7
+ * @res: The SMC return data
+ *
+ * Emulate FFA_RXTX_MAP FF-A function.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_rxtx_map(struct udevice *emul, ffa_value_t *pargs, ffa_value_t *res)
+{
+ int ret;
+ struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+ res->a0 = FFA_SMC_32(FFA_ERROR);
+
+ if (priv->pair.txbuf && priv->pair.rxbuf) {
+ res->a2 = -DENIED;
+ ret = ffa_to_std_errmap[DENIED];
+ goto feedback;
+ }
+
+ if (pargs->a3 >= RXTX_BUFFERS_MIN_PAGES && pargs->a1 && pargs->a2) {
+ priv->pair.txbuf = map_sysmem(pargs->a1, 0);
+ priv->pair.rxbuf = map_sysmem(pargs->a2, 0);
+ priv->pair_info.rxtx_buf_size = pargs->a3;
+ priv->pair_info.rxbuf_mapped = 1;
+ res->a0 = FFA_SMC_32(FFA_SUCCESS);
+ res->a2 = 0;
+ ret = 0;
+ goto feedback;
+ }
+
+ if (!pargs->a1 || !pargs->a2) {
+ res->a2 = -INVALID_PARAMETERS;
+ ret = ffa_to_std_errmap[INVALID_PARAMETERS];
+ } else {
+ res->a2 = -NO_MEMORY;
+ ret = ffa_to_std_errmap[NO_MEMORY];
+ }
+
+ log_err("Error in FFA_RXTX_MAP arguments (%d)\n",
+ (int)res->a2);
+
+feedback:
+
+ res->a1 = 0;
+
+ /* x3-x7 MBZ */
+ memset(FFA_X3_MBZ_REG_START, 0, FFA_X3X7_MBZ_CNT * sizeof(ulong));
+
+ return ret;
+}
+
+/**
+ * sandbox_ffa_rxtx_unmap() - Emulated FFA_RXTX_UNMAP handler
+ * @emul: The sandbox FF-A emulator device
+ * @pargs: The SMC call input arguments a0-a7
+ * @res: The SMC return data
+ *
+ * Emulate FFA_RXTX_UNMAP FF-A function.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_rxtx_unmap(struct udevice *emul, ffa_value_t *pargs, ffa_value_t *res)
+{
+ int ret;
+ struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+ res->a0 = FFA_SMC_32(FFA_ERROR);
+ res->a2 = -INVALID_PARAMETERS;
+ ret = ffa_to_std_errmap[INVALID_PARAMETERS];
+
+ if (GET_NS_PHYS_ENDPOINT_ID(pargs->a1) != priv->id)
+ goto feedback;
+
+ if (priv->pair.txbuf && priv->pair.rxbuf) {
+ priv->pair.txbuf = 0;
+ priv->pair.rxbuf = 0;
+ priv->pair_info.rxtx_buf_size = 0;
+ priv->pair_info.rxbuf_mapped = 0;
+ res->a0 = FFA_SMC_32(FFA_SUCCESS);
+ res->a2 = 0;
+ ret = 0;
+ goto feedback;
+ }
+
+ log_err("No buffer pair registered on behalf of the caller\n");
+
+feedback:
+
+ res->a1 = 0;
+
+ /* x3-x7 MBZ */
+ memset(FFA_X3_MBZ_REG_START, 0, FFA_X3X7_MBZ_CNT * sizeof(ulong));
+
+ return ret;
+}
+
+/**
+ * sandbox_ffa_rx_release() - Emulated FFA_RX_RELEASE handler
+ * @emul: The sandbox FF-A emulator device
+ * @pargs: The SMC call input arguments a0-a7
+ * @res: The SMC return data
+ *
+ * Emulate FFA_RX_RELEASE FF-A function.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_rx_release(struct udevice *emul, ffa_value_t *pargs, ffa_value_t *res)
+{
+ int ret;
+ struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+ if (!priv->pair_info.rxbuf_owned) {
+ res->a0 = FFA_SMC_32(FFA_ERROR);
+ res->a2 = -DENIED;
+ ret = ffa_to_std_errmap[DENIED];
+ } else {
+ priv->pair_info.rxbuf_owned = 0;
+ res->a0 = FFA_SMC_32(FFA_SUCCESS);
+ res->a2 = 0;
+ ret = 0;
+ }
+
+ res->a1 = 0;
+
+ /* x3-x7 MBZ */
+ memset(FFA_X3_MBZ_REG_START, 0, FFA_X3X7_MBZ_CNT * sizeof(ulong));
+
+ return ret;
+}
+
+/**
+ * sandbox_ffa_sp_valid() - Check SP validity
+ * @emul: The sandbox FF-A emulator device
+ * @part_id: partition ID to check
+ *
+ * Search the input ID in the descriptors table.
+ *
+ * Return:
+ *
+ * 1 on success (Partition found). Otherwise, failure
+ */
+static int sandbox_ffa_sp_valid(struct udevice *emul, u16 part_id)
+{
+ u32 descs_cnt;
+ struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+ for (descs_cnt = 0 ; descs_cnt < SANDBOX_PARTITIONS_CNT ; descs_cnt++)
+ if (priv->partitions.descs[descs_cnt].info.id == part_id)
+ return 1;
+
+ return 0;
+}
+
+/**
+ * sandbox_ffa_msg_send_direct_req() - Emulated FFA_MSG_SEND_DIRECT_{REQ,RESP} handler
+ * @emul: The sandbox FF-A emulator device
+ * @pargs: The SMC call input arguments a0-a7
+ * @res: The SMC return data
+ *
+ * Emulate FFA_MSG_SEND_DIRECT_{REQ,RESP} FF-A ABIs.
+ * Only SMC 64-bit is supported in Sandbox.
+ *
+ * Emulating interrupts is not supported. So, FFA_RUN and FFA_INTERRUPT are not
+ * supported. In case of success FFA_MSG_SEND_DIRECT_RESP is returned with
+ * default pattern data (0xff).
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_msg_send_direct_req(struct udevice *emul,
+ ffa_value_t *pargs, ffa_value_t *res)
+{
+ u16 part_id;
+ struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+ part_id = GET_DST_SP_ID(pargs->a1);
+
+ if (GET_NS_PHYS_ENDPOINT_ID(pargs->a1) != priv->id ||
+ !sandbox_ffa_sp_valid(emul, part_id) || pargs->a2) {
+ res->a0 = FFA_SMC_32(FFA_ERROR);
+ res->a1 = 0;
+ res->a2 = -INVALID_PARAMETERS;
+
+ /* x3-x7 MBZ */
+ memset(FFA_X3_MBZ_REG_START, 0, FFA_X3X7_MBZ_CNT * sizeof(ulong));
+
+ return ffa_to_std_errmap[INVALID_PARAMETERS];
+ }
+
+ res->a0 = FFA_SMC_64(FFA_MSG_SEND_DIRECT_RESP);
+
+ res->a1 = PREP_SRC_SP_ID(part_id) |
+ PREP_NS_PHYS_ENDPOINT_ID(priv->id);
+
+ res->a2 = 0;
+
+ /* Return 0xff bytes as a response */
+ res->a3 = -1UL;
+ res->a4 = -1UL;
+ res->a5 = -1UL;
+ res->a6 = -1UL;
+ res->a7 = -1UL;
+
+ return 0;
+}
+
+/**
+ * sandbox_ffa_get_rxbuf_flags() - Read the mapping/ownership flags
+ * @emul: The sandbox FF-A emulator device
+ * @queried_func_id: The FF-A function to be queried
+ * @func_data: Pointer to the FF-A function arguments container structure
+ *
+ * Query the status flags of the following emulated
+ * ABIs: FFA_RXTX_MAP, FFA_RXTX_UNMAP, FFA_RX_RELEASE.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_get_rxbuf_flags(struct udevice *emul, u32 queried_func_id,
+ struct ffa_sandbox_data *func_data)
+{
+ struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+ if (!func_data)
+ return -EINVAL;
+
+ if (!func_data->data0 || func_data->data0_size != sizeof(u8))
+ return -EINVAL;
+
+ switch (queried_func_id) {
+ case FFA_RXTX_MAP:
+ case FFA_RXTX_UNMAP:
+ *((u8 *)func_data->data0) = priv->pair_info.rxbuf_mapped;
+ return 0;
+ case FFA_RX_RELEASE:
+ *((u8 *)func_data->data0) = priv->pair_info.rxbuf_owned;
+ return 0;
+ default:
+ log_err("The querried FF-A interface flag (%d) undefined\n",
+ queried_func_id);
+ return -EINVAL;
+ }
+}
+
+/**
+ * sandbox_ffa_get_fwk_version() - Return the FFA framework version
+ * @emul: The sandbox FF-A emulator device
+ * @func_data: Pointer to the FF-A function arguments container structure
+ *
+ * Return the FFA framework version read from the FF-A emulator data.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_get_fwk_version(struct udevice *emul, struct ffa_sandbox_data *func_data)
+{
+ struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+ if (!func_data)
+ return -EINVAL;
+
+ if (!func_data->data0 ||
+ func_data->data0_size != sizeof(priv->fwk_version))
+ return -EINVAL;
+
+ *((u32 *)func_data->data0) = priv->fwk_version;
+
+ return 0;
+}
+
+/**
+ * sandbox_ffa_get_parts() - Return the address of partitions data
+ * @emul: The sandbox FF-A emulator device
+ * @func_data: Pointer to the FF-A function arguments container structure
+ *
+ * Return the address of partitions data read from the FF-A emulator data.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_get_parts(struct udevice *emul, struct ffa_sandbox_data *func_data)
+{
+ struct sandbox_ffa_emul *priv = dev_get_priv(emul);
+
+ if (!func_data)
+ return -EINVAL;
+
+ if (!func_data->data0 ||
+ func_data->data0_size != sizeof(struct ffa_partitions *))
+ return -EINVAL;
+
+ *((struct ffa_partitions **)func_data->data0) = &priv->partitions;
+
+ return 0;
+}
+
+/**
+ * sandbox_query_ffa_emul_state() - Inspect the FF-A ABIs
+ * @queried_func_id: The FF-A function to be queried
+ * @func_data: Pointer to the FF-A function arguments container structure
+ *
+ * Query the status of FF-A ABI specified in the input argument.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int sandbox_query_ffa_emul_state(u32 queried_func_id,
+ struct ffa_sandbox_data *func_data)
+{
+ struct udevice *emul;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_FFA_EMUL, &emul);
+ if (ret) {
+ log_err("Cannot find FF-A emulator during querying state\n");
+ return ret;
+ }
+
+ switch (queried_func_id) {
+ case FFA_RXTX_MAP:
+ case FFA_RXTX_UNMAP:
+ case FFA_RX_RELEASE:
+ return sandbox_ffa_get_rxbuf_flags(emul, queried_func_id, func_data);
+ case FFA_VERSION:
+ return sandbox_ffa_get_fwk_version(emul, func_data);
+ case FFA_PARTITION_INFO_GET:
+ return sandbox_ffa_get_parts(emul, func_data);
+ default:
+ log_err("Undefined FF-A interface (%d)\n",
+ queried_func_id);
+ return -EINVAL;
+ }
+}
+
+/**
+ * sandbox_arm_ffa_smccc_smc() - FF-A SMC call emulation
+ * @args: the SMC call arguments
+ * @res: the SMC call returned data
+ *
+ * Emulate the FF-A ABIs SMC call.
+ * The emulated FF-A ABI is identified and invoked.
+ * FF-A emulation is based on the FF-A specification 1.0
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure.
+ * FF-A protocol error codes are returned using the registers arguments as
+ * described by the specification
+ */
+void sandbox_arm_ffa_smccc_smc(ffa_value_t *args, ffa_value_t *res)
+{
+ int ret = 0;
+ struct udevice *emul;
+
+ ret = uclass_first_device_err(UCLASS_FFA_EMUL, &emul);
+ if (ret) {
+ log_err("Cannot find FF-A emulator during SMC emulation\n");
+ return;
+ }
+
+ switch (args->a0) {
+ case FFA_SMC_32(FFA_VERSION):
+ ret = sandbox_ffa_version(emul, args, res);
+ break;
+ case FFA_SMC_32(FFA_PARTITION_INFO_GET):
+ ret = sandbox_ffa_partition_info_get(emul, args, res);
+ break;
+ case FFA_SMC_32(FFA_RXTX_UNMAP):
+ ret = sandbox_ffa_rxtx_unmap(emul, args, res);
+ break;
+ case FFA_SMC_64(FFA_MSG_SEND_DIRECT_REQ):
+ ret = sandbox_ffa_msg_send_direct_req(emul, args, res);
+ break;
+ case FFA_SMC_32(FFA_ID_GET):
+ ret = sandbox_ffa_id_get(emul, args, res);
+ break;
+ case FFA_SMC_32(FFA_FEATURES):
+ ret = sandbox_ffa_features(args, res);
+ break;
+ case FFA_SMC_64(FFA_RXTX_MAP):
+ ret = sandbox_ffa_rxtx_map(emul, args, res);
+ break;
+ case FFA_SMC_32(FFA_RX_RELEASE):
+ ret = sandbox_ffa_rx_release(emul, args, res);
+ break;
+ default:
+ log_err("Undefined FF-A interface (%lx)\n",
+ args->a0);
+ }
+
+ if (ret != 0)
+ log_err("FF-A ABI internal failure (%d)\n", ret);
+}
+
+/**
+ * invoke_ffa_fn() - SMC wrapper
+ * @args: FF-A ABI arguments to be copied to Xn registers
+ * @res: FF-A ABI return data to be copied from Xn registers
+ *
+ * Calls the emulated SMC call.
+ */
+void invoke_ffa_fn(ffa_value_t args, ffa_value_t *res)
+{
+ sandbox_arm_ffa_smccc_smc(&args, res);
+}
+
+/**
+ * ffa_emul_find() - Find the FF-A emulator
+ * @dev: the sandbox FF-A device (sandbox-arm-ffa)
+ * @emulp: the FF-A emulator device (sandbox-ffa-emul)
+ *
+ * Search for the FF-A emulator and returns its device pointer.
+ *
+ * Return:
+ * 0 on success. Otherwise, failure
+ */
+int ffa_emul_find(struct udevice *dev, struct udevice **emulp)
+{
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_FFA_EMUL, emulp);
+ if (ret) {
+ log_err("Cannot find FF-A emulator\n");
+ return ret;
+ }
+
+ log_debug("FF-A emulator ready to use\n");
+
+ return 0;
+}
+
+UCLASS_DRIVER(ffa_emul) = {
+ .name = "ffa_emul",
+ .id = UCLASS_FFA_EMUL,
+ .post_bind = dm_scan_fdt_dev,
+};
+
+static const struct udevice_id sandbox_ffa_emul_ids[] = {
+ { .compatible = "sandbox,arm-ffa-emul" },
+ { }
+};
+
+/* Declaring the sandbox FF-A emulator under UCLASS_FFA_EMUL */
+U_BOOT_DRIVER(sandbox_ffa_emul) = {
+ .name = "sandbox_ffa_emul",
+ .id = UCLASS_FFA_EMUL,
+ .of_match = sandbox_ffa_emul_ids,
+ .priv_auto = sizeof(struct sandbox_ffa_emul),
+};
diff --git a/drivers/firmware/arm-ffa/sandbox_ffa.c b/drivers/firmware/arm-ffa/sandbox_ffa.c
new file mode 100644
index 0000000..1114242
--- /dev/null
+++ b/drivers/firmware/arm-ffa/sandbox_ffa.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+#include <common.h>
+#include <arm_ffa.h>
+#include <dm.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/sandbox_arm_ffa_priv.h>
+#include <dm/device-internal.h>
+#include <linux/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * sandbox_ffa_discover() - perform sandbox FF-A discovery
+ * @dev: The sandbox FF-A bus device
+ * Try to discover the FF-A framework. Discovery is performed by
+ * querying the FF-A framework version from secure world using the FFA_VERSION ABI.
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int sandbox_ffa_discover(struct udevice *dev)
+{
+ int ret;
+ struct udevice *emul;
+
+ log_debug("Emulated FF-A framework discovery\n");
+
+ ret = ffa_emul_find(dev, &emul);
+ if (ret) {
+ log_err("Cannot find FF-A emulator\n");
+ return ret;
+ }
+
+ ret = ffa_get_version_hdlr(dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+/**
+ * sandbox_ffa_probe() - The sandbox FF-A driver probe function
+ * @dev: the sandbox-arm-ffa device
+ * Save the emulator device in uc_priv.
+ * Return:
+ *
+ * 0 on success.
+ */
+static int sandbox_ffa_probe(struct udevice *dev)
+{
+ int ret;
+ struct ffa_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ ret = uclass_first_device_err(UCLASS_FFA_EMUL, &uc_priv->emul);
+ if (ret) {
+ log_err("Cannot find FF-A emulator\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * sandbox_ffa_bind() - The sandbox FF-A driver bind function
+ * @dev: the sandbox-arm-ffa device
+ * Try to discover the emulated FF-A bus.
+ * Return:
+ *
+ * 0 on success.
+ */
+static int sandbox_ffa_bind(struct udevice *dev)
+{
+ int ret;
+
+ ret = sandbox_ffa_discover(dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+/* Sandbox Arm FF-A emulator operations */
+
+static const struct ffa_bus_ops sandbox_ffa_ops = {
+ .partition_info_get = ffa_get_partitions_info_hdlr,
+ .sync_send_receive = ffa_msg_send_direct_req_hdlr,
+ .rxtx_unmap = ffa_unmap_rxtx_buffers_hdlr,
+};
+
+static const struct udevice_id sandbox_ffa_id[] = {
+ { "sandbox,arm-ffa", 0 },
+ { },
+};
+
+/* Declaring the sandbox FF-A driver under UCLASS_FFA */
+U_BOOT_DRIVER(sandbox_arm_ffa) = {
+ .name = "sandbox_arm_ffa",
+ .of_match = sandbox_ffa_id,
+ .id = UCLASS_FFA,
+ .bind = sandbox_ffa_bind,
+ .probe = sandbox_ffa_probe,
+ .ops = &sandbox_ffa_ops,
+};
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index 31027f3..fc395c9 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -28,6 +28,8 @@
DECLARE_GLOBAL_DATA_PTR;
+#define GPIO_ALLOC_BITS 32
+
/**
* gpio_desc_init() - Initialize the GPIO descriptor
*
@@ -75,6 +77,46 @@
return -ENOENT;
}
+/**
+ * gpio_is_claimed() - Test whether GPIO is claimed by consumer
+ *
+ * Test whether GPIO is claimed by consumer already.
+ *
+ * @uc_priv: gpio_dev_priv pointer.
+ * @offset: gpio offset within the device
+ * @return: true if claimed, false if not claimed
+ */
+static bool gpio_is_claimed(struct gpio_dev_priv *uc_priv, unsigned int offset)
+{
+ return !!(uc_priv->claimed[offset / GPIO_ALLOC_BITS] & BIT(offset % GPIO_ALLOC_BITS));
+}
+
+/**
+ * gpio_set_claim() - Set GPIO claimed by consumer
+ *
+ * Set a bit which indicate the GPIO is claimed by consumer
+ *
+ * @uc_priv: gpio_dev_priv pointer.
+ * @offset: gpio offset within the device
+ */
+static void gpio_set_claim(struct gpio_dev_priv *uc_priv, unsigned int offset)
+{
+ uc_priv->claimed[offset / GPIO_ALLOC_BITS] |= BIT(offset % GPIO_ALLOC_BITS);
+}
+
+/**
+ * gpio_clear_claim() - Clear GPIO claimed by consumer
+ *
+ * Clear a bit which indicate the GPIO is claimed by consumer
+ *
+ * @uc_priv: gpio_dev_priv pointer.
+ * @offset: gpio offset within the device
+ */
+static void gpio_clear_claim(struct gpio_dev_priv *uc_priv, unsigned int offset)
+{
+ uc_priv->claimed[offset / GPIO_ALLOC_BITS] &= ~BIT(offset % GPIO_ALLOC_BITS);
+}
+
#if CONFIG_IS_ENABLED(DM_GPIO_LOOKUP_LABEL)
/**
* dm_gpio_lookup_label() - look for name in gpio device
@@ -94,7 +136,7 @@
*offset = -1;
for (i = 0; i < uc_priv->gpio_count; i++) {
- if (!uc_priv->name[i])
+ if (!gpio_is_claimed(uc_priv, i))
continue;
if (!strcmp(name, uc_priv->name[i])) {
*offset = i;
@@ -350,7 +392,7 @@
int ret;
uc_priv = dev_get_uclass_priv(dev);
- if (uc_priv->name[desc->offset])
+ if (gpio_is_claimed(uc_priv, desc->offset))
return -EBUSY;
str = strdup(label);
if (!str)
@@ -362,6 +404,8 @@
return ret;
}
}
+
+ gpio_set_claim(uc_priv, desc->offset);
uc_priv->name[desc->offset] = str;
return 0;
@@ -438,7 +482,7 @@
int ret;
uc_priv = dev_get_uclass_priv(dev);
- if (!uc_priv->name[offset])
+ if (!gpio_is_claimed(uc_priv, offset))
return -ENXIO;
if (ops->rfree) {
ret = ops->rfree(dev, offset);
@@ -446,6 +490,7 @@
return ret;
}
+ gpio_clear_claim(uc_priv, offset);
free(uc_priv->name[offset]);
uc_priv->name[offset] = NULL;
@@ -480,7 +525,7 @@
return -ENOENT;
uc_priv = dev_get_uclass_priv(desc->dev);
- if (!uc_priv->name[desc->offset]) {
+ if (!gpio_is_claimed(uc_priv, desc->offset)) {
printf("%s: %s: error: gpio %s%d not reserved\n",
desc->dev->name, func,
uc_priv->bank_name ? uc_priv->bank_name : "",
@@ -826,7 +871,7 @@
return -EINVAL;
if (namep)
*namep = uc_priv->name[offset];
- if (skip_unused && !uc_priv->name[offset])
+ if (skip_unused && !gpio_is_claimed(uc_priv, offset))
return GPIOF_UNUSED;
if (ops->get_function) {
int ret;
@@ -1340,6 +1385,14 @@
uc_priv->name = calloc(uc_priv->gpio_count, sizeof(char *));
if (!uc_priv->name)
return -ENOMEM;
+
+ uc_priv->claimed = calloc(DIV_ROUND_UP(uc_priv->gpio_count,
+ GPIO_ALLOC_BITS),
+ GPIO_ALLOC_BITS / 8);
+ if (!uc_priv->claimed) {
+ free(uc_priv->name);
+ return -ENOMEM;
+ }
return gpio_renumber(NULL);
}
@@ -1353,6 +1406,7 @@
if (uc_priv->name[i])
free(uc_priv->name[i]);
}
+ free(uc_priv->claimed);
free(uc_priv->name);
return gpio_renumber(dev);
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index 4654f9e..b0c66d1 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -407,6 +407,7 @@
{ .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
{ .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
{ .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
+ { .compatible = "ti,tca9554", .data = OF_953X(8, PCA_INT), },
{ .compatible = "onsemi,pca9654", .data = OF_953X(8, PCA_INT), },
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 5e81698..4f42200 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -231,6 +231,15 @@
controller is used in various SoCs, e.g. the ST SPEAr, Altera
SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
+config SYS_I2C_DW_PCI
+ bool "Designware PCI I2C Controller"
+ depends on SYS_I2C_DW && PCI && ACPIGEN
+ default y
+ help
+ Say yes here to select the Designware PCI I2C Host Controller.
+ This PCI I2C controller is the base on Desigware I2C host
+ controller.
+
config SYS_I2C_AST2600
bool "AST2600 I2C Controller"
depends on DM_I2C && ARCH_ASPEED
@@ -363,7 +372,7 @@
config SYS_MXC_I2C1_SLAVE
hex "I2C1 Slave"
- default 0
+ default 0x0
help
MXC I2C1 Slave
endif
@@ -378,7 +387,7 @@
config SYS_MXC_I2C2_SLAVE
hex "I2C2 Slave"
- default 0
+ default 0x0
help
MXC I2C2 Slave
endif
@@ -392,7 +401,7 @@
config SYS_MXC_I2C3_SLAVE
hex "I2C3 Slave"
- default 0
+ default 0x0
help
MXC I2C3 Slave
endif
@@ -406,7 +415,7 @@
config SYS_MXC_I2C4_SLAVE
hex "I2C4 Slave"
- default 0
+ default 0x0
help
MXC I2C4 Slave
endif
@@ -420,7 +429,7 @@
config SYS_MXC_I2C5_SLAVE
hex "I2C5 Slave"
- default 0
+ default 0x0
help
MXC I2C5 Slave
endif
@@ -434,7 +443,7 @@
config SYS_MXC_I2C6_SLAVE
hex "I2C6 Slave"
- default 0
+ default 0x0
help
MXC I2C6 Slave
endif
@@ -448,7 +457,7 @@
config SYS_MXC_I2C7_SLAVE
hex "I2C7 Slave"
- default 0
+ default 0x0
help
MXC I2C7 Slave
endif
@@ -462,7 +471,7 @@
config SYS_MXC_I2C8_SLAVE
hex "I2C8 Slave"
- default 0
+ default 0x0
help
MXC I2C8 Slave
endif
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 99545df..d5b85f3 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -18,9 +18,7 @@
obj-$(CONFIG_SYS_I2C_CA) += i2c-cortina.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
-ifdef CONFIG_PCI
-obj-$(CONFIG_SYS_I2C_DW) += designware_i2c_pci.o
-endif
+obj-$(CONFIG_SYS_I2C_DW_PCI) += designware_i2c_pci.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
diff --git a/drivers/i2c/mtk_i2c.c b/drivers/i2c/mtk_i2c.c
index 5528bcd..2f331d3 100644
--- a/drivers/i2c/mtk_i2c.c
+++ b/drivers/i2c/mtk_i2c.c
@@ -183,9 +183,36 @@
[REG_DCM_EN] = 0xf88,
};
+static const uint mt_i2c_regs_v3[] = {
+ [REG_PORT] = 0x0,
+ [REG_INTR_MASK] = 0x8,
+ [REG_INTR_STAT] = 0xc,
+ [REG_CONTROL] = 0x10,
+ [REG_TRANSFER_LEN] = 0x14,
+ [REG_TRANSAC_LEN] = 0x18,
+ [REG_DELAY_LEN] = 0x1c,
+ [REG_TIMING] = 0x20,
+ [REG_START] = 0x24,
+ [REG_EXT_CONF] = 0x28,
+ [REG_LTIMING] = 0x2c,
+ [REG_HS] = 0x30,
+ [REG_IO_CONFIG] = 0x34,
+ [REG_FIFO_ADDR_CLR] = 0x38,
+ [REG_TRANSFER_LEN_AUX] = 0x44,
+ [REG_CLOCK_DIV] = 0x48,
+ [REG_SOFTRESET] = 0x50,
+ [REG_SLAVE_ADDR] = 0x94,
+ [REG_DEBUGSTAT] = 0xe4,
+ [REG_DEBUGCTRL] = 0xe8,
+ [REG_FIFO_STAT] = 0xf4,
+ [REG_FIFO_THRESH] = 0xf8,
+ [REG_DCM_EN] = 0xf88,
+};
+
struct mtk_i2c_soc_data {
const uint *regs;
uint dma_sync: 1;
+ uint ltiming_adjust: 1;
};
struct mtk_i2c_priv {
@@ -401,6 +428,10 @@
(sample_cnt << HS_SAMPLE_OFFSET) |
(step_cnt << HS_STEP_OFFSET);
i2c_writel(priv, REG_HS, high_speed_reg);
+ if (priv->soc_data->ltiming_adjust) {
+ timing_reg = (sample_cnt << 12) | (step_cnt << 9);
+ i2c_writel(priv, REG_LTIMING, timing_reg);
+ }
} else {
ret = mtk_i2c_calculate_speed(clk_src, priv->speed,
&step_cnt, &sample_cnt);
@@ -412,7 +443,12 @@
high_speed_reg = I2C_TIME_CLR_VALUE;
i2c_writel(priv, REG_TIMING, timing_reg);
i2c_writel(priv, REG_HS, high_speed_reg);
+ if (priv->soc_data->ltiming_adjust) {
+ timing_reg = (sample_cnt << 6) | step_cnt;
+ i2c_writel(priv, REG_LTIMING, timing_reg);
+ }
}
+
exit:
if (mtk_i2c_clk_disable(priv))
return log_msg_ret("set_speed disable clk", -1);
@@ -725,7 +761,6 @@
return log_msg_ret("probe enable clk", -1);
mtk_i2c_init_hw(priv);
-
if (mtk_i2c_clk_disable(priv))
return log_msg_ret("probe disable clk", -1);
@@ -750,31 +785,37 @@
static const struct mtk_i2c_soc_data mt76xx_soc_data = {
.regs = mt_i2c_regs_v1,
.dma_sync = 0,
+ .ltiming_adjust = 0,
};
static const struct mtk_i2c_soc_data mt7981_soc_data = {
- .regs = mt_i2c_regs_v1,
+ .regs = mt_i2c_regs_v3,
.dma_sync = 1,
+ .ltiming_adjust = 1,
};
static const struct mtk_i2c_soc_data mt7986_soc_data = {
.regs = mt_i2c_regs_v1,
.dma_sync = 1,
+ .ltiming_adjust = 0,
};
static const struct mtk_i2c_soc_data mt8183_soc_data = {
.regs = mt_i2c_regs_v2,
.dma_sync = 1,
+ .ltiming_adjust = 0,
};
static const struct mtk_i2c_soc_data mt8518_soc_data = {
.regs = mt_i2c_regs_v1,
.dma_sync = 0,
+ .ltiming_adjust = 0,
};
static const struct mtk_i2c_soc_data mt8512_soc_data = {
.regs = mt_i2c_regs_v1,
.dma_sync = 1,
+ .ltiming_adjust = 0,
};
static const struct dm_i2c_ops mtk_i2c_ops = {
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 93bbc69..14cdb0f 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -142,6 +142,8 @@
* code.
*/
enum mvstwsi_status_values {
+ /* Protocol violation on bus; this is a terminal state */
+ MVTWSI_BUS_ERROR = 0x00,
/* START condition transmitted */
MVTWSI_STATUS_START = 0x08,
/* Repeated START condition transmitted */
@@ -526,6 +528,36 @@
}
/*
+ * __twsi_i2c_reinit() - Reset and reinitialize the I2C controller.
+ *
+ * This function should be called to get the MVTWSI controller out of the
+ * "bus error" state. It saves and restores the baud and address registers.
+ *
+ * @twsi: The MVTWSI register structure to use.
+ * @tick: The duration of a clock cycle at the current I2C speed.
+ */
+static void __twsi_i2c_reinit(struct mvtwsi_registers *twsi, uint tick)
+{
+ uint baud;
+ uint slaveadd;
+
+ /* Save baud, address registers */
+ baud = readl(&twsi->baudrate);
+ slaveadd = readl(&twsi->slave_address);
+
+ /* Reset controller */
+ twsi_reset(twsi);
+
+ /* Restore baud, address registers */
+ writel(baud, &twsi->baudrate);
+ writel(slaveadd, &twsi->slave_address);
+ writel(0, &twsi->xtnd_slave_addr);
+
+ /* Assert STOP, but don't care for the result */
+ (void) twsi_stop(twsi, tick);
+}
+
+/*
* i2c_begin() - Start a I2C transaction.
*
* Begin a I2C transaction with a given expected start status and chip address.
@@ -621,6 +653,11 @@
int stop_status;
int expected_start = MVTWSI_STATUS_START;
+ /* Check for (and clear) a bus error from a previous failed transaction
+ * or another master on the same bus */
+ if (readl(&twsi->status) == MVTWSI_BUS_ERROR)
+ __twsi_i2c_reinit(twsi, tick);
+
if (alen > 0) {
/* Begin i2c write to send the address bytes */
status = i2c_begin(twsi, expected_start, (chip << 1), tick);
@@ -668,6 +705,11 @@
{
int status, stop_status;
+ /* Check for (and clear) a bus error from a previous failed transaction
+ * or another master on the same bus */
+ if (readl(&twsi->status) == MVTWSI_BUS_ERROR)
+ __twsi_i2c_reinit(twsi, tick);
+
/* Begin i2c write to send first the address bytes, then the
* data bytes */
status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1), tick);
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index b9f5c7a..a6e3f62 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -555,7 +555,7 @@
config SYS_I2C_EEPROM_ADDR
hex "Chip address of the EEPROM device"
depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
- default 0
+ default 0x0
if I2C_EEPROM
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 621d175..9c1e6a5 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -1100,8 +1100,11 @@
ret = ec_command_inptr(dev, EC_CMD_GET_SKU_ID, 0, NULL, 0,
(uint8_t **)&r, sizeof(*r));
- if (ret != sizeof(*r))
- return -ret;
+ if (ret != sizeof(*r)) {
+ if (ret >= 0)
+ ret = -EIO;
+ return ret;
+ }
return r->sku_id;
}
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 5085a3b..400066f 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -509,6 +509,10 @@
if (mmc->vqmmc_supply) {
int ret;
+ ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
+ if (ret)
+ return ret;
+
if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
regulator_set_value(mmc->vqmmc_supply, 1800000);
else
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 01d9b02..0e15767 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -421,7 +421,7 @@
mmc->cfg = cfg;
mmc->priv = dev;
- ret = bootdev_setup_sibling_blk(bdev, "mmc_bootdev");
+ ret = bootdev_setup_for_sibling_blk(bdev, "mmc_bootdev");
if (ret)
return log_msg_ret("bootdev", ret);
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 31cfda2..089a044 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -2775,9 +2775,10 @@
{
#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
if (mmc->vmmc_supply) {
- int ret = regulator_set_enable(mmc->vmmc_supply, true);
+ int ret = regulator_set_enable_if_allowed(mmc->vmmc_supply,
+ true);
- if (ret && ret != -EACCES) {
+ if (ret && ret != -ENOSYS) {
printf("Error enabling VMMC supply : %d\n", ret);
return ret;
}
@@ -2791,9 +2792,10 @@
mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
if (mmc->vmmc_supply) {
- int ret = regulator_set_enable(mmc->vmmc_supply, false);
+ int ret = regulator_set_enable_if_allowed(mmc->vmmc_supply,
+ false);
- if (ret && ret != -EACCES) {
+ if (ret && ret != -ENOSYS) {
pr_debug("Error disabling VMMC supply : %d\n", ret);
return ret;
}
diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c
index 4c9fb26..d4111e7 100644
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -54,6 +54,16 @@
(DP_PDMA << MC_DP_S) | \
(DP_PDMA << UN_DP_S))
+#define GDMA_BRIDGE_TO_CPU \
+ (0xC0000000 | \
+ GDM_ICS_EN | \
+ GDM_TCS_EN | \
+ GDM_UCS_EN | \
+ (DP_PDMA << MYMAC_DP_S) | \
+ (DP_PDMA << BC_DP_S) | \
+ (DP_PDMA << MC_DP_S) | \
+ (DP_PDMA << UN_DP_S))
+
#define GDMA_FWD_DISCARD \
(0x20000000 | \
GDM_ICS_EN | \
@@ -68,7 +78,8 @@
enum mtk_switch {
SW_NONE,
SW_MT7530,
- SW_MT7531
+ SW_MT7531,
+ SW_MT7988,
};
/* struct mtk_soc_data - This is the structure holding all differences
@@ -76,6 +87,7 @@
* @caps Flags shown the extra capability for the SoC
* @ana_rgc3: The offset for register ANA_RGC3 related to
* sgmiisys syscon
+ * @gdma_count: Number of GDMAs
* @pdma_base: Register base of PDMA block
* @txd_size: Tx DMA descriptor size.
* @rxd_size: Rx DMA descriptor size.
@@ -83,6 +95,7 @@
struct mtk_soc_data {
u32 caps;
u32 ana_rgc3;
+ u32 gdma_count;
u32 pdma_base;
u32 txd_size;
u32 rxd_size;
@@ -100,9 +113,17 @@
void __iomem *fe_base;
void __iomem *gmac_base;
void __iomem *sgmii_base;
+ void __iomem *gsw_base;
struct regmap *ethsys_regmap;
+ struct regmap *infra_regmap;
+
+ struct regmap *usxgmii_regmap;
+ struct regmap *xfi_pextp_regmap;
+ struct regmap *xfi_pll_regmap;
+ struct regmap *toprgu_regmap;
+
struct mii_dev *mdio_bus;
int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
@@ -123,8 +144,11 @@
enum mtk_switch sw;
int (*switch_init)(struct mtk_eth_priv *priv);
+ void (*switch_mac_control)(struct mtk_eth_priv *priv, bool enable);
u32 mt753x_smi_addr;
u32 mt753x_phy_base;
+ u32 mt753x_pmcr;
+ u32 mt753x_reset_wait_time;
struct gpio_desc rst_gpio;
int mcm;
@@ -149,7 +173,9 @@
{
u32 gdma_base;
- if (no == 1)
+ if (no == 2)
+ gdma_base = GDMA3_BASE;
+ else if (no == 1)
gdma_base = GDMA2_BASE;
else
gdma_base = GDMA1_BASE;
@@ -157,6 +183,11 @@
writel(val, priv->fe_base + gdma_base + reg);
}
+static void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
+{
+ clrsetbits_le32(priv->fe_base + reg, clr, set);
+}
+
static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg)
{
return readl(priv->gmac_base + reg);
@@ -183,6 +214,27 @@
regmap_write(priv->ethsys_regmap, reg, val);
}
+static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
+ u32 set)
+{
+ uint val;
+
+ regmap_read(priv->infra_regmap, reg, &val);
+ val &= ~clr;
+ val |= set;
+ regmap_write(priv->infra_regmap, reg, val);
+}
+
+static u32 mtk_gsw_read(struct mtk_eth_priv *priv, u32 reg)
+{
+ return readl(priv->gsw_base + reg);
+}
+
+static void mtk_gsw_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
+{
+ writel(val, priv->gsw_base + reg);
+}
+
/* Direct MDIO clause 22/45 access via SoC */
static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
u32 cmd, u32 st)
@@ -195,7 +247,7 @@
(((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
(((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
- if (cmd == MDIO_CMD_WRITE)
+ if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
val |= data & MDIO_RW_DATA_M;
mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST);
@@ -207,7 +259,7 @@
return ret;
}
- if (cmd == MDIO_CMD_READ) {
+ if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
val = mtk_gmac_read(priv, GMAC_PIAC_REG);
return val & MDIO_RW_DATA_M;
}
@@ -317,6 +369,11 @@
{
int ret, low_word, high_word;
+ if (priv->sw == SW_MT7988) {
+ *data = mtk_gsw_read(priv, reg);
+ return 0;
+ }
+
/* Write page address */
ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
if (ret)
@@ -342,6 +399,11 @@
{
int ret;
+ if (priv->sw == SW_MT7988) {
+ mtk_gsw_write(priv, reg, data);
+ return 0;
+ }
+
/* Write page address */
ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
if (ret)
@@ -433,7 +495,8 @@
MDIO_ST_C22);
}
-int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
+static int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad,
+ u16 reg)
{
u8 phy_addr;
int ret;
@@ -511,6 +574,7 @@
priv->mmd_write = mtk_mmd_ind_write;
break;
case SW_MT7531:
+ case SW_MT7988:
priv->mii_read = mt7531_mii_ind_read;
priv->mii_write = mt7531_mii_ind_write;
priv->mmd_read = mt7531_mmd_ind_read;
@@ -613,6 +677,16 @@
return 0;
}
+static void mt7530_mac_control(struct mtk_eth_priv *priv, bool enable)
+{
+ u32 pmcr = FORCE_MODE;
+
+ if (enable)
+ pmcr = priv->mt753x_pmcr;
+
+ mt753x_reg_write(priv, PMCR_REG(6), pmcr);
+}
+
static int mt7530_setup(struct mtk_eth_priv *priv)
{
u16 phy_addr, phy_val;
@@ -663,11 +737,14 @@
FORCE_DPX | FORCE_LINK;
/* MT7530 Port6: Forced 1000M/FD, FC disabled */
- mt753x_reg_write(priv, PMCR_REG(6), val);
+ priv->mt753x_pmcr = val;
/* MT7530 Port5: Forced link down */
mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE);
+ /* Keep MAC link down before starting eth */
+ mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE);
+
/* MT7530 Port6: Set to RGMII */
mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII);
@@ -823,6 +900,17 @@
}
}
+static void mt7531_mac_control(struct mtk_eth_priv *priv, bool enable)
+{
+ u32 pmcr = FORCE_MODE_LNK;
+
+ if (enable)
+ pmcr = priv->mt753x_pmcr;
+
+ mt753x_reg_write(priv, PMCR_REG(5), pmcr);
+ mt753x_reg_write(priv, PMCR_REG(6), pmcr);
+}
+
static int mt7531_setup(struct mtk_eth_priv *priv)
{
u16 phy_addr, phy_val;
@@ -865,7 +953,7 @@
if (!port5_sgmii)
mt7531_port_rgmii_init(priv, 5);
break;
- case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_2500BASEX:
mt7531_port_sgmii_init(priv, 6);
if (port5_sgmii)
mt7531_port_sgmii_init(priv, 5);
@@ -882,8 +970,11 @@
(SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
FORCE_LINK;
- mt753x_reg_write(priv, PMCR_REG(5), pmcr);
- mt753x_reg_write(priv, PMCR_REG(6), pmcr);
+ priv->mt753x_pmcr = pmcr;
+
+ /* Keep MAC link down before starting eth */
+ mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK);
+ mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
/* Turn on PHYs */
for (i = 0; i < MT753X_NUM_PHYS; i++) {
@@ -904,7 +995,104 @@
return 0;
}
+static void mt7988_phy_setting(struct mtk_eth_priv *priv)
+{
+ u16 val;
+ u32 i;
+
+ for (i = 0; i < MT753X_NUM_PHYS; i++) {
+ /* Enable HW auto downshift */
+ priv->mii_write(priv, i, 0x1f, 0x1);
+ val = priv->mii_read(priv, i, PHY_EXT_REG_14);
+ val |= PHY_EN_DOWN_SHFIT;
+ priv->mii_write(priv, i, PHY_EXT_REG_14, val);
+
+ /* PHY link down power saving enable */
+ val = priv->mii_read(priv, i, PHY_EXT_REG_17);
+ val |= PHY_LINKDOWN_POWER_SAVING_EN;
+ priv->mii_write(priv, i, PHY_EXT_REG_17, val);
+ }
+}
+
+static void mt7988_mac_control(struct mtk_eth_priv *priv, bool enable)
+{
+ u32 pmcr = FORCE_MODE_LNK;
+
+ if (enable)
+ pmcr = priv->mt753x_pmcr;
+
+ mt753x_reg_write(priv, PMCR_REG(6), pmcr);
+}
+
+static int mt7988_setup(struct mtk_eth_priv *priv)
+{
+ u16 phy_addr, phy_val;
+ u32 pmcr;
+ int i;
+
+ priv->gsw_base = regmap_get_range(priv->ethsys_regmap, 0) + GSW_BASE;
+
+ priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) &
+ MT753X_SMI_ADDR_MASK;
+
+ /* Turn off PHYs */
+ for (i = 0; i < MT753X_NUM_PHYS; i++) {
+ phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
+ phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
+ phy_val |= BMCR_PDOWN;
+ priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
+ }
+
+ switch (priv->phy_interface) {
+ case PHY_INTERFACE_MODE_USXGMII:
+ /* Use CPU bridge instead of actual USXGMII path */
+
+ /* Set GDM1 no drop */
+ mtk_fe_rmw(priv, PSE_NO_DROP_CFG_REG, 0, PSE_NO_DROP_GDM1);
+
+ /* Enable GDM1 to GSW CPU bridge */
+ mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, BIT(0));
+
+ /* XGMAC force link up */
+ mtk_gmac_rmw(priv, GMAC_XGMAC_STS_REG, 0, P1_XGMAC_FORCE_LINK);
+
+ /* Setup GSW CPU bridge IPG */
+ mtk_gmac_rmw(priv, GMAC_GSW_CFG_REG, GSWTX_IPG_M | GSWRX_IPG_M,
+ (0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S));
+ break;
+ default:
+ printf("Error: MT7988 GSW does not support %s interface\n",
+ phy_string_for_interface(priv->phy_interface));
+ break;
+ }
+
+ pmcr = MT7988_FORCE_MODE |
+ (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
+ MAC_MODE | MAC_TX_EN | MAC_RX_EN |
+ BKOFF_EN | BACKPR_EN |
+ FORCE_RX_FC | FORCE_TX_FC |
+ (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
+ FORCE_LINK;
+
+ priv->mt753x_pmcr = pmcr;
+
+ /* Keep MAC link down before starting eth */
+ mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
+
+ /* Turn on PHYs */
+ for (i = 0; i < MT753X_NUM_PHYS; i++) {
+ phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
+ phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
+ phy_val &= ~BMCR_PDOWN;
+ priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
+ }
+
+ mt7988_phy_setting(priv);
+
+ return 0;
+}
+
-int mt753x_switch_init(struct mtk_eth_priv *priv)
+static int mt753x_switch_init(struct mtk_eth_priv *priv)
{
int ret;
int i;
@@ -914,12 +1102,12 @@
reset_assert(&priv->rst_mcm);
udelay(1000);
reset_deassert(&priv->rst_mcm);
- mdelay(1000);
+ mdelay(priv->mt753x_reset_wait_time);
} else if (dm_gpio_is_valid(&priv->rst_gpio)) {
dm_gpio_set_value(&priv->rst_gpio, 0);
udelay(1000);
dm_gpio_set_value(&priv->rst_gpio, 1);
- mdelay(1000);
+ mdelay(priv->mt753x_reset_wait_time);
}
ret = priv->switch_init(priv);
@@ -945,6 +1133,42 @@
return 0;
}
+static void mtk_xphy_link_adjust(struct mtk_eth_priv *priv)
+{
+ u16 lcl_adv = 0, rmt_adv = 0;
+ u8 flowctrl;
+ u32 mcr;
+
+ mcr = mtk_gmac_read(priv, XGMAC_PORT_MCR(priv->gmac_id));
+ mcr &= ~(XGMAC_FORCE_TX_FC | XGMAC_FORCE_RX_FC);
+
+ if (priv->phydev->duplex) {
+ if (priv->phydev->pause)
+ rmt_adv = LPA_PAUSE_CAP;
+ if (priv->phydev->asym_pause)
+ rmt_adv |= LPA_PAUSE_ASYM;
+
+ if (priv->phydev->advertising & ADVERTISED_Pause)
+ lcl_adv |= ADVERTISE_PAUSE_CAP;
+ if (priv->phydev->advertising & ADVERTISED_Asym_Pause)
+ lcl_adv |= ADVERTISE_PAUSE_ASYM;
+
+ flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
+
+ if (flowctrl & FLOW_CTRL_TX)
+ mcr |= XGMAC_FORCE_TX_FC;
+ if (flowctrl & FLOW_CTRL_RX)
+ mcr |= XGMAC_FORCE_RX_FC;
+
+ debug("rx pause %s, tx pause %s\n",
+ flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
+ flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
+ }
+
+ mcr &= ~(XGMAC_TRX_DISABLE);
+ mtk_gmac_write(priv, XGMAC_PORT_MCR(priv->gmac_id), mcr);
+}
+
static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
{
u16 lcl_adv = 0, rmt_adv = 0;
@@ -955,6 +1179,7 @@
(MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
MAC_MODE | FORCE_MODE |
MAC_TX_EN | MAC_RX_EN |
+ DEL_RXFIFO_CLR |
BKOFF_EN | BACKPR_EN;
switch (priv->phydev->speed) {
@@ -965,6 +1190,7 @@
mcr |= (SPEED_100M << FORCE_SPD_S);
break;
case SPEED_1000:
+ case SPEED_2500:
mcr |= (SPEED_1000M << FORCE_SPD_S);
break;
};
@@ -1017,7 +1243,12 @@
return 0;
}
- mtk_phy_link_adjust(priv);
+ if (!priv->force_mode) {
+ if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
+ mtk_xphy_link_adjust(priv);
+ else
+ mtk_phy_link_adjust(priv);
+ }
debug("Speed: %d, %s duplex%s\n", phydev->speed,
(phydev->duplex) ? "full" : "half",
@@ -1045,7 +1276,31 @@
return 0;
}
-static void mtk_sgmii_init(struct mtk_eth_priv *priv)
+static void mtk_sgmii_an_init(struct mtk_eth_priv *priv)
+{
+ /* Set SGMII GEN1 speed(1G) */
+ clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
+ SGMSYS_SPEED_2500, 0);
+
+ /* Enable SGMII AN */
+ setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
+ SGMII_AN_ENABLE);
+
+ /* SGMII AN mode setting */
+ writel(SGMII_AN_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
+
+ /* SGMII PN SWAP setting */
+ if (priv->pn_swap) {
+ setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL,
+ SGMII_PN_SWAP_TX_RX);
+ }
+
+ /* Release PHYA power down state */
+ clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
+ SGMII_PHYA_PWD, 0);
+}
+
+static void mtk_sgmii_force_init(struct mtk_eth_priv *priv)
{
/* Set SGMII GEN2 speed(2.5G) */
setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
@@ -1069,6 +1324,112 @@
SGMII_PHYA_PWD, 0);
}
+static void mtk_xfi_pll_enable(struct mtk_eth_priv *priv)
+{
+ u32 val = 0;
+
+ /* Add software workaround for USXGMII PLL TCL issue */
+ regmap_write(priv->xfi_pll_regmap, XFI_PLL_ANA_GLB8,
+ RG_XFI_PLL_ANA_SWWA);
+
+ regmap_read(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, &val);
+ val |= RG_XFI_PLL_EN;
+ regmap_write(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, val);
+}
+
+static void mtk_usxgmii_reset(struct mtk_eth_priv *priv)
+{
+ switch (priv->gmac_id) {
+ case 1:
+ regmap_write(priv->toprgu_regmap, 0xFC, 0x0000A004);
+ regmap_write(priv->toprgu_regmap, 0x18, 0x88F0A004);
+ regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
+ regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
+ regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
+ break;
+ case 2:
+ regmap_write(priv->toprgu_regmap, 0xFC, 0x00005002);
+ regmap_write(priv->toprgu_regmap, 0x18, 0x88F05002);
+ regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
+ regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
+ regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
+ break;
+ }
+
+ mdelay(10);
+}
+
+static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv)
+{
+ regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6D);
+ regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B);
+ regmap_write(priv->usxgmii_regmap, 0x80C, 0x30000000);
+ ndelay(1020);
+ regmap_write(priv->usxgmii_regmap, 0x80C, 0x10000000);
+ ndelay(1020);
+ regmap_write(priv->usxgmii_regmap, 0x80C, 0x00000000);
+
+ regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C);
+ regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA);
+ regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707);
+ regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F);
+ regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032);
+ regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA);
+ regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B);
+ regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF);
+ regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA);
+ regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F);
+ regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68);
+ regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166);
+ regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF);
+ regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D);
+ regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909);
+ regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000);
+ regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000);
+ regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06);
+ regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C);
+ regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000);
+ regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342);
+ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20);
+ regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800);
+ ndelay(1020);
+ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020);
+ regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01);
+ regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884);
+ regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002);
+ regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220);
+ regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01);
+ regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600);
+ regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x40704000);
+ regmap_write(priv->xfi_pextp_regmap, 0x3050, 0xA8000000);
+ regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x000000AA);
+ regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00);
+ regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000);
+ regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800);
+ udelay(150);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111);
+ ndelay(1020);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101);
+ udelay(15);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111);
+ ndelay(1020);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101);
+ udelay(100);
+ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030);
+ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00);
+ regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000);
+ udelay(400);
+}
+
+static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv)
+{
+ mtk_xfi_pll_enable(priv);
+ mtk_usxgmii_reset(priv);
+ mtk_usxgmii_setup_phya_an_10000(priv);
+}
+
static void mtk_mac_init(struct mtk_eth_priv *priv)
{
int i, ge_mode = 0;
@@ -1080,10 +1441,19 @@
ge_mode = GE_MODE_RGMII;
break;
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) {
+ mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK,
+ SGMII_QPHY_SEL);
+ }
+
ge_mode = GE_MODE_RGMII;
mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
SYSCFG0_SGMII_SEL(priv->gmac_id));
- mtk_sgmii_init(priv);
+ if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
+ mtk_sgmii_an_init(priv);
+ else
+ mtk_sgmii_force_init(priv);
break;
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_GMII:
@@ -1117,6 +1487,7 @@
mcr |= SPEED_100M << FORCE_SPD_S;
break;
case SPEED_1000:
+ case SPEED_2500:
mcr |= SPEED_1000M << FORCE_SPD_S;
break;
}
@@ -1141,6 +1512,36 @@
}
}
+static void mtk_xmac_init(struct mtk_eth_priv *priv)
+{
+ u32 sts;
+
+ switch (priv->phy_interface) {
+ case PHY_INTERFACE_MODE_USXGMII:
+ mtk_usxgmii_an_init(priv);
+ break;
+ default:
+ break;
+ }
+
+ /* Set GMAC to the correct mode */
+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
+ SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
+ 0);
+
+ if (priv->gmac_id == 1) {
+ mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX,
+ NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL);
+ } else if (priv->gmac_id == 2) {
+ sts = mtk_gmac_read(priv, XGMAC_STS(priv->gmac_id));
+ sts |= XGMAC_FORCE_LINK;
+ mtk_gmac_write(priv, XGMAC_STS(priv->gmac_id), sts);
+ }
+
+ /* Force GMAC link down */
+ mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE);
+}
+
static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
{
char *pkt_base = priv->pkt_pool;
@@ -1167,7 +1568,10 @@
txd->txd1 = virt_to_phys(pkt_base);
txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0;
- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
+ txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id == 2 ?
+ 15 : priv->gmac_id + 1);
+ else if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id + 1);
else
txd->txd4 = PDMA_V1_TXD4_FPORT_SET(priv->gmac_id + 1);
@@ -1180,7 +1584,8 @@
rxd->rxd1 = virt_to_phys(pkt_base);
- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
+ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
else
rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
@@ -1204,7 +1609,7 @@
static int mtk_eth_start(struct udevice *dev)
{
struct mtk_eth_priv *priv = dev_get_priv(dev);
- int ret;
+ int i, ret;
/* Reset FE */
reset_assert(&priv->rst_fe);
@@ -1212,21 +1617,37 @@
reset_deassert(&priv->rst_fe);
mdelay(10);
- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
+ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
setbits_le32(priv->fe_base + FE_GLO_MISC_REG, PDMA_VER_V2);
/* Packets forward to PDMA */
mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU);
- if (priv->gmac_id == 0)
- mtk_gdma_write(priv, 1, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
- else
- mtk_gdma_write(priv, 0, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
+ for (i = 0; i < priv->soc->gdma_count; i++) {
+ if (i == priv->gmac_id)
+ continue;
+
+ mtk_gdma_write(priv, i, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
+ }
+
+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) {
+ if (priv->sw == SW_MT7988 && priv->gmac_id == 0) {
+ mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG,
+ GDMA_BRIDGE_TO_CPU);
+ }
+
+ mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
+ GDMA_CPU_BRIDGE_EN);
+ }
udelay(500);
mtk_eth_fifo_init(priv);
+ if (priv->switch_mac_control)
+ priv->switch_mac_control(priv, true);
+
/* Start PHY */
if (priv->sw == SW_NONE) {
ret = mtk_phy_start(priv);
@@ -1245,6 +1666,9 @@
{
struct mtk_eth_priv *priv = dev_get_priv(dev);
+ if (priv->switch_mac_control)
+ priv->switch_mac_control(priv, false);
+
mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG,
TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0);
udelay(500);
@@ -1289,7 +1713,8 @@
flush_dcache_range((ulong)pkt_base, (ulong)pkt_base +
roundup(length, ARCH_DMA_MINALIGN));
- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
+ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
txd->txd2 = PDMA_TXD2_LS0 | PDMA_V2_TXD2_SDL0_SET(length);
else
txd->txd2 = PDMA_TXD2_LS0 | PDMA_V1_TXD2_SDL0_SET(length);
@@ -1315,7 +1740,8 @@
return -EAGAIN;
}
- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
+ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
length = PDMA_V2_RXD2_PLEN0_GET(rxd->rxd2);
else
length = PDMA_V1_RXD2_PLEN0_GET(rxd->rxd2);
@@ -1338,7 +1764,8 @@
rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size;
- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
+ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
else
rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
@@ -1376,7 +1803,10 @@
ARCH_DMA_MINALIGN);
/* Set MAC mode */
- mtk_mac_init(priv);
+ if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
+ mtk_xmac_init(priv);
+ else
+ mtk_mac_init(priv);
/* Probe phy if switch is not specified */
if (priv->sw == SW_NONE)
@@ -1428,6 +1858,19 @@
if (IS_ERR(priv->ethsys_regmap))
return PTR_ERR(priv->ethsys_regmap);
+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_INFRA)) {
+ /* get corresponding infracfg phandle */
+ ret = dev_read_phandle_with_args(dev, "mediatek,infracfg",
+ NULL, 0, 0, &args);
+
+ if (ret)
+ return ret;
+
+ priv->infra_regmap = syscon_node_to_regmap(args.node);
+ if (IS_ERR(priv->infra_regmap))
+ return PTR_ERR(priv->infra_regmap);
+ }
+
/* Reset controllers */
ret = reset_get_by_name(dev, "fe", &priv->rst_fe);
if (ret) {
@@ -1453,13 +1896,15 @@
priv->duplex = ofnode_read_bool(subnode, "full-duplex");
if (priv->speed != SPEED_10 && priv->speed != SPEED_100 &&
- priv->speed != SPEED_1000) {
+ priv->speed != SPEED_1000 && priv->speed != SPEED_2500 &&
+ priv->speed != SPEED_10000) {
printf("error: no valid speed set in fixed-link\n");
return -EINVAL;
}
}
- if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
/* get corresponding sgmii phandle */
ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys",
NULL, 0, 0, &args);
@@ -1479,22 +1924,73 @@
}
priv->pn_swap = ofnode_read_bool(args.node, "pn_swap");
+ } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
+ /* get corresponding usxgmii phandle */
+ ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys",
+ NULL, 0, 0, &args);
+ if (ret)
+ return ret;
+
+ priv->usxgmii_regmap = syscon_node_to_regmap(args.node);
+ if (IS_ERR(priv->usxgmii_regmap))
+ return PTR_ERR(priv->usxgmii_regmap);
+
+ /* get corresponding xfi_pextp phandle */
+ ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pextp",
+ NULL, 0, 0, &args);
+ if (ret)
+ return ret;
+
+ priv->xfi_pextp_regmap = syscon_node_to_regmap(args.node);
+ if (IS_ERR(priv->xfi_pextp_regmap))
+ return PTR_ERR(priv->xfi_pextp_regmap);
+
+ /* get corresponding xfi_pll phandle */
+ ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pll",
+ NULL, 0, 0, &args);
+ if (ret)
+ return ret;
+
+ priv->xfi_pll_regmap = syscon_node_to_regmap(args.node);
+ if (IS_ERR(priv->xfi_pll_regmap))
+ return PTR_ERR(priv->xfi_pll_regmap);
+
+ /* get corresponding toprgu phandle */
+ ret = dev_read_phandle_with_args(dev, "mediatek,toprgu",
+ NULL, 0, 0, &args);
+ if (ret)
+ return ret;
+
+ priv->toprgu_regmap = syscon_node_to_regmap(args.node);
+ if (IS_ERR(priv->toprgu_regmap))
+ return PTR_ERR(priv->toprgu_regmap);
}
/* check for switch first, otherwise phy will be used */
priv->sw = SW_NONE;
priv->switch_init = NULL;
+ priv->switch_mac_control = NULL;
str = dev_read_string(dev, "mediatek,switch");
if (str) {
if (!strcmp(str, "mt7530")) {
priv->sw = SW_MT7530;
priv->switch_init = mt7530_setup;
+ priv->switch_mac_control = mt7530_mac_control;
priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
+ priv->mt753x_reset_wait_time = 1000;
} else if (!strcmp(str, "mt7531")) {
priv->sw = SW_MT7531;
priv->switch_init = mt7531_setup;
+ priv->switch_mac_control = mt7531_mac_control;
priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
+ priv->mt753x_reset_wait_time = 200;
+ } else if (!strcmp(str, "mt7988")) {
+ priv->sw = SW_MT7988;
+ priv->switch_init = mt7988_setup;
+ priv->switch_mac_control = mt7988_mac_control;
+ priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
+ priv->mt753x_reset_wait_time = 50;
} else {
printf("error: unsupported switch\n");
return -EINVAL;
@@ -1529,17 +2025,28 @@
return 0;
}
+static const struct mtk_soc_data mt7988_data = {
+ .caps = MT7988_CAPS,
+ .ana_rgc3 = 0x128,
+ .gdma_count = 3,
+ .pdma_base = PDMA_V3_BASE,
+ .txd_size = sizeof(struct mtk_tx_dma_v2),
+ .rxd_size = sizeof(struct mtk_rx_dma_v2),
+};
+
static const struct mtk_soc_data mt7986_data = {
.caps = MT7986_CAPS,
.ana_rgc3 = 0x128,
+ .gdma_count = 2,
.pdma_base = PDMA_V2_BASE,
.txd_size = sizeof(struct mtk_tx_dma_v2),
.rxd_size = sizeof(struct mtk_rx_dma_v2),
};
static const struct mtk_soc_data mt7981_data = {
- .caps = MT7986_CAPS,
+ .caps = MT7981_CAPS,
.ana_rgc3 = 0x128,
+ .gdma_count = 2,
.pdma_base = PDMA_V2_BASE,
.txd_size = sizeof(struct mtk_tx_dma_v2),
.rxd_size = sizeof(struct mtk_rx_dma_v2),
@@ -1547,6 +2054,7 @@
static const struct mtk_soc_data mt7629_data = {
.ana_rgc3 = 0x128,
+ .gdma_count = 2,
.pdma_base = PDMA_V1_BASE,
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
@@ -1554,6 +2062,7 @@
static const struct mtk_soc_data mt7623_data = {
.caps = MT7623_CAPS,
+ .gdma_count = 2,
.pdma_base = PDMA_V1_BASE,
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
@@ -1561,6 +2070,7 @@
static const struct mtk_soc_data mt7622_data = {
.ana_rgc3 = 0x2028,
+ .gdma_count = 2,
.pdma_base = PDMA_V1_BASE,
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
@@ -1568,12 +2078,14 @@
static const struct mtk_soc_data mt7621_data = {
.caps = MT7621_CAPS,
+ .gdma_count = 2,
.pdma_base = PDMA_V1_BASE,
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
};
static const struct udevice_id mtk_eth_ids[] = {
+ { .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data },
{ .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data },
{ .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data },
{ .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data },
diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h
index 1382ccb..491cac5 100644
--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
@@ -15,35 +15,53 @@
enum mkt_eth_capabilities {
MTK_TRGMII_BIT,
MTK_TRGMII_MT7621_CLK_BIT,
+ MTK_U3_COPHY_V2_BIT,
+ MTK_INFRA_BIT,
MTK_NETSYS_V2_BIT,
+ MTK_NETSYS_V3_BIT,
/* PATH BITS */
MTK_ETH_PATH_GMAC1_TRGMII_BIT,
+ MTK_ETH_PATH_GMAC2_SGMII_BIT,
};
#define MTK_TRGMII BIT(MTK_TRGMII_BIT)
#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
+#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT)
+#define MTK_INFRA BIT(MTK_INFRA_BIT)
#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
+#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT)
/* Supported path present on SoCs */
#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
+#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
+
#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
+#define MTK_GMAC2_U3_QPHY (MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA)
+
#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
#define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK)
#define MT7623_CAPS (MTK_GMAC1_TRGMII)
+#define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2)
+
#define MT7986_CAPS (MTK_NETSYS_V2)
+#define MT7988_CAPS (MTK_NETSYS_V3 | MTK_INFRA)
+
/* Frame Engine Register Bases */
#define PDMA_V1_BASE 0x0800
#define PDMA_V2_BASE 0x6000
+#define PDMA_V3_BASE 0x6800
#define GDMA1_BASE 0x0500
#define GDMA2_BASE 0x1500
+#define GDMA3_BASE 0x0540
#define GMAC_BASE 0x10000
+#define GSW_BASE 0x20000
/* Ethernet subsystem registers */
@@ -56,6 +74,16 @@
#define ETHSYS_CLKCFG0_REG 0x2c
#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
+/* Top misc registers */
+#define TOPMISC_NETSYS_PCS_MUX 0x84
+#define NETSYS_PCS_MUX_MASK GENMASK(1, 0)
+#define MUX_G2_USXGMII_SEL BIT(1)
+#define MUX_HSGMII1_G1_SEL BIT(0)
+
+#define USB_PHY_SWITCH_REG 0x218
+#define QPHY_SEL_MASK 0x3
+#define SGMII_QPHY_SEL 0x2
+
/* SYSCFG0_GE_MODE: GE Modes */
#define GE_MODE_RGMII 0
#define GE_MODE_MII 1
@@ -69,6 +97,7 @@
#define SGMII_AN_RESTART BIT(9)
#define SGMSYS_SGMII_MODE 0x20
+#define SGMII_AN_MODE 0x31120103
#define SGMII_FORCE_MODE 0x31120019
#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
@@ -81,7 +110,19 @@
#define SGMSYS_GEN2_SPEED_V2 0x128
#define SGMSYS_SPEED_2500 BIT(2)
+/* USXGMII subsystem config registers */
+/* Register to control USXGMII XFI PLL digital */
+#define XFI_PLL_DIG_GLB8 0x08
+#define RG_XFI_PLL_EN BIT(31)
+
+/* Register to control USXGMII XFI PLL analog */
+#define XFI_PLL_ANA_GLB8 0x108
+#define RG_XFI_PLL_ANA_SWWA 0x02283248
+
/* Frame Engine Registers */
+#define PSE_NO_DROP_CFG_REG 0x108
+#define PSE_NO_DROP_GDM1 BIT(1)
+
#define FE_GLO_MISC_REG 0x124
#define PDMA_VER_V2 BIT(4)
@@ -122,6 +163,9 @@
#define UN_DP_S 0
#define UN_DP_M 0x0f
+#define GDMA_EG_CTRL_REG 0x004
+#define GDMA_CPU_BRIDGE_EN BIT(31)
+
#define GDMA_MAC_LSB_REG 0x008
#define GDMA_MAC_MSB_REG 0x00c
@@ -149,6 +193,17 @@
#define MDIO_RW_DATA_S 0
#define MDIO_RW_DATA_M 0xffff
+#define GMAC_XGMAC_STS_REG 0x000c
+#define P1_XGMAC_FORCE_LINK BIT(15)
+
+#define GMAC_MAC_MISC_REG 0x0010
+
+#define GMAC_GSW_CFG_REG 0x0080
+#define GSWTX_IPG_M 0xF0000
+#define GSWTX_IPG_S 16
+#define GSWRX_IPG_M 0xF
+#define GSWRX_IPG_S 0
+
/* MDIO_CMD: MDIO commands */
#define MDIO_CMD_ADDR 0
#define MDIO_CMD_WRITE 1
@@ -168,6 +223,7 @@
#define FORCE_MODE BIT(15)
#define MAC_TX_EN BIT(14)
#define MAC_RX_EN BIT(13)
+#define DEL_RXFIFO_CLR BIT(12)
#define BKOFF_EN BIT(9)
#define BACKPR_EN BIT(8)
#define FORCE_RX_FC BIT(5)
@@ -203,6 +259,16 @@
#define TD_DM_DRVP_S 0
#define TD_DM_DRVP_M 0x0f
+/* XGMAC Status Registers */
+#define XGMAC_STS(x) (((x) == 2) ? 0x001C : 0x000C)
+#define XGMAC_FORCE_LINK BIT(15)
+
+/* XGMAC Registers */
+#define XGMAC_PORT_MCR(x) (0x2000 + (((x) - 1) * 0x1000))
+#define XGMAC_TRX_DISABLE 0xf
+#define XGMAC_FORCE_TX_FC BIT(5)
+#define XGMAC_FORCE_RX_FC BIT(4)
+
/* MT7530 Registers */
#define PCR_REG(p) (0x2004 + (p) * 0x100)
@@ -236,6 +302,9 @@
FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
FORCE_MODE_DPX | FORCE_MODE_SPD | \
FORCE_MODE_LNK
+#define MT7988_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
+ FORCE_MODE_DPX | FORCE_MODE_SPD | \
+ FORCE_MODE_LNK
/* MT7531 SGMII Registers */
#define MT7531_SGMII_REG_BASE 0x5000
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 2276a46..9637027 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -96,12 +96,12 @@
#define TX_TIMEOUT (6*HZ)
/* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
-#define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg))
-#define RTL_W16(reg, val16) writew((val16), ioaddr + (reg))
-#define RTL_W32(reg, val32) writel((val32), ioaddr + (reg))
-#define RTL_R8(reg) readb(ioaddr + (reg))
-#define RTL_R16(reg) readw(ioaddr + (reg))
-#define RTL_R32(reg) readl(ioaddr + (reg))
+#define RTL_W8(reg, val8) writeb((val8), (void *)(ioaddr + (reg)))
+#define RTL_W16(reg, val16) writew((val16), (void *)(ioaddr + (reg)))
+#define RTL_W32(reg, val32) writel((val32), (void *)(ioaddr + (reg)))
+#define RTL_R8(reg) readb((void *)(ioaddr + (reg)))
+#define RTL_R16(reg) readw((void *)(ioaddr + (reg)))
+#define RTL_R32(reg) readl((void *)(ioaddr + (reg)))
#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
(pci_addr_t)(unsigned long)a)
@@ -311,10 +311,12 @@
*
* This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
* the driver to allocate descriptors from a pool of non-cached memory.
+ *
+ * Hardware maintain D-cache coherency in RISC-V architecture.
*/
#if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
- !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
+ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86) && !defined(CONFIG_RISCV)
#warning cache-line size is larger than descriptor size
#endif
#endif
@@ -351,10 +353,11 @@
(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
static struct pci_device_id supported[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8125) },
+ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161) },
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) },
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) },
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) },
- { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8125) },
{}
};
@@ -1049,8 +1052,9 @@
int ret;
switch (pplat->device) {
- case 0x8168:
case 0x8125:
+ case 0x8161:
+ case 0x8168:
region = 2;
break;
default:
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index 51a8167..f4e5809 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <malloc.h>
#include <asm/cache.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <clk.h>
@@ -26,6 +27,7 @@
#include <soc.h>
#include <syscon.h>
#include <linux/bitops.h>
+#include <linux/delay.h>
#include <linux/soc/ti/ti-udma.h>
#include "cpsw_mdio.h"
@@ -57,6 +59,12 @@
#define AM65_CPSW_PN_REG_SA_L 0x308
#define AM65_CPSW_PN_REG_SA_H 0x30c
+#define AM65_CPSW_SGMII_CONTROL_REG 0x010
+#define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018
+#define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0)
+
+#define ADVERTISE_SGMII 0x1
+
#define AM65_CPSW_ALE_CTL_REG 0x8
#define AM65_CPSW_ALE_CTL_REG_ENABLE BIT(31)
#define AM65_CPSW_ALE_CTL_REG_RESET_TBL BIT(30)
@@ -90,8 +98,11 @@
#define AM65_CPSW_CPPI_PKT_TYPE 0x7
+#define DEFAULT_GPIO_RESET_DELAY 10
+
struct am65_cpsw_port {
fdt_addr_t port_base;
+ fdt_addr_t port_sgmii_base;
fdt_addr_t macsl_base;
bool disabled;
u32 mac_control;
@@ -113,6 +124,10 @@
struct mii_dev *bus;
u32 bus_freq;
+ struct gpio_desc mdio_gpio_reset;
+ u32 reset_delay_us;
+ u32 reset_post_delay_us;
+
struct dma dma_tx;
struct dma dma_rx;
u32 rx_next;
@@ -204,6 +219,8 @@
mac_control |= AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX;
if (phy->speed == 100)
mac_control |= AM65_CPSW_MACSL_CTL_REG_IFCTL_A;
+ if (phy->interface == PHY_INTERFACE_MODE_SGMII)
+ mac_control |= AM65_CPSW_MACSL_CTL_EXT_EN;
}
if (mac_control == port->mac_control)
@@ -229,6 +246,7 @@
#define AM65_GMII_SEL_MODE_MII 0
#define AM65_GMII_SEL_MODE_RMII 1
#define AM65_GMII_SEL_MODE_RGMII 2
+#define AM65_GMII_SEL_MODE_SGMII 3
#define AM65_GMII_SEL_RGMII_IDMODE BIT(4)
@@ -280,6 +298,10 @@
rgmii_id = true;
break;
+ case PHY_INTERFACE_MODE_SGMII:
+ mode = AM65_GMII_SEL_MODE_SGMII;
+ break;
+
default:
dev_warn(dev,
"Unsupported PHY mode: %u. Defaulting to MII.\n",
@@ -420,6 +442,13 @@
goto err_dis_rx;
}
+ if (priv->phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+ writel(ADVERTISE_SGMII,
+ port->port_sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG);
+ writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE,
+ port->port_sgmii_base + AM65_CPSW_SGMII_CONTROL_REG);
+ }
+
ret = phy_startup(priv->phydev);
if (ret) {
dev_err(dev, "phy_startup failed\n");
@@ -658,6 +687,16 @@
if (!priv->has_phy || cpsw_common->bus)
return 0;
+ if (IS_ENABLED(CONFIG_DM_GPIO)) {
+ if (dm_gpio_is_valid(&cpsw_common->mdio_gpio_reset)) {
+ dm_gpio_set_value(&cpsw_common->mdio_gpio_reset, 1);
+ udelay(cpsw_common->reset_delay_us);
+ dm_gpio_set_value(&cpsw_common->mdio_gpio_reset, 0);
+ if (cpsw_common->reset_post_delay_us > 0)
+ udelay(cpsw_common->reset_post_delay_us);
+ }
+ }
+
ret = am65_cpsw_mdio_setup(dev);
if (ret)
return ret;
@@ -797,7 +836,7 @@
static int am65_cpsw_probe_nuss(struct udevice *dev)
{
struct am65_cpsw_common *cpsw_common = dev_get_priv(dev);
- ofnode ports_np, node;
+ ofnode ports_np, node, mdio_np;
int ret, i;
struct udevice *port_dev;
@@ -824,6 +863,24 @@
AM65_CPSW_CPSW_NU_ALE_BASE;
cpsw_common->mdio_base = cpsw_common->ss_base + AM65_CPSW_MDIO_BASE;
+ if (IS_ENABLED(CONFIG_DM_GPIO)) {
+ /* get bus level PHY reset GPIO details */
+ mdio_np = dev_read_subnode(dev, "mdio");
+ if (!ofnode_valid(mdio_np)) {
+ ret = -ENOENT;
+ goto out;
+ }
+
+ cpsw_common->reset_delay_us = ofnode_read_u32_default(mdio_np, "reset-delay-us",
+ DEFAULT_GPIO_RESET_DELAY);
+ cpsw_common->reset_post_delay_us = ofnode_read_u32_default(mdio_np,
+ "reset-post-delay-us",
+ 0);
+ ret = gpio_request_by_name_nodev(mdio_np, "reset-gpios", 0,
+ &cpsw_common->mdio_gpio_reset,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ }
+
ports_np = dev_read_subnode(dev, "ethernet-ports");
if (!ofnode_valid(ports_np)) {
ret = -ENOENT;
@@ -872,6 +929,8 @@
port->port_base = cpsw_common->cpsw_base +
AM65_CPSW_CPSW_NU_PORTS_OFFSET +
(i * AM65_CPSW_CPSW_NU_PORTS_OFFSET);
+ port->port_sgmii_base = cpsw_common->ss_base +
+ (i * AM65_CPSW_SGMII_BASE);
port->macsl_base = port->port_base +
AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET;
}
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index a7add66..20dc910 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -910,7 +910,7 @@
if (ret)
goto free_id;
- ret = bootdev_setup_sibling_blk(ns_udev, "nvme_bootdev");
+ ret = bootdev_setup_for_sibling_blk(ns_udev, "nvme_bootdev");
if (ret)
return log_msg_ret("bootdev", ret);
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 93e6f50..463ec47 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -121,11 +121,18 @@
bool "Enable Apple PCIe driver"
depends on ARCH_APPLE
imply PCI_INIT_R
+ select SYS_PCI_64BIT
default y
help
Say Y here if you want to enable PCIe controller support on
Apple SoCs.
+config PCI_FTPCI100
+ bool "Enable Faraday FTPCI100 PCI Bridge Controller driver"
+ help
+ Say Y here if you want to enable Faraday FTPCI100 PCI.
+ FTPCI100 IP is used in SoC chip designs.
+
config PCI_GT64120
bool "GT64120 PCI support"
depends on MIPS
@@ -393,4 +400,17 @@
Say 'Y' here if you want support for Xilinx / AMD NWL PCIe
controller as Root Port.
+config PCIE_PLDA_COMMON
+ bool
+
+config PCIE_STARFIVE_JH7110
+ bool "Enable Starfive JH7110 PCIe driver"
+ select PCIE_PLDA_COMMON
+ imply STARFIVE_JH7110
+ imply CLK_JH7110
+ imply RESET_JH7110
+ help
+ Say Y here if you want to enable PLDA XpressRich PCIe controller
+ support on StarFive JH7110 SoC.
+
endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 11f60c6..72ef8b4 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -14,6 +14,7 @@
obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o
obj-$(CONFIG_PCIE_ECAM_SYNQUACER) += pcie_ecam_synquacer.o
obj-$(CONFIG_PCIE_APPLE) += pcie_apple.o
+obj-$(CONFIG_PCI_FTPCI100) += pci_ftpci100.o
obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
obj-$(CONFIG_PCI_MPC85XX) += pci_mpc85xx.o
obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
@@ -50,3 +51,5 @@
obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
+obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o
+obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 632c1a6..0adcdce 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -541,14 +541,13 @@
struct pci_child_plat *pplat;
unsigned int sub_bus;
struct udevice *dev;
- int ret;
sub_bus = dev_seq(bus);
debug("%s: start\n", __func__);
pciauto_config_init(hose);
- for (ret = device_find_first_child(bus, &dev);
- !ret && dev;
- ret = device_find_next_child(&dev)) {
+ for (device_find_first_child(bus, &dev);
+ dev;
+ device_find_next_child(&dev)) {
unsigned int max_bus;
int ret;
@@ -1446,7 +1445,7 @@
return res->phys_start + offset;
}
- puts("pci_hose_bus_to_phys: invalid physical address\n");
+ puts("dm_pci_bus_to_phys: invalid physical address\n");
return 0;
}
@@ -1486,7 +1485,7 @@
return res->bus_start + offset;
}
- puts("pci_hose_phys_to_bus: invalid physical address\n");
+ puts("dm_pci_phys_to_bus: invalid physical address\n");
return 0;
}
diff --git a/drivers/pci/pci_ftpci100.c b/drivers/pci/pci_ftpci100.c
new file mode 100644
index 0000000..a177544
--- /dev/null
+++ b/drivers/pci/pci_ftpci100.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <common.h>
+#include <pci.h>
+#include <dm.h>
+#include <asm/io.h>
+
+struct ftpci100_data {
+ void *reg_base;
+};
+
+/* AHB Control Registers */
+struct ftpci100_ahbc {
+ u32 iosize; /* 0x00 - I/O Space Size Signal */
+ u32 prot; /* 0x04 - AHB Protection */
+ u32 rsved[8]; /* 0x08-0x24 - Reserved */
+ u32 conf; /* 0x28 - PCI Configuration */
+ u32 data; /* 0x2c - PCI Configuration DATA */
+};
+
+static int ftpci100_read_config(const struct udevice *dev, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ struct ftpci100_data *priv = dev_get_priv(dev);
+ struct ftpci100_ahbc *regs = priv->reg_base;
+ u32 data;
+
+ out_le32(®s->conf, PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset));
+ data = in_le32(®s->data);
+ *valuep = pci_conv_32_to_size(data, offset, size);
+
+ return 0;
+}
+
+static int ftpci100_write_config(struct udevice *dev, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ struct ftpci100_data *priv = dev_get_priv(dev);
+ struct ftpci100_ahbc *regs = priv->reg_base;
+ u32 data;
+
+ out_le32(®s->conf, PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset));
+
+ if (size == PCI_SIZE_32) {
+ data = value;
+ } else {
+ u32 old = in_le32(®s->data);
+
+ data = pci_conv_size_to_32(old, value, offset, size);
+ }
+
+ out_le32(®s->data, data);
+
+ return 0;
+}
+
+static int ftpci100_probe(struct udevice *dev)
+{
+ struct ftpci100_data *priv = dev_get_priv(dev);
+ struct pci_region *io, *mem;
+ int count;
+
+ count = pci_get_regions(dev, &io, &mem, NULL);
+ if (count != 2) {
+ printf("%s: wrong count of regions: %d != 2\n", dev->name, count);
+ return -EINVAL;
+ }
+
+ priv->reg_base = phys_to_virt(io->phys_start);
+ if (!priv->reg_base)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dm_pci_ops ftpci100_ops = {
+ .read_config = ftpci100_read_config,
+ .write_config = ftpci100_write_config,
+};
+
+static const struct udevice_id ftpci100_ids[] = {
+ { .compatible = "faraday,ftpci100" },
+ { }
+};
+
+U_BOOT_DRIVER(ftpci100_pci) = {
+ .name = "ftpci100_pci",
+ .id = UCLASS_PCI,
+ .of_match = ftpci100_ids,
+ .ops = &ftpci100_ops,
+ .probe = ftpci100_probe,
+ .priv_auto = sizeof(struct ftpci100_data),
+};
diff --git a/drivers/pci/pcie_plda_common.c b/drivers/pci/pcie_plda_common.c
new file mode 100644
index 0000000..cd74bb4
--- /dev/null
+++ b/drivers/pci/pcie_plda_common.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PLDA XpressRich PCIe host controller common functions.
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ *
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <pci.h>
+#include <pci_ids.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include "pcie_plda_common.h"
+
+static bool plda_pcie_addr_valid(struct pcie_plda *plda, pci_dev_t bdf)
+{
+ /*
+ * Single device limitation.
+ * PCIe controller contain HW issue that secondary bus of
+ * host bridge emumerate duplicate devices.
+ * Only can access device 0 in secondary bus.
+ */
+ if (PCI_BUS(bdf) == plda->sec_busno && PCI_DEV(bdf) > 0)
+ return false;
+
+ return true;
+}
+
+static int plda_pcie_conf_address(const struct udevice *udev, pci_dev_t bdf,
+ uint offset, void **paddr)
+{
+ struct pcie_plda *priv = dev_get_priv(udev);
+ int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf) - dev_seq(udev),
+ PCI_DEV(bdf), PCI_FUNC(bdf), offset);
+
+ if (!plda_pcie_addr_valid(priv, bdf))
+ return -ENODEV;
+
+ *paddr = (void *)(priv->cfg_base + where);
+ return 0;
+}
+
+int plda_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ return pci_generic_mmap_read_config(udev, plda_pcie_conf_address,
+ bdf, offset, valuep, size);
+}
+
+int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ struct pcie_plda *priv = dev_get_priv(udev);
+ int ret;
+
+ ret = pci_generic_mmap_write_config(udev, plda_pcie_conf_address,
+ bdf, offset, value, size);
+
+ /* record secondary bus number */
+ if (!ret && PCI_BUS(bdf) == dev_seq(udev) &&
+ PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+ (offset == PCI_SECONDARY_BUS ||
+ (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))) {
+ priv->sec_busno =
+ ((offset == PCI_PRIMARY_BUS) ? (value >> 8) : value) & 0xff;
+ priv->sec_busno += dev_seq(udev);
+ debug("Secondary bus number was changed to %d\n",
+ priv->sec_busno);
+ }
+ return ret;
+}
+
+int plda_pcie_set_atr_entry(struct pcie_plda *plda, phys_addr_t src_addr,
+ phys_addr_t trsl_addr, phys_size_t window_size,
+ int trsl_param)
+{
+ void __iomem *base =
+ plda->reg_base + XR3PCI_ATR_AXI4_SLV0;
+
+ /* Support AXI4 Slave 0 Address Translation Tables 0-7. */
+ if (plda->atr_table_num >= XR3PCI_ATR_MAX_TABLE_NUM) {
+ dev_err(plda->dev, "ATR table number %d exceeds max num\n",
+ plda->atr_table_num);
+ return -EINVAL;
+ }
+ base += XR3PCI_ATR_TABLE_OFFSET * plda->atr_table_num;
+ plda->atr_table_num++;
+
+ /*
+ * X3PCI_ATR_SRC_ADDR_LOW:
+ * - bit 0: enable entry,
+ * - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
+ * - bits 7-11: reserved
+ * - bits 12-31: start of source address
+ */
+ writel((lower_32_bits(src_addr) & XR3PCI_ATR_SRC_ADDR_MASK) |
+ (fls(window_size) - 1) << XR3PCI_ATR_SRC_WIN_SIZE_SHIFT | 1,
+ base + XR3PCI_ATR_SRC_ADDR_LOW);
+ writel(upper_32_bits(src_addr), base + XR3PCI_ATR_SRC_ADDR_HIGH);
+ writel((lower_32_bits(trsl_addr) & XR3PCI_ATR_TRSL_ADDR_MASK),
+ base + XR3PCI_ATR_TRSL_ADDR_LOW);
+ writel(upper_32_bits(trsl_addr), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
+ writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
+
+ dev_dbg(plda->dev, "ATR entry: 0x%010llx %s 0x%010llx [0x%010llx] (param: 0x%06x)\n",
+ src_addr, (trsl_param & XR3PCI_ATR_TRSL_DIR) ? "<-" : "->",
+ trsl_addr, (u64)window_size, trsl_param);
+ return 0;
+}
diff --git a/drivers/pci/pcie_plda_common.h b/drivers/pci/pcie_plda_common.h
new file mode 100644
index 0000000..409949f
--- /dev/null
+++ b/drivers/pci/pcie_plda_common.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Minda Chen <minda.chen@starfivetech.com>
+ *
+ */
+
+#ifndef PCIE_PLDA_COMMON_H
+#define PCIE_PLDA_COMMON_H
+
+#define GEN_SETTINGS 0x80
+#define PCIE_PCI_IDS 0x9C
+#define PCIE_WINROM 0xFC
+#define PMSG_SUPPORT_RX 0x3F0
+#define PCI_MISC 0xB4
+
+#define PLDA_EP_ENABLE 0
+#define PLDA_RP_ENABLE 1
+
+#define IDS_CLASS_CODE_SHIFT 8
+
+#define PREF_MEM_WIN_64_SUPPORT BIT(3)
+#define PMSG_LTR_SUPPORT BIT(2)
+#define PLDA_FUNCTION_DIS BIT(15)
+#define PLDA_FUNC_NUM 4
+#define PLDA_PHY_FUNC_SHIFT 9
+
+#define XR3PCI_ATR_AXI4_SLV0 0x800
+#define XR3PCI_ATR_SRC_ADDR_LOW 0x0
+#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
+#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
+#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
+#define XR3PCI_ATR_TRSL_PARAM 0x10
+#define XR3PCI_ATR_TABLE_OFFSET 0x20
+#define XR3PCI_ATR_MAX_TABLE_NUM 8
+
+#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
+#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12)
+#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12)
+#define XR3PCI_ATR_TRSL_DIR BIT(22)
+/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
+#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
+#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
+
+/**
+ * struct pcie_plda - PLDA PCIe controller state
+ *
+ * @reg_base: The base address of controller register space
+ * @cfg_base: The base address of configuration space
+ * @cfg_size: The size of configuration space
+ * @sec_busno: Secondary bus number.
+ * @atr_table_num: Total ATR table numbers.
+ */
+struct pcie_plda {
+ struct udevice *dev;
+ void __iomem *reg_base;
+ void __iomem *cfg_base;
+ phys_size_t cfg_size;
+ int sec_busno;
+ int atr_table_num;
+};
+
+int plda_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size);
+int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size);
+int plda_pcie_set_atr_entry(struct pcie_plda *plda, phys_addr_t src_addr,
+ phys_addr_t trsl_addr, phys_size_t window_size,
+ int trsl_param);
+
+static inline void plda_pcie_enable_root_port(struct pcie_plda *plda)
+{
+ u32 value;
+
+ value = readl(plda->reg_base + GEN_SETTINGS);
+ value |= PLDA_RP_ENABLE;
+ writel(value, plda->reg_base + GEN_SETTINGS);
+}
+
+static inline void plda_pcie_set_standard_class(struct pcie_plda *plda)
+{
+ u32 value;
+
+ value = readl(plda->reg_base + PCIE_PCI_IDS);
+ value &= 0xff;
+ value |= (PCI_CLASS_BRIDGE_PCI_NORMAL << IDS_CLASS_CODE_SHIFT);
+ writel(value, plda->reg_base + PCIE_PCI_IDS);
+}
+
+static inline void plda_pcie_set_pref_win_64bit(struct pcie_plda *plda)
+{
+ u32 value;
+
+ value = readl(plda->reg_base + PCIE_WINROM);
+ value |= PREF_MEM_WIN_64_SUPPORT;
+ writel(value, plda->reg_base + PCIE_WINROM);
+}
+
+static inline void plda_pcie_disable_ltr(struct pcie_plda *plda)
+{
+ u32 value;
+
+ value = readl(plda->reg_base + PMSG_SUPPORT_RX);
+ value &= ~PMSG_LTR_SUPPORT;
+ writel(value, plda->reg_base + PMSG_SUPPORT_RX);
+}
+
+static inline void plda_pcie_disable_func(struct pcie_plda *plda)
+{
+ u32 value;
+
+ value = readl(plda->reg_base + PCI_MISC);
+ value |= PLDA_FUNCTION_DIS;
+ writel(value, plda->reg_base + PCI_MISC);
+}
+#endif
diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c
index 72b4139..624841e 100644
--- a/drivers/pci/pcie_rockchip.c
+++ b/drivers/pci/pcie_rockchip.c
@@ -12,23 +12,15 @@
*/
#include <common.h>
-#include <clk.h>
#include <dm.h>
-#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <generic-phy.h>
#include <pci.h>
-#include <power-domain.h>
#include <power/regulator.h>
#include <reset.h>
-#include <syscon.h>
-#include <asm/io.h>
#include <asm-generic/gpio.h>
-#include <asm/arch-rockchip/clock.h>
#include <linux/iopoll.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
@@ -383,41 +375,38 @@
struct rockchip_pcie *priv = dev_get_priv(dev);
int ret;
- if (priv->vpcie3v3) {
- ret = regulator_set_enable(priv->vpcie3v3, true);
- if (ret) {
- dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n",
- ret);
- return ret;
- }
+ ret = regulator_set_enable_if_allowed(priv->vpcie12v, true);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "failed to enable vpcie12v (ret=%d)\n", ret);
+ return ret;
}
- if (priv->vpcie1v8) {
- ret = regulator_set_enable(priv->vpcie1v8, true);
- if (ret) {
- dev_err(dev, "failed to enable vpcie1v8 (ret=%d)\n",
- ret);
- goto err_disable_3v3;
- }
+ ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n", ret);
+ goto err_disable_12v;
}
- if (priv->vpcie0v9) {
- ret = regulator_set_enable(priv->vpcie0v9, true);
- if (ret) {
- dev_err(dev, "failed to enable vpcie0v9 (ret=%d)\n",
- ret);
- goto err_disable_1v8;
- }
+ ret = regulator_set_enable_if_allowed(priv->vpcie1v8, true);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "failed to enable vpcie1v8 (ret=%d)\n", ret);
+ goto err_disable_3v3;
+ }
+
+ ret = regulator_set_enable_if_allowed(priv->vpcie0v9, true);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "failed to enable vpcie0v9 (ret=%d)\n", ret);
+ goto err_disable_1v8;
}
return 0;
err_disable_1v8:
- if (priv->vpcie1v8)
- regulator_set_enable(priv->vpcie1v8, false);
+ regulator_set_enable_if_allowed(priv->vpcie1v8, false);
err_disable_3v3:
- if (priv->vpcie3v3)
- regulator_set_enable(priv->vpcie3v3, false);
+ regulator_set_enable_if_allowed(priv->vpcie3v3, false);
+err_disable_12v:
+ regulator_set_enable_if_allowed(priv->vpcie12v, false);
return ret;
}
@@ -427,19 +416,12 @@
int ret;
priv->axi_base = dev_read_addr_name(dev, "axi-base");
- if (!priv->axi_base)
- return -ENODEV;
+ if (priv->axi_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
priv->apb_base = dev_read_addr_name(dev, "apb-base");
- if (!priv->axi_base)
- return -ENODEV;
-
- ret = gpio_request_by_name(dev, "ep-gpios", 0,
- &priv->ep_gpio, GPIOD_IS_OUT);
- if (ret) {
- dev_err(dev, "failed to find ep-gpios property\n");
- return ret;
- }
+ if (priv->apb_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
ret = reset_get_by_name(dev, "core", &priv->core_rst);
if (ret) {
@@ -483,6 +465,13 @@
return ret;
}
+ ret = device_get_supply_regulator(dev, "vpcie12v-supply",
+ &priv->vpcie12v);
+ if (ret && ret != -ENOENT) {
+ dev_err(dev, "failed to get vpcie12v supply (ret=%d)\n", ret);
+ return ret;
+ }
+
ret = device_get_supply_regulator(dev, "vpcie3v3-supply",
&priv->vpcie3v3);
if (ret && ret != -ENOENT) {
@@ -510,6 +499,13 @@
return ret;
}
+ ret = gpio_request_by_name(dev, "ep-gpios", 0,
+ &priv->ep_gpio, GPIOD_IS_OUT);
+ if (ret) {
+ dev_err(dev, "failed to find ep-gpios property\n");
+ return ret;
+ }
+
return 0;
}
@@ -529,16 +525,26 @@
ret = rockchip_pcie_set_vpcie(dev);
if (ret)
- return ret;
+ goto err_gpio_free;
ret = rockchip_pcie_init_port(dev);
if (ret)
- return ret;
+ goto err_disable_vpcie;
dev_info(dev, "PCIE-%d: Link up (Bus%d)\n",
dev_seq(dev), hose->first_busno);
return 0;
+
+err_disable_vpcie:
+ regulator_set_enable_if_allowed(priv->vpcie0v9, false);
+ regulator_set_enable_if_allowed(priv->vpcie1v8, false);
+ regulator_set_enable_if_allowed(priv->vpcie3v3, false);
+ regulator_set_enable_if_allowed(priv->vpcie12v, false);
+err_gpio_free:
+ if (dm_gpio_is_valid(&priv->ep_gpio))
+ dm_gpio_free(dev, &priv->ep_gpio);
+ return ret;
}
static const struct dm_pci_ops rockchip_pcie_ops = {
@@ -552,10 +558,10 @@
};
U_BOOT_DRIVER(rockchip_pcie) = {
- .name = "rockchip_pcie",
- .id = UCLASS_PCI,
- .of_match = rockchip_pcie_ids,
- .ops = &rockchip_pcie_ops,
- .probe = rockchip_pcie_probe,
+ .name = "rockchip_pcie",
+ .id = UCLASS_PCI,
+ .of_match = rockchip_pcie_ids,
+ .ops = &rockchip_pcie_ops,
+ .probe = rockchip_pcie_probe,
.priv_auto = sizeof(struct rockchip_pcie),
};
diff --git a/drivers/pci/pcie_starfive_jh7110.c b/drivers/pci/pcie_starfive_jh7110.c
new file mode 100644
index 0000000..903a544
--- /dev/null
+++ b/drivers/pci/pcie_starfive_jh7110.c
@@ -0,0 +1,317 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive PLDA PCIe host controller driver
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Mason Huo <mason.huo@starfivetech.com>
+ *
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <pci.h>
+#include <pci_ids.h>
+#include <power-domain.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <dm/device_compat.h>
+#include <dm/pinctrl.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include "pcie_plda_common.h"
+
+/* system control */
+#define STG_SYSCON_K_RP_NEP_MASK BIT(8)
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8)
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8
+#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0)
+#define STG_SYSCON_CLKREQ_MASK BIT(22)
+#define STG_SYSCON_CKREF_SRC_SHIFT 18
+#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct starfive_pcie {
+ struct pcie_plda plda;
+ struct clk_bulk clks;
+ struct reset_ctl_bulk rsts;
+ struct gpio_desc reset_gpio;
+ struct regmap *regmap;
+ u32 stg_arfun;
+ u32 stg_awfun;
+ u32 stg_rp_nep;
+};
+
+static int starfive_pcie_atr_init(struct starfive_pcie *priv)
+{
+ struct udevice *ctlr = pci_get_controller(priv->plda.dev);
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+ int i, ret;
+
+ /*
+ * As the two host bridges in JH7110 soc have the same default
+ * address translation table, this cause the second root port can't
+ * access it's host bridge config space correctly.
+ * To workaround, config the ATR of host bridge config space by SW.
+ */
+
+ ret = plda_pcie_set_atr_entry(&priv->plda,
+ (phys_addr_t)priv->plda.cfg_base, 0,
+ priv->plda.cfg_size,
+ XR3PCI_ATR_TRSLID_PCIE_CONFIG);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < hose->region_count; i++) {
+ if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
+ continue;
+
+ /* Only support identity mappings. */
+ if (hose->regions[i].bus_start !=
+ hose->regions[i].phys_start)
+ return -EINVAL;
+
+ ret = plda_pcie_set_atr_entry(&priv->plda,
+ hose->regions[i].phys_start,
+ hose->regions[i].bus_start,
+ hose->regions[i].size,
+ XR3PCI_ATR_TRSLID_PCIE_MEMORY);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int starfive_pcie_get_syscon(struct udevice *dev)
+{
+ struct starfive_pcie *priv = dev_get_priv(dev);
+ struct udevice *syscon;
+ struct ofnode_phandle_args syscfg_phandle;
+ u32 cells[4];
+ int ret;
+
+ /* get corresponding syscon phandle */
+ ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 0, 0,
+ &syscfg_phandle);
+
+ if (ret < 0) {
+ dev_err(dev, "Can't get syscfg phandle: %d\n", ret);
+ return ret;
+ }
+
+ ret = uclass_get_device_by_ofnode(UCLASS_SYSCON, syscfg_phandle.node,
+ &syscon);
+ if (ret) {
+ dev_err(dev, "Unable to find syscon device (%d)\n", ret);
+ return ret;
+ }
+
+ priv->regmap = syscon_get_regmap(syscon);
+ if (!priv->regmap) {
+ dev_err(dev, "Unable to find regmap\n");
+ return -ENODEV;
+ }
+
+ /* get syscon register offset */
+ ret = dev_read_u32_array(dev, "starfive,stg-syscon",
+ cells, ARRAY_SIZE(cells));
+ if (ret) {
+ dev_err(dev, "Get syscon register err %d\n", ret);
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "Get syscon values: %x, %x, %x\n",
+ cells[1], cells[2], cells[3]);
+ priv->stg_arfun = cells[1];
+ priv->stg_awfun = cells[2];
+ priv->stg_rp_nep = cells[3];
+
+ return 0;
+}
+
+static int starfive_pcie_parse_dt(struct udevice *dev)
+{
+ struct starfive_pcie *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->plda.reg_base = (void *)dev_read_addr_name(dev, "reg");
+ if (priv->plda.reg_base == (void __iomem *)FDT_ADDR_T_NONE) {
+ dev_err(dev, "Missing required reg address range\n");
+ return -EINVAL;
+ }
+
+ priv->plda.cfg_base =
+ (void *)dev_read_addr_size_name(dev,
+ "config",
+ &priv->plda.cfg_size);
+ if (priv->plda.cfg_base == (void __iomem *)FDT_ADDR_T_NONE) {
+ dev_err(dev, "Missing required config address range");
+ return -EINVAL;
+ }
+
+ ret = starfive_pcie_get_syscon(dev);
+ if (ret) {
+ dev_err(dev, "Can't get syscon: %d\n", ret);
+ return ret;
+ }
+
+ ret = reset_get_bulk(dev, &priv->rsts);
+ if (ret) {
+ dev_err(dev, "Can't get reset: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_get_bulk(dev, &priv->clks);
+ if (ret) {
+ dev_err(dev, "Can't get clock: %d\n", ret);
+ return ret;
+ }
+
+ ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio,
+ GPIOD_IS_OUT);
+ if (ret) {
+ dev_err(dev, "Can't get reset-gpio: %d\n", ret);
+ return ret;
+ }
+
+ if (!dm_gpio_is_valid(&priv->reset_gpio)) {
+ dev_err(dev, "reset-gpio is not valid\n");
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int starfive_pcie_init_port(struct udevice *dev)
+{
+ int ret, i;
+ struct starfive_pcie *priv = dev_get_priv(dev);
+ struct pcie_plda *plda = &priv->plda;
+
+ ret = clk_enable_bulk(&priv->clks);
+ if (ret) {
+ dev_err(dev, "Failed to enable clks (ret=%d)\n", ret);
+ return ret;
+ }
+
+ ret = reset_deassert_bulk(&priv->rsts);
+ if (ret) {
+ dev_err(dev, "Failed to deassert resets (ret=%d)\n", ret);
+ goto err_deassert_clk;
+ }
+
+ dm_gpio_set_value(&priv->reset_gpio, 1);
+ /* Disable physical functions except #0 */
+ for (i = 1; i < PLDA_FUNC_NUM; i++) {
+ regmap_update_bits(priv->regmap,
+ priv->stg_arfun,
+ STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
+ (i << PLDA_PHY_FUNC_SHIFT) <<
+ STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT);
+ regmap_update_bits(priv->regmap,
+ priv->stg_awfun,
+ STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
+ i << PLDA_PHY_FUNC_SHIFT);
+
+ plda_pcie_disable_func(plda);
+ }
+
+ /* Disable physical functions */
+ regmap_update_bits(priv->regmap,
+ priv->stg_arfun,
+ STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
+ 0);
+ regmap_update_bits(priv->regmap,
+ priv->stg_awfun,
+ STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
+ 0);
+
+ plda_pcie_enable_root_port(plda);
+
+ /* PCIe PCI Standard Configuration Identification Settings. */
+ plda_pcie_set_standard_class(plda);
+
+ /*
+ * The LTR message forwarding of PCIe Message Reception was set by core
+ * as default, but the forward id & addr are also need to be reset.
+ * If we do not disable LTR message forwarding here, or set a legal
+ * forwarding address, the kernel will get stuck after this driver probe.
+ * To workaround, disable the LTR message forwarding support on
+ * PCIe Message Reception.
+ */
+ plda_pcie_disable_ltr(plda);
+
+ /* Prefetchable memory window 64-bit addressing support */
+ plda_pcie_set_pref_win_64bit(plda);
+ starfive_pcie_atr_init(priv);
+
+ dm_gpio_set_value(&priv->reset_gpio, 0);
+ /* Ensure that PERST in default at least 300 ms */
+ mdelay(300);
+
+ return 0;
+
+err_deassert_clk:
+ clk_disable_bulk(&priv->clks);
+ return ret;
+}
+
+static int starfive_pcie_probe(struct udevice *dev)
+{
+ struct starfive_pcie *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->plda.atr_table_num = 0;
+ priv->plda.dev = dev;
+
+ ret = starfive_pcie_parse_dt(dev);
+ if (ret)
+ return ret;
+
+ regmap_update_bits(priv->regmap,
+ priv->stg_rp_nep,
+ STG_SYSCON_K_RP_NEP_MASK,
+ STG_SYSCON_K_RP_NEP_MASK);
+
+ regmap_update_bits(priv->regmap,
+ priv->stg_awfun,
+ STG_SYSCON_CKREF_SRC_MASK,
+ 2 << STG_SYSCON_CKREF_SRC_SHIFT);
+
+ regmap_update_bits(priv->regmap,
+ priv->stg_awfun,
+ STG_SYSCON_CLKREQ_MASK,
+ STG_SYSCON_CLKREQ_MASK);
+
+ ret = starfive_pcie_init_port(dev);
+ if (ret)
+ return ret;
+
+ dev_err(dev, "Starfive PCIe bus probed.\n");
+
+ return 0;
+}
+
+static const struct dm_pci_ops starfive_pcie_ops = {
+ .read_config = plda_pcie_config_read,
+ .write_config = plda_pcie_config_write,
+};
+
+static const struct udevice_id starfive_pcie_ids[] = {
+ { .compatible = "starfive,jh7110-pcie" },
+ { }
+};
+
+U_BOOT_DRIVER(starfive_pcie_drv) = {
+ .name = "starfive_7110_pcie",
+ .id = UCLASS_PCI,
+ .of_match = starfive_pcie_ids,
+ .ops = &starfive_pcie_ops,
+ .probe = starfive_pcie_probe,
+ .priv_auto = sizeof(struct starfive_pcie),
+};
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 7a2d54f..8ac5769 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -70,6 +70,16 @@
help
Support for the USB OTG PHY in ST-Ericsson AB8500.
+config APPLE_ATCPHY
+ bool "Apple Type-C PHY Driver"
+ depends on PHY && ARCH_APPLE
+ default y
+ help
+ Support for the Apple Type-C PHY.
+
+ This is a dummy driver since the PHY is initialized
+ sufficiently by previous stage firmware.
+
config BCM6318_USBH_PHY
bool "BCM6318 USBH PHY support"
depends on PHY && ARCH_BMIPS
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index aca365d..5d4de86 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -12,6 +12,7 @@
obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o
obj-$(CONFIG_MIPI_DPHY_HELPERS) += phy-core-mipi-dphy.o
obj-$(CONFIG_AB8500_USB_PHY) += phy-ab8500-usb.o
+obj-$(CONFIG_APPLE_ATCPHY) += phy-apple-atc.o
obj-$(CONFIG_BCM6318_USBH_PHY) += bcm6318-usbh-phy.o
obj-$(CONFIG_BCM6348_USBH_PHY) += bcm6348-usbh-phy.o
obj-$(CONFIG_BCM6358_USBH_PHY) += bcm6358-usbh-phy.o
diff --git a/drivers/phy/phy-apple-atc.c b/drivers/phy/phy-apple-atc.c
new file mode 100644
index 0000000..15c5b8a
--- /dev/null
+++ b/drivers/phy/phy-apple-atc.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Mark Kettenis <kettenis@openbsd.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <generic-phy.h>
+#include <reset-uclass.h>
+
+static const struct phy_ops apple_atcphy_ops = {
+};
+
+static struct driver apple_atcphy_driver = {
+ .name = "apple-atcphy",
+ .id = UCLASS_PHY,
+ .ops = &apple_atcphy_ops,
+};
+
+static int apple_atcphy_reset_of_xlate(struct reset_ctl *reset_ctl,
+ struct ofnode_phandle_args *args)
+{
+ if (args->args_count != 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct reset_ops apple_atcphy_reset_ops = {
+ .of_xlate = apple_atcphy_reset_of_xlate,
+};
+
+static int apple_atcphy_reset_probe(struct udevice *dev)
+{
+ struct udevice *child;
+
+ device_bind(dev, &apple_atcphy_driver, "apple-atcphy", NULL,
+ dev_ofnode(dev), &child);
+
+ return 0;
+}
+
+static const struct udevice_id apple_atcphy_ids[] = {
+ { .compatible = "apple,t6000-atcphy" },
+ { .compatible = "apple,t8103-atcphy" },
+ { }
+};
+
+U_BOOT_DRIVER(apple_atcphy_reset) = {
+ .name = "apple-atcphy-reset",
+ .id = UCLASS_RESET,
+ .of_match = apple_atcphy_ids,
+ .ops = &apple_atcphy_reset_ops,
+ .probe = apple_atcphy_reset_probe,
+};
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 34314d0..7261339 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -585,12 +585,20 @@
static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
{
- if (wiz->type != AM64_WIZ_10G)
- return 0;
-
- if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
- return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
+ switch (wiz->type) {
+ case AM64_WIZ_10G:
+ if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
+ return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
+ break;
+ case J721E_WIZ_16G:
+ case J721E_WIZ_10G:
+ if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)
+ return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);
+ break;
+ default:
+ return 0;
+ }
return 0;
}
@@ -706,7 +714,8 @@
int i;
for (i = 0; i < num_lanes; i++) {
- if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
+ if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII ||
+ wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);
if (ret)
return ret;
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 27e8998..34d23ce 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -24,6 +24,10 @@
bool "MT7986 SoC pinctrl driver"
select PINCTRL_MTK
+config PINCTRL_MT7988
+ bool "MT7988 SoC pinctrl driver"
+ select PINCTRL_MTK
+
config PINCTRL_MT8512
bool "MT8512 SoC pinctrl driver"
select PINCTRL_MTK
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index 6e73375..de39d1e 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -8,6 +8,7 @@
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
+obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o
obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o
obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
index bf4e9a2..114f260 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
@@ -233,283 +233,285 @@
*/
/* EMMC */
-static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
-static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
+static const int mt7622_emmc_pins[] = {
+ 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
+static const int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-static int mt7622_emmc_rst_pins[] = { 37, };
-static int mt7622_emmc_rst_funcs[] = { 1, };
+static const int mt7622_emmc_rst_pins[] = { 37, };
+static const int mt7622_emmc_rst_funcs[] = { 1, };
/* LED for EPHY */
-static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
-static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
-static int mt7622_ephy0_led_pins[] = { 86, };
-static int mt7622_ephy0_led_funcs[] = { 0, };
-static int mt7622_ephy1_led_pins[] = { 91, };
-static int mt7622_ephy1_led_funcs[] = { 2, };
-static int mt7622_ephy2_led_pins[] = { 92, };
-static int mt7622_ephy2_led_funcs[] = { 2, };
-static int mt7622_ephy3_led_pins[] = { 93, };
-static int mt7622_ephy3_led_funcs[] = { 2, };
-static int mt7622_ephy4_led_pins[] = { 94, };
-static int mt7622_ephy4_led_funcs[] = { 2, };
+static const int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
+static const int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
+static const int mt7622_ephy0_led_pins[] = { 86, };
+static const int mt7622_ephy0_led_funcs[] = { 0, };
+static const int mt7622_ephy1_led_pins[] = { 91, };
+static const int mt7622_ephy1_led_funcs[] = { 2, };
+static const int mt7622_ephy2_led_pins[] = { 92, };
+static const int mt7622_ephy2_led_funcs[] = { 2, };
+static const int mt7622_ephy3_led_pins[] = { 93, };
+static const int mt7622_ephy3_led_funcs[] = { 2, };
+static const int mt7622_ephy4_led_pins[] = { 94, };
+static const int mt7622_ephy4_led_funcs[] = { 2, };
/* Embedded Switch */
-static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
- 62, 63, 64, 65, 66, 67, 68, 69, 70, };
-static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, };
-static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
-static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
-static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67,
- 68, 69, 70, };
-static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, };
+static const int mt7622_esw_pins[] = {
+ 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68,
+ 69, 70, };
+static const int mt7622_esw_funcs[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+static const int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
+static const int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
+static const int mt7622_esw_p2_p3_p4_pins[] = {
+ 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, };
+static const int mt7622_esw_p2_p3_p4_funcs[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
/* RGMII via ESW */
-static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
- 67, 68, 69, 70, };
-static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, };
+static const int mt7622_rgmii_via_esw_pins[] = {
+ 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, };
+static const int mt7622_rgmii_via_esw_funcs[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
/* RGMII via GMAC1 */
-static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
- 67, 68, 69, 70, };
-static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
- 2, };
+static const int mt7622_rgmii_via_gmac1_pins[] = {
+ 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, };
+static const int mt7622_rgmii_via_gmac1_funcs[] = {
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
/* RGMII via GMAC2 */
-static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32,
- 33, 34, 35, 36, };
-static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, };
+static const int mt7622_rgmii_via_gmac2_pins[] = {
+ 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, };
+static const int mt7622_rgmii_via_gmac2_funcs[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
/* I2C */
-static int mt7622_i2c0_pins[] = { 14, 15, };
-static int mt7622_i2c0_funcs[] = { 0, 0, };
-static int mt7622_i2c1_0_pins[] = { 55, 56, };
-static int mt7622_i2c1_0_funcs[] = { 0, 0, };
-static int mt7622_i2c1_1_pins[] = { 73, 74, };
-static int mt7622_i2c1_1_funcs[] = { 3, 3, };
-static int mt7622_i2c1_2_pins[] = { 87, 88, };
-static int mt7622_i2c1_2_funcs[] = { 0, 0, };
-static int mt7622_i2c2_0_pins[] = { 57, 58, };
-static int mt7622_i2c2_0_funcs[] = { 0, 0, };
-static int mt7622_i2c2_1_pins[] = { 75, 76, };
-static int mt7622_i2c2_1_funcs[] = { 3, 3, };
-static int mt7622_i2c2_2_pins[] = { 89, 90, };
-static int mt7622_i2c2_2_funcs[] = { 0, 0, };
+static const int mt7622_i2c0_pins[] = { 14, 15, };
+static const int mt7622_i2c0_funcs[] = { 0, 0, };
+static const int mt7622_i2c1_0_pins[] = { 55, 56, };
+static const int mt7622_i2c1_0_funcs[] = { 0, 0, };
+static const int mt7622_i2c1_1_pins[] = { 73, 74, };
+static const int mt7622_i2c1_1_funcs[] = { 3, 3, };
+static const int mt7622_i2c1_2_pins[] = { 87, 88, };
+static const int mt7622_i2c1_2_funcs[] = { 0, 0, };
+static const int mt7622_i2c2_0_pins[] = { 57, 58, };
+static const int mt7622_i2c2_0_funcs[] = { 0, 0, };
+static const int mt7622_i2c2_1_pins[] = { 75, 76, };
+static const int mt7622_i2c2_1_funcs[] = { 3, 3, };
+static const int mt7622_i2c2_2_pins[] = { 89, 90, };
+static const int mt7622_i2c2_2_funcs[] = { 0, 0, };
/* I2S */
-static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
-static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
-static int mt7622_i2s1_in_data_pins[] = { 1, };
-static int mt7622_i2s1_in_data_funcs[] = { 0, };
-static int mt7622_i2s2_in_data_pins[] = { 16, };
-static int mt7622_i2s2_in_data_funcs[] = { 0, };
-static int mt7622_i2s3_in_data_pins[] = { 17, };
-static int mt7622_i2s3_in_data_funcs[] = { 0, };
-static int mt7622_i2s4_in_data_pins[] = { 18, };
-static int mt7622_i2s4_in_data_funcs[] = { 0, };
-static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
-static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
-static int mt7622_i2s1_out_data_pins[] = { 2, };
-static int mt7622_i2s1_out_data_funcs[] = { 0, };
-static int mt7622_i2s2_out_data_pins[] = { 19, };
-static int mt7622_i2s2_out_data_funcs[] = { 0, };
-static int mt7622_i2s3_out_data_pins[] = { 20, };
-static int mt7622_i2s3_out_data_funcs[] = { 0, };
-static int mt7622_i2s4_out_data_pins[] = { 21, };
-static int mt7622_i2s4_out_data_funcs[] = { 0, };
+static const int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
+static const int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
+static const int mt7622_i2s1_in_data_pins[] = { 1, };
+static const int mt7622_i2s1_in_data_funcs[] = { 0, };
+static const int mt7622_i2s2_in_data_pins[] = { 16, };
+static const int mt7622_i2s2_in_data_funcs[] = { 0, };
+static const int mt7622_i2s3_in_data_pins[] = { 17, };
+static const int mt7622_i2s3_in_data_funcs[] = { 0, };
+static const int mt7622_i2s4_in_data_pins[] = { 18, };
+static const int mt7622_i2s4_in_data_funcs[] = { 0, };
+static const int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
+static const int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
+static const int mt7622_i2s1_out_data_pins[] = { 2, };
+static const int mt7622_i2s1_out_data_funcs[] = { 0, };
+static const int mt7622_i2s2_out_data_pins[] = { 19, };
+static const int mt7622_i2s2_out_data_funcs[] = { 0, };
+static const int mt7622_i2s3_out_data_pins[] = { 20, };
+static const int mt7622_i2s3_out_data_funcs[] = { 0, };
+static const int mt7622_i2s4_out_data_pins[] = { 21, };
+static const int mt7622_i2s4_out_data_funcs[] = { 0, };
/* IR */
-static int mt7622_ir_0_tx_pins[] = { 16, };
-static int mt7622_ir_0_tx_funcs[] = { 4, };
-static int mt7622_ir_1_tx_pins[] = { 59, };
-static int mt7622_ir_1_tx_funcs[] = { 5, };
-static int mt7622_ir_2_tx_pins[] = { 99, };
-static int mt7622_ir_2_tx_funcs[] = { 3, };
-static int mt7622_ir_0_rx_pins[] = { 17, };
-static int mt7622_ir_0_rx_funcs[] = { 4, };
-static int mt7622_ir_1_rx_pins[] = { 60, };
-static int mt7622_ir_1_rx_funcs[] = { 5, };
-static int mt7622_ir_2_rx_pins[] = { 100, };
-static int mt7622_ir_2_rx_funcs[] = { 3, };
+static const int mt7622_ir_0_tx_pins[] = { 16, };
+static const int mt7622_ir_0_tx_funcs[] = { 4, };
+static const int mt7622_ir_1_tx_pins[] = { 59, };
+static const int mt7622_ir_1_tx_funcs[] = { 5, };
+static const int mt7622_ir_2_tx_pins[] = { 99, };
+static const int mt7622_ir_2_tx_funcs[] = { 3, };
+static const int mt7622_ir_0_rx_pins[] = { 17, };
+static const int mt7622_ir_0_rx_funcs[] = { 4, };
+static const int mt7622_ir_1_rx_pins[] = { 60, };
+static const int mt7622_ir_1_rx_funcs[] = { 5, };
+static const int mt7622_ir_2_rx_pins[] = { 100, };
+static const int mt7622_ir_2_rx_funcs[] = { 3, };
/* MDIO */
-static int mt7622_mdc_mdio_pins[] = { 23, 24, };
-static int mt7622_mdc_mdio_funcs[] = { 0, 0, };
+static const int mt7622_mdc_mdio_pins[] = { 23, 24, };
+static const int mt7622_mdc_mdio_funcs[] = { 0, 0, };
/* PCIE */
-static int mt7622_pcie0_0_waken_pins[] = { 14, };
-static int mt7622_pcie0_0_waken_funcs[] = { 2, };
-static int mt7622_pcie0_0_clkreq_pins[] = { 15, };
-static int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
-static int mt7622_pcie0_1_waken_pins[] = { 79, };
-static int mt7622_pcie0_1_waken_funcs[] = { 4, };
-static int mt7622_pcie0_1_clkreq_pins[] = { 80, };
-static int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
-static int mt7622_pcie1_0_waken_pins[] = { 14, };
-static int mt7622_pcie1_0_waken_funcs[] = { 3, };
-static int mt7622_pcie1_0_clkreq_pins[] = { 15, };
-static int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
+static const int mt7622_pcie0_0_waken_pins[] = { 14, };
+static const int mt7622_pcie0_0_waken_funcs[] = { 2, };
+static const int mt7622_pcie0_0_clkreq_pins[] = { 15, };
+static const int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
+static const int mt7622_pcie0_1_waken_pins[] = { 79, };
+static const int mt7622_pcie0_1_waken_funcs[] = { 4, };
+static const int mt7622_pcie0_1_clkreq_pins[] = { 80, };
+static const int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
+static const int mt7622_pcie1_0_waken_pins[] = { 14, };
+static const int mt7622_pcie1_0_waken_funcs[] = { 3, };
+static const int mt7622_pcie1_0_clkreq_pins[] = { 15, };
+static const int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
-static int mt7622_pcie0_pad_perst_pins[] = { 83, };
-static int mt7622_pcie0_pad_perst_funcs[] = { 0, };
-static int mt7622_pcie1_pad_perst_pins[] = { 84, };
-static int mt7622_pcie1_pad_perst_funcs[] = { 0, };
+static const int mt7622_pcie0_pad_perst_pins[] = { 83, };
+static const int mt7622_pcie0_pad_perst_funcs[] = { 0, };
+static const int mt7622_pcie1_pad_perst_pins[] = { 84, };
+static const int mt7622_pcie1_pad_perst_funcs[] = { 0, };
/* PMIC bus */
-static int mt7622_pmic_bus_pins[] = { 71, 72, };
-static int mt7622_pmic_bus_funcs[] = { 0, 0, };
+static const int mt7622_pmic_bus_pins[] = { 71, 72, };
+static const int mt7622_pmic_bus_funcs[] = { 0, 0, };
/* Parallel NAND */
-static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
- 48, 49, 50, };
-static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, };
+static const int mt7622_pnand_pins[] = {
+ 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, };
+static const int mt7622_pnand_funcs[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
/* PWM */
-static int mt7622_pwm_ch1_0_pins[] = { 51, };
-static int mt7622_pwm_ch1_0_funcs[] = { 3, };
-static int mt7622_pwm_ch1_1_pins[] = { 73, };
-static int mt7622_pwm_ch1_1_funcs[] = { 4, };
-static int mt7622_pwm_ch1_2_pins[] = { 95, };
-static int mt7622_pwm_ch1_2_funcs[] = { 0, };
-static int mt7622_pwm_ch2_0_pins[] = { 52, };
-static int mt7622_pwm_ch2_0_funcs[] = { 3, };
-static int mt7622_pwm_ch2_1_pins[] = { 74, };
-static int mt7622_pwm_ch2_1_funcs[] = { 4, };
-static int mt7622_pwm_ch2_2_pins[] = { 96, };
-static int mt7622_pwm_ch2_2_funcs[] = { 0, };
-static int mt7622_pwm_ch3_0_pins[] = { 53, };
-static int mt7622_pwm_ch3_0_funcs[] = { 3, };
-static int mt7622_pwm_ch3_1_pins[] = { 75, };
-static int mt7622_pwm_ch3_1_funcs[] = { 4, };
-static int mt7622_pwm_ch3_2_pins[] = { 97, };
-static int mt7622_pwm_ch3_2_funcs[] = { 0, };
-static int mt7622_pwm_ch4_0_pins[] = { 54, };
-static int mt7622_pwm_ch4_0_funcs[] = { 3, };
-static int mt7622_pwm_ch4_1_pins[] = { 67, };
-static int mt7622_pwm_ch4_1_funcs[] = { 3, };
-static int mt7622_pwm_ch4_2_pins[] = { 76, };
-static int mt7622_pwm_ch4_2_funcs[] = { 4, };
-static int mt7622_pwm_ch4_3_pins[] = { 98, };
-static int mt7622_pwm_ch4_3_funcs[] = { 0, };
-static int mt7622_pwm_ch5_0_pins[] = { 68, };
-static int mt7622_pwm_ch5_0_funcs[] = { 3, };
-static int mt7622_pwm_ch5_1_pins[] = { 77, };
-static int mt7622_pwm_ch5_1_funcs[] = { 4, };
-static int mt7622_pwm_ch5_2_pins[] = { 99, };
-static int mt7622_pwm_ch5_2_funcs[] = { 0, };
-static int mt7622_pwm_ch6_0_pins[] = { 69, };
-static int mt7622_pwm_ch6_0_funcs[] = { 3, };
-static int mt7622_pwm_ch6_1_pins[] = { 78, };
-static int mt7622_pwm_ch6_1_funcs[] = { 4, };
-static int mt7622_pwm_ch6_2_pins[] = { 81, };
-static int mt7622_pwm_ch6_2_funcs[] = { 4, };
-static int mt7622_pwm_ch6_3_pins[] = { 100, };
-static int mt7622_pwm_ch6_3_funcs[] = { 0, };
-static int mt7622_pwm_ch7_0_pins[] = { 70, };
-static int mt7622_pwm_ch7_0_funcs[] = { 3, };
-static int mt7622_pwm_ch7_1_pins[] = { 82, };
-static int mt7622_pwm_ch7_1_funcs[] = { 4, };
-static int mt7622_pwm_ch7_2_pins[] = { 101, };
-static int mt7622_pwm_ch7_2_funcs[] = { 0, };
+static const int mt7622_pwm_ch1_0_pins[] = { 51, };
+static const int mt7622_pwm_ch1_0_funcs[] = { 3, };
+static const int mt7622_pwm_ch1_1_pins[] = { 73, };
+static const int mt7622_pwm_ch1_1_funcs[] = { 4, };
+static const int mt7622_pwm_ch1_2_pins[] = { 95, };
+static const int mt7622_pwm_ch1_2_funcs[] = { 0, };
+static const int mt7622_pwm_ch2_0_pins[] = { 52, };
+static const int mt7622_pwm_ch2_0_funcs[] = { 3, };
+static const int mt7622_pwm_ch2_1_pins[] = { 74, };
+static const int mt7622_pwm_ch2_1_funcs[] = { 4, };
+static const int mt7622_pwm_ch2_2_pins[] = { 96, };
+static const int mt7622_pwm_ch2_2_funcs[] = { 0, };
+static const int mt7622_pwm_ch3_0_pins[] = { 53, };
+static const int mt7622_pwm_ch3_0_funcs[] = { 3, };
+static const int mt7622_pwm_ch3_1_pins[] = { 75, };
+static const int mt7622_pwm_ch3_1_funcs[] = { 4, };
+static const int mt7622_pwm_ch3_2_pins[] = { 97, };
+static const int mt7622_pwm_ch3_2_funcs[] = { 0, };
+static const int mt7622_pwm_ch4_0_pins[] = { 54, };
+static const int mt7622_pwm_ch4_0_funcs[] = { 3, };
+static const int mt7622_pwm_ch4_1_pins[] = { 67, };
+static const int mt7622_pwm_ch4_1_funcs[] = { 3, };
+static const int mt7622_pwm_ch4_2_pins[] = { 76, };
+static const int mt7622_pwm_ch4_2_funcs[] = { 4, };
+static const int mt7622_pwm_ch4_3_pins[] = { 98, };
+static const int mt7622_pwm_ch4_3_funcs[] = { 0, };
+static const int mt7622_pwm_ch5_0_pins[] = { 68, };
+static const int mt7622_pwm_ch5_0_funcs[] = { 3, };
+static const int mt7622_pwm_ch5_1_pins[] = { 77, };
+static const int mt7622_pwm_ch5_1_funcs[] = { 4, };
+static const int mt7622_pwm_ch5_2_pins[] = { 99, };
+static const int mt7622_pwm_ch5_2_funcs[] = { 0, };
+static const int mt7622_pwm_ch6_0_pins[] = { 69, };
+static const int mt7622_pwm_ch6_0_funcs[] = { 3, };
+static const int mt7622_pwm_ch6_1_pins[] = { 78, };
+static const int mt7622_pwm_ch6_1_funcs[] = { 4, };
+static const int mt7622_pwm_ch6_2_pins[] = { 81, };
+static const int mt7622_pwm_ch6_2_funcs[] = { 4, };
+static const int mt7622_pwm_ch6_3_pins[] = { 100, };
+static const int mt7622_pwm_ch6_3_funcs[] = { 0, };
+static const int mt7622_pwm_ch7_0_pins[] = { 70, };
+static const int mt7622_pwm_ch7_0_funcs[] = { 3, };
+static const int mt7622_pwm_ch7_1_pins[] = { 82, };
+static const int mt7622_pwm_ch7_1_funcs[] = { 4, };
+static const int mt7622_pwm_ch7_2_pins[] = { 101, };
+static const int mt7622_pwm_ch7_2_funcs[] = { 0, };
/* SD */
-static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
-static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
-static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
-static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
+static const int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
+static const int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
+static const int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
+static const int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
/* Serial NAND */
-static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
-static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
+static const int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
+static const int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
/* SPI NOR */
-static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
-static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
+static const int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
+static const int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
/* SPIC */
-static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
-static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
-static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
-static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
-static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
-static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
-static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
-static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
-static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
-static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
-static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
-static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
+static const int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
+static const int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
+static const int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
+static const int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
+static const int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
+static const int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
+static const int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
+static const int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
+static const int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
+static const int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
+static const int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
+static const int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
/* TDM */
-static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
-static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
-static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-static int mt7622_tdm_0_out_data_pins[] = { 20, };
-static int mt7622_tdm_0_out_data_funcs[] = { 3, };
-static int mt7622_tdm_0_in_data_pins[] = { 21, };
-static int mt7622_tdm_0_in_data_funcs[] = { 3, };
-static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
-static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
-static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-static int mt7622_tdm_1_out_data_pins[] = { 55, };
-static int mt7622_tdm_1_out_data_funcs[] = { 3, };
-static int mt7622_tdm_1_in_data_pins[] = { 56, };
-static int mt7622_tdm_1_in_data_funcs[] = { 3, };
+static const int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
+static const int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
+static const int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
+static const int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
+static const int mt7622_tdm_0_out_data_pins[] = { 20, };
+static const int mt7622_tdm_0_out_data_funcs[] = { 3, };
+static const int mt7622_tdm_0_in_data_pins[] = { 21, };
+static const int mt7622_tdm_0_in_data_funcs[] = { 3, };
+static const int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
+static const int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
+static const int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
+static const int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
+static const int mt7622_tdm_1_out_data_pins[] = { 55, };
+static const int mt7622_tdm_1_out_data_funcs[] = { 3, };
+static const int mt7622_tdm_1_in_data_pins[] = { 56, };
+static const int mt7622_tdm_1_in_data_funcs[] = { 3, };
/* UART */
-static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
-static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
-static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
-static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
-static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
-static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
-static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
-static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
-static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
-static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
-static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
-static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
-static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
-static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
-static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
-static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
-static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
-static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
-static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
-static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
-static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
-static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
-static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
-static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
-static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
-static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
-static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
-static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
-static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
-static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
-static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
-static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
-static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
-static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
-static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
-static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
-static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
-static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
-static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
-static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
+static const int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
+static const int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
+static const int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
+static const int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
+static const int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
+static const int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
+static const int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
+static const int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
+static const int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
+static const int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
+static const int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
+static const int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
+static const int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
+static const int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
+static const int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
+static const int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
+static const int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
+static const int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
+static const int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
+static const int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
+static const int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
+static const int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
+static const int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
+static const int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
+static const int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
+static const int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
+static const int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
+static const int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
+static const int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
+static const int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
+static const int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
+static const int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
+static const int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
+static const int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
+static const int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
+static const int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
+static const int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
+static const int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
+static const int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
+static const int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
/* Watchdog */
-static int mt7622_watchdog_pins[] = { 78, };
-static int mt7622_watchdog_funcs[] = { 0, };
+static const int mt7622_watchdog_pins[] = { 78, };
+static const int mt7622_watchdog_funcs[] = { 0, };
/* WLAN LED */
-static int mt7622_wled_pins[] = { 85, };
-static int mt7622_wled_funcs[] = { 0, };
+static const int mt7622_wled_pins[] = { 85, };
+static const int mt7622_wled_funcs[] = { 0, };
static const struct mtk_group_desc mt7622_groups[] = {
PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
@@ -719,7 +721,7 @@
{"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
};
-static struct mtk_pinctrl_soc mt7622_data = {
+static const struct mtk_pinctrl_soc mt7622_data = {
.name = "mt7622_pinctrl",
.reg_cal = mt7622_reg_cals,
.pins = mt7622_pins,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
index 2e3ae34..2703e6f 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
@@ -692,377 +692,377 @@
*/
/* AUDIO EXT CLK */
-static int mt7623_aud_ext_clk0_pins[] = { 208, };
-static int mt7623_aud_ext_clk0_funcs[] = { 1, };
-static int mt7623_aud_ext_clk1_pins[] = { 209, };
-static int mt7623_aud_ext_clk1_funcs[] = { 1, };
+static const int mt7623_aud_ext_clk0_pins[] = { 208, };
+static const int mt7623_aud_ext_clk0_funcs[] = { 1, };
+static const int mt7623_aud_ext_clk1_pins[] = { 209, };
+static const int mt7623_aud_ext_clk1_funcs[] = { 1, };
/* DISP PWM */
-static int mt7623_disp_pwm_0_pins[] = { 72, };
-static int mt7623_disp_pwm_0_funcs[] = { 5, };
-static int mt7623_disp_pwm_1_pins[] = { 203, };
-static int mt7623_disp_pwm_1_funcs[] = { 2, };
-static int mt7623_disp_pwm_2_pins[] = { 208, };
-static int mt7623_disp_pwm_2_funcs[] = { 5, };
+static const int mt7623_disp_pwm_0_pins[] = { 72, };
+static const int mt7623_disp_pwm_0_funcs[] = { 5, };
+static const int mt7623_disp_pwm_1_pins[] = { 203, };
+static const int mt7623_disp_pwm_1_funcs[] = { 2, };
+static const int mt7623_disp_pwm_2_pins[] = { 208, };
+static const int mt7623_disp_pwm_2_funcs[] = { 5, };
/* ESW */
-static int mt7623_esw_int_pins[] = { 273, };
-static int mt7623_esw_int_funcs[] = { 1, };
-static int mt7623_esw_rst_pins[] = { 277, };
-static int mt7623_esw_rst_funcs[] = { 1, };
+static const int mt7623_esw_int_pins[] = { 273, };
+static const int mt7623_esw_int_funcs[] = { 1, };
+static const int mt7623_esw_rst_pins[] = { 277, };
+static const int mt7623_esw_rst_funcs[] = { 1, };
/* EPHY */
-static int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268,
- 269, 270, 271, 272, 274, };
-static int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268,
+ 269, 270, 271, 272, 274, };
+static const int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
/* EXT_SDIO */
-static int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, };
-static int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, };
+static const int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, };
+static const int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, };
/* HDMI RX */
-static int mt7623_hdmi_rx_pins[] = { 247, 248, };
-static int mt7623_hdmi_rx_funcs[] = { 1, 1 };
-static int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, };
-static int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 };
+static const int mt7623_hdmi_rx_pins[] = { 247, 248, };
+static const int mt7623_hdmi_rx_funcs[] = { 1, 1 };
+static const int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, };
+static const int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 };
/* HDMI TX */
-static int mt7623_hdmi_cec_pins[] = { 122, };
-static int mt7623_hdmi_cec_funcs[] = { 1, };
-static int mt7623_hdmi_htplg_pins[] = { 123, };
-static int mt7623_hdmi_htplg_funcs[] = { 1, };
-static int mt7623_hdmi_i2c_pins[] = { 124, 125, };
-static int mt7623_hdmi_i2c_funcs[] = { 1, 1 };
+static const int mt7623_hdmi_cec_pins[] = { 122, };
+static const int mt7623_hdmi_cec_funcs[] = { 1, };
+static const int mt7623_hdmi_htplg_pins[] = { 123, };
+static const int mt7623_hdmi_htplg_funcs[] = { 1, };
+static const int mt7623_hdmi_i2c_pins[] = { 124, 125, };
+static const int mt7623_hdmi_i2c_funcs[] = { 1, 1 };
/* I2C */
-static int mt7623_i2c0_pins[] = { 75, 76, };
-static int mt7623_i2c0_funcs[] = { 1, 1, };
-static int mt7623_i2c1_0_pins[] = { 57, 58, };
-static int mt7623_i2c1_0_funcs[] = { 1, 1, };
-static int mt7623_i2c1_1_pins[] = { 242, 243, };
-static int mt7623_i2c1_1_funcs[] = { 4, 4, };
-static int mt7623_i2c1_2_pins[] = { 85, 86, };
-static int mt7623_i2c1_2_funcs[] = { 3, 3, };
-static int mt7623_i2c1_3_pins[] = { 105, 106, };
-static int mt7623_i2c1_3_funcs[] = { 3, 3, };
-static int mt7623_i2c1_4_pins[] = { 124, 125, };
-static int mt7623_i2c1_4_funcs[] = { 4, 4, };
-static int mt7623_i2c2_0_pins[] = { 77, 78, };
-static int mt7623_i2c2_0_funcs[] = { 1, 1, };
-static int mt7623_i2c2_1_pins[] = { 89, 90, };
-static int mt7623_i2c2_1_funcs[] = { 3, 3, };
-static int mt7623_i2c2_2_pins[] = { 109, 110, };
-static int mt7623_i2c2_2_funcs[] = { 3, 3, };
-static int mt7623_i2c2_3_pins[] = { 122, 123, };
-static int mt7623_i2c2_3_funcs[] = { 4, 4, };
+static const int mt7623_i2c0_pins[] = { 75, 76, };
+static const int mt7623_i2c0_funcs[] = { 1, 1, };
+static const int mt7623_i2c1_0_pins[] = { 57, 58, };
+static const int mt7623_i2c1_0_funcs[] = { 1, 1, };
+static const int mt7623_i2c1_1_pins[] = { 242, 243, };
+static const int mt7623_i2c1_1_funcs[] = { 4, 4, };
+static const int mt7623_i2c1_2_pins[] = { 85, 86, };
+static const int mt7623_i2c1_2_funcs[] = { 3, 3, };
+static const int mt7623_i2c1_3_pins[] = { 105, 106, };
+static const int mt7623_i2c1_3_funcs[] = { 3, 3, };
+static const int mt7623_i2c1_4_pins[] = { 124, 125, };
+static const int mt7623_i2c1_4_funcs[] = { 4, 4, };
+static const int mt7623_i2c2_0_pins[] = { 77, 78, };
+static const int mt7623_i2c2_0_funcs[] = { 1, 1, };
+static const int mt7623_i2c2_1_pins[] = { 89, 90, };
+static const int mt7623_i2c2_1_funcs[] = { 3, 3, };
+static const int mt7623_i2c2_2_pins[] = { 109, 110, };
+static const int mt7623_i2c2_2_funcs[] = { 3, 3, };
+static const int mt7623_i2c2_3_pins[] = { 122, 123, };
+static const int mt7623_i2c2_3_funcs[] = { 4, 4, };
/* I2S */
-static int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, };
-static int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, };
-static int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, };
-static int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, };
-static int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, };
-static int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
-static int mt7623_i2s2_data_in_pins[] = { 51, };
-static int mt7623_i2s2_data_in_funcs[] = { 1, };
-static int mt7623_i2s2_data_0_pins[] = { 203, };
-static int mt7623_i2s2_data_0_funcs[] = { 9, };
-static int mt7623_i2s2_data_1_pins[] = { 38, };
-static int mt7623_i2s2_data_1_funcs[] = { 4, };
-static int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, };
-static int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
-static int mt7623_i2s3_data_in_pins[] = { 190, };
-static int mt7623_i2s3_data_in_funcs[] = { 1, };
-static int mt7623_i2s3_data_0_pins[] = { 204, };
-static int mt7623_i2s3_data_0_funcs[] = { 9, };
-static int mt7623_i2s3_data_1_pins[] = { 2, };
-static int mt7623_i2s3_data_1_funcs[] = { 0, };
-static int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, };
-static int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, };
-static int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, };
-static int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, };
+static const int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, };
+static const int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, };
+static const int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, };
+static const int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, };
+static const int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, };
+static const int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
+static const int mt7623_i2s2_data_in_pins[] = { 51, };
+static const int mt7623_i2s2_data_in_funcs[] = { 1, };
+static const int mt7623_i2s2_data_0_pins[] = { 203, };
+static const int mt7623_i2s2_data_0_funcs[] = { 9, };
+static const int mt7623_i2s2_data_1_pins[] = { 38, };
+static const int mt7623_i2s2_data_1_funcs[] = { 4, };
+static const int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, };
+static const int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
+static const int mt7623_i2s3_data_in_pins[] = { 190, };
+static const int mt7623_i2s3_data_in_funcs[] = { 1, };
+static const int mt7623_i2s3_data_0_pins[] = { 204, };
+static const int mt7623_i2s3_data_0_funcs[] = { 9, };
+static const int mt7623_i2s3_data_1_pins[] = { 2, };
+static const int mt7623_i2s3_data_1_funcs[] = { 0, };
+static const int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, };
+static const int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, };
+static const int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, };
+static const int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, };
/* IR */
-static int mt7623_ir_pins[] = { 46, };
-static int mt7623_ir_funcs[] = { 1, };
+static const int mt7623_ir_pins[] = { 46, };
+static const int mt7623_ir_funcs[] = { 1, };
/* LCD */
-static int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98,
- 99, 100, };
-static int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-static int mt7623_dsi_te_pins[] = { 84, };
-static int mt7623_dsi_te_funcs[] = { 1, };
-static int mt7623_lcm_rst_pins[] = { 83, };
-static int mt7623_lcm_rst_funcs[] = { 1, };
+static const int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98,
+ 99, 100, };
+static const int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7623_dsi_te_pins[] = { 84, };
+static const int mt7623_dsi_te_funcs[] = { 1, };
+static const int mt7623_lcm_rst_pins[] = { 83, };
+static const int mt7623_lcm_rst_funcs[] = { 1, };
/* MDC/MDIO */
-static int mt7623_mdc_mdio_pins[] = { 275, 276, };
-static int mt7623_mdc_mdio_funcs[] = { 1, 1, };
+static const int mt7623_mdc_mdio_pins[] = { 275, 276, };
+static const int mt7623_mdc_mdio_funcs[] = { 1, 1, };
/* MSDC */
-static int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118,
- 119, 120, 121, };
-static int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-static int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, };
-static int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, };
-static int mt7623_msdc1_ins_pins[] = { 261, };
-static int mt7623_msdc1_ins_funcs[] = { 1, };
-static int mt7623_msdc1_wp_0_pins[] = { 29, };
-static int mt7623_msdc1_wp_0_funcs[] = { 1, };
-static int mt7623_msdc1_wp_1_pins[] = { 55, };
-static int mt7623_msdc1_wp_1_funcs[] = { 3, };
-static int mt7623_msdc1_wp_2_pins[] = { 209, };
-static int mt7623_msdc1_wp_2_funcs[] = { 2, };
-static int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, };
-static int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, };
-static int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256,
- 257, 258, 259, 260, };
-static int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118,
+ 119, 120, 121, };
+static const int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, };
+static const int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, };
+static const int mt7623_msdc1_ins_pins[] = { 261, };
+static const int mt7623_msdc1_ins_funcs[] = { 1, };
+static const int mt7623_msdc1_wp_0_pins[] = { 29, };
+static const int mt7623_msdc1_wp_0_funcs[] = { 1, };
+static const int mt7623_msdc1_wp_1_pins[] = { 55, };
+static const int mt7623_msdc1_wp_1_funcs[] = { 3, };
+static const int mt7623_msdc1_wp_2_pins[] = { 209, };
+static const int mt7623_msdc1_wp_2_funcs[] = { 2, };
+static const int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, };
+static const int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, };
+static const int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256,
+ 257, 258, 259, 260, };
+static const int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
/* NAND */
-static int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115,
- 116, 117, 118, 119, 120, 121, };
-static int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4,
- 4, 4, };
-static int mt7623_nandc_ceb0_pins[] = { 45, };
-static int mt7623_nandc_ceb0_funcs[] = { 1, };
-static int mt7623_nandc_ceb1_pins[] = { 44, };
-static int mt7623_nandc_ceb1_funcs[] = { 1, };
+static const int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115,
+ 116, 117, 118, 119, 120, 121, };
+static const int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4,
+ 4, 4, };
+static const int mt7623_nandc_ceb0_pins[] = { 45, };
+static const int mt7623_nandc_ceb0_funcs[] = { 1, };
+static const int mt7623_nandc_ceb1_pins[] = { 44, };
+static const int mt7623_nandc_ceb1_funcs[] = { 1, };
/* RTC */
-static int mt7623_rtc_pins[] = { 10, };
-static int mt7623_rtc_funcs[] = { 1, };
+static const int mt7623_rtc_pins[] = { 10, };
+static const int mt7623_rtc_funcs[] = { 1, };
/* OTG */
-static int mt7623_otg_iddig0_0_pins[] = { 29, };
-static int mt7623_otg_iddig0_0_funcs[] = { 1, };
-static int mt7623_otg_iddig0_1_pins[] = { 44, };
-static int mt7623_otg_iddig0_1_funcs[] = { 2, };
-static int mt7623_otg_iddig0_2_pins[] = { 236, };
-static int mt7623_otg_iddig0_2_funcs[] = { 2, };
-static int mt7623_otg_iddig1_0_pins[] = { 27, };
-static int mt7623_otg_iddig1_0_funcs[] = { 2, };
-static int mt7623_otg_iddig1_1_pins[] = { 47, };
-static int mt7623_otg_iddig1_1_funcs[] = { 2, };
-static int mt7623_otg_iddig1_2_pins[] = { 238, };
-static int mt7623_otg_iddig1_2_funcs[] = { 2, };
-static int mt7623_otg_drv_vbus0_0_pins[] = { 28, };
-static int mt7623_otg_drv_vbus0_0_funcs[] = { 1, };
-static int mt7623_otg_drv_vbus0_1_pins[] = { 45, };
-static int mt7623_otg_drv_vbus0_1_funcs[] = { 2, };
-static int mt7623_otg_drv_vbus0_2_pins[] = { 237, };
-static int mt7623_otg_drv_vbus0_2_funcs[] = { 2, };
-static int mt7623_otg_drv_vbus1_0_pins[] = { 26, };
-static int mt7623_otg_drv_vbus1_0_funcs[] = { 2, };
-static int mt7623_otg_drv_vbus1_1_pins[] = { 48, };
-static int mt7623_otg_drv_vbus1_1_funcs[] = { 2, };
-static int mt7623_otg_drv_vbus1_2_pins[] = { 239, };
-static int mt7623_otg_drv_vbus1_2_funcs[] = { 2, };
+static const int mt7623_otg_iddig0_0_pins[] = { 29, };
+static const int mt7623_otg_iddig0_0_funcs[] = { 1, };
+static const int mt7623_otg_iddig0_1_pins[] = { 44, };
+static const int mt7623_otg_iddig0_1_funcs[] = { 2, };
+static const int mt7623_otg_iddig0_2_pins[] = { 236, };
+static const int mt7623_otg_iddig0_2_funcs[] = { 2, };
+static const int mt7623_otg_iddig1_0_pins[] = { 27, };
+static const int mt7623_otg_iddig1_0_funcs[] = { 2, };
+static const int mt7623_otg_iddig1_1_pins[] = { 47, };
+static const int mt7623_otg_iddig1_1_funcs[] = { 2, };
+static const int mt7623_otg_iddig1_2_pins[] = { 238, };
+static const int mt7623_otg_iddig1_2_funcs[] = { 2, };
+static const int mt7623_otg_drv_vbus0_0_pins[] = { 28, };
+static const int mt7623_otg_drv_vbus0_0_funcs[] = { 1, };
+static const int mt7623_otg_drv_vbus0_1_pins[] = { 45, };
+static const int mt7623_otg_drv_vbus0_1_funcs[] = { 2, };
+static const int mt7623_otg_drv_vbus0_2_pins[] = { 237, };
+static const int mt7623_otg_drv_vbus0_2_funcs[] = { 2, };
+static const int mt7623_otg_drv_vbus1_0_pins[] = { 26, };
+static const int mt7623_otg_drv_vbus1_0_funcs[] = { 2, };
+static const int mt7623_otg_drv_vbus1_1_pins[] = { 48, };
+static const int mt7623_otg_drv_vbus1_1_funcs[] = { 2, };
+static const int mt7623_otg_drv_vbus1_2_pins[] = { 239, };
+static const int mt7623_otg_drv_vbus1_2_funcs[] = { 2, };
/* PCIE */
-static int mt7623_pcie0_0_perst_pins[] = { 208, };
-static int mt7623_pcie0_0_perst_funcs[] = { 3, };
-static int mt7623_pcie0_1_perst_pins[] = { 22, };
-static int mt7623_pcie0_1_perst_funcs[] = { 2, };
-static int mt7623_pcie1_0_perst_pins[] = { 209, };
-static int mt7623_pcie1_0_perst_funcs[] = { 3, };
-static int mt7623_pcie1_1_perst_pins[] = { 23, };
-static int mt7623_pcie1_1_perst_funcs[] = { 2, };
-static int mt7623_pcie2_0_perst_pins[] = { 24, };
-static int mt7623_pcie2_0_perst_funcs[] = { 2, };
-static int mt7623_pcie2_1_perst_pins[] = { 29, };
-static int mt7623_pcie2_1_perst_funcs[] = { 6, };
-static int mt7623_pcie0_0_wake_pins[] = { 28, };
-static int mt7623_pcie0_0_wake_funcs[] = { 6, };
-static int mt7623_pcie0_1_wake_pins[] = { 251, };
-static int mt7623_pcie0_1_wake_funcs[] = { 6, };
-static int mt7623_pcie1_0_wake_pins[] = { 27, };
-static int mt7623_pcie1_0_wake_funcs[] = { 6, };
-static int mt7623_pcie1_1_wake_pins[] = { 253, };
-static int mt7623_pcie1_1_wake_funcs[] = { 6, };
-static int mt7623_pcie2_0_wake_pins[] = { 26, };
-static int mt7623_pcie2_0_wake_funcs[] = { 6, };
-static int mt7623_pcie2_1_wake_pins[] = { 255, };
-static int mt7623_pcie2_1_wake_funcs[] = { 6, };
-static int mt7623_pcie0_clkreq_pins[] = { 250, };
-static int mt7623_pcie0_clkreq_funcs[] = { 6, };
-static int mt7623_pcie1_clkreq_pins[] = { 252, };
-static int mt7623_pcie1_clkreq_funcs[] = { 6, };
-static int mt7623_pcie2_clkreq_pins[] = { 254, };
-static int mt7623_pcie2_clkreq_funcs[] = { 6, };
+static const int mt7623_pcie0_0_perst_pins[] = { 208, };
+static const int mt7623_pcie0_0_perst_funcs[] = { 3, };
+static const int mt7623_pcie0_1_perst_pins[] = { 22, };
+static const int mt7623_pcie0_1_perst_funcs[] = { 2, };
+static const int mt7623_pcie1_0_perst_pins[] = { 209, };
+static const int mt7623_pcie1_0_perst_funcs[] = { 3, };
+static const int mt7623_pcie1_1_perst_pins[] = { 23, };
+static const int mt7623_pcie1_1_perst_funcs[] = { 2, };
+static const int mt7623_pcie2_0_perst_pins[] = { 24, };
+static const int mt7623_pcie2_0_perst_funcs[] = { 2, };
+static const int mt7623_pcie2_1_perst_pins[] = { 29, };
+static const int mt7623_pcie2_1_perst_funcs[] = { 6, };
+static const int mt7623_pcie0_0_wake_pins[] = { 28, };
+static const int mt7623_pcie0_0_wake_funcs[] = { 6, };
+static const int mt7623_pcie0_1_wake_pins[] = { 251, };
+static const int mt7623_pcie0_1_wake_funcs[] = { 6, };
+static const int mt7623_pcie1_0_wake_pins[] = { 27, };
+static const int mt7623_pcie1_0_wake_funcs[] = { 6, };
+static const int mt7623_pcie1_1_wake_pins[] = { 253, };
+static const int mt7623_pcie1_1_wake_funcs[] = { 6, };
+static const int mt7623_pcie2_0_wake_pins[] = { 26, };
+static const int mt7623_pcie2_0_wake_funcs[] = { 6, };
+static const int mt7623_pcie2_1_wake_pins[] = { 255, };
+static const int mt7623_pcie2_1_wake_funcs[] = { 6, };
+static const int mt7623_pcie0_clkreq_pins[] = { 250, };
+static const int mt7623_pcie0_clkreq_funcs[] = { 6, };
+static const int mt7623_pcie1_clkreq_pins[] = { 252, };
+static const int mt7623_pcie1_clkreq_funcs[] = { 6, };
+static const int mt7623_pcie2_clkreq_pins[] = { 254, };
+static const int mt7623_pcie2_clkreq_funcs[] = { 6, };
/* the pcie_*_rev are only used for MT7623 */
-static int mt7623_pcie0_0_rev_perst_pins[] = { 208, };
-static int mt7623_pcie0_0_rev_perst_funcs[] = { 11, };
-static int mt7623_pcie0_1_rev_perst_pins[] = { 22, };
-static int mt7623_pcie0_1_rev_perst_funcs[] = { 10, };
-static int mt7623_pcie1_0_rev_perst_pins[] = { 209, };
-static int mt7623_pcie1_0_rev_perst_funcs[] = { 11, };
-static int mt7623_pcie1_1_rev_perst_pins[] = { 23, };
-static int mt7623_pcie1_1_rev_perst_funcs[] = { 10, };
-static int mt7623_pcie2_0_rev_perst_pins[] = { 24, };
-static int mt7623_pcie2_0_rev_perst_funcs[] = { 11, };
-static int mt7623_pcie2_1_rev_perst_pins[] = { 29, };
-static int mt7623_pcie2_1_rev_perst_funcs[] = { 14, };
+static const int mt7623_pcie0_0_rev_perst_pins[] = { 208, };
+static const int mt7623_pcie0_0_rev_perst_funcs[] = { 11, };
+static const int mt7623_pcie0_1_rev_perst_pins[] = { 22, };
+static const int mt7623_pcie0_1_rev_perst_funcs[] = { 10, };
+static const int mt7623_pcie1_0_rev_perst_pins[] = { 209, };
+static const int mt7623_pcie1_0_rev_perst_funcs[] = { 11, };
+static const int mt7623_pcie1_1_rev_perst_pins[] = { 23, };
+static const int mt7623_pcie1_1_rev_perst_funcs[] = { 10, };
+static const int mt7623_pcie2_0_rev_perst_pins[] = { 24, };
+static const int mt7623_pcie2_0_rev_perst_funcs[] = { 11, };
+static const int mt7623_pcie2_1_rev_perst_pins[] = { 29, };
+static const int mt7623_pcie2_1_rev_perst_funcs[] = { 14, };
/* PCM */
-static int mt7623_pcm_clk_0_pins[] = { 18, };
-static int mt7623_pcm_clk_0_funcs[] = { 1, };
-static int mt7623_pcm_clk_1_pins[] = { 17, };
-static int mt7623_pcm_clk_1_funcs[] = { 3, };
-static int mt7623_pcm_clk_2_pins[] = { 35, };
-static int mt7623_pcm_clk_2_funcs[] = { 3, };
-static int mt7623_pcm_clk_3_pins[] = { 50, };
-static int mt7623_pcm_clk_3_funcs[] = { 3, };
-static int mt7623_pcm_clk_4_pins[] = { 74, };
-static int mt7623_pcm_clk_4_funcs[] = { 3, };
-static int mt7623_pcm_clk_5_pins[] = { 191, };
-static int mt7623_pcm_clk_5_funcs[] = { 3, };
-static int mt7623_pcm_clk_6_pins[] = { 196, };
-static int mt7623_pcm_clk_6_funcs[] = { 3, };
-static int mt7623_pcm_sync_0_pins[] = { 19, };
-static int mt7623_pcm_sync_0_funcs[] = { 1, };
-static int mt7623_pcm_sync_1_pins[] = { 30, };
-static int mt7623_pcm_sync_1_funcs[] = { 3, };
-static int mt7623_pcm_sync_2_pins[] = { 36, };
-static int mt7623_pcm_sync_2_funcs[] = { 3, };
-static int mt7623_pcm_sync_3_pins[] = { 52, };
-static int mt7623_pcm_sync_3_funcs[] = { 31, };
-static int mt7623_pcm_sync_4_pins[] = { 73, };
-static int mt7623_pcm_sync_4_funcs[] = { 3, };
-static int mt7623_pcm_sync_5_pins[] = { 192, };
-static int mt7623_pcm_sync_5_funcs[] = { 3, };
-static int mt7623_pcm_sync_6_pins[] = { 197, };
-static int mt7623_pcm_sync_6_funcs[] = { 3, };
-static int mt7623_pcm_rx_0_pins[] = { 20, };
-static int mt7623_pcm_rx_0_funcs[] = { 1, };
-static int mt7623_pcm_rx_1_pins[] = { 16, };
-static int mt7623_pcm_rx_1_funcs[] = { 3, };
-static int mt7623_pcm_rx_2_pins[] = { 34, };
-static int mt7623_pcm_rx_2_funcs[] = { 3, };
-static int mt7623_pcm_rx_3_pins[] = { 51, };
-static int mt7623_pcm_rx_3_funcs[] = { 3, };
-static int mt7623_pcm_rx_4_pins[] = { 72, };
-static int mt7623_pcm_rx_4_funcs[] = { 3, };
-static int mt7623_pcm_rx_5_pins[] = { 190, };
-static int mt7623_pcm_rx_5_funcs[] = { 3, };
-static int mt7623_pcm_rx_6_pins[] = { 195, };
-static int mt7623_pcm_rx_6_funcs[] = { 3, };
-static int mt7623_pcm_tx_0_pins[] = { 21, };
-static int mt7623_pcm_tx_0_funcs[] = { 1, };
-static int mt7623_pcm_tx_1_pins[] = { 32, };
-static int mt7623_pcm_tx_1_funcs[] = { 3, };
-static int mt7623_pcm_tx_2_pins[] = { 33, };
-static int mt7623_pcm_tx_2_funcs[] = { 3, };
-static int mt7623_pcm_tx_3_pins[] = { 38, };
-static int mt7623_pcm_tx_3_funcs[] = { 3, };
-static int mt7623_pcm_tx_4_pins[] = { 49, };
-static int mt7623_pcm_tx_4_funcs[] = { 3, };
-static int mt7623_pcm_tx_5_pins[] = { 189, };
-static int mt7623_pcm_tx_5_funcs[] = { 3, };
-static int mt7623_pcm_tx_6_pins[] = { 194, };
-static int mt7623_pcm_tx_6_funcs[] = { 3, };
+static const int mt7623_pcm_clk_0_pins[] = { 18, };
+static const int mt7623_pcm_clk_0_funcs[] = { 1, };
+static const int mt7623_pcm_clk_1_pins[] = { 17, };
+static const int mt7623_pcm_clk_1_funcs[] = { 3, };
+static const int mt7623_pcm_clk_2_pins[] = { 35, };
+static const int mt7623_pcm_clk_2_funcs[] = { 3, };
+static const int mt7623_pcm_clk_3_pins[] = { 50, };
+static const int mt7623_pcm_clk_3_funcs[] = { 3, };
+static const int mt7623_pcm_clk_4_pins[] = { 74, };
+static const int mt7623_pcm_clk_4_funcs[] = { 3, };
+static const int mt7623_pcm_clk_5_pins[] = { 191, };
+static const int mt7623_pcm_clk_5_funcs[] = { 3, };
+static const int mt7623_pcm_clk_6_pins[] = { 196, };
+static const int mt7623_pcm_clk_6_funcs[] = { 3, };
+static const int mt7623_pcm_sync_0_pins[] = { 19, };
+static const int mt7623_pcm_sync_0_funcs[] = { 1, };
+static const int mt7623_pcm_sync_1_pins[] = { 30, };
+static const int mt7623_pcm_sync_1_funcs[] = { 3, };
+static const int mt7623_pcm_sync_2_pins[] = { 36, };
+static const int mt7623_pcm_sync_2_funcs[] = { 3, };
+static const int mt7623_pcm_sync_3_pins[] = { 52, };
+static const int mt7623_pcm_sync_3_funcs[] = { 31, };
+static const int mt7623_pcm_sync_4_pins[] = { 73, };
+static const int mt7623_pcm_sync_4_funcs[] = { 3, };
+static const int mt7623_pcm_sync_5_pins[] = { 192, };
+static const int mt7623_pcm_sync_5_funcs[] = { 3, };
+static const int mt7623_pcm_sync_6_pins[] = { 197, };
+static const int mt7623_pcm_sync_6_funcs[] = { 3, };
+static const int mt7623_pcm_rx_0_pins[] = { 20, };
+static const int mt7623_pcm_rx_0_funcs[] = { 1, };
+static const int mt7623_pcm_rx_1_pins[] = { 16, };
+static const int mt7623_pcm_rx_1_funcs[] = { 3, };
+static const int mt7623_pcm_rx_2_pins[] = { 34, };
+static const int mt7623_pcm_rx_2_funcs[] = { 3, };
+static const int mt7623_pcm_rx_3_pins[] = { 51, };
+static const int mt7623_pcm_rx_3_funcs[] = { 3, };
+static const int mt7623_pcm_rx_4_pins[] = { 72, };
+static const int mt7623_pcm_rx_4_funcs[] = { 3, };
+static const int mt7623_pcm_rx_5_pins[] = { 190, };
+static const int mt7623_pcm_rx_5_funcs[] = { 3, };
+static const int mt7623_pcm_rx_6_pins[] = { 195, };
+static const int mt7623_pcm_rx_6_funcs[] = { 3, };
+static const int mt7623_pcm_tx_0_pins[] = { 21, };
+static const int mt7623_pcm_tx_0_funcs[] = { 1, };
+static const int mt7623_pcm_tx_1_pins[] = { 32, };
+static const int mt7623_pcm_tx_1_funcs[] = { 3, };
+static const int mt7623_pcm_tx_2_pins[] = { 33, };
+static const int mt7623_pcm_tx_2_funcs[] = { 3, };
+static const int mt7623_pcm_tx_3_pins[] = { 38, };
+static const int mt7623_pcm_tx_3_funcs[] = { 3, };
+static const int mt7623_pcm_tx_4_pins[] = { 49, };
+static const int mt7623_pcm_tx_4_funcs[] = { 3, };
+static const int mt7623_pcm_tx_5_pins[] = { 189, };
+static const int mt7623_pcm_tx_5_funcs[] = { 3, };
+static const int mt7623_pcm_tx_6_pins[] = { 194, };
+static const int mt7623_pcm_tx_6_funcs[] = { 3, };
/* PWM */
-static int mt7623_pwm_ch1_0_pins[] = { 203, };
-static int mt7623_pwm_ch1_0_funcs[] = { 1, };
-static int mt7623_pwm_ch1_1_pins[] = { 208, };
-static int mt7623_pwm_ch1_1_funcs[] = { 2, };
-static int mt7623_pwm_ch1_2_pins[] = { 72, };
-static int mt7623_pwm_ch1_2_funcs[] = { 4, };
-static int mt7623_pwm_ch1_3_pins[] = { 88, };
-static int mt7623_pwm_ch1_3_funcs[] = { 3, };
-static int mt7623_pwm_ch1_4_pins[] = { 108, };
-static int mt7623_pwm_ch1_4_funcs[] = { 3, };
-static int mt7623_pwm_ch2_0_pins[] = { 204, };
-static int mt7623_pwm_ch2_0_funcs[] = { 1, };
-static int mt7623_pwm_ch2_1_pins[] = { 53, };
-static int mt7623_pwm_ch2_1_funcs[] = { 5, };
-static int mt7623_pwm_ch2_2_pins[] = { 88, };
-static int mt7623_pwm_ch2_2_funcs[] = { 6, };
-static int mt7623_pwm_ch2_3_pins[] = { 108, };
-static int mt7623_pwm_ch2_3_funcs[] = { 6, };
-static int mt7623_pwm_ch2_4_pins[] = { 209, };
-static int mt7623_pwm_ch2_4_funcs[] = { 5, };
-static int mt7623_pwm_ch3_0_pins[] = { 205, };
-static int mt7623_pwm_ch3_0_funcs[] = { 1, };
-static int mt7623_pwm_ch3_1_pins[] = { 55, };
-static int mt7623_pwm_ch3_1_funcs[] = { 5, };
-static int mt7623_pwm_ch3_2_pins[] = { 89, };
-static int mt7623_pwm_ch3_2_funcs[] = { 6, };
-static int mt7623_pwm_ch3_3_pins[] = { 109, };
-static int mt7623_pwm_ch3_3_funcs[] = { 6, };
-static int mt7623_pwm_ch4_0_pins[] = { 206, };
-static int mt7623_pwm_ch4_0_funcs[] = { 1, };
-static int mt7623_pwm_ch4_1_pins[] = { 90, };
-static int mt7623_pwm_ch4_1_funcs[] = { 6, };
-static int mt7623_pwm_ch4_2_pins[] = { 110, };
-static int mt7623_pwm_ch4_2_funcs[] = { 6, };
-static int mt7623_pwm_ch4_3_pins[] = { 124, };
-static int mt7623_pwm_ch4_3_funcs[] = { 5, };
-static int mt7623_pwm_ch5_0_pins[] = { 207, };
-static int mt7623_pwm_ch5_0_funcs[] = { 1, };
-static int mt7623_pwm_ch5_1_pins[] = { 125, };
-static int mt7623_pwm_ch5_1_funcs[] = { 5, };
+static const int mt7623_pwm_ch1_0_pins[] = { 203, };
+static const int mt7623_pwm_ch1_0_funcs[] = { 1, };
+static const int mt7623_pwm_ch1_1_pins[] = { 208, };
+static const int mt7623_pwm_ch1_1_funcs[] = { 2, };
+static const int mt7623_pwm_ch1_2_pins[] = { 72, };
+static const int mt7623_pwm_ch1_2_funcs[] = { 4, };
+static const int mt7623_pwm_ch1_3_pins[] = { 88, };
+static const int mt7623_pwm_ch1_3_funcs[] = { 3, };
+static const int mt7623_pwm_ch1_4_pins[] = { 108, };
+static const int mt7623_pwm_ch1_4_funcs[] = { 3, };
+static const int mt7623_pwm_ch2_0_pins[] = { 204, };
+static const int mt7623_pwm_ch2_0_funcs[] = { 1, };
+static const int mt7623_pwm_ch2_1_pins[] = { 53, };
+static const int mt7623_pwm_ch2_1_funcs[] = { 5, };
+static const int mt7623_pwm_ch2_2_pins[] = { 88, };
+static const int mt7623_pwm_ch2_2_funcs[] = { 6, };
+static const int mt7623_pwm_ch2_3_pins[] = { 108, };
+static const int mt7623_pwm_ch2_3_funcs[] = { 6, };
+static const int mt7623_pwm_ch2_4_pins[] = { 209, };
+static const int mt7623_pwm_ch2_4_funcs[] = { 5, };
+static const int mt7623_pwm_ch3_0_pins[] = { 205, };
+static const int mt7623_pwm_ch3_0_funcs[] = { 1, };
+static const int mt7623_pwm_ch3_1_pins[] = { 55, };
+static const int mt7623_pwm_ch3_1_funcs[] = { 5, };
+static const int mt7623_pwm_ch3_2_pins[] = { 89, };
+static const int mt7623_pwm_ch3_2_funcs[] = { 6, };
+static const int mt7623_pwm_ch3_3_pins[] = { 109, };
+static const int mt7623_pwm_ch3_3_funcs[] = { 6, };
+static const int mt7623_pwm_ch4_0_pins[] = { 206, };
+static const int mt7623_pwm_ch4_0_funcs[] = { 1, };
+static const int mt7623_pwm_ch4_1_pins[] = { 90, };
+static const int mt7623_pwm_ch4_1_funcs[] = { 6, };
+static const int mt7623_pwm_ch4_2_pins[] = { 110, };
+static const int mt7623_pwm_ch4_2_funcs[] = { 6, };
+static const int mt7623_pwm_ch4_3_pins[] = { 124, };
+static const int mt7623_pwm_ch4_3_funcs[] = { 5, };
+static const int mt7623_pwm_ch5_0_pins[] = { 207, };
+static const int mt7623_pwm_ch5_0_funcs[] = { 1, };
+static const int mt7623_pwm_ch5_1_pins[] = { 125, };
+static const int mt7623_pwm_ch5_1_funcs[] = { 5, };
/* PWRAP */
-static int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, };
-static int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, };
+static const int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
/* SPDIF */
-static int mt7623_spdif_in0_0_pins[] = { 56, };
-static int mt7623_spdif_in0_0_funcs[] = { 3, };
-static int mt7623_spdif_in0_1_pins[] = { 201, };
-static int mt7623_spdif_in0_1_funcs[] = { 1, };
-static int mt7623_spdif_in1_0_pins[] = { 54, };
-static int mt7623_spdif_in1_0_funcs[] = { 3, };
-static int mt7623_spdif_in1_1_pins[] = { 202, };
-static int mt7623_spdif_in1_1_funcs[] = { 1, };
-static int mt7623_spdif_out_pins[] = { 202, };
-static int mt7623_spdif_out_funcs[] = { 1, };
+static const int mt7623_spdif_in0_0_pins[] = { 56, };
+static const int mt7623_spdif_in0_0_funcs[] = { 3, };
+static const int mt7623_spdif_in0_1_pins[] = { 201, };
+static const int mt7623_spdif_in0_1_funcs[] = { 1, };
+static const int mt7623_spdif_in1_0_pins[] = { 54, };
+static const int mt7623_spdif_in1_0_funcs[] = { 3, };
+static const int mt7623_spdif_in1_1_pins[] = { 202, };
+static const int mt7623_spdif_in1_1_funcs[] = { 1, };
+static const int mt7623_spdif_out_pins[] = { 202, };
+static const int mt7623_spdif_out_funcs[] = { 1, };
/* SPI */
-static int mt7623_spi0_pins[] = { 53, 54, 55, 56, };
-static int mt7623_spi0_funcs[] = { 1, 1, 1, 1, };
-static int mt7623_spi1_pins[] = { 7, 199, 8, 9, };
-static int mt7623_spi1_funcs[] = { 1, 1, 1, 1, };
-static int mt7623_spi2_pins[] = { 101, 104, 102, 103, };
-static int mt7623_spi2_funcs[] = { 1, 1, 1, 1, };
+static const int mt7623_spi0_pins[] = { 53, 54, 55, 56, };
+static const int mt7623_spi0_funcs[] = { 1, 1, 1, 1, };
+static const int mt7623_spi1_pins[] = { 7, 199, 8, 9, };
+static const int mt7623_spi1_funcs[] = { 1, 1, 1, 1, };
+static const int mt7623_spi2_pins[] = { 101, 104, 102, 103, };
+static const int mt7623_spi2_funcs[] = { 1, 1, 1, 1, };
/* UART */
-static int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, };
-static int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, };
-static int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, };
-static int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, };
-static int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, };
-static int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, };
-static int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, };
-static int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, };
-static int mt7623_uart0_rts_cts_pins[] = { 22, 23, };
-static int mt7623_uart0_rts_cts_funcs[] = { 1, 1, };
-static int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, };
-static int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, };
-static int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, };
-static int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, };
-static int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, };
-static int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, };
-static int mt7623_uart1_rts_cts_pins[] = { 24, 25, };
-static int mt7623_uart1_rts_cts_funcs[] = { 1, 1, };
-static int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, };
-static int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, };
-static int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, };
-static int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, };
-static int mt7623_uart2_rts_cts_pins[] = { 242, 243, };
-static int mt7623_uart2_rts_cts_funcs[] = { 1, 1, };
-static int mt7623_uart3_txd_rxd_pins[] = { 242, 243, };
-static int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, };
-static int mt7623_uart3_rts_cts_pins[] = { 26, 27, };
-static int mt7623_uart3_rts_cts_funcs[] = { 1, 1, };
+static const int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, };
+static const int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, };
+static const int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, };
+static const int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, };
+static const int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, };
+static const int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, };
+static const int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, };
+static const int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, };
+static const int mt7623_uart0_rts_cts_pins[] = { 22, 23, };
+static const int mt7623_uart0_rts_cts_funcs[] = { 1, 1, };
+static const int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, };
+static const int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, };
+static const int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, };
+static const int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, };
+static const int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, };
+static const int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, };
+static const int mt7623_uart1_rts_cts_pins[] = { 24, 25, };
+static const int mt7623_uart1_rts_cts_funcs[] = { 1, 1, };
+static const int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, };
+static const int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, };
+static const int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, };
+static const int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, };
+static const int mt7623_uart2_rts_cts_pins[] = { 242, 243, };
+static const int mt7623_uart2_rts_cts_funcs[] = { 1, 1, };
+static const int mt7623_uart3_txd_rxd_pins[] = { 242, 243, };
+static const int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, };
+static const int mt7623_uart3_rts_cts_pins[] = { 26, 27, };
+static const int mt7623_uart3_rts_cts_funcs[] = { 1, 1, };
/* Watchdog */
-static int mt7623_watchdog_0_pins[] = { 11, };
-static int mt7623_watchdog_0_funcs[] = { 1, };
-static int mt7623_watchdog_1_pins[] = { 121, };
-static int mt7623_watchdog_1_funcs[] = { 5, };
+static const int mt7623_watchdog_0_pins[] = { 11, };
+static const int mt7623_watchdog_0_funcs[] = { 1, };
+static const int mt7623_watchdog_1_pins[] = { 121, };
+static const int mt7623_watchdog_1_funcs[] = { 5, };
static const struct mtk_group_desc mt7623_groups[] = {
PINCTRL_PIN_GROUP("aud_ext_clk0", mt7623_aud_ext_clk0),
@@ -1362,7 +1362,7 @@
{"watchdog", mt7623_wdt_groups, ARRAY_SIZE(mt7623_wdt_groups)},
};
-static struct mtk_pinctrl_soc mt7623_data = {
+static const struct mtk_pinctrl_soc mt7623_data = {
.name = "mt7623_pinctrl",
.reg_cal = mt7623_reg_cals,
.pins = mt7623_pins,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
index 5d4bec2..45d4def 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
@@ -180,118 +180,118 @@
*/
/* WF 5G */
-static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, };
-static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, };
+static const int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
/* LED for EPHY */
-static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, };
-static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
-static int mt7629_ephy_led0_pins[] = { 12, };
-static int mt7629_ephy_led0_funcs[] = { 1, };
-static int mt7629_ephy_led1_pins[] = { 13, };
-static int mt7629_ephy_led1_funcs[] = { 1, };
-static int mt7629_ephy_led2_pins[] = { 14, };
-static int mt7629_ephy_led2_funcs[] = { 1, };
-static int mt7629_ephy_led3_pins[] = { 15, };
-static int mt7629_ephy_led3_funcs[] = { 1, };
-static int mt7629_ephy_led4_pins[] = { 16, };
-static int mt7629_ephy_led4_funcs[] = { 1, };
-static int mt7629_wf2g_led_pins[] = { 17, };
-static int mt7629_wf2g_led_funcs[] = { 1, };
-static int mt7629_wf5g_led_pins[] = { 18, };
-static int mt7629_wf5g_led_funcs[] = { 1, };
+static const int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, };
+static const int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7629_ephy_led0_pins[] = { 12, };
+static const int mt7629_ephy_led0_funcs[] = { 1, };
+static const int mt7629_ephy_led1_pins[] = { 13, };
+static const int mt7629_ephy_led1_funcs[] = { 1, };
+static const int mt7629_ephy_led2_pins[] = { 14, };
+static const int mt7629_ephy_led2_funcs[] = { 1, };
+static const int mt7629_ephy_led3_pins[] = { 15, };
+static const int mt7629_ephy_led3_funcs[] = { 1, };
+static const int mt7629_ephy_led4_pins[] = { 16, };
+static const int mt7629_ephy_led4_funcs[] = { 1, };
+static const int mt7629_wf2g_led_pins[] = { 17, };
+static const int mt7629_wf2g_led_funcs[] = { 1, };
+static const int mt7629_wf5g_led_pins[] = { 18, };
+static const int mt7629_wf5g_led_funcs[] = { 1, };
/* LED for EPHY used as JTAG */
-static int mt7629_ephy_leds_jtag_pins[] = { 12, 13, 14, 15, 16, };
-static int mt7629_ephy_leds_jtag_funcs[] = { 7, 7, 7, 7, 7, };
+static const int mt7629_ephy_leds_jtag_pins[] = { 12, 13, 14, 15, 16, };
+static const int mt7629_ephy_leds_jtag_funcs[] = { 7, 7, 7, 7, 7, };
/* Watchdog */
-static int mt7629_watchdog_pins[] = { 11, };
-static int mt7629_watchdog_funcs[] = { 1, };
+static const int mt7629_watchdog_pins[] = { 11, };
+static const int mt7629_watchdog_funcs[] = { 1, };
/* LED for GPHY */
-static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, };
-static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, };
-static int mt7629_gphy_led1_0_pins[] = { 21, };
-static int mt7629_gphy_led1_0_funcs[] = { 2, };
-static int mt7629_gphy_led2_0_pins[] = { 22, };
-static int mt7629_gphy_led2_0_funcs[] = { 2, };
-static int mt7629_gphy_led3_0_pins[] = { 23, };
-static int mt7629_gphy_led3_0_funcs[] = { 2, };
-static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, };
-static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, };
-static int mt7629_gphy_led1_1_pins[] = { 57, };
-static int mt7629_gphy_led1_1_funcs[] = { 1, };
-static int mt7629_gphy_led2_1_pins[] = { 58, };
-static int mt7629_gphy_led2_1_funcs[] = { 1, };
-static int mt7629_gphy_led3_1_pins[] = { 59, };
-static int mt7629_gphy_led3_1_funcs[] = { 1, };
+static const int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, };
+static const int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, };
+static const int mt7629_gphy_led1_0_pins[] = { 21, };
+static const int mt7629_gphy_led1_0_funcs[] = { 2, };
+static const int mt7629_gphy_led2_0_pins[] = { 22, };
+static const int mt7629_gphy_led2_0_funcs[] = { 2, };
+static const int mt7629_gphy_led3_0_pins[] = { 23, };
+static const int mt7629_gphy_led3_0_funcs[] = { 2, };
+static const int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, };
+static const int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, };
+static const int mt7629_gphy_led1_1_pins[] = { 57, };
+static const int mt7629_gphy_led1_1_funcs[] = { 1, };
+static const int mt7629_gphy_led2_1_pins[] = { 58, };
+static const int mt7629_gphy_led2_1_funcs[] = { 1, };
+static const int mt7629_gphy_led3_1_pins[] = { 59, };
+static const int mt7629_gphy_led3_1_funcs[] = { 1, };
/* I2C */
-static int mt7629_i2c_0_pins[] = { 19, 20, };
-static int mt7629_i2c_0_funcs[] = { 1, 1, };
-static int mt7629_i2c_1_pins[] = { 53, 54, };
-static int mt7629_i2c_1_funcs[] = { 1, 1, };
+static const int mt7629_i2c_0_pins[] = { 19, 20, };
+static const int mt7629_i2c_0_funcs[] = { 1, 1, };
+static const int mt7629_i2c_1_pins[] = { 53, 54, };
+static const int mt7629_i2c_1_funcs[] = { 1, 1, };
/* SPI */
-static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, };
-static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, };
-static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, };
-static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, };
-static int mt7629_spi_wp_pins[] = { 66, };
-static int mt7629_spi_wp_funcs[] = { 1, };
-static int mt7629_spi_hold_pins[] = { 67, };
-static int mt7629_spi_hold_funcs[] = { 1, };
+static const int mt7629_spi_0_pins[] = { 21, 22, 23, 24, };
+static const int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, };
+static const int mt7629_spi_1_pins[] = { 62, 63, 64, 65, };
+static const int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, };
+static const int mt7629_spi_wp_pins[] = { 66, };
+static const int mt7629_spi_wp_funcs[] = { 1, };
+static const int mt7629_spi_hold_pins[] = { 67, };
+static const int mt7629_spi_hold_funcs[] = { 1, };
/* UART */
-static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, };
-static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, };
-static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, };
-static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, };
-static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, };
-static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, };
-static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, };
-static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, };
-static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, };
-static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, };
-static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, };
-static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, };
-static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, };
-static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, };
-static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, };
-static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, };
-static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, };
-static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, };
+static const int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, };
+static const int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, };
+static const int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, };
+static const int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, };
+static const int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, };
+static const int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, };
+static const int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, };
+static const int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, };
+static const int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, };
+static const int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, };
+static const int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, };
+static const int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, };
+static const int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, };
+static const int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, };
+static const int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, };
+static const int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, };
+static const int mt7629_uart0_txd_rxd_pins[] = { 68, 69, };
+static const int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, };
/* MDC/MDIO */
-static int mt7629_mdc_mdio_pins[] = { 49, 50, };
-static int mt7629_mdc_mdio_funcs[] = { 1, 1, };
+static const int mt7629_mdc_mdio_pins[] = { 49, 50, };
+static const int mt7629_mdc_mdio_funcs[] = { 1, 1, };
/* PCIE */
-static int mt7629_pcie_pereset_pins[] = { 51, };
-static int mt7629_pcie_pereset_funcs[] = { 1, };
-static int mt7629_pcie_wake_pins[] = { 55, };
-static int mt7629_pcie_wake_funcs[] = { 1, };
-static int mt7629_pcie_clkreq_pins[] = { 56, };
-static int mt7629_pcie_clkreq_funcs[] = { 1, };
+static const int mt7629_pcie_pereset_pins[] = { 51, };
+static const int mt7629_pcie_pereset_funcs[] = { 1, };
+static const int mt7629_pcie_wake_pins[] = { 55, };
+static const int mt7629_pcie_wake_funcs[] = { 1, };
+static const int mt7629_pcie_clkreq_pins[] = { 56, };
+static const int mt7629_pcie_clkreq_funcs[] = { 1, };
/* PWM */
-static int mt7629_pwm_0_pins[] = { 52, };
-static int mt7629_pwm_0_funcs[] = { 1, };
-static int mt7629_pwm_1_pins[] = { 61, };
-static int mt7629_pwm_1_funcs[] = { 2, };
+static const int mt7629_pwm_0_pins[] = { 52, };
+static const int mt7629_pwm_0_funcs[] = { 1, };
+static const int mt7629_pwm_1_pins[] = { 61, };
+static const int mt7629_pwm_1_funcs[] = { 2, };
/* WF 2G */
-static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, };
-static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, };
+static const int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
/* SNFI */
-static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 };
-static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
+static const int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 };
+static const int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
/* SPI NOR */
-static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 };
-static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 };
+static const int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 };
+static const int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 };
static const struct mtk_group_desc mt7629_groups[] = {
PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g),
@@ -385,7 +385,7 @@
{"jtag", mt7629_jtag_groups, ARRAY_SIZE(mt7629_jtag_groups)},
};
-static struct mtk_pinctrl_soc mt7629_data = {
+static const struct mtk_pinctrl_soc mt7629_data = {
.name = "mt7629_pinctrl",
.reg_cal = mt7629_reg_cals,
.pins = mt7629_pins,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
index d887524..3fa198e 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
@@ -570,242 +570,246 @@
};
/* WA_AICE */
-static int mt7981_wa_aice1_pins[] = { 0, 1, };
-static int mt7981_wa_aice1_funcs[] = { 2, 2, };
+static const int mt7981_wa_aice1_pins[] = { 0, 1, };
+static const int mt7981_wa_aice1_funcs[] = { 2, 2, };
-static int mt7981_wa_aice2_pins[] = { 0, 1, };
-static int mt7981_wa_aice2_funcs[] = { 3, 3, };
+static const int mt7981_wa_aice2_pins[] = { 0, 1, };
+static const int mt7981_wa_aice2_funcs[] = { 3, 3, };
-static int mt7981_wa_aice3_pins[] = { 28, 29, };
-static int mt7981_wa_aice3_funcs[] = { 3, 3, };
+static const int mt7981_wa_aice3_pins[] = { 28, 29, };
+static const int mt7981_wa_aice3_funcs[] = { 3, 3, };
-static int mt7981_wm_aice1_pins[] = { 9, 10, };
-static int mt7981_wm_aice1_funcs[] = { 2, 2, };
+static const int mt7981_wm_aice1_pins[] = { 9, 10, };
+static const int mt7981_wm_aice1_funcs[] = { 2, 2, };
-static int mt7981_wm_aice2_pins[] = { 30, 31, };
-static int mt7981_wm_aice2_funcs[] = { 5, 5, };
+static const int mt7981_wm_aice2_pins[] = { 30, 31, };
+static const int mt7981_wm_aice2_funcs[] = { 5, 5, };
/* WM_UART */
-static int mt7981_wm_uart_0_pins[] = { 0, 1, };
-static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
+static const int mt7981_wm_uart_0_pins[] = { 0, 1, };
+static const int mt7981_wm_uart_0_funcs[] = { 5, 5, };
-static int mt7981_wm_uart_1_pins[] = { 20, 21, };
-static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
+static const int mt7981_wm_uart_1_pins[] = { 20, 21, };
+static const int mt7981_wm_uart_1_funcs[] = { 4, 4, };
-static int mt7981_wm_uart_2_pins[] = { 30, 31, };
-static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
+static const int mt7981_wm_uart_2_pins[] = { 30, 31, };
+static const int mt7981_wm_uart_2_funcs[] = { 3, 3, };
/* DFD */
-static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
-static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
+static const int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
+static const int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
/* SYS_WATCHDOG */
-static int mt7981_watchdog_pins[] = { 2, };
-static int mt7981_watchdog_funcs[] = { 1, };
+static const int mt7981_watchdog_pins[] = { 2, };
+static const int mt7981_watchdog_funcs[] = { 1, };
-static int mt7981_watchdog1_pins[] = { 13, };
-static int mt7981_watchdog1_funcs[] = { 5, };
+static const int mt7981_watchdog1_pins[] = { 13, };
+static const int mt7981_watchdog1_funcs[] = { 5, };
/* PCIE_PERESET_N */
-static int mt7981_pcie_pereset_pins[] = { 3, };
-static int mt7981_pcie_pereset_funcs[] = { 1, };
+static const int mt7981_pcie_pereset_pins[] = { 3, };
+static const int mt7981_pcie_pereset_funcs[] = { 1, };
/* JTAG */
-static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
-static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
+static const int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
+static const int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
/* WM_JTAG */
-static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
-static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
+static const int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
+static const int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
-static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
-static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
+static const int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
+static const int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
/* WO0_JTAG */
-static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
-static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
+static const int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
+static const int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
-static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
-static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
+static const int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
+static const int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
/* UART2 */
-static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
-static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
+static const int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
+static const int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
/* GBE_LED0 */
-static int mt7981_gbe_led0_pins[] = { 8, };
-static int mt7981_gbe_led0_funcs[] = { 3, };
+static const int mt7981_gbe_led0_pins[] = { 8, };
+static const int mt7981_gbe_led0_funcs[] = { 3, };
/* PTA_EXT */
-static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
-static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
+static const int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
+static const int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
-static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
-static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
+static const int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
+static const int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
/* PWM2 */
-static int mt7981_pwm2_pins[] = { 7, };
-static int mt7981_pwm2_funcs[] = { 4, };
+static const int mt7981_pwm2_pins[] = { 7, };
+static const int mt7981_pwm2_funcs[] = { 4, };
/* NET_WO0_UART_TXD */
-static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
-static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
+static const int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
+static const int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
-static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
-static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
+static const int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
+static const int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
-static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
-static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
+static const int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
+static const int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
/* SPI1 */
-static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
-static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
+static const int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
+static const int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
/* I2C */
-static int mt7981_i2c0_0_pins[] = { 6, 7, };
-static int mt7981_i2c0_0_funcs[] = { 6, 6, };
+static const int mt7981_i2c0_0_pins[] = { 6, 7, };
+static const int mt7981_i2c0_0_funcs[] = { 6, 6, };
-static int mt7981_i2c0_1_pins[] = { 30, 31, };
-static int mt7981_i2c0_1_funcs[] = { 4, 4, };
+static const int mt7981_i2c0_1_pins[] = { 30, 31, };
+static const int mt7981_i2c0_1_funcs[] = { 4, 4, };
-static int mt7981_i2c0_2_pins[] = { 36, 37, };
-static int mt7981_i2c0_2_funcs[] = { 2, 2, };
+static const int mt7981_i2c0_2_pins[] = { 36, 37, };
+static const int mt7981_i2c0_2_funcs[] = { 2, 2, };
-static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
-static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
+static const int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
+static const int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
-static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
+static const int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
+static const int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
-static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
+static const int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
+static const int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
-static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
+static const int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
+static const int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
/* DFD_NTRST */
-static int mt7981_dfd_ntrst_pins[] = { 8, };
-static int mt7981_dfd_ntrst_funcs[] = { 6, };
+static const int mt7981_dfd_ntrst_pins[] = { 8, };
+static const int mt7981_dfd_ntrst_funcs[] = { 6, };
/* PWM0 */
-static int mt7981_pwm0_0_pins[] = { 13, };
-static int mt7981_pwm0_0_funcs[] = { 2, };
+static const int mt7981_pwm0_0_pins[] = { 13, };
+static const int mt7981_pwm0_0_funcs[] = { 2, };
-static int mt7981_pwm0_1_pins[] = { 15, };
-static int mt7981_pwm0_1_funcs[] = { 1, };
+static const int mt7981_pwm0_1_pins[] = { 15, };
+static const int mt7981_pwm0_1_funcs[] = { 1, };
/* PWM1 */
-static int mt7981_pwm1_0_pins[] = { 14, };
-static int mt7981_pwm1_0_funcs[] = { 2, };
+static const int mt7981_pwm1_0_pins[] = { 14, };
+static const int mt7981_pwm1_0_funcs[] = { 2, };
-static int mt7981_pwm1_1_pins[] = { 15, };
-static int mt7981_pwm1_1_funcs[] = { 3, };
+static const int mt7981_pwm1_1_pins[] = { 15, };
+static const int mt7981_pwm1_1_funcs[] = { 3, };
/* GBE_LED1 */
-static int mt7981_gbe_led1_pins[] = { 13, };
-static int mt7981_gbe_led1_funcs[] = { 3, };
+static const int mt7981_gbe_led1_pins[] = { 13, };
+static const int mt7981_gbe_led1_funcs[] = { 3, };
/* PCM */
-static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
-static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
+static const int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
+static const int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
/* UDI */
-static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
-static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
+static const int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
+static const int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
/* DRV_VBUS */
-static int mt7981_drv_vbus_pins[] = { 14, };
-static int mt7981_drv_vbus_funcs[] = { 1, };
+static const int mt7981_drv_vbus_pins[] = { 14, };
+static const int mt7981_drv_vbus_funcs[] = { 1, };
/* EMMC */
-static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
-static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
+static const int mt7981_emmc_45_pins[] = {
+ 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
+static const int mt7981_emmc_45_funcs[] = {
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
/* SNFI */
-static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
-static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
+static const int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
+static const int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
/* SPI0 */
-static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
-static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
+static const int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
+static const int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
/* SPI0 */
-static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
-static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
+static const int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
+static const int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
/* SPI1 */
-static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
-static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
+static const int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
+static const int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
/* SPI2 */
-static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
-static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
+static const int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
+static const int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
/* SPI2 */
-static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
-static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
+static const int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
+static const int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
/* UART1 */
-static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
-static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
+static const int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
+static const int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
-static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
-static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
+static const int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
+static const int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
/* UART2 */
-static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
-static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
+static const int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
+static const int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
/* UART0 */
-static int mt7981_uart0_pins[] = { 32, 33, };
-static int mt7981_uart0_funcs[] = { 1, 1, };
+static const int mt7981_uart0_pins[] = { 32, 33, };
+static const int mt7981_uart0_funcs[] = { 1, 1, };
/* PCIE_CLK_REQ */
-static int mt7981_pcie_clk_pins[] = { 34, };
-static int mt7981_pcie_clk_funcs[] = { 2, };
+static const int mt7981_pcie_clk_pins[] = { 34, };
+static const int mt7981_pcie_clk_funcs[] = { 2, };
/* PCIE_WAKE_N */
-static int mt7981_pcie_wake_pins[] = { 35, };
-static int mt7981_pcie_wake_funcs[] = { 2, };
+static const int mt7981_pcie_wake_pins[] = { 35, };
+static const int mt7981_pcie_wake_funcs[] = { 2, };
/* MDC_MDIO */
-static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
-static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
+static const int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
+static const int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
-static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
-static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
+static const int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
+static const int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
/* WF0_MODE1 */
-static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
- 50, 51, 52, 53, 54, 55, 56 };
-static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1 };
+static const int mt7981_wf0_mode1_pins[] = {
+ 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 };
+static const int mt7981_wf0_mode1_funcs[] = {
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
/* WF0_MODE3 */
-static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
-static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
+static const int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
+static const int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
/* WF2G_LED */
-static int mt7981_wf2g_led0_pins[] = { 30, };
-static int mt7981_wf2g_led0_funcs[] = { 2, };
+static const int mt7981_wf2g_led0_pins[] = { 30, };
+static const int mt7981_wf2g_led0_funcs[] = { 2, };
-static int mt7981_wf2g_led1_pins[] = { 34, };
-static int mt7981_wf2g_led1_funcs[] = { 1, };
+static const int mt7981_wf2g_led1_pins[] = { 34, };
+static const int mt7981_wf2g_led1_funcs[] = { 1, };
/* WF5G_LED */
-static int mt7981_wf5g_led0_pins[] = { 31, };
-static int mt7981_wf5g_led0_funcs[] = { 2, };
+static const int mt7981_wf5g_led0_pins[] = { 31, };
+static const int mt7981_wf5g_led0_funcs[] = { 2, };
-static int mt7981_wf5g_led1_pins[] = { 35, };
-static int mt7981_wf5g_led1_funcs[] = { 1, };
+static const int mt7981_wf5g_led1_pins[] = { 35, };
+static const int mt7981_wf5g_led1_funcs[] = { 1, };
/* MT7531_INT */
-static int mt7981_mt7531_int_pins[] = { 38, };
-static int mt7981_mt7531_int_funcs[] = { 1, };
+static const int mt7981_mt7531_int_pins[] = { 38, };
+static const int mt7981_mt7531_int_funcs[] = { 1, };
/* ANT_SEL */
-static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
-static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
+static const int mt7981_ant_sel_pins[] = {
+ 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
+static const int mt7981_ant_sel_funcs[] = {
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
static const struct mtk_group_desc mt7981_groups[] = {
/* @GPIO(0,1): WA_AICE(2) */
@@ -1012,7 +1016,7 @@
"iocfg_lb_base", "iocfg_bl_base", "iocfg_tm_base", "iocfg_tl_base",
};
-static struct mtk_pinctrl_soc mt7981_data = {
+static const struct mtk_pinctrl_soc mt7981_data = {
.name = "mt7981_pinctrl",
.reg_cal = mt7981_reg_cals,
.pins = mt7981_pins,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
index 449e5ad..819d644 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
@@ -554,114 +554,117 @@
* The hardware probably has multiple combinations of these pinouts.
*/
-static int mt7986_watchdog_pins[] = { 0, };
-static int mt7986_watchdog_funcs[] = { 1, };
+static const int mt7986_watchdog_pins[] = { 0, };
+static const int mt7986_watchdog_funcs[] = { 1, };
-static int mt7986_wifi_led_pins[] = { 1, 2, };
-static int mt7986_wifi_led_funcs[] = { 1, 1, };
+static const int mt7986_wifi_led_pins[] = { 1, 2, };
+static const int mt7986_wifi_led_funcs[] = { 1, 1, };
-static int mt7986_i2c_pins[] = { 3, 4, };
-static int mt7986_i2c_funcs[] = { 1, 1, };
+static const int mt7986_i2c_pins[] = { 3, 4, };
+static const int mt7986_i2c_funcs[] = { 1, 1, };
-static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, };
-static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, };
+static const int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, };
+static const int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, };
-static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, };
-static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, };
+static const int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, };
+static const int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, };
-static int mt7986_pwm1_1_pins[] = { 20, };
-static int mt7986_pwm1_1_funcs[] = { 2, };
+static const int mt7986_pwm1_1_pins[] = { 20, };
+static const int mt7986_pwm1_1_funcs[] = { 2, };
-static int mt7986_pwm0_pins[] = { 21, };
-static int mt7986_pwm0_funcs[] = { 1, };
+static const int mt7986_pwm0_pins[] = { 21, };
+static const int mt7986_pwm0_funcs[] = { 1, };
-static int mt7986_pwm1_0_pins[] = { 22, };
-static int mt7986_pwm1_0_funcs[] = { 1, };
+static const int mt7986_pwm1_0_pins[] = { 22, };
+static const int mt7986_pwm1_0_funcs[] = { 1, };
-static int mt7986_emmc_45_pins[] = {
+static const int mt7986_emmc_45_pins[] = {
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, };
-static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
+static const int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, };
-static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, };
+static const int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, };
+static const int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, };
-static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, };
-static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, };
+static const int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, };
+static const int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, };
-static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, };
-static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, };
+static const int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, };
+static const int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, };
-static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
-static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
+static const int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
+static const int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
-static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
-static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
+static const int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
+static const int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
-static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
-static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
+static const int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
+static const int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
-static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
-static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
+static const int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
+static const int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
-static int mt7986_spi0_wp_hold_pins[] = { 37, 38, };
-static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, };
+static const int mt7986_spi0_wp_hold_pins[] = { 37, 38, };
+static const int mt7986_spi0_wp_hold_funcs[] = { 1, 1, };
-static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
-static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, };
+static const int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
+static const int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, };
-static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
-static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, };
+static const int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
+static const int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, };
-static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, };
-static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, };
+static const int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, };
+static const int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, };
-static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
-static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, };
+static const int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
+static const int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, };
-static int mt7986_uart0_pins[] = { 39, 40, };
-static int mt7986_uart0_funcs[] = { 1, 1, };
+static const int mt7986_uart0_pins[] = { 39, 40, };
+static const int mt7986_uart0_funcs[] = { 1, 1, };
-static int mt7986_pcie_reset_pins[] = { 41, };
-static int mt7986_pcie_reset_funcs[] = { 1, };
+static const int mt7986_pcie_reset_pins[] = { 41, };
+static const int mt7986_pcie_reset_funcs[] = { 1, };
-static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
-static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
+static const int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
+static const int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
-static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
-static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
+static const int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
+static const int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
-static int mt7986_emmc_51_pins[] = {
+static const int mt7986_emmc_51_pins[] = {
50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, };
-static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7986_emmc_51_funcs[] = {
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-static int mt7986_pcm_pins[] = { 62, 63, 64, 65, };
-static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, };
+static const int mt7986_pcm_pins[] = { 62, 63, 64, 65, };
+static const int mt7986_pcm_funcs[] = { 1, 1, 1, 1, };
-static int mt7986_i2s_pins[] = { 62, 63, 64, 65, };
-static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, };
+static const int mt7986_i2s_pins[] = { 62, 63, 64, 65, };
+static const int mt7986_i2s_funcs[] = { 1, 1, 1, 1, };
-static int mt7986_switch_int_pins[] = { 66, };
-static int mt7986_switch_int_funcs[] = { 1, };
+static const int mt7986_switch_int_pins[] = { 66, };
+static const int mt7986_switch_int_funcs[] = { 1, };
-static int mt7986_mdc_mdio_pins[] = { 67, 68, };
-static int mt7986_mdc_mdio_funcs[] = { 1, 1, };
+static const int mt7986_mdc_mdio_pins[] = { 67, 68, };
+static const int mt7986_mdc_mdio_funcs[] = { 1, 1, };
-static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, };
-static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7986_wf_2g_pins[] = {
+ 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, };
+static const int mt7986_wf_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, };
-static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt7986_wf_5g_pins[] = {
+ 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, };
+static const int mt7986_wf_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-static int mt7986_wf_dbdc_pins[] = {
+static const int mt7986_wf_dbdc_pins[] = {
74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
-static int mt7986_wf_dbdc_funcs[] = {
+static const int mt7986_wf_dbdc_funcs[] = {
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-static int mt7986_pcie_clk_pins[] = { 9, };
-static int mt7986_pcie_clk_funcs[] = { 1, };
+static const int mt7986_pcie_clk_pins[] = { 9, };
+static const int mt7986_pcie_clk_funcs[] = { 1, };
-static int mt7986_pcie_wake_pins[] = { 10, };
-static int mt7986_pcie_wake_funcs[] = { 1, };
+static const int mt7986_pcie_wake_pins[] = { 10, };
+static const int mt7986_pcie_wake_funcs[] = { 1, };
static const struct mtk_group_desc mt7986_groups[] = {
PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog),
@@ -738,7 +741,7 @@
{"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)},
};
-static struct mtk_pinctrl_soc mt7986_data = {
+static const struct mtk_pinctrl_soc mt7986_data = {
.name = "mt7986_pinctrl",
.reg_cal = mt7986_reg_cals,
.pins = mt7986_pins,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/drivers/pinctrl/mediatek/pinctrl-mt7988.c
new file mode 100644
index 0000000..03a38e8
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c
@@ -0,0 +1,1274 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <dm.h>
+#include "pinctrl-mtk-common.h"
+
+enum MT7988_PINCTRL_REG_PAGE {
+ GPIO_BASE,
+ IOCFG_TR_BASE,
+ IOCFG_BR_BASE,
+ IOCFG_RB_BASE,
+ IOCFG_LB_BASE,
+ IOCFG_TL_BASE,
+};
+
+#define MT7988_TYPE0_PIN(_number, _name) \
+ MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0)
+
+#define MT7988_TYPE1_PIN(_number, _name) \
+ MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1)
+
+#define MT7988_TYPE2_PIN(_number, _name) \
+ MTK_TYPED_PIN(_number, _name, DRV_FIXED, IO_TYPE_GRP2)
+
+#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs, \
+ _s_bit, _x_bits, 32, 0)
+
+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
+ _x_bits) \
+ PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \
+ _s_bit, _x_bits, 32, 0)
+
+#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
+ _x_bits) \
+ PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \
+ _s_bit, _x_bits, 32, 1)
+
+static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = {
+ PIN_FIELD_GPIO(0, 83, 0x300, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = {
+ PIN_FIELD_GPIO(0, 83, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_di_range[] = {
+ PIN_FIELD_GPIO(0, 83, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_do_range[] = {
+ PIN_FIELD_GPIO(0, 83, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
+ PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x30, 0x10, 13, 1),
+ PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x30, 0x10, 14, 1),
+ PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x30, 0x10, 11, 1),
+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x30, 0x10, 12, 1),
+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x30, 0x10, 9, 1),
+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x30, 0x10, 10, 1),
+
+ PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x30, 0x10, 8, 1),
+ PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x30, 0x10, 6, 1),
+ PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x30, 0x10, 5, 1),
+ PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x30, 0x10, 3, 1),
+
+ PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x40, 0x10, 0, 1),
+ PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x40, 0x10, 21, 1),
+ PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x40, 0x10, 1, 1),
+ PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x40, 0x10, 2, 1),
+
+ PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0x30, 0x10, 7, 1),
+ PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
+ PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0x30, 0x10, 3, 1),
+ PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
+
+ PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x30, 0x10, 7, 1),
+ PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x30, 0x10, 4, 1),
+
+ PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x50, 0x10, 17, 1),
+ PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x50, 0x10, 23, 1),
+ PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x50, 0x10, 20, 1),
+ PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x50, 0x10, 19, 1),
+ PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x50, 0x10, 21, 1),
+ PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x50, 0x10, 22, 1),
+ PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x50, 0x10, 18, 1),
+ PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x50, 0x10, 25, 1),
+ PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x50, 0x10, 26, 1),
+ PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x50, 0x10, 27, 1),
+ PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x50, 0x10, 24, 1),
+ PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x50, 0x10, 28, 1),
+ PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x60, 0x10, 0, 1),
+ PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x50, 0x10, 31, 1),
+ PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x50, 0x10, 29, 1),
+ PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x50, 0x10, 30, 1),
+ PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x60, 0x10, 1, 1),
+ PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x50, 0x10, 11, 1),
+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x50, 0x10, 10, 1),
+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x50, 0x10, 0, 1),
+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x50, 0x10, 1, 1),
+ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x50, 0x10, 9, 1),
+ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x50, 0x10, 8, 1),
+ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x50, 0x10, 7, 1),
+ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x50, 0x10, 6, 1),
+ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x50, 0x10, 5, 1),
+ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x50, 0x10, 4, 1),
+ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x50, 0x10, 3, 1),
+ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x50, 0x10, 2, 1),
+ PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x50, 0x10, 15, 1),
+ PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x50, 0x10, 12, 1),
+ PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x50, 0x10, 13, 1),
+ PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x50, 0x10, 14, 1),
+ PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x50, 0x10, 16, 1),
+
+ PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x40, 0x10, 14, 1),
+ PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x40, 0x10, 15, 1),
+ PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x40, 0x10, 13, 1),
+ PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x40, 0x10, 4, 1),
+ PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x40, 0x10, 5, 1),
+ PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x40, 0x10, 6, 1),
+ PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x40, 0x10, 3, 1),
+ PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x40, 0x10, 7, 1),
+ PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x40, 0x10, 20, 1),
+ PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x40, 0x10, 8, 1),
+ PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x40, 0x10, 9, 1),
+ PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x40, 0x10, 10, 1),
+ PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x40, 0x10, 11, 1),
+ PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x40, 0x10, 12, 1),
+
+ PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
+ PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0x30, 0x10, 5, 1),
+ PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0x30, 0x10, 6, 1),
+
+ PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x30, 0x10, 10, 1),
+ PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x30, 0x10, 1, 1),
+ PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x30, 0x10, 11, 1),
+ PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x30, 0x10, 9, 1),
+ PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x30, 0x10, 2, 1),
+ PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x30, 0x10, 0, 1),
+ PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x30, 0x10, 12, 1),
+
+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x40, 0x10, 18, 1),
+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x40, 0x10, 19, 1),
+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x40, 0x10, 16, 1),
+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x40, 0x10, 17, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
+ PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0xc0, 0x10, 13, 1),
+ PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0xc0, 0x10, 14, 1),
+ PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0xc0, 0x10, 11, 1),
+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0xc0, 0x10, 12, 1),
+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0xc0, 0x10, 0, 1),
+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0xc0, 0x10, 9, 1),
+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0xc0, 0x10, 10, 1),
+
+ PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0xb0, 0x10, 8, 1),
+ PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0xb0, 0x10, 6, 1),
+ PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0xb0, 0x10, 5, 1),
+ PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0xb0, 0x10, 3, 1),
+
+ PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0xe0, 0x10, 0, 1),
+ PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0xe0, 0x10, 21, 1),
+ PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0xe0, 0x10, 1, 1),
+ PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0xe0, 0x10, 2, 1),
+
+ PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0xc0, 0x10, 7, 1),
+ PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0xc0, 0x10, 8, 1),
+ PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0xc0, 0x10, 3, 1),
+ PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0xc0, 0x10, 4, 1),
+
+ PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0xb0, 0x10, 7, 1),
+ PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0xb0, 0x10, 4, 1),
+
+ PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x140, 0x10, 17, 1),
+ PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x140, 0x10, 23, 1),
+ PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x140, 0x10, 20, 1),
+ PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x140, 0x10, 19, 1),
+ PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x140, 0x10, 21, 1),
+ PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x140, 0x10, 22, 1),
+ PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x140, 0x10, 18, 1),
+ PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x140, 0x10, 25, 1),
+ PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x140, 0x10, 26, 1),
+ PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x140, 0x10, 27, 1),
+ PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x140, 0x10, 24, 1),
+ PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x140, 0x10, 28, 1),
+ PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x150, 0x10, 0, 1),
+ PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x140, 0x10, 31, 1),
+ PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x140, 0x10, 29, 1),
+ PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x140, 0x10, 30, 1),
+ PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x150, 0x10, 1, 1),
+ PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x140, 0x10, 11, 1),
+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x140, 0x10, 10, 1),
+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x140, 0x10, 0, 1),
+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x140, 0x10, 1, 1),
+ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x140, 0x10, 9, 1),
+ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x140, 0x10, 8, 1),
+ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x140, 0x10, 7, 1),
+ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x140, 0x10, 6, 1),
+ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x140, 0x10, 5, 1),
+ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x140, 0x10, 4, 1),
+ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x140, 0x10, 3, 1),
+ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x140, 0x10, 2, 1),
+ PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x140, 0x10, 15, 1),
+ PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x140, 0x10, 12, 1),
+ PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x140, 0x10, 13, 1),
+ PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x140, 0x10, 14, 1),
+ PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x140, 0x10, 16, 1),
+
+ PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0xe0, 0x10, 14, 1),
+ PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0xe0, 0x10, 15, 1),
+ PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0xe0, 0x10, 13, 1),
+ PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0xe0, 0x10, 4, 1),
+ PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0xe0, 0x10, 5, 1),
+ PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0xe0, 0x10, 6, 1),
+ PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0xe0, 0x10, 3, 1),
+ PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0xe0, 0x10, 7, 1),
+ PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0xe0, 0x10, 20, 1),
+ PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0xe0, 0x10, 8, 1),
+ PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0xe0, 0x10, 9, 1),
+ PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0xe0, 0x10, 10, 1),
+ PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0xe0, 0x10, 11, 1),
+ PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0xe0, 0x10, 12, 1),
+
+ PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0xc0, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0xc0, 0x10, 2, 1),
+ PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0xc0, 0x10, 5, 1),
+ PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0xc0, 0x10, 6, 1),
+
+ PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0xb0, 0x10, 10, 1),
+ PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0xb0, 0x10, 1, 1),
+ PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0xb0, 0x10, 11, 1),
+ PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0xb0, 0x10, 9, 1),
+ PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0xb0, 0x10, 2, 1),
+ PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0xb0, 0x10, 0, 1),
+ PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0xb0, 0x10, 12, 1),
+
+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0xe0, 0x10, 18, 1),
+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0xe0, 0x10, 19, 1),
+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0xe0, 0x10, 16, 1),
+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0xe0, 0x10, 17, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
+ PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x60, 0x10, 5, 1),
+ PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x60, 0x10, 4, 1),
+ PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x60, 0x10, 3, 1),
+ PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
+
+ PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x70, 0x10, 0, 1),
+ PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x70, 0x10, 1, 1),
+ PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x70, 0x10, 2, 1),
+
+ PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x60, 0x10, 7, 1),
+ PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x60, 0x10, 6, 1),
+ PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x60, 0x10, 1, 1),
+ PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
+ PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x60, 0x10, 8, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
+ PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x40, 0x10, 5, 1),
+ PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x40, 0x10, 4, 1),
+ PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x40, 0x10, 3, 1),
+ PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
+
+ PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x50, 0x10, 0, 1),
+ PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x50, 0x10, 1, 1),
+
+ PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
+ PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0x40, 0x10, 5, 1),
+ PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
+ PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
+
+ PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x50, 0x10, 2, 1),
+ PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
+ PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0x40, 0x10, 3, 1),
+
+ PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x40, 0x10, 7, 1),
+ PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x40, 0x10, 6, 1),
+ PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x40, 0x10, 1, 1),
+ PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
+ PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x40, 0x10, 8, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
+ PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x00, 0x10, 21, 3),
+ PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x00, 0x10, 24, 3),
+ PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x00, 0x10, 15, 3),
+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x00, 0x10, 18, 3),
+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x00, 0x10, 9, 3),
+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x00, 0x10, 12, 3),
+
+ PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x00, 0x10, 24, 3),
+ PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x00, 0x10, 28, 3),
+ PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x00, 0x10, 15, 3),
+ PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x00, 0x10, 9, 3),
+
+ PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x20, 0x10, 3, 3),
+ PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x00, 0x10, 3, 3),
+ PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x00, 0x10, 6, 3),
+
+ PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x00, 0x10, 21, 3),
+ PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x00, 0x10, 12, 3),
+
+ PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x10, 0x10, 21, 3),
+ PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x20, 0x10, 9, 3),
+ PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x20, 0x10, 0, 3),
+ PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x10, 0x10, 27, 3),
+ PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x20, 0x10, 3, 3),
+ PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x20, 0x10, 6, 3),
+ PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x10, 0x10, 24, 3),
+ PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x20, 0x10, 15, 3),
+ PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x20, 0x10, 18, 3),
+ PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x20, 0x10, 21, 3),
+ PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x20, 0x10, 12, 3),
+ PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x20, 0x10, 24, 3),
+ PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x30, 0x10, 6, 3),
+ PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x30, 0x10, 3, 3),
+ PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x20, 0x10, 27, 3),
+ PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x30, 0x10, 0, 3),
+ PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x30, 0x10, 9, 3),
+ PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x10, 0x10, 3, 3),
+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 0, 3),
+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x00, 0x10, 3, 3),
+ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x00, 0x10, 27, 3),
+ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x00, 0x10, 24, 3),
+ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x00, 0x10, 21, 3),
+ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x00, 0x10, 18, 3),
+ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x00, 0x10, 15, 3),
+ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x00, 0x10, 12, 3),
+ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x00, 0x10, 9, 3),
+ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x00, 0x10, 6, 3),
+ PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x10, 0x10, 15, 3),
+ PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x10, 0x10, 6, 3),
+ PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x10, 0x10, 9, 3),
+ PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x10, 0x10, 12, 3),
+ PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x10, 0x10, 18, 3),
+
+ PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x10, 0x10, 12, 3),
+ PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x10, 0x10, 15, 3),
+ PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x10, 0x10, 9, 3),
+ PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x00, 0x10, 12, 3),
+ PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x00, 0x10, 15, 3),
+ PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x00, 0x10, 18, 3),
+ PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x00, 0x10, 9, 3),
+ PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x00, 0x10, 21, 3),
+ PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x20, 0x10, 0, 3),
+ PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x00, 0x10, 24, 3),
+ PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x00, 0x10, 27, 3),
+ PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x10, 0x10, 0, 3),
+ PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x10, 0x10, 3, 3),
+ PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x10, 0x10, 6, 3),
+
+ PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x00, 0x10, 3, 3),
+ PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x00, 0x10, 6, 3),
+
+ PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x10, 0x10, 0, 3),
+ PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x00, 0x10, 3, 3),
+ PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x10, 0x10, 3, 3),
+ PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x00, 0x10, 27, 3),
+ PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x00, 0x10, 6, 3),
+ PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x10, 0x10, 6, 3),
+
+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x10, 0x10, 24, 3),
+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x10, 0x10, 27, 3),
+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x10, 0x10, 18, 3),
+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x10, 0x10, 21, 3),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
+ PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x50, 0x10, 7, 1),
+ PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
+ PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x50, 0x10, 5, 1),
+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x50, 0x10, 6, 1),
+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x50, 0x10, 3, 1),
+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
+
+ PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x60, 0x10, 0, 1),
+ PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x60, 0x10, 18, 1),
+
+ PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x50, 0x10, 2, 1),
+ PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x50, 0x10, 1, 1),
+
+ PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x70, 0x10, 17, 1),
+ PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x70, 0x10, 23, 1),
+ PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x70, 0x10, 20, 1),
+ PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x70, 0x10, 19, 1),
+ PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x70, 0x10, 21, 1),
+ PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x70, 0x10, 22, 1),
+ PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x70, 0x10, 18, 1),
+ PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x70, 0x10, 25, 1),
+ PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x70, 0x10, 26, 1),
+ PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x70, 0x10, 27, 1),
+ PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x70, 0x10, 24, 1),
+ PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x70, 0x10, 28, 1),
+ PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x80, 0x10, 0, 1),
+ PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x70, 0x10, 31, 1),
+ PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x70, 0x10, 29, 1),
+ PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x70, 0x10, 30, 1),
+ PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x80, 0x10, 1, 1),
+ PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x70, 0x10, 11, 1),
+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x70, 0x10, 10, 1),
+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 1, 1),
+ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x70, 0x10, 9, 1),
+ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x70, 0x10, 8, 1),
+ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x70, 0x10, 7, 1),
+ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x70, 0x10, 6, 1),
+ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x70, 0x10, 5, 1),
+ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x70, 0x10, 4, 1),
+ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x70, 0x10, 3, 1),
+ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
+ PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x70, 0x10, 15, 1),
+ PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x70, 0x10, 12, 1),
+ PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x70, 0x10, 13, 1),
+ PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x70, 0x10, 14, 1),
+ PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x70, 0x10, 16, 1),
+
+ PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x60, 0x10, 12, 1),
+ PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x60, 0x10, 13, 1),
+ PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x60, 0x10, 11, 1),
+ PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x60, 0x10, 2, 1),
+ PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x60, 0x10, 3, 1),
+ PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x60, 0x10, 4, 1),
+ PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x60, 0x10, 1, 1),
+ PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x60, 0x10, 5, 1),
+ PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x60, 0x10, 6, 1),
+ PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x60, 0x10, 7, 1),
+ PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x60, 0x10, 8, 1),
+ PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x60, 0x10, 9, 1),
+ PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x60, 0x10, 10, 1),
+
+ PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
+
+ PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x50, 0x10, 3, 1),
+ PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x50, 0x10, 0, 1),
+
+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x60, 0x10, 16, 1),
+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x60, 0x10, 17, 1),
+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x60, 0x10, 14, 1),
+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x60, 0x10, 15, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
+ PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x60, 0x10, 7, 1),
+ PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x60, 0x10, 8, 1),
+ PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x60, 0x10, 5, 1),
+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x60, 0x10, 6, 1),
+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x60, 0x10, 0, 1),
+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x60, 0x10, 3, 1),
+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x60, 0x10, 4, 1),
+
+ PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x80, 0x10, 0, 1),
+ PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x80, 0x10, 18, 1),
+
+ PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x70, 0x10, 2, 1),
+ PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x70, 0x10, 1, 1),
+
+ PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x90, 0x10, 17, 1),
+ PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x90, 0x10, 23, 1),
+ PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x90, 0x10, 20, 1),
+ PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x90, 0x10, 19, 1),
+ PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x90, 0x10, 21, 1),
+ PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x90, 0x10, 22, 1),
+ PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x90, 0x10, 18, 1),
+ PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x90, 0x10, 25, 1),
+ PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x90, 0x10, 26, 1),
+ PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x90, 0x10, 27, 1),
+ PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x90, 0x10, 24, 1),
+ PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x90, 0x10, 28, 1),
+ PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0xa0, 0x10, 0, 1),
+ PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x90, 0x10, 31, 1),
+ PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x90, 0x10, 29, 1),
+ PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x90, 0x10, 30, 1),
+ PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0xa0, 0x10, 1, 1),
+ PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x90, 0x10, 11, 1),
+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x90, 0x10, 10, 1),
+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x90, 0x10, 0, 1),
+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x90, 0x10, 1, 1),
+ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x90, 0x10, 9, 1),
+ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x90, 0x10, 8, 1),
+ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x90, 0x10, 7, 1),
+ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x90, 0x10, 6, 1),
+ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x90, 0x10, 5, 1),
+ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x90, 0x10, 4, 1),
+ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x90, 0x10, 3, 1),
+ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x90, 0x10, 2, 1),
+ PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x90, 0x10, 15, 1),
+ PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x90, 0x10, 12, 1),
+ PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x90, 0x10, 13, 1),
+ PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x90, 0x10, 14, 1),
+ PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x90, 0x10, 16, 1),
+
+ PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x80, 0x10, 12, 1),
+ PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x80, 0x10, 13, 1),
+ PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x80, 0x10, 11, 1),
+ PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x80, 0x10, 2, 1),
+ PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x80, 0x10, 3, 1),
+ PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x80, 0x10, 4, 1),
+ PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x80, 0x10, 1, 1),
+ PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x80, 0x10, 5, 1),
+ PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x80, 0x10, 6, 1),
+ PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x80, 0x10, 7, 1),
+ PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x80, 0x10, 8, 1),
+ PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x80, 0x10, 9, 1),
+ PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x80, 0x10, 10, 1),
+
+ PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x60, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x60, 0x10, 2, 1),
+
+ PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x70, 0x10, 3, 1),
+ PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x70, 0x10, 0, 1),
+
+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x80, 0x10, 16, 1),
+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x80, 0x10, 17, 1),
+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x80, 0x10, 14, 1),
+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x80, 0x10, 15, 1),
+};
+
+static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
+ PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x70, 0x10, 7, 1),
+ PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x70, 0x10, 8, 1),
+ PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x70, 0x10, 5, 1),
+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x70, 0x10, 6, 1),
+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x70, 0x10, 0, 1),
+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x70, 0x10, 3, 1),
+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x70, 0x10, 4, 1),
+
+ PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x90, 0x10, 0, 1),
+ PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x90, 0x10, 18, 1),
+
+ PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x80, 0x10, 2, 1),
+ PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x80, 0x10, 1, 1),
+
+ PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0xb0, 0x10, 17, 1),
+ PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0xb0, 0x10, 23, 1),
+ PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0xb0, 0x10, 20, 1),
+ PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0xb0, 0x10, 19, 1),
+ PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0xb0, 0x10, 21, 1),
+ PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0xb0, 0x10, 22, 1),
+ PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0xb0, 0x10, 18, 1),
+ PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0xb0, 0x10, 25, 1),
+ PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0xb0, 0x10, 26, 1),
+ PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0xb0, 0x10, 27, 1),
+ PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0xb0, 0x10, 24, 1),
+ PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0xb0, 0x10, 28, 1),
+ PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0xc0, 0x10, 0, 1),
+ PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0xb0, 0x10, 31, 1),
+ PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0xb0, 0x10, 29, 1),
+ PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0xb0, 0x10, 30, 1),
+ PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0xc0, 0x10, 1, 1),
+ PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0xb0, 0x10, 11, 1),
+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0xb0, 0x10, 10, 1),
+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0xb0, 0x10, 0, 1),
+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xb0, 0x10, 1, 1),
+ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0xb0, 0x10, 9, 1),
+ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0xb0, 0x10, 8, 1),
+ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0xb0, 0x10, 7, 1),
+ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0xb0, 0x10, 6, 1),
+ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0xb0, 0x10, 5, 1),
+ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0xb0, 0x10, 4, 1),
+ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0xb0, 0x10, 3, 1),
+ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0xb0, 0x10, 2, 1),
+ PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0xb0, 0x10, 15, 1),
+ PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0xb0, 0x10, 12, 1),
+ PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0xb0, 0x10, 13, 1),
+ PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0xb0, 0x10, 14, 1),
+ PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0xb0, 0x10, 16, 1),
+
+ PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x90, 0x10, 12, 1),
+ PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x90, 0x10, 13, 1),
+ PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x90, 0x10, 11, 1),
+ PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x90, 0x10, 2, 1),
+ PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x90, 0x10, 3, 1),
+ PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x90, 0x10, 4, 1),
+ PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x90, 0x10, 1, 1),
+ PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x90, 0x10, 5, 1),
+ PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x90, 0x10, 6, 1),
+ PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x90, 0x10, 7, 1),
+ PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x90, 0x10, 8, 1),
+ PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x90, 0x10, 9, 1),
+ PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x90, 0x10, 10, 1),
+
+ PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x70, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x70, 0x10, 2, 1),
+
+ PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x80, 0x10, 3, 1),
+ PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x80, 0x10, 0, 1),
+
+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x90, 0x10, 16, 1),
+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x90, 0x10, 17, 1),
+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x90, 0x10, 14, 1),
+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x90, 0x10, 15, 1),
+};
+
+static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range),
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range),
+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range),
+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range),
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range),
+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range),
+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range),
+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range),
+};
+
+static const struct mtk_pin_desc mt7988_pins[] = {
+ MT7988_TYPE0_PIN(0, "UART2_RXD"),
+ MT7988_TYPE0_PIN(1, "UART2_TXD"),
+ MT7988_TYPE0_PIN(2, "UART2_CTS"),
+ MT7988_TYPE0_PIN(3, "UART2_RTS"),
+ MT7988_TYPE0_PIN(4, "GPIO_A"),
+ MT7988_TYPE0_PIN(5, "SMI_0_MDC"),
+ MT7988_TYPE0_PIN(6, "SMI_0_MDIO"),
+ MT7988_TYPE1_PIN(7, "PCIE30_2L_0_WAKE_N"),
+ MT7988_TYPE1_PIN(8, "PCIE30_2L_0_CLKREQ_N"),
+ MT7988_TYPE1_PIN(9, "PCIE30_1L_1_WAKE_N"),
+ MT7988_TYPE1_PIN(10, "PCIE30_1L_1_CLKREQ_N"),
+ MT7988_TYPE0_PIN(11, "GPIO_P"),
+ MT7988_TYPE0_PIN(12, "WATCHDOG"),
+ MT7988_TYPE1_PIN(13, "GPIO_RESET"),
+ MT7988_TYPE1_PIN(14, "GPIO_WPS"),
+ MT7988_TYPE2_PIN(15, "PMIC_I2C_SCL"),
+ MT7988_TYPE2_PIN(16, "PMIC_I2C_SDA"),
+ MT7988_TYPE2_PIN(17, "I2C_1_SCL"),
+ MT7988_TYPE2_PIN(18, "I2C_1_SDA"),
+ MT7988_TYPE0_PIN(19, "PCIE30_2L_0_PRESET_N"),
+ MT7988_TYPE0_PIN(20, "PCIE30_1L_1_PRESET_N"),
+ MT7988_TYPE0_PIN(21, "PWMD1"),
+ MT7988_TYPE0_PIN(22, "SPI0_WP"),
+ MT7988_TYPE0_PIN(23, "SPI0_HOLD"),
+ MT7988_TYPE0_PIN(24, "SPI0_CSB"),
+ MT7988_TYPE0_PIN(25, "SPI0_MISO"),
+ MT7988_TYPE0_PIN(26, "SPI0_MOSI"),
+ MT7988_TYPE0_PIN(27, "SPI0_CLK"),
+ MT7988_TYPE0_PIN(28, "SPI1_CSB"),
+ MT7988_TYPE0_PIN(29, "SPI1_MISO"),
+ MT7988_TYPE0_PIN(30, "SPI1_MOSI"),
+ MT7988_TYPE0_PIN(31, "SPI1_CLK"),
+ MT7988_TYPE0_PIN(32, "SPI2_CLK"),
+ MT7988_TYPE0_PIN(33, "SPI2_MOSI"),
+ MT7988_TYPE0_PIN(34, "SPI2_MISO"),
+ MT7988_TYPE0_PIN(35, "SPI2_CSB"),
+ MT7988_TYPE0_PIN(36, "SPI2_HOLD"),
+ MT7988_TYPE0_PIN(37, "SPI2_WP"),
+ MT7988_TYPE0_PIN(38, "EMMC_RSTB"),
+ MT7988_TYPE0_PIN(39, "EMMC_DSL"),
+ MT7988_TYPE0_PIN(40, "EMMC_CK"),
+ MT7988_TYPE0_PIN(41, "EMMC_CMD"),
+ MT7988_TYPE0_PIN(42, "EMMC_DATA_7"),
+ MT7988_TYPE0_PIN(43, "EMMC_DATA_6"),
+ MT7988_TYPE0_PIN(44, "EMMC_DATA_5"),
+ MT7988_TYPE0_PIN(45, "EMMC_DATA_4"),
+ MT7988_TYPE0_PIN(46, "EMMC_DATA_3"),
+ MT7988_TYPE0_PIN(47, "EMMC_DATA_2"),
+ MT7988_TYPE0_PIN(48, "EMMC_DATA_1"),
+ MT7988_TYPE0_PIN(49, "EMMC_DATA_0"),
+ MT7988_TYPE0_PIN(50, "PCM_FS_I2S_LRCK"),
+ MT7988_TYPE0_PIN(51, "PCM_CLK_I2S_BCLK"),
+ MT7988_TYPE0_PIN(52, "PCM_DRX_I2S_DIN"),
+ MT7988_TYPE0_PIN(53, "PCM_DTX_I2S_DOUT"),
+ MT7988_TYPE0_PIN(54, "PCM_MCK_I2S_MCLK"),
+ MT7988_TYPE0_PIN(55, "UART0_RXD"),
+ MT7988_TYPE0_PIN(56, "UART0_TXD"),
+ MT7988_TYPE0_PIN(57, "PWMD0"),
+ MT7988_TYPE0_PIN(58, "JTAG_JTDI"),
+ MT7988_TYPE0_PIN(59, "JTAG_JTDO"),
+ MT7988_TYPE0_PIN(60, "JTAG_JTMS"),
+ MT7988_TYPE0_PIN(61, "JTAG_JTCLK"),
+ MT7988_TYPE0_PIN(62, "JTAG_JTRST_N"),
+ MT7988_TYPE1_PIN(63, "USB_DRV_VBUS_P1"),
+ MT7988_TYPE0_PIN(64, "LED_A"),
+ MT7988_TYPE0_PIN(65, "LED_B"),
+ MT7988_TYPE0_PIN(66, "LED_C"),
+ MT7988_TYPE0_PIN(67, "LED_D"),
+ MT7988_TYPE0_PIN(68, "LED_E"),
+ MT7988_TYPE0_PIN(69, "GPIO_B"),
+ MT7988_TYPE0_PIN(70, "GPIO_C"),
+ MT7988_TYPE2_PIN(71, "I2C_2_SCL"),
+ MT7988_TYPE2_PIN(72, "I2C_2_SDA"),
+ MT7988_TYPE0_PIN(73, "PCIE30_2L_1_PRESET_N"),
+ MT7988_TYPE0_PIN(74, "PCIE30_1L_0_PRESET_N"),
+ MT7988_TYPE1_PIN(75, "PCIE30_2L_1_WAKE_N"),
+ MT7988_TYPE1_PIN(76, "PCIE30_2L_1_CLKREQ_N"),
+ MT7988_TYPE1_PIN(77, "PCIE30_1L_0_WAKE_N"),
+ MT7988_TYPE1_PIN(78, "PCIE30_1L_0_CLKREQ_N"),
+ MT7988_TYPE1_PIN(79, "USB_DRV_VBUS_P0"),
+ MT7988_TYPE0_PIN(80, "UART1_RXD"),
+ MT7988_TYPE0_PIN(81, "UART1_TXD"),
+ MT7988_TYPE0_PIN(82, "UART1_CTS"),
+ MT7988_TYPE0_PIN(83, "UART1_RTS"),
+};
+
+/* jtag */
+static const int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 };
+static const int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 };
+
+static const int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 };
+static const int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 };
+
+static const int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 };
+static const int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 };
+
+static const int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 };
+static const int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 };
+
+static const int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 };
+static const int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 };
+
+static const int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 };
+static const int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 };
+
+/* int_usxgmii */
+static const int mt7988_int_usxgmii_pins[] = { 2, 3 };
+static const int mt7988_int_usxgmii_funcs[] = { 3, 3 };
+
+/* pwm */
+static const int mt7988_pwm0_pins[] = { 57 };
+static const int mt7988_pwm0_funcs[] = { 1 };
+
+static const int mt7988_pwm1_pins[] = { 21 };
+static const int mt7988_pwm1_funcs[] = { 1 };
+
+static const int mt7988_pwm2_pins[] = { 80 };
+static const int mt7988_pwm2_funcs[] = { 2 };
+
+static const int mt7988_pwm3_pins[] = { 81 };
+static const int mt7988_pwm3_funcs[] = { 2 };
+
+static const int mt7988_pwm4_pins[] = { 82 };
+static const int mt7988_pwm4_funcs[] = { 2 };
+
+static const int mt7988_pwm5_pins[] = { 83 };
+static const int mt7988_pwm5_funcs[] = { 2 };
+
+static const int mt7988_pwm6_pins[] = { 69 };
+static const int mt7988_pwm6_funcs[] = { 3 };
+
+static const int mt7988_pwm7_pins[] = { 70 };
+static const int mt7988_pwm7_funcs[] = { 3 };
+
+/* dfd */
+static const int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 };
+static const int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 };
+
+/* i2c */
+static const int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 };
+static const int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 };
+
+static const int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 };
+static const int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 };
+
+static const int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 };
+static const int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 };
+
+static const int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 };
+static const int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 };
+
+static const int mt7988_i2c0_0_pins[] = { 5, 6 };
+static const int mt7988_i2c0_0_funcs[] = { 2, 2 };
+
+static const int mt7988_i2c1_sfp_pins[] = { 5, 6 };
+static const int mt7988_i2c1_sfp_funcs[] = { 4, 4 };
+
+static const int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 };
+static const int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 };
+
+static const int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 };
+static const int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 };
+
+static const int mt7988_i2c0_1_pins[] = { 15, 16 };
+static const int mt7988_i2c0_1_funcs[] = { 1, 1 };
+
+static const int mt7988_u30_phy_i2c0_pins[] = { 15, 16 };
+static const int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 };
+
+static const int mt7988_u32_phy_i2c0_pins[] = { 15, 16 };
+static const int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 };
+
+static const int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 };
+static const int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 };
+
+static const int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 };
+static const int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 };
+
+static const int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 };
+static const int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 };
+
+static const int mt7988_i2c1_0_pins[] = { 17, 18 };
+static const int mt7988_i2c1_0_funcs[] = { 1, 1 };
+
+static const int mt7988_u30_phy_i2c1_pins[] = { 17, 18 };
+static const int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 };
+
+static const int mt7988_u32_phy_i2c1_pins[] = { 17, 18 };
+static const int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 };
+
+static const int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 };
+static const int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 };
+
+static const int mt7988_sgmii0_i2c_pins[] = { 17, 18 };
+static const int mt7988_sgmii0_i2c_funcs[] = { 5, 5 };
+
+static const int mt7988_sgmii1_i2c_pins[] = { 17, 18 };
+static const int mt7988_sgmii1_i2c_funcs[] = { 6, 6 };
+
+static const int mt7988_i2c1_2_pins[] = { 69, 70 };
+static const int mt7988_i2c1_2_funcs[] = { 2, 2 };
+
+static const int mt7988_i2c2_0_pins[] = { 69, 70 };
+static const int mt7988_i2c2_0_funcs[] = { 4, 4 };
+
+static const int mt7988_i2c2_1_pins[] = { 71, 72 };
+static const int mt7988_i2c2_1_funcs[] = { 1, 1 };
+
+/* eth */
+static const int mt7988_mdc_mdio0_pins[] = { 5, 6 };
+static const int mt7988_mdc_mdio0_funcs[] = { 1, 1 };
+
+static const int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 };
+static const int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 };
+
+static const int mt7988_gbe_ext_mdio_pins[] = { 30, 31 };
+static const int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 };
+
+static const int mt7988_mdc_mdio1_pins[] = { 69, 70 };
+static const int mt7988_mdc_mdio1_funcs[] = { 1, 1 };
+
+/* pcie */
+static const int mt7988_pcie_wake_n0_0_pins[] = { 7 };
+static const int mt7988_pcie_wake_n0_0_funcs[] = { 1 };
+
+static const int mt7988_pcie_clk_req_n0_0_pins[] = { 8 };
+static const int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 };
+
+static const int mt7988_pcie_wake_n3_0_pins[] = { 9 };
+static const int mt7988_pcie_wake_n3_0_funcs[] = { 1 };
+
+static const int mt7988_pcie_clk_req_n3_pins[] = { 10 };
+static const int mt7988_pcie_clk_req_n3_funcs[] = { 1 };
+
+static const int mt7988_pcie_clk_req_n0_1_pins[] = { 10 };
+static const int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 };
+
+static const int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 };
+static const int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 };
+
+static const int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 };
+static const int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 };
+
+static const int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 };
+static const int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 };
+
+static const int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 };
+static const int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 };
+
+static const int mt7988_ckm_phy_i2c_pins[] = { 9, 10 };
+static const int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 };
+
+static const int mt7988_pcie_wake_n0_1_pins[] = { 13 };
+static const int mt7988_pcie_wake_n0_1_funcs[] = { 2 };
+
+static const int mt7988_pcie_wake_n3_1_pins[] = { 14 };
+static const int mt7988_pcie_wake_n3_1_funcs[] = { 2 };
+
+static const int mt7988_pcie_2l_0_pereset_pins[] = { 19 };
+static const int mt7988_pcie_2l_0_pereset_funcs[] = { 1 };
+
+static const int mt7988_pcie_1l_1_pereset_pins[] = { 20 };
+static const int mt7988_pcie_1l_1_pereset_funcs[] = { 1 };
+
+static const int mt7988_pcie_clk_req_n2_1_pins[] = { 63 };
+static const int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 };
+
+static const int mt7988_pcie_2l_1_pereset_pins[] = { 73 };
+static const int mt7988_pcie_2l_1_pereset_funcs[] = { 1 };
+
+static const int mt7988_pcie_1l_0_pereset_pins[] = { 74 };
+static const int mt7988_pcie_1l_0_pereset_funcs[] = { 1 };
+
+static const int mt7988_pcie_wake_n1_0_pins[] = { 75 };
+static const int mt7988_pcie_wake_n1_0_funcs[] = { 1 };
+
+static const int mt7988_pcie_clk_req_n1_pins[] = { 76 };
+static const int mt7988_pcie_clk_req_n1_funcs[] = { 1 };
+
+static const int mt7988_pcie_wake_n2_0_pins[] = { 77 };
+static const int mt7988_pcie_wake_n2_0_funcs[] = { 1 };
+
+static const int mt7988_pcie_clk_req_n2_0_pins[] = { 78 };
+static const int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 };
+
+static const int mt7988_pcie_wake_n2_1_pins[] = { 79 };
+static const int mt7988_pcie_wake_n2_1_funcs[] = { 2 };
+
+/* pmic */
+static const int mt7988_pmic_pins[] = { 11 };
+static const int mt7988_pmic_funcs[] = { 1 };
+
+/* watchdog */
+static const int mt7988_watchdog_pins[] = { 12 };
+static const int mt7988_watchdog_funcs[] = { 1 };
+
+/* spi */
+static const int mt7988_spi0_wp_hold_pins[] = { 22, 23 };
+static const int mt7988_spi0_wp_hold_funcs[] = { 1, 1 };
+
+static const int mt7988_spi0_pins[] = { 24, 25, 26, 27 };
+static const int mt7988_spi0_funcs[] = { 1, 1, 1, 1 };
+
+static const int mt7988_spi1_pins[] = { 28, 29, 30, 31 };
+static const int mt7988_spi1_funcs[] = { 1, 1, 1, 1 };
+
+static const int mt7988_spi2_pins[] = { 32, 33, 34, 35 };
+static const int mt7988_spi2_funcs[] = { 1, 1, 1, 1 };
+
+static const int mt7988_spi2_wp_hold_pins[] = { 36, 37 };
+static const int mt7988_spi2_wp_hold_funcs[] = { 1, 1 };
+
+/* flash */
+static const int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 };
+static const int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
+
+static const int mt7988_emmc_45_pins[] = {
+ 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 };
+static const int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 };
+
+static const int mt7988_emmc_51_pins[] = {
+ 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49 };
+static const int mt7988_emmc_51_funcs[] = {
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
+
+/* uart */
+static const int mt7988_uart2_pins[] = { 0, 1, 2, 3 };
+static const int mt7988_uart2_funcs[] = { 1, 1, 1, 1 };
+
+static const int mt7988_tops_uart0_0_pins[] = { 22, 23 };
+static const int mt7988_tops_uart0_0_funcs[] = { 3, 3 };
+
+static const int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 };
+static const int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 };
+
+static const int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 };
+static const int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 };
+
+static const int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 };
+static const int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 };
+
+static const int mt7988_net_wo0_uart_txd_0_pins[] = { 28 };
+static const int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 };
+
+static const int mt7988_net_wo1_uart_txd_0_pins[] = { 29 };
+static const int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 };
+
+static const int mt7988_net_wo2_uart_txd_0_pins[] = { 30 };
+static const int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 };
+
+static const int mt7988_tops_uart1_0_pins[] = { 28, 29 };
+static const int mt7988_tops_uart1_0_funcs[] = { 4, 4 };
+
+static const int mt7988_tops_uart0_1_pins[] = { 30, 31 };
+static const int mt7988_tops_uart0_1_funcs[] = { 4, 4 };
+
+static const int mt7988_tops_uart1_1_pins[] = { 36, 37 };
+static const int mt7988_tops_uart1_1_funcs[] = { 3, 3 };
+
+static const int mt7988_uart0_pins[] = { 55, 56 };
+static const int mt7988_uart0_funcs[] = { 1, 1 };
+
+static const int mt7988_tops_uart0_2_pins[] = { 55, 56 };
+static const int mt7988_tops_uart0_2_funcs[] = { 2, 2 };
+
+static const int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 };
+static const int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 };
+
+static const int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 };
+static const int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 };
+
+static const int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 };
+static const int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 };
+
+static const int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 };
+static const int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 };
+
+static const int mt7988_tops_uart1_2_pins[] = { 80, 81 };
+static const int mt7988_tops_uart1_2_funcs[] = { 4, 4, };
+
+static const int mt7988_net_wo0_uart_txd_1_pins[] = { 80 };
+static const int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 };
+
+static const int mt7988_net_wo1_uart_txd_1_pins[] = { 81 };
+static const int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 };
+
+static const int mt7988_net_wo2_uart_txd_1_pins[] = { 82 };
+static const int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 };
+
+/* udi */
+static const int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 };
+static const int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 };
+
+/* pcm */
+static const int mt7988_pcm_pins[] = { 50, 51, 52, 53, 54 };
+static const int mt7988_pcm_funcs[] = { 1, 1, 1, 1, 1 };
+
+/* led */
+static const int mt7988_gbe_led1_pins[] = { 58, 59, 60, 61 };
+static const int mt7988_gbe_led1_funcs[] = { 6, 6, 6, 6 };
+
+static const int mt7988_2p5gbe_led1_pins[] = { 62 };
+static const int mt7988_2p5gbe_led1_funcs[] = { 6 };
+
+static const int mt7988_gbe_led0_pins[] = { 64, 65, 66, 67 };
+static const int mt7988_gbe_led0_funcs[] = { 1, 1, 1, 1 };
+
+static const int mt7988_2p5gbe_led0_pins[] = { 68 };
+static const int mt7988_2p5gbe_led0_funcs[] = { 1 };
+
+/* usb */
+static const int mt7988_drv_vbus_p1_pins[] = { 63 };
+static const int mt7988_drv_vbus_p1_funcs[] = { 1 };
+
+static const int mt7988_drv_vbus_pins[] = { 79 };
+static const int mt7988_drv_vbus_funcs[] = { 1 };
+
+static const struct mtk_group_desc mt7988_groups[] = {
+ PINCTRL_PIN_GROUP("uart2", mt7988_uart2),
+ PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0),
+ PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii),
+ PINCTRL_PIN_GROUP("dfd", mt7988_dfd),
+ PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0),
+ PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0),
+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0),
+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1),
+ PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0),
+ PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp),
+ PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c),
+ PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c),
+ PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0),
+ PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0),
+ PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0),
+ PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0),
+ PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3),
+ PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1),
+ PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c),
+ PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c),
+ PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c),
+ PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c),
+ PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c),
+ PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic),
+ PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog),
+ PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1),
+ PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1),
+ PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1),
+ PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0),
+ PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0),
+ PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1),
+ PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1),
+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2),
+ PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0),
+ PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1),
+ PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1),
+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3),
+ PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c),
+ PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c),
+ PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset),
+ PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset),
+ PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1),
+ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold),
+ PINCTRL_PIN_GROUP("spi0", mt7988_spi0),
+ PINCTRL_PIN_GROUP("spi1", mt7988_spi1),
+ PINCTRL_PIN_GROUP("spi2", mt7988_spi2),
+ PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold),
+ PINCTRL_PIN_GROUP("snfi", mt7988_snfi),
+ PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0),
+ PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0),
+ PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0),
+ PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1),
+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
+ PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
+ PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
+ PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0),
+ PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1),
+ PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1),
+ PINCTRL_PIN_GROUP("udi", mt7988_udi),
+ PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45),
+ PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51),
+ PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio),
+ PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio),
+ PINCTRL_PIN_GROUP("pcm", mt7988_pcm),
+ PINCTRL_PIN_GROUP("uart0", mt7988_uart0),
+ PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2),
+ PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2),
+ PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag),
+ PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag),
+ PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag),
+ PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0),
+ PINCTRL_PIN_GROUP("jtag", mt7988_jtag),
+ PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1),
+ PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3),
+ PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1),
+ PINCTRL_PIN_GROUP("gbe_led1", mt7988_gbe_led1),
+ PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1),
+ PINCTRL_PIN_GROUP("gbe_led0", mt7988_gbe_led0),
+ PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0),
+ PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1),
+ PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1),
+ PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1),
+ PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2),
+ PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6),
+ PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7),
+ PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0),
+ PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1),
+ PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset),
+ PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset),
+ PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0),
+ PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1),
+ PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0),
+ PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0),
+ PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus),
+ PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1),
+ PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2),
+ PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2),
+ PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3),
+ PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4),
+ PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5),
+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
+ PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
+ PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
+ PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2),
+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1),
+ PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1),
+ PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1),
+};
+
+static const struct mtk_io_type_desc mt7988_io_type_desc[] = {
+ [IO_TYPE_GRP0] = {
+ .name = "18OD33",
+ .bias_set = mtk_pinconf_bias_set_pupd_r1_r0,
+ .drive_set = mtk_pinconf_drive_set_v1,
+ .input_enable = mtk_pinconf_input_enable_v1,
+ },
+ [IO_TYPE_GRP1] = {
+ .name = "18A01",
+ .bias_set = mtk_pinconf_bias_set_pu_pd,
+ .drive_set = mtk_pinconf_drive_set_v1,
+ .input_enable = mtk_pinconf_input_enable_v1,
+ },
+ [IO_TYPE_GRP2] = {
+ .name = "I2C",
+ .input_enable = mtk_pinconf_input_enable_v1,
+ },
+};
+
+/* Joint those groups owning the same capability in user point of view which
+ * allows that people tend to use through the device tree.
+ */
+static const char *const mt7988_jtag_groups[] = { "tops_jtag0_0", "wo0_jtag",
+ "wo1_jtag", "wo2_jtag", "jtag", "tops_jtag0_1", };
+static const char *const mt7988_int_usxgmii_groups[] = { "int_usxgmii", };
+static const char *const mt7988_pwm_groups[] = { "pwm0", "pwm1", "pwm2", "pwm3",
+ "pwm4", "pwm5", "pwm6", "pwm7" };
+static const char *const mt7988_dfd_groups[] = { "dfd", };
+static const char *const mt7988_i2c_groups[] = { "xfi_phy0_i2c0",
+ "xfi_phy1_i2c0", "xfi_phy_pll_i2c0", "xfi_phy_pll_i2c1", "i2c0_0",
+ "i2c1_sfp", "xfi_pextp_phy0_i2c", "xfi_pextp_phy1_i2c", "i2c0_1",
+ "u30_phy_i2c0", "u32_phy_i2c0", "xfi_phy0_i2c1", "xfi_phy1_i2c1",
+ "xfi_phy_pll_i2c2", "i2c1_0", "u30_phy_i2c1", "u32_phy_i2c1",
+ "xfi_phy_pll_i2c3", "sgmii0_i2c", "sgmii1_i2c", "i2c1_2", "i2c2_0",
+ "i2c2_1", };
+static const char *const mt7988_ethernet_groups[] = { "mdc_mdio0",
+ "2p5g_ext_mdio", "gbe_ext_mdio", "mdc_mdio1", };
+static const char *const mt7988_pcie_groups[] = { "pcie_wake_n0_0",
+ "pcie_clk_req_n0_0", "pcie_wake_n3_0", "pcie_clk_req_n3",
+ "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", "pcie_p3_phy_i2",
+ "pcie_p2_phy_i2c", "ckm_phy_i2c", "pcie_wake_n0_1", "pcie_wake_n3_1",
+ "pcie_2l_0_pereset", "pcie_1l_1_pereset", "pcie_clk_req_n2_1",
+ "pcie_2l_1_perese", "pcie_1l_0_pereset", "pcie_wake_n1_0",
+ "cie_clk_req_n1", "pcie_wake_n2_0", "pcie_wake_n2_1", };
+static const char *const mt7988_pmic_groups[] = { "pmic", };
+static const char *const mt7988_wdt_groups[] = { "watchdog", };
+static const char *const mt7988_spi_groups[] = { "spi0", "spi0_wp_hold",
+ "spi1", "spi2", "spi2_wp_hold", };
+static const char *const mt7988_flash_groups[] = { "emmc_45", "snfi",
+ "emmc_51" };
+static const char *const mt7988_uart_groups[] = { "uart2", "tops_uart0_0",
+ "uart2_0", "uart1_0", "uart2_1",
+ "net_wo0_uart_txd_0", "net_wo1_uart_txd_0", "net_wo2_uart_txd_0",
+ "tops_uart1_0", "ops_uart0_1", "ops_uart1_1",
+ "uart0", "tops_uart0_2", "uart1_1",
+ "uart2_3", "uart1_2", "tops_uart1_2",
+ "net_wo0_uart_txd_1", "net_wo1_uart_txd_1", "net_wo2_uart_txd_1", };
+static const char *const mt7988_udi_groups[] = { "udi", };
+static const char *const mt7988_pcm_groups[] = { "pcm", };
+static const char *const mt7988_led_groups[] = { "gbe_led1", "2p5gbe_led1",
+ "gbe_led0", "2p5gbe_led0", "wf5g_led0", "wf5g_led1", };
+static const char *const mt7988_usb_groups[] = { "drv_vbus", "drv_vbus_p1", };
+
+static const struct mtk_function_desc mt7988_functions[] = {
+ {"jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups)},
+ {"int_usxgmii", mt7988_int_usxgmii_groups,
+ ARRAY_SIZE(mt7988_int_usxgmii_groups)},
+ {"pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups)},
+ {"dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups)},
+ {"i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups)},
+ {"eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups)},
+ {"pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups)},
+ {"pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups)},
+ {"watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups)},
+ {"spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups)},
+ {"flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups)},
+ {"uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups)},
+ {"udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups)},
+ {"pcm", mt7988_pcm_groups, ARRAY_SIZE(mt7988_pcm_groups)},
+ {"usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups)},
+ {"led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups)},
+};
+
+static const char *const mt7988_pinctrl_register_base_names[] = {
+ "gpio_base", "iocfg_tr_base", "iocfg_br_base", "iocfg_rb_base",
+ "iocfg_lb_base", "iocfg_tl_base",
+};
+
+static const struct mtk_pinctrl_soc mt7988_data = {
+ .name = "mt7988_pinctrl",
+ .reg_cal = mt7988_reg_cals,
+ .pins = mt7988_pins,
+ .npins = ARRAY_SIZE(mt7988_pins),
+ .grps = mt7988_groups,
+ .ngrps = ARRAY_SIZE(mt7988_groups),
+ .funcs = mt7988_functions,
+ .nfuncs = ARRAY_SIZE(mt7988_functions),
+ .io_type = mt7988_io_type_desc,
+ .ntype = ARRAY_SIZE(mt7988_io_type_desc),
+ .gpio_mode = 0,
+ .base_names = mt7988_pinctrl_register_base_names,
+ .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names),
+ .base_calc = 1,
+};
+
+static int mtk_pinctrl_mt7988_probe(struct udevice *dev)
+{
+ return mtk_pinctrl_common_probe(dev, &mt7988_data);
+}
+
+static const struct udevice_id mt7988_pctrl_match[] = {
+ {.compatible = "mediatek,mt7988-pinctrl"},
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mt7988_pinctrl) = {
+ .name = "mt7988_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = mt7988_pctrl_match,
+ .ops = &mtk_pinctrl_ops,
+ .probe = mtk_pinctrl_mt7988_probe,
+ .priv_auto = sizeof(struct mtk_pinctrl_priv),
+};
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8512.c b/drivers/pinctrl/mediatek/pinctrl-mt8512.c
index 3d9c0ab..bc5fb83 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8512.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8512.c
@@ -315,12 +315,12 @@
*/
/* UART */
-static int mt8512_uart0_0_rxd_txd_pins[] = { 52, 53, };
-static int mt8512_uart0_0_rxd_txd_funcs[] = { 1, 1, };
-static int mt8512_uart1_0_rxd_txd_pins[] = { 54, 55, };
-static int mt8512_uart1_0_rxd_txd_funcs[] = { 1, 1, };
-static int mt8512_uart2_0_rxd_txd_pins[] = { 28, 29, };
-static int mt8512_uart2_0_rxd_txd_funcs[] = { 1, 1, };
+static const int mt8512_uart0_0_rxd_txd_pins[] = { 52, 53, };
+static const int mt8512_uart0_0_rxd_txd_funcs[] = { 1, 1, };
+static const int mt8512_uart1_0_rxd_txd_pins[] = { 54, 55, };
+static const int mt8512_uart1_0_rxd_txd_funcs[] = { 1, 1, };
+static const int mt8512_uart2_0_rxd_txd_pins[] = { 28, 29, };
+static const int mt8512_uart2_0_rxd_txd_funcs[] = { 1, 1, };
/* Joint those groups owning the same capability in user point of view which
* allows that people tend to use through the device tree.
@@ -330,13 +330,13 @@
"uart2_0_rxd_txd", };
/* SNAND */
-static int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, };
-static int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
+static const int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, };
+static const int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
/* MMC0 */
-static int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84,
- 85, 86, };
-static int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84,
+ 85, 86, };
+static const int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
static const struct mtk_group_desc mt8512_groups[] = {
PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8512_uart0_0_rxd_txd),
@@ -356,7 +356,7 @@
{"snand", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)},
};
-static struct mtk_pinctrl_soc mt8512_data = {
+static const struct mtk_pinctrl_soc mt8512_data = {
.name = "mt8512_pinctrl",
.reg_cal = mt8512_reg_cals,
.pins = mt8512_pins,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
index 6f94f76..7487d6f 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
@@ -326,12 +326,12 @@
*/
/* UART */
-static int mt8516_uart0_0_rxd_txd_pins[] = { 62, 63, };
-static int mt8516_uart0_0_rxd_txd_funcs[] = { 1, 1, };
-static int mt8516_uart1_0_rxd_txd_pins[] = { 64, 65, };
-static int mt8516_uart1_0_rxd_txd_funcs[] = { 1, 1, };
-static int mt8516_uart2_0_rxd_txd_pins[] = { 34, 35, };
-static int mt8516_uart2_0_rxd_txd_funcs[] = { 1, 1, };
+static const int mt8516_uart0_0_rxd_txd_pins[] = { 62, 63, };
+static const int mt8516_uart0_0_rxd_txd_funcs[] = { 1, 1, };
+static const int mt8516_uart1_0_rxd_txd_pins[] = { 64, 65, };
+static const int mt8516_uart1_0_rxd_txd_funcs[] = { 1, 1, };
+static const int mt8516_uart2_0_rxd_txd_pins[] = { 34, 35, };
+static const int mt8516_uart2_0_rxd_txd_funcs[] = { 1, 1, };
/* Joint those groups owning the same capability in user point of view which
* allows that people tend to use through the device tree.
@@ -341,9 +341,9 @@
"uart2_0_rxd_txd", };
/* MMC0 */
-static int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117, 118,
- 119, 120, };
-static int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117,
+ 118, 119, 120, };
+static const int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
static const struct mtk_group_desc mt8516_groups[] = {
PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8516_uart0_0_rxd_txd),
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8518.c b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
index ed51bd3..66fcfdf 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8518.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
@@ -346,12 +346,12 @@
*/
/* UART */
-static int mt8518_uart0_0_rxd_txd_pins[] = { 104, 105, };
-static int mt8518_uart0_0_rxd_txd_funcs[] = { 1, 1, };
-static int mt8518_uart1_0_rxd_txd_pins[] = { 52, 53, };
-static int mt8518_uart1_0_rxd_txd_funcs[] = { 1, 1, };
-static int mt8518_uart2_0_rxd_txd_pins[] = { 106, 107, };
-static int mt8518_uart2_0_rxd_txd_funcs[] = { 1, 1, };
+static const int mt8518_uart0_0_rxd_txd_pins[] = { 104, 105, };
+static const int mt8518_uart0_0_rxd_txd_funcs[] = { 1, 1, };
+static const int mt8518_uart1_0_rxd_txd_pins[] = { 52, 53, };
+static const int mt8518_uart1_0_rxd_txd_funcs[] = { 1, 1, };
+static const int mt8518_uart2_0_rxd_txd_pins[] = { 106, 107, };
+static const int mt8518_uart2_0_rxd_txd_funcs[] = { 1, 1, };
/* Joint those groups owning the same capability in user point of view which
* allows that people tend to use through the device tree.
@@ -361,9 +361,9 @@
"uart2_0_rxd_txd", };
/* MMC0 */
-static int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11,
- 12, 13, };
-static int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+static const int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11,
+ 12, 13, };
+static const int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
static const struct mtk_group_desc mt8518_groups[] = {
PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8518_uart0_0_rxd_txd),
@@ -380,7 +380,7 @@
{"msdc", mt8518_msdc_groups, ARRAY_SIZE(mt8518_msdc_groups)},
};
-static struct mtk_pinctrl_soc mt8518_data = {
+static const struct mtk_pinctrl_soc mt8518_data = {
.name = "mt8518_pinctrl",
.reg_cal = mt8518_reg_cals,
.pins = mt8518_pins,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 5a4d58b..0baef57 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -304,6 +304,19 @@
return priv->soc->funcs[selector].name;
}
+static int mtk_pinmux_set(struct udevice *dev, unsigned int pin_selector,
+ unsigned int func_selector)
+{
+ int err;
+
+ err = mtk_hw_set_value(dev, pin_selector, PINCTRL_PIN_REG_MODE,
+ func_selector);
+ if (err)
+ return err;
+
+ return 0;
+}
+
static int mtk_pinmux_group_set(struct udevice *dev,
unsigned int group_selector,
unsigned int func_selector)
@@ -314,7 +327,7 @@
int i;
for (i = 0; i < grp->num_pins; i++) {
- int *pin_modes = grp->data;
+ const int *pin_modes = grp->data;
mtk_hw_set_value(dev, grp->pins[i], PINCTRL_PIN_REG_MODE,
pin_modes[i]);
@@ -513,7 +526,7 @@
return err;
}
- return 0;
+ return err;
}
int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg)
@@ -531,7 +544,7 @@
return err;
}
- return 0;
+ return err;
}
int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg)
@@ -647,6 +660,7 @@
.get_group_name = mtk_get_group_name,
.get_functions_count = mtk_get_functions_count,
.get_function_name = mtk_get_function_name,
+ .pinmux_set = mtk_pinmux_set,
.pinmux_group_set = mtk_pinmux_group_set,
#if CONFIG_IS_ENABLED(PINCONF)
.pinconf_num_params = ARRAY_SIZE(mtk_conf_params),
@@ -769,7 +783,7 @@
#endif
int mtk_pinctrl_common_probe(struct udevice *dev,
- struct mtk_pinctrl_soc *soc)
+ const struct mtk_pinctrl_soc *soc)
{
struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
int ret = 0;
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
index 0d9596f..c948b80 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -174,9 +174,9 @@
*/
struct mtk_group_desc {
const char *name;
- int *pins;
+ const int *pins;
int num_pins;
- void *data;
+ const void *data;
};
/**
@@ -233,7 +233,7 @@
*/
struct mtk_pinctrl_priv {
void __iomem *base[MAX_BASE_CALC];
- struct mtk_pinctrl_soc *soc;
+ const struct mtk_pinctrl_soc *soc;
};
extern const struct pinctrl_ops mtk_pinctrl_ops;
@@ -242,7 +242,7 @@
void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set);
void mtk_i_rmw(struct udevice *dev, u8 i, u32 reg, u32 mask, u32 set);
int mtk_pinctrl_common_probe(struct udevice *dev,
- struct mtk_pinctrl_soc *soc);
+ const struct mtk_pinctrl_soc *soc);
#if CONFIG_IS_ENABLED(PINCONF)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
index 314edb5..1d43919 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3568.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
@@ -113,11 +113,9 @@
struct rockchip_pinctrl_priv *priv = bank->priv;
int iomux_num = (pin / 8);
struct regmap *regmap;
- int reg, ret, mask;
+ int reg, mask;
u8 bit;
- u32 data;
-
- debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
+ u32 data, rmask;
if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
regmap = priv->regmap_pmu;
@@ -131,10 +129,10 @@
mask = 0xf;
data = (mask << (bit + 16));
+ rmask = data | (data >> 16);
data |= (mux & mask) << bit;
- ret = regmap_write(regmap, reg, data);
- return ret;
+ return regmap_update_bits(regmap, reg, rmask, data);
}
#define RK3568_PULL_PMU_OFFSET 0x20
@@ -225,7 +223,7 @@
struct regmap *regmap;
int reg, ret;
u8 bit, type;
- u32 data;
+ u32 data, rmask;
if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
return -ENOTSUPP;
@@ -249,52 +247,59 @@
/* enable the write to the equivalent lower bits */
data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
-
+ rmask = data | (data >> 16);
data |= (ret << bit);
- ret = regmap_write(regmap, reg, data);
- return ret;
+ return regmap_update_bits(regmap, reg, rmask, data);
}
+#define GRF_GPIO1C5_DS 0x0840
+#define GRF_GPIO2A2_DS 0x0844
+#define GRF_GPIO2B0_DS 0x0848
+#define GRF_GPIO3A0_DS 0x084c
+#define GRF_GPIO3A6_DS 0x0850
+#define GRF_GPIO4A0_DS 0x0854
+
static int rk3568_set_drive(struct rockchip_pin_bank *bank,
int pin_num, int strength)
{
struct regmap *regmap;
- int reg;
- u32 data;
+ int reg, ret;
+ u32 data, rmask;
u8 bit;
int drv = (1 << (strength + 1)) - 1;
- int ret = 0;
rk3568_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
/* enable the write to the equivalent lower bits */
data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+ rmask = data | (data >> 16);
data |= (drv << bit);
- ret = regmap_write(regmap, reg, data);
+ ret = regmap_update_bits(regmap, reg, rmask, data);
if (ret)
return ret;
if (bank->bank_num == 1 && pin_num == 21)
- reg = 0x0840;
+ reg = GRF_GPIO1C5_DS;
else if (bank->bank_num == 2 && pin_num == 2)
- reg = 0x0844;
+ reg = GRF_GPIO2A2_DS;
else if (bank->bank_num == 2 && pin_num == 8)
- reg = 0x0848;
+ reg = GRF_GPIO2B0_DS;
else if (bank->bank_num == 3 && pin_num == 0)
- reg = 0x084c;
+ reg = GRF_GPIO3A0_DS;
else if (bank->bank_num == 3 && pin_num == 6)
- reg = 0x0850;
+ reg = GRF_GPIO3A6_DS;
else if (bank->bank_num == 4 && pin_num == 0)
- reg = 0x0854;
+ reg = GRF_GPIO4A0_DS;
else
return 0;
data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16;
- data |= drv;
+ rmask = data | (data >> 16);
+ data |= drv >> 6;
- return regmap_write(regmap, reg, data);
+ return regmap_update_bits(regmap, reg, rmask, data);
}
static int rk3568_set_schmitt(struct rockchip_pin_bank *bank,
@@ -302,16 +307,17 @@
{
struct regmap *regmap;
int reg;
- u32 data;
+ u32 data, rmask;
u8 bit;
rk3568_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
/* enable the write to the equivalent lower bits */
data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
- data |= (enable << bit);
+ rmask = data | (data >> 16);
+ data |= ((enable ? 0x2 : 0x1) << bit);
- return regmap_write(regmap, reg, data);
+ return regmap_update_bits(regmap, reg, rmask, data);
}
static struct rockchip_pin_bank rk3568_pin_banks[] = {
diff --git a/drivers/pwm/pwm-mtk.c b/drivers/pwm/pwm-mtk.c
index 605142e..11e7444 100644
--- a/drivers/pwm/pwm-mtk.c
+++ b/drivers/pwm/pwm-mtk.c
@@ -205,12 +205,19 @@
.reg_ver = PWM_REG_V1,
};
+static const struct mtk_pwm_soc mt7988_data = {
+ .num_pwms = 8,
+ .pwm45_fixup = false,
+ .reg_ver = PWM_REG_V2,
+};
+
static const struct udevice_id mtk_pwm_ids[] = {
{ .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data },
{ .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data },
{ .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data },
{ .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data },
{ .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data },
+ { .compatible = "mediatek,mt7988-pwm", .data = (ulong)&mt7988_data },
{ }
};
diff --git a/drivers/ram/mediatek/ddr3-mt7629.c b/drivers/ram/mediatek/ddr3-mt7629.c
index 1737fda..f65fcf1 100644
--- a/drivers/ram/mediatek/ddr3-mt7629.c
+++ b/drivers/ram/mediatek/ddr3-mt7629.c
@@ -14,6 +14,7 @@
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <linux/sizes.h>
/* EMI */
#define EMI_CONA 0x000
diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c
index 50bcc90..19fe405 100644
--- a/drivers/remoteproc/rproc-uclass.c
+++ b/drivers/remoteproc/rproc-uclass.c
@@ -689,7 +689,7 @@
debug("alloc_mem(%#x, %d): %p\n", size, order, pa);
vring->da = (uintptr_t)pa;
- return !pa;
+ return 0;
}
static int handle_vdev(struct udevice *dev, struct fw_rsc_vdev *rsc,
diff --git a/drivers/reset/reset-mediatek.c b/drivers/reset/reset-mediatek.c
index 8b62d91..97ed221 100644
--- a/drivers/reset/reset-mediatek.c
+++ b/drivers/reset/reset-mediatek.c
@@ -79,6 +79,9 @@
return ret;
priv = malloc(sizeof(struct mediatek_reset_priv));
+ if (!priv)
+ return -ENOMEM;
+
priv->regofs = regofs;
priv->nr_resets = num_regs * 32;
dev_set_priv(rst_dev, priv);
diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c
index 6caeb3f..7411660 100644
--- a/drivers/scsi/scsi.c
+++ b/drivers/scsi/scsi.c
@@ -14,6 +14,7 @@
#include <env.h>
#include <libata.h>
#include <log.h>
+#include <memalign.h>
#include <part.h>
#include <pci.h>
#include <scsi.h>
@@ -42,7 +43,7 @@
#endif
static struct scsi_cmd tempccb; /* temporary scsi command buffer */
-static unsigned char tempbuff[512]; /* temporary data buffer */
+DEFINE_CACHE_ALIGN_BUFFER(u8, tempbuff, 512); /* temporary data buffer */
#if !defined(CONFIG_DM_SCSI)
static int scsi_max_devs; /* number of highest available scsi device */
@@ -273,6 +274,18 @@
__func__, start, smallblks, buf_addr);
return blkcnt;
}
+
+#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
+static int scsi_buffer_aligned(struct udevice *dev, struct bounce_buffer *state)
+{
+ struct scsi_ops *ops = scsi_get_ops(dev->parent);
+
+ if (ops->buffer_aligned)
+ return ops->buffer_aligned(dev->parent, state);
+
+ return 1;
+}
+#endif /* CONFIG_BOUNCE_BUFFER */
#endif
#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT) && \
@@ -490,7 +503,7 @@
pccb->target = target;
pccb->lun = lun;
- pccb->pdata = (unsigned char *)&tempbuff;
+ pccb->pdata = tempbuff;
pccb->datalen = 512;
pccb->dma_dir = DMA_FROM_DEVICE;
scsi_setup_inquiry(pccb);
@@ -607,7 +620,7 @@
/* TODO: undo create */
return log_msg_ret("pro", ret);
- ret = bootdev_setup_sibling_blk(bdev, "scsi_bootdev");
+ ret = bootdev_setup_for_sibling_blk(bdev, "scsi_bootdev");
if (ret)
return log_msg_ret("bd", ret);
@@ -719,6 +732,9 @@
static const struct blk_ops scsi_blk_ops = {
.read = scsi_read,
.write = scsi_write,
+#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
+ .buffer_aligned = scsi_buffer_aligned,
+#endif /* CONFIG_BOUNCE_BUFFER */
};
U_BOOT_DRIVER(scsi_blk) = {
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index a1e0899..7ca42df 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -482,8 +482,8 @@
config DEBUG_UART_BASE
hex "Base address of UART"
depends on DEBUG_UART
- default 0 if DEBUG_SBI_CONSOLE
- default 0 if DEBUG_UART_SANDBOX
+ default 0x0 if DEBUG_SBI_CONSOLE
+ default 0x0 if DEBUG_UART_SANDBOX
default 0xff000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP
default 0xe0000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ
help
@@ -1139,6 +1139,6 @@
config SYS_SDMR
hex "SDMR Value"
depends on MPC8XX_CONS
- default 0
+ default 0x0
endif
diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c
index ded7346..2dffa14 100644
--- a/drivers/serial/serial_mtk.c
+++ b/drivers/serial/serial_mtk.c
@@ -439,6 +439,7 @@
{
struct mtk_serial_priv priv;
+ memset(&priv, 0, sizeof(struct mtk_serial_priv));
priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE);
priv.fixed_clk_rate = CONFIG_DEBUG_UART_CLOCK;
diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
index 0085113..23d476f 100644
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -22,6 +22,14 @@
#include "serial_stm32.h"
#include <dm/device_compat.h>
+/*
+ * At 115200 bits/s
+ * 1 bit = 1 / 115200 = 8,68 us
+ * 8 bits = 69,444 us
+ * 10 bits are needed for worst case (8 bits + 1 start + 1 stop) = 86.806 us
+ */
+#define ONE_BYTE_B115200_US 87
+
static void _stm32_serial_setbrg(fdt_addr_t base,
struct stm32_uart_info *uart_info,
u32 clock_rate,
@@ -209,12 +217,10 @@
* before uart initialization, wait for TC bit (Transmission Complete)
* in case there is still chars from previous bootstage to transmit
*/
- ret = read_poll_timeout(readl, isr, isr & USART_ISR_TC, 10, 150,
- plat->base + ISR_OFFSET(stm32f4));
- if (ret) {
- clk_disable(&clk);
- return ret;
- }
+ ret = read_poll_timeout(readl, isr, isr & USART_ISR_TC, 50,
+ 16 * ONE_BYTE_B115200_US, plat->base + ISR_OFFSET(stm32f4));
+ if (ret)
+ dev_dbg(dev, "FIFO not empty, some character can be lost (%d)\n", ret);
ret = reset_get_by_index(dev, 0, &reset);
if (!ret) {
diff --git a/drivers/spi/mtk_spim.c b/drivers/spi/mtk_spim.c
index ebb8ee8..418e586 100644
--- a/drivers/spi/mtk_spim.c
+++ b/drivers/spi/mtk_spim.c
@@ -137,6 +137,8 @@
* @state: Controller state
* @sel_clk: Pad clock
* @spi_clk: Core clock
+ * @pll_clk_rate: Controller's PLL source clock rate, which is different
+ * from SPI bus clock rate
* @xfer_len: Current length of data for transfer
* @hw_cap: Controller capabilities
* @tick_dly: Used to postpone SPI sampling time
@@ -149,6 +151,7 @@
void __iomem *base;
u32 state;
struct clk sel_clk, spi_clk;
+ u32 pll_clk_rate;
u32 xfer_len;
struct mtk_spim_capability hw_cap;
u32 tick_dly;
@@ -239,6 +242,9 @@
reg_val &= ~SPI_CMD_SAMPLE_SEL;
}
+ /* Disable interrupt enable for pause mode & normal mode */
+ reg_val &= ~(SPI_CMD_PAUSE_IE | SPI_CMD_FINISH_IE);
+
/* disable dma mode */
reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
@@ -253,11 +259,10 @@
static void mtk_spim_prepare_transfer(struct mtk_spim_priv *priv,
u32 speed_hz)
{
- u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
+ u32 div, sck_time, cs_time, reg_val;
- spi_clk_hz = clk_get_rate(&priv->spi_clk);
- if (speed_hz <= spi_clk_hz / 4)
- div = DIV_ROUND_UP(spi_clk_hz, speed_hz);
+ if (speed_hz <= priv->pll_clk_rate / 4)
+ div = DIV_ROUND_UP(priv->pll_clk_rate, speed_hz);
else
div = 4;
@@ -404,7 +409,7 @@
{
struct udevice *bus = dev_get_parent(slave->dev);
struct mtk_spim_priv *priv = dev_get_priv(bus);
- u32 sck_l, sck_h, spi_bus_clk, clk_count, reg;
+ u32 sck_l, sck_h, clk_count, reg;
ulong us = 1;
int ret = 0;
@@ -413,12 +418,11 @@
else
clk_count = op->data.nbytes;
- spi_bus_clk = clk_get_rate(&priv->spi_clk);
sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET;
sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK;
- do_div(spi_bus_clk, sck_l + sck_h + 2);
+ do_div(priv->pll_clk_rate, sck_l + sck_h + 2);
- us = CLK_TO_US(spi_bus_clk, clk_count * 8);
+ us = CLK_TO_US(priv->pll_clk_rate, clk_count * 8);
us += 1000 * 1000; /* 1s tolerance */
if (us > UINT_MAX)
@@ -662,6 +666,10 @@
clk_enable(&priv->sel_clk);
clk_enable(&priv->spi_clk);
+ priv->pll_clk_rate = clk_get_rate(&priv->spi_clk);
+ if (priv->pll_clk_rate == 0)
+ return -EINVAL;
+
return 0;
}
diff --git a/drivers/ufs/cdns-platform.c b/drivers/ufs/cdns-platform.c
index bad1bf7..1e62e25 100644
--- a/drivers/ufs/cdns-platform.c
+++ b/drivers/ufs/cdns-platform.c
@@ -119,7 +119,7 @@
U_BOOT_DRIVER(cdns_ufs_pltfm) = {
.name = "cdns-ufs-pltfm",
- .id = UCLASS_UFS,
+ .id = UCLASS_UFS,
.of_match = cdns_ufs_pltfm_ids,
.probe = cdns_ufs_pltfm_probe,
.bind = cdns_ufs_pltfm_bind,
diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c
index 3bf1a95..7c48d57 100644
--- a/drivers/ufs/ufs.c
+++ b/drivers/ufs/ufs.c
@@ -8,6 +8,7 @@
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
*/
+#include <bouncebuf.h>
#include <charset.h>
#include <common.h>
#include <dm.h>
@@ -692,13 +693,29 @@
}
/**
+ * ufshcd_cache_flush_and_invalidate - Flush and invalidate cache
+ *
+ * Flush and invalidate cache in aligned address..address+size range.
+ * The invalidation is in place to avoid stale data in cache.
+ */
+static void ufshcd_cache_flush_and_invalidate(void *addr, unsigned long size)
+{
+ uintptr_t aaddr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1);
+ unsigned long asize = ALIGN(size, ARCH_DMA_MINALIGN);
+
+ flush_dcache_range(aaddr, aaddr + asize);
+ invalidate_dcache_range(aaddr, aaddr + asize);
+}
+
+/**
* ufshcd_prepare_req_desc_hdr() - Fills the requests header
* descriptor according to request
*/
-static void ufshcd_prepare_req_desc_hdr(struct utp_transfer_req_desc *req_desc,
+static void ufshcd_prepare_req_desc_hdr(struct ufs_hba *hba,
u32 *upiu_flags,
enum dma_data_direction cmd_dir)
{
+ struct utp_transfer_req_desc *req_desc = hba->utrdl;
u32 data_direction;
u32 dword_0;
@@ -733,6 +750,8 @@
req_desc->header.dword_3 = 0;
req_desc->prd_table_length = 0;
+
+ ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc));
}
static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
@@ -761,10 +780,15 @@
memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, QUERY_OSF_SIZE);
/* Copy the Descriptor */
- if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
+ if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) {
memcpy(ucd_req_ptr + 1, query->descriptor, len);
+ ufshcd_cache_flush_and_invalidate(ucd_req_ptr, 2 * sizeof(*ucd_req_ptr));
+ } else {
+ ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr));
+ }
memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
+ ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr));
}
static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba)
@@ -781,6 +805,9 @@
ucd_req_ptr->header.dword_2 = 0;
memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
+
+ ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr));
+ ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr));
}
/**
@@ -792,11 +819,10 @@
{
u32 upiu_flags;
int ret = 0;
- struct utp_transfer_req_desc *req_desc = hba->utrdl;
hba->dev_cmd.type = cmd_type;
- ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, DMA_NONE);
+ ufshcd_prepare_req_desc_hdr(hba, &upiu_flags, DMA_NONE);
switch (cmd_type) {
case DEV_CMD_TYPE_QUERY:
ufshcd_prepare_utp_query_req_upiu(hba, upiu_flags);
@@ -857,7 +883,9 @@
*/
static inline int ufshcd_get_tr_ocs(struct ufs_hba *hba)
{
- return le32_to_cpu(hba->utrdl->header.dword_2) & MASK_OCS;
+ struct utp_transfer_req_desc *req_desc = hba->utrdl;
+
+ return le32_to_cpu(req_desc->header.dword_2) & MASK_OCS;
}
static inline int ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
@@ -1406,6 +1434,8 @@
memcpy(ucd_req_ptr->sc.cdb, pccb->cmd, cdb_len);
memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
+ ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr));
+ ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr));
}
static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry,
@@ -1420,6 +1450,7 @@
{
struct utp_transfer_req_desc *req_desc = hba->utrdl;
struct ufshcd_sg_entry *prd_table = hba->ucd_prdt_ptr;
+ uintptr_t aaddr = (uintptr_t)(pccb->pdata) & ~(ARCH_DMA_MINALIGN - 1);
ulong datalen = pccb->datalen;
int table_length;
u8 *buf;
@@ -1427,9 +1458,19 @@
if (!datalen) {
req_desc->prd_table_length = 0;
+ ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc));
return;
}
+ if (pccb->dma_dir == DMA_TO_DEVICE) { /* Write to device */
+ flush_dcache_range(aaddr, aaddr +
+ ALIGN(datalen, ARCH_DMA_MINALIGN));
+ }
+
+ /* In any case, invalidate cache to avoid stale data in it. */
+ invalidate_dcache_range(aaddr, aaddr +
+ ALIGN(datalen, ARCH_DMA_MINALIGN));
+
table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY);
buf = pccb->pdata;
i = table_length;
@@ -1443,17 +1484,18 @@
prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1);
req_desc->prd_table_length = table_length;
+ ufshcd_cache_flush_and_invalidate(prd_table, sizeof(*prd_table) * table_length);
+ ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc));
}
static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb)
{
struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent);
- struct utp_transfer_req_desc *req_desc = hba->utrdl;
u32 upiu_flags;
int ocs, result = 0;
u8 scsi_status;
- ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, pccb->dma_dir);
+ ufshcd_prepare_req_desc_hdr(hba, &upiu_flags, pccb->dma_dir);
ufshcd_prepare_utp_scsi_cmd_upiu(hba, pccb, upiu_flags);
prepare_prdt_table(hba, pccb);
@@ -1630,8 +1672,13 @@
if (hba->max_pwr_info.is_valid)
return 0;
- pwr_info->pwr_tx = FAST_MODE;
- pwr_info->pwr_rx = FAST_MODE;
+ if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) {
+ pwr_info->pwr_tx = FASTAUTO_MODE;
+ pwr_info->pwr_rx = FASTAUTO_MODE;
+ } else {
+ pwr_info->pwr_tx = FAST_MODE;
+ pwr_info->pwr_rx = FAST_MODE;
+ }
pwr_info->hs_rate = PA_HS_MODE_B;
/* Get the connected lane count */
@@ -1889,13 +1936,16 @@
/* Read capabilties registers */
hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
+ if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS)
+ hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT;
/* Get UFS version supported by the controller */
hba->version = ufshcd_get_ufs_version(hba);
if (hba->version != UFSHCI_VERSION_10 &&
hba->version != UFSHCI_VERSION_11 &&
hba->version != UFSHCI_VERSION_20 &&
- hba->version != UFSHCI_VERSION_21)
+ hba->version != UFSHCI_VERSION_21 &&
+ hba->version != UFSHCI_VERSION_30)
dev_err(hba->dev, "invalid UFS version 0x%x\n",
hba->version);
@@ -1942,8 +1992,31 @@
return ret;
}
+#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
+static int ufs_scsi_buffer_aligned(struct udevice *scsi_dev, struct bounce_buffer *state)
+{
+#ifdef CONFIG_PHYS_64BIT
+ struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent);
+ uintptr_t ubuf = (uintptr_t)state->user_buffer;
+ size_t len = state->len_aligned;
+
+ /* Check if below 32bit boundary */
+ if ((hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS) &&
+ ((ubuf >> 32) || (ubuf + len) >> 32)) {
+ dev_dbg(scsi_dev, "Buffer above 32bit boundary %lx-%lx\n",
+ ubuf, ubuf + len);
+ return 0;
+ }
+#endif
+ return 1;
+}
+#endif /* CONFIG_BOUNCE_BUFFER */
+
static struct scsi_ops ufs_ops = {
.exec = ufs_scsi_exec,
+#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
+ .buffer_aligned = ufs_scsi_buffer_aligned,
+#endif /* CONFIG_BOUNCE_BUFFER */
};
int ufs_probe_dev(int index)
diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h
index 8a38832..9daaf03 100644
--- a/drivers/ufs/ufs.h
+++ b/drivers/ufs/ufs.h
@@ -717,7 +717,19 @@
* the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
* attribute of device to 0).
*/
-#define UFSHCD_QUIRK_BROKEN_LCC 0x1
+#define UFSHCD_QUIRK_BROKEN_LCC BIT(0)
+
+/*
+ * This quirk needs to be enabled if the host controller has
+ * 64-bit addressing supported capability but it doesn't work.
+ */
+#define UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS BIT(1)
+
+/*
+ * This quirk needs to be enabled if the host controller has
+ * auto-hibernate capability but it's FASTAUTO only.
+ */
+#define UFSHCD_QUIRK_HIBERN_FASTAUTO BIT(2)
/* Virtual memory reference */
struct utp_transfer_cmd_desc *ucdl;
@@ -769,6 +781,7 @@
UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
+ UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */
};
/* Interrupt disable masks */
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 1cfe602..4eccc5e 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -160,7 +160,7 @@
config SDP_LOADADDR
hex "Default load address at SDP_WRITE and SDP_JUMP"
- default 0
+ default 0x0
# Selected by UDC drivers that support high-speed operation.
config USB_GADGET_DUALSPEED
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index 85c971e..5ff06d3 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -2273,56 +2273,16 @@
}
/*-------------------------------------------------------------------------*/
-static void _usb_eth_halt(struct ether_priv *priv);
+static void usb_eth_stop(struct udevice *dev);
-static int _usb_eth_init(struct ether_priv *priv)
+static int usb_eth_start(struct udevice *udev)
{
+ struct ether_priv *priv = dev_get_priv(udev);
struct eth_dev *dev = &priv->ethdev;
struct usb_gadget *gadget;
unsigned long ts;
- int ret;
unsigned long timeout = USB_CONNECT_TIMEOUT;
- ret = usb_gadget_initialize(0);
- if (ret)
- return ret;
-
- /* Configure default mac-addresses for the USB ethernet device */
-#ifdef CONFIG_USBNET_DEV_ADDR
- strlcpy(dev_addr, CONFIG_USBNET_DEV_ADDR, sizeof(dev_addr));
-#endif
-#ifdef CONFIG_USBNET_HOST_ADDR
- strlcpy(host_addr, CONFIG_USBNET_HOST_ADDR, sizeof(host_addr));
-#endif
- /* Check if the user overruled the MAC addresses */
- if (env_get("usbnet_devaddr"))
- strlcpy(dev_addr, env_get("usbnet_devaddr"),
- sizeof(dev_addr));
-
- if (env_get("usbnet_hostaddr"))
- strlcpy(host_addr, env_get("usbnet_hostaddr"),
- sizeof(host_addr));
-
- if (!is_eth_addr_valid(dev_addr)) {
- pr_err("Need valid 'usbnet_devaddr' to be set");
- goto fail;
- }
- if (!is_eth_addr_valid(host_addr)) {
- pr_err("Need valid 'usbnet_hostaddr' to be set");
- goto fail;
- }
-
- priv->eth_driver.speed = DEVSPEED;
- priv->eth_driver.bind = eth_bind;
- priv->eth_driver.unbind = eth_unbind;
- priv->eth_driver.setup = eth_setup;
- priv->eth_driver.reset = eth_disconnect;
- priv->eth_driver.disconnect = eth_disconnect;
- priv->eth_driver.suspend = eth_suspend;
- priv->eth_driver.resume = eth_resume;
- if (usb_gadget_register_driver(&priv->eth_driver) < 0)
- goto fail;
-
dev->network_started = 0;
packet_received = 0;
@@ -2347,12 +2307,13 @@
rx_submit(dev, dev->rx_req, 0);
return 0;
fail:
- _usb_eth_halt(priv);
+ usb_eth_stop(udev);
return -1;
}
-static int _usb_eth_send(struct ether_priv *priv, void *packet, int length)
+static int usb_eth_send(struct udevice *udev, void *packet, int length)
{
+ struct ether_priv *priv = dev_get_priv(udev);
int retval;
void *rndis_pkt = NULL;
struct eth_dev *dev = &priv->ethdev;
@@ -2419,15 +2380,9 @@
return -ENOMEM;
}
-static int _usb_eth_recv(struct ether_priv *priv)
+static void usb_eth_stop(struct udevice *udev)
{
- usb_gadget_handle_interrupts(0);
-
- return 0;
-}
-
-static void _usb_eth_halt(struct ether_priv *priv)
-{
+ struct ether_priv *priv = dev_get_priv(udev);
struct eth_dev *dev = &priv->ethdev;
/* If the gadget not registered, simple return */
@@ -2454,36 +2409,14 @@
usb_gadget_handle_interrupts(0);
dev->network_started = 0;
}
-
- usb_gadget_unregister_driver(&priv->eth_driver);
- usb_gadget_release(0);
-}
-
-static int usb_eth_start(struct udevice *dev)
-{
- struct ether_priv *priv = dev_get_priv(dev);
-
- return _usb_eth_init(priv);
-}
-
-static int usb_eth_send(struct udevice *dev, void *packet, int length)
-{
- struct ether_priv *priv = dev_get_priv(dev);
-
- return _usb_eth_send(priv, packet, length);
}
static int usb_eth_recv(struct udevice *dev, int flags, uchar **packetp)
{
struct ether_priv *priv = dev_get_priv(dev);
struct eth_dev *ethdev = &priv->ethdev;
- int ret;
- ret = _usb_eth_recv(priv);
- if (ret) {
- pr_err("error packet receive\n");
- return ret;
- }
+ usb_gadget_handle_interrupts(0);
if (packet_received) {
if (ethdev->rx_req) {
@@ -2509,27 +2442,6 @@
return rx_submit(ethdev, ethdev->rx_req, 0);
}
-static void usb_eth_stop(struct udevice *dev)
-{
- struct ether_priv *priv = dev_get_priv(dev);
-
- _usb_eth_halt(priv);
-}
-
-static int usb_eth_probe(struct udevice *dev)
-{
- struct ether_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_plat(dev);
-
- priv->netdev = dev;
- l_priv = priv;
-
- get_ether_addr(CONFIG_USBNET_DEV_ADDR, pdata->enetaddr);
- eth_env_set_enetaddr("usbnet_devaddr", pdata->enetaddr);
-
- return 0;
-}
-
static const struct eth_ops usb_eth_ops = {
.start = usb_eth_start,
.send = usb_eth_send,
@@ -2555,6 +2467,69 @@
return ret;
}
+ return usb_gadget_initialize(0);
+}
+
+static int usb_eth_probe(struct udevice *dev)
+{
+ struct ether_priv *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+
+ priv->netdev = dev;
+ l_priv = priv;
+
+ get_ether_addr(CONFIG_USBNET_DEV_ADDR, pdata->enetaddr);
+ eth_env_set_enetaddr("usbnet_devaddr", pdata->enetaddr);
+
+ /* Configure default mac-addresses for the USB ethernet device */
+#ifdef CONFIG_USBNET_DEV_ADDR
+ strlcpy(dev_addr, CONFIG_USBNET_DEV_ADDR, sizeof(dev_addr));
+#endif
+#ifdef CONFIG_USBNET_HOST_ADDR
+ strlcpy(host_addr, CONFIG_USBNET_HOST_ADDR, sizeof(host_addr));
+#endif
+ /* Check if the user overruled the MAC addresses */
+ if (env_get("usbnet_devaddr"))
+ strlcpy(dev_addr, env_get("usbnet_devaddr"),
+ sizeof(dev_addr));
+
+ if (env_get("usbnet_hostaddr"))
+ strlcpy(host_addr, env_get("usbnet_hostaddr"),
+ sizeof(host_addr));
+
+ if (!is_eth_addr_valid(dev_addr)) {
+ pr_err("Need valid 'usbnet_devaddr' to be set");
+ return -EINVAL;
+ }
+ if (!is_eth_addr_valid(host_addr)) {
+ pr_err("Need valid 'usbnet_hostaddr' to be set");
+ return -EINVAL;
+ }
+
+ priv->eth_driver.speed = DEVSPEED;
+ priv->eth_driver.bind = eth_bind;
+ priv->eth_driver.unbind = eth_unbind;
+ priv->eth_driver.setup = eth_setup;
+ priv->eth_driver.reset = eth_disconnect;
+ priv->eth_driver.disconnect = eth_disconnect;
+ priv->eth_driver.suspend = eth_suspend;
+ priv->eth_driver.resume = eth_resume;
+ return usb_gadget_register_driver(&priv->eth_driver);
+}
+
+static int usb_eth_remove(struct udevice *dev)
+{
+ struct ether_priv *priv = dev_get_priv(dev);
+
+ usb_gadget_unregister_driver(&priv->eth_driver);
+
+ return 0;
+}
+
+static int usb_eth_unbind(struct udevice *dev)
+{
+ usb_gadget_release(0);
+
return 0;
}
@@ -2562,6 +2537,8 @@
.name = "usb_ether",
.id = UCLASS_ETH,
.probe = usb_eth_probe,
+ .remove = usb_eth_remove,
+ .unbind = usb_eth_unbind,
.ops = &usb_eth_ops,
.priv_auto = sizeof(struct ether_priv),
.plat_auto = sizeof(struct eth_pdata),
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 9818f9b..637eb2d 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -194,8 +194,8 @@
return 0;
}
- ret = regulator_set_enable(priv->vbus_supply, true);
- if (ret) {
+ ret = regulator_set_enable_if_allowed(priv->vbus_supply, true);
+ if (ret && ret != -ENOSYS) {
dev_err(dev, "Error enabling vbus supply\n");
return ret;
}
@@ -208,12 +208,10 @@
struct dwc2_priv *priv = dev_get_priv(dev);
int ret;
- if (priv->vbus_supply) {
- ret = regulator_set_enable(priv->vbus_supply, false);
- if (ret) {
- dev_err(dev, "Error disabling vbus supply\n");
- return ret;
- }
+ ret = regulator_set_enable_if_allowed(priv->vbus_supply, false);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "Error disabling vbus supply\n");
+ return ret;
}
return 0;
diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
index a765a30..936e304 100644
--- a/drivers/usb/host/ehci-generic.c
+++ b/drivers/usb/host/ehci-generic.c
@@ -39,14 +39,10 @@
if (ret && ret != -ENOENT)
return ret;
- if (priv->vbus_supply) {
- ret = regulator_set_enable(priv->vbus_supply, true);
- if (ret) {
- dev_err(dev, "Error enabling VBUS supply (ret=%d)\n", ret);
- return ret;
- }
- } else {
- dev_dbg(dev, "No vbus supply\n");
+ ret = regulator_set_enable_if_allowed(priv->vbus_supply, true);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "Error enabling VBUS supply (ret=%d)\n", ret);
+ return ret;
}
return 0;
@@ -54,10 +50,13 @@
static int ehci_disable_vbus_supply(struct generic_ehci *priv)
{
- if (priv->vbus_supply)
- return regulator_set_enable(priv->vbus_supply, false);
- else
- return 0;
+ int ret;
+
+ ret = regulator_set_enable_if_allowed(priv->vbus_supply, false);
+ if (ret && ret != -ENOSYS)
+ return ret;
+
+ return 0;
}
static int ehci_usb_probe(struct udevice *dev)
diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c
index 02c0138..7a03435 100644
--- a/drivers/usb/host/usb-uclass.c
+++ b/drivers/usb/host/usb-uclass.c
@@ -346,7 +346,7 @@
if (controllers_initialized == 0)
printf("No working controllers found\n");
- return usb_started ? 0 : -1;
+ return usb_started ? 0 : -ENOENT;
}
int usb_setup_ehci_gadget(struct ehci_ctrl **ctlrp)
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index e32ce13..09f2cb1 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -66,7 +66,7 @@
hex "Default framebuffer size to use if no drivers request it"
default 0x1000000 if X86
default 0x800000 if !X86 && VIDEO_BOCHS
- default 0 if !X86 && !VIDEO_BOCHS
+ default 0x0 if !X86 && !VIDEO_BOCHS
help
Generally, video drivers request the amount of memory they need for
the frame buffer when they are bound, by setting the size field in
@@ -1011,6 +1011,16 @@
if SPL_VIDEO
source "drivers/video/tidss/Kconfig"
+config SPL_VIDEO_HANDOFF
+ bool "Pass the video frame-buffer through to U-Boot proper"
+ depends on SPL_BLOBLIST
+ default y if !X86
+ help
+ Enable this to set up video-handoff information in SPL which can be
+ picked up in U-Boot proper. This includes the frame buffer and
+ various other pieces of information. With this enabled, SPL can set
+ up video and avoid re-initing it later.
+
config SPL_VIDEO_LOGO
bool "Show the U-Boot logo on the display at SPL"
default y if !SPL_SPLASH_SCREEN
@@ -1039,7 +1049,7 @@
hex "Default framebuffer size to use if no drivers request it at SPL"
default 0x1000000 if X86
default 0x800000 if !X86 && VIDEO_BOCHS
- default 0 if !X86 && !VIDEO_BOCHS
+ default 0x0 if !X86 && !VIDEO_BOCHS
help
Generally, video drivers request the amount of memory they need for
the frame buffer when they are bound, by setting the size field in
@@ -1105,7 +1115,7 @@
bool "Remove video driver after SPL stage"
help
if this option is enabled video driver will be removed at the end of
- SPL stage, beforeloading the next stage.
+ SPL stage, before loading the next stage.
if SPL_SPLASH_SCREEN
diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c
index c296293..1494252 100644
--- a/drivers/video/bcm2835.c
+++ b/drivers/video/bcm2835.c
@@ -54,6 +54,9 @@
{ .compatible = "brcm,bcm2835-hdmi" },
{ .compatible = "brcm,bcm2711-hdmi0" },
{ .compatible = "brcm,bcm2708-fb" },
+#if !IS_ENABLED(CONFIG_VIDEO_DT_SIMPLEFB)
+ { .compatible = "simple-framebuffer" },
+#endif
{ }
};
diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c
index 46c16a8..aa0e292 100644
--- a/drivers/video/pwm_backlight.c
+++ b/drivers/video/pwm_backlight.c
@@ -14,6 +14,7 @@
#include <pwm.h>
#include <asm/gpio.h>
#include <linux/delay.h>
+#include <linux/math64.h>
#include <power/regulator.h>
/**
@@ -59,12 +60,14 @@
static int set_pwm(struct pwm_backlight_priv *priv)
{
+ u64 width;
uint duty_cycle;
int ret;
if (priv->period_ns) {
- duty_cycle = (u64)priv->period_ns * (priv->cur_level - priv->min_level) /
- (priv->max_level - priv->min_level);
+ width = priv->period_ns * (priv->cur_level - priv->min_level);
+ duty_cycle = div_u64(width,
+ (priv->max_level - priv->min_level));
ret = pwm_set_config(priv->pwm, priv->channel, priv->period_ns,
duty_cycle);
} else {
diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c
index 05f9304..b5b3b66 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -603,7 +603,7 @@
struct vidconsole_ops *ops = vidconsole_get_ops(dev);
int ret;
- if (ops->select_font) {
+ if (ops->measure) {
ret = ops->measure(dev, name, size, text, bbox);
if (ret != -ENOSYS)
return ret;
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index 8f268fc..f743ed7 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -141,7 +141,7 @@
debug("Video frame buffers from %lx to %lx\n", gd->video_bottom,
gd->video_top);
- if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(BLOBLIST)) {
+ if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(VIDEO_HANDOFF)) {
struct video_handoff *ho;
ho = bloblist_add(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho), 0);
diff --git a/drivers/virtio/virtio-uclass.c b/drivers/virtio/virtio-uclass.c
index 31bb21c..c542016 100644
--- a/drivers/virtio/virtio-uclass.c
+++ b/drivers/virtio/virtio-uclass.c
@@ -238,7 +238,7 @@
ret = device_bind_driver(udev, name, str, &vdev);
if (ret == -ENOENT) {
- debug("(%s): no driver configured\n", udev->name);
+ debug("(%s): %s driver not configured\n", udev->name, name);
return 0;
}
if (ret) {
@@ -248,7 +248,7 @@
device_set_name_alloced(vdev);
if (uc_priv->device == VIRTIO_ID_BLOCK && !IS_ENABLED(CONFIG_SANDBOX)) {
- ret = bootdev_setup_sibling_blk(vdev, "virtio_bootdev");
+ ret = bootdev_setup_for_sibling_blk(vdev, "virtio_bootdev");
if (ret)
return log_msg_ret("bootdev", ret);
}
diff --git a/drivers/watchdog/ftwdt010_wdt.c b/drivers/watchdog/ftwdt010_wdt.c
index a6b33b1..1f5f301 100644
--- a/drivers/watchdog/ftwdt010_wdt.c
+++ b/drivers/watchdog/ftwdt010_wdt.c
@@ -25,8 +25,27 @@
struct ftwdt010_wdt __iomem *regs;
};
+static int ftwdt010_wdt_reset(struct udevice *dev)
+{
+ struct ftwdt010_wdt_priv *priv = dev_get_priv(dev);
+ struct ftwdt010_wdt *wd = priv->regs;
+
+ debug("Reset WDT..\n");
+
+ /* clear control register */
+ writel(0, &wd->wdcr);
+
+ /* Write Magic number */
+ writel(FTWDT010_WDRESTART_MAGIC, &wd->wdrestart);
+
+ /* Enable WDT */
+ writel(FTWDT010_WDCR_RST | FTWDT010_WDCR_ENABLE, &wd->wdcr);
+
+ return 0;
+}
+
/*
- * Set the watchdog time interval.
+ * Set the watchdog time interval and start the timer.
* Counter is 32 bit.
*/
static int ftwdt010_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
@@ -52,24 +71,7 @@
writel(reg, &wd->wdload);
- return 0;
-}
-
-static int ftwdt010_wdt_reset(struct udevice *dev)
-{
- struct ftwdt010_wdt_priv *priv = dev_get_priv(dev);
- struct ftwdt010_wdt *wd = priv->regs;
-
- /* clear control register */
- writel(0, &wd->wdcr);
-
- /* Write Magic number */
- writel(FTWDT010_WDRESTART_MAGIC, &wd->wdrestart);
-
- /* Enable WDT */
- writel((FTWDT010_WDCR_RST | FTWDT010_WDCR_ENABLE), &wd->wdcr);
-
- return 0;
+ return ftwdt010_wdt_reset(dev);
}
static int ftwdt010_wdt_stop(struct udevice *dev)
diff --git a/env/Kconfig b/env/Kconfig
index 13e3210..54203fa 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -571,7 +571,7 @@
default 0xE0000 if ARCH_ZYNQ
default 0x1E00000 if ARCH_ZYNQMP
default 0x7F40000 if ARCH_VERSAL || ARCH_VERSAL_NET
- default 0 if ARC
+ default 0x0 if ARC
default 0x140000 if ARCH_AT91
default 0x260000 if ARCH_OMAP2PLUS
default 0x1080000 if MICROBLAZE && ENV_IS_IN_SPI_FLASH
@@ -583,7 +583,7 @@
depends on (ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \
ENV_IS_IN_SPI_FLASH) && SYS_REDUNDAND_ENVIRONMENT
default 0x10C0000 if MICROBLAZE
- default 0
+ default 0x0
help
Offset from the start of the device (or partition) of the redundant
environment location.
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index 38e285b..4691612 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -390,7 +390,7 @@
csize);
ret = btrfs_decompress(btrfs_file_extent_compression(leaf, fi),
cbuf, csize, dbuf, dsize);
- if (ret == (u32)-1) {
+ if (ret < 0) {
ret = -EIO;
goto out;
}
@@ -500,7 +500,7 @@
ret = btrfs_decompress(btrfs_file_extent_compression(leaf, fi), cbuf,
csize, dbuf, dsize);
- if (ret == (u32)-1) {
+ if (ret < 0) {
ret = -EIO;
goto out;
}
diff --git a/fs/btrfs/subvolume.c b/fs/btrfs/subvolume.c
index d446e7a..68ca7e4 100644
--- a/fs/btrfs/subvolume.c
+++ b/fs/btrfs/subvolume.c
@@ -199,6 +199,7 @@
ret = PTR_ERR(root);
if (ret == -ENOENT)
goto next;
+ goto out;
}
ret = list_one_subvol(root, result);
if (ret < 0)
diff --git a/fs/cramfs/cramfs.c b/fs/cramfs/cramfs.c
index 6c017ce..abb2de3 100644
--- a/fs/cramfs/cramfs.c
+++ b/fs/cramfs/cramfs.c
@@ -166,8 +166,7 @@
unsigned long ret;
char *link;
if (p && strlen(p)) {
- printf ("unsupported symlink to \
- non-terminal path\n");
+ printf ("unsupported symlink to non-terminal path\n");
return 0;
}
link = cramfs_uncompress_link (begin,
@@ -177,8 +176,7 @@
namelen, namelen, name);
return 0;
} else if (link[0] == '/') {
- printf ("unsupported symlink to \
- absolute path\n");
+ printf ("unsupported symlink to absolute path\n");
free (link);
return 0;
}
diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h
index 433a3c6..1875f37 100644
--- a/fs/erofs/internal.h
+++ b/fs/erofs/internal.h
@@ -105,9 +105,6 @@
u8 xattr_prefix_count;
};
-/* make sure that any user of the erofs headers has at least 64bit off_t type */
-extern int erofs_assert_largefile[sizeof(off_t) - 8];
-
static inline erofs_off_t iloc(erofs_nid_t nid)
{
return erofs_pos(sbi.meta_blkaddr) + (nid << sbi.islotbits);
diff --git a/fs/erofs/super.c b/fs/erofs/super.c
index d339262..d405d48 100644
--- a/fs/erofs/super.c
+++ b/fs/erofs/super.c
@@ -68,14 +68,14 @@
ret = erofs_blk_read(data, 0, erofs_blknr(sizeof(data)));
if (ret < 0) {
- erofs_err("cannot read erofs superblock: %d", ret);
+ erofs_dbg("cannot read erofs superblock: %d", ret);
return -EIO;
}
dsb = (struct erofs_super_block *)(data + EROFS_SUPER_OFFSET);
ret = -EINVAL;
if (le32_to_cpu(dsb->magic) != EROFS_SUPER_MAGIC_V1) {
- erofs_err("cannot find valid erofs superblock");
+ erofs_dbg("cannot find valid erofs superblock");
return ret;
}
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index d1476aa..8ff1fd0 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -110,9 +110,7 @@
info.name[0] = 0;
info.type[0] = 0;
info.bootable = 0;
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- info.uuid[0] = 0;
-#endif
+ disk_partition_clr_uuid(&info);
}
return fat_set_blk_dev(dev_desc, &info);
diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
index e2a9913..8b5d669 100644
--- a/fs/fat/fat_write.c
+++ b/fs/fat/fat_write.c
@@ -132,9 +132,9 @@
return period_location;
if (*dirent.name == ' ')
*dirent.name = '_';
- /* 0xe5 signals a deleted directory entry. Replace it by 0x05. */
- if (*dirent.name == 0xe5)
- *dirent.name = 0x05;
+ /* Substitute character 0xe5 signaling deletetion by character 0x05 */
+ if (*dirent.name == DELETED_FLAG)
+ *dirent.name = aRING;
/* If filename and short name are the same, quit. */
sprintf(buf, "%.*s.%.3s", period_location, dirent.name, dirent.ext);
@@ -690,8 +690,8 @@
static u8 *tmpbuf_cluster;
unsigned int bytesperclust = mydata->clust_size * mydata->sect_size;
__u32 startsect;
- loff_t wsize;
- int clustcount, i, ret;
+ loff_t clustcount, wsize;
+ int i, ret;
*gotsize = 0;
if (!size)
diff --git a/include/abuf.h b/include/abuf.h
index 9badda6..be98ec7 100644
--- a/include/abuf.h
+++ b/include/abuf.h
@@ -91,6 +91,15 @@
bool abuf_realloc(struct abuf *abuf, size_t new_size);
/**
+ * abuf_realloc_inc() - Increment abuf size by a given amount
+ *
+ * @abuf: abuf to adjust
+ * @inc: Size incrmement to use (the buffer size will be increased by this much)
+ * Return: true if OK, false if out of memory
+ */
+bool abuf_realloc_inc(struct abuf *abuf, size_t inc);
+
+/**
* abuf_uninit_move() - Return the allocated contents and uninit the abuf
*
* This returns the abuf data to the caller, allocating it if necessary, so that
diff --git a/include/arm_ffa.h b/include/arm_ffa.h
new file mode 100644
index 0000000..db9b1be
--- /dev/null
+++ b/include/arm_ffa.h
@@ -0,0 +1,213 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#ifndef __ARM_FFA_H
+#define __ARM_FFA_H
+
+#include <linux/printk.h>
+
+/*
+ * This header is public. It can be used by clients to access
+ * data structures and definitions they need
+ */
+
+/*
+ * struct ffa_partition_info - Partition information descriptor
+ * @id: Partition ID
+ * @exec_ctxt: Execution context count
+ * @properties: Partition properties
+ *
+ * Data structure containing information about partitions instantiated in the system
+ * This structure is filled with the data queried by FFA_PARTITION_INFO_GET
+ */
+struct ffa_partition_info {
+ u16 id;
+ u16 exec_ctxt;
+/* partition supports receipt of direct requests */
+#define FFA_PARTITION_DIRECT_RECV BIT(0)
+/* partition can send direct requests. */
+#define FFA_PARTITION_DIRECT_SEND BIT(1)
+/* partition can send and receive indirect messages. */
+#define FFA_PARTITION_INDIRECT_MSG BIT(2)
+ u32 properties;
+};
+
+/*
+ * struct ffa_partition_uuid - 16 bytes UUID transmitted by FFA_PARTITION_INFO_GET
+ * @a1-4: 32-bit words access to the UUID data
+ *
+ */
+struct ffa_partition_uuid {
+ u32 a1; /* w1 */
+ u32 a2; /* w2 */
+ u32 a3; /* w3 */
+ u32 a4; /* w4 */
+};
+
+/**
+ * struct ffa_partition_desc - the secure partition descriptor
+ * @info: partition information
+ * @sp_uuid: the secure partition UUID
+ *
+ * Each partition has its descriptor containing the partitions information and the UUID
+ */
+struct ffa_partition_desc {
+ struct ffa_partition_info info;
+ struct ffa_partition_uuid sp_uuid;
+};
+
+/*
+ * struct ffa_send_direct_data - Data structure hosting the data
+ * used by FFA_MSG_SEND_DIRECT_{REQ,RESP}
+ * @data0-4: Data read/written from/to x3-x7 registers
+ *
+ * Data structure containing the data to be sent by FFA_MSG_SEND_DIRECT_REQ
+ * or read from FFA_MSG_SEND_DIRECT_RESP
+ */
+
+/* For use with FFA_MSG_SEND_DIRECT_{REQ,RESP} which pass data via registers */
+struct ffa_send_direct_data {
+ ulong data0; /* w3/x3 */
+ ulong data1; /* w4/x4 */
+ ulong data2; /* w5/x5 */
+ ulong data3; /* w6/x6 */
+ ulong data4; /* w7/x7 */
+};
+
+struct udevice;
+
+/**
+ * struct ffa_bus_ops - Operations for FF-A
+ * @partition_info_get: callback for the FFA_PARTITION_INFO_GET
+ * @sync_send_receive: callback for the FFA_MSG_SEND_DIRECT_REQ
+ * @rxtx_unmap: callback for the FFA_RXTX_UNMAP
+ *
+ * The data structure providing all the operations supported by the driver.
+ * This structure is EFI runtime resident.
+ */
+struct ffa_bus_ops {
+ int (*partition_info_get)(struct udevice *dev, const char *uuid_str,
+ u32 *sp_count, struct ffa_partition_desc **sp_descs);
+ int (*sync_send_receive)(struct udevice *dev, u16 dst_part_id,
+ struct ffa_send_direct_data *msg,
+ bool is_smc64);
+ int (*rxtx_unmap)(struct udevice *dev);
+};
+
+#define ffa_get_ops(dev) ((struct ffa_bus_ops *)(dev)->driver->ops)
+
+/**
+ * ffa_rxtx_unmap() - FFA_RXTX_UNMAP driver operation
+ * Please see ffa_unmap_rxtx_buffers_hdlr() description for more details.
+ */
+int ffa_rxtx_unmap(struct udevice *dev);
+
+/**
+ * ffa_unmap_rxtx_buffers_hdlr() - FFA_RXTX_UNMAP handler function
+ * @dev: The arm_ffa bus device
+ *
+ * This function implements FFA_RXTX_UNMAP FF-A function
+ * to unmap the RX/TX buffers
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int ffa_unmap_rxtx_buffers_hdlr(struct udevice *dev);
+
+/**
+ * ffa_sync_send_receive() - FFA_MSG_SEND_DIRECT_{REQ,RESP} driver operation
+ * Please see ffa_msg_send_direct_req_hdlr() description for more details.
+ */
+int ffa_sync_send_receive(struct udevice *dev, u16 dst_part_id,
+ struct ffa_send_direct_data *msg, bool is_smc64);
+
+/**
+ * ffa_msg_send_direct_req_hdlr() - FFA_MSG_SEND_DIRECT_{REQ,RESP} handler function
+ * @dev: The arm_ffa bus device
+ * @dst_part_id: destination partition ID
+ * @msg: pointer to the message data preallocated by the client (in/out)
+ * @is_smc64: select 64-bit or 32-bit FF-A ABI
+ *
+ * This function implements FFA_MSG_SEND_DIRECT_{REQ,RESP}
+ * FF-A functions.
+ *
+ * FFA_MSG_SEND_DIRECT_REQ is used to send the data to the secure partition.
+ * The response from the secure partition is handled by reading the
+ * FFA_MSG_SEND_DIRECT_RESP arguments.
+ *
+ * The maximum size of the data that can be exchanged is 40 bytes which is
+ * sizeof(struct ffa_send_direct_data) as defined by the FF-A specification 1.0
+ * in the section relevant to FFA_MSG_SEND_DIRECT_{REQ,RESP}
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int ffa_msg_send_direct_req_hdlr(struct udevice *dev, u16 dst_part_id,
+ struct ffa_send_direct_data *msg, bool is_smc64);
+
+/**
+ * ffa_partition_info_get() - FFA_PARTITION_INFO_GET driver operation
+ * Please see ffa_get_partitions_info_hdlr() description for more details.
+ */
+int ffa_partition_info_get(struct udevice *dev, const char *uuid_str,
+ u32 *sp_count, struct ffa_partition_desc **sp_descs);
+
+/**
+ * ffa_get_partitions_info_hdlr() - FFA_PARTITION_INFO_GET handler function
+ * @uuid_str: pointer to the UUID string
+ * @sp_count: address of the variable containing the number of partitions matching the UUID
+ * The variable is set by the driver
+ * @sp_descs: address of the descriptors of the partitions matching the UUID
+ * The address is set by the driver
+ *
+ * Return the number of partitions and their descriptors matching the UUID
+ *
+ * Query the secure partition data from uc_priv.
+ * If not found, invoke FFA_PARTITION_INFO_GET
+ * FF-A function to query the partition information from secure world.
+ *
+ * A client of the FF-A driver should know the UUID of the service it wants to
+ * access. It should use the UUID to request the FF-A driver to provide the
+ * partition(s) information of the service. The FF-A driver uses
+ * PARTITION_INFO_GET to obtain this information. This is implemented through
+ * ffa_get_partitions_info_hdlr() function.
+ * A new FFA_PARTITION_INFO_GET call is issued (first one performed through
+ * ffa_cache_partitions_info) allowing to retrieve the partition(s) information.
+ * They are not saved (already done). We only update the UUID in the cached area.
+ * This assumes that partitions data does not change in the secure world.
+ * Otherwise u-boot will have an outdated partition data. The benefit of caching
+ * the information in the FF-A driver is to accommodate discovery after
+ * ExitBootServices().
+ *
+ * Return:
+ *
+ * @sp_count: the number of partitions
+ * @sp_descs: address of the partitions descriptors
+ *
+ * On success 0 is returned. Otherwise, failure
+ */
+int ffa_get_partitions_info_hdlr(struct udevice *dev, const char *uuid_str,
+ u32 *sp_count, struct ffa_partition_desc **sp_descs);
+
+struct ffa_priv;
+
+/**
+ * ffa_set_smc_conduit() - Set the SMC conduit
+ * @dev: The FF-A bus device
+ *
+ * Selects the SMC conduit by setting the FF-A ABI invoke function.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int ffa_set_smc_conduit(struct udevice *dev);
+
+#endif
diff --git a/include/arm_ffa_priv.h b/include/arm_ffa_priv.h
new file mode 100644
index 0000000..d564c33
--- /dev/null
+++ b/include/arm_ffa_priv.h
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#ifndef __ARM_FFA_PRV_H
+#define __ARM_FFA_PRV_H
+
+#include <mapmem.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+
+/* This header is exclusively used by the FF-A Uclass and FF-A driver(s) */
+
+/* Arm FF-A driver name */
+#define FFA_DRV_NAME "arm_ffa"
+
+/* The FF-A SMC function definitions */
+
+#if CONFIG_IS_ENABLED(SANDBOX)
+
+/* Providing Arm SMCCC declarations to sandbox */
+
+/**
+ * struct sandbox_smccc_1_2_regs - emulated SMC call arguments or results
+ * @a0-a17 argument values from registers 0 to 17
+ */
+struct sandbox_smccc_1_2_regs {
+ ulong a0;
+ ulong a1;
+ ulong a2;
+ ulong a3;
+ ulong a4;
+ ulong a5;
+ ulong a6;
+ ulong a7;
+ ulong a8;
+ ulong a9;
+ ulong a10;
+ ulong a11;
+ ulong a12;
+ ulong a13;
+ ulong a14;
+ ulong a15;
+ ulong a16;
+ ulong a17;
+};
+
+typedef struct sandbox_smccc_1_2_regs ffa_value_t;
+
+#define ARM_SMCCC_FAST_CALL 1UL
+#define ARM_SMCCC_OWNER_STANDARD 4
+#define ARM_SMCCC_SMC_32 0
+#define ARM_SMCCC_SMC_64 1
+#define ARM_SMCCC_TYPE_SHIFT 31
+#define ARM_SMCCC_CALL_CONV_SHIFT 30
+#define ARM_SMCCC_OWNER_MASK 0x3f
+#define ARM_SMCCC_OWNER_SHIFT 24
+#define ARM_SMCCC_FUNC_MASK 0xffff
+
+#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \
+ (((type) << ARM_SMCCC_TYPE_SHIFT) | \
+ ((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \
+ (((owner) & ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \
+ ((func_num) & ARM_SMCCC_FUNC_MASK))
+
+#else
+/* CONFIG_ARM64 */
+#include <linux/arm-smccc.h>
+typedef struct arm_smccc_1_2_regs ffa_value_t;
+#endif
+
+/* Defining the function pointer type for the function executing the FF-A ABIs */
+typedef void (*invoke_ffa_fn_t)(ffa_value_t args, ffa_value_t *res);
+
+/* FF-A driver version definitions */
+
+#define MAJOR_VERSION_MASK GENMASK(30, 16)
+#define MINOR_VERSION_MASK GENMASK(15, 0)
+#define GET_FFA_MAJOR_VERSION(x) \
+ ((u16)(FIELD_GET(MAJOR_VERSION_MASK, (x))))
+#define GET_FFA_MINOR_VERSION(x) \
+ ((u16)(FIELD_GET(MINOR_VERSION_MASK, (x))))
+#define PACK_VERSION_INFO(major, minor) \
+ (FIELD_PREP(MAJOR_VERSION_MASK, (major)) | \
+ FIELD_PREP(MINOR_VERSION_MASK, (minor)))
+
+#define FFA_MAJOR_VERSION (1)
+#define FFA_MINOR_VERSION (0)
+#define FFA_VERSION_1_0 \
+ PACK_VERSION_INFO(FFA_MAJOR_VERSION, FFA_MINOR_VERSION)
+
+/* Endpoint ID mask (u-boot endpoint ID) */
+
+#define GET_SELF_ENDPOINT_ID_MASK GENMASK(15, 0)
+#define GET_SELF_ENDPOINT_ID(x) \
+ ((u16)(FIELD_GET(GET_SELF_ENDPOINT_ID_MASK, (x))))
+
+#define PREP_SELF_ENDPOINT_ID_MASK GENMASK(31, 16)
+#define PREP_SELF_ENDPOINT_ID(x) \
+ (FIELD_PREP(PREP_SELF_ENDPOINT_ID_MASK, (x)))
+
+/* Partition endpoint ID mask (partition with which u-boot communicates with) */
+
+#define PREP_PART_ENDPOINT_ID_MASK GENMASK(15, 0)
+#define PREP_PART_ENDPOINT_ID(x) \
+ (FIELD_PREP(PREP_PART_ENDPOINT_ID_MASK, (x)))
+
+/* Definitions of the Arm FF-A interfaces supported by the Arm FF-A driver */
+
+#define FFA_SMC(calling_convention, func_num) \
+ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, (calling_convention), \
+ ARM_SMCCC_OWNER_STANDARD, (func_num))
+
+#define FFA_SMC_32(func_num) FFA_SMC(ARM_SMCCC_SMC_32, (func_num))
+#define FFA_SMC_64(func_num) FFA_SMC(ARM_SMCCC_SMC_64, (func_num))
+
+enum ffa_abis {
+ FFA_ERROR = 0x60,
+ FFA_SUCCESS = 0x61,
+ FFA_INTERRUPT = 0x62,
+ FFA_VERSION = 0x63,
+ FFA_FEATURES = 0x64,
+ FFA_RX_RELEASE = 0x65,
+ FFA_RXTX_MAP = 0x66,
+ FFA_RXTX_UNMAP = 0x67,
+ FFA_PARTITION_INFO_GET = 0x68,
+ FFA_ID_GET = 0x69,
+ FFA_RUN = 0x6d,
+ FFA_MSG_SEND_DIRECT_REQ = 0x6f,
+ FFA_MSG_SEND_DIRECT_RESP = 0x70,
+
+ /* To be updated when adding new FFA IDs */
+ FFA_FIRST_ID = FFA_ERROR, /* Lowest number ID */
+ FFA_LAST_ID = FFA_MSG_SEND_DIRECT_RESP, /* Highest number ID */
+};
+
+enum ffa_abi_errcode {
+ NOT_SUPPORTED = 1,
+ INVALID_PARAMETERS,
+ NO_MEMORY,
+ BUSY,
+ INTERRUPTED,
+ DENIED,
+ RETRY,
+ ABORTED,
+ MAX_NUMBER_FFA_ERR
+};
+
+extern int ffa_to_std_errmap[MAX_NUMBER_FFA_ERR];
+
+/* Container structure and helper macros to map between an FF-A error and relevant error log */
+struct ffa_abi_errmap {
+ char *err_str[MAX_NUMBER_FFA_ERR];
+};
+
+#define FFA_ERRMAP_COUNT (FFA_LAST_ID - FFA_FIRST_ID + 1)
+#define FFA_ID_TO_ERRMAP_ID(ffa_id) ((ffa_id) - FFA_FIRST_ID)
+
+/**
+ * enum ffa_rxtx_buf_sizes - minimum sizes supported
+ * for the RX/TX buffers
+ */
+enum ffa_rxtx_buf_sizes {
+ RXTX_4K,
+ RXTX_64K,
+ RXTX_16K
+};
+
+/**
+ * struct ffa_rxtxpair - Hosts the RX/TX buffers virtual addresses
+ * @rxbuf: virtual address of the RX buffer
+ * @txbuf: virtual address of the TX buffer
+ * @rxtx_min_pages: RX/TX buffers minimum size in pages
+ *
+ * Hosts the virtual addresses of the mapped RX/TX buffers
+ * These addresses are used by the FF-A functions that use the RX/TX buffers
+ */
+struct ffa_rxtxpair {
+ void *rxbuf; /* Virtual address returned by memalign */
+ void *txbuf; /* Virtual address returned by memalign */
+ size_t rxtx_min_pages; /* Minimum number of pages in each of the RX/TX buffers */
+};
+
+struct ffa_partition_desc;
+
+/**
+ * struct ffa_partitions - descriptors for all secure partitions
+ * @count: The number of partitions descriptors
+ * @descs The partitions descriptors table
+ *
+ * Contains the partitions descriptors table
+ */
+struct ffa_partitions {
+ u32 count;
+ struct ffa_partition_desc *descs; /* Virtual address */
+};
+
+/**
+ * struct ffa_priv - the driver private data structure
+ *
+ * @fwk_version: FF-A framework version
+ * @emul: FF-A sandbox emulator
+ * @id: u-boot endpoint ID
+ * @partitions: The partitions descriptors structure
+ * @pair: The RX/TX buffers pair
+ *
+ * The device private data structure containing all the
+ * data read from secure world.
+ */
+struct ffa_priv {
+ u32 fwk_version;
+ struct udevice *emul;
+ u16 id;
+ struct ffa_partitions partitions;
+ struct ffa_rxtxpair pair;
+};
+
+/**
+ * ffa_get_version_hdlr() - FFA_VERSION handler function
+ * @dev: The FF-A bus device
+ *
+ * Implement FFA_VERSION FF-A function
+ * to get from the secure world the FF-A framework version
+ * FFA_VERSION is used to discover the FF-A framework.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+int ffa_get_version_hdlr(struct udevice *dev);
+
+/**
+ * invoke_ffa_fn() - SMC wrapper
+ * @args: FF-A ABI arguments to be copied to Xn registers
+ * @res: FF-A ABI return data to be copied from Xn registers
+ *
+ * Calls low level SMC implementation.
+ * This function should be implemented by the user driver.
+ */
+void invoke_ffa_fn(ffa_value_t args, ffa_value_t *res);
+
+#endif
diff --git a/include/asm-generic/bitops/builtin-__ffs.h b/include/asm-generic/bitops/builtin-__ffs.h
new file mode 100644
index 0000000..87024da
--- /dev/null
+++ b/include/asm-generic/bitops/builtin-__ffs.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_GENERIC_BITOPS_BUILTIN___FFS_H_
+#define _ASM_GENERIC_BITOPS_BUILTIN___FFS_H_
+
+/**
+ * __ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static __always_inline unsigned long __ffs(unsigned long word)
+{
+ return __builtin_ctzl(word);
+}
+
+#endif
diff --git a/include/asm-generic/bitops/builtin-__fls.h b/include/asm-generic/bitops/builtin-__fls.h
new file mode 100644
index 0000000..43a5aa9
--- /dev/null
+++ b/include/asm-generic/bitops/builtin-__fls.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_GENERIC_BITOPS_BUILTIN___FLS_H_
+#define _ASM_GENERIC_BITOPS_BUILTIN___FLS_H_
+
+/**
+ * __fls - find last (most-significant) set bit in a long word
+ * @word: the word to search
+ *
+ * Undefined if no set bit exists, so code should check against 0 first.
+ */
+static __always_inline unsigned long __fls(unsigned long word)
+{
+ return (sizeof(word) * 8) - 1 - __builtin_clzl(word);
+}
+
+#endif
diff --git a/include/asm-generic/bitops/builtin-ffs.h b/include/asm-generic/bitops/builtin-ffs.h
new file mode 100644
index 0000000..7b12932
--- /dev/null
+++ b/include/asm-generic/bitops/builtin-ffs.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_GENERIC_BITOPS_BUILTIN_FFS_H_
+#define _ASM_GENERIC_BITOPS_BUILTIN_FFS_H_
+
+/**
+ * ffs - find first bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from ffz (man ffs).
+ */
+#define ffs(x) __builtin_ffs(x)
+
+#endif
diff --git a/include/asm-generic/bitops/builtin-fls.h b/include/asm-generic/bitops/builtin-fls.h
new file mode 100644
index 0000000..c8455cc
--- /dev/null
+++ b/include/asm-generic/bitops/builtin-fls.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_GENERIC_BITOPS_BUILTIN_FLS_H_
+#define _ASM_GENERIC_BITOPS_BUILTIN_FLS_H_
+
+/**
+ * fls - find last (most-significant) bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as ffs.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+static __always_inline int fls(unsigned int x)
+{
+ return x ? sizeof(x) * 8 - __builtin_clz(x) : 0;
+}
+
+#endif
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index c4a7fd2..a21c606 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -414,6 +414,7 @@
* @gpio_base: Base GPIO number for this device. For the first active device
* this will be 0; the numbering for others will follow sequentially so that
* @gpio_base for device 1 will equal the number of GPIOs in device 0.
+ * @claimed: Array of bits indicating which GPIOs in the bank are claimed.
* @name: Array of pointers to the name for each GPIO in this bank. The
* value of the pointer will be NULL if the GPIO has not been claimed.
*/
@@ -421,6 +422,7 @@
const char *bank_name;
unsigned gpio_count;
unsigned gpio_base;
+ u32 *claimed;
char **name;
};
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 267f1db..1e1657a 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -61,8 +61,12 @@
/* Start of U-Boot text region */
extern char __text_start[];
-/* This marks the end of the text region which must be relocated */
-extern char __image_copy_end[];
+/* This marks the text region which must be relocated */
+extern char __image_copy_start[], __image_copy_end[];
+
+extern char __bss_end[];
+extern char __rel_dyn_start[], __rel_dyn_end[];
+extern char _image_binary_end[];
/*
* This is the U-Boot entry point - prior to relocation it should be same
@@ -70,30 +74,4 @@
*/
extern void _start(void);
-/*
- * ARM defines its symbols as char[]. Other arches define them as ulongs.
- */
-#ifdef CONFIG_ARM
-
-extern char __bss_start[];
-extern char __bss_end[];
-extern char __image_copy_start[];
-extern char __image_copy_end[];
-extern char _image_binary_end[];
-extern char __rel_dyn_start[];
-extern char __rel_dyn_end[];
-
-#else /* don't use offsets: */
-
-/* Exports from the Linker Script */
-extern ulong __data_end;
-extern ulong __rel_dyn_start;
-extern ulong __rel_dyn_end;
-extern ulong __bss_end;
-extern ulong _image_binary_end;
-
-extern ulong _TEXT_BASE; /* code start */
-
-#endif
-
#endif /* _ASM_GENERIC_SECTIONS_H_ */
diff --git a/include/blk.h b/include/blk.h
index 2c9c798..b819f97 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -7,6 +7,7 @@
#ifndef BLK_H
#define BLK_H
+#include <bouncebuf.h>
#include <dm/uclass-id.h>
#include <efi.h>
@@ -260,9 +261,25 @@
* @return 0 if OK, -ve on error
*/
int (*select_hwpart)(struct udevice *dev, int hwpart);
-};
-#define blk_get_ops(dev) ((struct blk_ops *)(dev)->driver->ops)
+#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
+ /**
+ * buffer_aligned() - test memory alignment of block operation buffer
+ *
+ * Some devices have limited DMA capabilities and require that the
+ * buffers passed to them fit specific properties. This optional
+ * callback can be used to indicate whether a buffer alignment is
+ * suitable for the device DMA or not, and trigger use of generic
+ * bounce buffer implementation to help use of unsuitable buffers
+ * at the expense of performance degradation.
+ *
+ * @dev: Block device associated with the request
+ * @state: Bounce buffer state
+ * @return 1 if OK, 0 if unaligned
+ */
+ int (*buffer_aligned)(struct udevice *dev, struct bounce_buffer *state);
+#endif /* CONFIG_BOUNCE_BUFFER */
+};
/*
* These functions should take struct udevice instead of struct blk_desc,
diff --git a/include/bootdev.h b/include/bootdev.h
index 1533adf..8482331 100644
--- a/include/bootdev.h
+++ b/include/bootdev.h
@@ -371,7 +371,7 @@
/**
* bootdev_setup_for_dev() - Bind a new bootdev device (deprecated)
*
- * Please use bootdev_setup_sibling_blk() instead since it supports multiple
+ * Please use bootdev_setup_for_sibling_blk() instead since it supports multiple
* (child) block devices for each media device.
*
* Creates a bootdev device as a child of @parent. This should be called from
@@ -386,7 +386,7 @@
int bootdev_setup_for_dev(struct udevice *parent, const char *drv_name);
/**
- * bootdev_setup_for_blk() - Bind a new bootdev device for a blk device
+ * bootdev_setup_for_sibling_blk() - Bind a new bootdev device for a blk device
*
* Creates a bootdev device as a sibling of @blk. This should be called from
* the driver's bind() method or its uclass' post_bind() method, at the same
@@ -398,7 +398,7 @@
* @drv_name: Name of bootdev driver to bind
* Return: 0 if OK, -ve on error
*/
-int bootdev_setup_sibling_blk(struct udevice *blk, const char *drv_name);
+int bootdev_setup_for_sibling_blk(struct udevice *blk, const char *drv_name);
/**
* bootdev_get_sibling_blk() - Locate the block device for a bootdev
@@ -428,8 +428,8 @@
return 0;
}
-static inline int bootdev_setup_sibling_blk(struct udevice *blk,
- const char *drv_name)
+static inline int bootdev_setup_for_sibling_blk(struct udevice *blk,
+ const char *drv_name)
{
return 0;
}
diff --git a/include/bootflow.h b/include/bootflow.h
index 4152577..44d3741 100644
--- a/include/bootflow.h
+++ b/include/bootflow.h
@@ -83,6 +83,7 @@
* @flags: Flags for the bootflow (see enum bootflow_flags_t)
* @cmdline: OS command line, or NULL if not known (allocated)
* @x86_setup: Pointer to x86 setup block inside @buf, NULL if not present
+ * @bootmeth_priv: Private data for the bootmeth
*/
struct bootflow {
struct list_head bm_node;
@@ -107,7 +108,8 @@
ulong fdt_addr;
int flags;
char *cmdline;
- char *x86_setup;
+ void *x86_setup;
+ void *bootmeth_priv;
};
/**
@@ -351,6 +353,17 @@
int bootflow_boot(struct bootflow *bflow);
/**
+ * bootflow_read_all() - Read all bootflow files
+ *
+ * Some bootmeths delay reading of large files until booting is requested. This
+ * causes those files to be read.
+ *
+ * @bflow: Bootflow to read
+ * Return: result of trying to read
+ */
+int bootflow_read_all(struct bootflow *bflow);
+
+/**
* bootflow_run_boot() - Try to boot a bootflow
*
* @iter: Current iteration (or NULL if none). Used to disable a bootmeth if the
diff --git a/include/bootm.h b/include/bootm.h
index 044a479..c3c7336 100644
--- a/include/bootm.h
+++ b/include/bootm.h
@@ -9,6 +9,7 @@
#include <image.h>
+struct boot_params;
struct cmd_tbl;
#define BOOTM_ERR_RESET (-1)
@@ -124,4 +125,50 @@
*/
int bootm_process_cmdline_env(int flags);
+/**
+ * zboot_start() - Boot a zimage
+ *
+ * Boot a zimage, given the component parts
+ *
+ * @addr: Address where the bzImage is moved before booting, either
+ * BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR
+ * @base: Pointer to the boot parameters, typically at address
+ * DEFAULT_SETUP_BASE
+ * @initrd: Address of the initial ramdisk, or 0 if none
+ * @initrd_size: Size of the initial ramdisk, or 0 if none
+ * @cmdline: Command line to use for booting
+ * Return: -EFAULT on error (normally it does not return)
+ */
+int zboot_start(ulong addr, ulong size, ulong initrd, ulong initrd_size,
+ ulong base, char *cmdline);
+
+/*
+ * zimage_get_kernel_version() - Get the version string from a kernel
+ *
+ * @params: boot_params pointer
+ * @kernel_base: base address of kernel
+ * Return: Kernel version as a NUL-terminated string
+ */
+const char *zimage_get_kernel_version(struct boot_params *params,
+ void *kernel_base);
+
+/**
+ * zimage_dump() - Dump the metadata of a zimage
+ *
+ * This shows all available information in a zimage that has been loaded.
+ *
+ * @base_ptr: Pointer to the boot parameters, typically at address
+ * DEFAULT_SETUP_BASE
+ * @show_cmdline: true to show the full command line
+ */
+void zimage_dump(struct boot_params *base_ptr, bool show_cmdline);
+
+/*
+ * bootm_boot_start() - Boot an image at the given address
+ *
+ * @addr: Image address
+ * @cmdline: Command line to set
+ */
+int bootm_boot_start(ulong addr, const char *cmdline);
+
#endif
diff --git a/include/bootmeth.h b/include/bootmeth.h
index c3df970..0fc3610 100644
--- a/include/bootmeth.h
+++ b/include/bootmeth.h
@@ -16,9 +16,12 @@
* enum bootmeth_flags - Flags for bootmeths
*
* @BOOTMETHF_GLOBAL: bootmeth handles bootdev selection automatically
+ * @BOOTMETHF_ANY_PART: bootmeth is willing to check any partition, even if it
+ * has no filesystem
*/
enum bootmeth_flags {
BOOTMETHF_GLOBAL = BIT(0),
+ BOOTMETHF_ANY_PART = BIT(1),
};
/**
@@ -119,7 +122,16 @@
*/
int (*read_file)(struct udevice *dev, struct bootflow *bflow,
const char *file_path, ulong addr, ulong *sizep);
-
+#if CONFIG_IS_ENABLED(BOOTSTD_FULL)
+ /**
+ * readall() - read all files for a bootflow
+ *
+ * @dev: Bootmethod device to boot
+ * @bflow: Bootflow to read
+ * Return: 0 if OK, -EIO on I/O error, other -ve on other error
+ */
+ int (*read_all)(struct udevice *dev, struct bootflow *bflow);
+#endif /* BOOTSTD_FULL */
/**
* boot() - boot a bootflow
*
@@ -224,6 +236,20 @@
const char *file_path, ulong addr, ulong *sizep);
/**
+ * bootmeth_read_all() - read all bootflow files
+ *
+ * Some bootmeths delay reading of large files until booting is requested. This
+ * causes those files to be read.
+ *
+ * @dev: Bootmethod device to use
+ * @bflow: Bootflow to read
+ * Return: does not return on success, since it should boot the
+ * Operating Systemn. Returns -EFAULT if that fails, other -ve on
+ * other error
+ */
+int bootmeth_read_all(struct udevice *dev, struct bootflow *bflow);
+
+/**
* bootmeth_boot() - boot a bootflow
*
* @dev: Bootmethod device to boot
@@ -263,6 +289,19 @@
int bootmeth_set_order(const char *order_str);
/**
+ * bootmeth_setup_fs() - Set up read to read a file
+ *
+ * We must redo the setup before each filesystem operation. This function
+ * handles that, including setting the filesystem type if a block device is not
+ * being used
+ *
+ * @bflow: Information about file to try
+ * @desc: Block descriptor to read from (NULL if not a block device)
+ * Return: 0 if OK, -ve on error
+ */
+int bootmeth_setup_fs(struct bootflow *bflow, struct blk_desc *desc);
+
+/**
* bootmeth_try_file() - See we can access a given file
*
* Check for a file with a given name. If found, the filename is allocated in
diff --git a/include/cedit.h b/include/cedit.h
new file mode 100644
index 0000000..f43cafa
--- /dev/null
+++ b/include/cedit.h
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __CEDIT_H
+#define __CEDIT_H
+
+#include <dm/ofnode_decl.h>
+
+struct abuf;
+struct expo;
+struct scene;
+struct video_priv;
+
+enum {
+ /* size increment for writing FDT */
+ CEDIT_SIZE_INC = 1024,
+};
+
+/* Name of the cedit node in the devicetree */
+#define CEDIT_NODE_NAME "cedit-values"
+
+extern struct expo *cur_exp;
+
+/**
+ * cedit_arange() - Arrange objects in a configuration-editor scene
+ *
+ * @exp: Expo to update
+ * @vid_priv: Private info of the video device
+ * @scene_id: scene ID to arrange
+ * Returns: 0 if OK, -ve on error
+ */
+int cedit_arange(struct expo *exp, struct video_priv *vid_priv, uint scene_id);
+
+/**
+ * cedit_run() - Run a configuration editor
+ *
+ * This accepts input until the user quits with Escape
+ *
+ * @exp: Expo to use
+ * Returns: 0 if OK, -ve on error
+ */
+int cedit_run(struct expo *exp);
+
+/**
+ * cedit_prepare() - Prepare to run a cedit
+ *
+ * Set up the video device, select the first scene and highlight the first item.
+ * This ensures that all menus have a selected item.
+ *
+ * @exp: Expo to use
+ * @vid_privp: Set to private data for the video device
+ * @scnp: Set to the first scene
+ * Return: scene ID of first scene if OK, -ve on error
+ */
+int cedit_prepare(struct expo *exp, struct video_priv **vid_privp,
+ struct scene **scnp);
+
+/**
+ * cedit_write_settings() - Write settings in FDT format
+ *
+ * Sets up an FDT with the settings
+ *
+ * @exp: Expo to write settings from
+ * @buf: Returns abuf containing the settings FDT (inited by this function)
+ * Return: 0 if OK, -ve on error
+ */
+int cedit_write_settings(struct expo *exp, struct abuf *buf);
+
+/**
+ * cedit_read_settings() - Read settings in FDT format
+ *
+ * Read an FDT with the settings
+ *
+ * @exp: Expo to read settings into
+ * @tree: Tree to read from
+ * Return: 0 if OK, -ve on error
+ */
+int cedit_read_settings(struct expo *exp, oftree tree);
+
+/**
+ * cedit_write_settings_env() - Write settings to envrionment variables
+ *
+ * @exp: Expo to write settings from
+ * @verbose: true to print each var as it is set
+ * Return: 0 if OK, -ve on error
+ */
+int cedit_write_settings_env(struct expo *exp, bool verbose);
+
+/*
+ * cedit_read_settings_env() - Read settings from the environment
+ *
+ * @exp: Expo to read settings into
+ * @verbose: true to print each var before it is read
+ */
+int cedit_read_settings_env(struct expo *exp, bool verbose);
+
+/**
+ * cedit_write_settings_cmos() - Write settings to CMOS RAM
+ *
+ * Write settings to the defined places in CMOS RAM
+ *
+ * @exp: Expo to write settings from
+ * @dev: UCLASS_RTC device containing space for this information
+ * Returns 0 if OK, -ve on error
+ * @verbose: true to print a summary at the end
+ */
+int cedit_write_settings_cmos(struct expo *exp, struct udevice *dev,
+ bool verbose);
+
+/**
+ * cedit_read_settings_cmos() - Read settings from CMOS RAM
+ *
+ * Read settings from the defined places in CMO RAM
+ *
+ * @exp: Expo to read settings into
+ * @dev: RTC device to read settings from
+ * @verbose: true to print a summary at the end
+ */
+int cedit_read_settings_cmos(struct expo *exp, struct udevice *dev,
+ bool verbose);
+
+#endif /* __CEDIT_H */
diff --git a/include/clk-uclass.h b/include/clk-uclass.h
index 65ebff9..a22f1a5 100644
--- a/include/clk-uclass.h
+++ b/include/clk-uclass.h
@@ -64,7 +64,7 @@
/**
* request() - Request a translated clock.
- * @clock: The clock struct to request; this has been fille in by
+ * @clock: The clock struct to request; this has been filled in by
* a previoux xxx_xlate() function call, or by the caller
* of clk_request().
*
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 5b47778..504b1f0 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -76,7 +76,7 @@
#include <config_distro_bootcmd.h>
#ifndef CONFIG_SPL_BUILD
-#include <environment/ti/dfu.h>
+#include <env/ti/dfu.h>
#define CFG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index a2f73c4..7ee7b7e 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -64,7 +64,7 @@
#include <config_distro_bootcmd.h>
#ifndef CONFIG_SPL_BUILD
-#include <environment/ti/dfu.h>
+#include <env/ti/dfu.h>
#define CFG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index ba91f2b..06edde6 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -11,7 +11,7 @@
#ifndef __CONFIG_AM57XX_EVM_H
#define __CONFIG_AM57XX_EVM_H
-#include <environment/ti/dfu.h>
+#include <env/ti/dfu.h>
#include <linux/sizes.h>
#define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
diff --git a/include/configs/am62ax_evm.h b/include/configs/am62ax_evm.h
index 3997ce5..57003f1 100644
--- a/include/configs/am62ax_evm.h
+++ b/include/configs/am62ax_evm.h
@@ -9,8 +9,8 @@
#define __CONFIG_AM62AX_EVM_H
#include <linux/sizes.h>
-#include <environment/ti/mmc.h>
-#include <environment/ti/k3_dfu.h>
+#include <env/ti/mmc.h>
+#include <env/ti/k3_dfu.h>
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE1 0x880000000
diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h
index 6b2a6ee..44180dc 100644
--- a/include/configs/am62x_evm.h
+++ b/include/configs/am62x_evm.h
@@ -10,7 +10,7 @@
#define __CONFIG_AM625_EVM_H
#include <config_distro_bootcmd.h>
-#include <environment/ti/mmc.h>
+#include <env/ti/mmc.h>
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE1 0x880000000
diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
index 1e37ab4..062102a 100644
--- a/include/configs/am64x_evm.h
+++ b/include/configs/am64x_evm.h
@@ -11,9 +11,9 @@
#include <linux/sizes.h>
#include <config_distro_bootcmd.h>
-#include <environment/ti/mmc.h>
+#include <env/ti/mmc.h>
#include <asm/arch/am64_hardware.h>
-#include <environment/ti/k3_dfu.h>
+#include <env/ti/k3_dfu.h>
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE1 0x880000000
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index 2fa658d..9e90239 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h
@@ -10,9 +10,9 @@
#define __CONFIG_AM654_EVM_H
#include <linux/sizes.h>
-#include <environment/ti/mmc.h>
-#include <environment/ti/k3_rproc.h>
-#include <environment/ti/k3_dfu.h>
+#include <env/ti/mmc.h>
+#include <env/ti/k3_rproc.h>
+#include <env/ti/k3_dfu.h>
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE1 0x880000000
diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h
index b0df328..9b0f5ce 100644
--- a/include/configs/bayleybay.h
+++ b/include/configs/bayleybay.h
@@ -2,20 +2,3 @@
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*/
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \
- "stdout=serial,vidconsole\0" \
- "stderr=serial,vidconsole\0"
-
-/* Environment configuration */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/cherryhill.h b/include/configs/cherryhill.h
index d6ce70a..a300957 100644
--- a/include/configs/cherryhill.h
+++ b/include/configs/cherryhill.h
@@ -2,16 +2,3 @@
/*
* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
*/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \
- "stdout=vidconsole,serial\0" \
- "stderr=vidconsole,serial\0"
-
-/* Environment configuration */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index b4f49bf..e00c408 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -2,23 +2,3 @@
/*
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*/
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define SPLASH_SETTINGS "splashsource=virtio_fs\0" \
- "splashimage=0x1000000\0"
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
- "stdout=serial,vidconsole\0" \
- "stderr=serial,vidconsole\0"
-
-/* ATA/IDE support */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h
index 31639e4..0406786 100644
--- a/include/configs/cougarcanyon2.h
+++ b/include/configs/cougarcanyon2.h
@@ -2,16 +2,3 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
- "stdout=serial,vga\0" \
- "stderr=serial,vga\0"
-
-/* Environment configuration */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index 387bb88..0c842dd 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -2,20 +2,3 @@
/*
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*/
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
- "stdout=serial,vidconsole\0" \
- "stderr=serial,vidconsole\0"
-
-/* Environment configuration */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 736af88..cef4042 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -143,7 +143,7 @@
"fdtaddr=0xc0600000\0" \
"scriptaddr=0xc0600000\0"
-#include <environment/ti/mmc.h>
+#include <env/ti/mmc.h>
#define CFG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index ef1d5a1..633ec1f 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -11,7 +11,7 @@
#ifndef __CONFIG_DRA7XX_EVM_H
#define __CONFIG_DRA7XX_EVM_H
-#include <environment/ti/dfu.h>
+#include <env/ti/dfu.h>
#define CFG_MAX_MEM_MAPPED 0x80000000
diff --git a/include/configs/edison.h b/include/configs/edison.h
index 455a889..127c2c4 100644
--- a/include/configs/edison.h
+++ b/include/configs/edison.h
@@ -2,14 +2,3 @@
/*
* Copyright (c) 2017 Intel Corp.
*/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/ibmpc.h>
-
-/* Miscellaneous configurable options */
-
-#define CFG_SYS_STACK_SIZE (32 * 1024)
-
-#endif
diff --git a/include/configs/efi-x86_app.h b/include/configs/efi-x86_app.h
index 843ed8b..d582404 100644
--- a/include/configs/efi-x86_app.h
+++ b/include/configs/efi-x86_app.h
@@ -2,14 +2,3 @@
/*
* Copyright (c) 2015 Google, Inc
*/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS "stdin=serial\0" \
- "stdout=vidconsole\0" \
- "stderr=vidconsole\0"
-
-#endif
diff --git a/include/configs/efi-x86_payload.h b/include/configs/efi-x86_payload.h
index c72b067..e00c408 100644
--- a/include/configs/efi-x86_payload.h
+++ b/include/configs/efi-x86_payload.h
@@ -2,20 +2,3 @@
/*
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*/
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
- "stdout=serial,vidconsole\0" \
- "stderr=serial,vidconsole\0"
-
-/* ATA/IDE support */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/endeavoru.h b/include/configs/endeavoru.h
new file mode 100644
index 0000000..46c582e
--- /dev/null
+++ b/include/configs/endeavoru.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2010,2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2022
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra30-common.h"
+
+/* High-level configuration options */
+#define CFG_TEGRA_BOARD_STRING "HTC One X"
+
+#define ENDEAVORU_FLASH_UBOOT \
+ "flash_uboot=echo Preparing RAM;" \
+ "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \
+ "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \
+ "echo Reading BCT;" \
+ "mmc dev 0 1;" \
+ "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \
+ "echo Reading bootloader;" \
+ "if load mmc 0:1 ${ramdisk_addr_r} ${bootloader_file};" \
+ "then echo Calculating bootloader size;" \
+ "size mmc 0:1 ${bootloader_file};" \
+ "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \
+ "echo Writing bootloader to eMMC;" \
+ "mmc dev 0 1;" \
+ "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \
+ "mmc dev 0 2;" \
+ "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \
+ "echo Bootloader written successfully;" \
+ "pause 'Press ANY key to reboot device...'; reset;" \
+ "else echo Reading bootloader failed;" \
+ "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0"
+
+#define ENDEAVORU_BOOTMENU \
+ ENDEAVORU_FLASH_UBOOT \
+ "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \
+ "bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \
+ "bootmenu_2=update bootloader=run flash_uboot\0" \
+ "bootmenu_3=reboot RCM=enterrcm\0" \
+ "bootmenu_4=reboot=reset\0" \
+ "bootmenu_5=power off=poweroff\0" \
+ "bootmenu_delay=-1\0"
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+ "boot_block_size_r=0x200000\0" \
+ "boot_block_size=0x1000\0" \
+ "bootloader_file=u-boot-dtb-tegra.bin\0" \
+ "check_button=gpio input 179; test $? -eq 0\0" \
+ "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \
+ ENDEAVORU_BOOTMENU
+
+/* Board-specific serial config */
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index 0380ac2..9b0f5ce 100644
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h
@@ -2,22 +2,3 @@
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*/
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/x86-common.h>
-
-/* ns16550 UART is memory-mapped in Quark SoC */
-
-#define CFG_STD_DEVICES_SETTINGS "stdin=serial\0" \
- "stdout=serial\0" \
- "stderr=serial\0"
-
-/* Environment configuration */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/grouper.h b/include/configs/grouper.h
new file mode 100644
index 0000000..93304dd
--- /dev/null
+++ b/include/configs/grouper.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra30-common.h"
+
+/* High-level configuration options */
+#define CFG_TEGRA_BOARD_STRING "ASUS Google Nexus 7 (2012)"
+
+#define GROUPER_FLASH_UBOOT \
+ "flash_uboot=echo Preparing RAM;" \
+ "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \
+ "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \
+ "echo Reading BCT;" \
+ "mmc dev 0 1;" \
+ "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \
+ "echo Reading bootloader;" \
+ "if load mmc 0:1 ${ramdisk_addr_r} ${bootloader_file};" \
+ "then echo Calculating bootloader size;" \
+ "size mmc 0:1 ${bootloader_file};" \
+ "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \
+ "echo Writing bootloader to eMMC;" \
+ "mmc dev 0 1;" \
+ "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \
+ "mmc dev 0 2;" \
+ "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \
+ "echo Bootloader written successfully;" \
+ "pause 'Press ANY key to reboot device...'; reset;" \
+ "else echo Reading bootloader failed;" \
+ "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0"
+
+#define GROUPER_BOOTMENU \
+ GROUPER_FLASH_UBOOT \
+ "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \
+ "bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \
+ "bootmenu_2=update bootloader=run flash_uboot\0" \
+ "bootmenu_3=reboot RCM=enterrcm\0" \
+ "bootmenu_4=reboot=reset\0" \
+ "bootmenu_5=power off=poweroff\0" \
+ "bootmenu_delay=-1\0"
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+ "boot_block_size_r=0x200000\0" \
+ "boot_block_size=0x1000\0" \
+ "bootloader_file=u-boot-dtb-tegra.bin\0" \
+ "check_button=gpio input 131; test $? -eq 0;\0" \
+ "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \
+ GROUPER_BOOTMENU
+
+/* Board-specific serial config */
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 842672d..068a2af 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -2,19 +2,3 @@
/*
* Copyright (C) 2015 Google, Inc
*/
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \
- "stdout=vidconsole,serial\0" \
- "stderr=vidconsole,serial\0" \
- "usb_pgood_delay=40\0"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/mt7620.h b/include/configs/mt7620.h
index d5bd492..d69d35f 100644
--- a/include/configs/mt7620.h
+++ b/include/configs/mt7620.h
@@ -10,10 +10,9 @@
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CFG_SYS_INIT_SP_OFFSET 0x400000
+#define CFG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
-
#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* Dummy value */
diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h
index a957494..bf2bc2d 100644
--- a/include/configs/mt7621.h
+++ b/include/configs/mt7621.h
@@ -12,13 +12,11 @@
#define CFG_MAX_MEM_MAPPED 0x1c000000
-#define CFG_SYS_INIT_SP_OFFSET 0x800000
+#define CFG_SYS_INIT_SP_OFFSET 0x800000
/* MMC */
#define MMC_SUPPORTS_TUNING
-/* NAND */
-
/* Serial SPL */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
#define CFG_SYS_NS16550_CLK 50000000
@@ -26,7 +24,7 @@
#endif
/* Serial common */
-#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600 }
/* Dummy value */
diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h
index 6541512..4a05695 100644
--- a/include/configs/mt7622.h
+++ b/include/configs/mt7622.h
@@ -9,14 +9,4 @@
#ifndef __MT7622_H
#define __MT7622_H
-/* Uboot definition */
-#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
-
-/* SPL -> Uboot */
-#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
-/* DRAM */
-#define CFG_SYS_SDRAM_BASE 0x40000000
-
-/* Ethernet */
-
#endif
diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h
index db12377..fca234a 100644
--- a/include/configs/mt7623.h
+++ b/include/configs/mt7623.h
@@ -11,12 +11,6 @@
#include <linux/sizes.h>
-/* Miscellaneous configurable options */
-
-/* Environment */
-
-/* Preloader -> Uboot */
-
/* MMC */
#define MMC_SUPPORTS_TUNING
@@ -32,8 +26,6 @@
"fdt_addr_r=" FDT_HIGH "\0" \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
-/* Ethernet */
-
#ifdef CONFIG_DISTRO_DEFAULTS
#define BOOT_TARGET_DEVICES(func) \
diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h
index 9df2715..0ac376d 100644
--- a/include/configs/mt7628.h
+++ b/include/configs/mt7628.h
@@ -10,7 +10,7 @@
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CFG_SYS_INIT_SP_OFFSET 0x80000
+#define CFG_SYS_INIT_SP_OFFSET 0x80000
/* Serial SPL */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
@@ -19,11 +19,10 @@
#endif
/* Serial common */
-#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600 }
/* SPL */
-
#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* Dummy value */
diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h
index f6ab486..59cdd22 100644
--- a/include/configs/mt7629.h
+++ b/include/configs/mt7629.h
@@ -9,21 +9,10 @@
#ifndef __MT7629_H
#define __MT7629_H
-#include <linux/sizes.h>
-
-/* Miscellaneous configurable options */
-
-/* Environment */
-
+/* SPL */
#define CFG_SYS_UBOOT_BASE (0x30000000 + CONFIG_SPL_PAD_TO)
-/* SPL -> Uboot */
-
-/* UBoot -> Kernel */
-
/* DRAM */
#define CFG_SYS_SDRAM_BASE 0x40000000
-/* Ethernet */
-
#endif
diff --git a/include/configs/mt7981.h b/include/configs/mt7981.h
index 14c885e..a6d647e 100644
--- a/include/configs/mt7981.h
+++ b/include/configs/mt7981.h
@@ -9,13 +9,4 @@
#ifndef __MT7981_H
#define __MT7981_H
-/* Uboot definition */
-#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
-
-/* SPL -> Uboot */
-#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
-
-/* DRAM */
-#define CFG_SYS_SDRAM_BASE 0x40000000
-
#endif
diff --git a/include/configs/mt7986.h b/include/configs/mt7986.h
index 0c41af1..090b4c6 100644
--- a/include/configs/mt7986.h
+++ b/include/configs/mt7986.h
@@ -9,13 +9,4 @@
#ifndef __MT7986_H
#define __MT7986_H
-/* Uboot definition */
-#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
-
-/* SPL -> Uboot */
-#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
-
-/* DRAM */
-#define CFG_SYS_SDRAM_BASE 0x40000000
-
#endif
diff --git a/include/configs/mt7988.h b/include/configs/mt7988.h
new file mode 100644
index 0000000..e63825a
--- /dev/null
+++ b/include/configs/mt7988.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for MediaTek MT7988 SoC
+ *
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#ifndef __MT7988_H
+#define __MT7988_H
+
+#define CFG_MAX_MEM_MAPPED 0xC0000000
+
+#endif
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index adb25a6..f449677 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -67,7 +67,7 @@
#include <config_distro_bootcmd.h>
-#include <environment/ti/mmc.h>
+#include <env/ti/mmc.h>
#define CFG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index af00935..fc2655a 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -135,7 +135,7 @@
"fdtaddr=0xc0600000\0" \
"scriptaddr=0xc0600000\0"
-#include <environment/ti/mmc.h>
+#include <env/ti/mmc.h>
#define CFG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h
index 4e6dc79..8668da6 100644
--- a/include/configs/phycore_am335x_r2.h
+++ b/include/configs/phycore_am335x_r2.h
@@ -59,8 +59,8 @@
func(NAND, nand, 0)
#include <config_distro_bootcmd.h>
-#include <environment/ti/dfu.h>
-#include <environment/ti/mmc.h>
+#include <env/ti/dfu.h>
+#include <env/ti/mmc.h>
#define CFG_EXTRA_ENV_SETTINGS \
DEFAULT_MMC_TI_ARGS \
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index f6d326b..584559c 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -17,24 +17,19 @@
/* Environment options */
+#define CFG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
#define BOOT_TARGET_DEVICES(func) \
- func(QEMU, qemu, na) \
func(VIRTIO, virtio, 0) \
func(SCSI, scsi, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
-#define BOOTENV_DEV_QEMU(devtypeu, devtypel, instance) \
- "bootcmd_qemu=" \
- "if env exists kernel_start; then " \
- "bootm ${kernel_start} - ${fdtcontroladdr};" \
- "fi;\0"
-
-#define BOOTENV_DEV_NAME_QEMU(devtypeu, devtypel, instance) \
- "qemu "
-
#define CFG_EXTRA_ENV_SETTINGS \
+ CFG_STD_DEVICES_SETTINGS \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"kernel_addr_r=0x84000000\0" \
diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h
index 3e52352..9b0f5ce 100644
--- a/include/configs/qemu-x86.h
+++ b/include/configs/qemu-x86.h
@@ -2,26 +2,3 @@
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*/
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \
- "stdout=serial,vidconsole\0" \
- "stderr=serial,vidconsole\0"
-
-/*
- * ATA/SATA support for QEMU x86 targets
- * - Only legacy IDE controller is supported for QEMU '-M pc' target
- * - AHCI controller is supported for QEMU '-M q35' target
- */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/rv1126_common.h b/include/configs/rv1126_common.h
index 1ec1640..a64c0c6 100644
--- a/include/configs/rv1126_common.h
+++ b/include/configs/rv1126_common.h
@@ -24,6 +24,7 @@
"scriptaddr=0x00000000\0" \
"pxefile_addr_r=0x00100000\0" \
"fdt_addr_r=0x08300000\0" \
+ "fdtoverlay_addr_r=0x02000000\0" \
"kernel_addr_r=0x02008000\0" \
"ramdisk_addr_r=0x0a200000\0"
diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h
index f208f5e..2996b37 100644
--- a/include/configs/sifive-unleashed.h
+++ b/include/configs/sifive-unleashed.h
@@ -26,7 +26,7 @@
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
-#include <environment/distro/sf.h>
+#include <env/distro/sf.h>
#define TYPE_GUID_LOADER1 "5B193300-FC78-40CD-8002-E86C45580B47"
#define TYPE_GUID_LOADER2 "2E54B353-1271-4842-806F-E436D6AF6985"
diff --git a/include/configs/slimbootloader.h b/include/configs/slimbootloader.h
index 20b99a1..85f6a96 100644
--- a/include/configs/slimbootloader.h
+++ b/include/configs/slimbootloader.h
@@ -2,38 +2,3 @@
/*
* Copyright (C) 2019 Intel Corporation <www.intel.com>
*/
-
-#ifndef __SLIMBOOTLOADER_CONFIG_H__
-#define __SLIMBOOTLOADER_CONFIG_H__
-
-#include <configs/x86-common.h>
-
-#define CFG_STD_DEVICES_SETTINGS \
- "stdin=serial,i8042-kbd,usbkbd\0" \
- "stdout=serial\0" \
- "stderr=serial\0"
-
-/*
- * Override CFG_EXTRA_ENV_SETTINGS in x86-common.h
- */
-#undef CFG_EXTRA_ENV_SETTINGS
-#define CFG_EXTRA_ENV_SETTINGS \
- CFG_STD_DEVICES_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=0x4000000\0" \
- "ramdiskfile=initrd\0" \
- "bootdev=usb\0" \
- "bootdevnum=0\0" \
- "bootdevpart=0\0" \
- "bootfsload=fatload\0" \
- "bootusb=setenv bootdev usb; boot\0" \
- "bootscsi=setenv bootdev scsi; boot\0" \
- "bootmmc=setenv bootdev mmc; boot\0" \
- "bootargs=console=ttyS0,115200 console=tty0\0"
-
-/*
- * Override CONFIG_BOOTCOMMAND in x86-common.h
- */
-
-#endif /* __SLIMBOOTLOADER_CONFIG_H__ */
diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h
index b45982a..60838cb 100644
--- a/include/configs/stm32mp15_st_common.h
+++ b/include/configs/stm32mp15_st_common.h
@@ -10,7 +10,9 @@
#define STM32MP_BOARD_EXTRA_ENV \
"usb_pgood_delay=2000\0" \
- "console=ttySTM0\0"
+ "console=ttySTM0\0" \
+ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "splashpos=m,m\0"
#include <configs/stm32mp15_common.h>
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index 991ffbb..0d0965e 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -8,18 +8,30 @@
#define __TEGRA_COMMON_POST_H
#if IS_ENABLED(CONFIG_CMD_USB)
-# define BOOT_TARGET_USB(func) func(USB, usb, 0)
+#define BOOT_TARGET_USB(func) func(USB, usb, 0)
#else
-# define BOOT_TARGET_USB(func)
+#define BOOT_TARGET_USB(func)
#endif
+#if CONFIG_IS_ENABLED(CMD_DHCP) && CONFIG_IS_ENABLED(CMD_PXE)
+#define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
+#else
+#define BOOT_TARGET_PXE(func)
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_DHCP)
+#define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
+#else
+#define BOOT_TARGET_DHCP(func)
+#endif
+
#ifndef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
BOOT_TARGET_USB(func) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
+ BOOT_TARGET_PXE(func) \
+ BOOT_TARGET_DHCP(func)
#endif
#include <config_distro_bootcmd.h>
@@ -35,6 +47,12 @@
#define STDIN_KBD_USB ""
#endif
+#ifdef CONFIG_BUTTON_KEYBOARD
+#define STDIN_BTN_KBD ",button-kbd"
+#else
+#define STDIN_BTN_KBD ""
+#endif
+
#ifdef CONFIG_VIDEO
#define STDOUT_VIDEO ",vidconsole"
#else
@@ -48,7 +66,7 @@
#endif
#define TEGRA_DEVICE_SETTINGS \
- "stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB STDOUT_CROS_EC "\0" \
+ "stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB STDOUT_CROS_EC STDIN_BTN_KBD "\0" \
"stdout=serial" STDOUT_VIDEO "\0" \
"stderr=serial" STDOUT_VIDEO "\0" \
""
diff --git a/include/configs/ten64.h b/include/configs/ten64.h
index e86c163..d2bef9b 100644
--- a/include/configs/ten64.h
+++ b/include/configs/ten64.h
@@ -15,15 +15,20 @@
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd"
#define SD_BOOTCOMMAND "run distro_bootcmd"
+#define SD_FIRMWARE_PATH "firmware/traverse/ten64/"
+
#define QSPI_MC_INIT_CMD \
"sf probe 0:0 && sf read 0x80000000 0x300000 0x200000 &&" \
"sf read 0x80200000 0x5C0000 0x40000 &&" \
"fsl_mc start mc 0x80000000 0x80200000 && " \
- "sf read 0x80300000 0x580000 0x40000 && fsl_mc lazyapply DPL 0x80300000\0"
+ "sf read 0x8E000000 0x580000 0x40000 && fsl_mc lazyapply DPL 0x8E000000 && "\
+ "echo 'default DPL loaded'\0"
#define SD_MC_INIT_CMD \
- "mmcinfo; fatload mmc 0 0x80000000 mcfirmware/mc_ls1088a.itb; "\
- "fatload mmc 0 0x80200000 dpaa2config/dpc.0x1D-0x0D.dtb; "\
- "fsl_mc start mc 0x80000000 0x80200000\0"
+ "mmcinfo; fatload mmc 0 0x80000000 " SD_FIRMWARE_PATH "mc_ls1088a.itb; "\
+ "fatload mmc 0 0x80200000 " SD_FIRMWARE_PATH "dpc.0x1D-0x0D.dtb; "\
+ "fsl_mc start mc 0x80000000 0x80200000 && " \
+ "fatload mmc 0 0x8E000000 " SD_FIRMWARE_PATH "eth-dpl-all.dtb && " \
+ "fsl_mc lazyapply DPL 0x8E000000 && echo 'default DPL loaded'\0"
#define BOOT_TARGET_DEVICES(func) \
func(NVME, nvme, 0) \
@@ -34,8 +39,22 @@
func(PXE, pxe, 0)
#include <config_distro_bootcmd.h>
+#define OPENWRT_NAND_BOOTCMD \
+ "bootcmd_openwrt_nand=ubi part ubi${openwrt_active_sys} && "\
+ "ubi read $load_addr kernel && " \
+ "setenv bootargs \"root=/dev/ubiblock0_1 earlycon ubi.mtd=ubi${openwrt_active_sys}\" &&"\
+ "bootm $load_addr#ten64\0"
#undef CFG_EXTRA_ENV_SETTINGS
+#if CONFIG_IS_ENABLED(CMD_BOOTMENU)
+#define DEFAULT_MENU_ENTRIES \
+ "bootmenu_0=Continue standard boot=run bootcmd\0" \
+ "bootmenu_1=Boot into recovery=run bootcmd_recovery\0" \
+ "bootmenu_2=Boot OpenWrt from NAND=run bootcmd_openwrt_nand\0"
+#else
+#define DEFAULT_MENU_ENTRIES ""
+#endif /* CONFIG_IS_ENABLED(CMD_BOOTMENU) */
+
#define CFG_EXTRA_ENV_SETTINGS \
"BOARD=ten64\0" \
"fdt_addr_r=0x90000000\0" \
@@ -43,9 +62,12 @@
"kernel_addr_r=0x81000000\0" \
"load_addr=0xa0000000\0" \
BOOTENV \
+ OPENWRT_NAND_BOOTCMD \
+ "openwrt_active_sys=a\0" \
"load_efi_dtb=mtd read devicetree $fdt_addr_r && fdt addr $fdt_addr_r && " \
"fdt resize && fdt boardsetup\0" \
- "bootcmd_recovery=mtd read recovery 0xa0000000; mtd read dpl 0x80100000 && " \
- "fsl_mc apply DPL 0x80100000 && bootm 0xa0000000#ten64\0"
+ "bootcmd_recovery=mtd read recovery 0xa0000000; " \
+ "setenv bootargs \"earlycon root=/dev/ram0 ramdisk_size=0x3000000\" && bootm 0xa0000000#ten64\0" \
+ DEFAULT_MENU_ENTRIES
#endif /* __TEN64_H */
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index 9e312ac..c4f116a 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -56,7 +56,7 @@
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
-#include <environment/ti/mmc.h>
+#include <env/ti/mmc.h>
#define CFG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 74a39c4..4e5aa74 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -39,8 +39,8 @@
#define DFUARGS
#endif
-#include <environment/ti/mmc.h>
-#include <environment/ti/nand.h>
+#include <env/ti/mmc.h>
+#include <env/ti/nand.h>
#ifndef CONSOLEDEV
#define CONSOLEDEV "ttyS2"
diff --git a/include/configs/transformer-common.h b/include/configs/transformer-common.h
new file mode 100644
index 0000000..dcdda1e
--- /dev/null
+++ b/include/configs/transformer-common.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022, Svyatoslav Ryhel <clamor95@gmail.com>.
+ */
+
+#ifndef __TRANSFORMER_COMMON_H
+#define __TRANSFORMER_COMMON_H
+
+/* High-level configuration options */
+#define CFG_TEGRA_BOARD_STRING "ASUS Transformer"
+
+#define TRANSFORMER_FLASH_UBOOT \
+ "flash_uboot=echo Preparing RAM;" \
+ "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \
+ "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \
+ "echo Reading BCT;" \
+ "mmc dev 0 1;" \
+ "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \
+ "echo Reading bootloader;" \
+ "if load mmc 1:1 ${ramdisk_addr_r} ${bootloader_file};" \
+ "then echo Calculating bootloader size;" \
+ "size mmc 1:1 ${bootloader_file};" \
+ "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \
+ "echo Writing bootloader to eMMC;" \
+ "mmc dev 0 1;" \
+ "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \
+ "mmc dev 0 2;" \
+ "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \
+ "echo Bootloader written successfully;" \
+ "pause 'Press ANY key to reboot device...'; reset;" \
+ "else echo Reading bootloader failed;" \
+ "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0"
+
+#define TRANSFORMER_FLASH_SPI \
+ "update_spi=sf probe 0:1;" \
+ "echo Dumping current SPI flash content ...;" \
+ "sf read ${kernel_addr_r} 0x0 ${spi_size};" \
+ "if fatwrite mmc 1:1 ${kernel_addr_r} spi-flash-backup.bin ${spi_size};" \
+ "then echo SPI flash content was successfully written into spi-flash-backup.bin;" \
+ "echo Reading SPI flash binary;" \
+ "if load mmc 1:1 ${kernel_addr_r} repart-block.bin;" \
+ "then echo Writing bootloader into SPI flash;" \
+ "sf probe 0:1;" \
+ "sf update ${kernel_addr_r} 0x0 ${spi_size};" \
+ "poweroff;" \
+ "else echo Preparing RAM;" \
+ "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \
+ "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \
+ "echo Reading BCT;" \
+ "sf read ${kernel_addr_r} 0x0 ${boot_block_size_r};" \
+ "echo Reading bootloader;" \
+ "if load mmc 1:1 ${ramdisk_addr_r} ${bootloader_file};" \
+ "then echo Calculating bootloader size;" \
+ "size mmc 1:1 ${bootloader_file};" \
+ "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \
+ "echo Writing bootloader into SPI flash;" \
+ "sf probe 0:1;" \
+ "sf update ${kernel_addr_r} 0x0 ${boot_block_size_r};" \
+ "sf update ${ramdisk_addr_r} ${boot_block_size_r} ${boot_block_size_r};" \
+ "echo Bootloader written successfully; poweroff;" \
+ "else echo Reading bootloader failed;" \
+ "poweroff; fi;" \
+ "fi;" \
+ "else echo SPI flash backup FAILED! Aborting ...;" \
+ "poweroff; fi\0"
+
+#define TRANSFORMER_REFRESH_USB \
+ "refresh_usb=usb start; usb reset; usb tree; usb info;" \
+ "pause 'Press ANY key to return to bootmenu...'; bootmenu\0"
+
+#define TRANSFORMER_BOOTMENU \
+ TRANSFORMER_FLASH_UBOOT \
+ TRANSFORMER_FLASH_SPI \
+ TRANSFORMER_REFRESH_USB \
+ "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \
+ "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \
+ "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \
+ "bootmenu_3=update bootloader=run flash_uboot\0" \
+ "bootmenu_4=refresh USB=run refresh_usb\0" \
+ "bootmenu_5=reboot RCM=enterrcm\0" \
+ "bootmenu_6=reboot=reset\0" \
+ "bootmenu_7=power off=poweroff\0" \
+ "bootmenu_delay=-1\0"
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+ "spi_size=0x400000\0" \
+ "boot_block_size_r=0x200000\0" \
+ "boot_block_size=0x1000\0" \
+ "check_button=gpio input ${gpio_button}; test $? -eq 0;\0" \
+ "bootloader_file=u-boot-dtb-tegra.bin\0" \
+ "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \
+ TRANSFORMER_BOOTMENU
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/transformer-t30.h b/include/configs/transformer-t30.h
new file mode 100644
index 0000000..d2a16f12
--- /dev/null
+++ b/include/configs/transformer-t30.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2010,2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2022
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra30-common.h"
+#include "transformer-common.h"
+
+/* Board-specific serial config */
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/verdin-am62.h b/include/configs/verdin-am62.h
new file mode 100644
index 0000000..7990ea8
--- /dev/null
+++ b/include/configs/verdin-am62.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Configuration header file for Verdin AM62 SoM
+ *
+ * Copyright 2023 Toradex - https://www.toradex.com/
+ */
+
+#ifndef __VERDIN_AM62_H
+#define __VERDIN_AM62_H
+
+#define RAMDISK_ADDR_R 0x90300000
+#define SCRIPTADDR 0x90280000
+
+/* DDR Configuration */
+#define CFG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE1 0x880000000
+#define CFG_SYS_SDRAM_SIZE SZ_2G /* Maximum supported size */
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "fdt_addr_r=0x90200000\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "kernel_comp_addr_r=0x80200000\0" \
+ "kernel_comp_size=0x08000000\0" \
+ "ramdisk_addr_r=" __stringify(RAMDISK_ADDR_R) "\0" \
+ "scriptaddr=" __stringify(SCRIPTADDR) "\0"
+
+#if CONFIG_TARGET_VERDIN_AM62_A53
+/* Enable Distro Boot */
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#else /* CONFIG_TARGET_VERDIN_AM62_A53 */
+#define BOOTENV \
+ ""
+#endif /* CONFIG_TARGET_VERDIN_AM62_A53 */
+
+/* Incorporate settings into the U-Boot environment */
+#define CFG_EXTRA_ENV_SETTINGS \
+ BOOTENV \
+ MEM_LAYOUT_ENV_SETTINGS \
+ "boot_scripts=boot.scr\0" \
+ "boot_script_dhcp=boot.scr\0" \
+ "console=ttyS2\0" \
+ "fdt_board=dev\0" \
+ "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \
+ "consoleblank=0 earlycon=ns16550a,mmio32,0x02800000\0" \
+ "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \
+ "if test \"$confirm\" = \"y\"; then " \
+ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
+ "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \
+ "${blkcnt}; fi\0"
+
+#endif /* __VERDIN_AM62_H */
diff --git a/include/configs/x3-t30.h b/include/configs/x3-t30.h
new file mode 100644
index 0000000..d29ea70
--- /dev/null
+++ b/include/configs/x3-t30.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2010,2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2022
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra30-common.h"
+
+#define CFG_TEGRA_BOARD_STRING "LG X3 Board"
+
+#ifdef CONFIG_DEVICE_P880
+/* High-level configuration options */
+#undef CFG_TEGRA_BOARD_STRING
+#define CFG_TEGRA_BOARD_STRING "LG Optimus 4X HD"
+#endif
+
+#ifdef CONFIG_DEVICE_P895
+/* High-level configuration options */
+#undef CFG_TEGRA_BOARD_STRING
+#define CFG_TEGRA_BOARD_STRING "LG Optimus Vu"
+#endif
+
+#define X3_FLASH_UBOOT \
+ "flash_uboot=echo Preparing RAM;" \
+ "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \
+ "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \
+ "echo Reading BCT;" \
+ "mmc dev 0 1;" \
+ "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \
+ "echo Reading bootloader;" \
+ "if load mmc 0:1 ${ramdisk_addr_r} ${bootloader_file};" \
+ "then echo Calculating bootloader size;" \
+ "size mmc 0:1 ${bootloader_file};" \
+ "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \
+ "echo Writing bootloader to eMMC;" \
+ "mmc dev 0 1;" \
+ "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \
+ "mmc dev 0 2;" \
+ "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \
+ "echo Bootloader written successfully;" \
+ "pause 'Press ANY key to reboot device...'; reset;" \
+ "else echo Reading bootloader failed;" \
+ "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0"
+
+#define X3_BOOTMENU \
+ X3_FLASH_UBOOT \
+ "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \
+ "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \
+ "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \
+ "bootmenu_3=update bootloader=run flash_uboot\0" \
+ "bootmenu_4=reboot RCM=enterrcm\0" \
+ "bootmenu_5=reboot=reset\0" \
+ "bootmenu_6=power off=poweroff\0" \
+ "bootmenu_delay=-1\0"
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+ "boot_block_size_r=0x200000\0" \
+ "boot_block_size=0x1000\0" \
+ "bootloader_file=u-boot-dtb-tegra.bin\0" \
+ "check_button=gpio input 116; test $? -eq 0\0" \
+ "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \
+ X3_BOOTMENU
+
+/* Board-specific serial config */
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index c1c5a09..8bd0716 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -5,22 +5,10 @@
* Graeme Russ, graeme.russ@gmail.com.
*/
-#include <asm/ibmpc.h>
-
#ifndef __CONFIG_X86_COMMON_H
#define __CONFIG_X86_COMMON_H
/*-----------------------------------------------------------------------
- * CPU Features
- */
-
-#define CFG_SYS_STACK_SIZE (32 * 1024)
-
-/*-----------------------------------------------------------------------
- * Environment configuration
- */
-
-/*-----------------------------------------------------------------------
* USB configuration
*/
@@ -32,18 +20,11 @@
#define CFG_OTHBOOTARGS "othbootargs=acpi=off\0"
#endif
-#if defined(CONFIG_DISTRO_DEFAULTS)
-#define DISTRO_BOOTENV BOOTENV
-#else
-#define DISTRO_BOOTENV
-#endif
-
#ifndef SPLASH_SETTINGS
#define SPLASH_SETTINGS
#endif
#define CFG_EXTRA_ENV_SETTINGS \
- DISTRO_BOOTENV \
CFG_STD_DEVICES_SETTINGS \
SPLASH_SETTINGS \
"pciconfighost=1\0" \
diff --git a/include/dm/device.h b/include/dm/device.h
index b86bf90..e54cb6b 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -367,7 +367,7 @@
* @ops: Driver-specific operations. This is typically a list of function
* pointers defined by the driver, to implement driver functions required by
* the uclass.
- * @flags: driver flags - see `DM_FLAGS_...`
+ * @flags: driver flags - see `DM_FLAG_...`
* @acpi_ops: Advanced Configuration and Power Interface (ACPI) operations,
* allowing the device to add things to the ACPI tables passed to Linux
*/
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 307ad69..0432c95 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -4,6 +4,11 @@
*
* (C) Copyright 2012
* Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
*/
#ifndef _DM_UCLASS_ID_H
@@ -57,6 +62,8 @@
UCLASS_ETH, /* Ethernet device */
UCLASS_ETH_PHY, /* Ethernet PHY device */
UCLASS_EXTCON, /* External Connector Class */
+ UCLASS_FFA, /* Arm Firmware Framework for Armv8-A */
+ UCLASS_FFA_EMUL, /* sandbox FF-A device emulator */
UCLASS_FIRMWARE, /* Firmware */
UCLASS_FPGA, /* FPGA device */
UCLASS_FUZZING_ENGINE, /* Fuzzing engine */
diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h
new file mode 100644
index 0000000..5c21bf6
--- /dev/null
+++ b/include/dt-bindings/clock/mt7988-clk.h
@@ -0,0 +1,349 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
+ *
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7988_H
+#define _DT_BINDINGS_CLK_MT7988_H
+
+/* INFRACFG */
+/* mtk_fixed_factor */
+#define CK_INFRA_CK_F26M 0
+#define CK_INFRA_PWM_O 1
+#define CK_INFRA_PCIE_OCC_P0 2
+#define CK_INFRA_PCIE_OCC_P1 3
+#define CK_INFRA_PCIE_OCC_P2 4
+#define CK_INFRA_PCIE_OCC_P3 5
+#define CK_INFRA_133M_HCK 6
+#define CK_INFRA_133M_PHCK 7
+#define CK_INFRA_66M_PHCK 8
+#define CK_INFRA_FAUD_L_O 9
+#define CK_INFRA_FAUD_AUD_O 10
+#define CK_INFRA_FAUD_EG2_O 11
+#define CK_INFRA_I2C_O 12
+#define CK_INFRA_UART_O0 13
+#define CK_INFRA_UART_O1 14
+#define CK_INFRA_UART_O2 15
+#define CK_INFRA_NFI_O 16
+#define CK_INFRA_SPINFI_O 17
+#define CK_INFRA_SPI0_O 18
+#define CK_INFRA_SPI1_O 19
+#define CK_INFRA_LB_MUX_FRTC 20
+#define CK_INFRA_FRTC 21
+#define CK_INFRA_FMSDC400_O 22
+#define CK_INFRA_FMSDC2_HCK_OCC 23
+#define CK_INFRA_PERI_133M 24
+#define CK_INFRA_USB_O 25
+#define CK_INFRA_USB_O_P1 26
+#define CK_INFRA_USB_FRMCNT_O 27
+#define CK_INFRA_USB_FRMCNT_O_P1 28
+#define CK_INFRA_USB_XHCI_O 29
+#define CK_INFRA_USB_XHCI_O_P1 30
+#define CK_INFRA_USB_PIPE_O 31
+#define CK_INFRA_USB_PIPE_O_P1 32
+#define CK_INFRA_USB_UTMI_O 33
+#define CK_INFRA_USB_UTMI_O_P1 34
+#define CK_INFRA_PCIE_PIPE_OCC_P0 35
+#define CK_INFRA_PCIE_PIPE_OCC_P1 36
+#define CK_INFRA_PCIE_PIPE_OCC_P2 37
+#define CK_INFRA_PCIE_PIPE_OCC_P3 38
+#define CK_INFRA_F26M_O0 39
+#define CK_INFRA_F26M_O1 40
+#define CK_INFRA_133M_MCK 41
+#define CK_INFRA_66M_MCK 42
+#define CK_INFRA_PERI_66M_O 43
+#define CK_INFRA_USB_SYS_O 44
+#define CK_INFRA_USB_SYS_O_P1 45
+
+/* INFRACFG_AO */
+#define GATE_OFFSET 65
+/* mtk_mux */
+#define CK_INFRA_MUX_UART0_SEL 46 /* Linux CLK ID (0) */
+#define CK_INFRA_MUX_UART1_SEL 47 /* Linux CLK ID (1) */
+#define CK_INFRA_MUX_UART2_SEL 48 /* Linux CLK ID (2) */
+#define CK_INFRA_MUX_SPI0_SEL 49 /* Linux CLK ID (3) */
+#define CK_INFRA_MUX_SPI1_SEL 50 /* Linux CLK ID (4) */
+#define CK_INFRA_MUX_SPI2_SEL 51 /* Linux CLK ID (5) */
+#define CK_INFRA_PWM_SEL 52 /* Linux CLK ID (6) */
+#define CK_INFRA_PWM_CK1_SEL 53 /* Linux CLK ID (7) */
+#define CK_INFRA_PWM_CK2_SEL 54 /* Linux CLK ID (8) */
+#define CK_INFRA_PWM_CK3_SEL 55 /* Linux CLK ID (9) */
+#define CK_INFRA_PWM_CK4_SEL 56 /* Linux CLK ID (10) */
+#define CK_INFRA_PWM_CK5_SEL 57 /* Linux CLK ID (11) */
+#define CK_INFRA_PWM_CK6_SEL 58 /* Linux CLK ID (12) */
+#define CK_INFRA_PWM_CK7_SEL 59 /* Linux CLK ID (13) */
+#define CK_INFRA_PWM_CK8_SEL 60 /* Linux CLK ID (14) */
+#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 61 /* Linux CLK ID (15) */
+#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 62 /* Linux CLK ID (16) */
+#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 63 /* Linux CLK ID (17) */
+#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 64 /* Linux CLK ID (18) */
+/* mtk_gate */
+#define CK_INFRA_66M_GPT_BCK (65 - GATE_OFFSET) /* Linux CLK ID (19) */
+#define CK_INFRA_66M_PWM_HCK (66 - GATE_OFFSET) /* Linux CLK ID (20) */
+#define CK_INFRA_66M_PWM_BCK (67 - GATE_OFFSET) /* Linux CLK ID (21) */
+#define CK_INFRA_66M_PWM_CK1 (68 - GATE_OFFSET) /* Linux CLK ID (22) */
+#define CK_INFRA_66M_PWM_CK2 (69 - GATE_OFFSET) /* Linux CLK ID (23) */
+#define CK_INFRA_66M_PWM_CK3 (70 - GATE_OFFSET) /* Linux CLK ID (24) */
+#define CK_INFRA_66M_PWM_CK4 (71 - GATE_OFFSET) /* Linux CLK ID (25) */
+#define CK_INFRA_66M_PWM_CK5 (72 - GATE_OFFSET) /* Linux CLK ID (26) */
+#define CK_INFRA_66M_PWM_CK6 (73 - GATE_OFFSET) /* Linux CLK ID (27) */
+#define CK_INFRA_66M_PWM_CK7 (74 - GATE_OFFSET) /* Linux CLK ID (28) */
+#define CK_INFRA_66M_PWM_CK8 (75 - GATE_OFFSET) /* Linux CLK ID (29) */
+#define CK_INFRA_133M_CQDMA_BCK (76 - GATE_OFFSET) /* Linux CLK ID (30) */
+#define CK_INFRA_66M_AUD_SLV_BCK (77 - GATE_OFFSET) /* Linux CLK ID (31) */
+#define CK_INFRA_AUD_26M (78 - GATE_OFFSET) /* Linux CLK ID (32) */
+#define CK_INFRA_AUD_L (79 - GATE_OFFSET) /* Linux CLK ID (33) */
+#define CK_INFRA_AUD_AUD (80 - GATE_OFFSET) /* Linux CLK ID (34) */
+#define CK_INFRA_AUD_EG2 (81 - GATE_OFFSET) /* Linux CLK ID (35) */
+#define CK_INFRA_DRAMC_F26M (82 - GATE_OFFSET) /* Linux CLK ID (36) */
+#define CK_INFRA_133M_DBG_ACKM (83 - GATE_OFFSET) /* Linux CLK ID (37) */
+#define CK_INFRA_66M_AP_DMA_BCK (84 - GATE_OFFSET) /* Linux CLK ID (38) */
+#define CK_INFRA_66M_SEJ_BCK (85 - GATE_OFFSET) /* Linux CLK ID (39) */
+#define CK_INFRA_PRE_CK_SEJ_F13M (86 - GATE_OFFSET) /* Linux CLK ID (40) */
+#define CK_INFRA_66M_TRNG (87 - GATE_OFFSET) /* Linux CLK ID (41) */
+#define CK_INFRA_26M_THERM_SYSTEM (88 - GATE_OFFSET) /* Linux CLK ID (42) */
+#define CK_INFRA_I2C_BCK (89 - GATE_OFFSET) /* Linux CLK ID (43) */
+#define CK_INFRA_66M_UART0_PCK (90 - GATE_OFFSET) /* Linux CLK ID (44) */
+#define CK_INFRA_66M_UART1_PCK (91 - GATE_OFFSET) /* Linux CLK ID (45) */
+#define CK_INFRA_66M_UART2_PCK (92 - GATE_OFFSET) /* Linux CLK ID (46) */
+#define CK_INFRA_52M_UART0_CK (93 - GATE_OFFSET) /* Linux CLK ID (47) */
+#define CK_INFRA_52M_UART1_CK (94 - GATE_OFFSET) /* Linux CLK ID (48) */
+#define CK_INFRA_52M_UART2_CK (95 - GATE_OFFSET) /* Linux CLK ID (49) */
+#define CK_INFRA_NFI (96 - GATE_OFFSET) /* Linux CLK ID (50) */
+#define CK_INFRA_SPINFI (97 - GATE_OFFSET) /* Linux CLK ID (51) */
+#define CK_INFRA_66M_NFI_HCK (98 - GATE_OFFSET) /* Linux CLK ID (52) */
+#define CK_INFRA_104M_SPI0 (99 - GATE_OFFSET) /* Linux CLK ID (53) */
+#define CK_INFRA_104M_SPI1 (100 - GATE_OFFSET) /* Linux CLK ID (54) */
+#define CK_INFRA_104M_SPI2_BCK (101 - GATE_OFFSET) /* Linux CLK ID (55) */
+#define CK_INFRA_66M_SPI0_HCK (102 - GATE_OFFSET) /* Linux CLK ID (56) */
+#define CK_INFRA_66M_SPI1_HCK (103 - GATE_OFFSET) /* Linux CLK ID (57) */
+#define CK_INFRA_66M_SPI2_HCK (104 - GATE_OFFSET) /* Linux CLK ID (58) */
+#define CK_INFRA_66M_FLASHIF_AXI (105 - GATE_OFFSET) /* Linux CLK ID (59) */
+#define CK_INFRA_RTC (106 - GATE_OFFSET) /* Linux CLK ID (60) */
+#define CK_INFRA_26M_ADC_BCK (107 - GATE_OFFSET) /* Linux CLK ID (61) */
+#define CK_INFRA_RC_ADC (108 - GATE_OFFSET) /* Linux CLK ID (62) */
+#define CK_INFRA_MSDC400 (109 - GATE_OFFSET) /* Linux CLK ID (63) */
+#define CK_INFRA_MSDC2_HCK (110 - GATE_OFFSET) /* Linux CLK ID (64) */
+#define CK_INFRA_133M_MSDC_0_HCK (111 - GATE_OFFSET) /* Linux CLK ID (65) */
+#define CK_INFRA_66M_MSDC_0_HCK (112 - GATE_OFFSET) /* Linux CLK ID (66) */
+#define CK_INFRA_133M_CPUM_BCK (113 - GATE_OFFSET) /* Linux CLK ID (67) */
+#define CK_INFRA_BIST2FPC (114 - GATE_OFFSET) /* Linux CLK ID (68) */
+#define CK_INFRA_I2C_X16W_MCK_CK_P1 (115 - GATE_OFFSET) /* Linux CLK ID (69) */
+#define CK_INFRA_I2C_X16W_PCK_CK_P1 (116 - GATE_OFFSET) /* Linux CLK ID (70) */
+#define CK_INFRA_133M_USB_HCK (117 - GATE_OFFSET) /* Linux CLK ID (71) */
+#define CK_INFRA_133M_USB_HCK_CK_P1 (118 - GATE_OFFSET) /* Linux CLK ID (72) */
+#define CK_INFRA_66M_USB_HCK (119 - GATE_OFFSET) /* Linux CLK ID (73) */
+#define CK_INFRA_66M_USB_HCK_CK_P1 (120 - GATE_OFFSET) /* Linux CLK ID (74) */
+#define CK_INFRA_USB_SYS (121 - GATE_OFFSET) /* Linux CLK ID (75) */
+#define CK_INFRA_USB_SYS_CK_P1 (122 - GATE_OFFSET) /* Linux CLK ID (76) */
+#define CK_INFRA_USB_REF (123 - GATE_OFFSET) /* Linux CLK ID (77) */
+#define CK_INFRA_USB_CK_P1 (124 - GATE_OFFSET) /* Linux CLK ID (78) */
+#define CK_INFRA_USB_FRMCNT (125 - GATE_OFFSET) /* Linux CLK ID (79) */
+#define CK_INFRA_USB_FRMCNT_CK_P1 (126 - GATE_OFFSET) /* Linux CLK ID (80) */
+#define CK_INFRA_USB_PIPE (127 - GATE_OFFSET) /* Linux CLK ID (81) */
+#define CK_INFRA_USB_PIPE_CK_P1 (128 - GATE_OFFSET) /* Linux CLK ID (82) */
+#define CK_INFRA_USB_UTMI (129 - GATE_OFFSET) /* Linux CLK ID (83) */
+#define CK_INFRA_USB_UTMI_CK_P1 (130 - GATE_OFFSET) /* Linux CLK ID (84) */
+#define CK_INFRA_USB_XHCI (131 - GATE_OFFSET) /* Linux CLK ID (85) */
+#define CK_INFRA_USB_XHCI_CK_P1 (132 - GATE_OFFSET) /* Linux CLK ID (86) */
+#define CK_INFRA_PCIE_GFMUX_TL_P0 (133 - GATE_OFFSET) /* Linux CLK ID (87) */
+#define CK_INFRA_PCIE_GFMUX_TL_P1 (134 - GATE_OFFSET) /* Linux CLK ID (88) */
+#define CK_INFRA_PCIE_GFMUX_TL_P2 (135 - GATE_OFFSET) /* Linux CLK ID (89) */
+#define CK_INFRA_PCIE_GFMUX_TL_P3 (136 - GATE_OFFSET) /* Linux CLK ID (90) */
+#define CK_INFRA_PCIE_PIPE_P0 (137 - GATE_OFFSET) /* Linux CLK ID (91) */
+#define CK_INFRA_PCIE_PIPE_P1 (138 - GATE_OFFSET) /* Linux CLK ID (92) */
+#define CK_INFRA_PCIE_PIPE_P2 (139 - GATE_OFFSET) /* Linux CLK ID (93) */
+#define CK_INFRA_PCIE_PIPE_P3 (140 - GATE_OFFSET) /* Linux CLK ID (94) */
+#define CK_INFRA_133M_PCIE_CK_P0 (141 - GATE_OFFSET) /* Linux CLK ID (95) */
+#define CK_INFRA_133M_PCIE_CK_P1 (142 - GATE_OFFSET) /* Linux CLK ID (96) */
+#define CK_INFRA_133M_PCIE_CK_P2 (143 - GATE_OFFSET) /* Linux CLK ID (97) */
+#define CK_INFRA_133M_PCIE_CK_P3 (144 - GATE_OFFSET) /* Linux CLK ID (98) */
+#define CK_INFRA_PCIE_PERI_26M_CK_P0 (145 - GATE_OFFSET) /* Linux CLK ID (99) */
+#define CK_INFRA_PCIE_PERI_26M_CK_P1 \
+ (146 - GATE_OFFSET) /* Linux CLK ID (100) */
+#define CK_INFRA_PCIE_PERI_26M_CK_P2 \
+ (147 - GATE_OFFSET) /* Linux CLK ID (101) */
+#define CK_INFRA_PCIE_PERI_26M_CK_P3 \
+ (148 - GATE_OFFSET) /* Linux CLK ID (102) */
+
+/* TOPCKGEN */
+/* mtk_fixed_factor */
+#define CK_TOP_CB_CKSQ_40M 0 /* Linux CLK ID (74) */
+#define CK_TOP_CB_M_416M 1 /* Linux CLK ID (75) */
+#define CK_TOP_CB_M_D2 2 /* Linux CLK ID (76) */
+#define CK_TOP_M_D3_D2 3 /* Linux CLK ID (77) */
+#define CK_TOP_CB_M_D4 4 /* Linux CLK ID (78) */
+#define CK_TOP_CB_M_D8 5 /* Linux CLK ID (79) */
+#define CK_TOP_M_D8_D2 6 /* Linux CLK ID (80) */
+#define CK_TOP_CB_MM_720M 7 /* Linux CLK ID (81) */
+#define CK_TOP_CB_MM_D2 8 /* Linux CLK ID (82) */
+#define CK_TOP_CB_MM_D3_D5 9 /* Linux CLK ID (83) */
+#define CK_TOP_CB_MM_D4 10 /* Linux CLK ID (84) */
+#define CK_TOP_MM_D6_D2 11 /* Linux CLK ID (85) */
+#define CK_TOP_CB_MM_D8 12 /* Linux CLK ID (86) */
+#define CK_TOP_CB_APLL2_196M 13 /* Linux CLK ID (87) */
+#define CK_TOP_CB_APLL2_D4 14 /* Linux CLK ID (88) */
+#define CK_TOP_CB_NET1_D4 15 /* Linux CLK ID (89) */
+#define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */
+#define CK_TOP_NET1_D5_D2 17 /* Linux CLK ID (91) */
+#define CK_TOP_NET1_D5_D4 18 /* Linux CLK ID (92) */
+#define CK_TOP_CB_NET1_D8 19 /* Linux CLK ID (93) */
+#define CK_TOP_NET1_D8_D2 20 /* Linux CLK ID (94) */
+#define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */
+#define CK_TOP_NET1_D8_D8 22 /* Linux CLK ID (96) */
+#define CK_TOP_NET1_D8_D16 23 /* Linux CLK ID (97) */
+#define CK_TOP_CB_NET2_800M 24 /* Linux CLK ID (98) */
+#define CK_TOP_CB_NET2_D2 25 /* Linux CLK ID (99) */
+#define CK_TOP_CB_NET2_D4 26 /* Linux CLK ID (100) */
+#define CK_TOP_NET2_D4_D4 27 /* Linux CLK ID (101) */
+#define CK_TOP_NET2_D4_D8 28 /* Linux CLK ID (102) */
+#define CK_TOP_CB_NET2_D6 29 /* Linux CLK ID (103) */
+#define CK_TOP_CB_NET2_D8 30 /* Linux CLK ID (104) */
+#define CK_TOP_CB_WEDMCU_208M 31 /* Linux CLK ID (105) */
+#define CK_TOP_CB_SGM_325M 32 /* Linux CLK ID (106) */
+#define CK_TOP_CB_NETSYS_850M 33 /* Linux CLK ID (107) */
+#define CK_TOP_CB_MSDC_400M 34 /* Linux CLK ID (108) */
+#define CK_TOP_CKSQ_40M_D2 35 /* Linux CLK ID (109) */
+#define CK_TOP_CB_RTC_32K 36 /* Linux CLK ID (110) */
+#define CK_TOP_CB_RTC_32P7K 37 /* Linux CLK ID (111) */
+#define CK_TOP_INFRA_F32K 38 /* Linux CLK ID (112) */
+#define CK_TOP_CKSQ_SRC 39 /* Linux CLK ID (113) */
+#define CK_TOP_NETSYS_2X 40 /* Linux CLK ID (114) */
+#define CK_TOP_NETSYS_GSW 41 /* Linux CLK ID (115) */
+#define CK_TOP_NETSYS_WED_MCU 42 /* Linux CLK ID (116) */
+#define CK_TOP_EIP197 43 /* Linux CLK ID (117) */
+#define CK_TOP_EMMC_250M 44 /* Linux CLK ID (118) */
+#define CK_TOP_EMMC_400M 45 /* Linux CLK ID (119) */
+#define CK_TOP_SPI 46 /* Linux CLK ID (120) */
+#define CK_TOP_SPIM_MST 47 /* Linux CLK ID (121) */
+#define CK_TOP_NFI1X 48 /* Linux CLK ID (122) */
+#define CK_TOP_SPINFI_BCK 49 /* Linux CLK ID (123) */
+#define CK_TOP_I2C_BCK 50 /* Linux CLK ID (124) */
+#define CK_TOP_USB_SYS 51 /* Linux CLK ID (125) */
+#define CK_TOP_USB_SYS_P1 52 /* Linux CLK ID (126) */
+#define CK_TOP_USB_XHCI 53 /* Linux CLK ID (127) */
+#define CK_TOP_USB_XHCI_P1 54 /* Linux CLK ID (128) */
+#define CK_TOP_USB_FRMCNT 55 /* Linux CLK ID (129) */
+#define CK_TOP_USB_FRMCNT_P1 56 /* Linux CLK ID (130) */
+#define CK_TOP_AUD 57 /* Linux CLK ID (131) */
+#define CK_TOP_A1SYS 58 /* Linux CLK ID (132) */
+#define CK_TOP_AUD_L 59 /* Linux CLK ID (133) */
+#define CK_TOP_A_TUNER 60 /* Linux CLK ID (134) */
+#define CK_TOP_SYSAXI 61 /* Linux CLK ID (135) */
+#define CK_TOP_INFRA_F26M 62 /* Linux CLK ID (136) */
+#define CK_TOP_USB_REF 63 /* Linux CLK ID (137) */
+#define CK_TOP_USB_CK_P1 64 /* Linux CLK ID (138) */
+/* mtk_mux */
+#define CK_TOP_NETSYS_SEL 65 /* Linux CLK ID (0) */
+#define CK_TOP_NETSYS_500M_SEL 66 /* Linux CLK ID (1) */
+#define CK_TOP_NETSYS_2X_SEL 67 /* Linux CLK ID (2) */
+#define CK_TOP_NETSYS_GSW_SEL 68 /* Linux CLK ID (3) */
+#define CK_TOP_ETH_GMII_SEL 69 /* Linux CLK ID (4) */
+#define CK_TOP_NETSYS_MCU_SEL 70 /* Linux CLK ID (5) */
+#define CK_TOP_NETSYS_PAO_2X_SEL 71 /* Linux CLK ID (6) */
+#define CK_TOP_EIP197_SEL 72 /* Linux CLK ID (7) */
+#define CK_TOP_AXI_INFRA_SEL 73 /* Linux CLK ID (8) */
+#define CK_TOP_UART_SEL 74 /* Linux CLK ID (9) */
+#define CK_TOP_EMMC_250M_SEL 75 /* Linux CLK ID (10) */
+#define CK_TOP_EMMC_400M_SEL 76 /* Linux CLK ID (11) */
+#define CK_TOP_SPI_SEL 77 /* Linux CLK ID (12) */
+#define CK_TOP_SPIM_MST_SEL 78 /* Linux CLK ID (13) */
+#define CK_TOP_NFI1X_SEL 79 /* Linux CLK ID (14) */
+#define CK_TOP_SPINFI_SEL 80 /* Linux CLK ID (15) */
+#define CK_TOP_PWM_SEL 81 /* Linux CLK ID (16) */
+#define CK_TOP_I2C_SEL 82 /* Linux CLK ID (17) */
+#define CK_TOP_PCIE_MBIST_250M_SEL 83 /* Linux CLK ID (18) */
+#define CK_TOP_PEXTP_TL_SEL 84 /* Linux CLK ID (19) */
+#define CK_TOP_PEXTP_TL_P1_SEL 85 /* Linux CLK ID (20) */
+#define CK_TOP_PEXTP_TL_P2_SEL 86 /* Linux CLK ID (21) */
+#define CK_TOP_PEXTP_TL_P3_SEL 87 /* Linux CLK ID (22) */
+#define CK_TOP_USB_SYS_SEL 88 /* Linux CLK ID (23) */
+#define CK_TOP_USB_SYS_P1_SEL 89 /* Linux CLK ID (24) */
+#define CK_TOP_USB_XHCI_SEL 90 /* Linux CLK ID (25) */
+#define CK_TOP_USB_XHCI_P1_SEL 91 /* Linux CLK ID (26) */
+#define CK_TOP_USB_FRMCNT_SEL 92 /* Linux CLK ID (27) */
+#define CK_TOP_USB_FRMCNT_P1_SEL 93 /* Linux CLK ID (28) */
+#define CK_TOP_AUD_SEL 94 /* Linux CLK ID (29) */
+#define CK_TOP_A1SYS_SEL 95 /* Linux CLK ID (30) */
+#define CK_TOP_AUD_L_SEL 96 /* Linux CLK ID (31) */
+#define CK_TOP_A_TUNER_SEL 97 /* Linux CLK ID (32) */
+#define CK_TOP_SSPXTP_SEL 98 /* Linux CLK ID (33) */
+#define CK_TOP_USB_PHY_SEL 99 /* Linux CLK ID (34) */
+#define CK_TOP_USXGMII_SBUS_0_SEL 100 /* Linux CLK ID (35) */
+#define CK_TOP_USXGMII_SBUS_1_SEL 101 /* Linux CLK ID (36) */
+#define CK_TOP_SGM_0_SEL 102 /* Linux CLK ID (37) */
+#define CK_TOP_SGM_SBUS_0_SEL 103 /* Linux CLK ID (38) */
+#define CK_TOP_SGM_1_SEL 104 /* Linux CLK ID (39) */
+#define CK_TOP_SGM_SBUS_1_SEL 105 /* Linux CLK ID (40) */
+#define CK_TOP_XFI_PHY_0_XTAL_SEL 106 /* Linux CLK ID (41) */
+#define CK_TOP_XFI_PHY_1_XTAL_SEL 107 /* Linux CLK ID (42) */
+#define CK_TOP_SYSAXI_SEL 108 /* Linux CLK ID (43) */
+#define CK_TOP_SYSAPB_SEL 109 /* Linux CLK ID (44) */
+#define CK_TOP_ETH_REFCK_50M_SEL 110 /* Linux CLK ID (45) */
+#define CK_TOP_ETH_SYS_200M_SEL 111 /* Linux CLK ID (46) */
+#define CK_TOP_ETH_SYS_SEL 112 /* Linux CLK ID (47) */
+#define CK_TOP_ETH_XGMII_SEL 113 /* Linux CLK ID (48) */
+#define CK_TOP_BUS_TOPS_SEL 114 /* Linux CLK ID (49) */
+#define CK_TOP_NPU_TOPS_SEL 115 /* Linux CLK ID (50) */
+#define CK_TOP_DRAMC_SEL 116 /* Linux CLK ID (51) */
+#define CK_TOP_DRAMC_MD32_SEL 117 /* Linux CLK ID (52) */
+#define CK_TOP_INFRA_F26M_SEL 118 /* Linux CLK ID (53) */
+#define CK_TOP_PEXTP_P0_SEL 119 /* Linux CLK ID (54) */
+#define CK_TOP_PEXTP_P1_SEL 120 /* Linux CLK ID (55) */
+#define CK_TOP_PEXTP_P2_SEL 121 /* Linux CLK ID (56) */
+#define CK_TOP_PEXTP_P3_SEL 122 /* Linux CLK ID (57) */
+#define CK_TOP_DA_XTP_GLB_P0_SEL 123 /* Linux CLK ID (58) */
+#define CK_TOP_DA_XTP_GLB_P1_SEL 124 /* Linux CLK ID (59) */
+#define CK_TOP_DA_XTP_GLB_P2_SEL 125 /* Linux CLK ID (60) */
+#define CK_TOP_DA_XTP_GLB_P3_SEL 126 /* Linux CLK ID (61) */
+#define CK_TOP_CKM_SEL 127 /* Linux CLK ID (62) */
+#define CK_TOP_DA_SELM_XTAL_SEL 128 /* Linux CLK ID (63) */
+#define CK_TOP_PEXTP_SEL 129 /* Linux CLK ID (64) */
+#define CK_TOP_TOPS_P2_26M_SEL 130 /* Linux CLK ID (65) */
+#define CK_TOP_MCUSYS_BACKUP_625M_SEL 131 /* Linux CLK ID (66) */
+#define CK_TOP_NETSYS_SYNC_250M_SEL 132 /* Linux CLK ID (67) */
+#define CK_TOP_MACSEC_SEL 133 /* Linux CLK ID (68) */
+#define CK_TOP_NETSYS_TOPS_400M_SEL 134 /* Linux CLK ID (69) */
+#define CK_TOP_NETSYS_PPEFB_250M_SEL 135 /* Linux CLK ID (70) */
+#define CK_TOP_NETSYS_WARP_SEL 136 /* Linux CLK ID (71) */
+#define CK_TOP_ETH_MII_SEL 137 /* Linux CLK ID (72) */
+#define CK_TOP_CK_NPU_SEL_CM_TOPS_SEL 138 /* Linux CLK ID (73) */
+
+/* APMIXEDSYS */
+/* mtk_pll_data */
+#define CK_APMIXED_NETSYSPLL 0
+#define CK_APMIXED_MPLL 1
+#define CK_APMIXED_MMPLL 2
+#define CK_APMIXED_APLL2 3
+#define CK_APMIXED_NET1PLL 4
+#define CK_APMIXED_NET2PLL 5
+#define CK_APMIXED_WEDMCUPLL 6
+#define CK_APMIXED_SGMPLL 7
+#define CK_APMIXED_ARM_B 8
+#define CK_APMIXED_CCIPLL2_B 9
+#define CK_APMIXED_USXGMIIPLL 10
+#define CK_APMIXED_MSDCPLL 11
+
+/* ETHSYS ETH DMA */
+/* mtk_gate */
+#define CK_ETHDMA_FE_EN 0
+
+/* SGMIISYS_0 */
+/* mtk_gate */
+#define CK_SGM0_TX_EN 0
+#define CK_SGM0_RX_EN 1
+
+/* SGMIISYS_1 */
+/* mtk_gate */
+#define CK_SGM1_TX_EN 0
+#define CK_SGM1_RX_EN 1
+
+/* ETHWARP */
+/* mtk_gate */
+#define CK_ETHWARP_WOCPU2_EN 0
+#define CK_ETHWARP_WOCPU1_EN 1
+#define CK_ETHWARP_WOCPU0_EN 2
+
+#endif /* _DT_BINDINGS_CLK_MT7988_H */
diff --git a/include/dt-bindings/reset/mt7988-reset.h b/include/dt-bindings/reset/mt7988-reset.h
new file mode 100644
index 0000000..d30011f
--- /dev/null
+++ b/include/dt-bindings/reset/mt7988-reset.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_MTK_RESET_H_
+#define _DT_BINDINGS_MTK_RESET_H_
+
+/* ETHDMA Subsystem resets */
+#define ETHDMA_FE_RST 6
+#define ETHDMA_PMTR_RST 8
+#define ETHDMA_GMAC_RST 23
+#define ETHDMA_WDMA0_RST 24
+#define ETHDMA_WDMA1_RST 25
+#define ETHDMA_WDMA2_RST 26
+#define ETHDMA_PPE0_RST 29
+#define ETHDMA_PPE1_RST 30
+#define ETHDMA_PPE2_RST 31
+
+/* ETHWARP Subsystem resets */
+#define ETHWARP_GSW_RST 9
+#define ETHWARP_EIP197_RST 10
+#define ETHWARP_WOCPU0_RST 32
+#define ETHWARP_WOCPU1_RST 33
+#define ETHWARP_WOCPU2_RST 34
+#define ETHWARP_WOX_NET_MUX_RST 35
+#define ETHWARP_WED0_RST 36
+#define ETHWARP_WED1_RST 37
+#define ETHWARP_WED2_RST 38
+
+#endif /* _DT_BINDINGS_MTK_RESET_H_ */
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 3a64eb9..4a29dda 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -696,9 +696,21 @@
/* return true if the device is removable */
bool efi_disk_is_removable(efi_handle_t handle);
-/* open file system: */
-struct efi_simple_file_system_protocol *efi_simple_file_system(
- struct blk_desc *desc, int part, struct efi_device_path *dp);
+/**
+ * efi_create_simple_file_system() - create simple file system protocol
+ *
+ * Create a simple file system protocol for a partition.
+ *
+ * @desc: block device descriptor
+ * @part: partition number
+ * @dp: device path
+ * @fsp: simple file system protocol
+ * Return: status code
+ */
+efi_status_t
+efi_create_simple_file_system(struct blk_desc *desc, int part,
+ struct efi_device_path *dp,
+ struct efi_simple_file_system_protocol **fsp);
/* open file from device-path: */
struct efi_file_handle *efi_file_from_path(struct efi_device_path *fp);
diff --git a/include/environment/distro/sf.h b/include/env/distro/sf.h
similarity index 100%
rename from include/environment/distro/sf.h
rename to include/env/distro/sf.h
diff --git a/include/environment/pg-wcom/common.env b/include/env/pg-wcom/common.env
similarity index 100%
rename from include/environment/pg-wcom/common.env
rename to include/env/pg-wcom/common.env
diff --git a/include/environment/pg-wcom/ls102xa.env b/include/env/pg-wcom/ls102xa.env
similarity index 95%
rename from include/environment/pg-wcom/ls102xa.env
rename to include/env/pg-wcom/ls102xa.env
index 5b5bda9..abbec42 100644
--- a/include/environment/pg-wcom/ls102xa.env
+++ b/include/env/pg-wcom/ls102xa.env
@@ -1,6 +1,6 @@
#define WCOM_UBI_PARTITION_APP
-#include <environment/pg-wcom/common.env>
+#include <env/pg-wcom/common.env>
EEprom_ivm=pca9547:70:9
boot=bootm $load_addr_r - $fdt_addr_r
diff --git a/include/environment/pg-wcom/powerpc.env b/include/env/pg-wcom/powerpc.env
similarity index 100%
rename from include/environment/pg-wcom/powerpc.env
rename to include/env/pg-wcom/powerpc.env
diff --git a/include/environment/ti/dfu.h b/include/env/ti/dfu.h
similarity index 100%
rename from include/environment/ti/dfu.h
rename to include/env/ti/dfu.h
diff --git a/include/environment/ti/k3_dfu.env b/include/env/ti/k3_dfu.env
similarity index 100%
rename from include/environment/ti/k3_dfu.env
rename to include/env/ti/k3_dfu.env
diff --git a/include/environment/ti/k3_dfu.h b/include/env/ti/k3_dfu.h
similarity index 100%
rename from include/environment/ti/k3_dfu.h
rename to include/env/ti/k3_dfu.h
diff --git a/include/environment/ti/k3_rproc.env b/include/env/ti/k3_rproc.env
similarity index 100%
rename from include/environment/ti/k3_rproc.env
rename to include/env/ti/k3_rproc.env
diff --git a/include/environment/ti/k3_rproc.h b/include/env/ti/k3_rproc.h
similarity index 100%
rename from include/environment/ti/k3_rproc.h
rename to include/env/ti/k3_rproc.h
diff --git a/include/environment/ti/mmc.env b/include/env/ti/mmc.env
similarity index 100%
rename from include/environment/ti/mmc.env
rename to include/env/ti/mmc.env
diff --git a/include/environment/ti/mmc.h b/include/env/ti/mmc.h
similarity index 100%
rename from include/environment/ti/mmc.h
rename to include/env/ti/mmc.h
diff --git a/include/environment/ti/nand.env b/include/env/ti/nand.env
similarity index 100%
rename from include/environment/ti/nand.env
rename to include/env/ti/nand.env
diff --git a/include/environment/ti/nand.h b/include/env/ti/nand.h
similarity index 100%
rename from include/environment/ti/nand.h
rename to include/env/ti/nand.h
diff --git a/include/environment/ti/ti_armv7_common.env b/include/env/ti/ti_armv7_common.env
similarity index 100%
rename from include/environment/ti/ti_armv7_common.env
rename to include/env/ti/ti_armv7_common.env
diff --git a/include/environment/ti/ti_armv7_keystone2.env b/include/env/ti/ti_armv7_keystone2.env
similarity index 100%
rename from include/environment/ti/ti_armv7_keystone2.env
rename to include/env/ti/ti_armv7_keystone2.env
diff --git a/include/environment/ti/ufs.env b/include/env/ti/ufs.env
similarity index 100%
rename from include/environment/ti/ufs.env
rename to include/env/ti/ufs.env
diff --git a/include/environment/ti/ufs.h b/include/env/ti/ufs.h
similarity index 100%
rename from include/environment/ti/ufs.h
rename to include/env/ti/ufs.h
diff --git a/include/env/x86.env b/include/env/x86.env
new file mode 100644
index 0000000..d00d98f
--- /dev/null
+++ b/include/env/x86.env
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com
+ */
+
+pciconfighost=1
+netdev=eth0
+consoledev=ttyS0
+scriptaddr=0x7000000
+kernel_addr_r=0x1000000
+ramdisk_addr_r=0x4000000
+ramdiskfile=initramfs.gz
+
+/* common console settings */
+stdin=serial,i8042-kbd,usbkbd
+stdout=serial,vidconsole
+stderr=serial,vidconsole
diff --git a/include/expo.h b/include/expo.h
index 0b1d944..a2b3a71 100644
--- a/include/expo.h
+++ b/include/expo.h
@@ -4,14 +4,13 @@
* Written by Simon Glass <sjg@chromium.org>
*/
-#ifndef __SCENE_H
-#define __SCENE_H
+#ifndef __EXPO_H
+#define __EXPO_H
#include <dm/ofnode_decl.h>
#include <linux/list.h>
struct udevice;
-struct video_priv;
/**
* enum expoact_type - types of actions reported by the expo
@@ -188,6 +187,8 @@
* @type: Type of this object
* @dim: Dimensions for this object
* @flags: Flags for this object
+ * @bit_length: Number of bits used for this object in CMOS RAM
+ * @start_bit: Start bit to use for this object in CMOS RAM
* @sibling: Node to link this object to its siblings
*/
struct scene_obj {
@@ -196,7 +197,9 @@
uint id;
enum scene_obj_t type;
struct scene_dim dim;
- int flags;
+ u8 flags;
+ u8 bit_length;
+ u16 start_bit;
struct list_head sibling;
};
@@ -676,24 +679,4 @@
*/
int expo_build(ofnode root, struct expo **expp);
-/**
- * cedit_arange() - Arrange objects in a configuration-editor scene
- *
- * @exp: Expo to update
- * @vid_priv: Private info of the video device
- * @scene_id: scene ID to arrange
- * Returns: 0 if OK, -ve on error
- */
-int cedit_arange(struct expo *exp, struct video_priv *vid_priv, uint scene_id);
-
-/**
- * cedit_run() - Run a configuration editor
- *
- * This accepts input until the user quits with Escape
- *
- * @exp: Expo to use
- * Returns: 0 if OK, -ve on error
- */
-int cedit_run(struct expo *exp);
-
-#endif /*__SCENE_H */
+#endif /*__EXPO_H */
diff --git a/include/init.h b/include/init.h
index 8873081..3bf3047 100644
--- a/include/init.h
+++ b/include/init.h
@@ -296,15 +296,20 @@
int show_board_info(void);
/**
- * Get the uppermost pointer that is valid to access
+ * board_get_usable_ram_top() - get uppermost address for U-Boot relocation
*
- * Some systems may not map all of their address space. This function allows
- * boards to indicate what their highest support pointer value is for DRAM
- * access.
+ * Some systems have reserved memory areas in high memory. By implementing this
+ * function boards can indicate the highest address value to be used when
+ * relocating U-Boot. The returned address is exclusive (i.e. 1 byte above the
+ * last usable address).
*
- * @param total_size Size of U-Boot (unused?)
+ * Due to overflow on systems with 32bit phys_addr_t a value 0 is used instead
+ * of 4GiB.
+ *
+ * @total_size: monitor length in bytes (size of U-Boot code)
+ * Return: uppermost address for U-Boot relocation
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size);
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size);
int board_early_init_f(void);
diff --git a/include/irq.h b/include/irq.h
index 1d08cb8..5638c10 100644
--- a/include/irq.h
+++ b/include/irq.h
@@ -109,7 +109,7 @@
* xxx_xlate() call, or as the only step in implementing a client's
* irq_request() call.
*
- * @irq: The irq struct to request; this has been fille in by
+ * @irq: The irq struct to request; this has been filled in by
* a previoux xxx_xlate() function call, or by the caller
* of irq_request().
* @return 0 if OK, or a negative error code.
diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
index e1d0988..f44e9e8 100644
--- a/include/linux/arm-smccc.h
+++ b/include/linux/arm-smccc.h
@@ -1,6 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015, Linaro Limited
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
*/
#ifndef __LINUX_ARM_SMCCC_H
#define __LINUX_ARM_SMCCC_H
@@ -70,6 +74,47 @@
unsigned long a3;
};
+#ifdef CONFIG_ARM64
+/**
+ * struct arm_smccc_1_2_regs - Arguments for or Results from SMC call
+ * @a0-a17 argument values from registers 0 to 17
+ */
+struct arm_smccc_1_2_regs {
+ unsigned long a0;
+ unsigned long a1;
+ unsigned long a2;
+ unsigned long a3;
+ unsigned long a4;
+ unsigned long a5;
+ unsigned long a6;
+ unsigned long a7;
+ unsigned long a8;
+ unsigned long a9;
+ unsigned long a10;
+ unsigned long a11;
+ unsigned long a12;
+ unsigned long a13;
+ unsigned long a14;
+ unsigned long a15;
+ unsigned long a16;
+ unsigned long a17;
+};
+
+/**
+ * arm_smccc_1_2_smc() - make SMC calls
+ * @args: arguments passed via struct arm_smccc_1_2_regs
+ * @res: result values via struct arm_smccc_1_2_regs
+ *
+ * This function is used to make SMC calls following SMC Calling Convention
+ * v1.2 or above. The content of the supplied param are copied from the
+ * structure to registers prior to the SMC instruction. The return values
+ * are updated with the content from registers on return from the SMC
+ * instruction.
+ */
+asmlinkage void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args,
+ struct arm_smccc_1_2_regs *res);
+#endif
+
/**
* struct arm_smccc_quirk - Contains quirk information
* @id: quirk identification
diff --git a/include/lmb.h b/include/lmb.h
index 07bf221..231b68b 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -116,16 +116,31 @@
phys_addr_t max_addr);
phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base, phys_size_t size);
phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr);
+
+/**
+ * lmb_is_reserved() - test if address is in reserved region
+ *
+ * The function checks if a reserved region comprising @addr exists.
+ *
+ * @lmb: the logical memory block struct
+ * @addr: address to be tested
+ * Return: 1 if reservation exists, 0 otherwise
+ */
int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr);
+
/**
- * lmb_is_reserved_flags - test if tha address is in reserved region with a bitfield flag
+ * lmb_is_reserved_flags() - test if address is in reserved region with flag bits set
+ *
+ * The function checks if a reserved region comprising @addr exists which has
+ * all flag bits set which are set in @flags.
*
* @lmb: the logical memory block struct
* @addr: address to be tested
- * @flags: flags bitfied to be tested
- * Return: if not reserved or reserved without the requested flag else 1
+ * @flags: bitmap with bits to be tested
+ * Return: 1 if matching reservation exists, 0 otherwise
*/
int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags);
+
long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size);
void lmb_dump_all(struct lmb *lmb);
diff --git a/include/mm_communication.h b/include/mm_communication.h
index e65fbde..f38f1a5 100644
--- a/include/mm_communication.h
+++ b/include/mm_communication.h
@@ -6,6 +6,9 @@
* Copyright (c) 2017, Intel Corporation. All rights reserved.
* Copyright (C) 2020 Linaro Ltd. <sughosh.ganu@linaro.org>
* Copyright (C) 2020 Linaro Ltd. <ilias.apalodimas@linaro.org>
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
*/
#ifndef _MM_COMMUNICATION_H_
@@ -13,6 +16,11 @@
#include <part_efi.h>
+#if CONFIG_IS_ENABLED(ARM_FFA_TRANSPORT)
+/* MM service UUID string (big-endian format). This UUID is common across all MM SPs */
+#define MM_SP_UUID "33d532ed-e699-0942-c09c-a798d9cd722d"
+#endif
+
/*
* Interface to the pseudo Trusted Application (TA), which provides a
* communication channel with the Standalone MM (Management Mode)
@@ -247,5 +255,14 @@
struct var_check_property property;
u16 name[];
};
+
+#if CONFIG_IS_ENABLED(ARM_FFA_TRANSPORT)
+/* supported MM transports */
+enum mm_comms_select {
+ MM_COMMS_UNDEFINED,
+ MM_COMMS_FFA,
+ MM_COMMS_OPTEE
+};
+#endif
#endif /* _MM_COMMUNICATION_H_ */
diff --git a/include/os.h b/include/os.h
index 968412b..fc8a1b1 100644
--- a/include/os.h
+++ b/include/os.h
@@ -98,6 +98,16 @@
*/
int os_unlink(const char *pathname);
+/** os_persistent_fname() - Find the path to a test file
+ *
+ * @buf: Buffer to hold path
+ * @maxsize: Maximum size of buffer
+ * @fname: Leaf filename to find
+ * Returns: 0 on success, -ENOENT if file is not found, -ENOSPC if the buffer is
+ * too small
+ */
+int os_persistent_file(char *buf, int maxsize, const char *fname);
+
/**
* os_exit() - access to the OS exit() system call
*
diff --git a/include/part.h b/include/part.h
index edc46f8..f321479 100644
--- a/include/part.h
+++ b/include/part.h
@@ -80,6 +80,73 @@
#endif
};
+/* Accessors for struct disk_partition field ->uuid */
+extern char *__invalid_use_of_disk_partition_uuid;
+
+static inline const char *disk_partition_uuid(const struct disk_partition *info)
+{
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
+ return info->uuid;
+#else
+ return __invalid_use_of_disk_partition_uuid;
+#endif
+}
+
+static inline void disk_partition_set_uuid(struct disk_partition *info,
+ const char *val)
+{
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
+ strlcpy(info->uuid, val, UUID_STR_LEN + 1);
+#endif
+}
+
+static inline void disk_partition_clr_uuid(struct disk_partition *info)
+{
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
+ *info->uuid = '\0';
+#endif
+}
+
+/* Accessors for struct disk_partition field ->type_guid */
+extern char *__invalid_use_of_disk_partition_type_uuid;
+
+static inline const
+char *disk_partition_type_uuid(const struct disk_partition *info)
+{
+#ifdef CONFIG_PARTITION_TYPE_GUID
+ return info->type_guid;
+#else
+ return __invalid_use_of_disk_partition_type_uuid;
+#endif
+}
+
+static inline void disk_partition_set_type_guid(struct disk_partition *info,
+ const char *val)
+{
+#ifdef CONFIG_PARTITION_TYPE_GUID
+ strlcpy(info->type_guid, val, UUID_STR_LEN + 1);
+#endif
+}
+
+static inline void disk_partition_clr_type_guid(struct disk_partition *info)
+{
+#ifdef CONFIG_PARTITION_TYPE_GUID
+ *info->type_guid = '\0';
+#endif
+}
+
+/* Accessors for struct disk_partition field ->sys_ind */
+extern int __invalid_use_of_disk_partition_sys_ind;
+
+static inline uint disk_partition_sys_ind(const struct disk_partition *info)
+{
+#ifdef CONFIG_DOS_PARTITION
+ return info->sys_ind;
+#else
+ return __invalid_use_of_disk_partition_sys_ind;
+#endif
+}
+
struct disk_part {
int partnum;
struct disk_partition gpt_part_info;
@@ -98,8 +165,8 @@
* @ifname: Interface name (e.g. "ide", "scsi")
* @dev: Device number (0 for first device on that interface, 1 for
* second, etc.
- * Return: pointer to the block device, or NULL if not available, or an
- * error occurred.
+ * Return:
+ * pointer to the block device, or NULL if not available, or an error occurred.
*/
struct blk_desc *blk_get_dev(const char *ifname, int dev);
@@ -113,7 +180,7 @@
* contained with the interface's data structure. There is no global
* numbering for block devices, so the interface name must be provided.
*
- * @dev_desc: Block device descriptor
+ * @desc: Block device descriptor
* @part: Partition number to read
* @part_type: Partition driver to use, or PART_TYPE_UNKNOWN to automatically
* choose a driver
@@ -121,20 +188,24 @@
*
* Return: 0 on success, negative errno on failure
*/
-int part_get_info_by_type(struct blk_desc *dev_desc, int part, int part_type,
+int part_get_info_by_type(struct blk_desc *desc, int part, int part_type,
struct disk_partition *info);
-int part_get_info(struct blk_desc *dev_desc, int part,
+int part_get_info(struct blk_desc *desc, int part,
struct disk_partition *info);
/**
* part_get_info_whole_disk() - get partition info for the special case of
* a partition occupying the entire disk.
+ *
+ * @desc: block device descriptor
+ * @info: returned partition information
+ * Return: 0 on success
*/
-int part_get_info_whole_disk(struct blk_desc *dev_desc,
+int part_get_info_whole_disk(struct blk_desc *desc,
struct disk_partition *info);
-void part_print(struct blk_desc *dev_desc);
-void part_init(struct blk_desc *dev_desc);
-void dev_print(struct blk_desc *dev_desc);
+void part_print(struct blk_desc *desc);
+void part_init(struct blk_desc *desc);
+void dev_print(struct blk_desc *desc);
/**
* blk_get_device_by_str() - Get a block device given its interface/hw partition
@@ -158,11 +229,11 @@
* containing the device number (e.g. "2") or the device number
* and hardware partition number (e.g. "2.4") for devices that
* support it (currently only MMC).
- * @dev_desc: Returns a pointer to the block device on success
+ * @desc: Returns a pointer to the block device on success
* Return: block device number (local to the interface), or -1 on error
*/
int blk_get_device_by_str(const char *ifname, const char *dev_str,
- struct blk_desc **dev_desc);
+ struct blk_desc **desc);
/**
* blk_get_device_part_str() - Get a block device and partition
@@ -170,15 +241,18 @@
* This calls blk_get_device_by_str() to look up a device. It also looks up
* a partition and returns information about it.
*
+ * @dev_part_str is in the format <dev>.<hw_part>:<part> where
+ *
- * @dev_part_str is in the format:
- * <dev>.<hw_part>:<part> where <dev> is the device number,
- * <hw_part> is the optional hardware partition number and
- * <part> is the partition number
+ * * <dev> is the device number,
*
- * If ifname is "hostfs" then this function returns the sandbox host block
+ * * <hw_part> is the optional hardware partition number and
+ *
+ * * <part> is the partition number.
+ *
+ * If @ifname is "hostfs", then this function returns the sandbox host block
* device.
*
- * If ifname is ubi, then this function returns 0, with @info set to a
+ * If @ifname is "ubi", then this function returns 0, with @info set to a
* special UBI device.
*
* If @dev_part_str is NULL or empty or "-", then this function looks up
@@ -187,56 +261,58 @@
* If the partition string is empty then the first partition is used. If the
* partition string is "auto" then the first bootable partition is used.
*
- * @ifname: Interface name (e.g. "ide", "scsi")
+ * @ifname: Interface name (e.g. "ide", "scsi")
* @dev_part_str: Device and partition string
- * @dev_desc: Returns a pointer to the block device on success
- * @info: Returns partition information
+ * @desc: Returns a pointer to the block device on success
+ * @info: Returns partition information
* @allow_whole_dev: true to allow the user to select partition 0
- * (which means the whole device), false to require a valid
- * partition number >= 1
+ * (which means the whole device), false to require a valid
+ * partition number >= 1
* Return: partition number, or -1 on error
*
*/
int blk_get_device_part_str(const char *ifname, const char *dev_part_str,
- struct blk_desc **dev_desc,
+ struct blk_desc **desc,
struct disk_partition *info, int allow_whole_dev);
/**
* part_get_info_by_name() - Search for a partition by name
* among all available registered partitions
*
- * @param dev_desc - block device descriptor
- * @param gpt_name - the specified table entry name
- * @param info - returns the disk partition info
+ * @desc: block device descriptor
+ * @name: the specified table entry name
+ * @info: returns the disk partition info
*
- * Return: - the partition number on match (starting on 1), -1 on no match,
+ * Return: the partition number on match (starting on 1), -1 on no match,
* otherwise error
*/
-int part_get_info_by_name(struct blk_desc *dev_desc,
- const char *name, struct disk_partition *info);
+int part_get_info_by_name(struct blk_desc *desc, const char *name,
+ struct disk_partition *info);
/**
- * Get partition info from dev number + part name, or dev number + part number.
+ * part_get_info_by_dev_and_name_or_num() - Get partition info from dev number
+ * and part name, or dev number and
+ * part number.
*
* Parse a device number and partition description (either name or number)
* in the form of device number plus partition name separated by a "#"
* (like "device_num#partition_name") or a device number plus a partition number
* separated by a ":". For example both "0#misc" and "0:1" can be valid
* partition descriptions for a given interface. If the partition is found, sets
- * dev_desc and part_info accordingly with the information of the partition.
+ * desc and part_info accordingly with the information of the partition.
*
- * @param[in] dev_iface Device interface
- * @param[in] dev_part_str Input partition description, like "0#misc" or "0:1"
- * @param[out] dev_desc Place to store the device description pointer
- * @param[out] part_info Place to store the partition information
- * @param[in] allow_whole_dev true to allow the user to select partition 0
- * (which means the whole device), false to require a valid
- * partition number >= 1
- * Return: the partition number on success, or negative errno on error
+ * @dev_iface: Device interface
+ * @dev_part_str: Input partition description, like "0#misc" or "0:1"
+ * @desc: Place to store the device description pointer
+ * @part_info: Place to store the partition information
+ * @allow_whole_dev: true to allow the user to select partition 0
+ * (which means the whole device), false to require a valid
+ * partition number >= 1
+ * Return: the partition number on success, or negative errno on error
*/
int part_get_info_by_dev_and_name_or_num(const char *dev_iface,
const char *dev_part_str,
- struct blk_desc **dev_desc,
+ struct blk_desc **desc,
struct disk_partition *part_info,
int allow_whole_dev);
@@ -247,12 +323,12 @@
* (DOS, ISO). Generates partition name out of the device type and partition
* number.
*
- * @dev_desc: pointer to the block device
+ * @desc: pointer to the block device
* @part_num: partition number for which the name is generated
* @name: buffer where the name is written
*/
-void part_set_generic_name(const struct blk_desc *dev_desc,
- int part_num, char *name);
+void part_set_generic_name(const struct blk_desc *desc, int part_num,
+ char *name);
extern const struct block_drvr block_drvr[];
#else
@@ -260,26 +336,25 @@
{ return NULL; }
static inline struct blk_desc *mg_disk_get_dev(int dev) { return NULL; }
-static inline int part_get_info(struct blk_desc *dev_desc, int part,
+static inline int part_get_info(struct blk_desc *desc, int part,
struct disk_partition *info) { return -1; }
-static inline int part_get_info_whole_disk(struct blk_desc *dev_desc,
+static inline int part_get_info_whole_disk(struct blk_desc *desc,
struct disk_partition *info)
{ return -1; }
-static inline void part_print(struct blk_desc *dev_desc) {}
-static inline void part_init(struct blk_desc *dev_desc) {}
-static inline void dev_print(struct blk_desc *dev_desc) {}
+static inline void part_print(struct blk_desc *desc) {}
+static inline void part_init(struct blk_desc *desc) {}
+static inline void dev_print(struct blk_desc *desc) {}
static inline int blk_get_device_by_str(const char *ifname, const char *dev_str,
- struct blk_desc **dev_desc)
+ struct blk_desc **desc)
{ return -1; }
static inline int blk_get_device_part_str(const char *ifname,
const char *dev_part_str,
- struct blk_desc **dev_desc,
+ struct blk_desc **desc,
struct disk_partition *info,
int allow_whole_dev)
-{ *dev_desc = NULL; return -1; }
+{ *desc = NULL; return -1; }
-static inline int part_get_info_by_name(struct blk_desc *dev_desc,
- const char *name,
+static inline int part_get_info_by_name(struct blk_desc *desc, const char *name,
struct disk_partition *info)
{
return -ENOENT;
@@ -288,41 +363,24 @@
static inline int
part_get_info_by_dev_and_name_or_num(const char *dev_iface,
const char *dev_part_str,
- struct blk_desc **dev_desc,
+ struct blk_desc **desc,
struct disk_partition *part_info,
int allow_whole_dev)
{
- *dev_desc = NULL;
+ *desc = NULL;
return -ENOSYS;
}
#endif
-/**
- * part_get_bootable() - Find the first bootable partition
- *
- * @desc: Block-device descriptor
- * @return first bootable partition, or 0 if there is none
- */
-int part_get_bootable(struct blk_desc *desc);
-
struct udevice;
/**
- * part_create_block_devices - Create block devices for disk partitions
- *
- * Create UCLASS_PARTITION udevices for each of disk partitions in @parent
- *
- * @blk_dev: Whole disk device
- */
-int part_create_block_devices(struct udevice *blk_dev);
-
-/**
* disk_blk_read() - read blocks from a disk partition
*
* @dev: Device to read from (UCLASS_PARTITION)
* @start: Start block number to read in the partition (0=first)
* @blkcnt: Number of blocks to read
* @buffer: Destination buffer for data read
- * Returns: number of blocks read, or -ve error number (see the
+ * Return: number of blocks read, or -ve error number (see the
* IS_ERR_VALUE() macro
*/
ulong disk_blk_read(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
@@ -335,7 +393,7 @@
* @start: Start block number to write in the partition (0=first)
* @blkcnt: Number of blocks to write
* @buffer: Source buffer for data to write
- * Returns: number of blocks written, or -ve error number (see the
+ * Return: number of blocks written, or -ve error number (see the
* IS_ERR_VALUE() macro
*/
ulong disk_blk_write(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
@@ -347,7 +405,7 @@
* @dev: Device to (partially) erase (UCLASS_PARTITION)
* @start: Start block number to erase in the partition (0=first)
* @blkcnt: Number of blocks to erase
- * Returns: number of blocks erased, or -ve error number (see the
+ * Return: number of blocks erased, or -ve error number (see the
* IS_ERR_VALUE() macro
*/
ulong disk_blk_erase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt);
@@ -369,37 +427,42 @@
#define part_get_info_ptr(x) x
#endif
-
+/**
+ * struct part_driver - partition driver
+ */
struct part_driver {
+ /** @name: partition name */
const char *name;
+ /** @part_type: (MBR) partition type */
int part_type;
- const int max_entries; /* maximum number of entries to search */
-
+ /** @max_entries: maximum number of partition table entries */
+ const int max_entries;
/**
- * get_info() - Get information about a partition
+ * @get_info: Get information about a partition
*
- * @dev_desc: Block device descriptor
- * @part: Partition number (1 = first)
- * @info: Returns partition information
+ * @get_info.desc: Block device descriptor
+ * @get_info.part: Partition number (1 = first)
+ * @get_info.info: Returns partition information
*/
- int (*get_info)(struct blk_desc *dev_desc, int part,
+ int (*get_info)(struct blk_desc *desc, int part,
struct disk_partition *info);
/**
- * print() - Print partition information
+ * @print: Print partition information
*
- * @dev_desc: Block device descriptor
+ * @print.desc: Block device descriptor
*/
- void (*print)(struct blk_desc *dev_desc);
+ void (*print)(struct blk_desc *desc);
/**
- * test() - Test if a device contains this partition type
+ * @test: Test if a device contains this partition type
*
- * @dev_desc: Block device descriptor
- * @return 0 if the block device appears to contain this partition
- * type, -ve if not
+ * @test.desc: Block device descriptor
+ * @test.Return:
+ * 0 if the block device appears to contain this partition type,
+ * -ve if not
*/
- int (*test)(struct blk_desc *dev_desc);
+ int (*test)(struct blk_desc *desc);
};
/* Declare a new U-Boot partition 'driver' */
@@ -413,100 +476,98 @@
/**
* write_gpt_table() - Write the GUID Partition Table to disk
*
- * @param dev_desc - block device descriptor
- * @param gpt_h - pointer to GPT header representation
- * @param gpt_e - pointer to GPT partition table entries
+ * @desc: block device descriptor
+ * @gpt_h: pointer to GPT header representation
+ * @gpt_e: pointer to GPT partition table entries
*
- * Return: - zero on success, otherwise error
+ * Return: zero on success, otherwise error
*/
-int write_gpt_table(struct blk_desc *dev_desc,
- gpt_header *gpt_h, gpt_entry *gpt_e);
+int write_gpt_table(struct blk_desc *desc, gpt_header *gpt_h, gpt_entry *gpt_e);
/**
- * gpt_fill_pte(): Fill the GPT partition table entry
+ * gpt_fill_pte() - Fill the GPT partition table entry
*
- * @param dev_desc - block device descriptor
- * @param gpt_h - GPT header representation
- * @param gpt_e - GPT partition table entries
- * @param partitions - list of partitions
- * @param parts - number of partitions
+ * @desc: block device descriptor
+ * @gpt_h: GPT header representation
+ * @gpt_e: GPT partition table entries
+ * @partitions: list of partitions
+ * @parts: number of partitions
*
- * Return: zero on success
+ * Return: zero on success
*/
-int gpt_fill_pte(struct blk_desc *dev_desc,
- gpt_header *gpt_h, gpt_entry *gpt_e,
+int gpt_fill_pte(struct blk_desc *desc, gpt_header *gpt_h, gpt_entry *gpt_e,
struct disk_partition *partitions, int parts);
/**
- * gpt_fill_header(): Fill the GPT header
+ * gpt_fill_header() - Fill the GPT header
*
- * @param dev_desc - block device descriptor
- * @param gpt_h - GPT header representation
- * @param str_guid - disk guid string representation
- * @param parts_count - number of partitions
+ * @desc: block device descriptor
+ * @gpt_h: GPT header representation
+ * @str_guid: disk guid string representation
+ * @parts_count: number of partitions
*
- * Return: - error on str_guid conversion error
+ * Return: error on str_guid conversion error
*/
-int gpt_fill_header(struct blk_desc *dev_desc, gpt_header *gpt_h,
- char *str_guid, int parts_count);
+int gpt_fill_header(struct blk_desc *desc, gpt_header *gpt_h, char *str_guid,
+ int parts_count);
/**
- * gpt_restore(): Restore GPT partition table
+ * gpt_restore() - Restore GPT partition table
*
- * @param dev_desc - block device descriptor
- * @param str_disk_guid - disk GUID
- * @param partitions - list of partitions
- * @param parts - number of partitions
+ * @desc: block device descriptor
+ * @str_disk_guid: disk GUID
+ * @partitions: list of partitions
+ * @parts_count: number of partitions
*
- * Return: zero on success
+ * Return: 0 on success
*/
-int gpt_restore(struct blk_desc *dev_desc, char *str_disk_guid,
+int gpt_restore(struct blk_desc *desc, char *str_disk_guid,
struct disk_partition *partitions, const int parts_count);
/**
* is_valid_gpt_buf() - Ensure that the Primary GPT information is valid
*
- * @param dev_desc - block device descriptor
- * @param buf - buffer which contains the MBR and Primary GPT info
+ * @desc: block device descriptor
+ * @buf: buffer which contains the MBR and Primary GPT info
*
- * Return: - '0' on success, otherwise error
+ * Return: 0 on success, otherwise error
*/
-int is_valid_gpt_buf(struct blk_desc *dev_desc, void *buf);
+int is_valid_gpt_buf(struct blk_desc *desc, void *buf);
/**
* write_mbr_and_gpt_partitions() - write MBR, Primary GPT and Backup GPT
*
- * @param dev_desc - block device descriptor
- * @param buf - buffer which contains the MBR and Primary GPT info
+ * @desc: block device descriptor
+ * @buf: buffer which contains the MBR and Primary GPT info
*
- * Return: - '0' on success, otherwise error
+ * Return: 0 on success, otherwise error
*/
-int write_mbr_and_gpt_partitions(struct blk_desc *dev_desc, void *buf);
+int write_mbr_and_gpt_partitions(struct blk_desc *desc, void *buf);
/**
- * gpt_verify_headers() - Function to read and CRC32 check of the GPT's header
+ * gpt_verify_headers() - Read and check CRC32 of the GPT's header
* and partition table entries (PTE)
*
* As a side effect if sets gpt_head and gpt_pte so they point to GPT data.
*
- * @param dev_desc - block device descriptor
- * @param gpt_head - pointer to GPT header data read from medium
- * @param gpt_pte - pointer to GPT partition table enties read from medium
+ * @desc: block device descriptor
+ * @gpt_head: pointer to GPT header data read from medium
+ * @gpt_pte: pointer to GPT partition table enties read from medium
*
- * Return: - '0' on success, otherwise error
+ * Return: 0 on success, otherwise error
*/
-int gpt_verify_headers(struct blk_desc *dev_desc, gpt_header *gpt_head,
+int gpt_verify_headers(struct blk_desc *desc, gpt_header *gpt_head,
gpt_entry **gpt_pte);
/**
* gpt_repair_headers() - Function to repair the GPT's header
* and partition table entries (PTE)
*
- * @param dev_desc - block device descriptor
+ * @desc: block device descriptor
*
- * Return: - '0' on success, otherwise error
+ * Return: 0 on success, otherwise error
*/
-int gpt_repair_headers(struct blk_desc *dev_desc);
+int gpt_repair_headers(struct blk_desc *desc);
/**
* gpt_verify_partitions() - Function to check if partitions' name, start and
@@ -516,31 +577,31 @@
* provided in '$partitions' environment variable. Specificially, name, start
* and size of the partition is checked.
*
- * @param dev_desc - block device descriptor
- * @param partitions - partition data read from '$partitions' env variable
- * @param parts - number of partitions read from '$partitions' env variable
- * @param gpt_head - pointer to GPT header data read from medium
- * @param gpt_pte - pointer to GPT partition table enties read from medium
+ * @desc: block device descriptor
+ * @partitions: partition data read from '$partitions' env variable
+ * @parts: number of partitions read from '$partitions' env variable
+ * @gpt_head: pointer to GPT header data read from medium
+ * @gpt_pte: pointer to GPT partition table enties read from medium
*
- * Return: - '0' on success, otherwise error
+ * Return: 0 on success, otherwise error
*/
-int gpt_verify_partitions(struct blk_desc *dev_desc,
+int gpt_verify_partitions(struct blk_desc *desc,
struct disk_partition *partitions, int parts,
gpt_header *gpt_head, gpt_entry **gpt_pte);
/**
- * get_disk_guid() - Function to read the GUID string from a device's GPT
+ * get_disk_guid() - Read the GUID string from a device's GPT
*
* This function reads the GUID string from a block device whose descriptor
* is provided.
*
- * @param dev_desc - block device descriptor
- * @param guid - pre-allocated string in which to return the GUID
+ * @desc: block device descriptor
+ * @guid: pre-allocated string in which to return the GUID
*
- * Return: - '0' on success, otherwise error
+ * Return: 0 on success, otherwise error
*/
-int get_disk_guid(struct blk_desc *dev_desc, char *guid);
+int get_disk_guid(struct blk_desc *desc, char *guid);
#endif
@@ -548,21 +609,21 @@
/**
* is_valid_dos_buf() - Ensure that a DOS MBR image is valid
*
- * @param buf - buffer which contains the MBR
+ * @buf: buffer which contains the MBR
*
- * Return: - '0' on success, otherwise error
+ * Return: 0 on success, otherwise error
*/
int is_valid_dos_buf(void *buf);
/**
* write_mbr_sector() - write DOS MBR
*
- * @param dev_desc - block device descriptor
- * @param buf - buffer which contains the MBR
+ * @desc: block device descriptor
+ * @buf: buffer which contains the MBR
*
- * Return: - '0' on success, otherwise error
+ * Return: 0 on success, otherwise error
*/
-int write_mbr_sector(struct blk_desc *dev_desc, void *buf);
+int write_mbr_sector(struct blk_desc *desc, void *buf);
int write_mbr_partitions(struct blk_desc *dev,
struct disk_partition *p, int count, unsigned int disksig);
@@ -575,7 +636,7 @@
/**
* part_driver_get_count() - get partition driver count
*
- * Return: - number of partition drivers
+ * Return: number of partition drivers
*/
static inline int part_driver_get_count(void)
{
@@ -585,7 +646,7 @@
/**
* part_driver_get_first() - get first partition driver
*
- * Return: - pointer to first partition driver on success, otherwise NULL
+ * Return: pointer to first partition driver on success, otherwise NULL
*/
static inline struct part_driver *part_driver_get_first(void)
{
@@ -595,18 +656,30 @@
/**
* part_get_type_by_name() - Get partition type by name
*
- * @name: Name of partition type to look up (not case-sensitive)
- * Returns: Corresponding partition type (PART_TYPE_...) or PART_TYPE_UNKNOWN if
- * not known
+ * @name: Name of partition type to look up (not case-sensitive)
+ * Return:
+ * Corresponding partition type (PART\_TYPE\_...) or PART\_TYPE\_UNKNOWN
*/
int part_get_type_by_name(const char *name);
+/**
+ * part_get_bootable() - Find the first bootable partition
+ *
+ * @desc: Block-device descriptor
+ * @return first bootable partition, or 0 if there is none
+ */
+int part_get_bootable(struct blk_desc *desc);
+
#else
static inline int part_driver_get_count(void)
{ return 0; }
static inline struct part_driver *part_driver_get_first(void)
{ return NULL; }
+
+static inline bool part_get_bootable(struct blk_desc *desc)
+{ return false; }
+
#endif /* CONFIG_PARTITIONS */
#endif /* _PART_H */
diff --git a/include/part_efi.h b/include/part_efi.h
index c68529b..59b7895 100644
--- a/include/part_efi.h
+++ b/include/part_efi.h
@@ -60,6 +60,20 @@
EFI_GUID( 0x3de21764, 0x95bd, 0x54bd, \
0xa5, 0xc3, 0x4a, 0xbe, 0x78, 0x6f, 0x38, 0xa8)
+/* Special ChromiumOS things */
+#define PARTITION_CROS_KERNEL \
+ EFI_GUID(0xfe3a2a5d, 0x4f32, 0x41a7, \
+ 0xb7, 0x25, 0xac, 0xcc, 0x32, 0x85, 0xa3, 0x09)
+#define PARTITION_CROS_ROOT \
+ EFI_GUID(0x3cb8e202, 0x3b7e, 0x47dd, \
+ 0x8a, 0x3c, 0x7f, 0xf2, 0xa1, 0x3c, 0xfc, 0xec)
+#define PARTITION_CROS_FIRMWARE \
+ EFI_GUID(0xcab6e88e, 0xabf3, 0x4102, \
+ 0xa0, 0x7a, 0xd4, 0xbb, 0x9b, 0xe3, 0xc1, 0xd3)
+#define PARTITION_CROS_RESERVED \
+ EFI_GUID(0x2e0a753d, 0x9e48, 0x43b0, \
+ 0x83, 0x37, 0xb1, 0x51, 0x92, 0xcb, 0x1b, 0x5e)
+
/* linux/include/efi.h */
typedef u16 efi_char16_t;
diff --git a/include/sandbox_efi_capsule.h b/include/sandbox_efi_capsule.h
new file mode 100644
index 0000000..3e288e8
--- /dev/null
+++ b/include/sandbox_efi_capsule.h
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#if !defined(_SANDBOX_EFI_CAPSULE_H_)
+#define _SANDBOX_EFI_CAPSULE_H_
+
+#define SANDBOX_UBOOT_IMAGE_GUID "09d7cf52-0720-4710-91d1-08469b7fe9c8"
+#define SANDBOX_UBOOT_ENV_IMAGE_GUID "5a7021f5-fef2-48b4-aaba-832e777418c0"
+#define SANDBOX_FIT_IMAGE_GUID "3673b45d-6a7c-46f3-9e60-adabb03f7937"
+#define SANDBOX_INCORRECT_GUID "058b7d83-50d5-4c47-a195-60d86ad341c4"
+
+#define UBOOT_FIT_IMAGE "u-boot_bin_env.itb"
+
+#define CAPSULE_PRIV_KEY "capsule_priv_key_good.key"
+#define CAPSULE_PUB_KEY "capsule_pub_key_good.crt"
+#define CAPSULE_INVAL_KEY "capsule_priv_key_bad.key"
+#define CAPSULE_INVAL_PUB_KEY "capsule_pub_key_bad.crt"
+
+#endif /* _SANDBOX_EFI_CAPSULE_H_ */
diff --git a/include/scsi.h b/include/scsi.h
index 9efefea..ee9d622 100644
--- a/include/scsi.h
+++ b/include/scsi.h
@@ -7,6 +7,7 @@
#define _SCSI_H
#include <asm/cache.h>
+#include <bouncebuf.h>
#include <linux/dma-direction.h>
/* Fix this to the maximum */
@@ -298,6 +299,24 @@
* @return 0 if OK, -ve on error
*/
int (*bus_reset)(struct udevice *dev);
+
+#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
+ /**
+ * buffer_aligned() - test memory alignment of block operation buffer
+ *
+ * Some devices have limited DMA capabilities and require that the
+ * buffers passed to them fit specific properties. This optional
+ * callback can be used to indicate whether a buffer alignment is
+ * suitable for the device DMA or not, and trigger use of generic
+ * bounce buffer implementation to help use of unsuitable buffers
+ * at the expense of performance degradation.
+ *
+ * @dev: Block device associated with the request
+ * @state: Bounce buffer state
+ * @return 1 if OK, 0 if unaligned
+ */
+ int (*buffer_aligned)(struct udevice *dev, struct bounce_buffer *state);
+#endif /* CONFIG_BOUNCE_BUFFER */
};
#define scsi_get_ops(dev) ((struct scsi_ops *)(dev)->driver->ops)
diff --git a/include/stdio_dev.h b/include/stdio_dev.h
index 77bf8a8..7f18102 100644
--- a/include/stdio_dev.h
+++ b/include/stdio_dev.h
@@ -84,8 +84,6 @@
*/
int stdio_add_devices(void);
-void stdio_print_current_devices(void);
-
/**
* stdio_deregister_dev() - deregister the device "devname".
*
diff --git a/include/usb.h b/include/usb.h
index 42b001c..09e3f0c 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -257,7 +257,14 @@
#endif
/* routines */
-int usb_init(void); /* initialize the USB Controller */
+
+/*
+ * usb_init() - initialize the USB Controllers
+ *
+ * Returns: 0 if OK, -ENOENT if there are no USB devices
+ */
+int usb_init(void);
+
int usb_stop(void); /* stop the USB Controller */
int usb_detect_change(void); /* detect if a USB device has been (un)plugged */
diff --git a/include/uuid.h b/include/uuid.h
index 4a4883d..f5a9412 100644
--- a/include/uuid.h
+++ b/include/uuid.h
@@ -2,12 +2,61 @@
/*
* Copyright (C) 2014 Samsung Electronics
* Przemyslaw Marczak <p.marczak@samsung.com>
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
*/
#ifndef __UUID_H__
#define __UUID_H__
#include <linux/bitops.h>
+/*
+ * UUID - Universally Unique IDentifier - 128 bits unique number.
+ * There are 5 versions and one variant of UUID defined by RFC4122
+ * specification. A UUID contains a set of fields. The set varies
+ * depending on the version of the UUID, as shown below:
+ * - time, MAC address(v1),
+ * - user ID(v2),
+ * - MD5 of name or URL(v3),
+ * - random data(v4),
+ * - SHA-1 of name or URL(v5),
+ *
+ * Layout of UUID:
+ * timestamp - 60-bit: time_low, time_mid, time_hi_and_version
+ * version - 4 bit (bit 4 through 7 of the time_hi_and_version)
+ * clock seq - 14 bit: clock_seq_hi_and_reserved, clock_seq_low
+ * variant: - bit 6 and 7 of clock_seq_hi_and_reserved
+ * node - 48 bit
+ *
+ * source: https://www.ietf.org/rfc/rfc4122.txt
+ *
+ * UUID binary format (16 bytes):
+ *
+ * 4B-2B-2B-2B-6B (big endian - network byte order)
+ *
+ * UUID string is 36 length of characters (36 bytes):
+ *
+ * 0 9 14 19 24
+ * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
+ * be be be be be
+ *
+ * where x is a hexadecimal character. Fields are separated by '-'s.
+ * When converting to a binary UUID, le means the field should be converted
+ * to little endian and be means it should be converted to big endian.
+ *
+ * UUID is also used as GUID (Globally Unique Identifier) with the same binary
+ * format but it differs in string format like below.
+ *
+ * GUID:
+ * 0 9 14 19 24
+ * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
+ * le le le be be
+ *
+ * GUID is used e.g. in GPT (GUID Partition Table) as a partiions unique id.
+ */
+
/* This is structure is in big-endian */
struct uuid {
unsigned int time_low;
@@ -36,12 +85,81 @@
#define UUID_VARIANT 0x1
int uuid_str_valid(const char *uuid);
+
+/*
+ * uuid_str_to_bin() - convert string UUID or GUID to big endian binary data.
+ *
+ * @param uuid_str - pointer to UUID or GUID string [37B] or GUID shorcut
+ * @param uuid_bin - pointer to allocated array for big endian output [16B]
+ * @str_format - UUID string format: 0 - UUID; 1 - GUID
+ * Return: 0 if OK, -EINVAL if the string is not a valid UUID
+ */
int uuid_str_to_bin(const char *uuid_str, unsigned char *uuid_bin,
int str_format);
+
+/*
+ * uuid_bin_to_str() - convert big endian binary data to string UUID or GUID.
+ *
+ * @param uuid_bin: pointer to binary data of UUID (big endian) [16B]
+ * @param uuid_str: pointer to allocated array for output string [37B]
+ * @str_format: bit 0: 0 - UUID; 1 - GUID
+ * bit 1: 0 - lower case; 2 - upper case
+ */
void uuid_bin_to_str(const unsigned char *uuid_bin, char *uuid_str,
int str_format);
+
+/*
+ * uuid_guid_get_bin() - this function get GUID bin for string
+ *
+ * @param guid_str - pointer to partition type string
+ * @param guid_bin - pointer to allocated array for big endian output [16B]
+ */
int uuid_guid_get_bin(const char *guid_str, unsigned char *guid_bin);
+
+/*
+ * uuid_guid_get_str() - this function get string for GUID.
+ *
+ * @param guid_bin - pointer to string with partition type guid [16B]
+ *
+ * Returns NULL if the type GUID is not known.
+ */
const char *uuid_guid_get_str(const unsigned char *guid_bin);
+
+/*
+ * gen_rand_uuid() - this function generates a random binary UUID version 4.
+ * In this version all fields beside 4 bits of version and
+ * 2 bits of variant are randomly generated.
+ *
+ * @param uuid_bin - pointer to allocated array [16B]. Output is in big endian.
+ */
void gen_rand_uuid(unsigned char *uuid_bin);
+
+/*
+ * gen_rand_uuid_str() - this function generates UUID v4 (random) in two string
+ * formats UUID or GUID.
+ *
+ * @param uuid_str - pointer to allocated array [37B].
+ * @param - uuid output type: UUID - 0, GUID - 1
+ */
void gen_rand_uuid_str(char *uuid_str, int str_format);
+
+/**
+ * uuid_str_to_le_bin() - Convert string UUID to little endian binary data.
+ * @uuid_str: pointer to UUID string
+ * @uuid_bin: pointer to allocated array for little endian output [16B]
+ *
+ * UUID string is 36 characters (36 bytes):
+ *
+ * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
+ *
+ * where x is a hexadecimal character. Fields are separated by '-'s.
+ * When converting to a little endian binary UUID, the string fields are reversed.
+ *
+ * Return:
+ *
+ * uuid_bin filled with little endian UUID data
+ * On success 0 is returned. Otherwise, failure code.
+ */
+int uuid_str_to_le_bin(const char *uuid_str, unsigned char *uuid_bin);
+
#endif
diff --git a/include/video.h b/include/video.h
index 2699151..66d109c 100644
--- a/include/video.h
+++ b/include/video.h
@@ -58,7 +58,7 @@
* Convert enum video_log2_bpp to bytes and bits. Note we omit the outer
* brackets to allow multiplication by fractional pixels.
*/
-#define VNBYTES(bpix) (1 << (bpix)) / 8
+#define VNBYTES(bpix) ((1 << (bpix)) / 8)
#define VNBITS(bpix) (1 << (bpix))
diff --git a/lib/Kconfig b/lib/Kconfig
index 3926652..42e559a 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -534,6 +534,17 @@
if SPL
+config SPL_CRC32
+ bool "Enable CRC32 support in SPL"
+ default y if SPL_LEGACY_IMAGE_SUPPORT || SPL_EFI_PARTITION
+ default y if SPL_ENV_SUPPORT || TPL_BLOBLIST
+ help
+ This option enables support of hashing using CRC32 algorithm.
+ The CRC32 algorithm produces 32-bit checksum value. For FIT
+ images, this is the least secure type of checksum, suitable for
+ detected accidental image corruption. For secure applications you
+ should consider SHA256 or SHA384.
+
config SPL_SHA1
bool "Enable SHA1 support in SPL"
default y if SHA1
@@ -851,7 +862,7 @@
config OF_LIBFDT_ASSUME_MASK
hex "Mask of conditions to assume for libfdt"
depends on OF_LIBFDT || FIT
- default 0
+ default 0x0
help
Use this to change the assumptions made by libfdt about the
device tree it is working with. A value of 0 means that no assumptions
diff --git a/lib/abuf.c b/lib/abuf.c
index bd27046..ce2cff5 100644
--- a/lib/abuf.c
+++ b/lib/abuf.c
@@ -82,6 +82,11 @@
}
}
+bool abuf_realloc_inc(struct abuf *abuf, size_t inc)
+{
+ return abuf_realloc(abuf, abuf->size + inc);
+}
+
void *abuf_uninit_move(struct abuf *abuf, size_t *sizep)
{
void *ptr;
diff --git a/lib/charset.c b/lib/charset.c
index b184275..5e4c4f9 100644
--- a/lib/charset.c
+++ b/lib/charset.c
@@ -444,14 +444,14 @@
size_t u16_strlcat(u16 *dest, const u16 *src, size_t count)
{
- size_t destlen = u16_strlen(dest);
+ size_t destlen = u16_strnlen(dest, count);
size_t srclen = u16_strlen(src);
- size_t ret = destlen + srclen + 1;
+ size_t ret = destlen + srclen;
if (destlen >= count)
return ret;
- if (ret > count)
- srclen -= ret - count;
+ if (ret >= count)
+ srclen -= (ret - count + 1);
memcpy(&dest[destlen], src, 2 * srclen);
dest[destlen + srclen] = 0x0000;
diff --git a/lib/crc32.c b/lib/crc32.c
index aa94d70..f6fad8c 100644
--- a/lib/crc32.c
+++ b/lib/crc32.c
@@ -10,7 +10,6 @@
#ifdef USE_HOSTCC
#include <arpa/inet.h>
-#include <u-boot/crc.h>
#else
#include <common.h>
#include <efi_loader.h>
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index a22e476..d20aaab 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -55,13 +55,50 @@
stored as file /ubootefi.var on the EFI system partition.
config EFI_MM_COMM_TEE
- bool "UEFI variables storage service via OP-TEE"
+ bool "UEFI variables storage service via the trusted world"
depends on OPTEE
help
+ Allowing access to the MM SP services (SPs such as StandAlonneMM, smm-gateway).
+ When using the u-boot OP-TEE driver, StandAlonneMM is supported.
+ When using the u-boot FF-A driver any MM SP is supported.
+
If OP-TEE is present and running StandAloneMM, dispatch all UEFI
variable related operations to that. The application will verify,
authenticate and store the variables on an RPMB.
+ When ARM_FFA_TRANSPORT is used, dispatch all UEFI variable related
+ operations to the MM SP running in the secure world.
+ A door bell mechanism is used to notify the SP when there is data in the shared
+ MM buffer. The data is copied by u-boot to the shared buffer before issuing
+ the door bell event.
+
+config FFA_SHARED_MM_BUF_SIZE
+ int "Memory size of the shared MM communication buffer"
+ depends on EFI_MM_COMM_TEE && ARM_FFA_TRANSPORT
+ help
+ This defines the size in bytes of the memory area reserved for the shared
+ buffer used for communication between the MM feature in U-Boot and
+ the MM SP in secure world.
+ The size of the memory region must be a multiple of the size of the maximum
+ translation granule size that is specified in the ID_AA64MMFR0_EL1 System register.
+ It is assumed that the MM SP knows the size of the shared MM communication buffer.
+
+config FFA_SHARED_MM_BUF_OFFSET
+ int "Data offset in the shared MM communication buffer"
+ depends on EFI_MM_COMM_TEE && ARM_FFA_TRANSPORT
+ help
+ This defines the offset in bytes of the data read or written to in the shared
+ buffer by the MM SP.
+
+config FFA_SHARED_MM_BUF_ADDR
+ hex "Define the address of the shared MM communication buffer"
+ depends on EFI_MM_COMM_TEE && ARM_FFA_TRANSPORT
+ help
+ This defines the address of the shared MM communication buffer
+ used for communication between the MM feature in U-Boot and
+ the MM SP in secure world.
+ It is assumed that the MM SP knows the address of the shared MM communication buffer.
+
config EFI_VARIABLE_NO_STORE
bool "Don't persist non-volatile UEFI variables"
help
@@ -235,6 +272,14 @@
Select the max capsule index value used for capsule report
variables. This value is used to create CapsuleMax variable.
+config EFI_CAPSULE_ESL_FILE
+ string "Path to the EFI Signature List File"
+ depends on EFI_CAPSULE_AUTHENTICATE
+ help
+ Provides the path to the EFI Signature List file which will
+ be embedded in the platform's device tree and used for
+ capsule authentication at the time of capsule update.
+
config EFI_DEVICE_PATH_TO_TEXT
bool "Device path to text protocol"
default y
diff --git a/lib/efi_loader/capsule_esl.dtsi.in b/lib/efi_loader/capsule_esl.dtsi.in
new file mode 100644
index 0000000..61a9f2b
--- /dev/null
+++ b/lib/efi_loader/capsule_esl.dtsi.in
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * Devicetree file with the public key EFI Signature List(ESL)
+ * node. This file is used to generate the dtsi file to be
+ * included into the DTB.
+*/
+/ {
+ signature {
+ capsule-key = /incbin/("ESL_BIN_FILE");
+ };
+};
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 7a6f195..af8a2ee 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -368,9 +368,8 @@
auth_hdr->auth_info.hdr.dwLength
- sizeof(auth_hdr->auth_info),
&buf);
- if (IS_ERR(capsule_sig)) {
+ if (!capsule_sig) {
debug("Parsing variable's pkcs7 header failed\n");
- capsule_sig = NULL;
goto out;
}
@@ -581,6 +580,13 @@
fw_accept_os = capsule_data->flags & FW_ACCEPT_OS ? 0x1 : 0x0;
}
+ if (guidcmp(&capsule_data->capsule_guid,
+ &efi_guid_firmware_management_capsule_id)) {
+ log_err("Unsupported capsule type: %pUs\n",
+ &capsule_data->capsule_guid);
+ return EFI_UNSUPPORTED;
+ }
+
/* sanity check */
if (capsule_data->header_size < sizeof(*capsule) ||
capsule_data->header_size >= capsule_data->capsule_image_size)
@@ -751,15 +757,7 @@
log_debug("Capsule[%d] (guid:%pUs)\n",
i, &capsule->capsule_guid);
- if (!guidcmp(&capsule->capsule_guid,
- &efi_guid_firmware_management_capsule_id)) {
- ret = efi_capsule_update_firmware(capsule);
- } else {
- log_err("Unsupported capsule type: %pUs\n",
- &capsule->capsule_guid);
- ret = EFI_UNSUPPORTED;
- }
-
+ ret = efi_capsule_update_firmware(capsule);
if (ret != EFI_SUCCESS)
goto out;
}
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index 46cb570..f0d7611 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -487,15 +487,16 @@
*/
if ((part || desc->part_type == PART_TYPE_UNKNOWN) &&
efi_fs_exists(desc, part)) {
- diskobj->volume = efi_simple_file_system(desc, part,
- diskobj->dp);
+ ret = efi_create_simple_file_system(desc, part, diskobj->dp,
+ &diskobj->volume);
+ if (ret != EFI_SUCCESS)
+ goto error;
+
ret = efi_add_protocol(&diskobj->header,
&efi_simple_file_system_protocol_guid,
diskobj->volume);
- if (ret != EFI_SUCCESS) {
- log_debug("simple FS failed\n");
- return ret;
- }
+ if (ret != EFI_SUCCESS)
+ goto error;
}
diskobj->ops = block_io_disk_template;
diskobj->dev_index = dev_index;
@@ -538,6 +539,8 @@
return EFI_SUCCESS;
error:
efi_delete_handle(&diskobj->header);
+ free(diskobj->volume);
+ free(diskobj);
return ret;
}
diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c
index 520c730..3c56ceb 100644
--- a/lib/efi_loader/efi_file.c
+++ b/lib/efi_loader/efi_file.c
@@ -195,6 +195,8 @@
/* +2 is for null and '/' */
fh = calloc(1, sizeof(*fh) + plen + (flen * MAX_UTF8_PER_UTF16) + 2);
+ if (!fh)
+ return NULL;
fh->open_mode = open_mode;
fh->base = efi_file_handle_protocol;
@@ -1192,18 +1194,22 @@
return EFI_EXIT(efi_open_volume_int(this, root));
}
-struct efi_simple_file_system_protocol *
-efi_simple_file_system(struct blk_desc *desc, int part,
- struct efi_device_path *dp)
+efi_status_t
+efi_create_simple_file_system(struct blk_desc *desc, int part,
+ struct efi_device_path *dp,
+ struct efi_simple_file_system_protocol **fsp)
{
struct file_system *fs;
fs = calloc(1, sizeof(*fs));
+ if (!fs)
+ return EFI_OUT_OF_RESOURCES;
fs->base.rev = EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION;
fs->base.open_volume = efi_open_volume;
fs->desc = desc;
fs->part = part;
fs->dp = dp;
+ *fsp = &fs->base;
- return &fs->base;
+ return EFI_SUCCESS;
}
diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
index b557738..9abb29f 100644
--- a/lib/efi_loader/efi_firmware.c
+++ b/lib/efi_loader/efi_firmware.c
@@ -159,7 +159,7 @@
const fdt32_t *val;
const char *guid_str;
int len, offset, index;
- int parent;
+ int parent, ret;
*lsv = 0;
@@ -173,7 +173,11 @@
guid_str = fdt_getprop(fdt, offset, "image-type-id", &len);
if (!guid_str)
continue;
- uuid_str_to_bin(guid_str, guid.b, UUID_STR_FORMAT_GUID);
+ ret = uuid_str_to_bin(guid_str, guid.b, UUID_STR_FORMAT_GUID);
+ if (ret < 0) {
+ log_warning("Wrong image-type-id format.\n");
+ continue;
+ }
val = fdt_getprop(fdt, offset, "image-index", &len);
if (!val)
diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c
index 26df0da..9754757 100644
--- a/lib/efi_loader/efi_image_loader.c
+++ b/lib/efi_loader/efi_image_loader.c
@@ -592,6 +592,7 @@
struct efi_signature_store *db = NULL, *dbx = NULL;
void *new_efi = NULL;
u8 *auth, *wincerts_end;
+ u64 new_efi_size = efi_size;
size_t auth_size;
bool ret = false;
@@ -600,11 +601,11 @@
if (!efi_secure_boot_enabled())
return true;
- new_efi = efi_prepare_aligned_image(efi, (u64 *)&efi_size);
+ new_efi = efi_prepare_aligned_image(efi, &new_efi_size);
if (!new_efi)
return false;
- if (!efi_image_parse(new_efi, efi_size, ®s, &wincerts,
+ if (!efi_image_parse(new_efi, new_efi_size, ®s, &wincerts,
&wincerts_len)) {
log_err("Parsing PE executable image failed\n");
goto out;
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index e2ca78d..f752703 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -34,6 +34,7 @@
#define EFI_CARVE_NO_OVERLAP -1
#define EFI_CARVE_LOOP_AGAIN -2
#define EFI_CARVE_OVERLAPS_NONRAM -3
+#define EFI_CARVE_OUT_OF_RESOURCES -4
/* This list contains all memory map items */
static LIST_HEAD(efi_mem);
@@ -239,6 +240,8 @@
/* Create a new map from [ carve_start ... map_end ] */
newmap = calloc(1, sizeof(*newmap));
+ if (!newmap)
+ return EFI_CARVE_OUT_OF_RESOURCES;
newmap->desc = map->desc;
newmap->desc.physical_start = carve_start;
newmap->desc.virtual_start = carve_start;
@@ -282,6 +285,8 @@
++efi_memory_map_key;
newlist = calloc(1, sizeof(*newlist));
+ if (!newlist)
+ return EFI_OUT_OF_RESOURCES;
newlist->desc.type = memory_type;
newlist->desc.physical_start = start;
newlist->desc.virtual_start = start;
@@ -311,11 +316,15 @@
r = efi_mem_carve_out(lmem, &newlist->desc,
overlap_only_ram);
switch (r) {
+ case EFI_CARVE_OUT_OF_RESOURCES:
+ free(newlist);
+ return EFI_OUT_OF_RESOURCES;
case EFI_CARVE_OVERLAPS_NONRAM:
/*
* The user requested to only have RAM overlaps,
* but we hit a non-RAM region. Error out.
*/
+ free(newlist);
return EFI_NO_MAPPING;
case EFI_CARVE_NO_OVERLAP:
/* Just ignore this list entry */
@@ -346,6 +355,7 @@
* The payload wanted to have RAM overlaps, but we overlapped
* with an unallocated region. Error out.
*/
+ free(newlist);
return EFI_NO_MAPPING;
}
@@ -487,7 +497,7 @@
enum efi_memory_type memory_type,
efi_uintn_t pages, uint64_t *memory)
{
- u64 len = pages << EFI_PAGE_SHIFT;
+ u64 len;
efi_status_t ret;
uint64_t addr;
@@ -497,6 +507,11 @@
return EFI_INVALID_PARAMETER;
if (!memory)
return EFI_INVALID_PARAMETER;
+ len = (u64)pages << EFI_PAGE_SHIFT;
+ /* Catch possible overflow on 64bit systems */
+ if (sizeof(efi_uintn_t) == sizeof(u64) &&
+ (len >> EFI_PAGE_SHIFT) != (u64)pages)
+ return EFI_OUT_OF_RESOURCES;
switch (type) {
case EFI_ALLOCATE_ANY_PAGES:
@@ -862,7 +877,7 @@
*/
__weak void efi_add_known_memory(void)
{
- u64 ram_top = board_get_usable_ram_top(0) & ~EFI_PAGE_MASK;
+ u64 ram_top = gd->ram_top & ~EFI_PAGE_MASK;
int i;
/*
diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c
index 49f8a5e..7b7926a 100644
--- a/lib/efi_loader/efi_tcg2.c
+++ b/lib/efi_loader/efi_tcg2.c
@@ -706,8 +706,7 @@
sha512_finish(&ctx_512, final);
break;
default:
- EFI_PRINT("Unsupported algorithm %x\n", hash_alg);
- return EFI_INVALID_PARAMETER;
+ continue;
}
digest_list->digests[digest_list->count].hash_alg = hash_alg;
memcpy(&digest_list->digests[digest_list->count].digest, final,
@@ -930,8 +929,7 @@
hash_calculate("sha512", regs->reg, regs->num, hash);
break;
default:
- EFI_PRINT("Unsupported algorithm %x\n", hash_alg);
- return EFI_INVALID_PARAMETER;
+ continue;
}
digest_list->digests[digest_list->count].hash_alg = hash_alg;
memcpy(&digest_list->digests[digest_list->count].digest, hash,
diff --git a/lib/efi_loader/efi_variable_tee.c b/lib/efi_loader/efi_variable_tee.c
index dfef184..09d03c0 100644
--- a/lib/efi_loader/efi_variable_tee.c
+++ b/lib/efi_loader/efi_variable_tee.c
@@ -4,16 +4,38 @@
*
* Copyright (C) 2019 Linaro Ltd. <sughosh.ganu@linaro.org>
* Copyright (C) 2019 Linaro Ltd. <ilias.apalodimas@linaro.org>
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
*/
#include <common.h>
+#if CONFIG_IS_ENABLED(ARM_FFA_TRANSPORT)
+#include <arm_ffa.h>
+#endif
+#include <cpu_func.h>
+#include <dm.h>
#include <efi.h>
#include <efi_api.h>
#include <efi_loader.h>
#include <efi_variable.h>
-#include <tee.h>
#include <malloc.h>
+#include <mapmem.h>
#include <mm_communication.h>
+#include <tee.h>
+
+#if CONFIG_IS_ENABLED(ARM_FFA_TRANSPORT)
+/* MM return codes */
+#define MM_SUCCESS (0)
+#define MM_NOT_SUPPORTED (-1)
+#define MM_INVALID_PARAMETER (-2)
+#define MM_DENIED (-3)
+#define MM_NO_MEMORY (-5)
+
+static const char *mm_sp_svc_uuid = MM_SP_UUID;
+static u16 mm_sp_id;
+#endif
extern struct efi_var_file __efi_runtime_data *efi_var_buf;
static efi_uintn_t max_buffer_size; /* comm + var + func + data */
@@ -144,12 +166,238 @@
return ret;
}
+#if CONFIG_IS_ENABLED(ARM_FFA_TRANSPORT)
/**
- * mm_communicate() - Adjust the cmonnucation buffer to StandAlonneMM and send
+ * ffa_notify_mm_sp() - Announce there is data in the shared buffer
+ *
+ * Notify the MM partition in the trusted world that
+ * data is available in the shared buffer.
+ * This is a blocking call during which trusted world has exclusive access
+ * to the MM shared buffer.
+ *
+ * Return:
+ *
+ * 0 on success
+ */
+static int ffa_notify_mm_sp(void)
+{
+ struct ffa_send_direct_data msg = {0};
+ int ret;
+ int sp_event_ret;
+ struct udevice *dev;
+
+ ret = uclass_first_device_err(UCLASS_FFA, &dev);
+ if (ret) {
+ log_err("EFI: Cannot find FF-A bus device, notify MM SP failure\n");
+ return ret;
+ }
+
+ msg.data0 = CONFIG_FFA_SHARED_MM_BUF_OFFSET; /* x3 */
+
+ ret = ffa_sync_send_receive(dev, mm_sp_id, &msg, 1);
+ if (ret)
+ return ret;
+
+ sp_event_ret = msg.data0; /* x3 */
+
+ switch (sp_event_ret) {
+ case MM_SUCCESS:
+ ret = 0;
+ break;
+ case MM_NOT_SUPPORTED:
+ ret = -EINVAL;
+ break;
+ case MM_INVALID_PARAMETER:
+ ret = -EPERM;
+ break;
+ case MM_DENIED:
+ ret = -EACCES;
+ break;
+ case MM_NO_MEMORY:
+ ret = -EBUSY;
+ break;
+ default:
+ ret = -EACCES;
+ }
+
+ return ret;
+}
+
+/**
+ * ffa_discover_mm_sp_id() - Query the MM partition ID
+ *
+ * Use the FF-A driver to get the MM partition ID.
+ * If multiple partitions are found, use the first one.
+ * This is a boot time function.
+ *
+ * Return:
+ *
+ * 0 on success
+ */
+static int ffa_discover_mm_sp_id(void)
+{
+ u32 count = 0;
+ int ret;
+ struct ffa_partition_desc *descs;
+ struct udevice *dev;
+
+ ret = uclass_first_device_err(UCLASS_FFA, &dev);
+ if (ret) {
+ log_err("EFI: Cannot find FF-A bus device, MM SP discovery failure\n");
+ return ret;
+ }
+
+ /* Ask the driver to fill the buffer with the SPs info */
+ ret = ffa_partition_info_get(dev, mm_sp_svc_uuid, &count, &descs);
+ if (ret) {
+ log_err("EFI: Failure in querying SPs info (%d), MM SP discovery failure\n", ret);
+ return ret;
+ }
+
+ /* MM SPs found , use the first one */
+
+ mm_sp_id = descs[0].info.id;
+
+ log_info("EFI: MM partition ID 0x%x\n", mm_sp_id);
+
+ return 0;
+}
+
+/**
+ * ffa_mm_communicate() - Exchange EFI services data with the MM partition using FF-A
+ * @comm_buf: locally allocated communication buffer used for rx/tx
+ * @dsize: communication buffer size
+ *
+ * Issue a door bell event to notify the MM partition (SP) running in OP-TEE
+ * that there is data to read from the shared buffer.
+ * Communication with the MM SP is performed using FF-A transport.
+ * On the event, MM SP can read the data from the buffer and
+ * update the MM shared buffer with response data.
+ * The response data is copied back to the communication buffer.
+ *
+ * Return:
+ *
+ * EFI status code
+ */
+static efi_status_t ffa_mm_communicate(void *comm_buf, ulong comm_buf_size)
+{
+ ulong tx_data_size;
+ int ffa_ret;
+ efi_status_t efi_ret;
+ struct efi_mm_communicate_header *mm_hdr;
+ void *virt_shared_buf;
+
+ if (!comm_buf)
+ return EFI_INVALID_PARAMETER;
+
+ /* Discover MM partition ID at boot time */
+ if (!mm_sp_id && ffa_discover_mm_sp_id()) {
+ log_err("EFI: Failure to discover MM SP ID at boot time, FF-A MM comms failure\n");
+ return EFI_UNSUPPORTED;
+ }
+
+ mm_hdr = (struct efi_mm_communicate_header *)comm_buf;
+ tx_data_size = mm_hdr->message_len + sizeof(efi_guid_t) + sizeof(size_t);
+
+ if (comm_buf_size != tx_data_size || tx_data_size > CONFIG_FFA_SHARED_MM_BUF_SIZE)
+ return EFI_INVALID_PARAMETER;
+
+ /* Copy the data to the shared buffer */
+
+ virt_shared_buf = map_sysmem((phys_addr_t)CONFIG_FFA_SHARED_MM_BUF_ADDR, 0);
+ memcpy(virt_shared_buf, comm_buf, tx_data_size);
+
+ /*
+ * The secure world might have cache disabled for
+ * the device region used for shared buffer (which is the case for Optee).
+ * In this case, the secure world reads the data from DRAM.
+ * Let's flush the cache so the DRAM is updated with the latest data.
+ */
+#ifdef CONFIG_ARM64
+ invalidate_dcache_all();
+#endif
+
+ /* Announce there is data in the shared buffer */
+
+ ffa_ret = ffa_notify_mm_sp();
+
+ switch (ffa_ret) {
+ case 0: {
+ ulong rx_data_size;
+ /* Copy the MM SP response from the shared buffer to the communication buffer */
+ rx_data_size = ((struct efi_mm_communicate_header *)virt_shared_buf)->message_len +
+ sizeof(efi_guid_t) +
+ sizeof(size_t);
+
+ if (rx_data_size > comm_buf_size) {
+ efi_ret = EFI_OUT_OF_RESOURCES;
+ break;
+ }
+
+ memcpy(comm_buf, virt_shared_buf, rx_data_size);
+ efi_ret = EFI_SUCCESS;
+ break;
+ }
+ case -EINVAL:
+ efi_ret = EFI_DEVICE_ERROR;
+ break;
+ case -EPERM:
+ efi_ret = EFI_INVALID_PARAMETER;
+ break;
+ case -EACCES:
+ efi_ret = EFI_ACCESS_DENIED;
+ break;
+ case -EBUSY:
+ efi_ret = EFI_OUT_OF_RESOURCES;
+ break;
+ default:
+ efi_ret = EFI_ACCESS_DENIED;
+ }
+
+ unmap_sysmem(virt_shared_buf);
+ return efi_ret;
+}
+
+/**
+ * get_mm_comms() - detect the available MM transport
+ *
+ * Make sure the FF-A bus is probed successfully
+ * which means FF-A communication with secure world works and ready
+ * for use.
+ *
+ * If FF-A bus is not ready, use OPTEE comms.
+ *
+ * Return:
+ *
+ * MM_COMMS_FFA or MM_COMMS_OPTEE
+ */
+static enum mm_comms_select get_mm_comms(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_FFA, &dev);
+ if (ret) {
+ log_debug("EFI: Cannot find FF-A bus device, trying Optee comms\n");
+ return MM_COMMS_OPTEE;
+ }
+
+ return MM_COMMS_FFA;
+}
+#endif
+
+/**
+ * mm_communicate() - Adjust the communication buffer to the MM SP and send
* it to OP-TEE
*
- * @comm_buf: locally allocted communcation buffer
+ * @comm_buf: locally allocated communication buffer
* @dsize: buffer size
+ *
+ * The SP (also called partition) can be any MM SP such as StandAlonneMM or smm-gateway.
+ * The comm_buf format is the same for both partitions.
+ * When using the u-boot OP-TEE driver, StandAlonneMM is supported.
+ * When using the u-boot FF-A driver, any MM SP is supported.
+ *
* Return: status code
*/
static efi_status_t mm_communicate(u8 *comm_buf, efi_uintn_t dsize)
@@ -157,12 +405,24 @@
efi_status_t ret;
struct efi_mm_communicate_header *mm_hdr;
struct smm_variable_communicate_header *var_hdr;
+#if CONFIG_IS_ENABLED(ARM_FFA_TRANSPORT)
+ enum mm_comms_select mm_comms;
+#endif
dsize += MM_COMMUNICATE_HEADER_SIZE + MM_VARIABLE_COMMUNICATE_SIZE;
mm_hdr = (struct efi_mm_communicate_header *)comm_buf;
var_hdr = (struct smm_variable_communicate_header *)mm_hdr->data;
+#if CONFIG_IS_ENABLED(ARM_FFA_TRANSPORT)
+ mm_comms = get_mm_comms();
+ if (mm_comms == MM_COMMS_FFA)
+ ret = ffa_mm_communicate(comm_buf, dsize);
+ else
+ ret = optee_mm_communicate(comm_buf, dsize);
+#else
+ ret = optee_mm_communicate(comm_buf, dsize);
+#endif
+
- ret = optee_mm_communicate(comm_buf, dsize);
if (ret != EFI_SUCCESS) {
log_err("%s failed!\n", __func__);
return ret;
@@ -697,7 +957,7 @@
ret = EFI_NOT_FOUND;
if (ret != EFI_SUCCESS)
- log_err("Unable to notify StMM for ExitBootServices\n");
+ log_err("Unable to notify the MM partition for ExitBootServices\n");
free(comm_buf);
/*
diff --git a/lib/efi_selftest/efi_selftest_hii.c b/lib/efi_selftest/efi_selftest_hii.c
index f4b5588..f219c01 100644
--- a/lib/efi_selftest/efi_selftest_hii.c
+++ b/lib/efi_selftest/efi_selftest_hii.c
@@ -220,14 +220,12 @@
if (ret != EFI_BUFFER_TOO_SMALL) {
efi_st_error("list_package_lists returned %u\n",
(unsigned int)ret);
- ret = EFI_ST_FAILURE;
goto out;
}
ret = boottime->allocate_pool(EFI_LOADER_DATA, handles_size,
(void **)&handles);
if (ret != EFI_SUCCESS) {
efi_st_error("AllocatePool failed\n");
- ret = EFI_ST_FAILURE;
goto out;
}
ret = hii_database_protocol->list_package_lists(hii_database_protocol,
@@ -236,7 +234,6 @@
if (ret != EFI_SUCCESS) {
efi_st_error("list_package_lists returned %u\n",
(unsigned int)ret);
- ret = EFI_ST_FAILURE;
goto out;
}
ret = boottime->free_pool(handles);
@@ -254,14 +251,12 @@
if (ret != EFI_BUFFER_TOO_SMALL) {
efi_st_error("list_package_lists returned %u\n",
(unsigned int)ret);
- ret = EFI_ST_FAILURE;
goto out;
}
ret = boottime->allocate_pool(EFI_LOADER_DATA, handles_size,
(void **)&handles);
if (ret != EFI_SUCCESS) {
efi_st_error("AllocatePool failed\n");
- ret = EFI_ST_FAILURE;
goto out;
}
ret = hii_database_protocol->list_package_lists(hii_database_protocol,
@@ -270,13 +265,11 @@
if (ret != EFI_SUCCESS) {
efi_st_error("list_package_lists returned %u\n",
(unsigned int)ret);
- ret = EFI_ST_FAILURE;
goto out;
}
ret = boottime->free_pool(handles);
if (ret != EFI_SUCCESS) {
efi_st_error("FreePool failed\n");
- ret = EFI_ST_FAILURE;
goto out;
}
@@ -289,14 +282,12 @@
if (ret != EFI_BUFFER_TOO_SMALL) {
efi_st_error("list_package_lists returned %u\n",
(unsigned int)ret);
- ret = EFI_ST_FAILURE;
goto out;
}
ret = boottime->allocate_pool(EFI_LOADER_DATA, handles_size,
(void **)&handles);
if (ret != EFI_SUCCESS) {
efi_st_error("AllocatePool failed\n");
- ret = EFI_ST_FAILURE;
goto out;
}
ret = hii_database_protocol->list_package_lists(hii_database_protocol,
@@ -305,13 +296,11 @@
if (ret != EFI_SUCCESS) {
efi_st_error("list_package_lists returned %u\n",
(unsigned int)ret);
- ret = EFI_ST_FAILURE;
goto out;
}
ret = boottime->free_pool(handles);
if (ret != EFI_SUCCESS) {
efi_st_error("FreePool failed\n");
- ret = EFI_ST_FAILURE;
goto out;
}
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index c60972d..7a69167 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1230,12 +1230,12 @@
#ifdef CONFIG_SPL_BUILD
/* FDT is at end of BSS unless it is in a different memory region */
if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
- fdt_blob = (ulong *)&_image_binary_end;
+ fdt_blob = (ulong *)_image_binary_end;
else
- fdt_blob = (ulong *)&__bss_end;
+ fdt_blob = (ulong *)__bss_end;
#else
/* FDT is at end of image */
- fdt_blob = (ulong *)&_end;
+ fdt_blob = (ulong *)_end;
if (_DEBUG && !fdtdec_prepare_fdt(fdt_blob)) {
int stack_ptr;
diff --git a/lib/string.c b/lib/string.c
index ecea755..f2c6147 100644
--- a/lib/string.c
+++ b/lib/string.c
@@ -116,20 +116,18 @@
* of course, the buffer size is zero). It does not pad
* out the result like strncpy() does.
*
- * Return: the number of bytes copied
+ * Return: strlen(src)
*/
size_t strlcpy(char *dest, const char *src, size_t size)
{
- if (size) {
- size_t srclen = strlen(src);
- size_t len = (srclen >= size) ? size - 1 : srclen;
+ size_t ret = strlen(src);
+ if (size) {
+ size_t len = (ret >= size) ? size - 1 : ret;
memcpy(dest, src, len);
dest[len] = '\0';
- return len + 1;
}
-
- return 0;
+ return ret;
}
#endif
@@ -191,6 +189,8 @@
* Compatible with *BSD: the result is always a valid NUL-terminated string that
* fits in the buffer (unless, of course, the buffer size is zero). It does not
* write past @size like strncat() does.
+ *
+ * Return: min(strlen(dest), size) + strlen(src)
*/
size_t strlcat(char *dest, const char *src, size_t size)
{
diff --git a/lib/trace.c b/lib/trace.c
index 1091a57..4874bef 100644
--- a/lib/trace.c
+++ b/lib/trace.c
@@ -51,7 +51,7 @@
uintptr_t offset = (uintptr_t)func_ptr;
#ifdef CONFIG_SANDBOX
- offset -= (uintptr_t)&_init;
+ offset -= (uintptr_t)_init;
#else
if (gd->flags & GD_FLG_RELOC)
offset -= gd->relocaddr;
diff --git a/lib/uuid.c b/lib/uuid.c
index ab30fbf..afb40bf 100644
--- a/lib/uuid.c
+++ b/lib/uuid.c
@@ -1,8 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011 Calxeda, Inc.
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
*/
+#define LOG_CATEGOT LOGC_CORE
+
#include <common.h>
#include <command.h>
#include <efi_api.h>
@@ -19,50 +25,6 @@
#include <dm/uclass.h>
#include <rng.h>
-/*
- * UUID - Universally Unique IDentifier - 128 bits unique number.
- * There are 5 versions and one variant of UUID defined by RFC4122
- * specification. A UUID contains a set of fields. The set varies
- * depending on the version of the UUID, as shown below:
- * - time, MAC address(v1),
- * - user ID(v2),
- * - MD5 of name or URL(v3),
- * - random data(v4),
- * - SHA-1 of name or URL(v5),
- *
- * Layout of UUID:
- * timestamp - 60-bit: time_low, time_mid, time_hi_and_version
- * version - 4 bit (bit 4 through 7 of the time_hi_and_version)
- * clock seq - 14 bit: clock_seq_hi_and_reserved, clock_seq_low
- * variant: - bit 6 and 7 of clock_seq_hi_and_reserved
- * node - 48 bit
- *
- * source: https://www.ietf.org/rfc/rfc4122.txt
- *
- * UUID binary format (16 bytes):
- *
- * 4B-2B-2B-2B-6B (big endian - network byte order)
- *
- * UUID string is 36 length of characters (36 bytes):
- *
- * 0 9 14 19 24
- * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
- * be be be be be
- *
- * where x is a hexadecimal character. Fields are separated by '-'s.
- * When converting to a binary UUID, le means the field should be converted
- * to little endian and be means it should be converted to big endian.
- *
- * UUID is also used as GUID (Globally Unique Identifier) with the same binary
- * format but it differs in string format like below.
- *
- * GUID:
- * 0 9 14 19 24
- * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
- * le le le be be
- *
- * GUID is used e.g. in GPT (GUID Partition Table) as a partiions unique id.
- */
int uuid_str_valid(const char *uuid)
{
int i, valid;
@@ -101,6 +63,10 @@
{"swap", PARTITION_LINUX_SWAP_GUID},
{"lvm", PARTITION_LINUX_LVM_GUID},
{"u-boot-env", PARTITION_U_BOOT_ENVIRONMENT},
+ {"cros-kern", PARTITION_CROS_KERNEL},
+ {"cros-root", PARTITION_CROS_ROOT},
+ {"cros-fw", PARTITION_CROS_FIRMWARE},
+ {"cros-rsrv", PARTITION_CROS_RESERVED},
#endif
#if defined(CONFIG_CMD_EFIDEBUG) || defined(CONFIG_EFI)
{
@@ -265,12 +231,6 @@
#endif
};
-/*
- * uuid_guid_get_bin() - this function get GUID bin for string
- *
- * @param guid_str - pointer to partition type string
- * @param guid_bin - pointer to allocated array for big endian output [16B]
- */
int uuid_guid_get_bin(const char *guid_str, unsigned char *guid_bin)
{
int i;
@@ -284,13 +244,6 @@
return -ENODEV;
}
-/*
- * uuid_guid_get_str() - this function get string for GUID.
- *
- * @param guid_bin - pointer to string with partition type guid [16B]
- *
- * Returns NULL if the type GUID is not known.
- */
const char *uuid_guid_get_str(const unsigned char *guid_bin)
{
int i;
@@ -303,13 +256,6 @@
return NULL;
}
-/*
- * uuid_str_to_bin() - convert string UUID or GUID to big endian binary data.
- *
- * @param uuid_str - pointer to UUID or GUID string [37B] or GUID shorcut
- * @param uuid_bin - pointer to allocated array for big endian output [16B]
- * @str_format - UUID string format: 0 - UUID; 1 - GUID
- */
int uuid_str_to_bin(const char *uuid_str, unsigned char *uuid_bin,
int str_format)
{
@@ -318,6 +264,7 @@
uint64_t tmp64;
if (!uuid_str_valid(uuid_str)) {
+ log_debug("not valid\n");
#ifdef CONFIG_PARTITION_TYPE_GUID
if (!uuid_guid_get_bin(uuid_str, uuid_bin))
return 0;
@@ -354,14 +301,33 @@
return 0;
}
-/*
- * uuid_bin_to_str() - convert big endian binary data to string UUID or GUID.
- *
- * @param uuid_bin: pointer to binary data of UUID (big endian) [16B]
- * @param uuid_str: pointer to allocated array for output string [37B]
- * @str_format: bit 0: 0 - UUID; 1 - GUID
- * bit 1: 0 - lower case; 2 - upper case
- */
+int uuid_str_to_le_bin(const char *uuid_str, unsigned char *uuid_bin)
+{
+ u16 tmp16;
+ u32 tmp32;
+ u64 tmp64;
+
+ if (!uuid_str_valid(uuid_str) || !uuid_bin)
+ return -EINVAL;
+
+ tmp32 = cpu_to_le32(hextoul(uuid_str, NULL));
+ memcpy(uuid_bin, &tmp32, 4);
+
+ tmp16 = cpu_to_le16(hextoul(uuid_str + 9, NULL));
+ memcpy(uuid_bin + 4, &tmp16, 2);
+
+ tmp16 = cpu_to_le16(hextoul(uuid_str + 14, NULL));
+ memcpy(uuid_bin + 6, &tmp16, 2);
+
+ tmp16 = cpu_to_le16(hextoul(uuid_str + 19, NULL));
+ memcpy(uuid_bin + 8, &tmp16, 2);
+
+ tmp64 = cpu_to_le64(simple_strtoull(uuid_str + 24, NULL, 16));
+ memcpy(uuid_bin + 10, &tmp64, 6);
+
+ return 0;
+}
+
void uuid_bin_to_str(const unsigned char *uuid_bin, char *uuid_str,
int str_format)
{
@@ -401,13 +367,6 @@
}
}
-/*
- * gen_rand_uuid() - this function generates a random binary UUID version 4.
- * In this version all fields beside 4 bits of version and
- * 2 bits of variant are randomly generated.
- *
- * @param uuid_bin - pointer to allocated array [16B]. Output is in big endian.
-*/
#if defined(CONFIG_RANDOM_UUID) || defined(CONFIG_CMD_UUID)
void gen_rand_uuid(unsigned char *uuid_bin)
{
@@ -445,13 +404,6 @@
memcpy(uuid_bin, uuid, 16);
}
-/*
- * gen_rand_uuid_str() - this function generates UUID v4 (random) in two string
- * formats UUID or GUID.
- *
- * @param uuid_str - pointer to allocated array [37B].
- * @param - uuid output type: UUID - 0, GUID - 1
- */
void gen_rand_uuid_str(char *uuid_str, int str_format)
{
unsigned char uuid_bin[UUID_BIN_LEN];
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index e87503e..e14c6ca 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -680,8 +680,10 @@
break;
case 'd':
- if (fmt[1] == 'E')
+ if (fmt[1] == 'E') {
flags |= ERRSTR;
+ fmt++;
+ }
/* fallthrough */
case 'i':
flags |= SIGN;
@@ -725,7 +727,6 @@
ADDCH(str, ' ');
for (p = errno_str(num); *p; p++)
ADDCH(str, *p);
- fmt++;
}
}
diff --git a/net/net.c b/net/net.c
index 43abbac..e6f61f0 100644
--- a/net/net.c
+++ b/net/net.c
@@ -716,7 +716,7 @@
case NETLOOP_SUCCESS:
net_cleanup_loop();
if (net_boot_file_size > 0) {
- printf("Bytes transferred = %d (%x hex)\n",
+ printf("Bytes transferred = %u (%x hex)\n",
net_boot_file_size, net_boot_file_size);
env_set_hex("filesize", net_boot_file_size);
env_set_hex("fileaddr", image_load_addr);
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index f5ab7af..8dc6ec8 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -179,10 +179,13 @@
u_boot_dtsi_options_debug = $(warning $(u_boot_dtsi_options_raw))
endif
-# We use the first match
-u_boot_dtsi = $(strip $(u_boot_dtsi_options_debug) \
+# We use the first match to be included
+dtsi_include_list = $(strip $(u_boot_dtsi_options_debug) \
$(notdir $(firstword $(u_boot_dtsi_options))))
+# The CONFIG_DEVICE_TREE_INCLUDES also need to be included
+dtsi_include_list += $(CONFIG_DEVICE_TREE_INCLUDES)
+
# Modified for U-Boot
dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc \
$(UBOOTINCLUDE) \
@@ -320,8 +323,8 @@
# Bring in any U-Boot-specific include at the end of the file
# And finally any custom .dtsi fragments specified with CONFIG_DEVICE_TREE_INCLUDES
cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
- (cat $<; $(if $(u_boot_dtsi),echo '$(pound)include "$(u_boot_dtsi)"')) > $(pre-tmp); \
- $(foreach f,$(subst $(quote),,$(CONFIG_DEVICE_TREE_INCLUDES)), \
+ (cat $< > $(pre-tmp)); \
+ $(foreach f,$(subst $(quote),,$(dtsi_include_list)), \
echo '$(pound)include "$(f)"' >> $(pre-tmp);) \
$(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $(pre-tmp) ; \
$(DTC) -O dtb -o $@ -b 0 \
@@ -331,7 +334,24 @@
; \
sed "s:$(pre-tmp):$(<):" $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
+quiet_cmd_capsule_esl_gen = CAPSULE_ESL_GEN $@
+cmd_capsule_esl_gen = \
+ $(shell sed "s:ESL_BIN_FILE:$(capsule_esl_path):" $(capsule_esl_input_file) > $@)
+
+$(obj)/.capsule_esl.dtsi: FORCE
+ $(call cmd_capsule_esl_gen)
+
+capsule_esl_input_file=$(srctree)/lib/efi_loader/capsule_esl.dtsi.in
+capsule_esl_dtsi = .capsule_esl.dtsi
+capsule_esl_path=$(abspath $(srctree)/$(subst $(quote),,$(CONFIG_EFI_CAPSULE_ESL_FILE)))
+
+ifdef CONFIG_EFI_CAPSULE_AUTHENTICATE
+dtsi_include_list += $(capsule_esl_dtsi)
+endif
+
+dtsi_include_list_deps = $(addprefix $(obj)/,$(subst $(quote),,$(dtsi_include_list)))
+
-$(obj)/%.dtb: $(src)/%.dts $(DTC) FORCE
+$(obj)/%.dtb: $(src)/%.dts $(DTC) $(dtsi_include_list_deps) FORCE
$(call if_changed_dep,dtc)
pre-tmp = $(subst $(comma),_,$(dot-target).pre.tmp)
diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile
index 12e525e..2d97aab 100644
--- a/scripts/kconfig/Makefile
+++ b/scripts/kconfig/Makefile
@@ -99,7 +99,9 @@
%_config: %_defconfig
@:
-configfiles=$(wildcard $(srctree)/kernel/configs/$@ $(srctree)/arch/$(SRCARCH)/configs/$@)
+configfiles=$(wildcard $(srctree)/kernel/configs/$@ \
+ $(srctree)/arch/$(SRCARCH)/configs/$@ \
+ $(shell find $(srctree)/board -name "$@"))
%.config: $(obj)/conf
$(if $(call configfiles),, $(error No configuration exists for this target on this architecture))
diff --git a/test/boot/Makefile b/test/boot/Makefile
index 22ed61c..5294758 100644
--- a/test/boot/Makefile
+++ b/test/boot/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_FIT) += image.o
obj-$(CONFIG_EXPO) += expo.o
+obj-$(CONFIG_CEDIT) += cedit.o
ifdef CONFIG_OF_LIVE
obj-$(CONFIG_BOOTMETH_VBE_SIMPLE) += vbe_simple.o
diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c
index 8a4e090..1ff2320 100644
--- a/test/boot/bootflow.c
+++ b/test/boot/bootflow.c
@@ -27,6 +27,7 @@
DECLARE_GLOBAL_DATA_PTR;
+extern U_BOOT_DRIVER(bootmeth_cros);
extern U_BOOT_DRIVER(bootmeth_script);
static int inject_response(struct unit_test_state *uts)
@@ -167,21 +168,22 @@
ut_assert_nextline("Seq Method State Uclass Part Name Filename");
ut_assert_nextlinen("---");
ut_assert_nextline("Scanning bootdev 'mmc2.bootdev':");
- ut_assert_nextline(" 0 extlinux media mmc 0 mmc2.bootdev.whole <NULL>");
+ ut_assert_nextline(" 0 extlinux media mmc 0 mmc2.bootdev.whole ");
ut_assert_nextline(" ** No partition found, err=-93: Protocol not supported");
- ut_assert_nextline(" 1 efi media mmc 0 mmc2.bootdev.whole <NULL>");
+ ut_assert_nextline(" 1 efi media mmc 0 mmc2.bootdev.whole ");
ut_assert_nextline(" ** No partition found, err=-93: Protocol not supported");
ut_assert_nextline("Scanning bootdev 'mmc1.bootdev':");
- ut_assert_nextline(" 2 extlinux media mmc 0 mmc1.bootdev.whole <NULL>");
+ ut_assert_nextline(" 2 extlinux media mmc 0 mmc1.bootdev.whole ");
ut_assert_nextline(" ** No partition found, err=-2: No such file or directory");
- ut_assert_nextline(" 3 efi media mmc 0 mmc1.bootdev.whole <NULL>");
+ ut_assert_nextline(" 3 efi media mmc 0 mmc1.bootdev.whole ");
ut_assert_nextline(" ** No partition found, err=-2: No such file or directory");
ut_assert_nextline(" 4 extlinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf");
ut_assert_nextline(" 5 efi fs mmc 1 mmc1.bootdev.part_1 efi/boot/bootsbox.efi");
ut_assert_skip_to_line("Scanning bootdev 'mmc0.bootdev':");
- ut_assert_skip_to_line(" 3f efi media mmc 0 mmc0.bootdev.whole <NULL>");
+ ut_assert_skip_to_line(
+ " 3f efi media mmc 0 mmc0.bootdev.whole ");
ut_assert_nextline(" ** No partition found, err=-93: Protocol not supported");
ut_assert_nextline("No more bootdevs");
ut_assert_nextlinen("---");
@@ -192,10 +194,11 @@
ut_assert_nextline("Showing all bootflows");
ut_assert_nextline("Seq Method State Uclass Part Name Filename");
ut_assert_nextlinen("---");
- ut_assert_nextline(" 0 extlinux media mmc 0 mmc2.bootdev.whole <NULL>");
- ut_assert_nextline(" 1 efi media mmc 0 mmc2.bootdev.whole <NULL>");
- ut_assert_skip_to_line(" 4 extlinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf");
- ut_assert_skip_to_line(" 3f efi media mmc 0 mmc0.bootdev.whole <NULL>");
+ ut_assert_nextline(" 0 extlinux media mmc 0 mmc2.bootdev.whole ");
+ ut_assert_nextline(" 1 efi media mmc 0 mmc2.bootdev.whole ");
+ ut_assert_skip_to_line(
+ " 4 extlinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf");
+ ut_assert_skip_to_line(" 3f efi media mmc 0 mmc0.bootdev.whole ");
ut_assert_nextlinen("---");
ut_assert_nextline("(64 bootflows, 1 valid)");
ut_assert_console_end();
@@ -384,7 +387,7 @@
console_record_reset_enable();
ut_assertok(run_command("bootflow scan -lH", 0));
ut_assert_skip_to_line(
- " 0 efi_mgr ready (none) 0 <NULL> <NULL>");
+ " 0 efi_mgr ready (none) 0 <NULL> ");
ut_assert_skip_to_line("No more bootdevs");
ut_assert_skip_to_line("(2 bootflows, 2 valid)");
ut_assert_console_end();
@@ -506,21 +509,25 @@
BOOTSTD_TEST(bootflow_cmd_boot, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
/**
- * prep_mmc4_bootdev() - Set up the mmc4 bootdev so we can access a fake Armbian
+ * prep_mmc_bootdev() - Set up an mmc bootdev so we can access other distros
*
* @uts: Unit test state
+ * @mmc_dev: MMC device to use, e.g. "mmc4"
* Returns 0 on success, -ve on failure
*/
-static int prep_mmc4_bootdev(struct unit_test_state *uts)
+static int prep_mmc_bootdev(struct unit_test_state *uts, const char *mmc_dev,
+ bool bind_cros)
{
- static const char *order[] = {"mmc2", "mmc1", "mmc4", NULL};
+ const char *order[] = {"mmc2", "mmc1", mmc_dev, NULL};
struct udevice *dev, *bootstd;
struct bootstd_priv *std;
const char **old_order;
- ofnode node;
+ ofnode root, node;
/* Enable the mmc4 node since we need a second bootflow */
- node = ofnode_path("/mmc4");
+ root = oftree_root(oftree_default());
+ node = ofnode_find_subnode(root, mmc_dev);
+ ut_assert(ofnode_valid(node));
ut_assertok(lists_bind_fdt(gd->dm_root, node, &dev, NULL, false));
/* Enable the script bootmeth too */
@@ -528,7 +535,14 @@
ut_assertok(device_bind(bootstd, DM_DRIVER_REF(bootmeth_script),
"bootmeth_script", 0, ofnode_null(), &dev));
+ /* Enable the cros bootmeth if needed */
+ if (bind_cros) {
+ ut_assertok(uclass_first_device_err(UCLASS_BOOTSTD, &bootstd));
+ ut_assertok(device_bind(bootstd, DM_DRIVER_REF(bootmeth_cros),
+ "cros", 0, ofnode_null(), &dev));
+ }
+
- /* Change the order to include mmc4 */
+ /* Change the order to include the device */
std = dev_get_priv(bootstd);
old_order = std->bootdev_order;
std->bootdev_order = order;
@@ -543,6 +557,19 @@
return 0;
}
+/**
+ * prep_mmc4_bootdev() - Set up the mmc4 bootdev so we can access a fake Armbian
+ *
+ * @uts: Unit test state
+ * Returns 0 on success, -ve on failure
+ */
+static int prep_mmc4_bootdev(struct unit_test_state *uts)
+{
+ ut_assertok(prep_mmc_bootdev(uts, "mmc4", false));
+
+ return 0;
+}
+
/* Check 'bootflow menu' to select a bootflow */
static int bootflow_cmd_menu(struct unit_test_state *uts)
{
@@ -945,3 +972,24 @@
return 0;
}
BOOTSTD_TEST(bootflow_cmdline, 0);
+
+/* Test ChromiumOS bootmeth */
+static int bootflow_cros(struct unit_test_state *uts)
+{
+ ut_assertok(prep_mmc_bootdev(uts, "mmc5", true));
+ ut_assertok(run_command("bootflow list", 0));
+
+ ut_assert_nextlinen("Showing all");
+ ut_assert_nextlinen("Seq");
+ ut_assert_nextlinen("---");
+ ut_assert_nextlinen(" 0 extlinux");
+ ut_assert_nextlinen(" 1 cros ready mmc 2 mmc5.bootdev.part_2 ");
+ ut_assert_nextlinen(" 2 cros ready mmc 4 mmc5.bootdev.part_4 ");
+ ut_assert_nextlinen("---");
+ ut_assert_skip_to_line("(3 bootflows, 3 valid)");
+
+ ut_assert_console_end();
+
+ return 0;
+}
+BOOTSTD_TEST(bootflow_cros, 0);
diff --git a/test/boot/cedit.c b/test/boot/cedit.c
new file mode 100644
index 0000000..ab2b8a1
--- /dev/null
+++ b/test/boot/cedit.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <cedit.h>
+#include <env.h>
+#include <expo.h>
+#include <mapmem.h>
+#include <dm/ofnode.h>
+#include <test/ut.h>
+#include "bootstd_common.h"
+#include <test/cedit-test.h>
+#include "../../boot/scene_internal.h"
+
+/* Check the cedit command */
+static int cedit_base(struct unit_test_state *uts)
+{
+ extern struct expo *cur_exp;
+ struct scene_obj_menu *menu;
+ struct scene_obj_txt *txt;
+ struct expo *exp;
+ struct scene *scn;
+
+ ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
+
+ console_record_reset_enable();
+
+ /*
+ * ^N Move down to second menu
+ * ^M Open menu
+ * ^N Move down to second item
+ * ^M Select item
+ * \e Quit
+ */
+ console_in_puts("\x0e\x0d\x0e\x0d\e");
+ ut_assertok(run_command("cedit run", 0));
+
+ exp = cur_exp;
+ scn = expo_lookup_scene_id(exp, exp->scene_id);
+ ut_assertnonnull(scn);
+
+ menu = scene_obj_find(scn, scn->highlight_id, SCENEOBJT_NONE);
+ ut_assertnonnull(menu);
+
+ txt = scene_obj_find(scn, menu->title_id, SCENEOBJT_NONE);
+ ut_assertnonnull(txt);
+ ut_asserteq_str("AC Power", expo_get_str(exp, txt->str_id));
+
+ ut_asserteq(ID_AC_ON, menu->cur_item_id);
+
+ return 0;
+}
+BOOTSTD_TEST(cedit_base, 0);
+
+/* Check the cedit write_fdt and read_fdt commands */
+static int cedit_fdt(struct unit_test_state *uts)
+{
+ struct video_priv *vid_priv;
+ extern struct expo *cur_exp;
+ struct scene_obj_menu *menu;
+ ulong addr = 0x1000;
+ struct ofprop prop;
+ struct scene *scn;
+ oftree tree;
+ ofnode node;
+ void *fdt;
+ int i;
+
+ console_record_reset_enable();
+ ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
+
+ ut_asserteq(ID_SCENE1, cedit_prepare(cur_exp, &vid_priv, &scn));
+
+ /* get a menu to fiddle with */
+ menu = scene_obj_find(scn, ID_CPU_SPEED, SCENEOBJT_MENU);
+ ut_assertnonnull(menu);
+ menu->cur_item_id = ID_CPU_SPEED_2;
+
+ ut_assertok(run_command("cedit write_fdt hostfs - settings.dtb", 0));
+ ut_assertok(run_commandf("load hostfs - %lx settings.dtb", addr));
+ ut_assert_nextlinen("1024 bytes read");
+
+ fdt = map_sysmem(addr, 1024);
+ tree = oftree_from_fdt(fdt);
+ node = ofnode_find_subnode(oftree_root(tree), CEDIT_NODE_NAME);
+
+ ut_asserteq(ID_CPU_SPEED_2,
+ ofnode_read_u32_default(node, "cpu-speed", 0));
+ ut_asserteq_str("2.5 GHz", ofnode_read_string(node, "cpu-speed-str"));
+ ut_assert(ofnode_valid(node));
+
+ /* There should only be 4 properties */
+ for (i = 0, ofnode_first_property(node, &prop); ofprop_valid(&prop);
+ i++, ofnode_next_property(&prop))
+ ;
+ ut_asserteq(4, i);
+
+ ut_assert_console_end();
+
+ /* reset the expo */
+ menu->cur_item_id = ID_CPU_SPEED_1;
+
+ /* load in the settings and make sure they update */
+ ut_assertok(run_command("cedit read_fdt hostfs - settings.dtb", 0));
+ ut_asserteq(ID_CPU_SPEED_2, menu->cur_item_id);
+
+ ut_assertnonnull(menu);
+ ut_assert_console_end();
+
+ return 0;
+}
+BOOTSTD_TEST(cedit_fdt, 0);
+
+/* Check the cedit write_env and read_env commands */
+static int cedit_env(struct unit_test_state *uts)
+{
+ struct video_priv *vid_priv;
+ extern struct expo *cur_exp;
+ struct scene_obj_menu *menu;
+ struct scene *scn;
+
+ console_record_reset_enable();
+ ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
+
+ ut_asserteq(ID_SCENE1, cedit_prepare(cur_exp, &vid_priv, &scn));
+
+ /* get a menu to fiddle with */
+ menu = scene_obj_find(scn, ID_CPU_SPEED, SCENEOBJT_MENU);
+ ut_assertnonnull(menu);
+ menu->cur_item_id = ID_CPU_SPEED_2;
+
+ ut_assertok(run_command("cedit write_env -v", 0));
+ ut_assert_nextlinen("c.cpu-speed=7");
+ ut_assert_nextlinen("c.cpu-speed-str=2.5 GHz");
+ ut_assert_nextlinen("c.power-loss=10");
+ ut_assert_nextlinen("c.power-loss-str=Always Off");
+ ut_assert_console_end();
+
+ ut_asserteq(7, env_get_ulong("c.cpu-speed", 10, 0));
+ ut_asserteq_str("2.5 GHz", env_get("c.cpu-speed-str"));
+
+ /* reset the expo */
+ menu->cur_item_id = ID_CPU_SPEED_1;
+
+ ut_assertok(run_command("cedit read_env -v", 0));
+ ut_assert_nextlinen("c.cpu-speed=7");
+ ut_assert_nextlinen("c.power-loss=10");
+ ut_assert_console_end();
+
+ ut_asserteq(ID_CPU_SPEED_2, menu->cur_item_id);
+
+ return 0;
+}
+BOOTSTD_TEST(cedit_env, 0);
+
+/* Check the cedit write_cmos and read_cmos commands */
+static int cedit_cmos(struct unit_test_state *uts)
+{
+ struct scene_obj_menu *menu, *menu2;
+ struct video_priv *vid_priv;
+ extern struct expo *cur_exp;
+ struct scene *scn;
+
+ console_record_reset_enable();
+ ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
+
+ ut_asserteq(ID_SCENE1, cedit_prepare(cur_exp, &vid_priv, &scn));
+
+ /* get the menus to fiddle with */
+ menu = scene_obj_find(scn, ID_CPU_SPEED, SCENEOBJT_MENU);
+ ut_assertnonnull(menu);
+ menu->cur_item_id = ID_CPU_SPEED_2;
+
+ menu2 = scene_obj_find(scn, ID_POWER_LOSS, SCENEOBJT_MENU);
+ ut_assertnonnull(menu2);
+ menu2->cur_item_id = ID_AC_MEMORY;
+
+ ut_assertok(run_command("cedit write_cmos -v", 0));
+ ut_assert_nextlinen("Write 2 bytes from offset 80 to 84");
+ ut_assert_console_end();
+
+ /* reset the expo */
+ menu->cur_item_id = ID_CPU_SPEED_1;
+ menu2->cur_item_id = ID_AC_OFF;
+
+ ut_assertok(run_command("cedit read_cmos -v", 0));
+ ut_assert_nextlinen("Read 2 bytes from offset 80 to 84");
+ ut_assert_console_end();
+
+ ut_asserteq(ID_CPU_SPEED_2, menu->cur_item_id);
+ ut_asserteq(ID_AC_MEMORY, menu2->cur_item_id);
+
+ return 0;
+}
+BOOTSTD_TEST(cedit_cmos, 0);
diff --git a/test/boot/expo.c b/test/boot/expo.c
index 3898f85..9002740 100644
--- a/test/boot/expo.c
+++ b/test/boot/expo.c
@@ -289,6 +289,33 @@
}
BOOTSTD_TEST(expo_object_attr, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+/**
+ * struct test_iter_priv - private data for expo-iterator test
+ *
+ * @count: number of scene objects
+ * @menu_count: number of menus
+ * @fail_at: item ID at which to return an error
+ */
+struct test_iter_priv {
+ int count;
+ int menu_count;
+ int fail_at;
+};
+
+int h_test_iter(struct scene_obj *obj, void *vpriv)
+{
+ struct test_iter_priv *priv = vpriv;
+
+ if (priv->fail_at == obj->id)
+ return -EINVAL;
+
+ priv->count++;
+ if (obj->type == SCENEOBJT_MENU)
+ priv->menu_count++;
+
+ return 0;
+}
+
/* Check creating a scene with a menu */
static int expo_object_menu(struct unit_test_state *uts)
{
@@ -296,6 +323,7 @@
struct scene_menitem *item;
int id, label_id, desc_id, key_id, pointer_id, preview_id;
struct scene_obj_txt *ptr, *name1, *desc1, *key1, *tit, *prev1;
+ struct test_iter_priv priv;
struct scene *scn;
struct expo *exp;
ulong start_mem;
@@ -382,6 +410,23 @@
ut_asserteq(menu->obj.dim.y + 32, prev1->obj.dim.y);
ut_asserteq(true, prev1->obj.flags & SCENEOF_HIDE);
+ /* check iterating through scene items */
+ memset(&priv, '\0', sizeof(priv));
+ ut_assertok(expo_iter_scene_objs(exp, h_test_iter, &priv));
+ ut_asserteq(7, priv.count);
+ ut_asserteq(1, priv.menu_count);
+
+ /* check the iterator failing part way through iteration */
+ memset(&priv, '\0', sizeof(priv));
+ priv.fail_at = key_id;
+ ut_asserteq(-EINVAL, expo_iter_scene_objs(exp, h_test_iter, &priv));
+
+ /* 2 items (preview_id and the menuitem) are after key_id, 7 - 2 = 5 */
+ ut_asserteq(5, priv.count);
+
+ /* menu is first, so is still processed */
+ ut_asserteq(1, priv.menu_count);
+
expo_destroy(exp);
ut_assertok(ut_check_delta(start_mem));
@@ -669,46 +714,3 @@
return 0;
}
BOOTSTD_TEST(expo_test_build, UT_TESTF_DM);
-
-/* Check the cedit command */
-static int expo_cedit(struct unit_test_state *uts)
-{
- extern struct expo *cur_exp;
- struct scene_obj_menu *menu;
- struct scene_obj_txt *txt;
- struct expo *exp;
- struct scene *scn;
-
- if (!IS_ENABLED(CONFIG_CMD_CEDIT))
- return -EAGAIN;
-
- ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
-
- console_record_reset_enable();
-
- /*
- * ^N Move down to second menu
- * ^M Open menu
- * ^N Move down to second item
- * ^M Select item
- * \e Quit
- */
- console_in_puts("\x0e\x0d\x0e\x0d\e");
- ut_assertok(run_command("cedit run", 0));
-
- exp = cur_exp;
- scn = expo_lookup_scene_id(exp, exp->scene_id);
- ut_assertnonnull(scn);
-
- menu = scene_obj_find(scn, scn->highlight_id, SCENEOBJT_NONE);
- ut_assertnonnull(menu);
-
- txt = scene_obj_find(scn, menu->title_id, SCENEOBJT_NONE);
- ut_assertnonnull(txt);
- ut_asserteq_str("AC Power", expo_get_str(exp, txt->str_id));
-
- ut_asserteq(ID_AC_ON, menu->cur_item_id);
-
- return 0;
-}
-BOOTSTD_TEST(expo_cedit, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
diff --git a/test/boot/files/expo_ids.h b/test/boot/files/expo_ids.h
new file mode 100644
index 0000000..027d44b
--- /dev/null
+++ b/test/boot/files/expo_ids.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Sample expo screen layout (ID numbers)
+ */
+
+enum {
+ ZERO,
+ ID_PROMPT,
+
+ ID_SCENE1,
+ ID_SCENE1_TITLE,
+
+ ID_CPU_SPEED,
+ ID_CPU_SPEED_TITLE,
+ ID_CPU_SPEED_1,
+ ID_CPU_SPEED_2,
+ ID_CPU_SPEED_3,
+
+ ID_POWER_LOSS,
+ ID_AC_OFF,
+ ID_AC_ON,
+ ID_AC_MEMORY,
+
+ ID_DYNAMIC_START,
+};
diff --git a/test/boot/files/expo_layout.dts b/test/boot/files/expo_layout.dts
index 55d5c91..cb2a674 100644
--- a/test/boot/files/expo_layout.dts
+++ b/test/boot/files/expo_layout.dts
@@ -5,28 +5,7 @@
/dts-v1/;
-/*
-enum {
- ZERO,
- ID_PROMPT,
-
- ID_SCENE1,
- ID_SCENE1_TITLE,
-
- ID_CPU_SPEED,
- ID_CPU_SPEED_TITLE,
- ID_CPU_SPEED_1,
- ID_CPU_SPEED_2,
- ID_CPU_SPEED_3,
-
- ID_POWER_LOSS,
- ID_AC_OFF,
- ID_AC_ON,
- ID_AC_MEMORY,
-
- ID_DYNAMIC_START,
-};
-*/
+/* see expo_ids.h for the IDs */
/ {
dynamic-start = <ID_DYNAMIC_START>;
@@ -59,6 +38,9 @@
/* IDs for the menu items */
item-id = <ID_CPU_SPEED_1 ID_CPU_SPEED_2
ID_CPU_SPEED_3>;
+
+ start-bit = <0x400>;
+ bit-length = <2>;
};
power-loss {
@@ -70,6 +52,8 @@
"Memory";
item-id = <ID_AC_OFF ID_AC_ON ID_AC_MEMORY>;
+ start-bit = <0x422>;
+ bit-length = <2>;
};
};
};
diff --git a/test/cmd/Makefile b/test/cmd/Makefile
index a3cf983..6e3d7e9 100644
--- a/test/cmd/Makefile
+++ b/test/cmd/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (c) 2013 Google, Inc
+# Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
ifdef CONFIG_HUSH_PARSER
obj-$(CONFIG_CONSOLE_RECORD) += test_echo.o
@@ -24,6 +25,7 @@
ifdef CONFIG_SANDBOX
obj-$(CONFIG_CMD_READ) += rw.o
obj-$(CONFIG_CMD_SETEXPR) += setexpr.o
+obj-$(CONFIG_ARM_FFA_TRANSPORT) += armffa.o
endif
obj-$(CONFIG_CMD_TEMPERATURE) += temperature.o
obj-$(CONFIG_CMD_WGET) += wget.o
diff --git a/test/cmd/armffa.c b/test/cmd/armffa.c
new file mode 100644
index 0000000..9a44a39
--- /dev/null
+++ b/test/cmd/armffa.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test for armffa command
+ *
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#include <common.h>
+#include <string.h>
+#include <asm/sandbox_arm_ffa.h>
+#include <dm/test.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+/* Basic test of 'armffa' command */
+static int dm_test_armffa_cmd(struct unit_test_state *uts)
+{
+ /* armffa getpart <UUID> */
+ ut_assertok(run_command("armffa getpart " SANDBOX_SERVICE1_UUID, 0));
+
+ /* armffa ping <ID> */
+ ut_assertok(run_commandf("armffa ping 0x%x", SANDBOX_SP1_ID));
+
+ /* armffa devlist */
+ ut_assertok(run_command("armffa devlist", 0));
+
+ return 0;
+}
+
+DM_TEST(dm_test_armffa_cmd, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
diff --git a/test/cmd_ut.c b/test/cmd_ut.c
index 0cb5144..0f56409 100644
--- a/test/cmd_ut.c
+++ b/test/cmd_ut.c
@@ -201,7 +201,7 @@
"\nfdt - fdt command"
#endif
#ifdef CONFIG_CONSOLE_TRUETYPE
- "\nut font - font command"
+ "\nfont - font command"
#endif
#ifdef CONFIG_CMD_LOADM
"\nloadm - loadm command parameters and loading memory blob"
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 3799b1a..7ed0073 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (c) 2013 Google, Inc
-# Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
obj-$(CONFIG_UT_DM) += test-dm.o
@@ -92,6 +92,7 @@
obj-$(CONFIG_ACPI_PMC) += pmc.o
obj-$(CONFIG_DM_PMIC) += pmic.o
obj-$(CONFIG_DM_PWM) += pwm.o
+obj-$(CONFIG_ARM_FFA_TRANSPORT) += ffa.o
obj-$(CONFIG_QFW) += qfw.o
obj-$(CONFIG_RAM) += ram.o
obj-y += regmap.o
diff --git a/test/dm/acpi.c b/test/dm/acpi.c
index 77eb524..5997bda 100644
--- a/test/dm/acpi.c
+++ b/test/dm/acpi.c
@@ -221,7 +221,8 @@
ut_assertnonnull(cpu);
ut_assertok(acpi_create_dmar(&dmar, DMAR_INTR_REMAP));
ut_asserteq(DMAR_INTR_REMAP, dmar.flags);
- ut_asserteq(32 - 1, dmar.host_address_width);
+ ut_asserteq((IS_ENABLED(CONFIG_PHYS_64BIT) ? 64 : 32) - 1,
+ dmar.host_address_width);
return 0;
}
@@ -277,13 +278,16 @@
*/
ut_asserteq_ptr(dmar + 3, ctx.current);
ut_asserteq(DMAR_INTR_REMAP, dmar->flags);
- ut_asserteq(32 - 1, dmar->host_address_width);
+ ut_asserteq((IS_ENABLED(CONFIG_PHYS_64BIT) ? 64 : 32) - 1,
+ dmar->host_address_width);
ut_asserteq(DMAR_INTR_REMAP, dmar[1].flags);
- ut_asserteq(32 - 1, dmar[1].host_address_width);
+ ut_asserteq((IS_ENABLED(CONFIG_PHYS_64BIT) ? 64 : 32) - 1,
+ dmar[1].host_address_width);
ut_asserteq(DMAR_INTR_REMAP, dmar[2].flags);
- ut_asserteq(32 - 1, dmar[2].host_address_width);
+ ut_asserteq((IS_ENABLED(CONFIG_PHYS_64BIT) ? 64 : 32) - 1,
+ dmar[2].host_address_width);
/* Check that the pointers were added correctly */
for (i = 0; i < 3; i++) {
diff --git a/test/dm/cpu.c b/test/dm/cpu.c
index d7e596ee..5734cd0 100644
--- a/test/dm/cpu.c
+++ b/test/dm/cpu.c
@@ -37,7 +37,7 @@
ut_assertok(cpu_get_info(dev, &info));
ut_asserteq(info.cpu_freq, 42 * 42 * 42 * 42 * 42);
ut_asserteq(info.features, 0x42424242);
- ut_asserteq(info.address_width, 32);
+ ut_asserteq(info.address_width, IS_ENABLED(CONFIG_PHYS_64BIT) ? 64 : 32);
ut_asserteq(cpu_get_count(dev), 42);
diff --git a/test/dm/ffa.c b/test/dm/ffa.c
new file mode 100644
index 0000000..6912666
--- /dev/null
+++ b/test/dm/ffa.c
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Functional tests for UCLASS_FFA class
+ *
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#include <common.h>
+#include <console.h>
+#include <dm.h>
+#include <asm/sandbox_arm_ffa.h>
+#include <asm/sandbox_arm_ffa_priv.h>
+#include <dm/test.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+/* Functional tests for the UCLASS_FFA */
+
+static int check_fwk_version(struct ffa_priv *uc_priv, struct unit_test_state *uts)
+{
+ struct ffa_sandbox_data func_data;
+ u32 fwk_version = 0;
+
+ func_data.data0 = &fwk_version;
+ func_data.data0_size = sizeof(fwk_version);
+ ut_assertok(sandbox_query_ffa_emul_state(FFA_VERSION, &func_data));
+ ut_asserteq(uc_priv->fwk_version, fwk_version);
+
+ return 0;
+}
+
+static int check_endpoint_id(struct ffa_priv *uc_priv, struct unit_test_state *uts)
+{
+ ut_asserteq(0, uc_priv->id);
+
+ return 0;
+}
+
+static int check_rxtxbuf(struct ffa_priv *uc_priv, struct unit_test_state *uts)
+{
+ ut_assertnonnull(uc_priv->pair.rxbuf);
+ ut_assertnonnull(uc_priv->pair.txbuf);
+
+ return 0;
+}
+
+static int check_features(struct ffa_priv *uc_priv, struct unit_test_state *uts)
+{
+ ut_assert(uc_priv->pair.rxtx_min_pages == RXTX_4K ||
+ uc_priv->pair.rxtx_min_pages == RXTX_16K ||
+ uc_priv->pair.rxtx_min_pages == RXTX_64K);
+
+ return 0;
+}
+
+static int check_rxbuf_mapped_flag(u32 queried_func_id,
+ u8 rxbuf_mapped,
+ struct unit_test_state *uts)
+{
+ switch (queried_func_id) {
+ case FFA_RXTX_MAP:
+ ut_asserteq(1, rxbuf_mapped);
+ break;
+ case FFA_RXTX_UNMAP:
+ ut_asserteq(0, rxbuf_mapped);
+ break;
+ default:
+ ut_assert(false);
+ }
+
+ return 0;
+}
+
+static int check_rxbuf_release_flag(u8 rxbuf_owned, struct unit_test_state *uts)
+{
+ ut_asserteq(0, rxbuf_owned);
+
+ return 0;
+}
+
+static int test_ffa_msg_send_direct_req(u16 part_id, struct unit_test_state *uts)
+{
+ struct ffa_send_direct_data msg;
+ u8 cnt;
+ struct udevice *dev;
+
+ ut_assertok(uclass_first_device_err(UCLASS_FFA, &dev));
+
+ ut_assertok(ffa_sync_send_receive(dev, part_id, &msg, 1));
+
+ for (cnt = 0; cnt < sizeof(struct ffa_send_direct_data) / sizeof(u64); cnt++)
+ ut_asserteq_64(-1UL, ((u64 *)&msg)[cnt]);
+
+ return 0;
+}
+
+static int test_partitions_and_comms(const char *service_uuid,
+ struct unit_test_state *uts)
+{
+ struct ffa_partition_desc *descs;
+ u32 count, i, j, valid_sps = 0;
+ struct udevice *dev;
+ struct ffa_sandbox_data func_data;
+ struct ffa_partitions *partitions;
+
+ ut_assertok(uclass_first_device_err(UCLASS_FFA, &dev));
+
+ /* Get from the driver the count and information of the SPs matching the UUID */
+ ut_assertok(ffa_partition_info_get(dev, service_uuid, &count, &descs));
+
+ /* Make sure the count is correct */
+ ut_asserteq(SANDBOX_SP_COUNT_PER_VALID_SERVICE, count);
+
+ /* SPs found , verify the partitions information */
+
+ func_data.data0 = &partitions;
+ func_data.data0_size = sizeof(struct ffa_partitions *);
+ ut_assertok(sandbox_query_ffa_emul_state(FFA_PARTITION_INFO_GET, &func_data));
+
+ for (i = 0; i < count ; i++) {
+ for (j = 0;
+ j < partitions->count;
+ j++) {
+ if (descs[i].info.id ==
+ partitions->descs[j].info.id) {
+ valid_sps++;
+ ut_asserteq_mem(&descs[i],
+ &partitions->descs[j],
+ sizeof(struct ffa_partition_desc));
+ /* Send and receive data from the current partition */
+ test_ffa_msg_send_direct_req(descs[i].info.id, uts);
+ }
+ }
+ }
+
+ /* Verify expected partitions found in the emulated secure world */
+ ut_asserteq(SANDBOX_SP_COUNT_PER_VALID_SERVICE, valid_sps);
+
+ return 0;
+}
+
+static int dm_test_ffa_ack(struct unit_test_state *uts)
+{
+ struct ffa_priv *uc_priv;
+ struct ffa_sandbox_data func_data;
+ u8 rxbuf_flag = 0;
+ const char *svc1_uuid = SANDBOX_SERVICE1_UUID;
+ const char *svc2_uuid = SANDBOX_SERVICE2_UUID;
+ struct udevice *dev;
+
+ /* Test probing the sandbox FF-A bus */
+ ut_assertok(uclass_first_device_err(UCLASS_FFA, &dev));
+
+ /* Get a pointer to the sandbox FF-A bus private data */
+ uc_priv = dev_get_uclass_priv(dev);
+
+ /* Make sure the private data pointer is retrieved */
+ ut_assertnonnull(uc_priv);
+
+ /* Test FFA_VERSION */
+ check_fwk_version(uc_priv, uts);
+
+ /* Test FFA_ID_GET */
+ check_endpoint_id(uc_priv, uts);
+
+ /* Test FFA_FEATURES */
+ check_features(uc_priv, uts);
+
+ /* Test RX/TX buffers */
+ check_rxtxbuf(uc_priv, uts);
+
+ /* Test FFA_RXTX_MAP */
+ func_data.data0 = &rxbuf_flag;
+ func_data.data0_size = sizeof(rxbuf_flag);
+
+ rxbuf_flag = 0;
+ sandbox_query_ffa_emul_state(FFA_RXTX_MAP, &func_data);
+ check_rxbuf_mapped_flag(FFA_RXTX_MAP, rxbuf_flag, uts);
+
+ /* FFA_PARTITION_INFO_GET / FFA_MSG_SEND_DIRECT_REQ */
+ test_partitions_and_comms(svc1_uuid, uts);
+
+ /* Test FFA_RX_RELEASE */
+ rxbuf_flag = 1;
+ sandbox_query_ffa_emul_state(FFA_RX_RELEASE, &func_data);
+ check_rxbuf_release_flag(rxbuf_flag, uts);
+
+ /* FFA_PARTITION_INFO_GET / FFA_MSG_SEND_DIRECT_REQ */
+ test_partitions_and_comms(svc2_uuid, uts);
+
+ /* Test FFA_RX_RELEASE */
+ rxbuf_flag = 1;
+ ut_assertok(sandbox_query_ffa_emul_state(FFA_RX_RELEASE, &func_data));
+ check_rxbuf_release_flag(rxbuf_flag, uts);
+
+ return 0;
+}
+
+DM_TEST(dm_test_ffa_ack, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+
+static int dm_test_ffa_nack(struct unit_test_state *uts)
+{
+ struct ffa_priv *uc_priv;
+ const char *valid_svc_uuid = SANDBOX_SERVICE1_UUID;
+ const char *unvalid_svc_uuid = SANDBOX_SERVICE3_UUID;
+ const char *unvalid_svc_uuid_str = SANDBOX_SERVICE4_UUID;
+ struct ffa_send_direct_data msg;
+ int ret;
+ u32 count;
+ u16 part_id = 0;
+ struct udevice *dev;
+ struct ffa_partition_desc *descs = NULL;
+
+ /* Test probing the sandbox FF-A bus */
+ ut_assertok(uclass_first_device_err(UCLASS_FFA, &dev));
+
+ /* Get a pointer to the sandbox FF-A bus private data */
+ uc_priv = dev_get_uclass_priv(dev);
+
+ /* Make sure the private data pointer is retrieved */
+ ut_assertnonnull(uc_priv);
+
+ /* Query partitions count using invalid arguments */
+ ret = ffa_partition_info_get(dev, NULL, NULL, NULL);
+ ut_asserteq(-EINVAL, ret);
+ ret = ffa_partition_info_get(dev, unvalid_svc_uuid, NULL, NULL);
+ ut_asserteq(-EINVAL, ret);
+ ret = ffa_partition_info_get(dev, unvalid_svc_uuid, &count, NULL);
+ ut_asserteq(-EINVAL, ret);
+
+ /* Query partitions count using an invalid UUID string */
+ ret = ffa_partition_info_get(dev, unvalid_svc_uuid_str, &count, &descs);
+ ut_asserteq(-EINVAL, ret);
+
+ /* Query partitions count using an invalid UUID (no matching SP) */
+ count = 0;
+ ret = ffa_partition_info_get(dev, unvalid_svc_uuid, &count, &descs);
+ ut_asserteq(0, count);
+
+ /* Query partitions data using a valid UUID */
+ count = 0;
+ ut_assertok(ffa_partition_info_get(dev, valid_svc_uuid, &count, &descs));
+ /* Make sure partitions are detected */
+ ut_asserteq(SANDBOX_SP_COUNT_PER_VALID_SERVICE, count);
+ ut_assertnonnull(descs);
+
+ /* Send data to an invalid partition */
+ ret = ffa_sync_send_receive(dev, part_id, &msg, 1);
+ ut_asserteq(-EINVAL, ret);
+
+ /* Send data to a valid partition */
+ part_id = uc_priv->partitions.descs[0].info.id;
+ ut_assertok(ffa_sync_send_receive(dev, part_id, &msg, 1));
+
+ return 0;
+}
+
+DM_TEST(dm_test_ffa_nack, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
diff --git a/test/dm/host.c b/test/dm/host.c
index 355ba77..85f21f9 100644
--- a/test/dm/host.c
+++ b/test/dm/host.c
@@ -8,6 +8,7 @@
#include <blk.h>
#include <dm.h>
#include <fs.h>
+#include <os.h>
#include <sandbox_host.h>
#include <asm/test.h>
#include <dm/device-internal.h>
@@ -15,9 +16,6 @@
#include <test/test.h>
#include <test/ut.h>
-static const char filename[] = "2MB.ext2.img";
-static const char filename2[] = "1MB.fat32.img";
-
/* Basic test of host interface */
static int dm_test_host(struct unit_test_state *uts)
{
@@ -25,6 +23,7 @@
struct udevice *dev, *part, *chk, *blk;
struct host_sb_plat *plat;
struct blk_desc *desc;
+ char fname[256];
ulong mem_start;
loff_t actwrite;
@@ -40,13 +39,15 @@
ut_assert(label != plat->label);
ut_asserteq(0, plat->fd);
- /* Attach a file created in test_host.py */
- ut_assertok(host_attach_file(dev, filename));
+ /* Attach a file created in test_ut_dm_init */
+ ut_assertok(os_persistent_file(fname, sizeof(fname), "2MB.ext2.img"));
+
+ ut_assertok(host_attach_file(dev, fname));
ut_assertok(uclass_first_device_err(UCLASS_HOST, &chk));
ut_asserteq_ptr(chk, dev);
- ut_asserteq_str(filename, plat->filename);
- ut_assert(filename != plat->filename);
+ ut_asserteq_str(fname, plat->filename);
+ ut_assert(fname != plat->filename);
ut_assert(plat->fd != 0);
/* Get the block device */
@@ -79,12 +80,14 @@
{
static char label[] = "test";
struct udevice *dev, *chk;
+ char fname[256];
ut_asserteq(0, uclass_id_count(UCLASS_HOST));
ut_assertok(host_create_device(label, true, &dev));
- /* Attach a file created in test_host.py */
- ut_assertok(host_attach_file(dev, filename));
+ /* Attach a file created in test_ut_dm_init */
+ ut_assertok(os_persistent_file(fname, sizeof(fname), "2MB.ext2.img"));
+ ut_assertok(host_attach_file(dev, fname));
ut_assertok(uclass_first_device_err(UCLASS_HOST, &chk));
ut_asserteq_ptr(chk, dev);
ut_asserteq(1, uclass_id_count(UCLASS_HOST));
@@ -92,8 +95,10 @@
/* Create another device with the same label (should remove old one) */
ut_assertok(host_create_device(label, true, &dev));
- /* Attach a different file created in test_host.py */
- ut_assertok(host_attach_file(dev, filename2));
+ /* Attach a different file created in test_ut_dm_init */
+ ut_assertok(os_persistent_file(fname, sizeof(fname), "1MB.fat32.img"));
+ ut_assertok(host_attach_file(dev, fname));
+
ut_assertok(uclass_first_device_err(UCLASS_HOST, &chk));
ut_asserteq_ptr(chk, dev);
@@ -109,6 +114,7 @@
{
struct udevice *dev, *blk;
struct blk_desc *desc;
+ char fname[256];
console_record_reset();
@@ -117,7 +123,8 @@
ut_assert_nextline("dev blocks label path");
ut_assert_console_end();
- ut_assertok(run_commandf("host bind -r test2 %s", filename));
+ ut_assertok(os_persistent_file(fname, sizeof(fname), "2MB.ext2.img"));
+ ut_assertok(run_commandf("host bind -r test2 %s", fname));
/* Check the -r flag worked */
ut_assertok(uclass_first_device_err(UCLASS_HOST, &dev));
@@ -127,10 +134,11 @@
ut_assertok(run_command("host info", 0));
ut_assert_nextline("dev blocks label path");
- ut_assert_nextline(" 0 4096 test2 2MB.ext2.img");
+ ut_assert_nextlinen(" 0 4096 test2");
ut_assert_console_end();
- ut_assertok(run_commandf("host bind fat %s", filename2));
+ ut_assertok(os_persistent_file(fname, sizeof(fname), "1MB.fat32.img"));
+ ut_assertok(run_commandf("host bind fat %s", fname));
/* Check it is not removable (no '-r') */
ut_assertok(uclass_next_device_err(&dev));
@@ -140,8 +148,8 @@
ut_assertok(run_command("host info", 0));
ut_assert_nextline("dev blocks label path");
- ut_assert_nextline(" 0 4096 test2 2MB.ext2.img");
- ut_assert_nextline(" 1 2048 fat 1MB.fat32.img");
+ ut_assert_nextlinen(" 0 4096 test2");
+ ut_assert_nextlinen(" 1 2048 fat");
ut_assert_console_end();
ut_asserteq(1, run_command("host info test", 0));
@@ -150,7 +158,7 @@
ut_assertok(run_command("host info fat", 0));
ut_assert_nextline("dev blocks label path");
- ut_assert_nextline(" 1 2048 fat 1MB.fat32.img");
+ ut_assert_nextlinen(" 1 2048 fat");
ut_assert_console_end();
/* check 'host dev' */
@@ -187,7 +195,7 @@
ut_assertok(run_command("host info", 0));
ut_assert_nextline("dev blocks label path");
- ut_assert_nextline(" 1 2048 fat 1MB.fat32.img");
+ ut_assert_nextlinen(" 1 2048 fat");
ut_assert_console_end();
return 0;
diff --git a/test/dm/pinmux.c b/test/dm/pinmux.c
index 265df4c..6880b2d 100644
--- a/test/dm/pinmux.c
+++ b/test/dm/pinmux.c
@@ -15,6 +15,16 @@
ut_asserteq_str(expected, (char *)&buf); \
} while (0)
+#define test_muxing_regaddr(selector, regaddr, expected) do { \
+ char estr[64] = { 0 }; \
+ if (IS_ENABLED(CONFIG_PHYS_64BIT)) \
+ snprintf(estr, sizeof(estr), "0x%016llx %s", (u64)regaddr, expected); \
+ else \
+ snprintf(estr, sizeof(estr), "0x%08x %s", (u32)regaddr, expected); \
+ ut_assertok(pinctrl_get_pin_muxing(dev, selector, buf, sizeof(buf))); \
+ ut_asserteq_str(estr, (char *)&buf); \
+} while (0)
+
#define test_name(selector, expected) do { \
ut_assertok(pinctrl_get_pin_name(dev, selector, buf, sizeof(buf))); \
ut_asserteq_str(expected, (char *)&buf); \
@@ -79,14 +89,14 @@
test_name(0, "PIN0");
test_name(141, "PIN141");
test_name(142, "Error");
- test_muxing(0, "0x00000000 0x00000000 UNCLAIMED");
- test_muxing(18, "0x00000048 0x00000006 pinmux_pwm_pins");
- test_muxing(28, "0x00000070 0x00000030 pinmux_uart0_pins");
- test_muxing(29, "0x00000074 0x00000000 pinmux_uart0_pins");
- test_muxing(100, "0x00000190 0x0000000c pinmux_spi0_pins");
- test_muxing(101, "0x00000194 0x0000000c pinmux_spi0_pins");
- test_muxing(102, "0x00000198 0x00000023 pinmux_spi0_pins");
- test_muxing(103, "0x0000019c 0x0000000c pinmux_spi0_pins");
+ test_muxing_regaddr(0, 0x0, "0x00000000 UNCLAIMED");
+ test_muxing_regaddr(18, 0x48, "0x00000006 pinmux_pwm_pins");
+ test_muxing_regaddr(28, 0x70, "0x00000030 pinmux_uart0_pins");
+ test_muxing_regaddr(29, 0x74, "0x00000000 pinmux_uart0_pins");
+ test_muxing_regaddr(100, 0x190, "0x0000000c pinmux_spi0_pins");
+ test_muxing_regaddr(101, 0x194, "0x0000000c pinmux_spi0_pins");
+ test_muxing_regaddr(102, 0x198, "0x00000023 pinmux_spi0_pins");
+ test_muxing_regaddr(103, 0x19c, "0x0000000c pinmux_spi0_pins");
ret = pinctrl_get_pin_muxing(dev, 142, buf, sizeof(buf));
ut_asserteq(-EINVAL, ret);
ut_assertok(uclass_get_device_by_name(UCLASS_I2C, "i2c@0", &dev));
@@ -97,39 +107,39 @@
test_name(0, "PIN0");
test_name(159, "PIN159");
test_name(160, "Error");
- test_muxing(0, "0x00000000 0x00000000 UNCLAIMED");
- test_muxing(34, "0x00000010 0x00000200 pinmux_i2c0_pins");
- test_muxing(35, "0x00000010 0x00002000 pinmux_i2c0_pins");
- test_muxing(130, "0x00000040 0x00000200 pinmux_lcd_pins");
- test_muxing(131, "0x00000040 0x00002000 pinmux_lcd_pins");
- test_muxing(132, "0x00000040 0x00020000 pinmux_lcd_pins");
- test_muxing(133, "0x00000040 0x00200000 pinmux_lcd_pins");
- test_muxing(134, "0x00000040 0x02000000 pinmux_lcd_pins");
- test_muxing(135, "0x00000040 0x20000000 pinmux_lcd_pins");
- test_muxing(136, "0x00000044 0x00000002 pinmux_lcd_pins");
- test_muxing(137, "0x00000044 0x00000020 pinmux_lcd_pins");
- test_muxing(138, "0x00000044 0x00000200 pinmux_lcd_pins");
- test_muxing(139, "0x00000044 0x00002000 pinmux_lcd_pins");
- test_muxing(140, "0x00000044 0x00020000 pinmux_lcd_pins");
- test_muxing(141, "0x00000044 0x00200000 pinmux_lcd_pins");
- test_muxing(142, "0x00000044 0x02000000 pinmux_lcd_pins");
- test_muxing(143, "0x00000044 0x20000000 pinmux_lcd_pins");
- test_muxing(144, "0x00000048 0x00000002 pinmux_lcd_pins");
- test_muxing(145, "0x00000048 0x00000020 pinmux_lcd_pins");
- test_muxing(146, "0x00000048 0x00000000 UNCLAIMED");
- test_muxing(147, "0x00000048 0x00000000 UNCLAIMED");
- test_muxing(148, "0x00000048 0x00000000 UNCLAIMED");
- test_muxing(149, "0x00000048 0x00000000 UNCLAIMED");
- test_muxing(150, "0x00000048 0x02000000 pinmux_lcd_pins");
- test_muxing(151, "0x00000048 0x00000000 UNCLAIMED");
- test_muxing(152, "0x0000004c 0x00000002 pinmux_lcd_pins");
- test_muxing(153, "0x0000004c 0x00000020 pinmux_lcd_pins");
- test_muxing(154, "0x0000004c 0x00000000 UNCLAIMED");
- test_muxing(155, "0x0000004c 0x00000000 UNCLAIMED");
- test_muxing(156, "0x0000004c 0x00000000 UNCLAIMED");
- test_muxing(157, "0x0000004c 0x00000000 UNCLAIMED");
- test_muxing(158, "0x0000004c 0x02000000 pinmux_lcd_pins");
- test_muxing(159, "0x0000004c 0x00000000 UNCLAIMED");
+ test_muxing_regaddr(0, 0x0, "0x00000000 UNCLAIMED");
+ test_muxing_regaddr(34, 0x10, "0x00000200 pinmux_i2c0_pins");
+ test_muxing_regaddr(35, 0x10, "0x00002000 pinmux_i2c0_pins");
+ test_muxing_regaddr(130, 0x40, "0x00000200 pinmux_lcd_pins");
+ test_muxing_regaddr(131, 0x40, "0x00002000 pinmux_lcd_pins");
+ test_muxing_regaddr(132, 0x40, "0x00020000 pinmux_lcd_pins");
+ test_muxing_regaddr(133, 0x40, "0x00200000 pinmux_lcd_pins");
+ test_muxing_regaddr(134, 0x40, "0x02000000 pinmux_lcd_pins");
+ test_muxing_regaddr(135, 0x40, "0x20000000 pinmux_lcd_pins");
+ test_muxing_regaddr(136, 0x44, "0x00000002 pinmux_lcd_pins");
+ test_muxing_regaddr(137, 0x44, "0x00000020 pinmux_lcd_pins");
+ test_muxing_regaddr(138, 0x44, "0x00000200 pinmux_lcd_pins");
+ test_muxing_regaddr(139, 0x44, "0x00002000 pinmux_lcd_pins");
+ test_muxing_regaddr(140, 0x44, "0x00020000 pinmux_lcd_pins");
+ test_muxing_regaddr(141, 0x44, "0x00200000 pinmux_lcd_pins");
+ test_muxing_regaddr(142, 0x44, "0x02000000 pinmux_lcd_pins");
+ test_muxing_regaddr(143, 0x44, "0x20000000 pinmux_lcd_pins");
+ test_muxing_regaddr(144, 0x48, "0x00000002 pinmux_lcd_pins");
+ test_muxing_regaddr(145, 0x48, "0x00000020 pinmux_lcd_pins");
+ test_muxing_regaddr(146, 0x48, "0x00000000 UNCLAIMED");
+ test_muxing_regaddr(147, 0x48, "0x00000000 UNCLAIMED");
+ test_muxing_regaddr(148, 0x48, "0x00000000 UNCLAIMED");
+ test_muxing_regaddr(149, 0x48, "0x00000000 UNCLAIMED");
+ test_muxing_regaddr(150, 0x48, "0x02000000 pinmux_lcd_pins");
+ test_muxing_regaddr(151, 0x48, "0x00000000 UNCLAIMED");
+ test_muxing_regaddr(152, 0x4c, "0x00000002 pinmux_lcd_pins");
+ test_muxing_regaddr(153, 0x4c, "0x00000020 pinmux_lcd_pins");
+ test_muxing_regaddr(154, 0x4c, "0x00000000 UNCLAIMED");
+ test_muxing_regaddr(155, 0x4c, "0x00000000 UNCLAIMED");
+ test_muxing_regaddr(156, 0x4c, "0x00000000 UNCLAIMED");
+ test_muxing_regaddr(157, 0x4c, "0x00000000 UNCLAIMED");
+ test_muxing_regaddr(158, 0x4c, "0x02000000 pinmux_lcd_pins");
+ test_muxing_regaddr(159, 0x4c, "0x00000000 UNCLAIMED");
ret = pinctrl_get_pin_muxing(dev, 160, buf, sizeof(buf));
ut_asserteq(-EINVAL, ret);
return 0;
diff --git a/test/lib/Makefile b/test/lib/Makefile
index e0bd9e0..e75a263 100644
--- a/test/lib/Makefile
+++ b/test/lib/Makefile
@@ -22,6 +22,7 @@
obj-$(CONFIG_GETOPT) += getopt.o
obj-$(CONFIG_CRC8) += test_crc8.o
obj-$(CONFIG_UT_LIB_CRYPT) += test_crypt.o
+obj-$(CONFIG_LIB_UUID) += uuid.o
else
obj-$(CONFIG_SANDBOX) += kconfig_spl.o
endif
diff --git a/test/lib/abuf.c b/test/lib/abuf.c
index 42ee4c1..42803b2 100644
--- a/test/lib/abuf.c
+++ b/test/lib/abuf.c
@@ -155,6 +155,31 @@
}
LIB_TEST(lib_test_abuf_realloc_size, 0);
+/* Test abuf_realloc_inc() */
+static int lib_test_abuf_realloc_inc(struct unit_test_state *uts)
+{
+ struct abuf buf;
+ ulong start;
+
+ start = ut_check_free();
+
+ abuf_init(&buf);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ abuf_realloc_inc(&buf, 20);
+ ut_asserteq(20, buf.size);
+ ut_asserteq(true, buf.alloced);
+
+ abuf_uninit(&buf);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_realloc_inc, 0);
+
/* Test handling of buffers that are too large */
static int lib_test_abuf_large(struct unit_test_state *uts)
{
diff --git a/test/lib/asn1.c b/test/lib/asn1.c
index 8661fdd..a66cdd7 100644
--- a/test/lib/asn1.c
+++ b/test/lib/asn1.c
@@ -120,7 +120,7 @@
cert = x509_cert_parse(cert_data, cert_data_len);
- ut_assertf(cert != NULL, "decoding failed\n");
+ ut_assertf(!IS_ERR(cert), "decoding failed\n");
ut_assertf(!strcmp(cert->subject, "Linaro: Tester"),
"subject doesn't match\n");
ut_assertf(!strcmp(cert->issuer, "Linaro: Tester"),
@@ -313,7 +313,7 @@
pkcs7 = pkcs7_parse_message(image_pk7, image_pk7_len);
- ut_assertf(pkcs7 != NULL, "decoding failed\n");
+ ut_assertf(!IS_ERR(pkcs7), "decoding failed\n");
ut_assertf(pkcs7->data_len == 104, "signature size doesn't match\n");
ut_assertf(pkcs7->signed_infos != NULL, "sign-info doesn't exist\n");
ut_assertf(pkcs7->signed_infos->msgdigest_len == 32,
diff --git a/test/lib/strlcat.c b/test/lib/strlcat.c
index a0ec037..d8453fe 100644
--- a/test/lib/strlcat.c
+++ b/test/lib/strlcat.c
@@ -43,11 +43,11 @@
s2[i] = 32 + 23 * i % (127 - 32);
s2[len2 - 1] = '\0';
- expected = len2 < n ? min(len1 + len2 - 1, n) : n;
+ expected = min(strlen(s2), n) + strlen(s1);
actual = strlcat(s2, s1, n);
if (expected != actual) {
ut_failf(uts, __FILE__, line, __func__,
- "strlcat(s2, s1, 2) == len2 < n ? min(len1 + len2, n) : n",
+ "strlcat(s2, s1, n) == min(len2, n) + len1",
"Expected %#zx (%zd), got %#zx (%zd)",
expected, expected, actual, actual);
return CMD_RET_FAILURE;
diff --git a/test/lib/uuid.c b/test/lib/uuid.c
new file mode 100644
index 0000000..e24331a
--- /dev/null
+++ b/test/lib/uuid.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Functional tests for UCLASS_FFA class
+ *
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#include <common.h>
+#include <uuid.h>
+#include <test/lib.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+/* test UUID */
+#define TEST_SVC_UUID "ed32d533-4209-99e6-2d72-cdd998a79cc0"
+
+#define UUID_SIZE 16
+
+/* The UUID binary data (little-endian format) */
+static const u8 ref_uuid_bin[UUID_SIZE] = {
+ 0x33, 0xd5, 0x32, 0xed,
+ 0x09, 0x42, 0xe6, 0x99,
+ 0x72, 0x2d, 0xc0, 0x9c,
+ 0xa7, 0x98, 0xd9, 0xcd
+};
+
+static int lib_test_uuid_to_le(struct unit_test_state *uts)
+{
+ const char *uuid_str = TEST_SVC_UUID;
+ u8 ret_uuid_bin[UUID_SIZE] = {0};
+
+ ut_assertok(uuid_str_to_le_bin(uuid_str, ret_uuid_bin));
+ ut_asserteq_mem(ref_uuid_bin, ret_uuid_bin, UUID_SIZE);
+
+ return 0;
+}
+
+LIB_TEST(lib_test_uuid_to_le, 0);
diff --git a/test/py/tests/fs_helper.py b/test/py/tests/fs_helper.py
index 17151bc..9882ddb 100644
--- a/test/py/tests/fs_helper.py
+++ b/test/py/tests/fs_helper.py
@@ -9,7 +9,7 @@
import os
from subprocess import call, check_call, check_output, CalledProcessError
-def mk_fs(config, fs_type, size, prefix, use_src_dir=False):
+def mk_fs(config, fs_type, size, prefix):
"""Create a file system volume
Args:
@@ -17,14 +17,12 @@
fs_type (str): File system type, e.g. 'ext4'
size (int): Size of file system in bytes
prefix (str): Prefix string of volume's file name
- use_src_dir (bool): true to put the file in the source directory
Raises:
CalledProcessError: if any error occurs when creating the filesystem
"""
fs_img = f'{prefix}.{fs_type}.img'
- fs_img = os.path.join(config.source_dir if use_src_dir
- else config.persistent_data_dir, fs_img)
+ fs_img = os.path.join(config.persistent_data_dir, fs_img)
if fs_type == 'fat16':
mkfs_opt = '-F 16'
diff --git a/test/py/tests/test_efi_capsule/capsule_gen_binman.dts b/test/py/tests/test_efi_capsule/capsule_gen_binman.dts
new file mode 100644
index 0000000..e8a1858
--- /dev/null
+++ b/test/py/tests/test_efi_capsule/capsule_gen_binman.dts
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Devicetree for capsule generation through binman
+ */
+
+/dts-v1/;
+
+#include <sandbox_efi_capsule.h>
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+&binman {
+ itb {
+ filename = UBOOT_FIT_IMAGE;
+
+ fit {
+ description = "Automatic U-Boot environment update";
+ #address-cells = <2>;
+
+ images {
+ u-boot-bin {
+ description = "U-Boot binary on SPI Flash";
+ compression = "none";
+ type = "firmware";
+ arch = "sandbox";
+ load = <0>;
+ text {
+ text = "u-boot:New";
+ };
+
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+ u-boot-env {
+ description = "U-Boot environment on SPI Flash";
+ compression = "none";
+ type = "firmware";
+ arch = "sandbox";
+ load = <0>;
+ text {
+ text = "u-boot-env:New";
+ };
+
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+ };
+ };
+ };
+
+ capsule1 {
+ filename = "Test01";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule2 {
+ filename = "Test02";
+ efi-capsule {
+ image-index = <0x2>;
+ image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID;
+
+ text {
+ text = "u-boot-env:New";
+ };
+ };
+ };
+
+ capsule3 {
+ filename = "Test03";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_INCORRECT_GUID;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule4 {
+ filename = "Test04";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_FIT_IMAGE_GUID;
+
+ blob {
+ filename = UBOOT_FIT_IMAGE;
+ };
+ };
+ };
+
+ capsule5 {
+ filename = "Test05";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_INCORRECT_GUID;
+
+ blob {
+ filename = UBOOT_FIT_IMAGE;
+ };
+ };
+ };
+
+ capsule6 {
+ filename = "Test101";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x5>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule7 {
+ filename = "Test102";
+ efi-capsule {
+ image-index = <0x2>;
+ fw-version = <0xa>;
+ image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID;
+
+ text {
+ text = "u-boot-env:New";
+ };
+ };
+ };
+
+ capsule8 {
+ filename = "Test103";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x2>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule9 {
+ filename = "Test104";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x5>;
+ image-guid = SANDBOX_FIT_IMAGE_GUID;
+
+ blob {
+ filename = UBOOT_FIT_IMAGE;
+ };
+ };
+ };
+
+ capsule10 {
+ filename = "Test105";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x2>;
+ image-guid = SANDBOX_FIT_IMAGE_GUID;
+
+ blob {
+ filename = UBOOT_FIT_IMAGE;
+ };
+ };
+ };
+
+ capsule11 {
+ filename = "Test11";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+ private-key = CAPSULE_PRIV_KEY;
+ public-key-cert = CAPSULE_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule12 {
+ filename = "Test12";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+ private-key = CAPSULE_INVAL_KEY;
+ public-key-cert = CAPSULE_INVAL_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule13 {
+ filename = "Test13";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_FIT_IMAGE_GUID;
+ private-key = CAPSULE_PRIV_KEY;
+ public-key-cert = CAPSULE_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = UBOOT_FIT_IMAGE;
+ };
+ };
+ };
+
+ capsule14 {
+ filename = "Test14";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_FIT_IMAGE_GUID;
+ private-key = CAPSULE_INVAL_KEY;
+ public-key-cert = CAPSULE_INVAL_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = UBOOT_FIT_IMAGE;
+ };
+ };
+ };
+
+ capsule15 {
+ filename = "Test111";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x5>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+ private-key = CAPSULE_PRIV_KEY;
+ public-key-cert = CAPSULE_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule16 {
+ filename = "Test112";
+ efi-capsule {
+ image-index = <0x2>;
+ fw-version = <0xa>;
+ image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID;
+ private-key = CAPSULE_PRIV_KEY;
+ public-key-cert = CAPSULE_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ text {
+ text = "u-boot-env:New";
+ };
+ };
+ };
+
+ capsule17 {
+ filename = "Test113";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x2>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+ private-key = CAPSULE_PRIV_KEY;
+ public-key-cert = CAPSULE_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule18 {
+ filename = "Test114";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x5>;
+ image-guid = SANDBOX_FIT_IMAGE_GUID;
+ private-key = CAPSULE_PRIV_KEY;
+ public-key-cert = CAPSULE_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = UBOOT_FIT_IMAGE;
+ };
+ };
+ };
+
+ capsule19 {
+ filename = "Test115";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x2>;
+ image-guid = SANDBOX_FIT_IMAGE_GUID;
+ private-key = CAPSULE_PRIV_KEY;
+ public-key-cert = CAPSULE_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = UBOOT_FIT_IMAGE;
+ };
+ };
+ };
+};
diff --git a/test/py/tests/test_efi_capsule/conftest.py b/test/py/tests/test_efi_capsule/conftest.py
index 054be1e..dd41da9 100644
--- a/test/py/tests/test_efi_capsule/conftest.py
+++ b/test/py/tests/test_efi_capsule/conftest.py
@@ -4,6 +4,8 @@
"""Fixture for UEFI capsule test."""
+import os
+
from subprocess import call, check_call, CalledProcessError
import pytest
from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR, EFITOOLS_PATH
@@ -34,40 +36,31 @@
capsule_auth_enabled = u_boot_config.buildconfig.get(
'config_efi_capsule_authenticate')
+ key_dir = u_boot_config.source_dir + '/board/sandbox'
if capsule_auth_enabled:
- # Create private key (SIGNER.key) and certificate (SIGNER.crt)
- check_call('cd %s; '
- 'openssl req -x509 -sha256 -newkey rsa:2048 '
- '-subj /CN=TEST_SIGNER/ -keyout SIGNER.key '
- '-out SIGNER.crt -nodes -days 365'
- % data_dir, shell=True)
- check_call('cd %s; %scert-to-efi-sig-list SIGNER.crt SIGNER.esl'
- % (data_dir, EFITOOLS_PATH), shell=True)
+ # Get the keys from the board directory
+ check_call('cp %s/capsule_priv_key_good.key %s/SIGNER.key'
+ % (key_dir, data_dir), shell=True)
+ check_call('cp %s/capsule_pub_key_good.crt %s/SIGNER.crt'
+ % (key_dir, data_dir), shell=True)
+ check_call('cp %s/capsule_pub_esl_good.esl %s/SIGNER.esl'
+ % (key_dir, data_dir), shell=True)
- # Update dtb adding capsule certificate
- check_call('cd %s; '
- 'cp %s/test/py/tests/test_efi_capsule/signature.dts .'
- % (data_dir, u_boot_config.source_dir), shell=True)
- check_call('cd %s; '
- 'dtc -@ -I dts -O dtb -o signature.dtbo signature.dts; '
- 'fdtoverlay -i %s/arch/sandbox/dts/test.dtb '
- '-o test_sig.dtb signature.dtbo'
- % (data_dir, u_boot_config.build_dir), shell=True)
-
- # Create *malicious* private key (SIGNER2.key) and certificate
- # (SIGNER2.crt)
- check_call('cd %s; '
- 'openssl req -x509 -sha256 -newkey rsa:2048 '
- '-subj /CN=TEST_SIGNER/ -keyout SIGNER2.key '
- '-out SIGNER2.crt -nodes -days 365'
- % data_dir, shell=True)
+ check_call('cp %s/capsule_priv_key_bad.key %s/SIGNER2.key'
+ % (key_dir, data_dir), shell=True)
+ check_call('cp %s/capsule_pub_key_bad.crt %s/SIGNER2.crt'
+ % (key_dir, data_dir), shell=True)
# Update dtb to add the version information
check_call('cd %s; '
'cp %s/test/py/tests/test_efi_capsule/version.dts .'
% (data_dir, u_boot_config.source_dir), shell=True)
+
if capsule_auth_enabled:
check_call('cd %s; '
+ 'cp %s/arch/sandbox/dts/test.dtb test_sig.dtb'
+ % (data_dir, u_boot_config.build_dir), shell=True)
+ check_call('cd %s; '
'dtc -@ -I dts -O dtb -o version.dtbo version.dts; '
'fdtoverlay -i test_sig.dtb '
'-o test_ver.dtb version.dtbo'
@@ -79,132 +72,20 @@
'-o test_ver.dtb version.dtbo'
% (data_dir, u_boot_config.build_dir), shell=True)
- # Create capsule files
# two regions: one for u-boot.bin and the other for u-boot.env
check_call('cd %s; echo -n u-boot:Old > u-boot.bin.old; echo -n u-boot:New > u-boot.bin.new; echo -n u-boot-env:Old > u-boot.env.old; echo -n u-boot-env:New > u-boot.env.new' % data_dir,
shell=True)
- check_call('sed -e \"s?BINFILE1?u-boot.bin.new?\" -e \"s?BINFILE2?u-boot.env.new?\" %s/test/py/tests/test_efi_capsule/uboot_bin_env.its > %s/uboot_bin_env.its' %
- (u_boot_config.source_dir, data_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkimage -f uboot_bin_env.its uboot_bin_env.itb' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 u-boot.bin.new Test01' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 2 --guid 5A7021F5-FEF2-48B4-AABA-832E777418C0 u-boot.env.new Test02' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid 058B7D83-50D5-4C47-A195-60D86AD341C4 u-boot.bin.new Test03' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 uboot_bin_env.itb Test04' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid 058B7D83-50D5-4C47-A195-60D86AD341C4 uboot_bin_env.itb Test05' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 5 '
- '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 u-boot.bin.new Test101' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 2 --fw-version 10 '
- '--guid 5A7021F5-FEF2-48B4-AABA-832E777418C0 u-boot.env.new Test102' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 2 '
- '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 u-boot.bin.new Test103' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 5 '
- '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 uboot_bin_env.itb Test104' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 2 '
- '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 uboot_bin_env.itb Test105' %
- (data_dir, u_boot_config.build_dir),
- shell=True)
- if capsule_auth_enabled:
- # raw firmware signed with proper key
- check_call('cd %s; '
- '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
- '--private-key SIGNER.key --certificate SIGNER.crt '
- '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 '
- 'u-boot.bin.new Test11'
- % (data_dir, u_boot_config.build_dir),
- shell=True)
- # raw firmware signed with *mal* key
- check_call('cd %s; '
- '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
- '--private-key SIGNER2.key '
- '--certificate SIGNER2.crt '
- '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 '
- 'u-boot.bin.new Test12'
- % (data_dir, u_boot_config.build_dir),
- shell=True)
- # FIT firmware signed with proper key
- check_call('cd %s; '
- '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
- '--private-key SIGNER.key --certificate SIGNER.crt '
- '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 '
- 'uboot_bin_env.itb Test13'
- % (data_dir, u_boot_config.build_dir),
- shell=True)
- # FIT firmware signed with *mal* key
- check_call('cd %s; '
- '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
- '--private-key SIGNER2.key '
- '--certificate SIGNER2.crt '
- '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 '
- 'uboot_bin_env.itb Test14'
- % (data_dir, u_boot_config.build_dir),
- shell=True)
- # raw firmware signed with proper key with version information
- check_call('cd %s; '
- '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
- '--fw-version 5 '
- '--private-key SIGNER.key --certificate SIGNER.crt '
- '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 '
- 'u-boot.bin.new Test111'
- % (data_dir, u_boot_config.build_dir),
- shell=True)
- # raw firmware signed with proper key with version information
- check_call('cd %s; '
- '%s/tools/mkeficapsule --index 2 --monotonic-count 1 '
- '--fw-version 10 '
- '--private-key SIGNER.key --certificate SIGNER.crt '
- '--guid 5A7021F5-FEF2-48B4-AABA-832E777418C0 '
- 'u-boot.env.new Test112'
- % (data_dir, u_boot_config.build_dir),
- shell=True)
- # raw firmware signed with proper key with lower version information
- check_call('cd %s; '
- '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
- '--fw-version 2 '
- '--private-key SIGNER.key --certificate SIGNER.crt '
- '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 '
- 'u-boot.bin.new Test113'
- % (data_dir, u_boot_config.build_dir),
- shell=True)
- # FIT firmware signed with proper key with version information
- check_call('cd %s; '
- '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
- '--fw-version 5 '
- '--private-key SIGNER.key --certificate SIGNER.crt '
- '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 '
- 'uboot_bin_env.itb Test114'
- % (data_dir, u_boot_config.build_dir),
- shell=True)
- # FIT firmware signed with proper key with lower version information
- check_call('cd %s; '
- '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
- '--fw-version 2 '
- '--private-key SIGNER.key --certificate SIGNER.crt '
- '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 '
- 'uboot_bin_env.itb Test115'
- % (data_dir, u_boot_config.build_dir),
- shell=True)
+ pythonpath = os.environ.get('PYTHONPATH', '')
+ os.environ['PYTHONPATH'] = pythonpath + ':' + '%s/scripts/dtc/pylibfdt' % u_boot_config.build_dir
+ check_call('cd %s; '
+ 'cc -E -I %s/include -x assembler-with-cpp -o capsule_gen_tmp.dts %s/test/py/tests/test_efi_capsule/capsule_gen_binman.dts; '
+ 'dtc -I dts -O dtb capsule_gen_tmp.dts -o capsule_binman.dtb;'
+ % (data_dir, u_boot_config.source_dir, u_boot_config.source_dir), shell=True)
+ check_call('cd %s; '
+ './tools/binman/binman --toolpath %s/tools build -u -d %s/capsule_binman.dtb -O %s -m --allow-missing -I %s -I ./board/sandbox -I ./arch/sandbox/dts'
+ % (u_boot_config.source_dir, u_boot_config.build_dir, data_dir, data_dir, data_dir), shell=True)
+ os.environ['PYTHONPATH'] = pythonpath
# Create a disk image with EFI system partition
check_call('virt-make-fs --partition=gpt --size=+1M --type=vfat %s %s' %
diff --git a/test/py/tests/test_efi_capsule/signature.dts b/test/py/tests/test_efi_capsule/signature.dts
deleted file mode 100644
index 078cfc7..0000000
--- a/test/py/tests/test_efi_capsule/signature.dts
+++ /dev/null
@@ -1,10 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-/dts-v1/;
-/plugin/;
-
-&{/} {
- signature {
- capsule-key = /incbin/("SIGNER.esl");
- };
-};
diff --git a/test/py/tests/test_efi_capsule/uboot_bin_env.its b/test/py/tests/test_efi_capsule/uboot_bin_env.its
deleted file mode 100644
index fc65907..0000000
--- a/test/py/tests/test_efi_capsule/uboot_bin_env.its
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Automatic software update for U-Boot
- * Make sure the flashing addresses ('load' prop) is correct for your board!
- */
-
-/dts-v1/;
-
-/ {
- description = "Automatic U-Boot environment update";
- #address-cells = <2>;
-
- images {
- u-boot-bin {
- description = "U-Boot binary on SPI Flash";
- data = /incbin/("BINFILE1");
- compression = "none";
- type = "firmware";
- arch = "sandbox";
- load = <0>;
- hash-1 {
- algo = "sha1";
- };
- };
- u-boot-env {
- description = "U-Boot environment on SPI Flash";
- data = /incbin/("BINFILE2");
- compression = "none";
- type = "firmware";
- arch = "sandbox";
- load = <0>;
- hash-1 {
- algo = "sha1";
- };
- };
- };
-};
diff --git a/test/py/tests/test_semihosting/conftest.py b/test/py/tests/test_semihosting/conftest.py
new file mode 100644
index 0000000..b00d8f4
--- /dev/null
+++ b/test/py/tests/test_semihosting/conftest.py
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+"""Fixture for semihosting command test
+"""
+
+import os
+import pytest
+
+@pytest.fixture(scope='session')
+def semihosting_data(u_boot_config):
+ """Set up a file system to be used in semihosting tests
+
+ Args:
+ u_boot_config -- U-Boot configuration.
+ """
+ image_path = u_boot_config.persistent_data_dir + '/semihosting.txt'
+
+ with open(image_path, 'w', encoding = 'utf-8') as file:
+ file.write('Das U-Boot\n')
+
+ yield image_path
+
+ os.remove(image_path)
diff --git a/test/py/tests/test_semihosting/test_hostfs.py b/test/py/tests/test_semihosting/test_hostfs.py
new file mode 100644
index 0000000..51f6fa7
--- /dev/null
+++ b/test/py/tests/test_semihosting/test_hostfs.py
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+""" Unit test for semihosting
+"""
+
+import pytest
+
+@pytest.mark.buildconfigspec('semihosting')
+def test_semihosting_hostfs(u_boot_console, semihosting_data):
+ """ Unit test for semihosting
+
+ Args:
+ u_boot_console -- U-Boot console
+ semihosting_data -- Path to the disk image used for testing.
+ """
+ response = u_boot_console.run_command(
+ f'load hostfs - $loadaddr {semihosting_data}')
+ assert '11 bytes read' in response
+
+ response = u_boot_console.run_command(
+ 'crc32 $loadaddr $filesize')
+ assert '==> 60cfccfc' in response
+
+ u_boot_console.run_command(
+ f'save hostfs - $loadaddr {semihosting_data} 11 11')
+
+ response = u_boot_console.run_command(
+ f'load hostfs - $loadaddr {semihosting_data} 4 13')
+ assert '4 bytes read' in response
+
+ response = u_boot_console.run_command(
+ 'crc32 $loadaddr $filesize')
+ assert '==> e29063ea' in response
diff --git a/test/py/tests/test_trace.py b/test/py/tests/test_trace.py
index ac3e959..ad22509 100644
--- a/test/py/tests/test_trace.py
+++ b/test/py/tests/test_trace.py
@@ -61,7 +61,7 @@
# Read out the trace data
addr = 0x02000000
- size = 0x01000000
+ size = 0x02000000
out = cons.run_command(f'trace calls {addr:x} {size:x}')
print(out)
fname = os.path.join(TMPDIR, 'trace')
diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
index aa1d477..82932a6 100644
--- a/test/py/tests/test_ut.py
+++ b/test/py/tests/test_ut.py
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
# Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+import collections
import getpass
import gzip
import os
@@ -282,13 +283,155 @@
copy_prepared_image(cons, mmc_dev, fname)
+def setup_cros_image(cons):
+ """Create a 20MB disk image with ChromiumOS partitions"""
+ Partition = collections.namedtuple('part', 'start,size,name')
+ parts = {}
+ disk_data = None
+
+ def pack_kernel(cons, arch, kern, dummy):
+ """Pack a kernel containing some fake data
+
+ Args:
+ cons (ConsoleBase): Console to use
+ arch (str): Architecture to use ('x86' or 'arm')
+ kern (str): Filename containing kernel
+ dummy (str): Dummy filename to use for config and bootloader
+
+ Return:
+ bytes: Packed-kernel data
+ """
+ kern_part = os.path.join(cons.config.result_dir, 'kern-part-{arch}.bin')
+ u_boot_utils.run_and_log(
+ cons,
+ f'futility vbutil_kernel --pack {kern_part} '
+ '--keyblock doc/chromium/files/devkeys/kernel.keyblock '
+ '--signprivate doc/chromium/files/devkeys/kernel_data_key.vbprivk '
+ f'--version 1 --config {dummy} --bootloader {dummy} '
+ f'--vmlinuz {kern}')
+
+ with open(kern_part, 'rb') as inf:
+ kern_part_data = inf.read()
+ return kern_part_data
+
+ def set_part_data(partnum, data):
+ """Set the contents of a disk partition
+
+ This updates disk_data by putting data in the right place
+
+ Args:
+ partnum (int): Partition number to set
+ data (bytes): Data for that partition
+ """
+ nonlocal disk_data
+
+ start = parts[partnum].start * sect_size
+ disk_data = disk_data[:start] + data + disk_data[start + len(data):]
+
+ mmc_dev = 5
+ fname = os.path.join(cons.config.source_dir, f'mmc{mmc_dev}.img')
+ u_boot_utils.run_and_log(cons, 'qemu-img create %s 20M' % fname)
+ #mnt = os.path.join(cons.config.persistent_data_dir, 'mnt')
+ #mkdir_cond(mnt)
+ u_boot_utils.run_and_log(cons, f'cgpt create {fname}')
+
+ uuid_state = 'ebd0a0a2-b9e5-4433-87c0-68b6b72699c7'
+ uuid_kern = 'fe3a2a5d-4f32-41a7-b725-accc3285a309'
+ uuid_root = '3cb8e202-3b7e-47dd-8a3c-7ff2a13cfcec'
+ uuid_rwfw = 'cab6e88e-abf3-4102-a07a-d4bb9be3c1d3'
+ uuid_reserved = '2e0a753d-9e48-43b0-8337-b15192cb1b5e'
+ uuid_efi = 'c12a7328-f81f-11d2-ba4b-00a0c93ec93b'
+
+ ptr = 40
+
+ # Number of sectors in 1MB
+ sect_size = 512
+ sect_1mb = (1 << 20) // sect_size
+
+ required_parts = [
+ {'num': 0xb, 'label':'RWFW', 'type': uuid_rwfw, 'size': '1'},
+ {'num': 6, 'label':'KERN_C', 'type': uuid_kern, 'size': '1'},
+ {'num': 7, 'label':'ROOT_C', 'type': uuid_root, 'size': '1'},
+ {'num': 9, 'label':'reserved', 'type': uuid_reserved, 'size': '1'},
+ {'num': 0xa, 'label':'reserved', 'type': uuid_reserved, 'size': '1'},
+
+ {'num': 2, 'label':'KERN_A', 'type': uuid_kern, 'size': '1M'},
+ {'num': 4, 'label':'KERN_B', 'type': uuid_kern, 'size': '1M'},
+
+ {'num': 8, 'label':'OEM', 'type': uuid_state, 'size': '1M'},
+ {'num': 0xc, 'label':'EFI-SYSTEM', 'type': uuid_efi, 'size': '1M'},
+
+ {'num': 5, 'label':'ROOT_B', 'type': uuid_root, 'size': '1'},
+ {'num': 3, 'label':'ROOT_A', 'type': uuid_root, 'size': '1'},
+ {'num': 1, 'label':'STATE', 'type': uuid_state, 'size': '1M'},
+ ]
+
+ for part in required_parts:
+ size_str = part['size']
+ if 'M' in size_str:
+ size = int(size_str[:-1]) * sect_1mb
+ else:
+ size = int(size_str)
+ u_boot_utils.run_and_log(
+ cons,
+ f"cgpt add -i {part['num']} -b {ptr} -s {size} -t {part['type']} {fname}")
+ ptr += size
+
+ u_boot_utils.run_and_log(cons, f'cgpt boot -p {fname}')
+ out = u_boot_utils.run_and_log(cons, f'cgpt show -q {fname}')
+ '''We expect something like this:
+ 8239 2048 1 Basic data
+ 45 2048 2 ChromeOS kernel
+ 8238 1 3 ChromeOS rootfs
+ 2093 2048 4 ChromeOS kernel
+ 8237 1 5 ChromeOS rootfs
+ 41 1 6 ChromeOS kernel
+ 42 1 7 ChromeOS rootfs
+ 4141 2048 8 Basic data
+ 43 1 9 ChromeOS reserved
+ 44 1 10 ChromeOS reserved
+ 40 1 11 ChromeOS firmware
+ 6189 2048 12 EFI System Partition
+ '''
+
+ # Create a dict (indexed by partition number) containing the above info
+ for line in out.splitlines():
+ start, size, num, name = line.split(maxsplit=3)
+ parts[int(num)] = Partition(int(start), int(size), name)
+
+ dummy = os.path.join(cons.config.result_dir, 'dummy.txt')
+ with open(dummy, 'wb') as outf:
+ outf.write(b'dummy\n')
+
+ # For now we just use dummy kernels. This limits testing to just detecting
+ # a signed kernel. We could add support for the x86 data structures so that
+ # testing could cover getting the cmdline, setup.bin and other pieces.
+ kern = os.path.join(cons.config.result_dir, 'kern.bin')
+ with open(kern, 'wb') as outf:
+ outf.write(b'kernel\n')
+
+ with open(fname, 'rb') as inf:
+ disk_data = inf.read()
+
+ # put x86 kernel in partition 2 and arm one in partition 4
+ set_part_data(2, pack_kernel(cons, 'x86', kern, dummy))
+ set_part_data(4, pack_kernel(cons, 'arm', kern, dummy))
+
+ with open(fname, 'wb') as outf:
+ outf.write(disk_data)
+
+ return fname
+
+
def setup_cedit_file(cons):
infname = os.path.join(cons.config.source_dir,
'test/boot/files/expo_layout.dts')
+ inhname = os.path.join(cons.config.source_dir,
+ 'test/boot/files/expo_ids.h')
expo_tool = os.path.join(cons.config.source_dir, 'tools/expo.py')
outfname = 'cedit.dtb'
u_boot_utils.run_and_log(
- cons, f'{expo_tool} -e {infname} -l {infname} -o {outfname}')
+ cons, f'{expo_tool} -e {inhname} -l {infname} -o {outfname}')
@pytest.mark.buildconfigspec('ut_dm')
@@ -317,10 +460,8 @@
u_boot_utils.run_and_log(
u_boot_console, f'sfdisk {fn}', stdin=b'type=83')
- fs_helper.mk_fs(u_boot_console.config, 'ext2', 0x200000, '2MB',
- use_src_dir=True)
- fs_helper.mk_fs(u_boot_console.config, 'fat32', 0x100000, '1MB',
- use_src_dir=True)
+ fs_helper.mk_fs(u_boot_console.config, 'ext2', 0x200000, '2MB')
+ fs_helper.mk_fs(u_boot_console.config, 'fat32', 0x100000, '1MB')
@pytest.mark.buildconfigspec('cmd_bootflow')
def test_ut_dm_init_bootstd(u_boot_console):
@@ -329,6 +470,7 @@
setup_bootflow_image(u_boot_console)
setup_bootmenu_image(u_boot_console)
setup_cedit_file(u_boot_console)
+ setup_cros_image(u_boot_console)
# Restart so that the new mmc1.img is picked up
u_boot_console.restart_uboot()
diff --git a/test/unicode_ut.c b/test/unicode_ut.c
index b27d711..1d0d90c 100644
--- a/test/unicode_ut.c
+++ b/test/unicode_ut.c
@@ -807,28 +807,28 @@
/* dest and src are empty string */
memset(buf, 0, sizeof(buf));
- ret = u16_strlcat(buf, &null_src, sizeof(buf));
- ut_asserteq(1, ret);
+ ret = u16_strlcat(buf, &null_src, ARRAY_SIZE(buf));
+ ut_asserteq(0, ret);
/* dest is empty string */
memset(buf, 0, sizeof(buf));
- ret = u16_strlcat(buf, src, sizeof(buf));
- ut_asserteq(5, ret);
+ ret = u16_strlcat(buf, src, ARRAY_SIZE(buf));
+ ut_asserteq(4, ret);
ut_assert(!unicode_test_u16_strcmp(buf, src, 40));
/* src is empty string */
memset(buf, 0xCD, (sizeof(buf) - sizeof(u16)));
buf[39] = 0;
memcpy(buf, dest, sizeof(dest));
- ret = u16_strlcat(buf, &null_src, sizeof(buf));
- ut_asserteq(6, ret);
+ ret = u16_strlcat(buf, &null_src, ARRAY_SIZE(buf));
+ ut_asserteq(5, ret);
ut_assert(!unicode_test_u16_strcmp(buf, dest, 40));
for (i = 0; i <= 40; i++) {
memset(buf, 0xCD, (sizeof(buf) - sizeof(u16)));
buf[39] = 0;
memcpy(buf, dest, sizeof(dest));
- expected = 10;
+ expected = min(5, i) + 4;
ret = u16_strlcat(buf, src, i);
ut_asserteq(expected, ret);
if (i <= 6) {
diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst
index 8f57b6c..aeea33f 100644
--- a/tools/binman/binman.rst
+++ b/tools/binman/binman.rst
@@ -1256,8 +1256,32 @@
do not exist there. In the example above, `some-property` is added to each of
`spi-image` and `mmc-image`.
-Note that template nodes are not removed from the binman description at present.
+Note that template nodes are removed from the binman description after
+processing and before binman builds the image descriptions.
+
+The initial devicetree produced by the templating process is written to the
+`u-boot.dtb.tmpl1` file. This can be useful to see what is going on if there is
+a failure before the final `u-boot.dtb.out` file is written. A second
+`u-boot.dtb.tmpl2` file is written when the templates themselves are removed.
+
+Dealing with phandles
+---------------------
+
+Templates can contain phandles and these are copied to the destination node.
+However this should be used with care, since if a template is instantiated twice
+then the phandle will be copied twice, resulting in a devicetree with duplicate
+phandles, i.e. the same phandle used by two different nodes. Binman detects this
+situation and produces an error, for example::
+
+ Duplicate phandle 1 in nodes /binman/image/fit/images/atf/atf-bl31 and
+ /binman/image-2/fit/images/atf/atf-bl31
+
+In this case an atf-bl31 node containing a phandle has been copied into two
+different target nodes, resulting in the same phandle for each. See
+testTemplatePhandleDup() for the test case.
+The solution is typically to put the phandles in the corresponding target nodes
+(one for each) and remove the phandle from the template.
Updating an ELF file
====================
diff --git a/tools/binman/bintool.py b/tools/binman/bintool.py
index 0b0f56d..3c4ad1a 100644
--- a/tools/binman/bintool.py
+++ b/tools/binman/bintool.py
@@ -328,7 +328,7 @@
return result.stdout
@classmethod
- def build_from_git(cls, git_repo, make_target, bintool_path, flags=None):
+ def build_from_git(cls, git_repo, make_targets, bintool_path, flags=None):
"""Build a bintool from a git repo
This clones the repo in a temporary directory, builds it with 'make',
@@ -336,7 +336,8 @@
Args:
git_repo (str): URL of git repo
- make_target (str): Target to pass to 'make' to build the tool
+ make_targets (list of str): List of targets to pass to 'make' to build
+ the tool
bintool_path (str): Relative path of the tool in the repo, after
build is complete
flags (list of str): Flags or variables to pass to make, or None
@@ -350,12 +351,14 @@
tmpdir = tempfile.mkdtemp(prefix='binmanf.')
print(f"- clone git repo '{git_repo}' to '{tmpdir}'")
tools.run('git', 'clone', '--depth', '1', git_repo, tmpdir)
- print(f"- build target '{make_target}'")
- cmd = ['make', '-C', tmpdir, '-j', f'{multiprocessing.cpu_count()}',
- make_target]
- if flags:
- cmd += flags
- tools.run(*cmd)
+ for target in make_targets:
+ print(f"- build target '{target}'")
+ cmd = ['make', '-C', tmpdir, '-j', f'{multiprocessing.cpu_count()}',
+ target]
+ if flags:
+ cmd += flags
+ tools.run(*cmd)
+
fname = os.path.join(tmpdir, bintool_path)
if not os.path.exists(fname):
print(f"- File '{fname}' was not produced")
diff --git a/tools/binman/bintools.rst b/tools/binman/bintools.rst
index 20ee243..1336f4d 100644
--- a/tools/binman/bintools.rst
+++ b/tools/binman/bintools.rst
@@ -208,7 +208,7 @@
Bintool: bootgen: Sign ZynqMP FSBL image
----------------------------------------------
+----------------------------------------
This bintool supports running `bootgen` in order to sign a SPL for ZynqMP
devices.
diff --git a/tools/binman/btool/bootgen.py b/tools/binman/btool/bootgen.py
new file mode 100644
index 0000000..f2ca552
--- /dev/null
+++ b/tools/binman/btool/bootgen.py
@@ -0,0 +1,137 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2023 Weidmüller Interface GmbH & Co. KG
+# Lukas Funke <lukas.funke@weidmueller.com>
+#
+"""Bintool implementation for bootgen
+
+bootgen allows creating bootable SPL for Zynq(MP)
+
+Documentation is available via:
+https://www.xilinx.com/support/documents/sw_manuals/xilinx2022_1/ug1283-bootgen-user-guide.pdf
+
+Source code is available at:
+https://github.com/Xilinx/bootgen
+
+"""
+
+from binman import bintool
+from u_boot_pylib import tools
+
+# pylint: disable=C0103
+class Bintoolbootgen(bintool.Bintool):
+ """Generate bootable fsbl image for zynq/zynqmp
+
+ This bintools supports running Xilinx "bootgen" in order
+ to generate a bootable, authenticated image form an SPL.
+
+ """
+ def __init__(self, name):
+ super().__init__(name, 'Xilinx Bootgen',
+ version_regex=r'^\*\*\*\*\*\* *Xilinx Bootgen *(.*)',
+ version_args='-help')
+
+ # pylint: disable=R0913
+ def sign(self, arch, spl_elf_fname, pmufw_elf_fname,
+ psk_fname, ssk_fname, fsbl_config, auth_params, keysrc_enc,
+ output_fname):
+ """Sign SPL elf file and bundle it with PMU firmware into an image
+
+ The method bundels the SPL together with a 'Platform Management Unit'
+ (PMU)[1] firmware into a single bootable image. The image in turn is
+ signed with the provided 'secondary secret key' (ssk), which in turn is
+ signed with the 'primary secret key' (psk). In order to verify the
+ authenticity of the ppk, it's hash has to be fused into the device
+ itself.
+
+ In Xilinx terms the SPL is usually called 'FSBL'
+ (First Stage Boot Loader). The jobs of the SPL and the FSBL are mostly
+ the same: load bitstream, bootstrap u-boot.
+
+ Args:
+ arch (str): Xilinx SoC architecture. Currently only 'zynqmp' is
+ supported.
+ spl_elf_fname (str): Filename of SPL ELF file. The filename must end
+ with '.elf' in order for bootgen to recognized it as an ELF
+ file. Otherwise the start address field is missinterpreted.
+ pmufw_elf_fname (str): Filename PMU ELF firmware.
+ psk_fname (str): Filename of the primary secret key (psk). The psk
+ is a .pem file which holds the RSA private key used for signing
+ the secondary secret key.
+ ssk_fname (str): Filename of the secondary secret key. The ssk
+ is a .pem file which holds the RSA private key used for signing
+ the actual boot firmware.
+ fsbl_config (str): FSBL config options. A string list of fsbl config
+ options. Valid values according to [2] are:
+ "bh_auth_enable": Boot Header Authentication Enable: RSA
+ authentication of the bootimage is done
+ excluding the verification of PPK hash and SPK ID. This is
+ useful for debugging before bricking a device.
+ "auth_only": Boot image is only RSA signed. FSBL should not be
+ decrypted. See the
+ Zynq UltraScale+ Device Technical Reference Manual (UG1085)
+ for more information.
+ There are more options which relate to PUF (physical unclonable
+ functions). Please refer to Xilinx manuals for further info.
+ auth_params (str): Authentication parameter. A semicolon separated
+ list of authentication parameters. Valid values according to [3]
+ are:
+ "ppk_select=<0|1>" - Select which ppk to use
+ "spk_id=<32-bit spk id>" - Specifies which SPK can be
+ used or revoked, default is 0x0
+ "spk_select=<spk-efuse/user-efuse>" - To differentiate spk and
+ user efuses.
+ "auth_header" - To authenticate headers when no partition
+ is authenticated.
+ keysrc_enc (str): This specifies the Key source for encryption.
+ Valid values according to [3] are:
+ "bbram_red_key" - RED key stored in BBRAM
+ "efuse_red_key" - RED key stored in eFUSE
+ "efuse_gry_key" - Grey (Obfuscated) Key stored in eFUSE.
+ "bh_gry_key" - Grey (Obfuscated) Key stored in boot header
+ "bh_blk_key" - Black Key stored in boot header
+ "efuse_blk_key" - Black Key stored in eFUSE
+ "kup_key" - User Key
+
+ output_fname (str): Filename where bootgen should write the result
+
+ Returns:
+ str: Bootgen output from stdout
+
+ [1] https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841724/PMU+Firmware
+ [2] https://docs.xilinx.com/r/en-US/ug1283-bootgen-user-guide/fsbl_config
+ [3] https://docs.xilinx.com/r/en-US/ug1283-bootgen-user-guide/auth_params
+ [4] https://docs.xilinx.com/r/en-US/ug1283-bootgen-user-guide/keysrc_encryption
+ """
+
+ _fsbl_config = f"[fsbl_config] {fsbl_config}" if fsbl_config else ""
+ _auth_params = f"[auth_params] {auth_params}" if auth_params else ""
+ _keysrc_enc = f"[keysrc_encryption] {keysrc_enc}" if keysrc_enc else ""
+
+ bif_template = f"""u_boot_spl_aes_rsa: {{
+ [pskfile] {psk_fname}
+ [sskfile] {ssk_fname}
+ {_keysrc_enc}
+ {_fsbl_config}
+ {_auth_params}
+ [ bootloader,
+ authentication = rsa,
+ destination_cpu=a53-0] {spl_elf_fname}
+ [pmufw_image] {pmufw_elf_fname}
+ }}"""
+ args = ["-arch", arch]
+
+ bif_fname = tools.get_output_filename('bootgen-in.sign.bif')
+ tools.write_file(bif_fname, bif_template, False)
+ args += ["-image", bif_fname, '-w', '-o', output_fname]
+ return self.run_cmd(*args)
+
+ def fetch(self, method):
+ """Fetch bootgen from git"""
+ if method != bintool.FETCH_BUILD:
+ return None
+
+ result = self.build_from_git(
+ 'https://github.com/Xilinx/bootgen',
+ 'all',
+ 'bootgen')
+ return result
diff --git a/tools/binman/btool/mkeficapsule.py b/tools/binman/btool/mkeficapsule.py
new file mode 100644
index 0000000..6117974
--- /dev/null
+++ b/tools/binman/btool/mkeficapsule.py
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2023 Linaro Limited
+#
+"""Bintool implementation for mkeficapsule tool
+
+mkeficapsule is a tool used for generating EFI capsules.
+
+The following are the commandline options to be provided
+to the tool
+Usage: mkeficapsule [options] <image blob> <output file>
+Options:
+ -g, --guid <guid string> guid for image blob type
+ -i, --index <index> update image index
+ -I, --instance <instance> update hardware instance
+ -v, --fw-version <version> firmware version
+ -p, --private-key <privkey file> private key file
+ -c, --certificate <cert file> signer's certificate file
+ -m, --monotonic-count <count> monotonic count
+ -d, --dump_sig dump signature (*.p7)
+ -A, --fw-accept firmware accept capsule, requires GUID, no image blob
+ -R, --fw-revert firmware revert capsule, takes no GUID, no image blob
+ -o, --capoemflag Capsule OEM Flag, an integer between 0x0000 and 0xffff
+ -h, --help print a help message
+"""
+
+from binman import bintool
+
+class Bintoolmkeficapsule(bintool.Bintool):
+ """Handles the 'mkeficapsule' tool
+
+ This bintool is used for generating the EFI capsules. The
+ capsule generation parameters can either be specified through
+ commandline, or through a config file.
+ """
+ def __init__(self, name):
+ super().__init__(name, 'mkeficapsule tool for generating capsules')
+
+ def generate_capsule(self, image_index, image_guid, hardware_instance,
+ payload, output_fname, priv_key, pub_key,
+ monotonic_count=0, version=0, oemflags=0):
+ """Generate a capsule through commandline-provided parameters
+
+ Args:
+ image_index (int): Unique number for identifying payload image
+ image_guid (str): GUID used for identifying the image
+ hardware_instance (int): Optional unique hardware instance of
+ a device in the system. 0 if not being used
+ payload (str): Path to the input payload image
+ output_fname (str): Path to the output capsule file
+ priv_key (str): Path to the private key
+ pub_key(str): Path to the public key
+ monotonic_count (int): Count used when signing an image
+ version (int): Image version (Optional)
+ oemflags (int): Optional 16 bit OEM flags
+
+ Returns:
+ str: Tool output
+ """
+ args = [
+ f'--index={image_index}',
+ f'--guid={image_guid}',
+ f'--instance={hardware_instance}'
+ ]
+
+ if version:
+ args += [f'--fw-version={version}']
+ if oemflags:
+ args += [f'--capoemflag={oemflags}']
+ if priv_key and pub_key:
+ args += [
+ f'--monotonic-count={monotonic_count}',
+ f'--private-key={priv_key}',
+ f'--certificate={pub_key}'
+ ]
+
+ args += [
+ payload,
+ output_fname
+ ]
+
+ return self.run_cmd(*args)
+
+ def fetch(self, method):
+ """Fetch handler for mkeficapsule
+
+ This builds the tool from source
+
+ Returns:
+ tuple:
+ str: Filename of fetched file to copy to a suitable directory
+ str: Name of temp directory to remove, or None
+ """
+ if method != bintool.FETCH_BUILD:
+ return None
+
+ cmd = ['tools-only_defconfig', 'tools']
+ result = self.build_from_git(
+ 'https://source.denx.de/u-boot/u-boot.git',
+ cmd,
+ 'tools/mkeficapsule')
+ return result
diff --git a/tools/binman/cmdline.py b/tools/binman/cmdline.py
index 9632ec1..39c61c2 100644
--- a/tools/binman/cmdline.py
+++ b/tools/binman/cmdline.py
@@ -126,6 +126,8 @@
help='Comma-separated list of bintools to consider missing (for testing)')
build_parser.add_argument('-i', '--image', type=str, action='append',
help='Image filename to build (if not specified, build all)')
+ build_parser.add_argument('--ignore-dup-phandles', action='store_true',
+ help='Temporary option to ignore duplicate phandles')
build_parser.add_argument('-I', '--indir', action='append',
help='Add a path to the list of directories to use for input files')
build_parser.add_argument('-m', '--map', action='store_true',
diff --git a/tools/binman/control.py b/tools/binman/control.py
index d1ee1d6..4594895 100644
--- a/tools/binman/control.py
+++ b/tools/binman/control.py
@@ -22,6 +22,7 @@
from binman import cbfs_util
from binman import elf
from binman import entry
+from dtoc import fdt
from dtoc import fdt_util
from u_boot_pylib import command
from u_boot_pylib import tools
@@ -57,7 +58,7 @@
images = OrderedDict()
if 'multiple-images' in binman_node.props:
for node in binman_node.subnodes:
- if 'template' not in node.name:
+ if not node.name.startswith('template'):
images[node.name] = Image(node.name, node,
use_expanded=use_expanded)
else:
@@ -112,12 +113,13 @@
_FinishTag(tag, msg, result)
return result
-def _ShowBlobHelp(path, text):
- tout.warning('\n%s:' % path)
+def _ShowBlobHelp(level, path, text, fname):
+ tout.do_output(level, '%s (%s):' % (path, fname))
for line in text.splitlines():
- tout.warning(' %s' % line)
+ tout.do_output(level, ' %s' % line)
+ tout.do_output(level, '')
-def _ShowHelpForMissingBlobs(missing_list):
+def _ShowHelpForMissingBlobs(level, missing_list):
"""Show help for each missing blob to help the user take action
Args:
@@ -132,10 +134,17 @@
tags = entry.GetHelpTags()
# Show the first match help message
+ shown_help = False
for tag in tags:
if tag in missing_blob_help:
- _ShowBlobHelp(entry._node.path, missing_blob_help[tag])
+ _ShowBlobHelp(level, entry._node.path, missing_blob_help[tag],
+ entry.GetDefaultFilename())
+ shown_help = True
break
+ # Or a generic help message
+ if not shown_help:
+ _ShowBlobHelp(level, entry._node.path, "Missing blob",
+ entry.GetDefaultFilename())
def GetEntryModules(include_testing=True):
"""Get a set of entry class implementations
@@ -486,6 +495,9 @@
Args:
parent: Binman node to process (typically /binman)
+ Returns:
+ bool: True if any templates were processed
+
Search though each target node looking for those with an 'insert-template'
property. Use that as a list of references to template nodes to use to
adjust the target node.
@@ -498,11 +510,22 @@
See 'Templates' in the Binman documnentation for details.
"""
+ found = False
for node in parent.subnodes:
tmpl = fdt_util.GetPhandleList(node, 'insert-template')
if tmpl:
node.copy_subnodes_from_phandles(tmpl)
- _ProcessTemplates(node)
+ found = True
+
+ found |= _ProcessTemplates(node)
+ return found
+
+def _RemoveTemplates(parent):
+ """Remove any templates in the binman description
+ """
+ for node in parent.subnodes:
+ if node.name.startswith('template'):
+ node.Delete()
def PrepareImagesAndDtbs(dtb_fname, select_images, update_fdt, use_expanded):
"""Prepare the images to be processed and select the device tree
@@ -546,7 +569,19 @@
raise ValueError("Device tree '%s' does not have a 'binman' "
"node" % dtb_fname)
+ if _ProcessTemplates(node):
+ dtb.Sync(True)
+ fname = tools.get_output_filename('u-boot.dtb.tmpl1')
+ tools.write_file(fname, dtb.GetContents())
+
- _ProcessTemplates(node)
+ _RemoveTemplates(node)
+ dtb.Sync(True)
+
+ # Rescan the dtb to pick up the new phandles
+ dtb.Scan()
+ node = _FindBinmanNode(dtb)
+ fname = tools.get_output_filename('u-boot.dtb.tmpl2')
+ tools.write_file(fname, dtb.GetContents())
images = _ReadImageDesc(node, use_expanded)
@@ -658,15 +693,15 @@
missing_list = []
image.CheckMissing(missing_list)
if missing_list:
- tout.warning("Image '%s' is missing external blobs and is non-functional: %s" %
- (image.name, ' '.join([e.name for e in missing_list])))
- _ShowHelpForMissingBlobs(missing_list)
+ tout.error("Image '%s' is missing external blobs and is non-functional: %s\n" %
+ (image.name, ' '.join([e.name for e in missing_list])))
+ _ShowHelpForMissingBlobs(tout.ERROR, missing_list)
faked_list = []
image.CheckFakedBlobs(faked_list)
if faked_list:
tout.warning(
- "Image '%s' has faked external blobs and is non-functional: %s" %
+ "Image '%s' has faked external blobs and is non-functional: %s\n" %
(image.name, ' '.join([os.path.basename(e.GetDefaultFilename())
for e in faked_list])))
@@ -674,15 +709,15 @@
image.CheckOptional(optional_list)
if optional_list:
tout.warning(
- "Image '%s' is missing external blobs but is still functional: %s" %
+ "Image '%s' is missing optional external blobs but is still functional: %s\n" %
(image.name, ' '.join([e.name for e in optional_list])))
- _ShowHelpForMissingBlobs(optional_list)
+ _ShowHelpForMissingBlobs(tout.WARNING, optional_list)
missing_bintool_list = []
image.check_missing_bintools(missing_bintool_list)
if missing_bintool_list:
tout.warning(
- "Image '%s' has missing bintools and is non-functional: %s" %
+ "Image '%s' has missing bintools and is non-functional: %s\n" %
(image.name, ' '.join([os.path.basename(bintool.name)
for bintool in missing_bintool_list])))
return any([missing_list, faked_list, missing_bintool_list])
@@ -782,6 +817,10 @@
cbfs_util.VERBOSE = args.verbosity > 2
state.use_fake_dtb = args.fake_dtb
+ # Temporary hack
+ if args.ignore_dup_phandles: # pragma: no cover
+ fdt.IGNORE_DUP_PHANDLES = True
+
# Normally we replace the 'u-boot' etype with 'u-boot-expanded', etc.
# When running tests this can be disabled using this flag. When not
# updating the FDT in image, it is not needed by binman, but we use it
@@ -827,7 +866,7 @@
# This can only be True if -M is provided, since otherwise binman
# would have raised an error already
if invalid:
- msg = '\nSome images are invalid'
+ msg = 'Some images are invalid'
if args.ignore_missing:
tout.warning(msg)
else:
diff --git a/tools/binman/elf.py b/tools/binman/elf.py
index 4219001..2ecc95f 100644
--- a/tools/binman/elf.py
+++ b/tools/binman/elf.py
@@ -447,13 +447,15 @@
Returns:
ElfInfo object containing information about the decoded ELF file
"""
+ if not ELF_TOOLS:
+ raise ValueError("Python: No module named 'elftools'")
file_size = len(data)
with io.BytesIO(data) as fd:
elf = ELFFile(fd)
- data_start = 0xffffffff;
- data_end = 0;
- mem_end = 0;
- virt_to_phys = 0;
+ data_start = 0xffffffff
+ data_end = 0
+ mem_end = 0
+ virt_to_phys = 0
for i in range(elf.num_segments()):
segment = elf.get_segment(i)
diff --git a/tools/binman/elf_test.py b/tools/binman/elf_test.py
index cc95b42..e3dee79 100644
--- a/tools/binman/elf_test.py
+++ b/tools/binman/elf_test.py
@@ -255,8 +255,20 @@
fname = self.ElfTestFile('embed_data')
with self.assertRaises(ValueError) as e:
elf.GetSymbolFileOffset(fname, ['embed_start', 'embed_end'])
- self.assertIn("Python: No module named 'elftools'",
- str(e.exception))
+ with self.assertRaises(ValueError) as e:
+ elf.DecodeElf(tools.read_file(fname), 0xdeadbeef)
+ with self.assertRaises(ValueError) as e:
+ elf.GetFileOffset(fname, 0xdeadbeef)
+ with self.assertRaises(ValueError) as e:
+ elf.GetSymbolFromAddress(fname, 0xdeadbeef)
+ with self.assertRaises(ValueError) as e:
+ entry = FakeEntry(10)
+ section = FakeSection()
+ elf.LookupAndWriteSymbols(fname, entry, section, True)
+
+ self.assertIn(
+ "Section 'section_path': entry 'entry_path': Cannot write symbols to an ELF file without Python elftools",
+ str(e.exception))
finally:
elf.ELF_TOOLS = old_val
diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst
index f237693..801bd94 100644
--- a/tools/binman/entries.rst
+++ b/tools/binman/entries.rst
@@ -468,6 +468,70 @@
+.. _etype_efi_capsule:
+
+Entry: capsule: Entry for generating EFI Capsule files
+------------------------------------------------------
+
+The parameters needed for generation of the capsules can be provided
+as properties in the entry.
+
+Properties / Entry arguments:
+ - image-index: Unique number for identifying corresponding
+ payload image. Number between 1 and descriptor count, i.e.
+ the total number of firmware images that can be updated. Mandatory
+ property.
+ - image-guid: Image GUID which will be used for identifying the
+ updatable image on the board. Mandatory property.
+ - hardware-instance: Optional number for identifying unique
+ hardware instance of a device in the system. Default value of 0
+ for images where value is not to be used.
+ - fw-version: Value of image version that can be put on the capsule
+ through the Firmware Management Protocol(FMP) header.
+ - monotonic-count: Count used when signing an image.
+ - private-key: Path to PEM formatted .key private key file. Mandatory
+ property for generating signed capsules.
+ - public-key-cert: Path to PEM formatted .crt public key certificate
+ file. Mandatory property for generating signed capsules.
+ - oem-flags - OEM flags to be passed through capsule header.
+
+ Since this is a subclass of Entry_section, all properties of the parent
+ class also apply here. Except for the properties stated as mandatory, the
+ rest of the properties are optional.
+
+For more details on the description of the capsule format, and the capsule
+update functionality, refer Section 8.5 and Chapter 23 in the `UEFI
+specification`_.
+
+The capsule parameters like image index and image GUID are passed as
+properties in the entry. The payload to be used in the capsule is to be
+provided as a subnode of the capsule entry.
+
+A typical capsule entry node would then look something like this::
+
+ capsule {
+ type = "efi-capsule";
+ image-index = <0x1>;
+ /* Image GUID for testing capsule update */
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+ hardware-instance = <0x0>;
+ private-key = "path/to/the/private/key";
+ public-key-cert = "path/to/the/public-key-cert";
+ oem-flags = <0x8000>;
+
+ u-boot {
+ };
+ };
+
+In the above example, the capsule payload is the U-Boot image. The
+capsule entry would read the contents of the payload and put them
+into the capsule. Any external file can also be specified as the
+payload using the blob-ext subnode.
+
+.. _`UEFI specification`: https://uefi.org/sites/default/files/resources/UEFI_Spec_2_10_Aug29.pdf
+
+
+
.. _etype_encrypted:
Entry: encrypted: Externally built encrypted binary blob
@@ -2667,3 +2731,78 @@
+.. _etype_xilinx_bootgen:
+
+Entry: xilinx-bootgen: Signed SPL boot image for Xilinx ZynqMP devices
+----------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - auth-params: (Optional) Authentication parameters passed to bootgen
+ - fsbl-config: (Optional) FSBL parameters passed to bootgen
+ - keysrc-enc: (Optional) Key source when using decryption engine
+ - pmufw-filename: Filename of PMU firmware. Default: pmu-firmware.elf
+ - psk-key-name-hint: Name of primary secret key to use for signing the
+ secondardy public key. Format: .pem file
+ - ssk-key-name-hint: Name of secondardy secret key to use for signing
+ the boot image. Format: .pem file
+
+The etype is used to create a boot image for Xilinx ZynqMP
+devices.
+
+Information for signed images:
+
+In AMD/Xilinx SoCs, two pairs of public and secret keys are used
+- primary and secondary. The function of the primary public/secret key pair
+is to authenticate the secondary public/secret key pair.
+The function of the secondary key is to sign/verify the boot image. [1]
+
+AMD/Xilinx uses the following terms for private/public keys [1]:
+
+ PSK = Primary Secret Key (Used to sign Secondary Public Key)
+ PPK = Primary Public Key (Used to verify Secondary Public Key)
+ SSK = Secondary Secret Key (Used to sign the boot image/partitions)
+ SPK = Used to verify the actual boot image
+
+The following example builds a signed boot image. The fuses of
+the primary public key (ppk) should be fused together with the RSA_EN flag.
+
+Example node::
+
+ spl {
+ filename = "boot.signed.bin";
+
+ xilinx-bootgen {
+ psk-key-name-hint = "psk0";
+ ssk-key-name-hint = "ssk0";
+ auth-params = "ppk_select=0", "spk_id=0x00000000";
+
+ u-boot-spl-nodtb {
+ };
+ u-boot-spl-pubkey-dtb {
+ algo = "sha384,rsa4096";
+ required = "conf";
+ key-name-hint = "dev";
+ };
+ };
+ };
+
+For testing purposes, e.g. if no RSA_EN should be fused, one could add
+the "bh_auth_enable" flag in the fsbl-config field. This will skip the
+verification of the ppk fuses and boot the image, even if ppk hash is
+invalid.
+
+Example node::
+
+ xilinx-bootgen {
+ psk-key-name-hint = "psk0";
+ psk-key-name-hint = "ssk0";
+ ...
+ fsbl-config = "bh_auth_enable";
+ ...
+ };
+
+[1] https://docs.xilinx.com/r/en-US/ug1283-bootgen-user-guide/Using-Authentication
+
+
+
+
diff --git a/tools/binman/etype/efi_capsule.py b/tools/binman/etype/efi_capsule.py
new file mode 100644
index 0000000..006eb63
--- /dev/null
+++ b/tools/binman/etype/efi_capsule.py
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2023 Linaro Limited
+#
+# Entry-type module for producing a EFI capsule
+#
+
+import os
+
+from binman.entry import Entry
+from binman.etype.section import Entry_section
+from dtoc import fdt_util
+from u_boot_pylib import tools
+
+class Entry_efi_capsule(Entry_section):
+ """Generate EFI capsules
+
+ The parameters needed for generation of the capsules can
+ be provided as properties in the entry.
+
+ Properties / Entry arguments:
+ - image-index: Unique number for identifying corresponding
+ payload image. Number between 1 and descriptor count, i.e.
+ the total number of firmware images that can be updated. Mandatory
+ property.
+ - image-guid: Image GUID which will be used for identifying the
+ updatable image on the board. Mandatory property.
+ - hardware-instance: Optional number for identifying unique
+ hardware instance of a device in the system. Default value of 0
+ for images where value is not to be used.
+ - fw-version: Value of image version that can be put on the capsule
+ through the Firmware Management Protocol(FMP) header.
+ - monotonic-count: Count used when signing an image.
+ - private-key: Path to PEM formatted .key private key file. Mandatory
+ property for generating signed capsules.
+ - public-key-cert: Path to PEM formatted .crt public key certificate
+ file. Mandatory property for generating signed capsules.
+ - oem-flags - OEM flags to be passed through capsule header.
+
+ Since this is a subclass of Entry_section, all properties of the parent
+ class also apply here. Except for the properties stated as mandatory, the
+ rest of the properties are optional.
+
+ For more details on the description of the capsule format, and the capsule
+ update functionality, refer Section 8.5 and Chapter 23 in the `UEFI
+ specification`_.
+
+ The capsule parameters like image index and image GUID are passed as
+ properties in the entry. The payload to be used in the capsule is to be
+ provided as a subnode of the capsule entry.
+
+ A typical capsule entry node would then look something like this
+
+ capsule {
+ type = "efi-capsule";
+ image-index = <0x1>;
+ /* Image GUID for testing capsule update */
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+ hardware-instance = <0x0>;
+ private-key = "path/to/the/private/key";
+ public-key-cert = "path/to/the/public-key-cert";
+ oem-flags = <0x8000>;
+
+ u-boot {
+ };
+ };
+
+ In the above example, the capsule payload is the U-Boot image. The
+ capsule entry would read the contents of the payload and put them
+ into the capsule. Any external file can also be specified as the
+ payload using the blob-ext subnode.
+
+ .. _`UEFI specification`: https://uefi.org/sites/default/files/resources/UEFI_Spec_2_10_Aug29.pdf
+ """
+ def __init__(self, section, etype, node):
+ super().__init__(section, etype, node)
+ self.required_props = ['image-index', 'image-guid']
+ self.image_index = 0
+ self.image_guid = ''
+ self.hardware_instance = 0
+ self.monotonic_count = 0
+ self.fw_version = 0
+ self.oem_flags = 0
+ self.private_key = ''
+ self.public_key_cert = ''
+ self.auth = 0
+
+ def ReadNode(self):
+ super().ReadNode()
+
+ self.image_index = fdt_util.GetInt(self._node, 'image-index')
+ self.image_guid = fdt_util.GetString(self._node, 'image-guid')
+ self.fw_version = fdt_util.GetInt(self._node, 'fw-version')
+ self.hardware_instance = fdt_util.GetInt(self._node, 'hardware-instance')
+ self.monotonic_count = fdt_util.GetInt(self._node, 'monotonic-count')
+ self.oem_flags = fdt_util.GetInt(self._node, 'oem-flags')
+
+ self.private_key = fdt_util.GetString(self._node, 'private-key')
+ self.public_key_cert = fdt_util.GetString(self._node, 'public-key-cert')
+ if ((self.private_key and not self.public_key_cert) or (self.public_key_cert and not self.private_key)):
+ self.Raise('Both private key and public key certificate need to be provided')
+ elif not (self.private_key and self.public_key_cert):
+ self.auth = 0
+ else:
+ self.auth = 1
+
+ def BuildSectionData(self, required):
+ def get_binman_test_guid(type_str):
+ TYPE_TO_GUID = {
+ 'binman-test' : '09d7cf52-0720-4710-91d1-08469b7fe9c8'
+ }
+ return TYPE_TO_GUID[type_str]
+
+ private_key = ''
+ public_key_cert = ''
+ if self.auth:
+ if not os.path.isabs(self.private_key):
+ private_key = tools.get_input_filename(self.private_key)
+ if not os.path.isabs(self.public_key_cert):
+ public_key_cert = tools.get_input_filename(self.public_key_cert)
+ data, payload, uniq = self.collect_contents_to_file(
+ self._entries.values(), 'capsule_in')
+ outfile = self._filename if self._filename else 'capsule.%s' % uniq
+ capsule_fname = tools.get_output_filename(outfile)
+ guid = self.image_guid
+ if self.image_guid == "binman-test":
+ guid = get_binman_test_guid('binman-test')
+
+ ret = self.mkeficapsule.generate_capsule(self.image_index,
+ guid,
+ self.hardware_instance,
+ payload,
+ capsule_fname,
+ private_key,
+ public_key_cert,
+ self.monotonic_count,
+ self.fw_version,
+ self.oem_flags)
+ if ret is not None:
+ os.remove(payload)
+ return tools.read_file(capsule_fname)
+
+ def AddBintools(self, btools):
+ self.mkeficapsule = self.AddBintool(btools, 'mkeficapsule')
diff --git a/tools/binman/etype/fit.py b/tools/binman/etype/fit.py
index ef4d066..2c14b15 100644
--- a/tools/binman/etype/fit.py
+++ b/tools/binman/etype/fit.py
@@ -842,6 +842,13 @@
for entry in self._priv_entries.values():
entry.CheckMissing(missing_list)
+ def CheckOptional(self, optional_list):
+ # We must use our private entry list for this since generator nodes
+ # which are removed from self._entries will otherwise not show up as
+ # optional
+ for entry in self._priv_entries.values():
+ entry.CheckOptional(optional_list)
+
def CheckEntries(self):
pass
diff --git a/tools/binman/etype/xilinx_bootgen.py b/tools/binman/etype/xilinx_bootgen.py
new file mode 100644
index 0000000..70a4b2e
--- /dev/null
+++ b/tools/binman/etype/xilinx_bootgen.py
@@ -0,0 +1,225 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2023 Weidmueller GmbH
+# Written by Lukas Funke <lukas.funke@weidmueller.com>
+#
+# Entry-type module for Zynq(MP) boot images (boot.bin)
+#
+
+import tempfile
+
+from collections import OrderedDict
+
+from binman import elf
+from binman.etype.section import Entry_section
+
+from dtoc import fdt_util
+
+from u_boot_pylib import tools
+from u_boot_pylib import command
+
+# pylint: disable=C0103
+class Entry_xilinx_bootgen(Entry_section):
+ """Signed SPL boot image for Xilinx ZynqMP devices
+
+ Properties / Entry arguments:
+ - auth-params: (Optional) Authentication parameters passed to bootgen
+ - fsbl-config: (Optional) FSBL parameters passed to bootgen
+ - keysrc-enc: (Optional) Key source when using decryption engine
+ - pmufw-filename: Filename of PMU firmware. Default: pmu-firmware.elf
+ - psk-key-name-hint: Name of primary secret key to use for signing the
+ secondardy public key. Format: .pem file
+ - ssk-key-name-hint: Name of secondardy secret key to use for signing
+ the boot image. Format: .pem file
+
+ The etype is used to create a boot image for Xilinx ZynqMP
+ devices.
+
+ Information for signed images:
+
+ In AMD/Xilinx SoCs, two pairs of public and secret keys are used
+ - primary and secondary. The function of the primary public/secret key pair
+ is to authenticate the secondary public/secret key pair.
+ The function of the secondary key is to sign/verify the boot image. [1]
+
+ AMD/Xilinx uses the following terms for private/public keys [1]:
+
+ PSK = Primary Secret Key (Used to sign Secondary Public Key)
+ PPK = Primary Public Key (Used to verify Secondary Public Key)
+ SSK = Secondary Secret Key (Used to sign the boot image/partitions)
+ SPK = Used to verify the actual boot image
+
+ The following example builds a signed boot image. The fuses of
+ the primary public key (ppk) should be fused together with the RSA_EN flag.
+
+ Example node::
+
+ spl {
+ filename = "boot.signed.bin";
+
+ xilinx-bootgen {
+ psk-key-name-hint = "psk0";
+ ssk-key-name-hint = "ssk0";
+ auth-params = "ppk_select=0", "spk_id=0x00000000";
+
+ u-boot-spl-nodtb {
+ };
+ u-boot-spl-pubkey-dtb {
+ algo = "sha384,rsa4096";
+ required = "conf";
+ key-name-hint = "dev";
+ };
+ };
+ };
+
+ For testing purposes, e.g. if no RSA_EN should be fused, one could add
+ the "bh_auth_enable" flag in the fsbl-config field. This will skip the
+ verification of the ppk fuses and boot the image, even if ppk hash is
+ invalid.
+
+ Example node::
+
+ xilinx-bootgen {
+ psk-key-name-hint = "psk0";
+ psk-key-name-hint = "ssk0";
+ ...
+ fsbl-config = "bh_auth_enable";
+ ...
+ };
+
+ [1] https://docs.xilinx.com/r/en-US/ug1283-bootgen-user-guide/Using-Authentication
+
+ """
+ def __init__(self, section, etype, node):
+ super().__init__(section, etype, node)
+ self._auth_params = None
+ self._entries = OrderedDict()
+ self._filename = None
+ self._fsbl_config = None
+ self._keysrc_enc = None
+ self._pmufw_filename = None
+ self._psk_key_name_hint = None
+ self._ssk_key_name_hint = None
+ self.align_default = None
+ self.bootgen = None
+ self.required_props = ['pmufw-filename',
+ 'psk-key-name-hint',
+ 'ssk-key-name-hint']
+
+ def ReadNode(self):
+ """Read properties from the xilinx-bootgen node"""
+ super().ReadNode()
+ self._auth_params = fdt_util.GetStringList(self._node,
+ 'auth-params')
+ self._filename = fdt_util.GetString(self._node, 'filename')
+ self._fsbl_config = fdt_util.GetStringList(self._node,
+ 'fsbl-config')
+ self._keysrc_enc = fdt_util.GetString(self._node,
+ 'keysrc-enc')
+ self._pmufw_filename = fdt_util.GetString(self._node, 'pmufw-filename')
+ self._psk_key_name_hint = fdt_util.GetString(self._node,
+ 'psk-key-name-hint')
+ self._ssk_key_name_hint = fdt_util.GetString(self._node,
+ 'ssk-key-name-hint')
+ self.ReadEntries()
+
+ @classmethod
+ def _ToElf(cls, data, output_fname):
+ """Convert SPL object file to bootable ELF file
+
+ Args:
+ data (bytearray): u-boot-spl-nodtb + u-boot-spl-pubkey-dtb obj file
+ data
+ output_fname (str): Filename of converted FSBL ELF file
+ """
+ platform_elfflags = {"aarch64":
+ ["-B", "aarch64", "-O", "elf64-littleaarch64"],
+ # amd64 support makes no sense for the target
+ # platform, but we include it here to enable
+ # testing on hosts
+ "x86_64":
+ ["-B", "i386", "-O", "elf64-x86-64"]
+ }
+
+ gcc, args = tools.get_target_compile_tool('cc')
+ args += ['-dumpmachine']
+ stdout = command.output(gcc, *args)
+ # split target machine triplet (arch, vendor, os)
+ arch, _, _ = stdout.split('-')
+
+ spl_elf = elf.DecodeElf(tools.read_file(
+ tools.get_input_filename('spl/u-boot-spl')), 0)
+
+ # Obj file to swap data and text section (rename-section)
+ with tempfile.NamedTemporaryFile(prefix="u-boot-spl-pubkey-",
+ suffix=".o.tmp",
+ dir=tools.get_output_dir())\
+ as tmp_obj:
+ input_objcopy_fname = tmp_obj.name
+ # Align packed content to 4 byte boundary
+ pad = bytearray(tools.align(len(data), 4) - len(data))
+ tools.write_file(input_objcopy_fname, data + pad)
+ # Final output elf file which contains a valid start address
+ with tempfile.NamedTemporaryFile(prefix="u-boot-spl-pubkey-elf-",
+ suffix=".o.tmp",
+ dir=tools.get_output_dir())\
+ as tmp_elf_obj:
+ input_ld_fname = tmp_elf_obj.name
+ objcopy, args = tools.get_target_compile_tool('objcopy')
+ args += ["--rename-section", ".data=.text",
+ "-I", "binary"]
+ args += platform_elfflags[arch]
+ args += [input_objcopy_fname, input_ld_fname]
+ command.run(objcopy, *args)
+
+ ld, args = tools.get_target_compile_tool('ld')
+ args += [input_ld_fname, '-o', output_fname,
+ "--defsym", f"_start={hex(spl_elf.entry)}",
+ "-Ttext", hex(spl_elf.entry)]
+ command.run(ld, *args)
+
+ def BuildSectionData(self, required):
+ """Pack node content, and create bootable, signed ZynqMP boot image
+
+ The method collects the content of this node (usually SPL + dtb) and
+ converts them to an ELF file. The ELF file is passed to the
+ Xilinx bootgen tool which packs the SPL ELF file together with
+ Platform Management Unit (PMU) firmware into a bootable image
+ for ZynqMP devices. The image is signed within this step.
+
+ The result is a bootable, signed SPL image for Xilinx ZynqMP devices.
+ """
+ data = super().BuildSectionData(required)
+ bootbin_fname = self._filename if self._filename else \
+ tools.get_output_filename(
+ f'boot.{self.GetUniqueName()}.bin')
+
+ pmufw_elf_fname = tools.get_input_filename(self._pmufw_filename)
+ psk_fname = tools.get_input_filename(self._psk_key_name_hint + ".pem")
+ ssk_fname = tools.get_input_filename(self._ssk_key_name_hint + ".pem")
+ fsbl_config = ";".join(self._fsbl_config) if self._fsbl_config else None
+ auth_params = ";".join(self._auth_params) if self._auth_params else None
+
+ spl_elf_fname = tools.get_output_filename('u-boot-spl-pubkey.dtb.elf')
+
+ # We need to convert to node content (see above) into an ELF
+ # file in order to be processed by bootgen.
+ self._ToElf(bytearray(data), spl_elf_fname)
+
+ # Call Bootgen in order to sign the SPL
+ if self.bootgen.sign('zynqmp', spl_elf_fname, pmufw_elf_fname,
+ psk_fname, ssk_fname, fsbl_config,
+ auth_params, self._keysrc_enc, bootbin_fname) is None:
+ # Bintool is missing; just use empty data as the output
+ self.record_missing_bintool(self.bootgen)
+ data = tools.get_bytes(0, 1024)
+ else:
+ data = tools.read_file(bootbin_fname)
+
+ self.SetContents(data)
+
+ return data
+
+ # pylint: disable=C0116
+ def AddBintools(self, btools):
+ super().AddBintools(btools)
+ self.bootgen = self.AddBintool(btools, 'bootgen')
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 1cfa349..8e41964 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -48,6 +48,7 @@
BLOB_DATA = b'89'
ME_DATA = b'0abcd'
VGA_DATA = b'vga'
+EFI_CAPSULE_DATA = b'efi'
U_BOOT_DTB_DATA = b'udtb'
U_BOOT_SPL_DTB_DATA = b'spldtb'
U_BOOT_TPL_DTB_DATA = b'tpldtb'
@@ -119,6 +120,11 @@
TEE_ADDR = 0x5678
+# Firmware Management Protocol(FMP) GUID
+FW_MGMT_GUID = 'edd5cb6d2de8444cbda17194199ad92a'
+# Image GUID specified in the DTS
+CAPSULE_IMAGE_GUID = '52cfd7092007104791d108469b7fe9c8'
+
class TestFunctional(unittest.TestCase):
"""Functional tests for binman
@@ -215,6 +221,7 @@
TestFunctional._MakeInputFile('scp.bin', SCP_DATA)
TestFunctional._MakeInputFile('rockchip-tpl.bin', ROCKCHIP_TPL_DATA)
TestFunctional._MakeInputFile('ti_unsecure.bin', TI_UNSECURE_DATA)
+ TestFunctional._MakeInputFile('capsule_input.bin', EFI_CAPSULE_DATA)
# Add a few .dtb files for testing
TestFunctional._MakeInputFile('%s/test-fdt1.dtb' % TEST_FDT_SUBDIR,
@@ -3806,6 +3813,7 @@
allow_missing=True)
self.assertEqual(103, ret)
err = stderr.getvalue()
+ self.assertIn('(missing-file)', err)
self.assertRegex(err, "Image 'image'.*missing.*: blob-ext")
self.assertIn('Some images are invalid', err)
@@ -3816,6 +3824,7 @@
allow_missing=True, ignore_missing=True)
self.assertEqual(0, ret)
err = stderr.getvalue()
+ self.assertIn('(missing-file)', err)
self.assertRegex(err, "Image 'image'.*missing.*: blob-ext")
self.assertIn('Some images are invalid', err)
@@ -6358,6 +6367,13 @@
fdt_util.fdt32_to_cpu(node.props['entry'].value))
self.assertEqual(U_BOOT_DATA, node.props['data'].bytes)
+ with test_util.capture_sys_output() as (stdout, stderr):
+ self.checkFitTee('264_tee_os_opt_fit.dts', '')
+ err = stderr.getvalue()
+ self.assertRegex(
+ err,
+ "Image '.*' is missing optional external blobs but is still functional: tee-os")
+
def testFitTeeOsOptionalFitBad(self):
"""Test an image with a FIT with an optional OP-TEE binary"""
with self.assertRaises(ValueError) as exc:
@@ -6390,7 +6406,7 @@
err = stderr.getvalue()
self.assertRegex(
err,
- "Image '.*' is missing external blobs but is still functional: missing")
+ "Image '.*' is missing optional external blobs but is still functional: missing")
def testSectionInner(self):
"""Test an inner section with a size"""
@@ -6853,6 +6869,22 @@
second = U_BOOT_DATA + b'#' + VGA_DATA + U_BOOT_DTB_DATA
self.assertEqual(U_BOOT_IMG_DATA + first + second, data)
+ dtb_fname1 = tools.get_output_filename('u-boot.dtb.tmpl1')
+ self.assertTrue(os.path.exists(dtb_fname1))
+ dtb = fdt.Fdt.FromData(tools.read_file(dtb_fname1))
+ dtb.Scan()
+ node1 = dtb.GetNode('/binman/template')
+ self.assertTrue(node1)
+ vga = dtb.GetNode('/binman/first/intel-vga')
+ self.assertTrue(vga)
+
+ dtb_fname2 = tools.get_output_filename('u-boot.dtb.tmpl2')
+ self.assertTrue(os.path.exists(dtb_fname2))
+ dtb2 = fdt.Fdt.FromData(tools.read_file(dtb_fname2))
+ dtb2.Scan()
+ node2 = dtb2.GetNode('/binman/template')
+ self.assertFalse(node2)
+
def testTemplateBlobMulti(self):
"""Test using a template with 'multiple-images' enabled"""
TestFunctional._MakeInputFile('my-blob.bin', b'blob')
@@ -6944,6 +6976,33 @@
# Move to next
spl_data = content[:0x18]
+ def testTemplatePhandle(self):
+ """Test using a template in a node containing a phandle"""
+ entry_args = {
+ 'atf-bl31-path': 'bl31.elf',
+ }
+ data = self._DoReadFileDtb('309_template_phandle.dts',
+ entry_args=entry_args)
+ fname = tools.get_output_filename('image.bin')
+ out = tools.run('dumpimage', '-l', fname)
+
+ # We should see the FIT description and one for each of the two images
+ lines = out.splitlines()
+ descs = [line.split()[-1] for line in lines if 'escription' in line]
+ self.assertEqual(['test-desc', 'atf', 'fdt'], descs)
+
+ def testTemplatePhandleDup(self):
+ """Test using a template in a node containing a phandle"""
+ entry_args = {
+ 'atf-bl31-path': 'bl31.elf',
+ }
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFileDtb('310_template_phandle_dup.dts',
+ entry_args=entry_args)
+ self.assertIn(
+ 'Duplicate phandle 1 in nodes /binman/image/fit/images/atf/atf-bl31 and /binman/image-2/fit/images/atf/atf-bl31',
+ str(e.exception))
+
def testTIBoardConfig(self):
"""Test that a schema validated board config file can be generated"""
data = self._DoReadFile('293_ti_board_cfg.dts')
@@ -7087,5 +7146,193 @@
self.assertEqual(fdt_util.GetString(key_node, "key-name-hint"),
"key")
+ def testXilinxBootgenSigning(self):
+ """Test xilinx-bootgen etype"""
+ bootgen = bintool.Bintool.create('bootgen')
+ self._CheckBintool(bootgen)
+ data = tools.read_file(self.TestFile("key.key"))
+ self._MakeInputFile("psk.pem", data)
+ self._MakeInputFile("ssk.pem", data)
+ self._SetupPmuFwlElf()
+ self._SetupSplElf()
+ self._DoReadFileRealDtb('307_xilinx_bootgen_sign.dts')
+ image_fname = tools.get_output_filename('image.bin')
+
+ # Read partition header table and check if authentication is enabled
+ bootgen_out = bootgen.run_cmd("-arch", "zynqmp",
+ "-read", image_fname, "pht").splitlines()
+ attributes = {"authentication": None,
+ "core": None,
+ "encryption": None}
+
+ for l in bootgen_out:
+ for a in attributes.keys():
+ if a in l:
+ m = re.match(fr".*{a} \[([^]]+)\]", l)
+ attributes[a] = m.group(1)
+
+ self.assertTrue(attributes['authentication'] == "rsa")
+ self.assertTrue(attributes['core'] == "a53-0")
+ self.assertTrue(attributes['encryption'] == "no")
+
+ def testXilinxBootgenSigningEncryption(self):
+ """Test xilinx-bootgen etype"""
+ bootgen = bintool.Bintool.create('bootgen')
+ self._CheckBintool(bootgen)
+ data = tools.read_file(self.TestFile("key.key"))
+ self._MakeInputFile("psk.pem", data)
+ self._MakeInputFile("ssk.pem", data)
+ self._SetupPmuFwlElf()
+ self._SetupSplElf()
+ self._DoReadFileRealDtb('308_xilinx_bootgen_sign_enc.dts')
+ image_fname = tools.get_output_filename('image.bin')
+
+ # Read boot header in order to verify encryption source and
+ # encryption parameter
+ bootgen_out = bootgen.run_cmd("-arch", "zynqmp",
+ "-read", image_fname, "bh").splitlines()
+ attributes = {"auth_only":
+ {"re": r".*auth_only \[([^]]+)\]", "value": None},
+ "encryption_keystore":
+ {"re": r" *encryption_keystore \(0x28\) : (.*)",
+ "value": None},
+ }
+
+ for l in bootgen_out:
+ for a in attributes.keys():
+ if a in l:
+ m = re.match(attributes[a]['re'], l)
+ attributes[a] = m.group(1)
+
+ # Check if fsbl-attribute is set correctly
+ self.assertTrue(attributes['auth_only'] == "true")
+ # Check if key is stored in efuse
+ self.assertTrue(attributes['encryption_keystore'] == "0xa5c3c5a3")
+
+ def testXilinxBootgenMissing(self):
+ """Test that binman still produces an image if bootgen is missing"""
+ data = tools.read_file(self.TestFile("key.key"))
+ self._MakeInputFile("psk.pem", data)
+ self._MakeInputFile("ssk.pem", data)
+ self._SetupPmuFwlElf()
+ self._SetupSplElf()
+ with test_util.capture_sys_output() as (_, stderr):
+ self._DoTestFile('307_xilinx_bootgen_sign.dts',
+ force_missing_bintools='bootgen')
+ err = stderr.getvalue()
+ self.assertRegex(err,
+ "Image 'image'.*missing bintools.*: bootgen")
+
+ def _CheckCapsule(self, data, signed_capsule=False, version_check=False,
+ capoemflags=False):
+ fmp_signature = "4d535331" # 'M', 'S', 'S', '1'
+ fmp_size = "10"
+ fmp_fw_version = "02"
+ oemflag = "0080"
+
+ payload_data = EFI_CAPSULE_DATA
+
+ # TODO - Currently, these offsets for capsule fields are hardcoded.
+ # There are plans to add support to the mkeficapsule tool to dump
+ # the capsule contents which can then be used for capsule
+ # verification.
+
+ # Firmware Management Protocol(FMP) GUID - offset(0 - 32)
+ self.assertEqual(FW_MGMT_GUID, data.hex()[:32])
+ # Image GUID - offset(96 - 128)
+ self.assertEqual(CAPSULE_IMAGE_GUID, data.hex()[96:128])
+
+ if capoemflags:
+ # OEM Flags - offset(40 - 44)
+ self.assertEqual(oemflag, data.hex()[40:44])
+ if signed_capsule and version_check:
+ # FMP header signature - offset(4770 - 4778)
+ self.assertEqual(fmp_signature, data.hex()[4770:4778])
+ # FMP header size - offset(4778 - 4780)
+ self.assertEqual(fmp_size, data.hex()[4778:4780])
+ # firmware version - offset(4786 - 4788)
+ self.assertEqual(fmp_fw_version, data.hex()[4786:4788])
+ # payload offset signed capsule(4802 - 4808)
+ self.assertEqual(payload_data.hex(), data.hex()[4802:4808])
+ elif signed_capsule:
+ # payload offset signed capsule(4770 - 4776)
+ self.assertEqual(payload_data.hex(), data.hex()[4770:4776])
+ elif version_check:
+ # FMP header signature - offset(184 - 192)
+ self.assertEqual(fmp_signature, data.hex()[184:192])
+ # FMP header size - offset(192 - 194)
+ self.assertEqual(fmp_size, data.hex()[192:194])
+ # firmware version - offset(200 - 202)
+ self.assertEqual(fmp_fw_version, data.hex()[200:202])
+ # payload offset for non-signed capsule with version header(216 - 222)
+ self.assertEqual(payload_data.hex(), data.hex()[216:222])
+ else:
+ # payload offset for non-signed capsule with no version header(184 - 190)
+ self.assertEqual(payload_data.hex(), data.hex()[184:190])
+
+ def testCapsuleGen(self):
+ """Test generation of EFI capsule"""
+ data = self._DoReadFile('311_capsule.dts')
+
+ self._CheckCapsule(data)
+
+ def testSignedCapsuleGen(self):
+ """Test generation of EFI capsule"""
+ data = tools.read_file(self.TestFile("key.key"))
+ self._MakeInputFile("key.key", data)
+ data = tools.read_file(self.TestFile("key.pem"))
+ self._MakeInputFile("key.crt", data)
+
+ data = self._DoReadFile('312_capsule_signed.dts')
+
+ self._CheckCapsule(data, signed_capsule=True)
+
+ def testCapsuleGenVersionSupport(self):
+ """Test generation of EFI capsule with version support"""
+ data = self._DoReadFile('313_capsule_version.dts')
+
+ self._CheckCapsule(data, version_check=True)
+
+ def testCapsuleGenSignedVer(self):
+ """Test generation of signed EFI capsule with version information"""
+ data = tools.read_file(self.TestFile("key.key"))
+ self._MakeInputFile("key.key", data)
+ data = tools.read_file(self.TestFile("key.pem"))
+ self._MakeInputFile("key.crt", data)
+
+ data = self._DoReadFile('314_capsule_signed_ver.dts')
+
+ self._CheckCapsule(data, signed_capsule=True, version_check=True)
+
+ def testCapsuleGenCapOemFlags(self):
+ """Test generation of EFI capsule with OEM Flags set"""
+ data = self._DoReadFile('315_capsule_oemflags.dts')
+
+ self._CheckCapsule(data, capoemflags=True)
+
+ def testCapsuleGenKeyMissing(self):
+ """Test that binman errors out on missing key"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('316_capsule_missing_key.dts')
+
+ self.assertIn("Both private key and public key certificate need to be provided",
+ str(e.exception))
+
+ def testCapsuleGenIndexMissing(self):
+ """Test that binman errors out on missing image index"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('317_capsule_missing_index.dts')
+
+ self.assertIn("entry is missing properties: image-index",
+ str(e.exception))
+
+ def testCapsuleGenGuidMissing(self):
+ """Test that binman errors out on missing image GUID"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('318_capsule_missing_guid.dts')
+
+ self.assertIn("entry is missing properties: image-guid",
+ str(e.exception))
+
if __name__ == "__main__":
unittest.main()
diff --git a/tools/binman/missing-blob-help b/tools/binman/missing-blob-help
index f013367..ab0023e 100644
--- a/tools/binman/missing-blob-help
+++ b/tools/binman/missing-blob-help
@@ -43,7 +43,7 @@
tee-os:
See the documentation for your board. You may need to build Open Portable
-Trusted Execution Environment (OP-TEE) with TEE=/path/to/tee.bin
+Trusted Execution Environment (OP-TEE) and build with TEE=/path/to/tee.bin
opensbi:
See the documentation for your board. The OpenSBI git repo is at
diff --git a/tools/binman/test/264_tee_os_opt_fit.dts b/tools/binman/test/264_tee_os_opt_fit.dts
index ae44b43..e9634d3 100644
--- a/tools/binman/test/264_tee_os_opt_fit.dts
+++ b/tools/binman/test/264_tee_os_opt_fit.dts
@@ -25,6 +25,7 @@
fit,data;
tee-os {
+ optional;
};
};
};
diff --git a/tools/binman/test/307_xilinx_bootgen_sign.dts b/tools/binman/test/307_xilinx_bootgen_sign.dts
new file mode 100644
index 0000000..02acf86
--- /dev/null
+++ b/tools/binman/test/307_xilinx_bootgen_sign.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ xilinx-bootgen {
+ auth-params = "ppk_select=0", "spk_id=0x00000000";
+ pmufw-filename = "pmu-firmware.elf";
+ psk-key-name-hint = "psk";
+ ssk-key-name-hint = "ssk";
+
+ u-boot-spl-nodtb {
+ };
+ u-boot-spl-dtb {
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/308_xilinx_bootgen_sign_enc.dts b/tools/binman/test/308_xilinx_bootgen_sign_enc.dts
new file mode 100644
index 0000000..5d7ce4c
--- /dev/null
+++ b/tools/binman/test/308_xilinx_bootgen_sign_enc.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ xilinx-bootgen {
+ auth-params = "ppk_select=0", "spk_id=0x00000000";
+ fsbl-config = "auth_only";
+ keysrc-enc = "efuse_red_key";
+ pmufw-filename = "pmu-firmware.elf";
+ psk-key-name-hint = "psk";
+ ssk-key-name-hint = "ssk";
+
+ u-boot-spl-nodtb {
+ };
+ u-boot-spl-dtb {
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/309_template_phandle.dts b/tools/binman/test/309_template_phandle.dts
new file mode 100644
index 0000000..c4ec1dd
--- /dev/null
+++ b/tools/binman/test/309_template_phandle.dts
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ multiple-images;
+
+ ti_spl_template: template-1 {
+ fit {
+ description = "test-desc";
+ #address-cells = <1>;
+ images {
+ atf {
+ description = "atf";
+ ti-secure {
+ type = "collection";
+ content = <&atf>;
+ keyfile = "key.pem";
+ };
+ atf: atf-bl31 {
+ description = "atf";
+ };
+ };
+ };
+ };
+ };
+
+ image {
+ insert-template = <&ti_spl_template>;
+ fit {
+ images {
+ fdt-0 {
+ description = "fdt";
+ ti-secure {
+ type = "collection";
+ content = <&foo_dtb>;
+ keyfile = "key.pem";
+ };
+ foo_dtb: blob-ext {
+ filename = "vga.bin";
+ };
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/310_template_phandle_dup.dts b/tools/binman/test/310_template_phandle_dup.dts
new file mode 100644
index 0000000..dc86f06
--- /dev/null
+++ b/tools/binman/test/310_template_phandle_dup.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ multiple-images;
+
+ ti_spl_template: template-1 {
+ fit {
+ description = "test-desc";
+ #address-cells = <1>;
+ images {
+ atf {
+ description = "atf";
+ ti-secure {
+ type = "collection";
+ content = <&atf>;
+ keyfile = "key.pem";
+ };
+ atf: atf-bl31 {
+ description = "atf";
+ };
+ };
+ };
+ };
+ };
+
+ image {
+ insert-template = <&ti_spl_template>;
+ fit {
+ images {
+ fdt-0 {
+ description = "fdt";
+ ti-secure {
+ type = "collection";
+ content = <&foo_dtb>;
+ keyfile = "key.pem";
+ };
+ foo_dtb: blob-ext {
+ filename = "vga.bin";
+ };
+ };
+ };
+ };
+ };
+
+ image-2 {
+ insert-template = <&ti_spl_template>;
+ fit {
+ images {
+ fdt-0 {
+ description = "fdt";
+ blob-ext {
+ filename = "vga.bin";
+ };
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/311_capsule.dts b/tools/binman/test/311_capsule.dts
new file mode 100644
index 0000000..8eb4250
--- /dev/null
+++ b/tools/binman/test/311_capsule.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ efi-capsule {
+ image-index = <0x1>;
+ /* Image GUID for testing capsule update */
+ image-guid = "binman-test";
+ hardware-instance = <0x0>;
+
+ blob {
+ filename = "capsule_input.bin";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/312_capsule_signed.dts b/tools/binman/test/312_capsule_signed.dts
new file mode 100644
index 0000000..d1c76e2
--- /dev/null
+++ b/tools/binman/test/312_capsule_signed.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ efi-capsule {
+ image-index = <0x1>;
+ /* Image GUID for testing capsule update */
+ image-guid = "binman-test";
+ hardware-instance = <0x0>;
+ private-key = "key.key";
+ public-key-cert = "key.crt";
+
+ blob {
+ filename = "capsule_input.bin";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/313_capsule_version.dts b/tools/binman/test/313_capsule_version.dts
new file mode 100644
index 0000000..bafef36
--- /dev/null
+++ b/tools/binman/test/313_capsule_version.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x2>;
+ /* Image GUID for testing capsule update */
+ image-guid = "binman-test";
+ hardware-instance = <0x0>;
+
+ blob {
+ filename = "capsule_input.bin";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/314_capsule_signed_ver.dts b/tools/binman/test/314_capsule_signed_ver.dts
new file mode 100644
index 0000000..85c784b
--- /dev/null
+++ b/tools/binman/test/314_capsule_signed_ver.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x2>;
+ /* Image GUID for testing capsule update */
+ image-guid = "binman-test";
+ hardware-instance = <0x0>;
+ private-key = "key.key";
+ public-key-cert = "key.crt";
+
+ blob {
+ filename = "capsule_input.bin";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/315_capsule_oemflags.dts b/tools/binman/test/315_capsule_oemflags.dts
new file mode 100644
index 0000000..f736e87
--- /dev/null
+++ b/tools/binman/test/315_capsule_oemflags.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ efi-capsule {
+ image-index = <0x1>;
+ /* Image GUID for testing capsule update */
+ image-guid = "binman-test";
+ hardware-instance = <0x0>;
+ oem-flags = <0x8000>;
+
+ blob {
+ filename = "capsule_input.bin";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/316_capsule_missing_key.dts b/tools/binman/test/316_capsule_missing_key.dts
new file mode 100644
index 0000000..2080b50
--- /dev/null
+++ b/tools/binman/test/316_capsule_missing_key.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ efi-capsule {
+ image-index = <0x1>;
+ /* Image GUID for testing capsule update */
+ image-guid = "binman-test";
+ hardware-instance = <0x0>;
+ private-key = "tools/binman/test/key.key";
+
+ blob {
+ filename = "capsule_input.bin";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/317_capsule_missing_index.dts b/tools/binman/test/317_capsule_missing_index.dts
new file mode 100644
index 0000000..aadb61f
--- /dev/null
+++ b/tools/binman/test/317_capsule_missing_index.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ efi-capsule {
+ /* Image GUID for testing capsule update */
+ image-guid = "binman-test";
+ hardware-instance = <0x0>;
+
+ blob {
+ filename = "capsule_input.bin";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/318_capsule_missing_guid.dts b/tools/binman/test/318_capsule_missing_guid.dts
new file mode 100644
index 0000000..d76afba
--- /dev/null
+++ b/tools/binman/test/318_capsule_missing_guid.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ efi-capsule {
+ image-index = <0x1>;
+ hardware-instance = <0x0>;
+
+ blob {
+ filename = "capsule_input.bin";
+ };
+ };
+ };
+};
diff --git a/tools/buildman/boards.py b/tools/buildman/boards.py
index 83adbf1..eef3f19 100644
--- a/tools/buildman/boards.py
+++ b/tools/buildman/boards.py
@@ -377,16 +377,9 @@
Args:
linenum (int): Current line number
"""
- added = False
if targets:
for target in targets:
self.database[target] = (status, maintainers)
- added = True
- if not added and (status != '-' and maintainers):
- leaf = fname[len(srcdir) + 1:]
- if leaf != 'MAINTAINERS':
- self.warnings.append(
- f'WARNING: orphaned defconfig in {leaf} ending at line {linenum + 1}')
targets = []
maintainers = []
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index 5c57200..f2ffb7f 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -610,6 +610,9 @@
toolchains = get_toolchains(toolchains, col, args.override_toolchain,
args.fetch_arch, args.list_tool_chains,
args.verbose)
+ if isinstance(toolchains, int):
+ return toolchains
+
output_dir = setup_output_dir(
args.output_dir, args.work_in_output, args.branch,
args.no_subdirs, col, clean_dir)
diff --git a/tools/buildman/func_test.py b/tools/buildman/func_test.py
index 3115700..55dd494 100644
--- a/tools/buildman/func_test.py
+++ b/tools/buildman/func_test.py
@@ -926,10 +926,7 @@
tools.write_file(main, data, binary=False)
params_list, warnings = self._boards.build_board_list(config_dir, src)
self.assertEquals(2, len(params_list))
- self.assertEquals(
- ["WARNING: no maintainers for 'board0'",
- 'WARNING: orphaned defconfig in boards/board0/MAINTAINERS ending at line 4',
- ], warnings)
+ self.assertEquals(["WARNING: no maintainers for 'board0'"], warnings)
# Mark a board as orphaned - this should give a warning
lines = ['S: Orphaned' if line.startswith('S') else line
@@ -969,9 +966,7 @@
tools.write_file(main, both_data + extra, binary=False)
params_list, warnings = self._boards.build_board_list(config_dir, src)
self.assertEquals(2, len(params_list))
- self.assertEquals(
- ['WARNING: orphaned defconfig in boards/board0/MAINTAINERS ending at line 16'],
- warnings)
+ self.assertFalse(warnings)
# Add another TARGET to the Kconfig
tools.write_file(main, both_data, binary=False)
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index b050011..79c7c11 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -499,7 +499,7 @@
if arch == 'aarch64':
arch = 'arm64'
base = 'https://www.kernel.org/pub/tools/crosstool/files/bin'
- versions = ['13.1.0', '12.2.0']
+ versions = ['13.2.0', '12.2.0']
links = []
for version in versions:
url = '%s/%s/%s/' % (base, arch, version)
diff --git a/tools/default_image.c b/tools/default_image.c
index 0e49ab3..04bc85b 100644
--- a/tools/default_image.c
+++ b/tools/default_image.c
@@ -15,7 +15,6 @@
#include "imagetool.h"
#include "mkimage.h"
-#include <u-boot/crc.h>
#include <image.h>
#include <tee/optee.h>
diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile
index 3d2b64a..279b3a3 100644
--- a/tools/docker/Dockerfile
+++ b/tools/docker/Dockerfile
@@ -2,7 +2,7 @@
# This Dockerfile is used to build an image containing basic stuff to be used
# to build U-Boot and run our test suites.
-FROM ubuntu:jammy-20230624
+FROM ubuntu:jammy-20230804
MAINTAINER Tom Rini <trini@konsulko.com>
LABEL Description=" This image is for building U-Boot inside a container"
@@ -14,19 +14,19 @@
RUN wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add -
RUN echo deb http://apt.llvm.org/jammy/ llvm-toolchain-jammy-16 main | tee /etc/apt/sources.list.d/llvm.list
-# Manually install the kernel.org "Crosstool" based toolchains for gcc-13.1.0
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-arc-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-arm-linux-gnueabi.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-i386-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-m68k-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-mips-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-microblaze-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-nios2-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-powerpc-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-riscv64-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-riscv32-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.1.0/x86_64-gcc-13.1.0-nolibc-sh2-linux.tar.xz | tar -C /opt -xJ
+# Manually install the kernel.org "Crosstool" based toolchains for gcc-13.2.0
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-arc-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-arm-linux-gnueabi.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-i386-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-m68k-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-mips-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-microblaze-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-nios2-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-powerpc-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-riscv64-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-riscv32-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-sh2-linux.tar.xz | tar -C /opt -xJ
# Manually install other toolchains
RUN wget -O - https://github.com/foss-xtensa/toolchain/releases/download/2020.07/x86_64-2020.07-xtensa-dc233c-elf.tar.gz | tar -C /opt -xz
@@ -39,6 +39,7 @@
binutils-dev \
bison \
build-essential \
+ cgpt \
clang-16 \
coreutils \
cpio \
@@ -115,6 +116,8 @@
util-linux \
uuid-dev \
virtualenv \
+ vboot-kernel-utils \
+ vboot-utils \
xxd \
zip \
&& rm -rf /var/lib/apt/lists/*
@@ -134,11 +137,11 @@
mkdir -p /opt/grub && \
./configure --target=aarch64 --with-platform=efi \
CC=gcc \
- TARGET_CC=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc \
- TARGET_OBJCOPY=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-objcopy \
- TARGET_STRIP=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-strip \
- TARGET_NM=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-nm \
- TARGET_RANLIB=/opt/gcc-13.1.0-nolibc/aarch64-linux/bin/aarch64-linux-ranlib && \
+ TARGET_CC=/opt/gcc-13.2.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc \
+ TARGET_OBJCOPY=/opt/gcc-13.2.0-nolibc/aarch64-linux/bin/aarch64-linux-objcopy \
+ TARGET_STRIP=/opt/gcc-13.2.0-nolibc/aarch64-linux/bin/aarch64-linux-strip \
+ TARGET_NM=/opt/gcc-13.2.0-nolibc/aarch64-linux/bin/aarch64-linux-nm \
+ TARGET_RANLIB=/opt/gcc-13.2.0-nolibc/aarch64-linux/bin/aarch64-linux-ranlib && \
make && \
./grub-mkimage -O arm64-efi -o /opt/grub/grubaa64.efi --prefix= -d \
grub-core cat chain configfile echo efinet ext2 fat halt help linux \
@@ -148,11 +151,11 @@
make clean && \
./configure --target=arm --with-platform=efi \
CC=gcc \
- TARGET_CC=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc \
- TARGET_OBJCOPY=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-objcopy \
- TARGET_STRIP=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-strip \
- TARGET_NM=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-nm \
- TARGET_RANLIB=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ranlib && \
+ TARGET_CC=/opt/gcc-13.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc \
+ TARGET_OBJCOPY=/opt/gcc-13.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-objcopy \
+ TARGET_STRIP=/opt/gcc-13.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-strip \
+ TARGET_NM=/opt/gcc-13.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-nm \
+ TARGET_RANLIB=/opt/gcc-13.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ranlib && \
make && \
./grub-mkimage -O arm-efi -o /opt/grub/grubarm.efi --prefix= -d \
grub-core cat chain configfile echo efinet ext2 fat halt help linux \
@@ -162,11 +165,11 @@
make clean && \
./configure --target=riscv64 --with-platform=efi \
CC=gcc \
- TARGET_CC=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-gcc \
- TARGET_OBJCOPY=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-objcopy \
- TARGET_STRIP=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-strip \
- TARGET_NM=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-nm \
- TARGET_RANLIB=/opt/gcc-13.1.0-nolibc/riscv64-linux/bin/riscv64-linux-ranlib && \
+ TARGET_CC=/opt/gcc-13.2.0-nolibc/riscv64-linux/bin/riscv64-linux-gcc \
+ TARGET_OBJCOPY=/opt/gcc-13.2.0-nolibc/riscv64-linux/bin/riscv64-linux-objcopy \
+ TARGET_STRIP=/opt/gcc-13.2.0-nolibc/riscv64-linux/bin/riscv64-linux-strip \
+ TARGET_NM=/opt/gcc-13.2.0-nolibc/riscv64-linux/bin/riscv64-linux-nm \
+ TARGET_RANLIB=/opt/gcc-13.2.0-nolibc/riscv64-linux/bin/riscv64-linux-ranlib && \
make && \
./grub-mkimage -O riscv64-efi -o /opt/grub/grubriscv64.efi --prefix= -d \
grub-core cat chain configfile echo efinet ext2 fat halt help linux \
@@ -277,7 +280,7 @@
# Create the buildman config file
RUN /bin/echo -e "[toolchain]\nroot = /usr" > ~/.buildman
-RUN /bin/echo -e "kernelorg = /opt/gcc-13.1.0-nolibc/*" >> ~/.buildman
+RUN /bin/echo -e "kernelorg = /opt/gcc-13.2.0-nolibc/*" >> ~/.buildman
RUN /bin/echo -e "\n[toolchain-prefix]\nxtensa = /opt/2020.07/xtensa-dc233c-elf/bin/xtensa-dc233c-elf-" >> ~/.buildman;
RUN /bin/echo -e "\n[toolchain-alias]\nsh = sh2" >> ~/.buildman
RUN /bin/echo -e "\nsandbox = x86_64" >> ~/.buildman
diff --git a/tools/dtoc/fdt.py b/tools/dtoc/fdt.py
index fd0f3e9..0b20d52 100644
--- a/tools/dtoc/fdt.py
+++ b/tools/dtoc/fdt.py
@@ -15,6 +15,9 @@
from u_boot_pylib import tools
from u_boot_pylib import tout
+# Temporary hack
+IGNORE_DUP_PHANDLES = False
+
# This deals with a device tree, presenting it as an assortment of Node and
# Prop objects, representing nodes and properties, respectively. This file
# contains the base classes and defines the high-level API. You can use
@@ -249,6 +252,7 @@
"""
if self.dirty:
node = self._node
+ tout.debug(f'sync {node.path}: {self.name}')
fdt_obj = node._fdt._fdt_obj
node_name = fdt_obj.get_name(node._offset)
if node_name and node_name != node.name:
@@ -272,6 +276,7 @@
the FDT is synced
"""
self._offset = None
+ self.dirty = True
class Node:
"""A device tree node
@@ -335,7 +340,13 @@
self.props = self._fdt.GetProps(self)
phandle = fdt_obj.get_phandle(self.Offset())
if phandle:
- self._fdt.phandle_to_node[phandle] = self
+ dup = self._fdt.phandle_to_node.get(phandle)
+ if dup:
+ if not IGNORE_DUP_PHANDLES:
+ raise ValueError(
+ f'Duplicate phandle {phandle} in nodes {dup.path} and {self.path}')
+ else:
+ self._fdt.phandle_to_node[phandle] = self
offset = fdt_obj.first_subnode(self.Offset(), QUIET_NOTFOUND)
while offset >= 0:
@@ -705,30 +716,38 @@
prop.Sync(auto_resize)
return added
- def merge_props(self, src):
+ def merge_props(self, src, copy_phandles):
"""Copy missing properties (except 'phandle') from another node
Args:
src (Node): Node containing properties to copy
+ copy_phandles (bool): True to copy phandle properties in nodes
Adds properties which are present in src but not in this node. Any
'phandle' property is not copied since this might result in two nodes
with the same phandle, thus making phandle references ambiguous.
"""
+ tout.debug(f'copy to {self.path}: {src.path}')
for name, src_prop in src.props.items():
- if name != 'phandle' and name not in self.props:
- self.props[name] = Prop(self, None, name, src_prop.bytes)
+ done = False
+ if name not in self.props:
+ if copy_phandles or name != 'phandle':
+ self.props[name] = Prop(self, None, name, src_prop.bytes)
+ done = True
+ tout.debug(f" {name}{'' if done else ' - ignored'}")
- def copy_node(self, src):
+ def copy_node(self, src, copy_phandles=False):
"""Copy a node and all its subnodes into this node
Args:
src (Node): Node to copy
+ copy_phandles (bool): True to copy phandle properties in nodes
Returns:
Node: Resulting destination node
- This works recursively.
+ This works recursively, with copy_phandles being set to True for the
+ recursive calls
The new node is put before all other nodes. If the node already
exists, just its subnodes and properties are copied, placing them before
@@ -740,12 +759,12 @@
dst.move_to_first()
else:
dst = self.insert_subnode(src.name)
- dst.merge_props(src)
+ dst.merge_props(src, copy_phandles)
# Process in reverse order so that they appear correctly in the result,
# since copy_node() puts the node first in the list
for node in reversed(src.subnodes):
- dst.copy_node(node)
+ dst.copy_node(node, True)
return dst
def copy_subnodes_from_phandles(self, phandle_list):
@@ -768,7 +787,7 @@
dst = self.copy_node(node)
tout.debug(f'merge props from {parent.path} to {dst.path}')
- self.merge_props(parent)
+ self.merge_props(parent, False)
class Fdt:
@@ -829,6 +848,7 @@
TODO(sjg@chromium.org): Implement the 'root' parameter
"""
+ self.phandle_to_node = {}
self._cached_offsets = True
self._root = self.Node(self, None, 0, '/', '/')
self._root.Scan()
diff --git a/tools/dtoc/test/dtoc_test_copy.dts b/tools/dtoc/test/dtoc_test_copy.dts
index 36faa9b..8e50c75 100644
--- a/tools/dtoc/test/dtoc_test_copy.dts
+++ b/tools/dtoc/test/dtoc_test_copy.dts
@@ -37,11 +37,12 @@
new-prop;
};
- second1 {
+ second1: second1 {
new-prop;
};
second4 {
+ use_second1 = <&second1>;
};
};
};
@@ -65,12 +66,13 @@
};
second: second {
- second1 {
+ second_1_bad: second1 {
some-prop;
};
second2 {
some-prop;
+ use_second1_bad = <&second_1_bad>;
};
};
};
diff --git a/tools/dtoc/test_fdt.py b/tools/dtoc/test_fdt.py
index 3e54694..0b01518 100755
--- a/tools/dtoc/test_fdt.py
+++ b/tools/dtoc/test_fdt.py
@@ -32,6 +32,7 @@
import libfdt
from u_boot_pylib import test_util
from u_boot_pylib import tools
+from u_boot_pylib import tout
#pylint: disable=protected-access
@@ -308,7 +309,7 @@
def test_copy_node(self):
"""Test copy_node() function"""
- def do_copy_checks(dtb, dst, expect_none):
+ def do_copy_checks(dtb, dst, second1_ph_val, expect_none):
self.assertEqual(
['/dest/base', '/dest/first@0', '/dest/existing'],
[n.path for n in dst.subnodes])
@@ -339,8 +340,8 @@
over = dtb.GetNode('/dest/base/over')
self.assertTrue(over)
- # Make sure that the phandle for 'over' is not copied
- self.assertNotIn('phandle', over.props.keys())
+ # Make sure that the phandle for 'over' is copied
+ self.assertIn('phandle', over.props.keys())
second = dtb.GetNode('/dest/base/second')
self.assertTrue(second)
@@ -348,7 +349,7 @@
[n.name for n in chk.subnodes])
self.assertEqual(chk, over.parent)
self.assertEqual(
- {'bootph-all', 'compatible', 'reg', 'low-power'},
+ {'bootph-all', 'compatible', 'reg', 'low-power', 'phandle'},
over.props.keys())
if expect_none:
@@ -365,20 +366,43 @@
['second1', 'second2', 'second3', 'second4'],
[n.name for n in second.subnodes])
+ # Check the 'second_1_bad' phandle is not copied over
+ second1 = second.FindNode('second1')
+ self.assertTrue(second1)
+ sph = second1.props.get('phandle')
+ self.assertTrue(sph)
+ self.assertEqual(second1_ph_val, sph.bytes)
+
+
dtb = fdt.FdtScan(find_dtb_file('dtoc_test_copy.dts'))
tmpl = dtb.GetNode('/base')
dst = dtb.GetNode('/dest')
+ second1_ph_val = (dtb.GetNode('/dest/base/second/second1').
+ props['phandle'].bytes)
dst.copy_node(tmpl)
- do_copy_checks(dtb, dst, expect_none=True)
+ do_copy_checks(dtb, dst, second1_ph_val, expect_none=True)
dtb.Sync(auto_resize=True)
- # Now check that the FDT looks correct
+ # Now check the resulting FDT. It should have duplicate phandles since
+ # 'over' has been copied to 'dest/base/over' but still exists in its old
+ # place
new_dtb = fdt.Fdt.FromData(dtb.GetContents())
+ with self.assertRaises(ValueError) as exc:
+ new_dtb.Scan()
+ self.assertIn(
+ 'Duplicate phandle 1 in nodes /dest/base/over and /base/over',
+ str(exc.exception))
+
+ # Remove the source nodes for the copy
+ new_dtb.GetNode('/base').Delete()
+
+ # Now it should scan OK
new_dtb.Scan()
+
dst = new_dtb.GetNode('/dest')
- do_copy_checks(new_dtb, dst, expect_none=False)
+ do_copy_checks(new_dtb, dst, second1_ph_val, expect_none=False)
def test_copy_subnodes_from_phandles(self):
"""Test copy_node() function"""
@@ -404,7 +428,7 @@
# Make sure that the phandle for 'over' is not copied
over = dst.FindNode('over')
- print('keys', over.props.keys())
+ tout.debug(f'keys: {over.props.keys()}')
self.assertNotIn('phandle', over.props.keys())
# Check the merged properties, first the base ones in '/dest'
diff --git a/tools/expo.py b/tools/expo.py
index c6eb87a..ea80c70 100755
--- a/tools/expo.py
+++ b/tools/expo.py
@@ -69,7 +69,10 @@
def run_expo(args):
"""Run the expo program"""
- ids = calc_ids(args.enum_fname)
+ fname = args.enum_fname or args.layout
+ ids = calc_ids(fname)
+ if not ids:
+ print(f"Warning: No enum ID values found in file '{fname}'")
indata = tools.read_file(args.layout)
@@ -88,10 +91,10 @@
with open('/tmp/asc', 'wb') as outf:
outf.write(data)
- proc = subprocess.run('dtc', input=data, capture_output=True, check=True)
+ proc = subprocess.run('dtc', input=data, capture_output=True)
edtb = proc.stdout
if proc.stderr:
- print(proc.stderr)
+ print(f"Devicetree compiler error:\n{proc.stderr.decode('utf-8')}")
return 1
tools.write_file(args.outfile, edtb)
return 0
@@ -109,11 +112,13 @@
args is a list of string arguments
"""
parser = argparse.ArgumentParser()
+ parser.add_argument('-D', '--debug', action='store_true',
+ help='Enable full debug traceback')
parser.add_argument('-e', '--enum-fname', type=str,
- help='C file containing enum declaration for expo items')
- parser.add_argument('-l', '--layout', type=str,
- help='Devicetree file source .dts for expo layout')
- parser.add_argument('-o', '--outfile', type=str,
+ help='.dts or C file containing enum declaration for expo items')
+ parser.add_argument('-l', '--layout', type=str, required=True,
+ help='Devicetree file source .dts for expo layout (and perhaps enums)')
+ parser.add_argument('-o', '--outfile', type=str, required=True,
help='Filename to write expo layout dtb')
return parser.parse_args(argv)
@@ -122,6 +127,9 @@
"""Start the expo program"""
args = parse_args(sys.argv[1:])
+ if not args.debug:
+ sys.tracebacklimit = 0
+
ret_code = run_expo(args)
sys.exit(ret_code)
diff --git a/tools/logos/st.bmp b/tools/logos/st.bmp
new file mode 100644
index 0000000..f59d3c5
--- /dev/null
+++ b/tools/logos/st.bmp
Binary files differ
diff --git a/tools/mtk_image.c b/tools/mtk_image.c
index 30f54c8..1b1aed5 100644
--- a/tools/mtk_image.c
+++ b/tools/mtk_image.c
@@ -542,11 +542,13 @@
hdr->type = cpu_to_le32(type);
}
-static void put_ghf_common_header(struct gfh_common_header *gfh, int size,
- int type, int ver)
+static void put_ghf_common_header(struct gfh_common_header *gfh, uint16_t size,
+ uint16_t type, uint8_t ver)
{
- memcpy(gfh->magic, GFH_HEADER_MAGIC, sizeof(gfh->magic));
- gfh->version = ver;
+ uint32_t magic_version = GFH_HEADER_MAGIC |
+ (uint32_t)ver << GFH_HEADER_VERSION_SHIFT;
+
+ gfh->magic_version = cpu_to_le32(magic_version);
gfh->size = cpu_to_le16(size);
gfh->type = cpu_to_le16(type);
}
diff --git a/tools/mtk_image.h b/tools/mtk_image.h
index fad9372..54a838d 100644
--- a/tools/mtk_image.h
+++ b/tools/mtk_image.h
@@ -63,13 +63,13 @@
/* BootROM header definitions */
struct gfh_common_header {
- uint8_t magic[3];
- uint8_t version;
+ uint32_t magic_version;
uint16_t size;
uint16_t type;
};
-#define GFH_HEADER_MAGIC "MMM"
+#define GFH_HEADER_MAGIC 0x4D4D4D
+#define GFH_HEADER_VERSION_SHIFT 24
#define GFH_TYPE_FILE_INFO 0
#define GFH_TYPE_BL_INFO 1
