diff --git a/.gitignore b/.gitignore
index a163728..e40eb7b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -15,6 +15,7 @@
 *.swp
 *.patch
 *.bin
+*.cfgtmp
 
 # Build tree
 /build-*
diff --git a/MAINTAINERS b/MAINTAINERS
index d3ed390..45e2dd4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -819,6 +819,9 @@
 
 	omap730p2	ARM926EJS
 
+Lars Poeschel <poeschel@lemonage.de>
+	pcm051  	ARM ARMV7 (AM33xx Soc)
+
 Mathieu Poirier <mathieu.poirier@linaro.org>
 
 	snowball	ARM ARMV7 (u8500 SoC)
@@ -939,6 +942,7 @@
 	palmtc		xscale/pxa
 	vpac270		xscale/pxa
 	zipitz2		xscale/pxa
+	mx23_olinuxino	i.MX23
 	m28evk		i.MX28
 	sc_sps_1	i.MX28
 
@@ -950,6 +954,10 @@
 
 	ca9x4_ct_vxp	ARM ARMV7 (Quad Core)
 
+Otavio Salvador <otavio@ossystems.com.br>
+
+	mx23evk		i.MX23
+
 Prafulla Wadaskar <prafulla@marvell.com>
 
 	aspenite	ARM926EJS (ARMADA100 88AP168 SoC)
diff --git a/Makefile b/Makefile
index 51bd918..fc18dd4 100644
--- a/Makefile
+++ b/Makefile
@@ -230,10 +230,6 @@
 # U-Boot objects....order is important (i.e. start must be first)
 
 OBJS  = $(CPUDIR)/start.o
-ifeq ($(CPU),x86)
-RESET_OBJS-$(CONFIG_X86_NO_RESET_VECTOR) += $(CPUDIR)/start16.o
-RESET_OBJS-$(CONFIG_X86_NO_RESET_VECTOR) += $(CPUDIR)/resetvec.o
-endif
 ifeq ($(CPU),ppc4xx)
 OBJS += $(CPUDIR)/resetvec.o
 endif
@@ -241,7 +237,7 @@
 OBJS += $(CPUDIR)/resetvec.o
 endif
 
-OBJS := $(addprefix $(obj),$(OBJS) $(RESET_OBJS-))
+OBJS := $(addprefix $(obj),$(OBJS))
 
 HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n)
 
@@ -348,7 +344,7 @@
 ifeq ($(SOC),exynos)
 LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o
 endif
-ifeq ($(SOC),tegra20)
+ifneq ($(CONFIG_TEGRA),)
 LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
 LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
 LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
@@ -413,7 +409,7 @@
 ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
 
 # enable combined SPL/u-boot/dtb rules for tegra
-ifeq ($(SOC),tegra20)
+ifneq ($(CONFIG_TEGRA),)
 ifeq ($(CONFIG_OF_SEPARATE),y)
 ALL-y += $(obj)u-boot-dtb-tegra.bin
 else
@@ -467,9 +463,8 @@
 			sed -e 's/"[	 ]*$$/ for $(BOARD) board"/') \
 		-d $< $@
 
-$(obj)u-boot.imx:       $(obj)u-boot.bin
-		$(obj)tools/mkimage -n  $(CONFIG_IMX_CONFIG) -T imximage \
-		-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
+$(OBJTREE)/u-boot.imx : $(obj)u-boot.bin $(SUBDIR_TOOLS) depend
+		$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $@
 
 $(obj)u-boot.kwb:       $(obj)u-boot.bin
 		$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
@@ -512,6 +507,7 @@
 			$(obj)u-boot.ais
 
 # Specify the target for use in elftosb call
+ELFTOSB_TARGET-$(CONFIG_MX23) = imx23
 ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
 
 $(obj)u-boot.sb:       $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
@@ -534,7 +530,7 @@
 			conv=notrunc 2>/dev/null
 		cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@
 
-ifeq ($(SOC),tegra20)
+ifneq ($(CONFIG_TEGRA),)
 ifeq ($(CONFIG_OF_SEPARATE),y)
 nodtb=dtb
 dtbfile=$(obj)u-boot.dtb
@@ -847,7 +843,8 @@
 	@$(MAKE) -s -C doc/DocBook/ cleandocs
 	@find $(OBJTREE) -type f \
 		\( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \
-		-o -name '*.o'	-o -name '*.a' -o -name '*.exe'	\) -print \
+		-o -name '*.o'	-o -name '*.a' -o -name '*.exe' \
+		-o -name '*.cfgtmp' \) -print \
 		| xargs rm -f
 
 # Removes everything not needed for testing u-boot
diff --git a/README b/README
index 2352e38..d8cb394 100644
--- a/README
+++ b/README
@@ -3816,14 +3816,9 @@
 		be used if available. These functions may be faster under some
 		conditions but may increase the binary size.
 
-- CONFIG_X86_NO_RESET_VECTOR
-		If defined, the x86 reset vector code is excluded. You will need
-		to do this when U-Boot is running from Coreboot.
-
-- CONFIG_X86_NO_REAL_MODE
-		If defined, x86 real mode code is omitted. This assumes a
-		32-bit environment where such code is not needed. You will
-		need to do this when U-Boot is running from Coreboot.
+- CONFIG_X86_RESET_VECTOR
+		If defined, the x86 reset vector code is included. This is not
+		needed when U-Boot is running from Coreboot.
 
 
 Freescale QE/FMAN Firmware Support:
diff --git a/arch/arm/cpu/arm720t/tegra-common/Makefile b/arch/arm/cpu/arm720t/tegra-common/Makefile
index febd2e3..6cbc6ad 100644
--- a/arch/arm/cpu/arm720t/tegra-common/Makefile
+++ b/arch/arm/cpu/arm720t/tegra-common/Makefile
@@ -28,6 +28,7 @@
 LIB	= $(obj)libtegra-common.o
 
 COBJS-$(CONFIG_SPL_BUILD) += spl.o
+COBJS-y	+= cpu.o
 
 SRCS	:= $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
new file mode 100644
index 0000000..119342e
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -0,0 +1,333 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/scu.h>
+#include "cpu.h"
+
+int get_num_cpus(void)
+{
+	struct apb_misc_gp_ctlr *gp;
+	uint rev;
+
+	gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
+	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
+
+	switch (rev) {
+	case CHIPID_TEGRA20:
+		return 2;
+		break;
+	case CHIPID_TEGRA30:
+	case CHIPID_TEGRA114:
+	default:
+		return 4;
+		break;
+	}
+}
+
+/*
+ * Timing tables for each SOC for all four oscillator options.
+ */
+struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
+	/* T20: 1 GHz */
+	/*  n,  m, p, cpcon */
+	{{ 1000, 13, 0, 12},	/* OSC 13M */
+	 { 625,  12, 0, 8},	/* OSC 19.2M */
+	 { 1000, 12, 0, 12},	/* OSC 12M */
+	 { 1000, 26, 0, 12},	/* OSC 26M */
+	},
+
+	/* T25: 1.2 GHz */
+	{{ 923, 10, 0, 12},
+	 { 750, 12, 0, 8},
+	 { 600,  6, 0, 12},
+	 { 600, 13, 0, 12},
+	},
+
+	/* T30: 1.4 GHz */
+	{{ 862, 8, 0, 8},
+	 { 583, 8, 0, 4},
+	 { 700, 6, 0, 8},
+	 { 700, 13, 0, 8},
+	},
+
+	/* T114: 1.4 GHz */
+	{{ 862, 8, 0, 8},
+	 { 583, 8, 0, 4},
+	 { 696, 12, 0, 8},
+	 { 700, 13, 0, 8},
+	},
+};
+
+void adjust_pllp_out_freqs(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
+	u32 reg;
+
+	/* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
+	reg = readl(&pll->pll_out[0]);	/* OUTA, contains OUT2 / OUT1 */
+	reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
+		| (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
+	writel(reg, &pll->pll_out[0]);
+
+	reg = readl(&pll->pll_out[1]);   /* OUTB, contains OUT4 / OUT3 */
+	reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
+		| (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
+	writel(reg, &pll->pll_out[1]);
+}
+
+int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
+		u32 divp, u32 cpcon)
+{
+	u32 reg;
+
+	/* If PLLX is already enabled, just return */
+	if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
+		debug("pllx_set_rate: PLLX already enabled, returning\n");
+		return 0;
+	}
+
+	debug(" pllx_set_rate entry\n");
+
+	/* Set BYPASS, m, n and p to PLLX_BASE */
+	reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
+	reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
+	writel(reg, &pll->pll_base);
+
+	/* Set cpcon to PLLX_MISC */
+	reg = (cpcon << PLL_CPCON_SHIFT);
+
+	/* Set dccon to PLLX_MISC if freq > 600MHz */
+	if (divn > 600)
+		reg |= (1 << PLL_DCCON_SHIFT);
+	writel(reg, &pll->pll_misc);
+
+	/* Enable PLLX */
+	reg = readl(&pll->pll_base);
+	reg |= PLL_ENABLE_MASK;
+
+	/* Disable BYPASS */
+	reg &= ~PLL_BYPASS_MASK;
+	writel(reg, &pll->pll_base);
+
+	/* Set lock_enable to PLLX_MISC */
+	reg = readl(&pll->pll_misc);
+	reg |= PLL_LOCK_ENABLE_MASK;
+	writel(reg, &pll->pll_misc);
+
+	return 0;
+}
+
+void init_pllx(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
+	int chip_type;
+	enum clock_osc_freq osc;
+	struct clk_pll_table *sel;
+
+	debug("init_pllx entry\n");
+
+	/* get chip type */
+	chip_type = tegra_get_chip_type();
+	debug(" init_pllx: chip_type = %d\n", chip_type);
+
+	/* get osc freq */
+	osc = clock_get_osc_freq();
+	debug("  init_pllx: osc = %d\n", osc);
+
+	/* set pllx */
+	sel = &tegra_pll_x_table[chip_type][osc];
+	pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
+
+	/* adjust PLLP_out1-4 on T30/T114 */
+	if (chip_type == TEGRA_SOC_T30 || chip_type == TEGRA_SOC_T114) {
+		debug("  init_pllx: adjusting PLLP out freqs\n");
+		adjust_pllp_out_freqs();
+	}
+}
+
+void enable_cpu_clock(int enable)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 clk;
+
+	/*
+	 * NOTE:
+	 * Regardless of whether the request is to enable or disable the CPU
+	 * clock, every processor in the CPU complex except the master (CPU 0)
+	 * will have it's clock stopped because the AVP only talks to the
+	 * master.
+	 */
+
+	if (enable) {
+		/* Initialize PLLX */
+		init_pllx();
+
+		/* Wait until all clocks are stable */
+		udelay(PLL_STABILIZATION_DELAY);
+
+		writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+		writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
+	}
+
+	/*
+	 * Read the register containing the individual CPU clock enables and
+	 * always stop the clocks to CPUs > 0.
+	 */
+	clk = readl(&clkrst->crc_clk_cpu_cmplx);
+	clk |= 1 << CPU1_CLK_STP_SHIFT;
+	if (get_num_cpus() == 4)
+		clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
+
+	/* Stop/Unstop the CPU clock */
+	clk &= ~CPU0_CLK_STP_MASK;
+	clk |= !enable << CPU0_CLK_STP_SHIFT;
+	writel(clk, &clkrst->crc_clk_cpu_cmplx);
+
+	clock_enable(PERIPH_ID_CPU);
+}
+
+static int is_cpu_powered(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
+}
+
+static void remove_cpu_io_clamps(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	/* Remove the clamps on the CPU I/O signals */
+	reg = readl(&pmc->pmc_remove_clamping);
+	reg |= CPU_CLMP;
+	writel(reg, &pmc->pmc_remove_clamping);
+
+	/* Give I/O signals time to stabilize */
+	udelay(IO_STABILIZATION_DELAY);
+}
+
+void powerup_cpu(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+	int timeout = IO_STABILIZATION_DELAY;
+
+	if (!is_cpu_powered()) {
+		/* Toggle the CPU power state (OFF -> ON) */
+		reg = readl(&pmc->pmc_pwrgate_toggle);
+		reg &= PARTID_CP;
+		reg |= START_CP;
+		writel(reg, &pmc->pmc_pwrgate_toggle);
+
+		/* Wait for the power to come up */
+		while (!is_cpu_powered()) {
+			if (timeout-- == 0)
+				printf("CPU failed to power up!\n");
+			else
+				udelay(10);
+		}
+
+		/*
+		 * Remove the I/O clamps from CPU power partition.
+		 * Recommended only on a Warm boot, if the CPU partition gets
+		 * power gated. Shouldn't cause any harm when called after a
+		 * cold boot according to HW, probably just redundant.
+		 */
+		remove_cpu_io_clamps();
+	}
+}
+
+void reset_A9_cpu(int reset)
+{
+	/*
+	* NOTE:  Regardless of whether the request is to hold the CPU in reset
+	*        or take it out of reset, every processor in the CPU complex
+	*        except the master (CPU 0) will be held in reset because the
+	*        AVP only talks to the master. The AVP does not know that there
+	*        are multiple processors in the CPU complex.
+	*/
+	int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
+	int num_cpus = get_num_cpus();
+	int cpu;
+
+	debug("reset_a9_cpu entry\n");
+	/* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
+	for (cpu = 1; cpu < num_cpus; cpu++)
+		reset_cmplx_set_enable(cpu, mask, 1);
+	reset_cmplx_set_enable(0, mask, reset);
+
+	/* Enable/Disable master CPU reset */
+	reset_set_enable(PERIPH_ID_CPU, reset);
+}
+
+void clock_enable_coresight(int enable)
+{
+	u32 rst, src = 2;
+	int chip;
+
+	debug("clock_enable_coresight entry\n");
+	clock_set_enable(PERIPH_ID_CORESIGHT, enable);
+	reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
+
+	if (enable) {
+		/*
+		 * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by
+		 *  1.5, giving an effective frequency of 144MHz.
+		 * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
+		 *  (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
+		 *
+		 * Clock divider request for 204MHz would setup CSITE clock as
+		 * 144MHz for PLLP base 216MHz and 204MHz for PLLP base 408MHz
+		 */
+		chip = tegra_get_chip_type();
+		if (chip == TEGRA_SOC_T30 || chip == TEGRA_SOC_T114)
+			src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
+		else if (chip == TEGRA_SOC_T20 || chip == TEGRA_SOC_T25)
+			src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
+		else
+			printf("%s: Unknown chip type %X!\n", __func__, chip);
+		clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
+
+		/* Unlock the CPU CoreSight interfaces */
+		rst = CORESIGHT_UNLOCK;
+		writel(rst, CSITE_CPU_DBG0_LAR);
+		writel(rst, CSITE_CPU_DBG1_LAR);
+		if (get_num_cpus() == 4) {
+			writel(rst, CSITE_CPU_DBG2_LAR);
+			writel(rst, CSITE_CPU_DBG3_LAR);
+		}
+	}
+}
+
+void halt_avp(void)
+{
+	for (;;) {
+		writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
+			| HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
+			FLOW_CTLR_HALT_COP_EVENTS);
+	}
+}
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/cpu/arm720t/tegra-common/cpu.h
index 6804cd7..e8e05d7 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.h
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.h
@@ -26,7 +26,13 @@
 #define PLL_STABILIZATION_DELAY (300)
 #define IO_STABILIZATION_DELAY	(1000)
 
+#if defined(CONFIG_TEGRA20)
 #define NVBL_PLLP_KHZ	(216000)
+#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
+#define NVBL_PLLP_KHZ	(408000)
+#else
+#error "Unknown Tegra chip!"
+#endif
 
 #define PLLX_ENABLED		(1 << 30)
 #define CCLK_BURST_POLICY	0x20008888
@@ -44,50 +50,11 @@
 
 #define CORESIGHT_UNLOCK	0xC5ACCE55;
 
-/* AP20-Specific Base Addresses */
-
-/* AP20 Base physical address of SDRAM. */
-#define AP20_BASE_PA_SDRAM      0x00000000
-/* AP20 Base physical address of internal SRAM. */
-#define AP20_BASE_PA_SRAM       0x40000000
-/* AP20 Size of internal SRAM (256KB). */
-#define AP20_BASE_PA_SRAM_SIZE  0x00040000
-/* AP20 Base physical address of flash. */
-#define AP20_BASE_PA_NOR_FLASH  0xD0000000
-/* AP20 Base physical address of boot information table. */
-#define AP20_BASE_PA_BOOT_INFO  AP20_BASE_PA_SRAM
-
-/*
- * Super-temporary stacks for EXTREMELY early startup. The values chosen for
- * these addresses must be valid on ALL SOCs because this value is used before
- * we are able to differentiate between the SOC types.
- *
- * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
- *       stack is placed below the AVP stack. Once the CPU stack has been moved,
- *       the AVP is free to use the IRAM the CPU stack previously occupied if
- *       it should need to do so.
- *
- * NOTE: In multi-processor CPU complex configurations, each processor will have
- *       its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
- *       limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
- *       stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
- *       CPU.
- */
-
-/* Common AVP early boot stack limit */
-#define AVP_EARLY_BOOT_STACK_LIMIT	\
-	(AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
-/* Common AVP early boot stack size */
-#define AVP_EARLY_BOOT_STACK_SIZE	0x1000
-/* Common CPU early boot stack limit */
-#define CPU_EARLY_BOOT_STACK_LIMIT	\
-	(AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
-/* Common CPU early boot stack size */
-#define CPU_EARLY_BOOT_STACK_SIZE	0x1000
-
 #define EXCEP_VECTOR_CPU_RESET_VECTOR	(NV_PA_EVP_BASE + 0x100)
 #define CSITE_CPU_DBG0_LAR		(NV_PA_CSITE_BASE + 0x10FB0)
 #define CSITE_CPU_DBG1_LAR		(NV_PA_CSITE_BASE + 0x12FB0)
+#define CSITE_CPU_DBG2_LAR		(NV_PA_CSITE_BASE + 0x14FB0)
+#define CSITE_CPU_DBG3_LAR		(NV_PA_CSITE_BASE + 0x16FB0)
 
 #define FLOW_CTLR_HALT_COP_EVENTS	(NV_PA_FLOW_BASE + 4)
 #define FLOW_MODE_STOP			2
@@ -95,6 +62,23 @@
 #define HALT_COP_EVENT_IRQ_1		(1 << 11)
 #define HALT_COP_EVENT_FIQ_1		(1 << 9)
 
-void start_cpu(u32 reset_vector);
-int ap20_cpu_is_cortexa9(void);
+#define FLOW_MODE_NONE		0
+
+#define SIMPLE_PLLX     (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
+
+struct clk_pll_table {
+	u16	n;
+	u16	m;
+	u8	p;
+	u8	cpcon;
+};
+
+void clock_enable_coresight(int enable);
+void enable_cpu_clock(int enable);
 void halt_avp(void)  __attribute__ ((noreturn));
+void init_pllx(void);
+void powerup_cpu(void);
+void reset_A9_cpu(int reset);
+void start_cpu(u32 reset_vector);
+int tegra_get_chip_type(void);
+void adjust_pllp_out_freqs(void);
diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/cpu/arm720t/tegra-common/spl.c
index c280ab7..a9a1c39 100644
--- a/arch/arm/cpu/arm720t/tegra-common/spl.c
+++ b/arch/arm/cpu/arm720t/tegra-common/spl.c
@@ -23,7 +23,6 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
-#include "cpu.h"
 #include <spl.h>
 
 #include <asm/io.h>
@@ -32,7 +31,7 @@
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/board.h>
 #include <asm/arch/spl.h>
-
+#include "cpu.h"
 
 void spl_board_init(void)
 {
diff --git a/arch/arm/cpu/arm720t/tegra114/Makefile b/arch/arm/cpu/arm720t/tegra114/Makefile
new file mode 100644
index 0000000..6cf7fe9
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra114/Makefile
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+#COBJS-y	+= cpu.o t11x.o
+COBJS-y	+= cpu.o
+
+SRCS	:= $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm720t/tegra114/config.mk b/arch/arm/cpu/arm720t/tegra114/config.mk
new file mode 100644
index 0000000..7947b50
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra114/config.mk
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c
new file mode 100644
index 0000000..5962e15
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra114/cpu.c
@@ -0,0 +1,297 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include "../tegra-common/cpu.h"
+
+/* Tegra114-specific CPU init code */
+static void enable_cpu_power_rail(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	debug("enable_cpu_power_rail entry\n");
+
+	/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
+	pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
+	pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
+
+	/*
+	 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
+	 * set it for 25ms (102MHz * .025)
+	 */
+	reg = 0x26E8F0;
+	writel(reg, &pmc->pmc_cpupwrgood_timer);
+
+	/* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
+	clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
+	setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
+
+	/*
+	 * Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH
+	 * to 408 to satisfy the requirement of having at least 16 CPU clock
+	 * cycles before clamp removal.
+	 */
+
+	clrbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 0xFFF);
+	setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408);
+}
+
+static void enable_cpu_clocks(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	debug("enable_cpu_clocks entry\n");
+
+	/* Wait for PLL-X to lock */
+	do {
+		reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
+	} while ((reg & (1 << 27)) == 0);
+
+	/* Wait until all clocks are stable */
+	udelay(PLL_STABILIZATION_DELAY);
+
+	writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+	writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
+
+	/* Always enable the main CPU complex clocks */
+	clock_enable(PERIPH_ID_CPU);
+	clock_enable(PERIPH_ID_CPULP);
+	clock_enable(PERIPH_ID_CPUG);
+}
+
+static void remove_cpu_resets(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	debug("remove_cpu_resets entry\n");
+	/* Take the slow non-CPU partition out of reset */
+	reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
+	writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr);
+
+	/* Take the fast non-CPU partition out of reset */
+	reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
+	writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpug_cmplx_clr);
+
+	/* Clear the SW-controlled reset of the slow cluster */
+	reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
+	reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
+	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+
+	/* Clear the SW-controlled reset of the fast cluster */
+	reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
+	reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
+	reg |= (CLR_CPURESET1+CLR_DBGRESET1+CLR_CORERESET1+CLR_CXRESET1);
+	reg |= (CLR_CPURESET2+CLR_DBGRESET2+CLR_CORERESET2+CLR_CXRESET2);
+	reg |= (CLR_CPURESET3+CLR_DBGRESET3+CLR_CORERESET3+CLR_CXRESET3);
+	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+}
+
+/**
+ * The T114 requires some special clock initialization, including setting up
+ * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
+ */
+void t114_init_clocks(void)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+	u32 val;
+
+	debug("t114_init_clocks entry\n");
+
+	/* Set active CPU cluster to G */
+	clrbits_le32(&flow->cluster_control, 1);
+
+	/*
+	 * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
+	 * at 108 MHz. This is glitch free as only the source is changed, no
+	 * special precaution needed.
+	 */
+	val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
+		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
+		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
+		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
+		(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
+	writel(val, &clkrst->crc_sclk_brst_pol);
+
+	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
+
+	debug("Setting up PLLX\n");
+	init_pllx();
+
+	val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
+	writel(val, &clkrst->crc_clk_sys_rate);
+
+	/* Enable clocks to required peripherals. TBD - minimize this list */
+	debug("Enabling clocks\n");
+
+	clock_set_enable(PERIPH_ID_CACHE2, 1);
+	clock_set_enable(PERIPH_ID_GPIO, 1);
+	clock_set_enable(PERIPH_ID_TMR, 1);
+	clock_set_enable(PERIPH_ID_RTC, 1);
+	clock_set_enable(PERIPH_ID_CPU, 1);
+	clock_set_enable(PERIPH_ID_EMC, 1);
+	clock_set_enable(PERIPH_ID_I2C5, 1);
+	clock_set_enable(PERIPH_ID_FUSE, 1);
+	clock_set_enable(PERIPH_ID_PMC, 1);
+	clock_set_enable(PERIPH_ID_APBDMA, 1);
+	clock_set_enable(PERIPH_ID_MEM, 1);
+	clock_set_enable(PERIPH_ID_IRAMA, 1);
+	clock_set_enable(PERIPH_ID_IRAMB, 1);
+	clock_set_enable(PERIPH_ID_IRAMC, 1);
+	clock_set_enable(PERIPH_ID_IRAMD, 1);
+	clock_set_enable(PERIPH_ID_CORESIGHT, 1);
+	clock_set_enable(PERIPH_ID_MSELECT, 1);
+	clock_set_enable(PERIPH_ID_EMC1, 1);
+	clock_set_enable(PERIPH_ID_MC1, 1);
+	clock_set_enable(PERIPH_ID_DVFS, 1);
+
+	/* Switch MSELECT clock to PLLP (00) */
+	clock_ll_set_source(PERIPH_ID_MSELECT, 0);
+
+	/*
+	 * Clock divider request for 102MHz would setup MSELECT clock as
+	 * 102MHz for PLLP base 408MHz
+	 */
+	clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
+		(NVBL_PLLP_KHZ/102000));
+
+	/* I2C5 (DVC) gets CLK_M and a divisor of 17 */
+	clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
+
+	/* Give clocks time to stabilize */
+	udelay(1000);
+
+	/* Take required peripherals out of reset */
+	debug("Taking periphs out of reset\n");
+	reset_set_enable(PERIPH_ID_CACHE2, 0);
+	reset_set_enable(PERIPH_ID_GPIO, 0);
+	reset_set_enable(PERIPH_ID_TMR, 0);
+	reset_set_enable(PERIPH_ID_COP, 0);
+	reset_set_enable(PERIPH_ID_EMC, 0);
+	reset_set_enable(PERIPH_ID_I2C5, 0);
+	reset_set_enable(PERIPH_ID_FUSE, 0);
+	reset_set_enable(PERIPH_ID_APBDMA, 0);
+	reset_set_enable(PERIPH_ID_MEM, 0);
+	reset_set_enable(PERIPH_ID_CORESIGHT, 0);
+	reset_set_enable(PERIPH_ID_MSELECT, 0);
+	reset_set_enable(PERIPH_ID_EMC1, 0);
+	reset_set_enable(PERIPH_ID_MC1, 0);
+
+	debug("t114_init_clocks exit\n");
+}
+
+static int is_partition_powered(u32 mask)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	/* Get power gate status */
+	reg = readl(&pmc->pmc_pwrgate_status);
+	return (reg & mask) == mask;
+}
+
+static int is_clamp_enabled(u32 mask)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	/* Get clamp status. TODO: Add pmc_clamp_status alias to pmc.h */
+	reg = readl(&pmc->pmc_pwrgate_timer_on);
+	return (reg & mask) == mask;
+}
+
+static void power_partition(u32 status, u32 partid)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	debug("%s: status = %08X, part ID = %08X\n", __func__, status, partid);
+	/* Is the partition already on? */
+	if (!is_partition_powered(status)) {
+		/* No, toggle the partition power state (OFF -> ON) */
+		debug("power_partition, toggling state\n");
+		clrbits_le32(&pmc->pmc_pwrgate_toggle, 0x1F);
+		setbits_le32(&pmc->pmc_pwrgate_toggle, partid);
+		setbits_le32(&pmc->pmc_pwrgate_toggle, START_CP);
+
+		/* Wait for the power to come up */
+		while (!is_partition_powered(status))
+			;
+
+		/* Wait for the clamp status to be cleared */
+		while (is_clamp_enabled(status))
+			;
+
+		/* Give I/O signals time to stabilize */
+		udelay(IO_STABILIZATION_DELAY);
+	}
+}
+
+void powerup_cpus(void)
+{
+	debug("powerup_cpus entry\n");
+
+	/* We boot to the fast cluster */
+	debug("powerup_cpus entry: G cluster\n");
+	/* Power up the fast cluster rail partition */
+	power_partition(CRAIL, CRAILID);
+
+	/* Power up the fast cluster non-CPU partition */
+	power_partition(C0NC, C0NCID);
+
+	/* Power up the fast cluster CPU0 partition */
+	power_partition(CE0, CE0ID);
+}
+
+void start_cpu(u32 reset_vector)
+{
+	debug("start_cpu entry, reset_vector = %x\n", reset_vector);
+
+	t114_init_clocks();
+
+	/* Enable VDD_CPU */
+	enable_cpu_power_rail();
+
+	/* Get the CPU(s) running */
+	enable_cpu_clocks();
+
+	/* Enable CoreSight */
+	clock_enable_coresight(1);
+
+	/* Take CPU(s) out of reset */
+	remove_cpu_resets();
+
+	/*
+	 * Set the entry point for CPU execution from reset,
+	 *  if it's a non-zero value.
+	 */
+	if (reset_vector)
+		writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+
+	/* If the CPU(s) don't already have power, power 'em up */
+	powerup_cpus();
+}
diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.c b/arch/arm/cpu/arm720t/tegra20/cpu.c
index ef7f375..2533899 100644
--- a/arch/arm/cpu/arm720t/tegra20/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra20/cpu.c
@@ -1,160 +1,25 @@
 /*
-* (C) Copyright 2010-2011
-* NVIDIA Corporation <www.nvidia.com>
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/pinmux.h>
 #include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/scu.h>
 #include "../tegra-common/cpu.h"
 
-/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
-int ap20_cpu_is_cortexa9(void)
-{
-	u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
-	return id == (PG_UP_TAG_0_PID_CPU & 0xff);
-}
-
-void init_pllx(void)
-{
-	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU];
-	u32 reg;
-
-	/* If PLLX is already enabled, just return */
-	if (readl(&pll->pll_base) & PLL_ENABLE_MASK)
-		return;
-
-	/* Set PLLX_MISC */
-	writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc);
-
-	/* Use 12MHz clock here */
-	reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT);
-	reg |= 1000 << PLL_DIVN_SHIFT;
-	writel(reg, &pll->pll_base);
-
-	reg |= PLL_ENABLE_MASK;
-	writel(reg, &pll->pll_base);
-
-	reg &= ~PLL_BYPASS_MASK;
-	writel(reg, &pll->pll_base);
-}
-
-static void enable_cpu_clock(int enable)
-{
-	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	u32 clk;
-
-	/*
-	 * NOTE:
-	 * Regardless of whether the request is to enable or disable the CPU
-	 * clock, every processor in the CPU complex except the master (CPU 0)
-	 * will have it's clock stopped because the AVP only talks to the
-	 * master. The AVP does not know (nor does it need to know) that there
-	 * are multiple processors in the CPU complex.
-	 */
-
-	if (enable) {
-		/* Initialize PLLX */
-		init_pllx();
-
-		/* Wait until all clocks are stable */
-		udelay(PLL_STABILIZATION_DELAY);
-
-		writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
-		writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
-	}
-
-	/*
-	 * Read the register containing the individual CPU clock enables and
-	 * always stop the clock to CPU 1.
-	 */
-	clk = readl(&clkrst->crc_clk_cpu_cmplx);
-	clk |= 1 << CPU1_CLK_STP_SHIFT;
-
-	/* Stop/Unstop the CPU clock */
-	clk &= ~CPU0_CLK_STP_MASK;
-	clk |= !enable << CPU0_CLK_STP_SHIFT;
-	writel(clk, &clkrst->crc_clk_cpu_cmplx);
-
-	clock_enable(PERIPH_ID_CPU);
-}
-
-static int is_cpu_powered(void)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
-	return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
-}
-
-static void remove_cpu_io_clamps(void)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	u32 reg;
-
-	/* Remove the clamps on the CPU I/O signals */
-	reg = readl(&pmc->pmc_remove_clamping);
-	reg |= CPU_CLMP;
-	writel(reg, &pmc->pmc_remove_clamping);
-
-	/* Give I/O signals time to stabilize */
-	udelay(IO_STABILIZATION_DELAY);
-}
-
-static void powerup_cpu(void)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	u32 reg;
-	int timeout = IO_STABILIZATION_DELAY;
-
-	if (!is_cpu_powered()) {
-		/* Toggle the CPU power state (OFF -> ON) */
-		reg = readl(&pmc->pmc_pwrgate_toggle);
-		reg &= PARTID_CP;
-		reg |= START_CP;
-		writel(reg, &pmc->pmc_pwrgate_toggle);
-
-		/* Wait for the power to come up */
-		while (!is_cpu_powered()) {
-			if (timeout-- == 0)
-				printf("CPU failed to power up!\n");
-			else
-				udelay(10);
-		}
-
-		/*
-		 * Remove the I/O clamps from CPU power partition.
-		 * Recommended only on a Warm boot, if the CPU partition gets
-		 * power gated. Shouldn't cause any harm when called after a
-		 * cold boot according to HW, probably just redundant.
-		 */
-		remove_cpu_io_clamps();
-	}
-}
-
 static void enable_cpu_power_rail(void)
 {
 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
@@ -173,49 +38,6 @@
 	udelay(3750);
 }
 
-static void reset_A9_cpu(int reset)
-{
-	/*
-	* NOTE:  Regardless of whether the request is to hold the CPU in reset
-	*        or take it out of reset, every processor in the CPU complex
-	*        except the master (CPU 0) will be held in reset because the
-	*        AVP only talks to the master. The AVP does not know that there
-	*        are multiple processors in the CPU complex.
-	*/
-
-	/* Hold CPU 1 in reset, and CPU 0 if asked */
-	reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1);
-	reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug,
-			       reset);
-
-	/* Enable/Disable master CPU reset */
-	reset_set_enable(PERIPH_ID_CPU, reset);
-}
-
-static void clock_enable_coresight(int enable)
-{
-	u32 rst, src;
-
-	clock_set_enable(PERIPH_ID_CORESIGHT, enable);
-	reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
-
-	if (enable) {
-		/*
-		 * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by
-		 *  1.5, giving an effective frequency of 144MHz.
-		 * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
-		 *  (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
-		 */
-		src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
-		clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
-
-		/* Unlock the CPU CoreSight interfaces */
-		rst = 0xC5ACCE55;
-		writel(rst, CSITE_CPU_DBG0_LAR);
-		writel(rst, CSITE_CPU_DBG1_LAR);
-	}
-}
-
 void start_cpu(u32 reset_vector)
 {
 	/* Enable VDD_CPU */
@@ -246,13 +68,3 @@
 	/* Take the CPU out of reset */
 	reset_A9_cpu(0);
 }
-
-
-void halt_avp(void)
-{
-	for (;;) {
-		writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
-			| HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
-			FLOW_CTLR_HALT_COP_EVENTS);
-	}
-}
diff --git a/arch/arm/cpu/arm720t/tegra30/Makefile b/arch/arm/cpu/arm720t/tegra30/Makefile
new file mode 100644
index 0000000..bd96997
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra30/Makefile
@@ -0,0 +1,41 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	+= cpu.o
+
+SRCS	:= $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm720t/tegra30/config.mk b/arch/arm/cpu/arm720t/tegra30/config.mk
new file mode 100644
index 0000000..2388c56
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra30/config.mk
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c
new file mode 100644
index 0000000..dedcdd9
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra30/cpu.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include "../tegra-common/cpu.h"
+
+/* Tegra30-specific CPU init code */
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(addr, &reg->cmd_addr0);
+	writel(config, &reg->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(data, &reg->cmd_data1);
+	writel(config, &reg->cnfg);
+}
+
+#define TPS65911_I2C_ADDR		0x5A
+#define TPS65911_VDDCTRL_OP_REG		0x28
+#define TPS65911_VDDCTRL_SR_REG		0x27
+#define TPS65911_VDDCTRL_OP_DATA	(0x2300 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA	(0x0100 | TPS65911_VDDCTRL_SR_REG)
+#define I2C_SEND_2_BYTES		0x0A02
+
+static void enable_cpu_power_rail(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	debug("enable_cpu_power_rail entry\n");
+	reg = readl(&pmc->pmc_cntrl);
+	reg |= CPUPWRREQ_OE;
+	writel(reg, &pmc->pmc_cntrl);
+
+	/*
+	 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+	 * First set VDD to 1.4V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
+	udelay(1000);
+	tegra_i2c_ll_write_data(TPS65911_VDDCTRL_SR_DATA, I2C_SEND_2_BYTES);
+	udelay(10 * 1000);
+}
+
+/**
+ * The T30 requires some special clock initialization, including setting up
+ * the dvc i2c, turning on mselect and selecting the G CPU cluster
+ */
+void t30_init_clocks(void)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+	u32 val;
+
+	debug("t30_init_clocks entry\n");
+	/* Set active CPU cluster to G */
+	clrbits_le32(flow->cluster_control, 1 << 0);
+
+	/*
+	 * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
+	 * at 108 MHz. This is glitch free as only the source is changed, no
+	 * special precaution needed.
+	 */
+	val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
+		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
+		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
+		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
+		(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
+	writel(val, &clkrst->crc_sclk_brst_pol);
+
+	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
+
+	val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
+		(1 << CLK_SYS_RATE_AHB_RATE_SHIFT) |
+		(0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) |
+		(0 << CLK_SYS_RATE_APB_RATE_SHIFT);
+	writel(val, &clkrst->crc_clk_sys_rate);
+
+	/* Put i2c, mselect in reset and enable clocks */
+	reset_set_enable(PERIPH_ID_DVC_I2C, 1);
+	clock_set_enable(PERIPH_ID_DVC_I2C, 1);
+	reset_set_enable(PERIPH_ID_MSELECT, 1);
+	clock_set_enable(PERIPH_ID_MSELECT, 1);
+
+	/* Switch MSELECT clock to PLLP (00) */
+	clock_ll_set_source(PERIPH_ID_MSELECT, 0);
+
+	/*
+	 * Our high-level clock routines are not available prior to
+	 * relocation. We use the low-level functions which require a
+	 * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)
+	 */
+	clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16);
+
+	/*
+	 * Give clocks time to stabilize, then take i2c and mselect out of
+	 * reset
+	 */
+	udelay(1000);
+	reset_set_enable(PERIPH_ID_DVC_I2C, 0);
+	reset_set_enable(PERIPH_ID_MSELECT, 0);
+}
+
+static void set_cpu_running(int run)
+{
+	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+
+	debug("set_cpu_running entry, run = %d\n", run);
+	writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events);
+}
+
+void start_cpu(u32 reset_vector)
+{
+	debug("start_cpu entry, reset_vector = %x\n", reset_vector);
+	t30_init_clocks();
+
+	/* Enable VDD_CPU */
+	enable_cpu_power_rail();
+
+	set_cpu_running(0);
+
+	/* Hold the CPUs in reset */
+	reset_A9_cpu(1);
+
+	/* Disable the CPU clock */
+	enable_cpu_clock(0);
+
+	/* Enable CoreSight */
+	clock_enable_coresight(1);
+
+	/*
+	 * Set the entry point for CPU execution from reset,
+	 *  if it's a non-zero value.
+	 */
+	if (reset_vector)
+		writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+
+	/* Enable the CPU clock */
+	enable_cpu_clock(1);
+
+	/* If the CPU doesn't already have power, power it up */
+	powerup_cpu();
+
+	/* Take the CPU out of reset */
+	reset_A9_cpu(0);
+
+	set_cpu_running(1);
+}
diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk
index 6a3a1bb..47f24f5 100644
--- a/arch/arm/cpu/arm926ejs/config.mk
+++ b/arch/arm/cpu/arm926ejs/config.mk
@@ -34,6 +34,6 @@
 
 ifneq ($(CONFIG_IMX_CONFIG),)
 
-ALL-y	+= $(obj)u-boot.imx
+ALL-y	+= $(OBJTREE)/u-boot.imx
 
 endif
diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c
index 4ff19c3..00b9aba 100644
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -1,5 +1,5 @@
 /*
- * Freescale i.MX28 clock setup code
+ * Freescale i.MX23/i.MX28 clock setup code
  *
  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  * on behalf of DENX Software Engineering GmbH
@@ -32,16 +32,25 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 
-/* The PLL frequency is always 480MHz, see section 10.2 in iMX28 datasheet. */
+/*
+ * The PLL frequency is 480MHz and XTAL frequency is 24MHz
+ *   iMX23: datasheet section 4.2
+ *   iMX28: datasheet section 10.2
+ */
 #define	PLL_FREQ_KHZ	480000
 #define	PLL_FREQ_COEF	18
-/* The XTAL frequency is always 24MHz, see section 10.2 in iMX28 datasheet. */
 #define	XTAL_FREQ_KHZ	24000
 
 #define	PLL_FREQ_MHZ	(PLL_FREQ_KHZ / 1000)
 #define	XTAL_FREQ_MHZ	(XTAL_FREQ_KHZ / 1000)
 
-static uint32_t mx28_get_pclk(void)
+#if defined(CONFIG_MX23)
+#define MXC_SSPCLK_MAX MXC_SSPCLK0
+#elif defined(CONFIG_MX28)
+#define MXC_SSPCLK_MAX MXC_SSPCLK3
+#endif
+
+static uint32_t mxs_get_pclk(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -73,7 +82,7 @@
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
 }
 
-static uint32_t mx28_get_hclk(void)
+static uint32_t mxs_get_hclk(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -88,10 +97,10 @@
 		return 0;
 
 	div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
-	return mx28_get_pclk() / div;
+	return mxs_get_pclk() / div;
 }
 
-static uint32_t mx28_get_emiclk(void)
+static uint32_t mxs_get_emiclk(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -116,11 +125,17 @@
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
 }
 
-static uint32_t mx28_get_gpmiclk(void)
+static uint32_t mxs_get_gpmiclk(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
-
+#if defined(CONFIG_MX23)
+	uint8_t *reg =
+		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU];
+#elif defined(CONFIG_MX28)
+	uint8_t *reg =
+		&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI];
+#endif
 	uint32_t clkctrl, clkseq, div;
 	uint8_t clkfrac, frac;
 
@@ -134,7 +149,7 @@
 	}
 
 	/* REF Path */
-	clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]);
+	clkfrac = readb(reg);
 	frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
 	div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
@@ -143,7 +158,7 @@
 /*
  * Set IO clock frequency, in kHz
  */
-void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
+void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -176,7 +191,7 @@
 /*
  * Get IO clock, returns IO clock in kHz
  */
-static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
+static uint32_t mxs_get_ioclk(enum mxs_ioclock io)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -197,13 +212,13 @@
 /*
  * Configure SSP clock frequency, in kHz
  */
-void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
+void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	uint32_t clk, clkreg;
 
-	if (ssp > MXC_SSPCLK3)
+	if (ssp > MXC_SSPCLK_MAX)
 		return;
 
 	clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
@@ -216,7 +231,7 @@
 	if (xtal)
 		clk = XTAL_FREQ_KHZ;
 	else
-		clk = mx28_get_ioclk(ssp >> 1);
+		clk = mxs_get_ioclk(ssp >> 1);
 
 	if (freq > clk)
 		return;
@@ -241,14 +256,14 @@
 /*
  * Return SSP frequency, in kHz
  */
-static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
+static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	uint32_t clkreg;
 	uint32_t clk, tmp;
 
-	if (ssp > MXC_SSPCLK3)
+	if (ssp > MXC_SSPCLK_MAX)
 		return 0;
 
 	tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq);
@@ -263,7 +278,7 @@
 	if (tmp == 0)
 		return 0;
 
-	clk = mx28_get_ioclk(ssp >> 1);
+	clk = mxs_get_ioclk(ssp >> 1);
 
 	return clk / tmp;
 }
@@ -271,14 +286,14 @@
 /*
  * Set SSP/MMC bus frequency, in kHz)
  */
-void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq)
+void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
 {
 	struct mxs_ssp_regs *ssp_regs;
-	const uint32_t sspclk = mx28_get_sspclk(bus);
+	const uint32_t sspclk = mxs_get_sspclk(bus);
 	uint32_t reg;
 	uint32_t divide, rate, tgtclk;
 
-	ssp_regs = (struct mxs_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
+	ssp_regs = mxs_ssp_regs_by_bus(bus);
 
 	/*
 	 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
@@ -313,28 +328,30 @@
 {
 	switch (clk) {
 	case MXC_ARM_CLK:
-		return mx28_get_pclk() * 1000000;
+		return mxs_get_pclk() * 1000000;
 	case MXC_GPMI_CLK:
-		return mx28_get_gpmiclk() * 1000000;
+		return mxs_get_gpmiclk() * 1000000;
 	case MXC_AHB_CLK:
 	case MXC_IPG_CLK:
-		return mx28_get_hclk() * 1000000;
+		return mxs_get_hclk() * 1000000;
 	case MXC_EMI_CLK:
-		return mx28_get_emiclk();
+		return mxs_get_emiclk();
 	case MXC_IO0_CLK:
-		return mx28_get_ioclk(MXC_IOCLK0);
+		return mxs_get_ioclk(MXC_IOCLK0);
 	case MXC_IO1_CLK:
-		return mx28_get_ioclk(MXC_IOCLK1);
+		return mxs_get_ioclk(MXC_IOCLK1);
+	case MXC_XTAL_CLK:
+		return XTAL_FREQ_KHZ * 1000;
 	case MXC_SSP0_CLK:
-		return mx28_get_sspclk(MXC_SSPCLK0);
+		return mxs_get_sspclk(MXC_SSPCLK0);
+#ifdef CONFIG_MX28
 	case MXC_SSP1_CLK:
-		return mx28_get_sspclk(MXC_SSPCLK1);
+		return mxs_get_sspclk(MXC_SSPCLK1);
 	case MXC_SSP2_CLK:
-		return mx28_get_sspclk(MXC_SSPCLK2);
+		return mxs_get_sspclk(MXC_SSPCLK2);
 	case MXC_SSP3_CLK:
-		return mx28_get_sspclk(MXC_SSPCLK3);
-	case MXC_XTAL_CLK:
-		return XTAL_FREQ_KHZ * 1000;
+		return mxs_get_sspclk(MXC_SSPCLK3);
+#endif
 	}
 
 	return 0;
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index 6ce8019..e2b4196 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -1,5 +1,5 @@
 /*
- * Freescale i.MX28 common code
+ * Freescale i.MX23/i.MX28 common code
  *
  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  * on behalf of DENX Software Engineering GmbH
@@ -35,6 +35,7 @@
 #include <asm/arch/iomux.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
+#include <linux/compiler.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -196,6 +197,8 @@
 		(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
 
 	switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
+	case HW_DIGCTL_CHIPID_MX23:
+		return "23";
 	case HW_DIGCTL_CHIPID_MX28:
 		return "28";
 	default:
@@ -210,6 +213,21 @@
 	uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
 
 	switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
+	case HW_DIGCTL_CHIPID_MX23:
+		switch (rev) {
+		case 0x0:
+			return "1.0";
+		case 0x1:
+			return "1.1";
+		case 0x2:
+			return "1.2";
+		case 0x3:
+			return "1.3";
+		case 0x4:
+			return "1.4";
+		default:
+			return "??";
+		}
 	case HW_DIGCTL_CHIPID_MX28:
 		switch (rev) {
 		case 0x1:
@@ -276,7 +294,7 @@
 }
 #endif
 
-static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
+__weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
 {
 	mac[0] = 0x00;
 	mac[1] = 0x04; /* Use FSL vendor MAC address by default */
@@ -285,9 +303,6 @@
 		mac[5] += 1;
 }
 
-void mx28_adjust_mac(int dev_id, unsigned char *mac)
-	__attribute__((weak, alias("__mx28_adjust_mac")));
-
 #ifdef	CONFIG_MX28_FEC_MAC_IN_OCOTP
 
 #define	MXS_OCOTP_MAX_TIMEOUT	1000000
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index 1b8502e..7e70440 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -51,12 +51,21 @@
 
 #define	MUX_CONFIG_BOOTMODE_PAD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
 static const iomux_cfg_t iomux_boot[] = {
+#if defined(CONFIG_MX23)
+	MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
+	MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
+	MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
+	MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
+	MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
+	MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
+#elif defined(CONFIG_MX28)
 	MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
 	MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
 	MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
 	MX28_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
 	MX28_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
 	MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
+#endif
 };
 
 static uint8_t mxs_get_bootmode_index(void)
@@ -68,6 +77,21 @@
 	/* Setup IOMUX of bootmode pads to GPIO */
 	mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot));
 
+#if defined(CONFIG_MX23)
+	/* Setup bootmode pins as GPIO input */
+	gpio_direction_input(MX23_PAD_LCD_D00__GPIO_1_0);
+	gpio_direction_input(MX23_PAD_LCD_D01__GPIO_1_1);
+	gpio_direction_input(MX23_PAD_LCD_D02__GPIO_1_2);
+	gpio_direction_input(MX23_PAD_LCD_D03__GPIO_1_3);
+	gpio_direction_input(MX23_PAD_LCD_D05__GPIO_1_5);
+
+	/* Read bootmode pads */
+	bootmode |= (gpio_get_value(MX23_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0;
+	bootmode |= (gpio_get_value(MX23_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1;
+	bootmode |= (gpio_get_value(MX23_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2;
+	bootmode |= (gpio_get_value(MX23_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
+	bootmode |= (gpio_get_value(MX23_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
+#elif defined(CONFIG_MX28)
 	/* Setup bootmode pins as GPIO input */
 	gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0);
 	gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1);
@@ -83,6 +107,7 @@
 	bootmode |= (gpio_get_value(MX28_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
 	bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4;
 	bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
+#endif
 
 	for (i = 0; i < ARRAY_SIZE(mxs_boot_modes); i++) {
 		masked = bootmode & mxs_boot_modes[i].boot_mask;
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index 401c513..f8392f6 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -27,6 +27,7 @@
 #include <config.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
+#include <linux/compiler.h>
 
 #include "mxs_init.h"
 
@@ -83,16 +84,30 @@
 	0x06120612, 0x04320432, 0x04320432, 0x00040004,
 	0x00040004, 0x00000000, 0x00000000, 0x00000000,
 	0x00000000, 0x00010001
+
+/*
+ * i.MX23 DDR at 133MHz
+ */
+#elif defined(CONFIG_MX23)
+	0x01010001, 0x00010100, 0x01000101, 0x00000001,
+	0x00000101, 0x00000000, 0x00010000, 0x01000001,
+	0x00000000, 0x00000001, 0x07000200, 0x00070202,
+	0x02020000, 0x04040a01, 0x00000201, 0x02040000,
+	0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313,
+	0x02061521, 0x0000000a, 0x00080008, 0x00200020,
+	0x00200020, 0x00200020, 0x000003f7, 0x00000000,
+	0x00000000, 0x00000020, 0x00000020, 0x00c80000,
+	0x000a23cd, 0x000000c8, 0x00006665, 0x00000000,
+	0x00000101, 0x00040001, 0x00000000, 0x00000000,
+	0x00010000
 #else
 #error Unsupported memory initialization
 #endif
 };
 
-void __mxs_adjust_memory_params(uint32_t *dram_vals)
+__weak void mxs_adjust_memory_params(uint32_t *dram_vals)
 {
 }
-void mxs_adjust_memory_params(uint32_t *dram_vals)
-	__attribute__((weak, alias("__mxs_adjust_memory_params")));
 
 static void initialize_dram_values(void)
 {
@@ -102,19 +117,30 @@
 
 	for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
 		writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+
+#ifdef CONFIG_MX23
+	writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
+#endif
 }
 
 static void mxs_mem_init_clock(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+#if defined(CONFIG_MX23)
+	/* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */
+	const unsigned char divider = 33;
+#elif defined(CONFIG_MX28)
+	/* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */
+	const unsigned char divider = 21;
+#endif
 
 	/* Gate EMI clock */
 	writeb(CLKCTRL_FRAC_CLKGATE,
 		&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
 
-	/* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */
-	writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK),
+	/* Set fractional divider for ref_emi */
+	writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK),
 		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
 
 	/* Ungate EMI clock */
@@ -197,10 +223,60 @@
 	return sz;
 }
 
-void mxs_mem_init(void)
+#ifdef CONFIG_MX23
+static void mx23_mem_setup_vddmem(void)
 {
-	struct mxs_clkctrl_regs *clkctrl_regs =
-		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) |
+		POWER_VDDMEMCTRL_ENABLE_ILIMIT |
+		POWER_VDDMEMCTRL_ENABLE_LINREG |
+		POWER_VDDMEMCTRL_PULLDOWN_ACTIVE,
+		&power_regs->hw_power_vddmemctrl);
+
+	early_delay(10000);
+
+	writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) |
+		POWER_VDDMEMCTRL_ENABLE_LINREG,
+		&power_regs->hw_power_vddmemctrl);
+}
+
+static void mx23_mem_init(void)
+{
+	mx23_mem_setup_vddmem();
+
+	/*
+	 * Configure the DRAM registers
+	 */
+
+	/* Clear START and SREFRESH bit from DRAM_CTL8 */
+	clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8));
+
+	initialize_dram_values();
+
+	/* Set START bit in DRAM_CTL16 */
+	setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
+
+	clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
+	early_delay(20000);
+
+	/* Adjust EMI port priority. */
+	clrsetbits_le32(0x80020000, 0x1f << 16, 0x8);
+	early_delay(20000);
+
+	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
+	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
+
+	/* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */
+	while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10)))
+		;
+}
+#endif
+
+#ifdef CONFIG_MX28
+static void mx28_mem_init(void)
+{
 	struct mxs_pinctrl_regs *pinctrl_regs =
 		(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
 
@@ -208,16 +284,6 @@
 	writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
 		&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
 
-	/* Power up PLL0 */
-	writel(CLKCTRL_PLL0CTRL0_POWER,
-		&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
-
-	early_delay(11000);
-
-	mxs_mem_init_clock();
-
-	mxs_mem_setup_vdda();
-
 	/*
 	 * Configure the DRAM registers
 	 */
@@ -236,6 +302,22 @@
 	/* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */
 	while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
 		;
+}
+#endif
+
+void mxs_mem_init(void)
+{
+	early_delay(11000);
+
+	mxs_mem_init_clock();
+
+	mxs_mem_setup_vdda();
+
+#if defined(CONFIG_MX23)
+	mx23_mem_init();
+#elif defined(CONFIG_MX28)
+	mx28_mem_init();
+#endif
 
 	early_delay(10000);
 
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index be44c22..e9d6302 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -881,11 +881,23 @@
 	early_delay(10);
 }
 
+static void mxs_ungate_power(void)
+{
+#ifdef CONFIG_MX23
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
+#endif
+}
+
 void mxs_power_init(void)
 {
 	struct mxs_power_regs *power_regs =
 		(struct mxs_power_regs *)MXS_POWER_BASE;
 
+	mxs_ungate_power();
+
 	mxs_power_clock2xtal();
 	mxs_power_clear_auto_restart();
 	mxs_power_set_linreg();
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
new file mode 100644
index 0000000..3a51879
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
@@ -0,0 +1,18 @@
+options {
+	driveTag = 0x00;
+	flags = 0x01;
+}
+
+sources {
+	u_boot_spl="spl/u-boot-spl.bin";
+	u_boot="u-boot.bin";
+}
+
+section (0) {
+	load u_boot_spl > 0x0000;
+	load ivt (entry = 0x0014) > 0x8000;
+	call 0x8000;
+
+	load u_boot > 0x40000100;
+	call 0x40000100;
+}
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 4fdbee4..ee8c2b3 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,7 @@
 COBJS	+= cpu.o
 COBJS	+= syslib.o
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA),)
 SOBJS	+= lowlevel_init.o
 endif
 
diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk
index 9c3e2f3..350e946 100644
--- a/arch/arm/cpu/armv7/config.mk
+++ b/arch/arm/cpu/armv7/config.mk
@@ -40,5 +40,5 @@
 PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
 
 ifneq ($(CONFIG_IMX_CONFIG),)
-ALL-y	+= $(obj)u-boot.imx
+ALL-y	+= $(OBJTREE)/u-boot.imx
 endif
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index dcc1f83..6b59529d 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -251,12 +251,12 @@
 /*
  * Move vector table
  */
-#if !defined(CONFIG_TEGRA20)
+#if !defined(CONFIG_TEGRA)
 	/* Set vector address in CP15 VBAR register */
 	ldr     r0, =_start
 	add     r0, r0, r9
 	mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
-#endif /* !Tegra20 */
+#endif /* !Tegra */
 
 	bx	lr
 
diff --git a/arch/arm/cpu/armv7/tegra114/Makefile b/arch/arm/cpu/armv7/tegra114/Makefile
new file mode 100644
index 0000000..eb98c8e
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra114/Makefile
@@ -0,0 +1,40 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/tegra114/config.mk b/arch/arm/cpu/armv7/tegra114/config.mk
new file mode 100644
index 0000000..cb1a19d
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra114/config.mk
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+CONFIG_ARCH_DEVICE_TREE := tegra114
diff --git a/arch/arm/cpu/armv7/tegra30/Makefile b/arch/arm/cpu/armv7/tegra30/Makefile
new file mode 100644
index 0000000..04adb52
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra30/Makefile
@@ -0,0 +1,40 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/tegra30/config.mk b/arch/arm/cpu/armv7/tegra30/config.mk
new file mode 100644
index 0000000..719ca81
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra30/config.mk
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+CONFIG_ARCH_DEVICE_TREE := tegra30
diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/cpu/tegra-common/Makefile
index 38e90d3..8e95c7e 100644
--- a/arch/arm/cpu/tegra-common/Makefile
+++ b/arch/arm/cpu/tegra-common/Makefile
@@ -28,7 +28,7 @@
 LIB	= $(obj)libcputegra-common.o
 
 SOBJS += lowlevel_init.o
-COBJS-y	+= ap.o board.o sys_info.o timer.o
+COBJS-y	+= ap.o board.o sys_info.o timer.o clock.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index c4eb137..236cda8 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -20,13 +20,18 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
+
+/* Tegra AP (Application Processor) code */
+
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/gp_padctrl.h>
 #include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/clock.h>
 #include <asm/arch-tegra/fuse.h>
 #include <asm/arch-tegra/pmc.h>
 #include <asm/arch-tegra/scu.h>
+#include <asm/arch-tegra/tegra.h>
 #include <asm/arch-tegra/warmboot.h>
 
 int tegra_get_chip_type(void)
@@ -38,7 +43,7 @@
 	/*
 	 * This is undocumented, Chip ID is bits 15:8 of the register
 	 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
-	 * Tegra30
+	 * Tegra30, and 0x35 for T114.
 	 */
 	gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
@@ -58,6 +63,18 @@
 			return TEGRA_SOC_T25;
 		}
 		break;
+	case CHIPID_TEGRA30:
+		switch (tegra_sku_id) {
+		case SKU_ID_T30:
+			return TEGRA_SOC_T30;
+		}
+		break;
+	case CHIPID_TEGRA114:
+		switch (tegra_sku_id) {
+		case SKU_ID_T114_ENG:
+			return TEGRA_SOC_T114;
+		}
+		break;
 	}
 	/* unknown sku id */
 	return TEGRA_SOC_UNKNOWN;
@@ -93,7 +110,7 @@
 
 	u32 bct_start, odmdata;
 
-	bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
+	bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
 	odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
 
 	return odmdata;
@@ -127,5 +144,5 @@
 		"orr	r0, r0, #0x41\n"
 		"mcr	p15, 0, r0, c1, c0, 1\n");
 
-	/* FIXME: should have ap20's L2 disabled too? */
+	/* FIXME: should have SoC's L2 disabled too? */
 }
diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c
index b2e10c6..58ea628 100644
--- a/arch/arm/cpu/tegra-common/board.c
+++ b/arch/arm/cpu/tegra-common/board.c
@@ -37,8 +37,10 @@
 	/* UARTs which we can enable */
 	UARTA	= 1 << 0,
 	UARTB	= 1 << 1,
+	UARTC	= 1 << 2,
 	UARTD	= 1 << 3,
-	UART_COUNT = 4,
+	UARTE	= 1 << 4,
+	UART_COUNT = 5,
 };
 
 /*
@@ -54,16 +56,37 @@
 	reg = readl(&pmc->pmc_scratch20);
 	debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
 
-	/* bits 31:28 in OdmData are used for RAM size  */
+#if defined(CONFIG_TEGRA20)
+	/* bits 30:28 in OdmData are used for RAM size on T20  */
+	reg &= 0x70000000;
+
 	switch ((reg) >> 28) {
 	case 1:
 		return 0x10000000;	/* 256 MB */
+	case 0:
 	case 2:
 	default:
 		return 0x20000000;	/* 512 MB */
 	case 3:
 		return 0x40000000;	/* 1GB */
 	}
+#else	/* Tegra30/Tegra114 */
+	/* bits 31:28 in OdmData are used for RAM size on T30  */
+	switch ((reg) >> 28) {
+	case 0:
+	case 1:
+	default:
+		return 0x10000000;	/* 256 MB */
+	case 2:
+		return 0x20000000;	/* 512 MB */
+	case 3:
+		return 0x30000000;	/* 768 MB */
+	case 4:
+		return 0x40000000;	/* 1GB */
+	case 8:
+		return 0x7ff00000;	/* 2GB - 1MB */
+	}
+#endif
 }
 
 int dram_init(void)
@@ -82,19 +105,33 @@
 #endif	/* CONFIG_DISPLAY_BOARDINFO */
 
 static int uart_configs[] = {
-#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
+#if defined(CONFIG_TEGRA20)
+ #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
 	FUNCMUX_UART1_UAA_UAB,
-#elif defined(CONFIG_TEGRA_UARTA_GPU)
+ #elif defined(CONFIG_TEGRA_UARTA_GPU)
 	FUNCMUX_UART1_GPU,
-#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
+ #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
 	FUNCMUX_UART1_SDIO1,
-#else
+ #else
 	FUNCMUX_UART1_IRRX_IRTX,
 #endif
-	FUNCMUX_UART2_IRDA,
+	FUNCMUX_UART2_UAD,
 	-1,
 	FUNCMUX_UART4_GMC,
 	-1,
+#elif defined(CONFIG_TEGRA30)
+	FUNCMUX_UART1_ULPI,	/* UARTA */
+	-1,
+	-1,
+	-1,
+	-1,
+#else	/* Tegra114 */
+	-1,
+	-1,
+	-1,
+	FUNCMUX_UART4_GMI,	/* UARTD */
+	-1,
+#endif
 };
 
 /**
@@ -109,6 +146,7 @@
 		PERIPH_ID_UART2,
 		PERIPH_ID_UART3,
 		PERIPH_ID_UART4,
+		PERIPH_ID_UART5,
 	};
 	size_t i;
 
@@ -132,9 +170,15 @@
 #ifdef CONFIG_TEGRA_ENABLE_UARTB
 	uart_ids |= UARTB;
 #endif
+#ifdef CONFIG_TEGRA_ENABLE_UARTC
+	uart_ids |= UARTC;
+#endif
 #ifdef CONFIG_TEGRA_ENABLE_UARTD
 	uart_ids |= UARTD;
 #endif
+#ifdef CONFIG_TEGRA_ENABLE_UARTE
+	uart_ids |= UARTE;
+#endif
 	setup_uarts(uart_ids);
 }
 
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c
new file mode 100644
index 0000000..49a0633
--- /dev/null
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -0,0 +1,560 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra SoC common clock control functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+#include <div64.h>
+#include <fdtdec.h>
+
+/*
+ * This is our record of the current clock rate of each clock. We don't
+ * fill all of these in since we are only really interested in clocks which
+ * we use as parents.
+ */
+static unsigned pll_rate[CLOCK_ID_COUNT];
+
+/*
+ * The oscillator frequency is fixed to one of four set values. Based on this
+ * the other clocks are set up appropriately.
+ */
+static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
+	13000000,
+	19200000,
+	12000000,
+	26000000,
+};
+
+/* return 1 if a peripheral ID is in range */
+#define clock_type_id_isvalid(id) ((id) >= 0 && \
+		(id) < CLOCK_TYPE_COUNT)
+
+char pllp_valid = 1;	/* PLLP is set up correctly */
+
+/* return 1 if a periphc_internal_id is in range */
+#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
+		(id) < PERIPHC_COUNT)
+
+/* number of clock outputs of a PLL */
+static const u8 pll_num_clkouts[] = {
+	1,	/* PLLC */
+	1,	/* PLLM */
+	4,	/* PLLP */
+	1,	/* PLLA */
+	0,	/* PLLU */
+	0,	/* PLLD */
+};
+
+int clock_get_osc_bypass(void)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	reg = readl(&clkrst->crc_osc_ctrl);
+	return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
+}
+
+/* Returns a pointer to the registers of the given pll */
+static struct clk_pll *get_pll(enum clock_id clkid)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+	assert(clock_id_is_pll(clkid));
+	return &clkrst->crc_pll[clkid];
+}
+
+int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
+		u32 *divp, u32 *cpcon, u32 *lfcon)
+{
+	struct clk_pll *pll = get_pll(clkid);
+	u32 data;
+
+	assert(clkid != CLOCK_ID_USB);
+
+	/* Safety check, adds to code size but is small */
+	if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
+		return -1;
+	data = readl(&pll->pll_base);
+	*divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
+	*divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT;
+	*divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
+	data = readl(&pll->pll_misc);
+	*cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
+	*lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
+
+	return 0;
+}
+
+unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
+		u32 divp, u32 cpcon, u32 lfcon)
+{
+	struct clk_pll *pll = get_pll(clkid);
+	u32 data;
+
+	/*
+	 * We cheat by treating all PLL (except PLLU) in the same fashion.
+	 * This works only because:
+	 * - same fields are always mapped at same offsets, except DCCON
+	 * - DCCON is always 0, doesn't conflict
+	 * - M,N, P of PLLP values are ignored for PLLP
+	 */
+	data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
+	writel(data, &pll->pll_misc);
+
+	data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
+			(0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
+
+	if (clkid == CLOCK_ID_USB)
+		data |= divp << PLLU_VCO_FREQ_SHIFT;
+	else
+		data |= divp << PLL_DIVP_SHIFT;
+	writel(data, &pll->pll_base);
+
+	/* calculate the stable time */
+	return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
+}
+
+void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
+			unsigned divisor)
+{
+	u32 *reg = get_periph_source_reg(periph_id);
+	u32 value;
+
+	value = readl(reg);
+
+	value &= ~OUT_CLK_SOURCE_MASK;
+	value |= source << OUT_CLK_SOURCE_SHIFT;
+
+	value &= ~OUT_CLK_DIVISOR_MASK;
+	value |= divisor << OUT_CLK_DIVISOR_SHIFT;
+
+	writel(value, reg);
+}
+
+void clock_ll_set_source(enum periph_id periph_id, unsigned source)
+{
+	u32 *reg = get_periph_source_reg(periph_id);
+
+	clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
+			source << OUT_CLK_SOURCE_SHIFT);
+}
+
+/**
+ * Given the parent's rate and the required rate for the children, this works
+ * out the peripheral clock divider to use, in 7.1 binary format.
+ *
+ * @param divider_bits	number of divider bits (8 or 16)
+ * @param parent_rate	clock rate of parent clock in Hz
+ * @param rate		required clock rate for this clock
+ * @return divider which should be used
+ */
+static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
+			   unsigned long rate)
+{
+	u64 divider = parent_rate * 2;
+	unsigned max_divider = 1 << divider_bits;
+
+	divider += rate - 1;
+	do_div(divider, rate);
+
+	if ((s64)divider - 2 < 0)
+		return 0;
+
+	if ((s64)divider - 2 >= max_divider)
+		return -1;
+
+	return divider - 2;
+}
+
+int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
+{
+	struct clk_pll *pll = get_pll(clkid);
+	int data = 0, div = 0, offset = 0;
+
+	if (!clock_id_is_pll(clkid))
+		return -1;
+
+	if (pllout + 1 > pll_num_clkouts[clkid])
+		return -1;
+
+	div = clk_get_divider(8, pll_rate[clkid], rate);
+
+	if (div < 0)
+		return -1;
+
+	/* out2 and out4 are in the high part of the register */
+	if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
+		offset = 16;
+
+	data = (div << PLL_OUT_RATIO_SHIFT) |
+			PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
+	clrsetbits_le32(&pll->pll_out[pllout >> 1],
+			PLL_OUT_RATIO_MASK << offset, data << offset);
+
+	return 0;
+}
+
+/**
+ * Given the parent's rate and the divider in 7.1 format, this works out the
+ * resulting peripheral clock rate.
+ *
+ * @param parent_rate	clock rate of parent clock in Hz
+ * @param divider which should be used in 7.1 format
+ * @return effective clock rate of peripheral
+ */
+static unsigned long get_rate_from_divider(unsigned long parent_rate,
+					   int divider)
+{
+	u64 rate;
+
+	rate = (u64)parent_rate * 2;
+	do_div(rate, divider + 2);
+	return rate;
+}
+
+unsigned long clock_get_periph_rate(enum periph_id periph_id,
+		enum clock_id parent)
+{
+	u32 *reg = get_periph_source_reg(periph_id);
+
+	return get_rate_from_divider(pll_rate[parent],
+		(readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
+}
+
+/**
+ * Find the best available 7.1 format divisor given a parent clock rate and
+ * required child clock rate. This function assumes that a second-stage
+ * divisor is available which can divide by powers of 2 from 1 to 256.
+ *
+ * @param divider_bits	number of divider bits (8 or 16)
+ * @param parent_rate	clock rate of parent clock in Hz
+ * @param rate		required clock rate for this clock
+ * @param extra_div	value for the second-stage divisor (not set if this
+ *			function returns -1.
+ * @return divider which should be used, or -1 if nothing is valid
+ *
+ */
+static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
+				unsigned long rate, int *extra_div)
+{
+	int shift;
+	int best_divider = -1;
+	int best_error = rate;
+
+	/* try dividers from 1 to 256 and find closest match */
+	for (shift = 0; shift <= 8 && best_error > 0; shift++) {
+		unsigned divided_parent = parent_rate >> shift;
+		int divider = clk_get_divider(divider_bits, divided_parent,
+						rate);
+		unsigned effective_rate = get_rate_from_divider(divided_parent,
+						divider);
+		int error = rate - effective_rate;
+
+		/* Given a valid divider, look for the lowest error */
+		if (divider != -1 && error < best_error) {
+			best_error = error;
+			*extra_div = 1 << shift;
+			best_divider = divider;
+		}
+	}
+
+	/* return what we found - *extra_div will already be set */
+	return best_divider;
+}
+
+/**
+ * Adjust peripheral PLL to use the given divider and source.
+ *
+ * @param periph_id	peripheral to adjust
+ * @param source	Source number (0-3 or 0-7)
+ * @param mux_bits	Number of mux bits (2 or 4)
+ * @param divider	Required divider in 7.1 or 15.1 format
+ * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
+ *		for this peripheral)
+ */
+static int adjust_periph_pll(enum periph_id periph_id, int source,
+				int mux_bits, unsigned divider)
+{
+	u32 *reg = get_periph_source_reg(periph_id);
+
+	clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
+			divider << OUT_CLK_DIVISOR_SHIFT);
+	udelay(1);
+
+	/* work out the source clock and set it */
+	if (source < 0)
+		return -1;
+	if (mux_bits == 4) {
+		clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK,
+			source << OUT_CLK_SOURCE4_SHIFT);
+	} else {
+		clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
+			source << OUT_CLK_SOURCE_SHIFT);
+	}
+	udelay(2);
+	return 0;
+}
+
+unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
+		enum clock_id parent, unsigned rate, int *extra_div)
+{
+	unsigned effective_rate;
+	int mux_bits, divider_bits, source;
+	int divider;
+
+	/* work out the source clock and set it */
+	source = get_periph_clock_source(periph_id, parent, &mux_bits,
+					 &divider_bits);
+
+	if (extra_div)
+		divider = find_best_divider(divider_bits, pll_rate[parent],
+						rate, extra_div);
+	else
+		divider = clk_get_divider(divider_bits, pll_rate[parent],
+					  rate);
+	assert(divider >= 0);
+	if (adjust_periph_pll(periph_id, source, mux_bits, divider))
+		return -1U;
+	debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
+		get_periph_source_reg(periph_id),
+		readl(get_periph_source_reg(periph_id)));
+
+	/* Check what we ended up with. This shouldn't matter though */
+	effective_rate = clock_get_periph_rate(periph_id, parent);
+	if (extra_div)
+		effective_rate /= *extra_div;
+	if (rate != effective_rate)
+		debug("Requested clock rate %u not honored (got %u)\n",
+			rate, effective_rate);
+	return effective_rate;
+}
+
+unsigned clock_start_periph_pll(enum periph_id periph_id,
+		enum clock_id parent, unsigned rate)
+{
+	unsigned effective_rate;
+
+	reset_set_enable(periph_id, 1);
+	clock_enable(periph_id);
+
+	effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
+						 NULL);
+
+	reset_set_enable(periph_id, 0);
+	return effective_rate;
+}
+
+void clock_enable(enum periph_id clkid)
+{
+	clock_set_enable(clkid, 1);
+}
+
+void clock_disable(enum periph_id clkid)
+{
+	clock_set_enable(clkid, 0);
+}
+
+void reset_periph(enum periph_id periph_id, int us_delay)
+{
+	/* Put peripheral into reset */
+	reset_set_enable(periph_id, 1);
+	udelay(us_delay);
+
+	/* Remove reset */
+	reset_set_enable(periph_id, 0);
+
+	udelay(us_delay);
+}
+
+void reset_cmplx_set_enable(int cpu, int which, int reset)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 mask;
+
+	/* Form the mask, which depends on the cpu chosen (2 or 4) */
+	assert(cpu >= 0 && cpu < MAX_NUM_CPU);
+	mask = which << cpu;
+
+	/* either enable or disable those reset for that CPU */
+	if (reset)
+		writel(mask, &clkrst->crc_cpu_cmplx_set);
+	else
+		writel(mask, &clkrst->crc_cpu_cmplx_clr);
+}
+
+unsigned clock_get_rate(enum clock_id clkid)
+{
+	struct clk_pll *pll;
+	u32 base;
+	u32 divm;
+	u64 parent_rate;
+	u64 rate;
+
+	parent_rate = osc_freq[clock_get_osc_freq()];
+	if (clkid == CLOCK_ID_OSC)
+		return parent_rate;
+
+	pll = get_pll(clkid);
+	base = readl(&pll->pll_base);
+
+	/* Oh for bf_unpack()... */
+	rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT);
+	divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
+	if (clkid == CLOCK_ID_USB)
+		divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT;
+	else
+		divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
+	do_div(rate, divm);
+	return rate;
+}
+
+/**
+ * Set the output frequency you want for each PLL clock.
+ * PLL output frequencies are programmed by setting their N, M and P values.
+ * The governing equations are:
+ *     VCO = (Fi / m) * n, Fo = VCO / (2^p)
+ *     where Fo is the output frequency from the PLL.
+ * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
+ *     216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
+ * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
+ *
+ * @param n PLL feedback divider(DIVN)
+ * @param m PLL input divider(DIVN)
+ * @param p post divider(DIVP)
+ * @param cpcon base PLL charge pump(CPCON)
+ * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
+ *		be overriden), 1 if PLL is already correct
+ */
+int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
+{
+	u32 base_reg;
+	u32 misc_reg;
+	struct clk_pll *pll;
+
+	pll = get_pll(clkid);
+
+	base_reg = readl(&pll->pll_base);
+
+	/* Set BYPASS, m, n and p to PLL_BASE */
+	base_reg &= ~PLL_DIVM_MASK;
+	base_reg |= m << PLL_DIVM_SHIFT;
+
+	base_reg &= ~PLL_DIVN_MASK;
+	base_reg |= n << PLL_DIVN_SHIFT;
+
+	base_reg &= ~PLL_DIVP_MASK;
+	base_reg |= p << PLL_DIVP_SHIFT;
+
+	if (clkid == CLOCK_ID_PERIPH) {
+		/*
+		 * If the PLL is already set up, check that it is correct
+		 * and record this info for clock_verify() to check.
+		 */
+		if (base_reg & PLL_BASE_OVRRIDE_MASK) {
+			base_reg |= PLL_ENABLE_MASK;
+			if (base_reg != readl(&pll->pll_base))
+				pllp_valid = 0;
+			return pllp_valid ? 1 : -1;
+		}
+		base_reg |= PLL_BASE_OVRRIDE_MASK;
+	}
+
+	base_reg |= PLL_BYPASS_MASK;
+	writel(base_reg, &pll->pll_base);
+
+	/* Set cpcon to PLL_MISC */
+	misc_reg = readl(&pll->pll_misc);
+	misc_reg &= ~PLL_CPCON_MASK;
+	misc_reg |= cpcon << PLL_CPCON_SHIFT;
+	writel(misc_reg, &pll->pll_misc);
+
+	/* Enable PLL */
+	base_reg |= PLL_ENABLE_MASK;
+	writel(base_reg, &pll->pll_base);
+
+	/* Disable BYPASS */
+	base_reg &= ~PLL_BYPASS_MASK;
+	writel(base_reg, &pll->pll_base);
+
+	return 0;
+}
+
+void clock_ll_start_uart(enum periph_id periph_id)
+{
+	/* Assert UART reset and enable clock */
+	reset_set_enable(periph_id, 1);
+	clock_enable(periph_id);
+	clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
+
+	/* wait for 2us */
+	udelay(2);
+
+	/* De-assert reset to UART */
+	reset_set_enable(periph_id, 0);
+}
+
+#ifdef CONFIG_OF_CONTROL
+int clock_decode_periph_id(const void *blob, int node)
+{
+	enum periph_id id;
+	u32 cell[2];
+	int err;
+
+	err = fdtdec_get_int_array(blob, node, "clocks", cell,
+				   ARRAY_SIZE(cell));
+	if (err)
+		return -1;
+	id = clk_id_to_periph_id(cell[1]);
+	assert(clock_periph_id_isvalid(id));
+	return id;
+}
+#endif /* CONFIG_OF_CONTROL */
+
+int clock_verify(void)
+{
+	struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
+	u32 reg = readl(&pll->pll_base);
+
+	if (!pllp_valid) {
+		printf("Warning: PLLP %x is not correct\n", reg);
+		return -1;
+	}
+	debug("PLLP %x is correct\n", reg);
+	return 0;
+}
+
+void clock_init(void)
+{
+	pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
+	pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
+	pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
+	pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
+	pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
+	pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
+	debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
+	debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
+	debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
+	debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
+	debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
+}
diff --git a/arch/arm/cpu/tegra-common/sys_info.c b/arch/arm/cpu/tegra-common/sys_info.c
index 1a0bb56..4632f15 100644
--- a/arch/arm/cpu/tegra-common/sys_info.c
+++ b/arch/arm/cpu/tegra-common/sys_info.c
@@ -22,12 +22,26 @@
  */
 
 #include <common.h>
+#include <linux/ctype.h>
 
 #ifdef CONFIG_DISPLAY_CPUINFO
+void upstring(char *s)
+{
+	while (*s) {
+		*s = toupper(*s);
+		s++;
+	}
+}
+
 /* Print CPU information */
 int print_cpuinfo(void)
 {
-	puts("TEGRA20\n");
+	char soc_name[10];
+
+	strncpy(soc_name, CONFIG_SYS_SOC, 10);
+	upstring(soc_name);
+	puts(soc_name);
+	puts("\n");
 
 	/* TBD: Add printf of major/minor rev info, stepping, etc. */
 	return 0;
diff --git a/arch/arm/cpu/tegra114-common/Makefile b/arch/arm/cpu/tegra114-common/Makefile
new file mode 100644
index 0000000..5b53a71
--- /dev/null
+++ b/arch/arm/cpu/tegra114-common/Makefile
@@ -0,0 +1,41 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC)-common.o
+
+COBJS-y	+= clock.o funcmux.o pinmux.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c
new file mode 100644
index 0000000..9b29ce1
--- /dev/null
+++ b/arch/arm/cpu/tegra114-common/clock.c
@@ -0,0 +1,655 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 Clock control functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+#include <div64.h>
+#include <fdtdec.h>
+
+/*
+ * Clock types that we can use as a source. The Tegra114 has muxes for the
+ * peripheral clocks, and in most cases there are four options for the clock
+ * source. This gives us a clock 'type' and exploits what commonality exists
+ * in the device.
+ *
+ * Letters are obvious, except for T which means CLK_M, and S which means the
+ * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
+ * datasheet) and PLL_M are different things. The former is the basic
+ * clock supplied to the SOC from an external oscillator. The latter is the
+ * memory clock PLL.
+ *
+ * See definitions in clock_id in the header file.
+ */
+enum clock_type_id {
+	CLOCK_TYPE_AXPT,	/* PLL_A, PLL_X, PLL_P, CLK_M */
+	CLOCK_TYPE_MCPA,	/* and so on */
+	CLOCK_TYPE_MCPT,
+	CLOCK_TYPE_PCM,
+	CLOCK_TYPE_PCMT,
+	CLOCK_TYPE_PCMT16,
+	CLOCK_TYPE_PDCT,
+	CLOCK_TYPE_ACPT,
+	CLOCK_TYPE_ASPTE,
+	CLOCK_TYPE_PMDACD2T,
+	CLOCK_TYPE_PCST,
+
+	CLOCK_TYPE_COUNT,
+	CLOCK_TYPE_NONE = -1,   /* invalid clock type */
+};
+
+enum {
+	CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
+};
+
+enum {
+	MASK_BITS_31_30	= 2,	/* num of bits used to specify clock source */
+	MASK_BITS_31_29,
+	MASK_BITS_29_28,
+};
+
+/*
+ * Clock source mux for each clock type. This just converts our enum into
+ * a list of mux sources for use by the code.
+ *
+ * Note:
+ *  The extra column in each clock source array is used to store the mask
+ *  bits in its register for the source.
+ */
+#define CLK(x) CLOCK_ID_ ## x
+static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
+	{ CLK(AUDIO),	CLK(XCPU),	CLK(PERIPH),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(AUDIO),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(NONE),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(DISPLAY),	CLK(CGENERAL),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(AUDIO),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(AUDIO),	CLK(SFROM32KHZ),	CLK(PERIPH),	CLK(OSC),
+		CLK(EPCI),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_29},
+	{ CLK(PERIPH),	CLK(MEMORY),	CLK(DISPLAY),	CLK(AUDIO),
+		CLK(CGENERAL),	CLK(DISPLAY2),	CLK(OSC),	CLK(NONE),
+		MASK_BITS_31_29},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(SFROM32KHZ),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_29_28}
+};
+
+/*
+ * Clock type for each peripheral clock source. We put the name in each
+ * record just so it is easy to match things up
+ */
+#define TYPE(name, type) type
+static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
+	/* 0x00 */
+	TYPE(PERIPHC_I2S1,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S2,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_OUT,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_IN,	CLOCK_TYPE_PCM),
+	TYPE(PERIPHC_PWM,	CLOCK_TYPE_PCST),  /* only PWM uses b29:28 */
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC2,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SBC3,	CLOCK_TYPE_PCMT),
+
+	/* 0x08 */
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_I2C1,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_I2C5,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC1,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_DISP1,	CLOCK_TYPE_PMDACD2T),
+	TYPE(PERIPHC_DISP2,	CLOCK_TYPE_PMDACD2T),
+
+	/* 0x10 */
+	TYPE(PERIPHC_CVE,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SDMMC1,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SDMMC2,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_G3D,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_G2D,	CLOCK_TYPE_MCPA),
+
+	/* 0x18 */
+	TYPE(PERIPHC_NDFLASH,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SDMMC4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_VFIR,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_EPP,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MPE,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MIPI,	CLOCK_TYPE_PCMT),	/* MIPI base-band HSI */
+	TYPE(PERIPHC_UART1,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_UART2,	CLOCK_TYPE_PCMT),
+
+	/* 0x20 */
+	TYPE(PERIPHC_HOST1X,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_TVO,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_HDMI,	CLOCK_TYPE_PMDACD2T),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_TVDAC,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_I2C2,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_EMC,	CLOCK_TYPE_MCPT),
+
+	/* 0x28 */
+	TYPE(PERIPHC_UART3,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2C3,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_SDMMC3,	CLOCK_TYPE_PCMT),
+
+	/* 0x30 */
+	TYPE(PERIPHC_UART4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_UART5,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_VDE,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_OWR,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NOR,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_CSITE,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2S0,      CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+
+	/* 0x38h */  /* Jumps to reg offset 0x3B0h */
+	TYPE(PERIPHC_G3D2,      CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MSELECT,   CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_TSENSOR,   CLOCK_TYPE_PCST),	/* s/b PCTS */
+	TYPE(PERIPHC_I2S3,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S4,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2C4,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_SBC5,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SBC6,	CLOCK_TYPE_PCMT),
+
+	/* 0x40 */
+	TYPE(PERIPHC_AUDIO,	CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_DAM0,	CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_DAM1,	CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_DAM2,	CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_ACTMON,	CLOCK_TYPE_PCST),	/* MASK 31:30 */
+	TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
+
+	/* 0x48 */
+	TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
+	TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
+	TYPE(PERIPHC_NANDSPEED,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2CSLOW,	CLOCK_TYPE_PCST),	/* MASK 31:30 */
+	TYPE(PERIPHC_SYS,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SPEEDO,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+
+	/* 0x50 */
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SATAOOB,	CLOCK_TYPE_PCMT),	/* offset 0x420h */
+	TYPE(PERIPHC_SATA,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_HDA,	CLOCK_TYPE_PCMT),
+};
+
+/*
+ * This array translates a periph_id to a periphc_internal_id
+ *
+ * Not present/matched up:
+ *	uint vi_sensor;	 _VI_SENSOR_0,		0x1A8
+ *	SPDIF - which is both 0x08 and 0x0c
+ *
+ */
+#define NONE(name) (-1)
+#define OFFSET(name, value) PERIPHC_ ## name
+static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
+	/* Low word: 31:0 */
+	NONE(CPU),
+	NONE(COP),
+	NONE(TRIGSYS),
+	NONE(RESERVED3),
+	NONE(RTC),
+	NONE(TMR),
+	PERIPHC_UART1,
+	PERIPHC_UART2,	/* and vfir 0x68 */
+
+	/* 8 */
+	NONE(GPIO),
+	PERIPHC_SDMMC2,
+	NONE(SPDIF),		/* 0x08 and 0x0c, unclear which to use */
+	PERIPHC_I2S1,
+	PERIPHC_I2C1,
+	PERIPHC_NDFLASH,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC4,
+
+	/* 16 */
+	NONE(RESERVED16),
+	PERIPHC_PWM,
+	PERIPHC_I2S2,
+	PERIPHC_EPP,
+	PERIPHC_VI,
+	PERIPHC_G2D,
+	NONE(USBD),
+	NONE(ISP),
+
+	/* 24 */
+	PERIPHC_G3D,
+	NONE(RESERVED25),
+	PERIPHC_DISP2,
+	PERIPHC_DISP1,
+	PERIPHC_HOST1X,
+	NONE(VCP),
+	PERIPHC_I2S0,
+	NONE(CACHE2),
+
+	/* Middle word: 63:32 */
+	NONE(MEM),
+	NONE(AHBDMA),
+	NONE(APBDMA),
+	NONE(RESERVED35),
+	NONE(RESERVED36),
+	NONE(STAT_MON),
+	NONE(RESERVED38),
+	NONE(RESERVED39),
+
+	/* 40 */
+	NONE(KFUSE),
+	NONE(SBC1),	/* SBC1, 0x34, is this SPI1? */
+	PERIPHC_NOR,
+	NONE(RESERVED43),
+	PERIPHC_SBC2,
+	NONE(RESERVED45),
+	PERIPHC_SBC3,
+	PERIPHC_I2C5,
+
+	/* 48 */
+	NONE(DSI),
+	PERIPHC_TVO,	/* also CVE 0x40 */
+	PERIPHC_MIPI,
+	PERIPHC_HDMI,
+	NONE(CSI),
+	PERIPHC_TVDAC,
+	PERIPHC_I2C2,
+	PERIPHC_UART3,
+
+	/* 56 */
+	NONE(RESERVED56),
+	PERIPHC_EMC,
+	NONE(USB2),
+	NONE(USB3),
+	PERIPHC_MPE,
+	PERIPHC_VDE,
+	NONE(BSEA),
+	NONE(BSEV),
+
+	/* Upper word 95:64 */
+	PERIPHC_SPEEDO,
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_I2C3,
+	PERIPHC_SBC4,
+	PERIPHC_SDMMC3,
+	NONE(PCIE),
+	PERIPHC_OWR,
+
+	/* 72 */
+	NONE(AFI),
+	PERIPHC_CSITE,
+	NONE(PCIEXCLK),
+	NONE(AVPUCQ),
+	NONE(RESERVED76),
+	NONE(RESERVED77),
+	NONE(RESERVED78),
+	NONE(DTV),
+
+	/* 80 */
+	PERIPHC_NANDSPEED,
+	PERIPHC_I2CSLOW,
+	NONE(DSIB),
+	NONE(RESERVED83),
+	NONE(IRAMA),
+	NONE(IRAMB),
+	NONE(IRAMC),
+	NONE(IRAMD),
+
+	/* 88 */
+	NONE(CRAM2),
+	NONE(RESERVED89),
+	NONE(MDOUBLER),
+	NONE(RESERVED91),
+	NONE(SUSOUT),
+	NONE(RESERVED93),
+	NONE(RESERVED94),
+	NONE(RESERVED95),
+
+	/* V word: 31:0 */
+	NONE(CPUG),
+	NONE(CPULP),
+	PERIPHC_G3D2,
+	PERIPHC_MSELECT,
+	PERIPHC_TSENSOR,
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+
+	/* 08 */
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+	PERIPHC_AUDIO,
+	NONE(APBIF),
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+
+	/* 16 */
+	NONE(ATOMICS),
+	NONE(RESERVED17),
+	NONE(RESERVED18),
+	NONE(RESERVED19),
+	NONE(RESERVED20),
+	NONE(RESERVED21),
+	NONE(RESERVED22),
+	PERIPHC_ACTMON,
+
+	/* 24 */
+	NONE(RESERVED24),
+	NONE(RESERVED25),
+	NONE(RESERVED26),
+	NONE(RESERVED27),
+	PERIPHC_SATA,
+	PERIPHC_HDA,
+	NONE(RESERVED30),
+	NONE(RESERVED31),
+
+	/* W word: 31:0 */
+	NONE(HDA2HDMICODEC),
+	NONE(RESERVED1_SATACOLD),
+	NONE(RESERVED2_PCIERX0),
+	NONE(RESERVED3_PCIERX1),
+	NONE(RESERVED4_PCIERX2),
+	NONE(RESERVED5_PCIERX3),
+	NONE(RESERVED6_PCIERX4),
+	NONE(RESERVED7_PCIERX5),
+
+	/* 40 */
+	NONE(CEC),
+	NONE(PCIE2_IOBIST),
+	NONE(EMC_IOBIST),
+	NONE(HDMI_IOBIST),
+	NONE(SATA_IOBIST),
+	NONE(MIPI_IOBIST),
+	NONE(EMC1_IOBIST),
+	NONE(XUSB),
+
+	/* 48 */
+	NONE(CILAB),
+	NONE(CILCD),
+	NONE(CILE),
+	NONE(DSIA_LP),
+	NONE(DSIB_LP),
+	NONE(RESERVED21_ENTROPY),
+	NONE(RESERVED22_W),
+	NONE(RESERVED23_W),
+
+	/* 56 */
+	NONE(RESERVED24_W),
+	NONE(AMX0),
+	NONE(ADX0),
+	NONE(DVFS),
+	NONE(XUSB_SS),
+	NONE(EMC_DLL),
+	NONE(MC1),
+	NONE(EMC1),
+};
+
+/*
+ * Get the oscillator frequency, from the corresponding hardware configuration
+ * field. Note that T30/T114 support 3 new higher freqs, but we map back
+ * to the old T20 freqs. Support for the higher oscillators is TBD.
+ */
+enum clock_osc_freq clock_get_osc_freq(void)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	reg = readl(&clkrst->crc_osc_ctrl);
+	reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+
+	if (reg & 1)				/* one of the newer freqs */
+		printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
+
+	return reg >> 2;	/* Map to most common (T20) freqs */
+}
+
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	enum periphc_internal_id internal_id;
+
+	/* Coresight is a special case */
+	if (periph_id == PERIPH_ID_CSI)
+		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
+
+	assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
+	internal_id = periph_id_to_internal_id[periph_id];
+	assert(internal_id != -1);
+	if (internal_id >= PERIPHC_VW_FIRST) {
+		internal_id -= PERIPHC_VW_FIRST;
+		return &clkrst->crc_clk_src_vw[internal_id];
+	} else
+		return &clkrst->crc_clk_src[internal_id];
+}
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id	peripheral to start
+ * @param source	PLL id of required parent clock
+ * @param mux_bits	Set to number of bits in mux register: 2 or 4
+ * @param divider_bits Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+	enum clock_id parent, int *mux_bits, int *divider_bits)
+{
+	enum clock_type_id type;
+	enum periphc_internal_id internal_id;
+	int mux;
+
+	assert(clock_periph_id_isvalid(periph_id));
+
+	internal_id = periph_id_to_internal_id[periph_id];
+	assert(periphc_internal_id_isvalid(internal_id));
+
+	type = clock_periph_type[internal_id];
+	assert(clock_type_id_isvalid(type));
+
+	*mux_bits = clock_source[type][CLOCK_MAX_MUX];
+
+	if (type == CLOCK_TYPE_PCMT16)
+		*divider_bits = 16;
+	else
+		*divider_bits = 8;
+
+	for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
+		if (clock_source[type][mux] == parent)
+			return mux;
+
+	/* if we get here, either us or the caller has made a mistake */
+	printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
+		parent);
+	return -1;
+}
+
+void clock_set_enable(enum periph_id periph_id, int enable)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 *clk;
+	u32 reg;
+
+	/* Enable/disable the clock to this peripheral */
+	assert(clock_periph_id_isvalid(periph_id));
+	if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
+		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+	else
+		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
+	reg = readl(clk);
+	if (enable)
+		reg |= PERIPH_MASK(periph_id);
+	else
+		reg &= ~PERIPH_MASK(periph_id);
+	writel(reg, clk);
+}
+
+void reset_set_enable(enum periph_id periph_id, int enable)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 *reset;
+	u32 reg;
+
+	/* Enable/disable reset to the peripheral */
+	assert(clock_periph_id_isvalid(periph_id));
+	if (periph_id < PERIPH_ID_VW_FIRST)
+		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+	else
+		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
+	reg = readl(reset);
+	if (enable)
+		reg |= PERIPH_MASK(periph_id);
+	else
+		reg &= ~PERIPH_MASK(periph_id);
+	writel(reg, reset);
+}
+
+#ifdef CONFIG_OF_CONTROL
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id    Clock ID according to tegra114 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id)
+{
+	if (clk_id > PERIPH_ID_COUNT)
+		return PERIPH_ID_NONE;
+
+	switch (clk_id) {
+	case PERIPH_ID_RESERVED3:
+	case PERIPH_ID_RESERVED16:
+	case PERIPH_ID_RESERVED24:
+	case PERIPH_ID_RESERVED35:
+	case PERIPH_ID_RESERVED43:
+	case PERIPH_ID_RESERVED45:
+	case PERIPH_ID_RESERVED56:
+	case PERIPH_ID_RESERVED76:
+	case PERIPH_ID_RESERVED77:
+	case PERIPH_ID_RESERVED78:
+	case PERIPH_ID_RESERVED83:
+	case PERIPH_ID_RESERVED89:
+	case PERIPH_ID_RESERVED91:
+	case PERIPH_ID_RESERVED93:
+	case PERIPH_ID_RESERVED94:
+	case PERIPH_ID_RESERVED95:
+		return PERIPH_ID_NONE;
+	default:
+		return clk_id;
+	}
+}
+#endif /* CONFIG_OF_CONTROL */
+
+void clock_early_init(void)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+	/*
+	 * PLLP output frequency set to 408Mhz
+	 * PLLC output frequency set to 600Mhz
+	 * PLLD output frequency set to 925Mhz
+	 */
+	switch (clock_get_osc_freq()) {
+	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
+		clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
+		break;
+
+	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+		clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
+		break;
+
+	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+		clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
+		break;
+	case CLOCK_OSC_FREQ_19_2:
+	default:
+		/*
+		 * These are not supported. It is too early to print a
+		 * message and the UART likely won't work anyway due to the
+		 * oscillator being wrong.
+		 */
+		break;
+	}
+
+	/* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
+	writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
+
+	/* PLLC_MISC: Set LOCK_ENABLE */
+	writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc);
+	udelay(2);
+
+	/* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
+	writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
+	udelay(2);
+}
diff --git a/arch/arm/cpu/tegra114-common/funcmux.c b/arch/arm/cpu/tegra114-common/funcmux.c
new file mode 100644
index 0000000..5af7550
--- /dev/null
+++ b/arch/arm/cpu/tegra114-common/funcmux.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 high-level function multiplexing */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+
+int funcmux_select(enum periph_id id, int config)
+{
+	int bad_config = config != FUNCMUX_DEFAULT;
+
+	switch (id) {
+	case PERIPH_ID_UART4:
+		switch (config) {
+		case FUNCMUX_UART4_GMI:
+			pinmux_set_func(PINGRP_GMI_A16, PMUX_FUNC_UARTD);
+			pinmux_set_func(PINGRP_GMI_A17, PMUX_FUNC_UARTD);
+			pinmux_set_func(PINGRP_GMI_A18, PMUX_FUNC_UARTD);
+			pinmux_set_func(PINGRP_GMI_A19, PMUX_FUNC_UARTD);
+
+			pinmux_set_io(PINGRP_GMI_A16, PMUX_PIN_OUTPUT);
+			pinmux_set_io(PINGRP_GMI_A17, PMUX_PIN_INPUT);
+			pinmux_set_io(PINGRP_GMI_A18, PMUX_PIN_INPUT);
+			pinmux_set_io(PINGRP_GMI_A19, PMUX_PIN_OUTPUT);
+
+			pinmux_tristate_disable(PINGRP_GMI_A16);
+			pinmux_tristate_disable(PINGRP_GMI_A17);
+			pinmux_tristate_disable(PINGRP_GMI_A18);
+			pinmux_tristate_disable(PINGRP_GMI_A19);
+			break;
+		}
+		break;
+
+	/* Add other periph IDs here as needed */
+
+	default:
+		debug("%s: invalid periph_id %d", __func__, id);
+		return -1;
+	}
+
+	if (bad_config) {
+		debug("%s: invalid config %d for periph_id %d", __func__,
+		      config, id);
+		return -1;
+	}
+	return 0;
+}
diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c
new file mode 100644
index 0000000..52b3ec4
--- /dev/null
+++ b/arch/arm/cpu/tegra114-common/pinmux.c
@@ -0,0 +1,506 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 pin multiplexing functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/pinmux.h>
+
+struct tegra_pingroup_desc {
+	const char *name;
+	enum pmux_func funcs[4];
+	enum pmux_func func_safe;
+	enum pmux_vddio vddio;
+	enum pmux_pin_io io;
+};
+
+#define PMUX_MUXCTL_SHIFT	0
+#define PMUX_PULL_SHIFT		2
+#define PMUX_TRISTATE_SHIFT	4
+#define PMUX_TRISTATE_MASK	(1 << PMUX_TRISTATE_SHIFT)
+#define PMUX_IO_SHIFT		5
+#define PMUX_OD_SHIFT		6
+#define PMUX_LOCK_SHIFT		7
+#define PMUX_IO_RESET_SHIFT	8
+
+/* Convenient macro for defining pin group properties */
+#define PIN(pg_name, vdd, f0, f1, f2, f3, iod)	\
+	{						\
+		.vddio = PMUX_VDDIO_ ## vdd,		\
+		.funcs = {				\
+			PMUX_FUNC_ ## f0,		\
+			PMUX_FUNC_ ## f1,		\
+			PMUX_FUNC_ ## f2,		\
+			PMUX_FUNC_ ## f3,		\
+		},					\
+		.func_safe = PMUX_FUNC_RSVD1,		\
+		.io = PMUX_PIN_ ## iod,			\
+	}
+
+/* Input and output pins */
+#define PINI(pg_name, vdd, f0, f1, f2, f3) \
+	PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
+#define PINO(pg_name, vdd, f0, f1, f2, f3) \
+	PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
+
+const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
+	/*	NAME	  VDD	   f0		f1	   f2	    f3  */
+	PINI(ULPI_DATA0,  BB,	   SPI3,       HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA1,  BB,	   SPI3,       HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA2,  BB,	   SPI3,       HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA3,  BB,	   SPI3,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA4,  BB,	   SPI2,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA5,  BB,      SPI2,        HSI,       UARTA,   ULPI),
+	PINI(ULPI_DATA6,  BB,      SPI2,        HSI,       UARTA,   ULPI),
+	PINI(ULPI_DATA7,  BB,      SPI2,        HSI,       UARTA,   ULPI),
+	PINI(ULPI_CLK,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
+	PINI(ULPI_DIR,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
+	PINI(ULPI_NXT,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
+	PINI(ULPI_STP,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
+	PINI(DAP3_FS,     BB,      I2S2,       SPI5,       DISPA,   DISPB),
+	PINI(DAP3_DIN,    BB,      I2S2,       SPI5,       DISPA,   DISPB),
+	PINI(DAP3_DOUT,   BB,      I2S2,       SPI5,       DISPA,   DISPB),
+	PINI(DAP3_SCLK,   BB,      I2S2,       SPI5,       DISPA,   DISPB),
+	PINI(GPIO_PV0,    BB,      USB,        RSVD2,      RSVD3,   RSVD4),
+	PINI(GPIO_PV1,    BB,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(SDMMC1_CLK,  SDMMC1,  SDMMC1,     CLK12,      RSVD3,   RSVD4),
+	PINI(SDMMC1_CMD,  SDMMC1,  SDMMC1,     SPDIF,      SPI4,    UARTA),
+	PINI(SDMMC1_DAT3, SDMMC1,  SDMMC1,     SPDIF,      SPI4,    UARTA),
+	PINI(SDMMC1_DAT2, SDMMC1,  SDMMC1,     PWM0,       SPI4,    UARTA),
+	PINI(SDMMC1_DAT1, SDMMC1,  SDMMC1,     PWM1,       SPI4,    UARTA),
+	PINI(SDMMC1_DAT0, SDMMC1,  SDMMC1,     RSVD2,      SPI4,    UARTA),
+	PINI(GPIO_PV2,    BB,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(GPIO_PV3,    BB,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(CLK2_OUT,    SDMMC1,  EXTPERIPH2, RSVD2,      RSVD3,   RSVD4),
+	PINI(CLK2_REQ,    SDMMC1,  DAP,        RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_PWR1,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_PWR2,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_SDIN,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_SDOUT,   LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_WR_N,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_CS0_N,   LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_DC0,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_SCK,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_PWR0,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_PCLK,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_DE,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_HSYNC,   LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_VSYNC,   LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D0,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D1,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D2,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D3,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D4,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D5,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D6,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D7,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D8,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D9,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D10,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D11,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D12,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D13,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D14,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D15,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D16,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D17,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D18,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D19,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D20,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D21,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D22,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_D23,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_CS1_N,   LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_M1,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINO(LCD_DC1,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(HDMI_INT,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(DDC_SCL,     LCD,     I2C4,       RSVD2,      RSVD3,   RSVD4),
+	PINI(DDC_SDA,     LCD,     I2C4,       RSVD2,      RSVD3,   RSVD4),
+	PINI(CRT_HSYNC,   LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(CRT_VSYNC,   LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(VI_D0,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(VI_D1,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(VI_D2,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(VI_D3,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(VI_D4,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(VI_D5,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(VI_D6,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(VI_D7,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(VI_D8,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(VI_D9,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(VI_D10,      VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(VI_D11,      VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(VI_PCLK,     VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(VI_MCLK,     VI,      RSVD1,      RSVD3,      RSVD3,   RSVD4),
+	PINI(VI_VSYNC,    VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(VI_HSYNC,    VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(UART2_RXD,   UART,    UARTB,      SPDIF,      UARTA,   SPI4),
+	PINI(UART2_TXD,   UART,    UARTB,      SPDIF,      UARTA,   SPI4),
+	PINI(UART2_RTS_N, UART,    UARTA,      UARTB,      RSVD3,   SPI4),
+	PINI(UART2_CTS_N, UART,    UARTA,      UARTB,      RSVD3,   SPI4),
+	PINI(UART3_TXD,   UART,    UARTC,      RSVD2,      RSVD3,   SPI4),
+	PINI(UART3_RXD,   UART,    UARTC,      RSVD2,      RSVD3,   SPI4),
+	PINI(UART3_CTS_N, UART,    UARTC,      SDMMC1,     DTV,     SPI4),
+	PINI(UART3_RTS_N, UART,    UARTC,      PWM0,       DTV,     DISPA),
+	PINI(GPIO_PU0,    UART,    OWR,        UARTA,      RSVD3,   RSVD4),
+	PINI(GPIO_PU1,    UART,    RSVD1,      UARTA,      RSVD3,   RSVD4),
+	PINI(GPIO_PU2,    UART,    RSVD1,      UARTA,      RSVD3,   RSVD4),
+	PINI(GPIO_PU3,    UART,    PWM0,       UARTA,      DISPA,   DISPB),
+	PINI(GPIO_PU4,    UART,    PWM1,       UARTA,      DISPA,   DISPB),
+	PINI(GPIO_PU5,    UART,    PWM2,       UARTA,      DISPA,   DISPB),
+	PINI(GPIO_PU6,    UART,    PWM3,       UARTA,      USB,     DISPB),
+	PINI(GEN1_I2C_SDA, UART,   I2C1,       RSVD2,      RSVD3,   RSVD4),
+	PINI(GEN1_I2C_SCL, UART,   I2C1,       RSVD2,      RSVD3,   RSVD4),
+	PINI(DAP4_FS,     UART,    I2S3,       RSVD2,      DTV,     RSVD4),
+	PINI(DAP4_DIN,    UART,    I2S3,       RSVD2,      RSVD3,   RSVD4),
+	PINI(DAP4_DOUT,   UART,    I2S3,       RSVD2,      DTV,     RSVD4),
+	PINI(DAP4_SCLK,   UART,    I2S3,       RSVD2,      RSVD3,   RSVD4),
+	PINI(CLK3_OUT,    UART,    EXTPERIPH3, RSVD2,      RSVD3,   RSVD4),
+	PINI(CLK3_REQ,    UART,    DEV3,       RSVD2,      RSVD3,   RSVD4),
+	PINI(GMI_WP_N,    GMI,     RSVD1,      NAND,       GMI,     GMI_ALT),
+	PINI(GMI_IORDY,   GMI,     SDMMC2,     RSVD2,      GMI,     TRACE),
+	PINI(GMI_WAIT,    GMI,     SPI4,       NAND,       GMI,     DTV),
+	PINI(GMI_ADV_N,   GMI,     RSVD1,      NAND,       GMI,     TRACE),
+	PINI(GMI_CLK,     GMI,     SDMMC2,     NAND,       GMI,     TRACE),
+	PINI(GMI_CS0_N,   GMI,     RSVD1,      NAND,       GMI,     USB),
+	PINI(GMI_CS1_N,   GMI,     RSVD1,      NAND,       GMI,     SOC),
+	PINI(GMI_CS2_N,   GMI,     SDMMC2,     NAND,       GMI,     TRACE),
+	PINI(GMI_CS3_N,   GMI,     SDMMC2,     NAND,       GMI,     GMI_ALT),
+	PINI(GMI_CS4_N,   GMI,     USB,        NAND,       GMI,     TRACE),
+	PINI(GMI_CS6_N,   GMI,     NAND,       NAND_ALT,   GMI,     SPI4),
+	PINI(GMI_CS7_N,   GMI,     NAND,       NAND_ALT,   GMI,     SDMMC2),
+	PINI(GMI_AD0,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+	PINI(GMI_AD1,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+	PINI(GMI_AD2,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+	PINI(GMI_AD3,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+	PINI(GMI_AD4,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+	PINI(GMI_AD5,     GMI,     RSVD1,      NAND,       GMI,     SPI4),
+	PINI(GMI_AD6,     GMI,     RSVD1,      NAND,       GMI,     SPI4),
+	PINI(GMI_AD7,     GMI,     RSVD1,      NAND,       GMI,     SPI4),
+	PINI(GMI_AD8,     GMI,     PWM0,       NAND,       GMI,     DTV),
+	PINI(GMI_AD9,     GMI,     PWM1,       NAND,       GMI,     CLDVFS),
+	PINI(GMI_AD10,    GMI,     PWM2,       NAND,       GMI,     CLDVFS),
+	PINI(GMI_AD11,    GMI,     PWM3,       NAND,       GMI,     USB),
+	PINI(GMI_AD12,    GMI,     SDMMC2,     NAND,       GMI,     RSVD4),
+	PINI(GMI_AD13,    GMI,     SDMMC2,     NAND,       GMI,     RSVD4),
+	PINI(GMI_AD14,    GMI,     SDMMC2,     NAND,       GMI,     DTV),
+	PINI(GMI_AD15,    GMI,     SDMMC2,     NAND,       GMI,     DTV),
+	PINI(GMI_A16,     GMI,     UARTD,      TRACE,      GMI,     GMI_ALT),
+	PINI(GMI_A17,     GMI,     UARTD,      RSVD2,      GMI,     TRACE),
+	PINI(GMI_A18,     GMI,     UARTD,      RSVD2,      GMI,     TRACE),
+	PINI(GMI_A19,     GMI,     UARTD,      SPI4,       GMI,     TRACE),
+	PINI(GMI_WR_N,    GMI,     RSVD1,      NAND,       GMI,     SPI4),
+	PINI(GMI_OE_N,    GMI,     RSVD1,      NAND,       GMI,     SOC),
+	PINI(GMI_DQS,     GMI,     SDMMC2,     NAND,       GMI,     TRACE),
+	PINI(GMI_RST_N,   GMI,     NAND,       NAND_ALT,   GMI,     RSVD4),
+	PINI(GEN2_I2C_SCL, GMI,    I2C2,       RSVD2,      GMI,     RSVD4),
+	PINI(GEN2_I2C_SDA, GMI,    I2C2,       RSVD2,      GMI,     RSVD4),
+	PINI(SDMMC4_CLK,  SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
+	PINI(SDMMC4_CMD,  SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
+	PINI(SDMMC4_DAT0, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT1, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT2, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT3, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT4, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT5, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT6, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT7, SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
+	PINI(SDMMC4_RST_N, SDMMC4, RSVD1,      RSVD2,      RSVD3,   SDMMC4),
+	PINI(CAM_MCLK,    CAM,     VI,         VI_ALT1,    VI_ALT2, RSVD4),
+	PINI(GPIO_PCC1,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
+	PINI(GPIO_PBB0,   CAM,     I2S4,       VI,         VI_ALT1, VI_ALT3),
+	PINI(CAM_I2C_SCL, CAM,     VGP1,       I2C3,       RSVD3,   RSVD4),
+	PINI(CAM_I2C_SDA, CAM,     VGP2,       I2C3,       RSVD3,   RSVD4),
+	PINI(GPIO_PBB3,   CAM,     VGP3,       DISPA,      DISPB,   RSVD4),
+	PINI(GPIO_PBB4,   CAM,     VGP4,       DISPA,      DISPB,   RSVD4),
+	PINI(GPIO_PBB5,   CAM,     VGP5,       DISPA,      DISPB,   RSVD4),
+	PINI(GPIO_PBB6,   CAM,     VGP6,       DISPA,      DISPB,   RSVD4),
+	PINI(GPIO_PBB7,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
+	PINI(GPIO_PCC2,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
+	PINI(JTAG_RTCK,   SYS,     RTCK,       RSVD2,      RSVD3,   RSVD4),
+	PINI(PWR_I2C_SCL, SYS,     I2CPWR,     RSVD2,      RSVD3,   RSVD4),
+	PINI(PWR_I2C_SDA, SYS,     I2CPWR,     RSVD2,      RSVD3,   RSVD4),
+	PINI(KB_ROW0,     SYS,     KBC,        RSVD2,      DTV,     RSVD4),
+	PINI(KB_ROW1,     SYS,     KBC,        RSVD2,      DTV,     RSVD4),
+	PINI(KB_ROW2,     SYS,     KBC,        RSVD2,      DTV,     SOC),
+	PINI(KB_ROW3,     SYS,     KBC,        DISPA,      RSVD3,   DISPB),
+	PINI(KB_ROW4,     SYS,     KBC,        DISPA,      SPI2,    DISPB),
+	PINI(KB_ROW5,     SYS,     KBC,        DISPA,      SPI2,    DISPB),
+	PINI(KB_ROW6,     SYS,     KBC,        DISPA,      RSVD3,   DISPB),
+	PINI(KB_ROW7,     SYS,     KBC,        RSVD2,      CLDVFS,  UARTA),
+	PINI(KB_ROW8,     SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
+	PINI(KB_ROW9,     SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
+	PINI(KB_ROW10,    SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
+	PINI(KB_ROW11,    SYS,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(KB_ROW12,    SYS,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(KB_ROW13,    SYS,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(KB_ROW14,    SYS,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(KB_ROW15,    SYS,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(KB_COL0,     SYS,     KBC,        USB,        SPI2,    EMC_DLL),
+	PINI(KB_COL1,     SYS,     KBC,        RSVD2,      SPI2,    EMC_DLL),
+	PINI(KB_COL2,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
+	PINI(KB_COL3,     SYS,     KBC,        DISPA,      PWM2,    UARTA),
+	PINI(KB_COL4,     SYS,     KBC,        OWR,        SDMMC3,  UARTA),
+	PINI(KB_COL5,     SYS,     KBC,        RSVD2,      SDMMC1,  RSVD4),
+	PINI(KB_COL6,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
+	PINI(KB_COL7,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
+	PINI(CLK_32K_OUT, SYS,     BLINK,      SOC,        RSVD3,   RSVD4),
+	PINI(SYS_CLK_REQ, SYS,     SYSCLK,     RSVD2,      RSVD3,   RSVD4),
+	PINI(CORE_PWR_REQ, SYS,    PWRON,      RSVD2,      RSVD3,   RSVD4),
+	PINI(CPU_PWR_REQ, SYS,     CPU,        RSVD2,      RSVD3,   RSVD4),
+	PINI(PWR_INT_N,   SYS,     PMI,        RSVD2,      RSVD3,   RSVD4),
+	PINI(CLK_32K_IN,  SYS,     CLK,        RSVD2,      RSVD3,   RSVD4),
+	PINI(OWR,         SYS,     OWR,        RSVD2,      RSVD3,   RSVD4),
+	PINI(DAP1_FS,     AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
+	PINI(DAP1_DIN,    AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
+	PINI(DAP1_DOUT,   AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
+	PINI(DAP1_SCLK,   AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
+	PINI(CLK1_REQ,    AUDIO,   DAP,        DAP1,       RSVD3,   RSVD4),
+	PINI(CLK1_OUT,    AUDIO,   EXTPERIPH1, DAP2,       RSVD3,   RSVD4),
+	PINI(SPDIF_IN,    AUDIO,   SPDIF,      USB,        RSVD3,   RSVD4),
+	PINI(SPDIF_OUT,   AUDIO,   SPDIF,      RSVD2,      RSVD3,   RSVD4),
+	PINI(DAP2_FS,     AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
+	PINI(DAP2_DIN,    AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
+	PINI(DAP2_DOUT,   AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
+	PINI(DAP2_SCLK,   AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
+	PINI(SPI2_MOSI,   AUDIO,   SPI6,       CLDVFS,     RSVD3,   RSVD4),
+	PINI(SPI2_MISO,   AUDIO,   SPI6,       RSVD2,      RSVD3,   RSVD4),
+	PINI(SPI2_CS0_N,  AUDIO,   SPI6,       SPI1,       RSVD3,   RSVD4),
+	PINI(SPI2_SCK,    AUDIO,   SPI6,       CLDVFS,     RSVD3,   RSVD4),
+	PINI(SPI1_MOSI,   AUDIO,   RSVD1,      SPI1,       SPI2,    DAP2),
+	PINI(SPI1_SCK,    AUDIO,   RSVD1,      SPI1,       SPI2,    RSVD4),
+	PINI(SPI1_CS0_N,  AUDIO,   SPI6,       SPI1,       SPI2,    RSVD4),
+	PINI(SPI1_MISO,   AUDIO,   RSVD1,      SPI1,       SPI2,    RSVD4),
+	PINI(SPI2_CS1_N,  AUDIO,   RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(SPI2_CS2_N,  AUDIO,   RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(SDMMC3_CLK,  SDMMC3,  SDMMC3,     RSVD2,      RSVD3,   SPI3),
+	PINI(SDMMC3_CMD,  SDMMC3,  SDMMC3,     PWM3,       UARTA,   SPI3),
+	PINI(SDMMC3_DAT0, SDMMC3,  SDMMC3,     RSVD2,      RSVD3,   SPI3),
+	PINI(SDMMC3_DAT1, SDMMC3,  SDMMC3,     PWM2,       UARTA,   SPI3),
+	PINI(SDMMC3_DAT2, SDMMC3,  SDMMC3,     PWM1,       DISPA,   SPI3),
+	PINI(SDMMC3_DAT3, SDMMC3,  SDMMC3,     PWM0,       DISPB,   SPI3),
+	PINI(SDMMC3_DAT4, SDMMC3,  RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(SDMMC3_DAT5, SDMMC3,  RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(SDMMC3_DAT6, SDMMC3,  RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(SDMMC3_DAT7, SDMMC3,  RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(HDMI_CEC,    SYS,     CEC,        SDMMC3,     RSVD3,   SOC),
+	PINI(SDMMC1_WP_N, SDMMC1,  SDMMC1,     CLK12,      SPI4,    UARTA),
+	PINI(SDMMC3_CD_N, SDMMC3,  SDMMC3,     OWR,        RSVD3,   RSVD4),
+	PINI(SPI1_CS1_N,  AUDIO,   SPI6,       RSVD2,      SPI2,    I2C1),
+	PINI(SPI1_CS2_N,  AUDIO,   SPI6,       SPI1,       SPI2,    I2C1),
+	PINI(USB_VBUS_EN0, SYS,    USB,        RSVD2,      RSVD3,   RSVD4),
+	PINI(USB_VBUS_EN1, SYS,    USB,        RSVD2,      RSVD3,   RSVD4),
+	PINI(SDMMC3_CLK_LB_IN,  SDMMC3, SDMMC3, RSVD2,     RSVD3,   RSVD4),
+	PINO(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2,     RSVD3,   RSVD4),
+	PINO(NAND_GMI_CLK_LB,   GMI,    SDMMC2, NAND,      GMI,     RSVD4),
+	PINO(RESET_OUT_N, SYS,     RSVD1,      RSVD2,      RSVD3, RESET_OUT_N),
+};
+
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *tri = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin */
+	assert(pmux_pingrp_isvalid(pin));
+
+	reg = readl(tri);
+	if (enable)
+		reg |= PMUX_TRISTATE_MASK;
+	else
+		reg &= ~PMUX_TRISTATE_MASK;
+	writel(reg, tri);
+}
+
+void pinmux_tristate_enable(enum pmux_pingrp pin)
+{
+	pinmux_set_tristate(pin, 1);
+}
+
+void pinmux_tristate_disable(enum pmux_pingrp pin)
+{
+	pinmux_set_tristate(pin, 0);
+}
+
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pull = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and pupd */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_pupd_isvalid(pupd));
+
+	reg = readl(pull);
+	reg &= ~(0x3 << PMUX_PULL_SHIFT);
+	reg |= (pupd << PMUX_PULL_SHIFT);
+	writel(reg, pull);
+}
+
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *muxctl = &pmt->pmt_ctl[pin];
+	int i, mux = -1;
+	u32 reg;
+
+	/* Error check on pin and func */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_func_isvalid(func));
+
+	/* Handle special values */
+	if (func == PMUX_FUNC_SAFE)
+		func = tegra_soc_pingroups[pin].func_safe;
+
+	if (func & PMUX_FUNC_RSVD1) {
+		mux = func & 0x3;
+	} else {
+		/* Search for the appropriate function */
+		for (i = 0; i < 4; i++) {
+			if (tegra_soc_pingroups[pin].funcs[i] == func) {
+				mux = i;
+				break;
+			}
+		}
+	}
+	assert(mux != -1);
+
+	reg = readl(muxctl);
+	reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
+	reg |= (mux << PMUX_MUXCTL_SHIFT);
+	writel(reg, muxctl);
+
+}
+
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_io = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and io */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_io_isvalid(io));
+
+	reg = readl(pin_io);
+	reg &= ~(0x1 << PMUX_IO_SHIFT);
+	reg |= (io & 0x1) << PMUX_IO_SHIFT;
+	writel(reg, pin_io);
+}
+
+static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_lock = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and lock */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_lock_isvalid(lock));
+
+	if (lock == PMUX_PIN_LOCK_DEFAULT)
+		return 0;
+
+	reg = readl(pin_lock);
+	reg &= ~(0x1 << PMUX_LOCK_SHIFT);
+	if (lock == PMUX_PIN_LOCK_ENABLE)
+		reg |= (0x1 << PMUX_LOCK_SHIFT);
+	else {
+		/* lock == DISABLE, which isn't possible */
+		printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
+			__func__, lock);
+	}
+	writel(reg, pin_lock);
+
+	return 0;
+}
+
+static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_od = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and od */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_od_isvalid(od));
+
+	if (od == PMUX_PIN_OD_DEFAULT)
+		return 0;
+
+	reg = readl(pin_od);
+	reg &= ~(0x1 << PMUX_OD_SHIFT);
+	if (od == PMUX_PIN_OD_ENABLE)
+		reg |= (0x1 << PMUX_OD_SHIFT);
+	writel(reg, pin_od);
+
+	return 0;
+}
+
+static int pinmux_set_ioreset(enum pmux_pingrp pin,
+				enum pmux_pin_ioreset ioreset)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_ioreset = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and ioreset */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_ioreset_isvalid(ioreset));
+
+	if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
+		return 0;
+
+	reg = readl(pin_ioreset);
+	reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
+	if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
+		reg |= (0x1 << PMUX_IO_RESET_SHIFT);
+	writel(reg, pin_ioreset);
+
+	return 0;
+}
+
+void pinmux_config_pingroup(struct pingroup_config *config)
+{
+	enum pmux_pingrp pin = config->pingroup;
+
+	pinmux_set_func(pin, config->func);
+	pinmux_set_pullupdown(pin, config->pull);
+	pinmux_set_tristate(pin, config->tristate);
+	pinmux_set_io(pin, config->io);
+	pinmux_set_lock(pin, config->lock);
+	pinmux_set_od(pin, config->od);
+	pinmux_set_ioreset(pin, config->ioreset);
+}
+
+void pinmux_config_table(struct pingroup_config *config, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		pinmux_config_pingroup(&config[i]);
+}
diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra20-common/clock.c
index 12987a6..ec93894 100644
--- a/arch/arm/cpu/tegra20-common/clock.c
+++ b/arch/arm/cpu/tegra20-common/clock.c
@@ -31,24 +31,6 @@
 #include <fdtdec.h>
 
 /*
- * This is our record of the current clock rate of each clock. We don't
- * fill all of these in since we are only really interested in clocks which
- * we use as parents.
- */
-static unsigned pll_rate[CLOCK_ID_COUNT];
-
-/*
- * The oscillator frequency is fixed to one of four set values. Based on this
- * the other clocks are set up appropriately.
- */
-static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
-	13000000,
-	19200000,
-	12000000,
-	26000000,
-};
-
-/*
  * Clock types that we can use as a source. The Tegra20 has muxes for the
  * peripheral clocks, and in most cases there are four options for the clock
  * source. This gives us a clock 'type' and exploits what commonality exists
@@ -76,12 +58,6 @@
 	CLOCK_TYPE_NONE = -1,	/* invalid clock type */
 };
 
-/* return 1 if a peripheral ID is in range */
-#define clock_type_id_isvalid(id) ((id) >= 0 && \
-		(id) < CLOCK_TYPE_COUNT)
-
-char pllp_valid = 1;	/* PLLP is set up correctly */
-
 enum {
 	CLOCK_MAX_MUX	= 4	/* number of source options for each clock */
 };
@@ -192,10 +168,6 @@
 	PERIPHC_NONE = -1,
 };
 
-/* return 1 if a periphc_internal_id is in range */
-#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
-		(id) < PERIPHC_COUNT)
-
 /*
  * Clock type for each peripheral clock source. We put the name in each
  * record just so it is easy to match things up
@@ -396,19 +368,9 @@
 	NONE(CRAM2),
 };
 
-/* number of clock outputs of a PLL */
-static const u8 pll_num_clkouts[] = {
-	1,	/* PLLC */
-	1,	/* PLLM */
-	4,	/* PLLP */
-	1,	/* PLLA */
-	0,	/* PLLU */
-	0,	/* PLLD */
-};
-
 /*
  * Get the oscillator frequency, from the corresponding hardware configuration
- * field.
+ * field. T20 has 4 frequencies that it supports.
  */
 enum clock_osc_freq clock_get_osc_freq(void)
 {
@@ -420,110 +382,8 @@
 	return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
 }
 
-int clock_get_osc_bypass(void)
-{
-	struct clk_rst_ctlr *clkrst =
-			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	u32 reg;
-
-	reg = readl(&clkrst->crc_osc_ctrl);
-	return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
-}
-
-/* Returns a pointer to the registers of the given pll */
-static struct clk_pll *get_pll(enum clock_id clkid)
-{
-	struct clk_rst_ctlr *clkrst =
-			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-
-	assert(clock_id_is_pll(clkid));
-	return &clkrst->crc_pll[clkid];
-}
-
-int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
-		u32 *divp, u32 *cpcon, u32 *lfcon)
-{
-	struct clk_pll *pll = get_pll(clkid);
-	u32 data;
-
-	assert(clkid != CLOCK_ID_USB);
-
-	/* Safety check, adds to code size but is small */
-	if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
-		return -1;
-	data = readl(&pll->pll_base);
-	*divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
-	*divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT;
-	*divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
-	data = readl(&pll->pll_misc);
-	*cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
-	*lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
-
-	return 0;
-}
-
-unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
-		u32 divp, u32 cpcon, u32 lfcon)
-{
-	struct clk_pll *pll = get_pll(clkid);
-	u32 data;
-
-	/*
-	 * We cheat by treating all PLL (except PLLU) in the same fashion.
-	 * This works only because:
-	 * - same fields are always mapped at same offsets, except DCCON
-	 * - DCCON is always 0, doesn't conflict
-	 * - M,N, P of PLLP values are ignored for PLLP
-	 */
-	data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
-	writel(data, &pll->pll_misc);
-
-	data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
-			(0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
-
-	if (clkid == CLOCK_ID_USB)
-		data |= divp << PLLU_VCO_FREQ_SHIFT;
-	else
-		data |= divp << PLL_DIVP_SHIFT;
-	writel(data, &pll->pll_base);
-
-	/* calculate the stable time */
-	return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
-}
-
-/* return 1 if a peripheral ID is in range and valid */
-static int clock_periph_id_isvalid(enum periph_id id)
-{
-	if (id < PERIPH_ID_FIRST || id >= PERIPH_ID_COUNT)
-		printf("Peripheral id %d out of range\n", id);
-	else {
-		switch (id) {
-		case PERIPH_ID_RESERVED1:
-		case PERIPH_ID_RESERVED2:
-		case PERIPH_ID_RESERVED30:
-		case PERIPH_ID_RESERVED35:
-		case PERIPH_ID_RESERVED56:
-		case PERIPH_ID_RESERVED74:
-		case PERIPH_ID_RESERVED76:
-		case PERIPH_ID_RESERVED77:
-		case PERIPH_ID_RESERVED78:
-		case PERIPH_ID_RESERVED79:
-		case PERIPH_ID_RESERVED80:
-		case PERIPH_ID_RESERVED81:
-		case PERIPH_ID_RESERVED82:
-		case PERIPH_ID_RESERVED83:
-		case PERIPH_ID_RESERVED91:
-			printf("Peripheral id %d is reserved\n", id);
-			break;
-		default:
-			return 1;
-		}
-	}
-	return 0;
-}
-
 /* Returns a pointer to the clock source register for a peripheral */
-static u32 *get_periph_source_reg(enum periph_id periph_id)
+u32 *get_periph_source_reg(enum periph_id periph_id)
 {
 	struct clk_rst_ctlr *clkrst =
 			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
@@ -535,154 +395,6 @@
 	return &clkrst->crc_clk_src[internal_id];
 }
 
-void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
-			      unsigned divisor)
-{
-	u32 *reg = get_periph_source_reg(periph_id);
-	u32 value;
-
-	value = readl(reg);
-
-	value &= ~OUT_CLK_SOURCE_MASK;
-	value |= source << OUT_CLK_SOURCE_SHIFT;
-
-	value &= ~OUT_CLK_DIVISOR_MASK;
-	value |= divisor << OUT_CLK_DIVISOR_SHIFT;
-
-	writel(value, reg);
-}
-
-void clock_ll_set_source(enum periph_id periph_id, unsigned source)
-{
-	u32 *reg = get_periph_source_reg(periph_id);
-
-	clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
-			source << OUT_CLK_SOURCE_SHIFT);
-}
-
-/**
- * Given the parent's rate and the required rate for the children, this works
- * out the peripheral clock divider to use, in 7.1 binary format.
- *
- * @param divider_bits	number of divider bits (8 or 16)
- * @param parent_rate	clock rate of parent clock in Hz
- * @param rate		required clock rate for this clock
- * @return divider which should be used
- */
-static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
-			   unsigned long rate)
-{
-	u64 divider = parent_rate * 2;
-	unsigned max_divider = 1 << divider_bits;
-
-	divider += rate - 1;
-	do_div(divider, rate);
-
-	if ((s64)divider - 2 < 0)
-		return 0;
-
-	if ((s64)divider - 2 >= max_divider)
-		return -1;
-
-	return divider - 2;
-}
-
-/**
- * Given the parent's rate and the divider in 7.1 format, this works out the
- * resulting peripheral clock rate.
- *
- * @param parent_rate	clock rate of parent clock in Hz
- * @param divider which should be used in 7.1 format
- * @return effective clock rate of peripheral
- */
-static unsigned long get_rate_from_divider(unsigned long parent_rate,
-					   int divider)
-{
-	u64 rate;
-
-	rate = (u64)parent_rate * 2;
-	do_div(rate, divider + 2);
-	return rate;
-}
-
-unsigned long clock_get_periph_rate(enum periph_id periph_id,
-		enum clock_id parent)
-{
-	u32 *reg = get_periph_source_reg(periph_id);
-
-	return get_rate_from_divider(pll_rate[parent],
-		(readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
-}
-
-int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
-{
-	struct clk_pll *pll = get_pll(clkid);
-	int data = 0, div = 0, offset = 0;
-
-	if (!clock_id_is_pll(clkid))
-		return -1;
-
-	if (pllout + 1 > pll_num_clkouts[clkid])
-		return -1;
-
-	div = clk_get_divider(8, pll_rate[clkid], rate);
-
-	if (div < 0)
-		return -1;
-
-	/* out2 and out4 are in the high part of the register */
-	if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
-		offset = 16;
-
-	data = (div << PLL_OUT_RATIO_SHIFT) |
-			PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
-	clrsetbits_le32(&pll->pll_out[pllout >> 1],
-			PLL_OUT_RATIO_MASK << offset, data << offset);
-
-	return 0;
-}
-
-/**
- * Find the best available 7.1 format divisor given a parent clock rate and
- * required child clock rate. This function assumes that a second-stage
- * divisor is available which can divide by powers of 2 from 1 to 256.
- *
- * @param divider_bits	number of divider bits (8 or 16)
- * @param parent_rate	clock rate of parent clock in Hz
- * @param rate		required clock rate for this clock
- * @param extra_div	value for the second-stage divisor (not set if this
- *			function returns -1.
- * @return divider which should be used, or -1 if nothing is valid
- *
- */
-static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
-			     unsigned long rate, int *extra_div)
-{
-	int shift;
-	int best_divider = -1;
-	int best_error = rate;
-
-	/* try dividers from 1 to 256 and find closest match */
-	for (shift = 0; shift <= 8 && best_error > 0; shift++) {
-		unsigned divided_parent = parent_rate >> shift;
-		int divider = clk_get_divider(divider_bits, divided_parent,
-					      rate);
-		unsigned effective_rate = get_rate_from_divider(divided_parent,
-						       divider);
-		int error = rate - effective_rate;
-
-		/* Given a valid divider, look for the lowest error */
-		if (divider != -1 && error < best_error) {
-			best_error = error;
-			*extra_div = 1 << shift;
-			best_divider = divider;
-		}
-	}
-
-	/* return what we found - *extra_div will already be set */
-	return best_divider;
-}
-
 /**
  * Given a peripheral ID and the required source clock, this returns which
  * value should be programmed into the source mux for that peripheral.
@@ -695,7 +407,7 @@
  * @param divider_bits	Set to number of divider bits (8 or 16)
  * @return mux value (0-4, or -1 if not found)
  */
-static int get_periph_clock_source(enum periph_id periph_id,
+int get_periph_clock_source(enum periph_id periph_id,
 		enum clock_id parent, int *mux_bits, int *divider_bits)
 {
 	enum clock_type_id type;
@@ -743,88 +455,6 @@
 	return -1;
 }
 
-/**
- * Adjust peripheral PLL to use the given divider and source.
- *
- * @param periph_id	peripheral to adjust
- * @param source	Source number (0-3 or 0-7)
- * @param mux_bits	Number of mux bits (2 or 4)
- * @param divider	Required divider in 7.1 or 15.1 format
- * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
- *		for this peripheral)
- */
-static int adjust_periph_pll(enum periph_id periph_id, int source,
-			     int mux_bits, unsigned divider)
-{
-	u32 *reg = get_periph_source_reg(periph_id);
-
-	clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
-			divider << OUT_CLK_DIVISOR_SHIFT);
-	udelay(1);
-
-	/* work out the source clock and set it */
-	if (source < 0)
-		return -1;
-	if (mux_bits == 4) {
-		clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK,
-			source << OUT_CLK_SOURCE4_SHIFT);
-	} else {
-		clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
-			source << OUT_CLK_SOURCE_SHIFT);
-	}
-	udelay(2);
-	return 0;
-}
-
-unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
-		enum clock_id parent, unsigned rate, int *extra_div)
-{
-	unsigned effective_rate;
-	int mux_bits, divider_bits, source;
-	int divider;
-
-	/* work out the source clock and set it */
-	source = get_periph_clock_source(periph_id, parent, &mux_bits,
-					 &divider_bits);
-
-	if (extra_div)
-		divider = find_best_divider(divider_bits, pll_rate[parent],
-					    rate, extra_div);
-	else
-		divider = clk_get_divider(divider_bits, pll_rate[parent],
-					  rate);
-	assert(divider >= 0);
-	if (adjust_periph_pll(periph_id, source, mux_bits, divider))
-		return -1U;
-	debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
-		get_periph_source_reg(periph_id),
-		readl(get_periph_source_reg(periph_id)));
-
-	/* Check what we ended up with. This shouldn't matter though */
-	effective_rate = clock_get_periph_rate(periph_id, parent);
-	if (extra_div)
-		effective_rate /= *extra_div;
-	if (rate != effective_rate)
-		debug("Requested clock rate %u not honored (got %u)\n",
-		       rate, effective_rate);
-	return effective_rate;
-}
-
-unsigned clock_start_periph_pll(enum periph_id periph_id,
-		enum clock_id parent, unsigned rate)
-{
-	unsigned effective_rate;
-
-	reset_set_enable(periph_id, 1);
-	clock_enable(periph_id);
-
-	effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
-						 NULL);
-
-	reset_set_enable(periph_id, 0);
-	return effective_rate;
-}
-
 void clock_set_enable(enum periph_id periph_id, int enable)
 {
 	struct clk_rst_ctlr *clkrst =
@@ -842,16 +472,6 @@
 	writel(reg, clk);
 }
 
-void clock_enable(enum periph_id clkid)
-{
-	clock_set_enable(clkid, 1);
-}
-
-void clock_disable(enum periph_id clkid)
-{
-	clock_set_enable(clkid, 0);
-}
-
 void reset_set_enable(enum periph_id periph_id, int enable)
 {
 	struct clk_rst_ctlr *clkrst =
@@ -869,146 +489,6 @@
 	writel(reg, reset);
 }
 
-void reset_periph(enum periph_id periph_id, int us_delay)
-{
-	/* Put peripheral into reset */
-	reset_set_enable(periph_id, 1);
-	udelay(us_delay);
-
-	/* Remove reset */
-	reset_set_enable(periph_id, 0);
-
-	udelay(us_delay);
-}
-
-void reset_cmplx_set_enable(int cpu, int which, int reset)
-{
-	struct clk_rst_ctlr *clkrst =
-			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	u32 mask;
-
-	/* Form the mask, which depends on the cpu chosen. Tegra20 has 2 */
-	assert(cpu >= 0 && cpu < 2);
-	mask = which << cpu;
-
-	/* either enable or disable those reset for that CPU */
-	if (reset)
-		writel(mask, &clkrst->crc_cpu_cmplx_set);
-	else
-		writel(mask, &clkrst->crc_cpu_cmplx_clr);
-}
-
-unsigned clock_get_rate(enum clock_id clkid)
-{
-	struct clk_pll *pll;
-	u32 base;
-	u32 divm;
-	u64 parent_rate;
-	u64 rate;
-
-	parent_rate = osc_freq[clock_get_osc_freq()];
-	if (clkid == CLOCK_ID_OSC)
-		return parent_rate;
-
-	pll = get_pll(clkid);
-	base = readl(&pll->pll_base);
-
-	/* Oh for bf_unpack()... */
-	rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT);
-	divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
-	if (clkid == CLOCK_ID_USB)
-		divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT;
-	else
-		divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
-	do_div(rate, divm);
-	return rate;
-}
-
-/**
- * Set the output frequency you want for each PLL clock.
- * PLL output frequencies are programmed by setting their N, M and P values.
- * The governing equations are:
- *     VCO = (Fi / m) * n, Fo = VCO / (2^p)
- *     where Fo is the output frequency from the PLL.
- * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
- *     216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
- * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
- *
- * @param n PLL feedback divider(DIVN)
- * @param m PLL input divider(DIVN)
- * @param p post divider(DIVP)
- * @param cpcon base PLL charge pump(CPCON)
- * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
- *		be overriden), 1 if PLL is already correct
- */
-static int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
-{
-	u32 base_reg;
-	u32 misc_reg;
-	struct clk_pll *pll;
-
-	pll = get_pll(clkid);
-
-	base_reg = readl(&pll->pll_base);
-
-	/* Set BYPASS, m, n and p to PLL_BASE */
-	base_reg &= ~PLL_DIVM_MASK;
-	base_reg |= m << PLL_DIVM_SHIFT;
-
-	base_reg &= ~PLL_DIVN_MASK;
-	base_reg |= n << PLL_DIVN_SHIFT;
-
-	base_reg &= ~PLL_DIVP_MASK;
-	base_reg |= p << PLL_DIVP_SHIFT;
-
-	if (clkid == CLOCK_ID_PERIPH) {
-		/*
-		 * If the PLL is already set up, check that it is correct
-		 * and record this info for clock_verify() to check.
-		 */
-		if (base_reg & PLL_BASE_OVRRIDE_MASK) {
-			base_reg |= PLL_ENABLE_MASK;
-			if (base_reg != readl(&pll->pll_base))
-				pllp_valid = 0;
-			return pllp_valid ? 1 : -1;
-		}
-		base_reg |= PLL_BASE_OVRRIDE_MASK;
-	}
-
-	base_reg |= PLL_BYPASS_MASK;
-	writel(base_reg, &pll->pll_base);
-
-	/* Set cpcon to PLL_MISC */
-	misc_reg = readl(&pll->pll_misc);
-	misc_reg &= ~PLL_CPCON_MASK;
-	misc_reg |= cpcon << PLL_CPCON_SHIFT;
-	writel(misc_reg, &pll->pll_misc);
-
-	/* Enable PLL */
-	base_reg |= PLL_ENABLE_MASK;
-	writel(base_reg, &pll->pll_base);
-
-	/* Disable BYPASS */
-	base_reg &= ~PLL_BYPASS_MASK;
-	writel(base_reg, &pll->pll_base);
-
-	return 0;
-}
-
-void clock_ll_start_uart(enum periph_id periph_id)
-{
-	/* Assert UART reset and enable clock */
-	reset_set_enable(periph_id, 1);
-	clock_enable(periph_id);
-	clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
-
-	/* wait for 2us */
-	udelay(2);
-
-	/* De-assert reset to UART */
-	reset_set_enable(periph_id, 0);
-}
-
 #ifdef CONFIG_OF_CONTROL
 /*
  * Convert a device tree clock ID to our peripheral ID. They are mostly
@@ -1018,67 +498,34 @@
  * @param clk_id	Clock ID according to tegra20 device tree binding
  * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
  */
-static enum periph_id clk_id_to_periph_id(int clk_id)
+enum periph_id clk_id_to_periph_id(int clk_id)
 {
-	if (clk_id > 95)
+	if (clk_id > PERIPH_ID_COUNT)
 		return PERIPH_ID_NONE;
 
 	switch (clk_id) {
-	case 1:
-	case 2:
-	case 7:
-	case 10:
-	case 20:
-	case 30:
-	case 35:
-	case 49:
-	case 56:
-	case 74:
-	case 76:
-	case 77:
-	case 78:
-	case 79:
-	case 80:
-	case 81:
-	case 82:
-	case 83:
-	case 91:
-	case 95:
+	case PERIPH_ID_RESERVED1:
+	case PERIPH_ID_RESERVED2:
+	case PERIPH_ID_RESERVED30:
+	case PERIPH_ID_RESERVED35:
+	case PERIPH_ID_RESERVED56:
+	case PERIPH_ID_RESERVED74:
+	case PERIPH_ID_RESERVED76:
+	case PERIPH_ID_RESERVED77:
+	case PERIPH_ID_RESERVED78:
+	case PERIPH_ID_RESERVED79:
+	case PERIPH_ID_RESERVED80:
+	case PERIPH_ID_RESERVED81:
+	case PERIPH_ID_RESERVED82:
+	case PERIPH_ID_RESERVED83:
+	case PERIPH_ID_RESERVED91:
 		return PERIPH_ID_NONE;
 	default:
 		return clk_id;
 	}
 }
-
-int clock_decode_periph_id(const void *blob, int node)
-{
-	enum periph_id id;
-	u32 cell[2];
-	int err;
-
-	err = fdtdec_get_int_array(blob, node, "clocks", cell,
-				   ARRAY_SIZE(cell));
-	if (err)
-		return -1;
-	id = clk_id_to_periph_id(cell[1]);
-	assert(clock_periph_id_isvalid(id));
-	return id;
-}
 #endif /* CONFIG_OF_CONTROL */
 
-int clock_verify(void)
-{
-	struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
-	u32 reg = readl(&pll->pll_base);
-
-	if (!pllp_valid) {
-		printf("Warning: PLLP %x is not correct\n", reg);
-		return -1;
-	}
-	debug("PLLX %x is correct\n", reg);
-	return 0;
-}
-
 void clock_early_init(void)
 {
 	/*
@@ -1112,15 +559,3 @@
 		break;
 	}
 }
-
-void clock_init(void)
-{
-	pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
-	pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
-	pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
-	pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
-	pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
-	debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
-	debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
-	debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
-}
diff --git a/arch/arm/cpu/tegra20-common/funcmux.c b/arch/arm/cpu/tegra20-common/funcmux.c
index ece7ad9..80a9bd9 100644
--- a/arch/arm/cpu/tegra20-common/funcmux.c
+++ b/arch/arm/cpu/tegra20-common/funcmux.c
@@ -98,8 +98,8 @@
 		break;
 
 	case PERIPH_ID_UART2:
-		if (config == FUNCMUX_UART2_IRDA) {
-			pinmux_set_func(PINGRP_UAD, PMUX_FUNC_IRDA);
+		if (config == FUNCMUX_UART2_UAD) {
+			pinmux_set_func(PINGRP_UAD, PMUX_FUNC_UARTB);
 			pinmux_tristate_disable(PINGRP_UAD);
 		}
 		break;
diff --git a/arch/arm/cpu/tegra20-common/pinmux.c b/arch/arm/cpu/tegra20-common/pinmux.c
index a2a0916..5ad2121 100644
--- a/arch/arm/cpu/tegra20-common/pinmux.c
+++ b/arch/arm/cpu/tegra20-common/pinmux.c
@@ -390,7 +390,7 @@
 	PIN(UAA,  BB,    SPI3,   MIPI_HS, UARTA,    ULPI,        MIPI_HS),
 	PIN(UAB,  BB,    SPI2,   MIPI_HS, UARTA,    ULPI,        MIPI_HS),
 	PIN(UAC,  BB,    OWR,    RSVD,   RSVD,      RSVD,        RSVD4),
-	PIN(UAD,  UART,  IRDA,   SPDIF,  UARTA,     SPI4,        SPDIF),
+	PIN(UAD,  UART,  UARTB,  SPDIF,  UARTA,     SPI4,        SPDIF),
 	PIN(UCA,  UART,  UARTC,  RSVD,   GMI,       RSVD,        RSVD4),
 	PIN(UCB,  UART,  UARTC,  PWM,    GMI,       RSVD,        RSVD4),
 
diff --git a/arch/arm/cpu/tegra20-common/warmboot.c b/arch/arm/cpu/tegra20-common/warmboot.c
index 157b9ab..0d472cf 100644
--- a/arch/arm/cpu/tegra20-common/warmboot.c
+++ b/arch/arm/cpu/tegra20-common/warmboot.c
@@ -46,7 +46,7 @@
  * This is the place in SRAM where the SDRAM parameters are stored. There
  * are 4 blocks, one for each RAM code
  */
-#define SDRAM_PARAMS_BASE	(AP20_BASE_PA_SRAM + 0x188)
+#define SDRAM_PARAMS_BASE	(NV_PA_BASE_SRAM + 0x188)
 
 /* TODO: If we later add support for the Misc GP controller, refactor this */
 union xm2cfga_reg {
diff --git a/arch/arm/cpu/tegra30-common/Makefile b/arch/arm/cpu/tegra30-common/Makefile
new file mode 100644
index 0000000..75fef32
--- /dev/null
+++ b/arch/arm/cpu/tegra30-common/Makefile
@@ -0,0 +1,44 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+# The AVP is ARMv4T architecture so we must use special compiler
+# flags for any startup files it might use.
+
+LIB	= $(obj)lib$(SOC)-common.o
+
+COBJS-y	+= clock.o funcmux.o pinmux.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c
new file mode 100644
index 0000000..a93f2c9
--- /dev/null
+++ b/arch/arm/cpu/tegra30-common/clock.c
@@ -0,0 +1,618 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 Clock control functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+#include <div64.h>
+#include <fdtdec.h>
+
+/*
+ * Clock types that we can use as a source. The Tegra30 has muxes for the
+ * peripheral clocks, and in most cases there are four options for the clock
+ * source. This gives us a clock 'type' and exploits what commonality exists
+ * in the device.
+ *
+ * Letters are obvious, except for T which means CLK_M, and S which means the
+ * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
+ * datasheet) and PLL_M are different things. The former is the basic
+ * clock supplied to the SOC from an external oscillator. The latter is the
+ * memory clock PLL.
+ *
+ * See definitions in clock_id in the header file.
+ */
+enum clock_type_id {
+	CLOCK_TYPE_AXPT,	/* PLL_A, PLL_X, PLL_P, CLK_M */
+	CLOCK_TYPE_MCPA,	/* and so on */
+	CLOCK_TYPE_MCPT,
+	CLOCK_TYPE_PCM,
+	CLOCK_TYPE_PCMT,
+	CLOCK_TYPE_PCMT16,
+	CLOCK_TYPE_PDCT,
+	CLOCK_TYPE_ACPT,
+	CLOCK_TYPE_ASPTE,
+	CLOCK_TYPE_PMDACD2T,
+	CLOCK_TYPE_PCST,
+
+	CLOCK_TYPE_COUNT,
+	CLOCK_TYPE_NONE = -1,   /* invalid clock type */
+};
+
+enum {
+	CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
+};
+
+enum {
+	MASK_BITS_31_30 = 2,    /* num of bits used to specify clock source */
+	MASK_BITS_31_29,
+	MASK_BITS_29_28,
+};
+
+/*
+ * Clock source mux for each clock type. This just converts our enum into
+ * a list of mux sources for use by the code.
+ *
+ * Note:
+ *  The extra column in each clock source array is used to store the mask
+ *  bits in its register for the source.
+ */
+#define CLK(x) CLOCK_ID_ ## x
+static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
+	{ CLK(AUDIO),   CLK(XCPU),      CLK(PERIPH),    CLK(OSC),
+		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(AUDIO),
+		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
+		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(NONE),
+		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC),
+		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC),
+		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),  CLK(DISPLAY),   CLK(CGENERAL),  CLK(OSC),
+		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(AUDIO),   CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
+		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(AUDIO),   CLK(SFROM32KHZ),	CLK(PERIPH),   CLK(OSC),
+		CLK(EPCI),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_29},
+	{ CLK(PERIPH),  CLK(MEMORY),    CLK(DISPLAY),   CLK(AUDIO),
+		CLK(CGENERAL),  CLK(DISPLAY2),  CLK(OSC),       CLK(NONE),
+		MASK_BITS_31_29},
+	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(SFROM32KHZ), CLK(OSC),
+		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_29_28}
+};
+
+/*
+ * Clock type for each peripheral clock source. We put the name in each
+ * record just so it is easy to match things up
+ */
+#define TYPE(name, type) type
+static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
+	/* 0x00 */
+	TYPE(PERIPHC_I2S1,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S2,      CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_IN,  CLOCK_TYPE_PCM),
+	TYPE(PERIPHC_PWM,       CLOCK_TYPE_PCST),  /* only PWM uses b29:28 */
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC2,      CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SBC3,      CLOCK_TYPE_PCMT),
+
+	/* 0x08 */
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_I2C1,      CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_DVC_I2C,   CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC1,      CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_DISP1,     CLOCK_TYPE_PMDACD2T),
+	TYPE(PERIPHC_DISP2,     CLOCK_TYPE_PMDACD2T),
+
+	/* 0x10 */
+	TYPE(PERIPHC_CVE,       CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SDMMC1,    CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SDMMC2,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_G3D,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_G2D,	CLOCK_TYPE_MCPA),
+
+	/* 0x18 */
+	TYPE(PERIPHC_NDFLASH,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SDMMC4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_VFIR,      CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_EPP,       CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MPE,       CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MIPI,      CLOCK_TYPE_PCMT),       /* MIPI base-band HSI */
+	TYPE(PERIPHC_UART1,     CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_UART2,     CLOCK_TYPE_PCMT),
+
+	/* 0x20 */
+	TYPE(PERIPHC_HOST1X,    CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_TVO,       CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_HDMI,      CLOCK_TYPE_PMDACD2T),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_TVDAC,     CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_I2C2,      CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_EMC,	CLOCK_TYPE_MCPT),
+
+	/* 0x28 */
+	TYPE(PERIPHC_UART3,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC4,      CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2C3,      CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_SDMMC3,    CLOCK_TYPE_PCMT),
+
+	/* 0x30 */
+	TYPE(PERIPHC_UART4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_UART5,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_VDE,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_OWR,       CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NOR,       CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_CSITE,     CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2S0,      CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+
+	/* 0x38h */	     /* Jumps to reg offset 0x3B0h - new for T30 */
+	TYPE(PERIPHC_G3D2,      CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MSELECT,   CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_TSENSOR,   CLOCK_TYPE_PCST),       /* s/b PCTS */
+	TYPE(PERIPHC_I2S3,      CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S4,      CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2C4,      CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_SBC5,      CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SBC6,      CLOCK_TYPE_PCMT),
+
+	/* 0x40 */
+	TYPE(PERIPHC_AUDIO,     CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_DAM0,      CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_DAM1,      CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_DAM2,      CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_ACTMON,    CLOCK_TYPE_PCST),       /* MASK 31:30 */
+	TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
+
+	/* 0x48 */
+	TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
+	TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
+	TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2CSLOW,   CLOCK_TYPE_PCST),       /* MASK 31:30 */
+	TYPE(PERIPHC_SYS,       CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SPEEDO,    CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+
+	/* 0x50 */
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SATAOOB,   CLOCK_TYPE_PCMT),       /* offset 0x420h */
+	TYPE(PERIPHC_SATA,      CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_HDA,       CLOCK_TYPE_PCMT),
+};
+
+/*
+ * This array translates a periph_id to a periphc_internal_id
+ *
+ * Not present/matched up:
+ *	uint vi_sensor;	 _VI_SENSOR_0,		0x1A8
+ *	SPDIF - which is both 0x08 and 0x0c
+ *
+ */
+#define NONE(name) (-1)
+#define OFFSET(name, value) PERIPHC_ ## name
+static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
+	/* Low word: 31:0 */
+	NONE(CPU),
+	NONE(COP),
+	NONE(TRIGSYS),
+	NONE(RESERVED3),
+	NONE(RESERVED4),
+	NONE(TMR),
+	PERIPHC_UART1,
+	PERIPHC_UART2,  /* and vfir 0x68 */
+
+	/* 8 */
+	NONE(GPIO),
+	PERIPHC_SDMMC2,
+	NONE(SPDIF),	    /* 0x08 and 0x0c, unclear which to use */
+	PERIPHC_I2S1,
+	PERIPHC_I2C1,
+	PERIPHC_NDFLASH,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC4,
+
+	/* 16 */
+	NONE(RESERVED16),
+	PERIPHC_PWM,
+	PERIPHC_I2S2,
+	PERIPHC_EPP,
+	PERIPHC_VI,
+	PERIPHC_G2D,
+	NONE(USBD),
+	NONE(ISP),
+
+	/* 24 */
+	PERIPHC_G3D,
+	NONE(RESERVED25),
+	PERIPHC_DISP2,
+	PERIPHC_DISP1,
+	PERIPHC_HOST1X,
+	NONE(VCP),
+	PERIPHC_I2S0,
+	NONE(CACHE2),
+
+	/* Middle word: 63:32 */
+	NONE(MEM),
+	NONE(AHBDMA),
+	NONE(APBDMA),
+	NONE(RESERVED35),
+	NONE(RESERVED36),
+	NONE(STAT_MON),
+	NONE(RESERVED38),
+	NONE(RESERVED39),
+
+	/* 40 */
+	NONE(KFUSE),
+	PERIPHC_SBC1,
+	PERIPHC_NOR,
+	NONE(RESERVED43),
+	PERIPHC_SBC2,
+	NONE(RESERVED45),
+	PERIPHC_SBC3,
+	PERIPHC_DVC_I2C,
+
+	/* 48 */
+	NONE(DSI),
+	PERIPHC_TVO,    /* also CVE 0x40 */
+	PERIPHC_MIPI,
+	PERIPHC_HDMI,
+	NONE(CSI),
+	PERIPHC_TVDAC,
+	PERIPHC_I2C2,
+	PERIPHC_UART3,
+
+	/* 56 */
+	NONE(RESERVED56),
+	PERIPHC_EMC,
+	NONE(USB2),
+	NONE(USB3),
+	PERIPHC_MPE,
+	PERIPHC_VDE,
+	NONE(BSEA),
+	NONE(BSEV),
+
+	/* Upper word 95:64 */
+	PERIPHC_SPEEDO,
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_I2C3,
+	PERIPHC_SBC4,
+	PERIPHC_SDMMC3,
+	NONE(PCIE),
+	PERIPHC_OWR,
+
+	/* 72 */
+	NONE(AFI),
+	PERIPHC_CSITE,
+	NONE(PCIEXCLK),
+	NONE(AVPUCQ),
+	NONE(RESERVED76),
+	NONE(RESERVED77),
+	NONE(RESERVED78),
+	NONE(DTV),
+
+	/* 80 */
+	PERIPHC_NANDSPEED,
+	PERIPHC_I2CSLOW,
+	NONE(DSIB),
+	NONE(RESERVED83),
+	NONE(IRAMA),
+	NONE(IRAMB),
+	NONE(IRAMC),
+	NONE(IRAMD),
+
+	/* 88 */
+	NONE(CRAM2),
+	NONE(RESERVED89),
+	NONE(MDOUBLER),
+	NONE(RESERVED91),
+	NONE(SUSOUT),
+	NONE(RESERVED93),
+	NONE(RESERVED94),
+	NONE(RESERVED95),
+
+	/* V word: 31:0 */
+	NONE(CPUG),
+	NONE(CPULP),
+	PERIPHC_G3D2,
+	PERIPHC_MSELECT,
+	PERIPHC_TSENSOR,
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+
+	/* 08 */
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+	PERIPHC_AUDIO,
+	NONE(APBIF),
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+
+	/* 16 */
+	NONE(ATOMICS),
+	NONE(RESERVED17),
+	NONE(RESERVED18),
+	NONE(RESERVED19),
+	NONE(RESERVED20),
+	NONE(RESERVED21),
+	NONE(RESERVED22),
+	PERIPHC_ACTMON,
+
+	/* 24 */
+	NONE(RESERVED24),
+	NONE(RESERVED25),
+	NONE(RESERVED26),
+	NONE(RESERVED27),
+	PERIPHC_SATA,
+	PERIPHC_HDA,
+	NONE(RESERVED30),
+	NONE(RESERVED31),
+
+	/* W word: 31:0 */
+	NONE(HDA2HDMICODEC),
+	NONE(SATACOLD),
+	NONE(RESERVED0_PCIERX0),
+	NONE(RESERVED1_PCIERX1),
+	NONE(RESERVED2_PCIERX2),
+	NONE(RESERVED3_PCIERX3),
+	NONE(RESERVED4_PCIERX4),
+	NONE(RESERVED5_PCIERX5),
+
+	/* 40 */
+	NONE(CEC),
+	NONE(RESERVED6_PCIE2),
+	NONE(RESERVED7_EMC),
+	NONE(RESERVED8_HDMI),
+	NONE(RESERVED9_SATA),
+	NONE(RESERVED10_MIPI),
+	NONE(EX_RESERVED46),
+	NONE(EX_RESERVED47),
+};
+
+/*
+ * Get the oscillator frequency, from the corresponding hardware configuration
+ * field. Note that T30 supports 3 new higher freqs, but we map back
+ * to the old T20 freqs. Support for the higher oscillators is TBD.
+ */
+enum clock_osc_freq clock_get_osc_freq(void)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	reg = readl(&clkrst->crc_osc_ctrl);
+	reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+
+	if (reg & 1)			/* one of the newer freqs */
+		printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
+
+	return reg >> 2;	/* Map to most common (T20) freqs */
+}
+
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	enum periphc_internal_id internal_id;
+
+	/* Coresight is a special case */
+	if (periph_id == PERIPH_ID_CSI)
+		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
+
+	assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
+	internal_id = periph_id_to_internal_id[periph_id];
+	assert(internal_id != -1);
+	if (internal_id >= PERIPHC_VW_FIRST) {
+		internal_id -= PERIPHC_VW_FIRST;
+		return &clkrst->crc_clk_src_vw[internal_id];
+	} else
+		return &clkrst->crc_clk_src[internal_id];
+}
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id	peripheral to start
+ * @param source	PLL id of required parent clock
+ * @param mux_bits	Set to number of bits in mux register: 2 or 4
+ * @param divider_bits  Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+	enum clock_id parent, int *mux_bits, int *divider_bits)
+{
+	enum clock_type_id type;
+	enum periphc_internal_id internal_id;
+	int mux;
+
+	assert(clock_periph_id_isvalid(periph_id));
+
+	internal_id = periph_id_to_internal_id[periph_id];
+	assert(periphc_internal_id_isvalid(internal_id));
+
+	type = clock_periph_type[internal_id];
+	assert(clock_type_id_isvalid(type));
+
+	*mux_bits = clock_source[type][CLOCK_MAX_MUX];
+
+	if (type == CLOCK_TYPE_PCMT16)
+		*divider_bits = 16;
+	else
+		*divider_bits = 8;
+
+	for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
+		if (clock_source[type][mux] == parent)
+			return mux;
+
+	/* if we get here, either us or the caller has made a mistake */
+	printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
+		parent);
+	return -1;
+}
+
+void clock_set_enable(enum periph_id periph_id, int enable)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 *clk;
+	u32 reg;
+
+	/* Enable/disable the clock to this peripheral */
+	assert(clock_periph_id_isvalid(periph_id));
+	if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
+		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+	else
+		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
+	reg = readl(clk);
+	if (enable)
+		reg |= PERIPH_MASK(periph_id);
+	else
+		reg &= ~PERIPH_MASK(periph_id);
+	writel(reg, clk);
+}
+
+void reset_set_enable(enum periph_id periph_id, int enable)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 *reset;
+	u32 reg;
+
+	/* Enable/disable reset to the peripheral */
+	assert(clock_periph_id_isvalid(periph_id));
+	if (periph_id < PERIPH_ID_VW_FIRST)
+		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+	else
+		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
+	reg = readl(reset);
+	if (enable)
+		reg |= PERIPH_MASK(periph_id);
+	else
+		reg &= ~PERIPH_MASK(periph_id);
+	writel(reg, reset);
+}
+
+#ifdef CONFIG_OF_CONTROL
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id	Clock ID according to tegra30 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id)
+{
+	if (clk_id > PERIPH_ID_COUNT)
+		return PERIPH_ID_NONE;
+
+	switch (clk_id) {
+	case PERIPH_ID_RESERVED3:
+	case PERIPH_ID_RESERVED4:
+	case PERIPH_ID_RESERVED16:
+	case PERIPH_ID_RESERVED24:
+	case PERIPH_ID_RESERVED35:
+	case PERIPH_ID_RESERVED43:
+	case PERIPH_ID_RESERVED45:
+	case PERIPH_ID_RESERVED56:
+	case PERIPH_ID_RESERVED76:
+	case PERIPH_ID_RESERVED77:
+	case PERIPH_ID_RESERVED78:
+	case PERIPH_ID_RESERVED83:
+	case PERIPH_ID_RESERVED89:
+	case PERIPH_ID_RESERVED91:
+	case PERIPH_ID_RESERVED93:
+	case PERIPH_ID_RESERVED94:
+	case PERIPH_ID_RESERVED95:
+		return PERIPH_ID_NONE;
+	default:
+		return clk_id;
+	}
+}
+#endif /* CONFIG_OF_CONTROL */
+
+void clock_early_init(void)
+{
+	/*
+	 * PLLP output frequency set to 408Mhz
+	 * PLLC output frequency set to 228Mhz
+	 */
+	switch (clock_get_osc_freq()) {
+	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
+		break;
+
+	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+		break;
+
+	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+		break;
+	case CLOCK_OSC_FREQ_19_2:
+	default:
+		/*
+		 * These are not supported. It is too early to print a
+		 * message and the UART likely won't work anyway due to the
+		 * oscillator being wrong.
+		 */
+		break;
+	}
+}
diff --git a/arch/arm/cpu/tegra30-common/funcmux.c b/arch/arm/cpu/tegra30-common/funcmux.c
new file mode 100644
index 0000000..e24c57e
--- /dev/null
+++ b/arch/arm/cpu/tegra30-common/funcmux.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 high-level function multiplexing */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+
+int funcmux_select(enum periph_id id, int config)
+{
+	int bad_config = config != FUNCMUX_DEFAULT;
+
+	switch (id) {
+	case PERIPH_ID_UART1:
+		switch (config) {
+		case FUNCMUX_UART1_ULPI:
+			pinmux_set_func(PINGRP_ULPI_DATA0, PMUX_FUNC_UARTA);
+			pinmux_set_func(PINGRP_ULPI_DATA1, PMUX_FUNC_UARTA);
+			pinmux_set_func(PINGRP_ULPI_DATA2, PMUX_FUNC_UARTA);
+			pinmux_set_func(PINGRP_ULPI_DATA3, PMUX_FUNC_UARTA);
+			pinmux_tristate_disable(PINGRP_ULPI_DATA0);
+			pinmux_tristate_disable(PINGRP_ULPI_DATA1);
+			pinmux_tristate_disable(PINGRP_ULPI_DATA2);
+			pinmux_tristate_disable(PINGRP_ULPI_DATA3);
+			break;
+		}
+		break;
+
+	/* Add other periph IDs here as needed */
+
+	default:
+		debug("%s: invalid periph_id %d", __func__, id);
+		return -1;
+	}
+
+	if (bad_config) {
+		debug("%s: invalid config %d for periph_id %d", __func__,
+		      config, id);
+		return -1;
+	}
+	return 0;
+}
diff --git a/arch/arm/cpu/tegra30-common/pinmux.c b/arch/arm/cpu/tegra30-common/pinmux.c
new file mode 100644
index 0000000..122665f
--- /dev/null
+++ b/arch/arm/cpu/tegra30-common/pinmux.c
@@ -0,0 +1,506 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 pin multiplexing functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/pinmux.h>
+
+struct tegra_pingroup_desc {
+	const char *name;
+	enum pmux_func funcs[4];
+	enum pmux_func func_safe;
+	enum pmux_vddio vddio;
+	enum pmux_pin_io io;
+};
+
+#define PMUX_MUXCTL_SHIFT	0
+#define PMUX_PULL_SHIFT		2
+#define PMUX_TRISTATE_SHIFT	4
+#define PMUX_TRISTATE_MASK	(1 << PMUX_TRISTATE_SHIFT)
+#define PMUX_IO_SHIFT		5
+#define PMUX_OD_SHIFT		6
+#define PMUX_LOCK_SHIFT		7
+#define PMUX_IO_RESET_SHIFT	8
+
+/* Convenient macro for defining pin group properties */
+#define PIN(pg_name, vdd, f0, f1, f2, f3, iod)	\
+	{						\
+		.vddio = PMUX_VDDIO_ ## vdd,		\
+		.funcs = {				\
+			PMUX_FUNC_ ## f0,		\
+			PMUX_FUNC_ ## f1,		\
+			PMUX_FUNC_ ## f2,		\
+			PMUX_FUNC_ ## f3,		\
+		},					\
+		.func_safe = PMUX_FUNC_RSVD1,		\
+		.io = PMUX_PIN_ ## iod,			\
+	}
+
+/* Input and output pins */
+#define PINI(pg_name, vdd, f0, f1, f2, f3) \
+	PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
+#define PINO(pg_name, vdd, f0, f1, f2, f3) \
+	PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
+
+const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
+	/*	NAME	  VDD	   f0		f1	   f2	    f3  */
+	PINI(ULPI_DATA0,  BB,	   SPI3,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA1,  BB,	   SPI3,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA2,  BB,	   SPI3,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA3,  BB,	   SPI3,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA4,  BB,	   SPI2,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA5,  BB,	   SPI2,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA6,  BB,	   SPI2,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA7,  BB,	   SPI2,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_CLK,	  BB,	   SPI1,	RSVD2,	   UARTD,   ULPI),
+	PINI(ULPI_DIR,	  BB,	   SPI1,	RSVD2,	   UARTD,   ULPI),
+	PINI(ULPI_NXT,	  BB,	   SPI1,	RSVD2,	   UARTD,   ULPI),
+	PINI(ULPI_STP,	  BB,	   SPI1,	RSVD2,	   UARTD,   ULPI),
+	PINI(DAP3_FS,	  BB,	   I2S2,	RSVD2,	   DISPA,   DISPB),
+	PINI(DAP3_DIN,	  BB,	   I2S2,	RSVD2,	   DISPA,   DISPB),
+	PINI(DAP3_DOUT,	  BB,	   I2S2,	RSVD2,	   DISPA,   DISPB),
+	PINI(DAP3_SCLK,	  BB,	   I2S2,	RSVD2,	   DISPA,   DISPB),
+	PINI(GPIO_PV0,	  BB,	   RSVD1,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(GPIO_PV1,	  BB,	   RSVD1,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(SDMMC1_CLK,  SDMMC1,  SDMMC1,	RSVD2,	   RSVD3,   UARTA),
+	PINI(SDMMC1_CMD,  SDMMC1,  SDMMC1,	RSVD2,	   RSVD3,   UARTA),
+	PINI(SDMMC1_DAT3, SDMMC1,  SDMMC1,	RSVD2,	   UARTE,   UARTA),
+	PINI(SDMMC1_DAT2, SDMMC1,  SDMMC1,	RSVD2,	   UARTE,   UARTA),
+	PINI(SDMMC1_DAT1, SDMMC1,  SDMMC1,	RSVD2,	   UARTE,   UARTA),
+	PINI(SDMMC1_DAT0, SDMMC1,  SDMMC1,	RSVD2,	   UARTE,   UARTA),
+	PINI(GPIO_PV2,	  SDMMC1,  OWR,		RSVD2,	   RSVD3,   RSVD4),
+	PINI(GPIO_PV3,	  SDMMC1,  CLK_12M_OUT,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(CLK2_OUT,	  SDMMC1,  EXTPERIPH2,	RSVD2,     RSVD3,   RSVD4),
+	PINI(CLK2_REQ,	  SDMMC1,  DAP,		RSVD2,	   RSVD3,   RSVD4),
+	PINO(LCD_PWR1,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_PWR2,	  LCD,	   DISPA,	DISPB,	   SPI5,    HDCP),
+	PINO(LCD_SDIN,	  LCD,	   DISPA,	DISPB,	   SPI5,    RSVD4),
+	PINO(LCD_SDOUT,	  LCD,	   DISPA,	DISPB,	   SPI5,    HDCP),
+	PINO(LCD_WR_N,	  LCD,	   DISPA,	DISPB,	   SPI5,    HDCP),
+	PINO(LCD_CS0_N,	  LCD,	   DISPA,	DISPB,	   SPI5,    RSVD4),
+	PINO(LCD_DC0,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_SCK,	  LCD,	   DISPA,	DISPB,	   SPI5,    HDCP),
+	PINO(LCD_PWR0,	  LCD,	   DISPA,	DISPB,	   SPI5,    HDCP),
+	PINO(LCD_PCLK,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_DE,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_HSYNC,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_VSYNC,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D0,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D1,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D2,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D3,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D4,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D5,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D6,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D7,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D8,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D9,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D10,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D11,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D12,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D13,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D14,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D15,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D16,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D17,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D18,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D19,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D20,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D21,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D22,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_D23,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_CS1_N,	  LCD,	   DISPA,	DISPB,	   SPI5,    RSVD4),
+	PINO(LCD_M1,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINO(LCD_DC1,	  LCD,	   DISPA,	DISPB,	   RSVD3,   RSVD4),
+	PINI(HDMI_INT,	  LCD,	   HDMI,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(DDC_SCL,	  LCD,	   I2C4,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(DDC_SDA,	  LCD,	   I2C4,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(CRT_HSYNC,	  LCD,	   CRT,		RSVD2,	   RSVD3,   RSVD4),
+	PINI(CRT_VSYNC,	  LCD,	   CRT,		RSVD2,	   RSVD3,   RSVD4),
+	PINI(VI_D0,	  VI,	   DDR,		RSVD2,	   VI,      RSVD4),
+	PINI(VI_D1,	  VI,	   DDR,		SDMMC2,	   VI,      RSVD4),
+	PINI(VI_D2,	  VI,	   DDR,		SDMMC2,	   VI,      RSVD4),
+	PINI(VI_D3,	  VI,	   DDR,		SDMMC2,	   VI,      RSVD4),
+	PINI(VI_D4,	  VI,	   DDR,		SDMMC2,	   VI,      RSVD4),
+	PINI(VI_D5,	  VI,	   DDR,		SDMMC2,	   VI,      RSVD4),
+	PINI(VI_D6,	  VI,	   DDR,		SDMMC2,	   VI,      RSVD4),
+	PINI(VI_D7,	  VI,	   DDR,		SDMMC2,	   VI,      RSVD4),
+	PINI(VI_D8,	  VI,	   DDR,		SDMMC2,	   VI,      RSVD4),
+	PINI(VI_D9,	  VI,	   DDR,		SDMMC2,	   VI,      RSVD4),
+	PINI(VI_D10,	  VI,	   DDR,		RSVD2,	   VI,      RSVD4),
+	PINI(VI_D11,	  VI,	   DDR,		RSVD2,	   VI,      RSVD4),
+	PINI(VI_PCLK,	  VI,	   RSVD1,	SDMMC2,	   VI,      RSVD4),
+	PINI(VI_MCLK,	  VI,	   VI,		VI,	   VI,      VI),
+	PINI(VI_VSYNC,	  VI,	   DDR,		RSVD2,	   VI,      RSVD4),
+	PINI(VI_HSYNC,	  VI,	   DDR,		RSVD2,	   VI,      RSVD4),
+	PINI(UART2_RXD,	  UART,	   UARTB,	SPDIF,	   UARTA,   SPI4),
+	PINI(UART2_TXD,	  UART,	   UARTB,	SPDIF,	   UARTA,   SPI4),
+	PINI(UART2_RTS_N, UART,	   UARTA,	UARTB,	   GMI,     SPI4),
+	PINI(UART2_CTS_N, UART,	   UARTA,	UARTB,	   GMI,     SPI4),
+	PINI(UART3_TXD,	  UART,	   UARTC,	RSVD2,	   GMI,     RSVD4),
+	PINI(UART3_RXD,	  UART,	   UARTC,	RSVD2,	   GMI,     RSVD4),
+	PINI(UART3_CTS_N, UART,	   UARTC,	RSVD2,	   GMI,     RSVD4),
+	PINI(UART3_RTS_N, UART,	   UARTC,	PWM0,	   GMI,     RSVD4),
+	PINI(GPIO_PU0,	  UART,	   OWR,		UARTA,	   GMI,     RSVD4),
+	PINI(GPIO_PU1,	  UART,	   RSVD1,	UARTA,	   GMI,     RSVD4),
+	PINI(GPIO_PU2,	  UART,	   RSVD1,	UARTA,	   GMI,     RSVD4),
+	PINI(GPIO_PU3,	  UART,	   PWM0,	UARTA,	   GMI,     RSVD4),
+	PINI(GPIO_PU4,	  UART,	   PWM1,	UARTA,	   GMI,     RSVD4),
+	PINI(GPIO_PU5,	  UART,	   PWM2,	UARTA,	   GMI,     RSVD4),
+	PINI(GPIO_PU6,	  UART,	   PWM3,	UARTA,	   GMI,     RSVD4),
+	PINI(GEN1_I2C_SDA, UART,   I2C1,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(GEN1_I2C_SCL, UART,   I2C1,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(DAP4_FS,	  UART,	   I2S3,	RSVD2,	   GMI,     RSVD4),
+	PINI(DAP4_DIN,	  UART,	   I2S3,	RSVD2,	   GMI,     RSVD4),
+	PINI(DAP4_DOUT,	  UART,	   I2S3,	RSVD2,	   GMI,     RSVD4),
+	PINI(DAP4_SCLK,	  UART,	   I2S3,	RSVD2,	   GMI,     RSVD4),
+	PINI(CLK3_OUT,	  UART,	   EXTPERIPH3,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(CLK3_REQ,	  UART,	   DEV3,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(GMI_WP_N,	  GMI,	   RSVD1,	NAND,	   GMI,     GMI_ALT),
+	PINI(GMI_IORDY,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_WAIT,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_ADV_N,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_CLK,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_CS0_N,	  GMI,	   RSVD1,	NAND,	   GMI,     DTV),
+	PINI(GMI_CS1_N,	  GMI,	   RSVD1,	NAND,	   GMI,     DTV),
+	PINI(GMI_CS2_N,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_CS3_N,	  GMI,	   RSVD1,	NAND,	   GMI,     GMI_ALT),
+	PINI(GMI_CS4_N,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_CS6_N,	  GMI,	   NAND,	NAND_ALT,  GMI,     SATA),
+	PINI(GMI_CS7_N,	  GMI,	   NAND,	NAND_ALT,  GMI,     GMI_ALT),
+	PINI(GMI_AD0,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_AD1,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_AD2,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_AD3,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_AD4,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_AD5,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_AD6,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_AD7,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_AD8,	  GMI,	   PWM0,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_AD9,	  GMI,	   PWM1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_AD10,	  GMI,	   PWM2,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_AD11,	  GMI,	   PWM3,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_AD12,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_AD13,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_AD14,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_AD15,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_A16,	  GMI,	   UARTD,	SPI4,	   GMI,     GMI_ALT),
+	PINI(GMI_A17,	  GMI,	   UARTD,	SPI4,	   GMI,     DTV),
+	PINI(GMI_A18,	  GMI,	   UARTD,	SPI4,	   GMI,     DTV),
+	PINI(GMI_A19,	  GMI,	   UARTD,	SPI4,	   GMI,     RSVD4),
+	PINI(GMI_WR_N,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_OE_N,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_DQS,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD4),
+	PINI(GMI_RST_N,	  GMI,	   NAND,	NAND_ALT,  GMI,     RSVD4),
+	PINI(GEN2_I2C_SCL, GMI,	   I2C2,	HDCP,	   GMI,     RSVD4),
+	PINI(GEN2_I2C_SDA, GMI,    I2C2,	HDCP,	   GMI,     RSVD4),
+	PINI(SDMMC4_CLK,  SDMMC4,   RSVD1,	NAND,	   GMI,     SDMMC4),
+	PINI(SDMMC4_CMD,  SDMMC4,   I2C3,	NAND,	   GMI,     SDMMC4),
+	PINI(SDMMC4_DAT0, SDMMC4,   UARTE,	SPI3,	   GMI,     SDMMC4),
+	PINI(SDMMC4_DAT1, SDMMC4,   UARTE,	SPI3,	   GMI,     SDMMC4),
+	PINI(SDMMC4_DAT2, SDMMC4,   UARTE,	SPI3,	   GMI,     SDMMC4),
+	PINI(SDMMC4_DAT3, SDMMC4,   UARTE,	SPI3,	   GMI,     SDMMC4),
+	PINI(SDMMC4_DAT4, SDMMC4,   I2C3,	I2S4,	   GMI,     SDMMC4),
+	PINI(SDMMC4_DAT5, SDMMC4,   VGP3,	I2S4,	   GMI,     SDMMC4),
+	PINI(SDMMC4_DAT6, SDMMC4,   VGP4,	I2S4,	   GMI,     SDMMC4),
+	PINI(SDMMC4_DAT7, SDMMC4,   VGP5,	I2S4,	   GMI,     SDMMC4),
+	PINI(SDMMC4_RST_N, SDMMC4,  VGP6,	RSVD2,	   RSVD3,   SDMMC4),
+	PINI(CAM_MCLK,	  CAM,	   VI,		RSVD2,	   VI_ALT2, SDMMC4),
+	PINI(GPIO_PCC1,	  CAM,	   I2S4,	RSVD2,	   RSVD3,   SDMMC4),
+	PINI(GPIO_PBB0,	  CAM,	   I2S4,	RSVD2,	   RSVD3,   SDMMC4),
+	PINI(CAM_I2C_SCL, CAM,	   VGP1,	I2C3,	   RSVD3,   SDMMC4),
+	PINI(CAM_I2C_SDA, CAM,	   VGP2,	I2C3,	   RSVD3,   SDMMC4),
+	PINI(GPIO_PBB3,	  CAM,	   VGP3,	DISPA,	   DISPB,   SDMMC4),
+	PINI(GPIO_PBB4,	  CAM,	   VGP4,	DISPA,	   DISPB,   SDMMC4),
+	PINI(GPIO_PBB5,	  CAM,	   VGP5,	DISPA,	   DISPB,   SDMMC4),
+	PINI(GPIO_PBB6,	  CAM,	   VGP6,	DISPA,	   DISPB,   SDMMC4),
+	PINI(GPIO_PBB7,	  CAM,	   I2S4,	RSVD2,	   RSVD3,   SDMMC4),
+	PINI(GPIO_PCC2,	  CAM,	   I2S4,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(JTAG_RTCK,	  SYS,	   RTCK,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(PWR_I2C_SCL, SYS,	   I2CPWR,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(PWR_I2C_SDA, SYS,	   I2CPWR,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(KB_ROW0,	  SYS,	   KBC,		NAND,	   RSVD3,   RSVD4),
+	PINI(KB_ROW1,	  SYS,	   KBC,		NAND,	   RSVD3,   RSVD4),
+	PINI(KB_ROW2,	  SYS,	   KBC,		NAND,	   RSVD3,   RSVD4),
+	PINI(KB_ROW3,	  SYS,	   KBC,		NAND,	   RSVD3,   RSVD4),
+	PINI(KB_ROW4,	  SYS,	   KBC,		NAND,	   TRACE,   RSVD4),
+	PINI(KB_ROW5,	  SYS,	   KBC,		NAND,	   TRACE,   OWR),
+	PINI(KB_ROW6,	  SYS,	   KBC,		NAND,	   SDMMC2,  MIO),
+	PINI(KB_ROW7,	  SYS,	   KBC,		NAND,	   SDMMC2,  MIO),
+	PINI(KB_ROW8,	  SYS,	   KBC,		NAND,	   SDMMC2,  MIO),
+	PINI(KB_ROW9,	  SYS,	   KBC,		NAND,	   SDMMC2,  MIO),
+	PINI(KB_ROW10,	  SYS,	   KBC,		NAND,	   SDMMC2,  MIO),
+	PINI(KB_ROW11,	  SYS,	   KBC,		NAND,	   SDMMC2,  MIO),
+	PINI(KB_ROW12,	  SYS,	   KBC,		NAND,	   SDMMC2,  MIO),
+	PINI(KB_ROW13,	  SYS,	   KBC,		NAND,	   SDMMC2,  MIO),
+	PINI(KB_ROW14,	  SYS,	   KBC,		NAND,	   SDMMC2,  MIO),
+	PINI(KB_ROW15,	  SYS,	   KBC,		NAND,	   SDMMC2,  MIO),
+	PINI(KB_COL0,	  SYS,	   KBC,		NAND,	   TRACE,   TEST),
+	PINI(KB_COL1,	  SYS,	   KBC,		NAND,	   TRACE,   TEST),
+	PINI(KB_COL2,	  SYS,	   KBC,		NAND,	   TRACE,   RSVD4),
+	PINI(KB_COL3,	  SYS,	   KBC,		NAND,	   TRACE,   RSVD4),
+	PINI(KB_COL4,	  SYS,	   KBC,		NAND,	   TRACE,   RSVD4),
+	PINI(KB_COL5,	  SYS,	   KBC,		NAND,	   TRACE,   RSVD4),
+	PINI(KB_COL6,	  SYS,	   KBC,		NAND,	   TRACE,   MIO),
+	PINI(KB_COL7,	  SYS,	   KBC,		NAND,	   TRACE,   MIO),
+	PINI(CLK_32K_OUT, SYS,	   BLINK,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(SYS_CLK_REQ, SYS,	   SYSCLK,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(CORE_PWR_REQ, SYS,	   CORE_PWR_REQ, RSVD2,	   RSVD3,   RSVD4),
+	PINI(CPU_PWR_REQ, SYS,	   CPU_PWR_REQ,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(PWR_INT_N,	  SYS,	   PWR_INT_N,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(CLK_32K_IN,  SYS,	   CLK_32K_IN,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(OWR,	  SYS,	   OWR,		CEC,	   RSVD3,   RSVD4),
+	PINI(DAP1_FS,	  AUDIO,   I2S0,	HDA,	   GMI,     SDMMC2),
+	PINI(DAP1_DIN,	  AUDIO,   I2S0,	HDA,	   GMI,     SDMMC2),
+	PINI(DAP1_DOUT,	  AUDIO,   I2S0,	HDA,	   GMI,     SDMMC2),
+	PINI(DAP1_SCLK,	  AUDIO,   I2S0,	HDA,	   GMI,     SDMMC2),
+	PINI(CLK1_REQ,	  AUDIO,   DAP,		HDA,	   RSVD3,   RSVD4),
+	PINI(CLK1_OUT,	  AUDIO,   EXTPERIPH1,	RSVD2,	   RSVD3,   RSVD4),
+	PINI(SPDIF_IN,	  AUDIO,   SPDIF,	HDA,	   I2C1,    SDMMC2),
+	PINI(SPDIF_OUT,	  AUDIO,   SPDIF,	RSVD2,	   I2C1,    SDMMC2),
+	PINI(DAP2_FS,	  AUDIO,   I2S1,	HDA,	   RSVD3,   GMI),
+	PINI(DAP2_DIN,	  AUDIO,   I2S1,	HDA,	   RSVD3,   GMI),
+	PINI(DAP2_DOUT,	  AUDIO,   I2S1,	HDA,	   RSVD3,   GMI),
+	PINI(DAP2_SCLK,	  AUDIO,   I2S1,	HDA,	   RSVD3,   GMI),
+	PINI(SPI2_MOSI,	  AUDIO,   SPI6,	SPI2,	   GMI,     GMI),
+	PINI(SPI2_MISO,	  AUDIO,   SPI6,	SPI2,	   GMI,     GMI),
+	PINI(SPI2_CS0_N,  AUDIO,   SPI6,	SPI2,	   GMI,     GMI),
+	PINI(SPI2_SCK,	  AUDIO,   SPI6,	SPI2,	   GMI,     GMI),
+	PINI(SPI1_MOSI,	  AUDIO,   SPI2,	SPI1,	   SPI2_ALT, GMI),
+	PINI(SPI1_SCK,	  AUDIO,   SPI2,	SPI1,	   SPI2_ALT, GMI),
+	PINI(SPI1_CS0_N,  AUDIO,   SPI2,	SPI1,	   SPI2_ALT, GMI),
+	PINI(SPI1_MISO,	  AUDIO,   SPI3,	SPI1,	   SPI2_ALT, RSVD4),
+	PINI(SPI2_CS1_N,  AUDIO,   SPI3,	SPI2,	   SPI2_ALT, I2C1),
+	PINI(SPI2_CS2_N,  AUDIO,   SPI3,	SPI2,	   SPI2_ALT, I2C1),
+	PINI(SDMMC3_CLK,  SDMMC3,  UARTA,	PWM2,	   SDMMC3,  SPI3),
+	PINI(SDMMC3_CMD,  SDMMC3,  UARTA,	PWM3,	   SDMMC3,  SPI2),
+	PINI(SDMMC3_DAT0, SDMMC3,  RSVD1,	RSVD2,	   SDMMC3,  SPI3),
+	PINI(SDMMC3_DAT1, SDMMC3,  RSVD1,	RSVD2,	   SDMMC3,  SPI3),
+	PINI(SDMMC3_DAT2, SDMMC3,  RSVD1,	PWM1,	   SDMMC3,  SPI3),
+	PINI(SDMMC3_DAT3, SDMMC3,  RSVD1,	PWM0,	   SDMMC3,  SPI3),
+	PINI(SDMMC3_DAT4, SDMMC3,  PWM1,	SPI4,	   SDMMC3,  SPI2),
+	PINI(SDMMC3_DAT5, SDMMC3,  PWM0,	SPI4,	   SDMMC3,  SPI2),
+	PINI(SDMMC3_DAT6, SDMMC3,  SPDIF,	SPI4,	   SDMMC3,  SPI2),
+	PINI(SDMMC3_DAT7, SDMMC3,  SPDIF,	SPI4,	   SDMMC3,  SPI2),
+	PINI(PEX_L0_PRSNT_N,	PEXCTL,   PCIE,	HDA,	   RSVD3,   RSVD4),
+	PINI(PEX_L0_RST_N,	PEXCTL,   PCIE,	HDA,	   RSVD3,   RSVD4),
+	PINI(PEX_L0_CLKREQ_N,	PEXCTL,   PCIE,	HDA,	   RSVD3,   RSVD4),
+	PINI(PEX_WAKE_N,	PEXCTL,   PCIE,	HDA,	   RSVD3,   RSVD4),
+	PINI(PEX_L1_PRSNT_N,	PEXCTL,   PCIE,	HDA,	   RSVD3,   RSVD4),
+	PINI(PEX_L1_RST_N,	PEXCTL,   PCIE,	HDA,	   RSVD3,   RSVD4),
+	PINI(PEX_L1_CLKREQ_N,	PEXCTL,   PCIE,	HDA,	   RSVD3,   RSVD4),
+	PINI(PEX_L2_PRSNT_N,	PEXCTL,   PCIE,	HDA,	   RSVD3,   RSVD4),
+	PINI(PEX_L2_RST_N,	PEXCTL,   PCIE,	HDA,	   RSVD3,   RSVD4),
+	PINI(PEX_L2_CLKREQ_N,	PEXCTL,   PCIE,	HDA,	   RSVD3,   RSVD4),
+	PINI(HDMI_CEC,		SYS,      CEC,	RSVD2,	   RSVD3,   RSVD4),
+};
+
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *tri = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin */
+	assert(pmux_pingrp_isvalid(pin));
+
+	reg = readl(tri);
+	if (enable)
+		reg |= PMUX_TRISTATE_MASK;
+	else
+		reg &= ~PMUX_TRISTATE_MASK;
+	writel(reg, tri);
+}
+
+void pinmux_tristate_enable(enum pmux_pingrp pin)
+{
+	pinmux_set_tristate(pin, 1);
+}
+
+void pinmux_tristate_disable(enum pmux_pingrp pin)
+{
+	pinmux_set_tristate(pin, 0);
+}
+
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pull = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and pupd */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_pupd_isvalid(pupd));
+
+	reg = readl(pull);
+	reg &= ~(0x3 << PMUX_PULL_SHIFT);
+	reg |= (pupd << PMUX_PULL_SHIFT);
+	writel(reg, pull);
+}
+
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *muxctl = &pmt->pmt_ctl[pin];
+	int i, mux = -1;
+	u32 reg;
+
+	/* Error check on pin and func */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_func_isvalid(func));
+
+	/* Handle special values */
+	if (func == PMUX_FUNC_SAFE)
+		func = tegra_soc_pingroups[pin].func_safe;
+
+	if (func & PMUX_FUNC_RSVD1) {
+		mux = func & 0x3;
+	} else {
+		/* Search for the appropriate function */
+		for (i = 0; i < 4; i++) {
+			if (tegra_soc_pingroups[pin].funcs[i] == func) {
+				mux = i;
+				break;
+			}
+		}
+	}
+	assert(mux != -1);
+
+	reg = readl(muxctl);
+	reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
+	reg |= (mux << PMUX_MUXCTL_SHIFT);
+	writel(reg, muxctl);
+
+}
+
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_io = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and io */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_io_isvalid(io));
+
+	reg = readl(pin_io);
+	reg &= ~(0x1 << PMUX_IO_SHIFT);
+	reg |= (io & 0x1) << PMUX_IO_SHIFT;
+	writel(reg, pin_io);
+}
+
+static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_lock = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and lock */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_lock_isvalid(lock));
+
+	if (lock == PMUX_PIN_LOCK_DEFAULT)
+		return 0;
+
+	reg = readl(pin_lock);
+	reg &= ~(0x1 << PMUX_LOCK_SHIFT);
+	if (lock == PMUX_PIN_LOCK_ENABLE)
+		reg |= (0x1 << PMUX_LOCK_SHIFT);
+	else {
+		/* lock == DISABLE, which isn't possible */
+		printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
+			__func__, lock);
+	}
+	writel(reg, pin_lock);
+
+	return 0;
+}
+
+static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_od = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and od */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_od_isvalid(od));
+
+	if (od == PMUX_PIN_OD_DEFAULT)
+		return 0;
+
+	reg = readl(pin_od);
+	reg &= ~(0x1 << PMUX_OD_SHIFT);
+	if (od == PMUX_PIN_OD_ENABLE)
+		reg |= (0x1 << PMUX_OD_SHIFT);
+	writel(reg, pin_od);
+
+	return 0;
+}
+
+static int pinmux_set_ioreset(enum pmux_pingrp pin,
+				enum pmux_pin_ioreset ioreset)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_ioreset = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and ioreset */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_ioreset_isvalid(ioreset));
+
+	if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
+		return 0;
+
+	reg = readl(pin_ioreset);
+	reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
+	if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
+		reg |= (0x1 << PMUX_IO_RESET_SHIFT);
+	writel(reg, pin_ioreset);
+
+	return 0;
+}
+
+void pinmux_config_pingroup(struct pingroup_config *config)
+{
+	enum pmux_pingrp pin = config->pingroup;
+
+	pinmux_set_func(pin, config->func);
+	pinmux_set_pullupdown(pin, config->pull);
+	pinmux_set_tristate(pin, config->tristate);
+	pinmux_set_io(pin, config->io);
+	pinmux_set_lock(pin, config->lock);
+	pinmux_set_od(pin, config->od);
+	pinmux_set_ioreset(pin, config->ioreset);
+}
+
+void pinmux_config_table(struct pingroup_config *config, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		pinmux_config_pingroup(&config[i]);
+}
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
new file mode 100644
index 0000000..d06cd12
--- /dev/null
+++ b/arch/arm/dts/tegra114.dtsi
@@ -0,0 +1,5 @@
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "nvidia,tegra114";
+};
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index 636ec2c..9a89685 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -4,19 +4,101 @@
 	compatible = "nvidia,tegra20";
 	interrupt-parent = <&intc>;
 
-	tegra_car: clock@60006000 {
-		compatible = "nvidia,tegra20-car";
-		reg = <0x60006000 0x1000>;
-		#clock-cells = <1>;
-	};
+	host1x {
+		compatible = "nvidia,tegra20-host1x", "simple-bus";
+		reg = <0x50000000 0x00024000>;
+		interrupts = <0 65 0x04   /* mpcore syncpt */
+			      0 67 0x04>; /* mpcore general */
+		status = "disabled";
 
-	clocks {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
+
+		ranges = <0x54000000 0x54000000 0x04000000>;
+
+		/* video-encoding/decoding */
+		mpe {
+			reg = <0x54040000 0x00040000>;
+			interrupts = <0 68 0x04>;
+			status = "disabled";
+		};
+
+		/* video input */
+		vi {
+			reg = <0x54080000 0x00040000>;
+			interrupts = <0 69 0x04>;
+			status = "disabled";
+		};
+
+		/* EPP */
+		epp {
+			reg = <0x540c0000 0x00040000>;
+			interrupts = <0 70 0x04>;
+			status = "disabled";
+		};
+
+		/* ISP */
+		isp {
+			reg = <0x54100000 0x00040000>;
+			interrupts = <0 71 0x04>;
+			status = "disabled";
+		};
+
+		/* 2D engine */
+		gr2d {
+			reg = <0x54140000 0x00040000>;
+			interrupts = <0 72 0x04>;
+			status = "disabled";
+		};
+
+		/* 3D engine */
+		gr3d {
+			reg = <0x54180000 0x00040000>;
+			status = "disabled";
+		};
+
+		/* display controllers */
+		dc@54200000 {
+			compatible = "nvidia,tegra20-dc";
+			reg = <0x54200000 0x00040000>;
+			interrupts = <0 73 0x04>;
+			status = "disabled";
+
+			rgb {
+				status = "disabled";
+			};
+		};
+
+		dc@54240000 {
+			compatible = "nvidia,tegra20-dc";
+			reg = <0x54240000 0x00040000>;
+			interrupts = <0 74 0x04>;
+			status = "disabled";
+
+			rgb {
+				status = "disabled";
+			};
+		};
+
+		/* outputs */
+		hdmi {
+			compatible = "nvidia,tegra20-hdmi";
+			reg = <0x54280000 0x00040000>;
+			interrupts = <0 75 0x04>;
+			status = "disabled";
+		};
 
-		osc: clock {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
+		tvo {
+			compatible = "nvidia,tegra20-tvo";
+			reg = <0x542c0000 0x00040000>;
+			interrupts = <0 76 0x04>;
+			status = "disabled";
+		};
+
+		dsi {
+			compatible = "nvidia,tegra20-dsi";
+			reg = <0x54300000 0x00040000>;
+			status = "disabled";
 		};
 	};
 
@@ -28,44 +110,54 @@
 		      < 0x50040100 0x0100 >;
 	};
 
-	i2c@7000c000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "nvidia,tegra20-i2c";
-		reg = <0x7000C000 0x100>;
-		interrupts = < 70 >;
-		/* PERIPH_ID_I2C1, PLL_P_OUT3 */
-		clocks = <&tegra_car 12>, <&tegra_car 124>;
+	tegra_car: clock@60006000 {
+		compatible = "nvidia,tegra20-car";
+		reg = <0x60006000 0x1000>;
+		#clock-cells = <1>;
 	};
 
-	i2c@7000c400 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "nvidia,tegra20-i2c";
-		reg = <0x7000C400 0x100>;
-		interrupts = < 116 >;
-		/* PERIPH_ID_I2C2, PLL_P_OUT3 */
-		clocks = <&tegra_car 54>, <&tegra_car 124>;
+	apbdma: dma {
+		compatible = "nvidia,tegra20-apbdma";
+		reg = <0x6000a000 0x1200>;
+		interrupts = <0 104 0x04
+			      0 105 0x04
+			      0 106 0x04
+			      0 107 0x04
+			      0 108 0x04
+			      0 109 0x04
+			      0 110 0x04
+			      0 111 0x04
+			      0 112 0x04
+			      0 113 0x04
+			      0 114 0x04
+			      0 115 0x04
+			      0 116 0x04
+			      0 117 0x04
+			      0 118 0x04
+			      0 119 0x04>;
 	};
 
-	i2c@7000c500 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "nvidia,tegra20-i2c";
-		reg = <0x7000C500 0x100>;
-		interrupts = < 124 >;
-		/* PERIPH_ID_I2C3, PLL_P_OUT3 */
-		clocks = <&tegra_car 67>, <&tegra_car 124>;
+	gpio: gpio@6000d000 {
+		compatible = "nvidia,tegra20-gpio";
+		reg = < 0x6000d000 0x1000 >;
+		interrupts = < 64 65 66 67 87 119 121 >;
+		#gpio-cells = <2>;
+		gpio-controller;
 	};
 
-	i2c@7000d000 {
+	pinmux: pinmux@70000000 {
+		compatible = "nvidia,tegra20-pinmux";
+		reg = < 0x70000014 0x10    /* Tri-state registers */
+			0x70000080 0x20    /* Mux registers */
+			0x700000a0 0x14    /* Pull-up/down registers */
+			0x70000868 0xa8 >; /* Pad control registers */
+	};
+
+	das@70000c00 {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		compatible = "nvidia,tegra20-i2c-dvc";
-		reg = <0x7000D000 0x200>;
-		interrupts = < 85 >;
-		/* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
-		clocks = <&tegra_car 47>, <&tegra_car 124>;
+		compatible = "nvidia,tegra20-das";
+		reg = <0x70000c00 0x80>;
 	};
 
 	i2s@70002800 {
@@ -86,29 +178,6 @@
 		dma-channel = < 1 >;
 	};
 
-	das@70000c00 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "nvidia,tegra20-das";
-		reg = <0x70000c00 0x80>;
-	};
-
-	gpio: gpio@6000d000 {
-		compatible = "nvidia,tegra20-gpio";
-		reg = < 0x6000d000 0x1000 >;
-		interrupts = < 64 65 66 67 87 119 121 >;
-		#gpio-cells = <2>;
-		gpio-controller;
-	};
-
-	pinmux: pinmux@70000000 {
-		compatible = "nvidia,tegra20-pinmux";
-		reg = < 0x70000014 0x10    /* Tri-state registers */
-			0x70000080 0x20    /* Mux registers */
-			0x700000a0 0x14    /* Pull-up/down registers */
-			0x70000868 0xa8 >; /* Pad control registers */
-	};
-
 	serial@70006000 {
 		compatible = "nvidia,tegra20-uart";
 		reg = <0x70006000 0x40>;
@@ -144,28 +213,81 @@
 		interrupts = < 123 >;
 	};
 
-	sdhci@c8000000 {
-		compatible = "nvidia,tegra20-sdhci";
-		reg = <0xc8000000 0x200>;
-		interrupts = < 46 >;
+	nand: nand-controller@70008000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-nand";
+		reg = <0x70008000 0x100>;
 	};
 
-	sdhci@c8000200 {
-		compatible = "nvidia,tegra20-sdhci";
-		reg = <0xc8000200 0x200>;
-		interrupts = < 47 >;
+	pwm: pwm@7000a000 {
+		compatible = "nvidia,tegra20-pwm";
+		reg = <0x7000a000 0x100>;
+		#pwm-cells = <2>;
 	};
 
-	sdhci@c8000400 {
-		compatible = "nvidia,tegra20-sdhci";
-		reg = <0xc8000400 0x200>;
-		interrupts = < 51 >;
+	i2c@7000c000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-i2c";
+		reg = <0x7000C000 0x100>;
+		interrupts = < 70 >;
+		/* PERIPH_ID_I2C1, PLL_P_OUT3 */
+		clocks = <&tegra_car 12>, <&tegra_car 124>;
 	};
 
-	sdhci@c8000600 {
-		compatible = "nvidia,tegra20-sdhci";
-		reg = <0xc8000600 0x200>;
-		interrupts = < 63 >;
+	spi@7000c380 {
+		compatible = "nvidia,tegra20-sflash";
+		reg = <0x7000c380 0x80>;
+		interrupts = <0 39 0x04>;
+		nvidia,dma-request-selector = <&apbdma 11>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SPI1, PLLP_OUT0 */
+		clocks = <&tegra_car 43>;
+	};
+
+	i2c@7000c400 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-i2c";
+		reg = <0x7000C400 0x100>;
+		interrupts = < 116 >;
+		/* PERIPH_ID_I2C2, PLL_P_OUT3 */
+		clocks = <&tegra_car 54>, <&tegra_car 124>;
+	};
+
+	i2c@7000c500 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-i2c";
+		reg = <0x7000C500 0x100>;
+		interrupts = < 124 >;
+		/* PERIPH_ID_I2C3, PLL_P_OUT3 */
+		clocks = <&tegra_car 67>, <&tegra_car 124>;
+	};
+
+	i2c@7000d000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-i2c-dvc";
+		reg = <0x7000D000 0x200>;
+		interrupts = < 85 >;
+		/* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
+		clocks = <&tegra_car 47>, <&tegra_car 124>;
+	};
+
+	kbc@7000e200 {
+		compatible = "nvidia,tegra20-kbc";
+		reg = <0x7000e200 0x0078>;
+	};
+
+	emc@7000f400 {
+		#address-cells = < 1 >;
+		#size-cells = < 0 >;
+		compatible = "nvidia,tegra20-emc";
+		reg = <0x7000f400 0x200>;
 	};
 
 	usb@c5000000 {
@@ -193,127 +315,27 @@
 		clocks = <&tegra_car 59>;	/* PERIPH_ID_USB3 */
 	};
 
-	emc@7000f400 {
-		#address-cells = < 1 >;
-		#size-cells = < 0 >;
-		compatible = "nvidia,tegra20-emc";
-		reg = <0x7000f400 0x200>;
-	};
-
-	kbc@7000e200 {
-		compatible = "nvidia,tegra20-kbc";
-		reg = <0x7000e200 0x0078>;
+	sdhci@c8000000 {
+		compatible = "nvidia,tegra20-sdhci";
+		reg = <0xc8000000 0x200>;
+		interrupts = < 46 >;
 	};
 
-	nand: nand-controller@70008000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "nvidia,tegra20-nand";
-		reg = <0x70008000 0x100>;
+	sdhci@c8000200 {
+		compatible = "nvidia,tegra20-sdhci";
+		reg = <0xc8000200 0x200>;
+		interrupts = < 47 >;
 	};
 
-	pwm: pwm@7000a000 {
-		compatible = "nvidia,tegra20-pwm";
-		reg = <0x7000a000 0x100>;
-		#pwm-cells = <2>;
+	sdhci@c8000400 {
+		compatible = "nvidia,tegra20-sdhci";
+		reg = <0xc8000400 0x200>;
+		interrupts = < 51 >;
 	};
 
-	host1x {
-		compatible = "nvidia,tegra20-host1x", "simple-bus";
-		reg = <0x50000000 0x00024000>;
-		interrupts = <0 65 0x04   /* mpcore syncpt */
-			      0 67 0x04>; /* mpcore general */
-		status = "disabled";
-
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		ranges = <0x54000000 0x54000000 0x04000000>;
-
-		/* video-encoding/decoding */
-		mpe {
-			reg = <0x54040000 0x00040000>;
-			interrupts = <0 68 0x04>;
-			status = "disabled";
-		};
-
-		/* video input */
-		vi {
-			reg = <0x54080000 0x00040000>;
-			interrupts = <0 69 0x04>;
-			status = "disabled";
-		};
-
-		/* EPP */
-		epp {
-			reg = <0x540c0000 0x00040000>;
-			interrupts = <0 70 0x04>;
-			status = "disabled";
-		};
-
-		/* ISP */
-		isp {
-			reg = <0x54100000 0x00040000>;
-			interrupts = <0 71 0x04>;
-			status = "disabled";
-		};
-
-		/* 2D engine */
-		gr2d {
-			reg = <0x54140000 0x00040000>;
-			interrupts = <0 72 0x04>;
-			status = "disabled";
-		};
-
-		/* 3D engine */
-		gr3d {
-			reg = <0x54180000 0x00040000>;
-			status = "disabled";
-		};
-
-		/* display controllers */
-		dc@54200000 {
-			compatible = "nvidia,tegra20-dc";
-			reg = <0x54200000 0x00040000>;
-			interrupts = <0 73 0x04>;
-			status = "disabled";
-
-			rgb {
-				status = "disabled";
-			};
-		};
-
-		dc@54240000 {
-			compatible = "nvidia,tegra20-dc";
-			reg = <0x54240000 0x00040000>;
-			interrupts = <0 74 0x04>;
-			status = "disabled";
-
-			rgb {
-				status = "disabled";
-			};
-		};
-
-		/* outputs */
-		hdmi {
-			compatible = "nvidia,tegra20-hdmi";
-			reg = <0x54280000 0x00040000>;
-			interrupts = <0 75 0x04>;
-			status = "disabled";
-		};
-
-		tvo {
-			compatible = "nvidia,tegra20-tvo";
-			reg = <0x542c0000 0x00040000>;
-			interrupts = <0 76 0x04>;
-			status = "disabled";
-		};
-
-		dsi {
-			compatible = "nvidia,tegra20-dsi";
-			reg = <0x54300000 0x00040000>;
-			status = "disabled";
-		};
+	sdhci@c8000600 {
+		compatible = "nvidia,tegra20-sdhci";
+		reg = <0xc8000600 0x200>;
+		interrupts = < 63 >;
 	};
-
 };
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
new file mode 100644
index 0000000..7b8126f
--- /dev/null
+++ b/arch/arm/dts/tegra30.dtsi
@@ -0,0 +1,165 @@
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "nvidia,tegra30";
+
+	tegra_car: clock@60006000 {
+		compatible = "nvidia,tegra30-car", "nvidia,tegra20-car";
+		reg = <0x60006000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	apbdma: dma {
+		compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
+		reg = <0x6000a000 0x1400>;
+		interrupts = <0 104 0x04
+			      0 105 0x04
+			      0 106 0x04
+			      0 107 0x04
+			      0 108 0x04
+			      0 109 0x04
+			      0 110 0x04
+			      0 111 0x04
+			      0 112 0x04
+			      0 113 0x04
+			      0 114 0x04
+			      0 115 0x04
+			      0 116 0x04
+			      0 117 0x04
+			      0 118 0x04
+			      0 119 0x04
+			      0 128 0x04
+			      0 129 0x04
+			      0 130 0x04
+			      0 131 0x04
+			      0 132 0x04
+			      0 133 0x04
+			      0 134 0x04
+			      0 135 0x04
+			      0 136 0x04
+			      0 137 0x04
+			      0 138 0x04
+			      0 139 0x04
+			      0 140 0x04
+			      0 141 0x04
+			      0 142 0x04
+			      0 143 0x04>;
+	};
+
+	i2c@7000c000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+		reg = <0x7000C000 0x100>;
+		/* PERIPH_ID_I2C1, CLK_M */
+		clocks = <&tegra_car 12>;
+	};
+
+	i2c@7000c400 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+		reg = <0x7000C400 0x100>;
+		/* PERIPH_ID_I2C2, CLK_M */
+		clocks = <&tegra_car 54>;
+	};
+
+	i2c@7000c500 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+		reg = <0x7000C500 0x100>;
+		/* PERIPH_ID_I2C3, CLK_M */
+		clocks = <&tegra_car 67>;
+	};
+
+	i2c@7000c700 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+		reg = <0x7000C700 0x100>;
+		/* PERIPH_ID_I2C4, CLK_M */
+		clocks = <&tegra_car 103>;
+	};
+
+	i2c@7000d000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+		reg = <0x7000D000 0x100>;
+		/* PERIPH_ID_I2C_DVC, CLK_M */
+		clocks = <&tegra_car 47>;
+	};
+
+	spi@7000d400 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000d400 0x200>;
+		interrupts = <0 59 0x04>;
+		nvidia,dma-request-selector = <&apbdma 15>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC1, PLLP_OUT0 */
+		clocks = <&tegra_car 41>;
+	};
+
+	spi@7000d600 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000d600 0x200>;
+		interrupts = <0 82 0x04>;
+		nvidia,dma-request-selector = <&apbdma 16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC2, PLLP_OUT0 */
+		clocks = <&tegra_car 44>;
+	};
+
+	spi@7000d800 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000d480 0x200>;
+		interrupts = <0 83 0x04>;
+		nvidia,dma-request-selector = <&apbdma 17>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC3, PLLP_OUT0 */
+		clocks = <&tegra_car 46>;
+	};
+
+	spi@7000da00 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000da00 0x200>;
+		interrupts = <0 93 0x04>;
+		nvidia,dma-request-selector = <&apbdma 18>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC4, PLLP_OUT0 */
+		clocks = <&tegra_car 68>;
+	};
+
+	spi@7000dc00 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000dc00 0x200>;
+		interrupts = <0 94 0x04>;
+		nvidia,dma-request-selector = <&apbdma 27>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC5, PLLP_OUT0 */
+		clocks = <&tegra_car 104>;
+	};
+
+	spi@7000de00 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000de00 0x200>;
+		interrupts = <0 79 0x04>;
+		nvidia,dma-request-selector = <&apbdma 28>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC6, PLLP_OUT0 */
+		clocks = <&tegra_car 105>;
+	};
+};
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index b3e608e..6309fcd 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -42,6 +42,19 @@
 $(LIB):	$(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
+$(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp: $(OBJTREE)/%.cfgtmp : $(SRCTREE)/%
+	mkdir -p $(dir $@)
+	$(CC) -E -x c $< $(CPPFLAGS) -o $@
+
+$(OBJTREE)/u-boot.imx: $(OBJTREE)/u-boot.bin $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp
+	$(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \
+	-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
+
+$(OBJTREE)/SPL: $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp
+	$(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \
+	-e $(CONFIG_SPL_TEXT_BASE) -d $< $@
+
+
 #########################################################################
 
 # defines $(obj).depend target
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 8e69fb6..ae43ef8 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -65,6 +65,40 @@
 #define MT41J128MJT125_PHY_FIFO_WE		0x100
 #define MT41J128MJT125_IOCTRL_VALUE		0x18B
 
+/* Micron MT41J256M8HX-15E */
+#define MT41J256M8HX15E_EMIF_READ_LATENCY	0x06
+#define MT41J256M8HX15E_EMIF_TIM1		0x0888A39B
+#define MT41J256M8HX15E_EMIF_TIM2		0x26337FDA
+#define MT41J256M8HX15E_EMIF_TIM3		0x501F830F
+#define MT41J256M8HX15E_EMIF_SDCFG		0x61C04B32
+#define MT41J256M8HX15E_EMIF_SDREF		0x0000093B
+#define MT41J256M8HX15E_ZQ_CFG			0x50074BE4
+#define MT41J256M8HX15E_DLL_LOCK_DIFF		0x1
+#define MT41J256M8HX15E_RATIO			0x40
+#define MT41J256M8HX15E_INVERT_CLKOUT		0x1
+#define MT41J256M8HX15E_RD_DQS			0x3B
+#define MT41J256M8HX15E_WR_DQS			0x85
+#define MT41J256M8HX15E_PHY_WR_DATA		0xC1
+#define MT41J256M8HX15E_PHY_FIFO_WE		0x100
+#define MT41J256M8HX15E_IOCTRL_VALUE		0x18B
+
+/* Micron MT41J512M8RH-125 on EVM v1.5 */
+#define MT41J512M8RH125_EMIF_READ_LATENCY	0x06
+#define MT41J512M8RH125_EMIF_TIM1		0x0888A39B
+#define MT41J512M8RH125_EMIF_TIM2		0x26517FDA
+#define MT41J512M8RH125_EMIF_TIM3		0x501F84EF
+#define MT41J512M8RH125_EMIF_SDCFG		0x61C04BB2
+#define MT41J512M8RH125_EMIF_SDREF		0x0000093B
+#define MT41J512M8RH125_ZQ_CFG			0x50074BE4
+#define MT41J512M8RH125_DLL_LOCK_DIFF		0x1
+#define MT41J512M8RH125_RATIO			0x80
+#define MT41J512M8RH125_INVERT_CLKOUT		0x0
+#define MT41J512M8RH125_RD_DQS			0x3B
+#define MT41J512M8RH125_WR_DQS			0x3C
+#define MT41J512M8RH125_PHY_FIFO_WE		0xA5
+#define MT41J512M8RH125_PHY_WR_DATA		0x74
+#define MT41J512M8RH125_IOCTRL_VALUE		0x18B
+
 /**
  * Configure SDRAM
  */
diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h
index aed6b00..460ac1c 100644
--- a/arch/arm/include/asm/arch-am33xx/mux.h
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -25,7 +25,8 @@
 /* PAD Control Fields */
 #define SLEWCTRL	(0x1 << 6)
 #define RXACTIVE	(0x1 << 5)
-#define PULLUP_EN	(0x1 << 4) /* Pull UP Selection */
+#define PULLDOWN_EN	(0x0 << 4) /* Pull Down Selection */
+#define PULLUP_EN	(0x1 << 4) /* Pull Up Selection */
 #define PULLUDEN	(0x0 << 3) /* Pull up enabled */
 #define PULLUDDIS	(0x1 << 3) /* Pull up disabled */
 #define MODE(val)	val	/* used for Readability */
diff --git a/arch/arm/include/asm/arch-mxs/clock.h b/arch/arm/include/asm/arch-mxs/clock.h
index 3d39ef2..3f7d3f0 100644
--- a/arch/arm/include/asm/arch-mxs/clock.h
+++ b/arch/arm/include/asm/arch-mxs/clock.h
@@ -1,5 +1,5 @@
 /*
- * Freescale i.MX28 Clock
+ * Freescale i.MX23/i.MX28 Clock
  *
  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  * on behalf of DENX Software Engineering GmbH
@@ -31,11 +31,13 @@
 	MXC_GPMI_CLK,
 	MXC_IO0_CLK,
 	MXC_IO1_CLK,
+	MXC_XTAL_CLK,
 	MXC_SSP0_CLK,
+#ifdef CONFIG_MX28
 	MXC_SSP1_CLK,
 	MXC_SSP2_CLK,
 	MXC_SSP3_CLK,
-	MXC_XTAL_CLK,
+#endif
 };
 
 enum mxs_ioclock {
@@ -45,16 +47,18 @@
 
 enum mxs_sspclock {
 	MXC_SSPCLK0 = 0,
+#ifdef CONFIG_MX28
 	MXC_SSPCLK1,
 	MXC_SSPCLK2,
 	MXC_SSPCLK3,
+#endif
 };
 
 uint32_t mxc_get_clock(enum mxc_clock clk);
 
-void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq);
-void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
-void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq);
+void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq);
+void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
+void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq);
 
 /* Compatibility with the FEC Ethernet driver */
 #define	imx_get_fecclk()	mxc_get_clock(MXC_AHB_CLK)
diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h
index 9764041..05eb63c 100644
--- a/arch/arm/include/asm/arch-mxs/imx-regs.h
+++ b/arch/arm/include/asm/arch-mxs/imx-regs.h
@@ -1,5 +1,5 @@
 /*
- * Freescale i.MX28 Registers
+ * Freescale i.MX23/i.MX28 Registers
  *
  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  * on behalf of DENX Software Engineering GmbH
@@ -37,6 +37,11 @@
 #include <asm/arch/regs-ssp.h>
 #include <asm/arch/regs-timrot.h>
 
+#ifdef CONFIG_MX23
+#include <asm/arch/regs-clkctrl-mx23.h>
+#include <asm/arch/regs-power-mx23.h>
+#endif
+
 #ifdef CONFIG_MX28
 #include <asm/arch/regs-clkctrl-mx28.h>
 #include <asm/arch/regs-power-mx28.h>
diff --git a/arch/arm/include/asm/arch-mxs/iomux-mx23.h b/arch/arm/include/asm/arch-mxs/iomux-mx23.h
new file mode 100644
index 0000000..7cb5e71
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/iomux-mx23.h
@@ -0,0 +1,355 @@
+/*
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __MACH_IOMUX_MX23_H__
+#define __MACH_IOMUX_MX23_H__
+
+#include <asm/arch/iomux.h>
+
+/*
+ * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux.h
+ *
+ *									BANK	PIN	MUX
+ */
+/* MUXSEL_0 */
+#define MX23_PAD_GPMI_D00__GPMI_D00		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D01__GPMI_D01		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D02__GPMI_D02		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D03__GPMI_D03		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D04__GPMI_D04		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D05__GPMI_D05		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D06__GPMI_D06		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D07__GPMI_D07		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D08__GPMI_D08		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D09__GPMI_D09		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D10__GPMI_D10		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D11__GPMI_D11		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D12__GPMI_D12		MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D13__GPMI_D13		MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D14__GPMI_D14		MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D15__GPMI_D15		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CLE__GPMI_CLE		MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_ALE__GPMI_ALE		MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CE2N__GPMI_CE2N		MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY0__GPMI_RDY0		MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY1__GPMI_RDY1		MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY2__GPMI_RDY2		MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY3__GPMI_RDY3		MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_WPN__GPMI_WPN		MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_WRN__GPMI_WRN		MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDN__GPMI_RDN		MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_CTS__AUART1_CTS		MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_RTS__AUART1_RTS		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_RX__AUART1_RX		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_TX__AUART1_TX		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0)
+#define MX23_PAD_I2C_SCL__I2C_SCL		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0)
+#define MX23_PAD_I2C_SDA__I2C_SDA		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0)
+
+#define MX23_PAD_LCD_D00__LCD_D00		MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D01__LCD_D01		MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D02__LCD_D02		MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D03__LCD_D03		MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D04__LCD_D04		MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D05__LCD_D05		MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D06__LCD_D06		MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D07__LCD_D07		MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D08__LCD_D08		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D09__LCD_D09		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D10__LCD_D10		MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D11__LCD_D11		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D12__LCD_D12		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D13__LCD_D13		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D14__LCD_D14		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D15__LCD_D15		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D16__LCD_D16		MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D17__LCD_D17		MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_RESET__LCD_RESET		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_RS__LCD_RS			MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_WR__LCD_WR			MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_CS__LCD_CS			MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_DOTCK__LCD_DOTCK		MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_ENABLE__LCD_ENABLE		MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_HSYNC__LCD_HSYNC		MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_VSYNC__LCD_VSYNC		MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
+#define MX23_PAD_PWM0__PWM0			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
+#define MX23_PAD_PWM1__PWM1			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
+#define MX23_PAD_PWM2__PWM2			MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
+#define MX23_PAD_PWM3__PWM3			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
+#define MX23_PAD_PWM4__PWM4			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
+
+#define MX23_PAD_SSP1_CMD__SSP1_CMD		MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DETECT__SSP1_DETECT	MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA0__SSP1_DATA0		MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA1__SSP1_DATA1		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA2__SSP1_DATA2		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA3__SSP1_DATA3		MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_SCK__SSP1_SCK		MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
+#define MX23_PAD_ROTARYA__ROTARYA		MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
+#define MX23_PAD_ROTARYB__ROTARYB		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A00__EMI_A00		MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A01__EMI_A01		MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A02__EMI_A02		MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A03__EMI_A03		MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A04__EMI_A04		MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A05__EMI_A05		MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A06__EMI_A06		MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A07__EMI_A07		MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A08__EMI_A08		MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A09__EMI_A09		MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A10__EMI_A10		MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A11__EMI_A11		MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A12__EMI_A12		MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_BA0__EMI_BA0		MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_BA1__EMI_BA1		MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CASN__EMI_CASN		MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CE0N__EMI_CE0N		MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CE1N__EMI_CE1N		MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CE1N__GPMI_CE1N		MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CE0N__GPMI_CE0N		MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CKE__EMI_CKE		MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_RASN__EMI_RASN		MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_WEN__EMI_WEN		MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0)
+
+#define MX23_PAD_EMI_D00__EMI_D00		MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D01__EMI_D01		MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D02__EMI_D02		MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D03__EMI_D03		MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D04__EMI_D04		MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D05__EMI_D05		MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D06__EMI_D06		MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D07__EMI_D07		MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D08__EMI_D08		MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D09__EMI_D09		MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D10__EMI_D10		MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D11__EMI_D11		MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D12__EMI_D12		MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D13__EMI_D13		MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D14__EMI_D14		MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D15__EMI_D15		MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQM0__EMI_DQM0		MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQM1__EMI_DQM1		MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQS0__EMI_DQS0		MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQS1__EMI_DQS1		MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CLK__EMI_CLK		MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CLKN__EMI_CLKN		MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
+
+/* MUXSEL_1 */
+#define MX23_PAD_GPMI_D00__LCD_D8		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D01__LCD_D9		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D02__LCD_D10		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D03__LCD_D11		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D04__LCD_D12		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D05__LCD_D13		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D06__LCD_D14		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D07__LCD_D15		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D08__LCD_D18		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D09__LCD_D19		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D10__LCD_D20		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D11__LCD_D21		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D12__LCD_D22		MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D13__LCD_D23		MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D14__AUART2_RX		MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D15__AUART2_TX		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_CLE__LCD_D16		MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_ALE__LCD_D17		MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_CE2N__ATA_A2		MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
+#define MX23_PAD_AUART1_RTS__IR_CLK		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
+#define MX23_PAD_AUART1_RX__IR_RX		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
+#define MX23_PAD_AUART1_TX__IR_TX		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1)
+#define MX23_PAD_I2C_SCL__GPMI_RDY2		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1)
+#define MX23_PAD_I2C_SDA__GPMI_CE2N		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1)
+
+#define MX23_PAD_LCD_D00__ETM_DA8		MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D01__ETM_DA9		MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D02__ETM_DA10		MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D03__ETM_DA11		MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D04__ETM_DA12		MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D05__ETM_DA13		MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D06__ETM_DA14		MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D07__ETM_DA15		MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D08__ETM_DA0		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D09__ETM_DA1		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D10__ETM_DA2		MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D11__ETM_DA3		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D12__ETM_DA4		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D13__ETM_DA5		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D14__ETM_DA6		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D15__ETM_DA7		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_RESET__ETM_TCTL		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_RS__ETM_TCLK		MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_DOTCK__GPMI_RDY3		MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_ENABLE__I2C_SCL		MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_HSYNC__I2C_SDA		MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_VSYNC__LCD_BUSY		MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
+#define MX23_PAD_PWM0__ROTARYA			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
+#define MX23_PAD_PWM1__ROTARYB			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
+#define MX23_PAD_PWM2__GPMI_RDY3		MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
+#define MX23_PAD_PWM3__ETM_TCTL			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
+#define MX23_PAD_PWM4__ETM_TCLK			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
+
+#define MX23_PAD_SSP1_DETECT__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_1)
+#define MX23_PAD_SSP1_DATA1__I2C_SCL		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_1)
+#define MX23_PAD_SSP1_DATA2__I2C_SDA		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
+#define MX23_PAD_ROTARYA__AUART2_RTS		MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
+#define MX23_PAD_ROTARYB__AUART2_CTS		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_1)
+
+/* MUXSEL_2 */
+#define MX23_PAD_GPMI_D00__SSP2_DATA0		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D01__SSP2_DATA1		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D02__SSP2_DATA2		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D03__SSP2_DATA3		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D04__SSP2_DATA4		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D05__SSP2_DATA5		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D06__SSP2_DATA6		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D07__SSP2_DATA7		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D08__SSP1_DATA4		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D09__SSP1_DATA5		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D10__SSP1_DATA6		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D11__SSP1_DATA7		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D15__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_RDY0__SSP2_DETECT		MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_RDY1__SSP2_CMD		MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_WRN__SSP2_SCK		MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_CTS__SSP1_DATA4		MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_RTS__SSP1_DATA5		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_RX__SSP1_DATA6		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_TX__SSP1_DATA7		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2)
+#define MX23_PAD_I2C_SCL__AUART1_TX		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2)
+#define MX23_PAD_I2C_SDA__AUART1_RX		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2)
+
+#define MX23_PAD_LCD_D08__SAIF2_SDATA0		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D09__SAIF1_SDATA0		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK	MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D11__SAIF_LRCLK		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D12__SAIF2_SDATA1		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D13__SAIF2_SDATA2		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D14__SAIF1_SDATA2		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D15__SAIF1_SDATA1		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK	MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_RESET__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
+#define MX23_PAD_PWM0__DUART_RX			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2)
+#define MX23_PAD_PWM1__DUART_TX			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2)
+#define MX23_PAD_PWM3__AUART1_CTS		MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
+#define MX23_PAD_PWM4__AUART1_RTS		MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
+
+#define MX23_PAD_SSP1_CMD__JTAG_TDO		MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DETECT__USB_OTG_ID	MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA0__JTAG_TDI		MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA1__JTAG_TCLK		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA2__JTAG_RTCK		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA3__JTAG_TMS		MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_SCK__JTAG_TRST		MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_2)
+#define MX23_PAD_ROTARYA__SPDIF			MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_2)
+#define MX23_PAD_ROTARYB__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_2)
+
+/* MUXSEL_GPIO */
+#define MX23_PAD_GPMI_D00__GPIO_0_0		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D01__GPIO_0_1		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D02__GPIO_0_2		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D03__GPIO_0_3		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D04__GPIO_0_4		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D05__GPIO_0_5		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D06__GPIO_0_6		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D07__GPIO_0_7		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D08__GPIO_0_8		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D09__GPIO_0_9		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D10__GPIO_0_10		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D11__GPIO_0_11		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D12__GPIO_0_12		MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D13__GPIO_0_13		MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D14__GPIO_0_14		MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D15__GPIO_0_15		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CLE__GPIO_0_16		MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_ALE__GPIO_0_17		MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE2N__GPIO_0_18		MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY0__GPIO_0_19		MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY1__GPIO_0_20		MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY2__GPIO_0_21		MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY3__GPIO_0_22		MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_WPN__GPIO_0_23		MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_WRN__GPIO_0_24		MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDN__GPIO_0_25		MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_CTS__GPIO_0_26		MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_RTS__GPIO_0_27		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_RX__GPIO_0_28		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_TX__GPIO_0_29		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_I2C_SCL__GPIO_0_30		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
+#define MX23_PAD_I2C_SDA__GPIO_0_31		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
+
+#define MX23_PAD_LCD_D00__GPIO_1_0		MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D01__GPIO_1_1		MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D02__GPIO_1_2		MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D03__GPIO_1_3		MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D04__GPIO_1_4		MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D05__GPIO_1_5		MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D06__GPIO_1_6		MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D07__GPIO_1_7		MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D08__GPIO_1_8		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D09__GPIO_1_9		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D10__GPIO_1_10		MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D11__GPIO_1_11		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D12__GPIO_1_12		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D13__GPIO_1_13		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D14__GPIO_1_14		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D15__GPIO_1_15		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D16__GPIO_1_16		MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D17__GPIO_1_17		MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_RESET__GPIO_1_18		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_RS__GPIO_1_19		MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_WR__GPIO_1_20		MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_CS__GPIO_1_21		MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_DOTCK__GPIO_1_22		MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_ENABLE__GPIO_1_23		MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_HSYNC__GPIO_1_24		MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_VSYNC__GPIO_1_25		MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM0__GPIO_1_26		MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM1__GPIO_1_27		MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM2__GPIO_1_28		MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM3__GPIO_1_29		MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM4__GPIO_1_30		MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
+
+#define MX23_PAD_SSP1_CMD__GPIO_2_0		MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DETECT__GPIO_2_1		MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA0__GPIO_2_2		MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA1__GPIO_2_3		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA2__GPIO_2_4		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA3__GPIO_2_5		MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_SCK__GPIO_2_6		MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_ROTARYA__GPIO_2_7		MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_ROTARYB__GPIO_2_8		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A00__GPIO_2_9		MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A01__GPIO_2_10		MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A02__GPIO_2_11		MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A03__GPIO_2_12		MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A04__GPIO_2_13		MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A05__GPIO_2_14		MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A06__GPIO_2_15		MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A07__GPIO_2_16		MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A08__GPIO_2_17		MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A09__GPIO_2_18		MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A10__GPIO_2_19		MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A11__GPIO_2_20		MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A12__GPIO_2_21		MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_BA0__GPIO_2_22		MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_BA1__GPIO_2_23		MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CASN__GPIO_2_24		MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CE0N__GPIO_2_25		MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CE1N__GPIO_2_26		MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE1N__GPIO_2_27		MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE0N__GPIO_2_28		MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CKE__GPIO_2_29		MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_RASN__GPIO_2_30		MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_WEN__GPIO_2_31		MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
+
+#endif /* __MACH_IOMUX_MX23_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-apbh.h b/arch/arm/include/asm/arch-mxs/regs-apbh.h
index e18e677..fcef4b8 100644
--- a/arch/arm/include/asm/arch-mxs/regs-apbh.h
+++ b/arch/arm/include/asm/arch-mxs/regs-apbh.h
@@ -29,11 +29,92 @@
 #include <asm/arch/regs-common.h>
 
 #ifndef	__ASSEMBLY__
+
+#if defined(CONFIG_MX23)
 struct mxs_apbh_regs {
 	mxs_reg_32(hw_apbh_ctrl0)
 	mxs_reg_32(hw_apbh_ctrl1)
 	mxs_reg_32(hw_apbh_ctrl2)
 	mxs_reg_32(hw_apbh_channel_ctrl)
+
+	union {
+	struct {
+		mxs_reg_32(hw_apbh_ch_curcmdar)
+		mxs_reg_32(hw_apbh_ch_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch_cmd)
+		mxs_reg_32(hw_apbh_ch_bar)
+		mxs_reg_32(hw_apbh_ch_sema)
+		mxs_reg_32(hw_apbh_ch_debug1)
+		mxs_reg_32(hw_apbh_ch_debug2)
+	} ch[8];
+	struct {
+		mxs_reg_32(hw_apbh_ch0_curcmdar)
+		mxs_reg_32(hw_apbh_ch0_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch0_cmd)
+		mxs_reg_32(hw_apbh_ch0_bar)
+		mxs_reg_32(hw_apbh_ch0_sema)
+		mxs_reg_32(hw_apbh_ch0_debug1)
+		mxs_reg_32(hw_apbh_ch0_debug2)
+		mxs_reg_32(hw_apbh_ch1_curcmdar)
+		mxs_reg_32(hw_apbh_ch1_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch1_cmd)
+		mxs_reg_32(hw_apbh_ch1_bar)
+		mxs_reg_32(hw_apbh_ch1_sema)
+		mxs_reg_32(hw_apbh_ch1_debug1)
+		mxs_reg_32(hw_apbh_ch1_debug2)
+		mxs_reg_32(hw_apbh_ch2_curcmdar)
+		mxs_reg_32(hw_apbh_ch2_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch2_cmd)
+		mxs_reg_32(hw_apbh_ch2_bar)
+		mxs_reg_32(hw_apbh_ch2_sema)
+		mxs_reg_32(hw_apbh_ch2_debug1)
+		mxs_reg_32(hw_apbh_ch2_debug2)
+		mxs_reg_32(hw_apbh_ch3_curcmdar)
+		mxs_reg_32(hw_apbh_ch3_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch3_cmd)
+		mxs_reg_32(hw_apbh_ch3_bar)
+		mxs_reg_32(hw_apbh_ch3_sema)
+		mxs_reg_32(hw_apbh_ch3_debug1)
+		mxs_reg_32(hw_apbh_ch3_debug2)
+		mxs_reg_32(hw_apbh_ch4_curcmdar)
+		mxs_reg_32(hw_apbh_ch4_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch4_cmd)
+		mxs_reg_32(hw_apbh_ch4_bar)
+		mxs_reg_32(hw_apbh_ch4_sema)
+		mxs_reg_32(hw_apbh_ch4_debug1)
+		mxs_reg_32(hw_apbh_ch4_debug2)
+		mxs_reg_32(hw_apbh_ch5_curcmdar)
+		mxs_reg_32(hw_apbh_ch5_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch5_cmd)
+		mxs_reg_32(hw_apbh_ch5_bar)
+		mxs_reg_32(hw_apbh_ch5_sema)
+		mxs_reg_32(hw_apbh_ch5_debug1)
+		mxs_reg_32(hw_apbh_ch5_debug2)
+		mxs_reg_32(hw_apbh_ch6_curcmdar)
+		mxs_reg_32(hw_apbh_ch6_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch6_cmd)
+		mxs_reg_32(hw_apbh_ch6_bar)
+		mxs_reg_32(hw_apbh_ch6_sema)
+		mxs_reg_32(hw_apbh_ch6_debug1)
+		mxs_reg_32(hw_apbh_ch6_debug2)
+		mxs_reg_32(hw_apbh_ch7_curcmdar)
+		mxs_reg_32(hw_apbh_ch7_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch7_cmd)
+		mxs_reg_32(hw_apbh_ch7_bar)
+		mxs_reg_32(hw_apbh_ch7_sema)
+		mxs_reg_32(hw_apbh_ch7_debug1)
+		mxs_reg_32(hw_apbh_ch7_debug2)
+	};
+	};
+	mxs_reg_32(hw_apbh_version)
+};
+
+#elif defined(CONFIG_MX28)
+struct mxs_apbh_regs {
+	mxs_reg_32(hw_apbh_ctrl0)
+	mxs_reg_32(hw_apbh_ctrl1)
+	mxs_reg_32(hw_apbh_ctrl2)
+	mxs_reg_32(hw_apbh_channel_ctrl)
 	mxs_reg_32(hw_apbh_devsel)
 	mxs_reg_32(hw_apbh_dma_burst_size)
 	mxs_reg_32(hw_apbh_debug)
@@ -169,10 +250,26 @@
 };
 #endif
 
+#endif
+
 #define	APBH_CTRL0_SFTRST				(1 << 31)
 #define	APBH_CTRL0_CLKGATE				(1 << 30)
 #define	APBH_CTRL0_AHB_BURST8_EN			(1 << 29)
 #define	APBH_CTRL0_APB_BURST_EN				(1 << 28)
+#if defined(CONFIG_MX23)
+#define	APBH_CTRL0_RSVD0_MASK				(0xf << 24)
+#define	APBH_CTRL0_RSVD0_OFFSET				24
+#define	APBH_CTRL0_RESET_CHANNEL_MASK			(0xff << 16)
+#define	APBH_CTRL0_RESET_CHANNEL_OFFSET			16
+#define	APBH_CTRL0_CLKGATE_CHANNEL_MASK			(0xff << 8)
+#define	APBH_CTRL0_CLKGATE_CHANNEL_OFFSET		8
+#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP0			0x02
+#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP1			0x04
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND0		0x10
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND1		0x20
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND2		0x40
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND3		0x80
+#elif defined(CONFIG_MX28)
 #define	APBH_CTRL0_RSVD0_MASK				(0xfff << 16)
 #define	APBH_CTRL0_RSVD0_OFFSET				16
 #define	APBH_CTRL0_CLKGATE_CHANNEL_MASK			0xffff
@@ -191,6 +288,7 @@
 #define	APBH_CTRL0_CLKGATE_CHANNEL_NAND7		0x0800
 #define	APBH_CTRL0_CLKGATE_CHANNEL_HSADC		0x1000
 #define	APBH_CTRL0_CLKGATE_CHANNEL_LCDIF		0x2000
+#endif
 
 #define	APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN			(1 << 31)
 #define	APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN			(1 << 30)
@@ -260,6 +358,7 @@
 #define	APBH_CTRL2_CH1_ERROR_IRQ			(1 << 1)
 #define	APBH_CTRL2_CH0_ERROR_IRQ			(1 << 0)
 
+#if defined(CONFIG_MX28)
 #define	APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK		(0xffff << 16)
 #define	APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET		16
 #define	APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0		(0x0001 << 16)
@@ -292,7 +391,26 @@
 #define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7		0x0800
 #define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC		0x1000
 #define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF		0x2000
+#endif
 
+#if defined(CONFIG_MX23)
+#define	APBH_DEVSEL_CH7_MASK				(0xf << 28)
+#define	APBH_DEVSEL_CH7_OFFSET				28
+#define	APBH_DEVSEL_CH6_MASK				(0xf << 24)
+#define	APBH_DEVSEL_CH6_OFFSET				24
+#define	APBH_DEVSEL_CH5_MASK				(0xf << 20)
+#define	APBH_DEVSEL_CH5_OFFSET				20
+#define	APBH_DEVSEL_CH4_MASK				(0xf << 16)
+#define	APBH_DEVSEL_CH4_OFFSET				16
+#define	APBH_DEVSEL_CH3_MASK				(0xf << 12)
+#define	APBH_DEVSEL_CH3_OFFSET				12
+#define	APBH_DEVSEL_CH2_MASK				(0xf << 8)
+#define	APBH_DEVSEL_CH2_OFFSET				8
+#define	APBH_DEVSEL_CH1_MASK				(0xf << 4)
+#define	APBH_DEVSEL_CH1_OFFSET				4
+#define	APBH_DEVSEL_CH0_MASK				(0xf << 0)
+#define	APBH_DEVSEL_CH0_OFFSET				0
+#elif defined(CONFIG_MX28)
 #define	APBH_DEVSEL_CH15_MASK				(0x3 << 30)
 #define	APBH_DEVSEL_CH15_OFFSET				30
 #define	APBH_DEVSEL_CH14_MASK				(0x3 << 28)
@@ -325,7 +443,9 @@
 #define	APBH_DEVSEL_CH1_OFFSET				2
 #define	APBH_DEVSEL_CH0_MASK				(0x3 << 0)
 #define	APBH_DEVSEL_CH0_OFFSET				0
+#endif
 
+#if defined(CONFIG_MX28)
 #define	APBH_DMA_BURST_SIZE_CH15_MASK			(0x3 << 30)
 #define	APBH_DMA_BURST_SIZE_CH15_OFFSET			30
 #define	APBH_DMA_BURST_SIZE_CH14_MASK			(0x3 << 28)
@@ -377,6 +497,7 @@
 #define	APBH_DMA_BURST_SIZE_CH0_BURST8			0x2
 
 #define	APBH_DEBUG_GPMI_ONE_FIFO			(1 << 0)
+#endif
 
 #define	APBH_CHn_CURCMDAR_CMD_ADDR_MASK			0xffffffff
 #define	APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET		0
diff --git a/arch/arm/include/asm/arch-mxs/regs-base.h b/arch/arm/include/asm/arch-mxs/regs-base.h
index dbdcc2b..2d9f96b 100644
--- a/arch/arm/include/asm/arch-mxs/regs-base.h
+++ b/arch/arm/include/asm/arch-mxs/regs-base.h
@@ -1,5 +1,5 @@
 /*
- * Freescale i.MX28 Peripheral Base Addresses
+ * Freescale i.MX23/i.MX28 Peripheral Base Addresses
  *
  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  * on behalf of DENX Software Engineering GmbH
@@ -25,12 +25,55 @@
  *
  */
 
-#ifndef __MX28_REGS_BASE_H__
-#define __MX28_REGS_BASE_H__
+#ifndef __MXS_REGS_BASE_H__
+#define __MXS_REGS_BASE_H__
 
 /*
- * Register base address
+ * Register base addresses for i.MX23
  */
+#if defined(CONFIG_MX23)
+#define	MXS_ICOLL_BASE		0x80000000
+#define	MXS_APBH_BASE		0x80004000
+#define	MXS_ECC8_BASE		0x80008000
+#define	MXS_BCH_BASE		0x8000A000
+#define	MXS_GPMI_BASE		0x8000C000
+#define	MXS_SSP0_BASE		0x80010000
+#define	MXS_SSP1_BASE		0x80034000
+#define	MXS_ETM_BASE		0x80014000
+#define	MXS_PINCTRL_BASE	0x80018000
+#define	MXS_DIGCTL_BASE		0x8001C000
+#define	MXS_EMI_BASE		0x80020000
+#define	MXS_APBX_BASE		0x80024000
+#define	MXS_DCP_BASE		0x80028000
+#define	MXS_PXP_BASE		0x8002A000
+#define	MXS_OCOTP_BASE		0x8002C000
+#define	MXS_AXI_BASE		0x8002E000
+#define	MXS_LCDIF_BASE		0x80030000
+#define	MXS_SSP1_BASE		0x80034000
+#define	MXS_TVENC_BASE		0x80038000
+#define	MXS_CLKCTRL_BASE	0x80040000
+#define	MXS_SAIF0_BASE		0x80042000
+#define	MXS_POWER_BASE		0x80044000
+#define	MXS_SAIF1_BASE		0x80046000
+#define	MXS_AUDIOOUT_BASE	0x80048000
+#define	MXS_AUDIOIN_BASE	0x8004C000
+#define	MXS_LRADC_BASE		0x80050000
+#define	MXS_SPDIF_BASE		0x80054000
+#define	MXS_I2C0_BASE		0x80058000
+#define	MXS_RTC_BASE		0x8005C000
+#define	MXS_PWM_BASE		0x80064000
+#define	MXS_TIMROT_BASE		0x80068000
+#define	MXS_UARTAPP0_BASE	0x8006C000
+#define	MXS_UARTAPP1_BASE	0x8006E000
+#define	MXS_UARTDBG_BASE	0x80070000
+#define	MXS_USBPHY0_BASE	0x8007C000
+#define	MXS_USBCTRL0_BASE	0x80080000
+#define	MXS_DRAM_BASE		0x800E0000
+
+/*
+ * Register base addresses for i.MX28
+ */
+#elif defined(CONFIG_MX28)
 #define	MXS_ICOL_BASE		0x80000000
 #define	MXS_HSADC_BASE		0x80002000
 #define	MXS_APBH_BASE		0x80004000
@@ -84,5 +127,8 @@
 #define	MXS_DRAM_BASE		0x800E0000
 #define	MXS_ENET0_BASE		0x800F0000
 #define	MXS_ENET1_BASE		0x800F4000
+#else
+#error Unkown SoC. Please set CONFIG_MX23 or CONFIG_MX28
+#endif
 
-#endif /* __MX28_REGS_BASE_H__ */
+#endif /* __MXS_REGS_BASE_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
new file mode 100644
index 0000000..62810ec
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
@@ -0,0 +1,221 @@
+/*
+ * Freescale i.MX23 CLKCTRL Register Definitions
+ *
+ * Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#ifndef __MX23_REGS_CLKCTRL_H__
+#define __MX23_REGS_CLKCTRL_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_clkctrl_regs {
+	mxs_reg_32(hw_clkctrl_pll0ctrl0)	/* 0x00 */
+	uint32_t	hw_clkctrl_pll0ctrl1;	/* 0x10 */
+	uint32_t	reserved_pll0ctrl1[3];	/* 0x14-0x1c */
+	mxs_reg_32(hw_clkctrl_cpu)		/* 0x20 */
+	mxs_reg_32(hw_clkctrl_hbus)		/* 0x30 */
+	mxs_reg_32(hw_clkctrl_xbus)		/* 0x40 */
+	mxs_reg_32(hw_clkctrl_xtal)		/* 0x50 */
+	mxs_reg_32(hw_clkctrl_pix)		/* 0x60 */
+	mxs_reg_32(hw_clkctrl_ssp0)		/* 0x70 */
+	mxs_reg_32(hw_clkctrl_gpmi)		/* 0x80 */
+	mxs_reg_32(hw_clkctrl_spdif)		/* 0x90 */
+	mxs_reg_32(hw_clkctrl_emi)		/* 0xa0 */
+
+	uint32_t	reserved1[4];
+
+	mxs_reg_32(hw_clkctrl_saif0)		/* 0xc0 */
+	mxs_reg_32(hw_clkctrl_tv)		/* 0xd0 */
+	mxs_reg_32(hw_clkctrl_etm)		/* 0xe0 */
+	mxs_reg_8(hw_clkctrl_frac0)		/* 0xf0 */
+	mxs_reg_8(hw_clkctrl_frac1)		/* 0x100 */
+	mxs_reg_32(hw_clkctrl_clkseq)		/* 0x110 */
+	mxs_reg_32(hw_clkctrl_reset)		/* 0x120 */
+	mxs_reg_32(hw_clkctrl_status)		/* 0x130 */
+	mxs_reg_32(hw_clkctrl_version)		/* 0x140 */
+};
+#endif
+
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_MASK		(0x3 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET	28
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT	(0x0 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2	(0x1 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05	(0x2 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED	(0x3 << 28)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_MASK		(0x3 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET		24
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT	(0x0 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2	(0x1 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05	(0x2 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED	(0x3 << 24)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_MASK		(0x3 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET	20
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT	(0x0 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER		(0x1 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST	(0x2 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED	(0x3 << 20)
+#define	CLKCTRL_PLL0CTRL0_EN_USB_CLKS		(1 << 18)
+#define	CLKCTRL_PLL0CTRL0_POWER			(1 << 16)
+
+#define	CLKCTRL_PLL0CTRL1_LOCK			(1 << 31)
+#define	CLKCTRL_PLL0CTRL1_FORCE_LOCK		(1 << 30)
+#define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK	0xffff
+#define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET	0
+
+#define	CLKCTRL_CPU_BUSY_REF_XTAL		(1 << 29)
+#define	CLKCTRL_CPU_BUSY_REF_CPU		(1 << 28)
+#define	CLKCTRL_CPU_DIV_XTAL_FRAC_EN		(1 << 26)
+#define	CLKCTRL_CPU_DIV_XTAL_MASK		(0x3ff << 16)
+#define	CLKCTRL_CPU_DIV_XTAL_OFFSET		16
+#define	CLKCTRL_CPU_INTERRUPT_WAIT		(1 << 12)
+#define	CLKCTRL_CPU_DIV_CPU_FRAC_EN		(1 << 10)
+#define	CLKCTRL_CPU_DIV_CPU_MASK		0x3f
+#define	CLKCTRL_CPU_DIV_CPU_OFFSET		0
+
+#define	CLKCTRL_HBUS_BUSY			(1 << 29)
+#define	CLKCTRL_HBUS_DCP_AS_ENABLE		(1 << 28)
+#define	CLKCTRL_HBUS_PXP_AS_ENABLE		(1 << 27)
+#define	CLKCTRL_HBUS_APBHDMA_AS_ENABLE		(1 << 26)
+#define	CLKCTRL_HBUS_APBXDMA_AS_ENABLE		(1 << 25)
+#define	CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE	(1 << 24)
+#define	CLKCTRL_HBUS_TRAFFIC_AS_ENABLE		(1 << 23)
+#define	CLKCTRL_HBUS_CPU_DATA_AS_ENABLE		(1 << 22)
+#define	CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE	(1 << 21)
+#define	CLKCTRL_HBUS_AUTO_SLOW_MODE		(1 << 20)
+#define	CLKCTRL_HBUS_SLOW_DIV_MASK		(0x7 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_OFFSET		16
+#define	CLKCTRL_HBUS_SLOW_DIV_BY1		(0x0 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY2		(0x1 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY4		(0x2 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY8		(0x3 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY16		(0x4 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY32		(0x5 << 16)
+#define	CLKCTRL_HBUS_DIV_FRAC_EN		(1 << 5)
+#define	CLKCTRL_HBUS_DIV_MASK			0x1f
+#define	CLKCTRL_HBUS_DIV_OFFSET			0
+
+#define	CLKCTRL_XBUS_BUSY			(1 << 31)
+#define	CLKCTRL_XBUS_DIV_FRAC_EN		(1 << 10)
+#define	CLKCTRL_XBUS_DIV_MASK			0x3ff
+#define	CLKCTRL_XBUS_DIV_OFFSET			0
+
+#define	CLKCTRL_XTAL_UART_CLK_GATE		(1 << 31)
+#define	CLKCTRL_XTAL_FILT_CLK24M_GATE		(1 << 30)
+#define	CLKCTRL_XTAL_PWM_CLK24M_GATE		(1 << 29)
+#define	CLKCTRL_XTAL_DRI_CLK24M_GATE		(1 << 28)
+#define	CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE		(1 << 27)
+#define	CLKCTRL_XTAL_TIMROT_CLK32K_GATE		(1 << 26)
+#define	CLKCTRL_XTAL_DIV_UART_MASK		0x3
+#define	CLKCTRL_XTAL_DIV_UART_OFFSET		0
+
+#define	CLKCTRL_PIX_CLKGATE			(1 << 31)
+#define	CLKCTRL_PIX_BUSY			(1 << 29)
+#define	CLKCTRL_PIX_DIV_FRAC_EN			(1 << 12)
+#define	CLKCTRL_PIX_DIV_MASK			0xfff
+#define	CLKCTRL_PIX_DIV_OFFSET			0
+
+#define	CLKCTRL_SSP_CLKGATE			(1 << 31)
+#define	CLKCTRL_SSP_BUSY			(1 << 29)
+#define	CLKCTRL_SSP_DIV_FRAC_EN			(1 << 9)
+#define	CLKCTRL_SSP_DIV_MASK			0x1ff
+#define	CLKCTRL_SSP_DIV_OFFSET			0
+
+#define	CLKCTRL_GPMI_CLKGATE			(1 << 31)
+#define	CLKCTRL_GPMI_BUSY			(1 << 29)
+#define	CLKCTRL_GPMI_DIV_FRAC_EN		(1 << 10)
+#define	CLKCTRL_GPMI_DIV_MASK			0x3ff
+#define	CLKCTRL_GPMI_DIV_OFFSET			0
+
+#define	CLKCTRL_SPDIF_CLKGATE			(1 << 31)
+
+#define	CLKCTRL_EMI_CLKGATE			(1 << 31)
+#define	CLKCTRL_EMI_SYNC_MODE_EN		(1 << 30)
+#define	CLKCTRL_EMI_BUSY_REF_XTAL		(1 << 29)
+#define	CLKCTRL_EMI_BUSY_REF_EMI		(1 << 28)
+#define	CLKCTRL_EMI_BUSY_REF_CPU		(1 << 27)
+#define	CLKCTRL_EMI_BUSY_SYNC_MODE		(1 << 26)
+#define	CLKCTRL_EMI_BUSY_DCC_RESYNC		(1 << 17)
+#define	CLKCTRL_EMI_DCC_RESYNC_ENABLE		(1 << 16)
+#define	CLKCTRL_EMI_DIV_XTAL_MASK		(0xf << 8)
+#define	CLKCTRL_EMI_DIV_XTAL_OFFSET		8
+#define	CLKCTRL_EMI_DIV_EMI_MASK		0x3f
+#define	CLKCTRL_EMI_DIV_EMI_OFFSET		0
+
+#define	CLKCTRL_IR_CLKGATE			(1 << 31)
+#define	CLKCTRL_IR_AUTO_DIV			(1 << 29)
+#define	CLKCTRL_IR_IR_BUSY			(1 << 28)
+#define	CLKCTRL_IR_IROV_BUSY			(1 << 27)
+#define	CLKCTRL_IR_IROV_DIV_MASK		(0x1ff << 16)
+#define	CLKCTRL_IR_IROV_DIV_OFFSET		16
+#define	CLKCTRL_IR_IR_DIV_MASK			0x3ff
+#define	CLKCTRL_IR_IR_DIV_OFFSET		0
+
+#define	CLKCTRL_SAIF0_CLKGATE			(1 << 31)
+#define	CLKCTRL_SAIF0_BUSY			(1 << 29)
+#define	CLKCTRL_SAIF0_DIV_FRAC_EN		(1 << 16)
+#define	CLKCTRL_SAIF0_DIV_MASK			0xffff
+#define	CLKCTRL_SAIF0_DIV_OFFSET		0
+
+#define	CLKCTRL_TV_CLK_TV108M_GATE		(1 << 31)
+#define	CLKCTRL_TV_CLK_TV_GATE			(1 << 30)
+
+#define	CLKCTRL_ETM_CLKGATE			(1 << 31)
+#define	CLKCTRL_ETM_BUSY			(1 << 29)
+#define	CLKCTRL_ETM_DIV_FRAC_EN			(1 << 6)
+#define	CLKCTRL_ETM_DIV_MASK			0x3f
+#define	CLKCTRL_ETM_DIV_OFFSET			0
+
+#define	CLKCTRL_FRAC_CLKGATE			(1 << 7)
+#define	CLKCTRL_FRAC_STABLE			(1 << 6)
+#define	CLKCTRL_FRAC_FRAC_MASK			0x3f
+#define	CLKCTRL_FRAC_FRAC_OFFSET		0
+#define	CLKCTRL_FRAC0_CPU			0
+#define	CLKCTRL_FRAC0_EMI			1
+#define	CLKCTRL_FRAC0_PIX			2
+#define	CLKCTRL_FRAC0_IO0			3
+#define	CLKCTRL_FRAC1_VID			3
+
+#define	CLKCTRL_CLKSEQ_BYPASS_ETM		(1 << 8)
+#define	CLKCTRL_CLKSEQ_BYPASS_CPU		(1 << 7)
+#define	CLKCTRL_CLKSEQ_BYPASS_EMI		(1 << 6)
+#define	CLKCTRL_CLKSEQ_BYPASS_SSP0		(1 << 5)
+#define	CLKCTRL_CLKSEQ_BYPASS_GPMI		(1 << 4)
+#define	CLKCTRL_CLKSEQ_BYPASS_IR		(1 << 3)
+#define	CLKCTRL_CLKSEQ_BYPASS_PIX		(1 << 1)
+#define	CLKCTRL_CLKSEQ_BYPASS_SAIF		(1 << 0)
+
+#define	CLKCTRL_RESET_CHIP			(1 << 1)
+#define	CLKCTRL_RESET_DIG			(1 << 0)
+
+#define	CLKCTRL_STATUS_CPU_LIMIT_MASK		(0x3 << 30)
+#define	CLKCTRL_STATUS_CPU_LIMIT_OFFSET		30
+
+#define	CLKCTRL_VERSION_MAJOR_MASK		(0xff << 24)
+#define	CLKCTRL_VERSION_MAJOR_OFFSET		24
+#define	CLKCTRL_VERSION_MINOR_MASK		(0xff << 16)
+#define	CLKCTRL_VERSION_MINOR_OFFSET		16
+#define	CLKCTRL_VERSION_STEP_MASK		0xffff
+#define	CLKCTRL_VERSION_STEP_OFFSET		0
+
+#endif /* __MX23_REGS_CLKCTRL_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-digctl.h b/arch/arm/include/asm/arch-mxs/regs-digctl.h
index e7cc4b4..d043325 100644
--- a/arch/arm/include/asm/arch-mxs/regs-digctl.h
+++ b/arch/arm/include/asm/arch-mxs/regs-digctl.h
@@ -154,6 +154,7 @@
 
 /* Product code identification */
 #define HW_DIGCTL_CHIPID_MASK	(0xffff << 16)
+#define HW_DIGCTL_CHIPID_MX23	(0x3780 << 16)
 #define HW_DIGCTL_CHIPID_MX28	(0x2800 << 16)
 
 #endif /* __MX28_REGS_DIGCTL_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h b/arch/arm/include/asm/arch-mxs/regs-power-mx23.h
new file mode 100644
index 0000000..51a981a
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-power-mx23.h
@@ -0,0 +1,358 @@
+/*
+ * Freescale i.MX23 Power Controller Register Definitions
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#ifndef __MX23_REGS_POWER_H__
+#define __MX23_REGS_POWER_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_power_regs {
+	mxs_reg_32(hw_power_ctrl)
+	mxs_reg_32(hw_power_5vctrl)
+	mxs_reg_32(hw_power_minpwr)
+	mxs_reg_32(hw_power_charge)
+	uint32_t	hw_power_vdddctrl;
+	uint32_t	reserved_vddd[3];
+	uint32_t	hw_power_vddactrl;
+	uint32_t	reserved_vdda[3];
+	uint32_t	hw_power_vddioctrl;
+	uint32_t	reserved_vddio[3];
+	uint32_t	hw_power_vddmemctrl;
+	uint32_t	reserved_vddmem[3];
+	uint32_t	hw_power_dcdc4p2;
+	uint32_t	reserved_dcdc4p2[3];
+	uint32_t	hw_power_misc;
+	uint32_t	reserved_misc[3];
+	uint32_t	hw_power_dclimits;
+	uint32_t	reserved_dclimits[3];
+	mxs_reg_32(hw_power_loopctrl)
+	uint32_t	hw_power_sts;
+	uint32_t	reserved_sts[3];
+	mxs_reg_32(hw_power_speed)
+	uint32_t	hw_power_battmonitor;
+	uint32_t	reserved_battmonitor[3];
+
+	uint32_t	reserved1[4];
+
+	mxs_reg_32(hw_power_reset)
+
+	uint32_t	reserved2[4];
+
+	mxs_reg_32(hw_power_special)
+	mxs_reg_32(hw_power_version)
+};
+#endif
+
+#define	POWER_CTRL_CLKGATE				(1 << 30)
+#define	POWER_CTRL_PSWITCH_MID_TRAN			(1 << 27)
+#define	POWER_CTRL_DCDC4P2_BO_IRQ			(1 << 24)
+#define	POWER_CTRL_ENIRQ_DCDC4P2_BO			(1 << 23)
+#define	POWER_CTRL_VDD5V_DROOP_IRQ			(1 << 22)
+#define	POWER_CTRL_ENIRQ_VDD5V_DROOP			(1 << 21)
+#define	POWER_CTRL_PSWITCH_IRQ				(1 << 20)
+#define	POWER_CTRL_PSWITCH_IRQ_SRC			(1 << 19)
+#define	POWER_CTRL_POLARITY_PSWITCH			(1 << 18)
+#define	POWER_CTRL_ENIRQ_PSWITCH			(1 << 17)
+#define	POWER_CTRL_POLARITY_DC_OK			(1 << 16)
+#define	POWER_CTRL_DC_OK_IRQ				(1 << 15)
+#define	POWER_CTRL_ENIRQ_DC_OK				(1 << 14)
+#define	POWER_CTRL_BATT_BO_IRQ				(1 << 13)
+#define	POWER_CTRL_ENIRQ_BATT_BO			(1 << 12)
+#define	POWER_CTRL_VDDIO_BO_IRQ				(1 << 11)
+#define	POWER_CTRL_ENIRQ_VDDIO_BO			(1 << 10)
+#define	POWER_CTRL_VDDA_BO_IRQ				(1 << 9)
+#define	POWER_CTRL_ENIRQ_VDDA_BO			(1 << 8)
+#define	POWER_CTRL_VDDD_BO_IRQ				(1 << 7)
+#define	POWER_CTRL_ENIRQ_VDDD_BO			(1 << 6)
+#define	POWER_CTRL_POLARITY_VBUSVALID			(1 << 5)
+#define	POWER_CTRL_VBUS_VALID_IRQ			(1 << 4)
+#define	POWER_CTRL_ENIRQ_VBUS_VALID			(1 << 3)
+#define	POWER_CTRL_POLARITY_VDD5V_GT_VDDIO		(1 << 2)
+#define	POWER_CTRL_VDD5V_GT_VDDIO_IRQ			(1 << 1)
+#define	POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO			(1 << 0)
+
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_MASK		(0x3 << 28)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET		28
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V3			(0x0 << 28)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V4			(0x1 << 28)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V5			(0x2 << 28)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V7			(0x3 << 28)
+#define	POWER_5VCTRL_HEADROOM_ADJ_MASK			(0x7 << 24)
+#define	POWER_5VCTRL_HEADROOM_ADJ_OFFSET		24
+#define	POWER_5VCTRL_PWD_CHARGE_4P2_MASK		(0x1 << 20)
+#define	POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET		20
+#define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK		(0x3f << 12)
+#define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET		12
+#define	POWER_5VCTRL_VBUSVALID_TRSH_MASK		(0x7 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_OFFSET		8
+#define	POWER_5VCTRL_VBUSVALID_TRSH_2V9			(0x0 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V0			(0x1 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V1			(0x2 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V2			(0x3 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V3			(0x4 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V4			(0x5 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V5			(0x6 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V6			(0x7 << 8)
+#define	POWER_5VCTRL_PWDN_5VBRNOUT			(1 << 7)
+#define	POWER_5VCTRL_ENABLE_LINREG_ILIMIT		(1 << 6)
+#define	POWER_5VCTRL_DCDC_XFER				(1 << 5)
+#define	POWER_5VCTRL_VBUSVALID_5VDETECT			(1 << 4)
+#define	POWER_5VCTRL_VBUSVALID_TO_B			(1 << 3)
+#define	POWER_5VCTRL_ILIMIT_EQ_ZERO			(1 << 2)
+#define	POWER_5VCTRL_PWRUP_VBUS_CMPS			(1 << 1)
+#define	POWER_5VCTRL_ENABLE_DCDC			(1 << 0)
+
+#define	POWER_MINPWR_LOWPWR_4P2				(1 << 14)
+#define	POWER_MINPWR_VDAC_DUMP_CTRL			(1 << 13)
+#define	POWER_MINPWR_PWD_BO				(1 << 12)
+#define	POWER_MINPWR_USE_VDDXTAL_VBG			(1 << 11)
+#define	POWER_MINPWR_PWD_ANA_CMPS			(1 << 10)
+#define	POWER_MINPWR_ENABLE_OSC				(1 << 9)
+#define	POWER_MINPWR_SELECT_OSC				(1 << 8)
+#define	POWER_MINPWR_VBG_OFF				(1 << 7)
+#define	POWER_MINPWR_DOUBLE_FETS			(1 << 6)
+#define	POWER_MINPWR_HALFFETS				(1 << 5)
+#define	POWER_MINPWR_LESSANA_I				(1 << 4)
+#define	POWER_MINPWR_PWD_XTAL24				(1 << 3)
+#define	POWER_MINPWR_DC_STOPCLK				(1 << 2)
+#define	POWER_MINPWR_EN_DC_PFM				(1 << 1)
+#define	POWER_MINPWR_DC_HALFCLK				(1 << 0)
+
+#define	POWER_CHARGE_ADJ_VOLT_MASK			(0x7 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_OFFSET			24
+#define	POWER_CHARGE_ADJ_VOLT_M025P			(0x1 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_P050P			(0x2 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_M075P			(0x3 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_P025P			(0x4 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_M050P			(0x5 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_P075P			(0x6 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_M100P			(0x7 << 24)
+#define	POWER_CHARGE_ENABLE_LOAD			(1 << 22)
+#define	POWER_CHARGE_ENABLE_CHARGER_RESISTORS		(1 << 21)
+#define	POWER_CHARGE_ENABLE_FAULT_DETECT		(1 << 20)
+#define	POWER_CHARGE_CHRG_STS_OFF			(1 << 19)
+#define	POWER_CHARGE_USE_EXTERN_R			(1 << 17)
+#define	POWER_CHARGE_PWD_BATTCHRG			(1 << 16)
+#define	POWER_CHARGE_STOP_ILIMIT_MASK			(0xf << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_OFFSET			8
+#define	POWER_CHARGE_STOP_ILIMIT_10MA			(0x1 << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_20MA			(0x2 << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_50MA			(0x4 << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_100MA			(0x8 << 8)
+#define	POWER_CHARGE_BATTCHRG_I_MASK			0x3f
+#define	POWER_CHARGE_BATTCHRG_I_OFFSET			0
+#define	POWER_CHARGE_BATTCHRG_I_10MA			0x01
+#define	POWER_CHARGE_BATTCHRG_I_20MA			0x02
+#define	POWER_CHARGE_BATTCHRG_I_50MA			0x04
+#define	POWER_CHARGE_BATTCHRG_I_100MA			0x08
+#define	POWER_CHARGE_BATTCHRG_I_200MA			0x10
+#define	POWER_CHARGE_BATTCHRG_I_400MA			0x20
+
+#define	POWER_VDDDCTRL_ADJTN_MASK			(0xf << 28)
+#define	POWER_VDDDCTRL_ADJTN_OFFSET			28
+#define	POWER_VDDDCTRL_PWDN_BRNOUT			(1 << 23)
+#define	POWER_VDDDCTRL_DISABLE_STEPPING			(1 << 22)
+#define	POWER_VDDDCTRL_ENABLE_LINREG			(1 << 21)
+#define	POWER_VDDDCTRL_DISABLE_FET			(1 << 20)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_MASK		(0x3 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_OFFSET		16
+#define	POWER_VDDDCTRL_LINREG_OFFSET_0STEPS		(0x0 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 16)
+#define	POWER_VDDDCTRL_BO_OFFSET_MASK			(0x7 << 8)
+#define	POWER_VDDDCTRL_BO_OFFSET_OFFSET			8
+#define	POWER_VDDDCTRL_TRG_MASK				0x1f
+#define	POWER_VDDDCTRL_TRG_OFFSET			0
+
+#define	POWER_VDDACTRL_PWDN_BRNOUT			(1 << 19)
+#define	POWER_VDDACTRL_DISABLE_STEPPING			(1 << 18)
+#define	POWER_VDDACTRL_ENABLE_LINREG			(1 << 17)
+#define	POWER_VDDACTRL_DISABLE_FET			(1 << 16)
+#define	POWER_VDDACTRL_LINREG_OFFSET_MASK		(0x3 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_OFFSET		12
+#define	POWER_VDDACTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
+#define	POWER_VDDACTRL_BO_OFFSET_MASK			(0x7 << 8)
+#define	POWER_VDDACTRL_BO_OFFSET_OFFSET			8
+#define	POWER_VDDACTRL_TRG_MASK				0x1f
+#define	POWER_VDDACTRL_TRG_OFFSET			0
+
+#define	POWER_VDDIOCTRL_ADJTN_MASK			(0xf << 20)
+#define	POWER_VDDIOCTRL_ADJTN_OFFSET			20
+#define	POWER_VDDIOCTRL_PWDN_BRNOUT			(1 << 18)
+#define	POWER_VDDIOCTRL_DISABLE_STEPPING		(1 << 17)
+#define	POWER_VDDIOCTRL_DISABLE_FET			(1 << 16)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_MASK		(0x3 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET		12
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
+#define	POWER_VDDIOCTRL_BO_OFFSET_MASK			(0x7 << 8)
+#define	POWER_VDDIOCTRL_BO_OFFSET_OFFSET		8
+#define	POWER_VDDIOCTRL_TRG_MASK			0x1f
+#define	POWER_VDDIOCTRL_TRG_OFFSET			0
+
+#define	POWER_VDDMEMCTRL_PULLDOWN_ACTIVE		(1 << 10)
+#define	POWER_VDDMEMCTRL_ENABLE_ILIMIT			(1 << 9)
+#define	POWER_VDDMEMCTRL_ENABLE_LINREG			(1 << 8)
+#define	POWER_VDDMEMCTRL_TRG_MASK			0x1f
+#define	POWER_VDDMEMCTRL_TRG_OFFSET			0
+
+#define	POWER_DCDC4P2_DROPOUT_CTRL_MASK			(0xf << 28)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_OFFSET		28
+#define	POWER_DCDC4P2_DROPOUT_CTRL_200MV		(0x3 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_100MV		(0x2 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_50MV			(0x1 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_25MV			(0x0 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2		(0x0 << 28)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT	(0x1 << 28)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL		(0x2 << 28)
+#define	POWER_DCDC4P2_ISTEAL_THRESH_MASK		(0x3 << 24)
+#define	POWER_DCDC4P2_ISTEAL_THRESH_OFFSET		24
+#define	POWER_DCDC4P2_ENABLE_4P2			(1 << 23)
+#define	POWER_DCDC4P2_ENABLE_DCDC			(1 << 22)
+#define	POWER_DCDC4P2_HYST_DIR				(1 << 21)
+#define	POWER_DCDC4P2_HYST_THRESH			(1 << 20)
+#define	POWER_DCDC4P2_TRG_MASK				(0x7 << 16)
+#define	POWER_DCDC4P2_TRG_OFFSET			16
+#define	POWER_DCDC4P2_TRG_4V2				(0x0 << 16)
+#define	POWER_DCDC4P2_TRG_4V1				(0x1 << 16)
+#define	POWER_DCDC4P2_TRG_4V0				(0x2 << 16)
+#define	POWER_DCDC4P2_TRG_3V9				(0x3 << 16)
+#define	POWER_DCDC4P2_TRG_BATT				(0x4 << 16)
+#define	POWER_DCDC4P2_BO_MASK				(0x1f << 8)
+#define	POWER_DCDC4P2_BO_OFFSET				8
+#define	POWER_DCDC4P2_CMPTRIP_MASK			0x1f
+#define	POWER_DCDC4P2_CMPTRIP_OFFSET			0
+
+#define	POWER_MISC_FREQSEL_MASK				(0x7 << 4)
+#define	POWER_MISC_FREQSEL_OFFSET			4
+#define	POWER_MISC_FREQSEL_20MHZ			(0x1 << 4)
+#define	POWER_MISC_FREQSEL_24MHZ			(0x2 << 4)
+#define	POWER_MISC_FREQSEL_19MHZ			(0x3 << 4)
+#define	POWER_MISC_FREQSEL_14MHZ			(0x4 << 4)
+#define	POWER_MISC_FREQSEL_18MHZ			(0x5 << 4)
+#define	POWER_MISC_FREQSEL_21MHZ			(0x6 << 4)
+#define	POWER_MISC_FREQSEL_17MHZ			(0x7 << 4)
+#define	POWER_MISC_DISABLE_FET_BO_LOGIC			(1 << 3)
+#define	POWER_MISC_DELAY_TIMING				(1 << 2)
+#define	POWER_MISC_TEST					(1 << 1)
+#define	POWER_MISC_SEL_PLLCLK				(1 << 0)
+
+#define	POWER_DCLIMITS_POSLIMIT_BUCK_MASK		(0x7f << 8)
+#define	POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET		8
+#define	POWER_DCLIMITS_NEGLIMIT_MASK			0x7f
+#define	POWER_DCLIMITS_NEGLIMIT_OFFSET			0
+
+#define	POWER_LOOPCTRL_TOGGLE_DIF			(1 << 20)
+#define	POWER_LOOPCTRL_HYST_SIGN			(1 << 19)
+#define	POWER_LOOPCTRL_EN_CM_HYST			(1 << 18)
+#define	POWER_LOOPCTRL_EN_DF_HYST			(1 << 17)
+#define	POWER_LOOPCTRL_CM_HYST_THRESH			(1 << 16)
+#define	POWER_LOOPCTRL_DF_HYST_THRESH			(1 << 15)
+#define	POWER_LOOPCTRL_RCSCALE_THRESH			(1 << 14)
+#define	POWER_LOOPCTRL_EN_RCSCALE_MASK			(0x3 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_OFFSET		12
+#define	POWER_LOOPCTRL_EN_RCSCALE_DIS			(0x0 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_2X			(0x1 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_4X			(0x2 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_8X			(0x3 << 12)
+#define	POWER_LOOPCTRL_DC_FF_MASK			(0x7 << 8)
+#define	POWER_LOOPCTRL_DC_FF_OFFSET			8
+#define	POWER_LOOPCTRL_DC_R_MASK			(0xf << 4)
+#define	POWER_LOOPCTRL_DC_R_OFFSET			4
+#define	POWER_LOOPCTRL_DC_C_MASK			0x3
+#define	POWER_LOOPCTRL_DC_C_OFFSET			0
+#define	POWER_LOOPCTRL_DC_C_MAX				0x0
+#define	POWER_LOOPCTRL_DC_C_2X				0x1
+#define	POWER_LOOPCTRL_DC_C_4X				0x2
+#define	POWER_LOOPCTRL_DC_C_MIN				0x3
+
+#define	POWER_STS_PWRUP_SOURCE_MASK			(0x3f << 24)
+#define	POWER_STS_PWRUP_SOURCE_OFFSET			24
+#define	POWER_STS_PWRUP_SOURCE_5V			(0x20 << 24)
+#define	POWER_STS_PWRUP_SOURCE_RTC			(0x10 << 24)
+#define	POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH		(0x02 << 24)
+#define	POWER_STS_PWRUP_SOURCE_PSWITCH_MID		(0x01 << 24)
+#define	POWER_STS_PSWITCH_MASK				(0x3 << 20)
+#define	POWER_STS_PSWITCH_OFFSET			20
+#define	POWER_STS_AVALID0_STATUS			(1 << 17)
+#define	POWER_STS_BVALID0_STATUS			(1 << 16)
+#define	POWER_STS_VBUSVALID0_STATUS			(1 << 15)
+#define	POWER_STS_SESSEND0_STATUS			(1 << 14)
+#define	POWER_STS_BATT_BO				(1 << 13)
+#define	POWER_STS_VDD5V_FAULT				(1 << 12)
+#define	POWER_STS_CHRGSTS				(1 << 11)
+#define	POWER_STS_DCDC_4P2_BO				(1 << 10)
+#define	POWER_STS_DC_OK					(1 << 9)
+#define	POWER_STS_VDDIO_BO				(1 << 8)
+#define	POWER_STS_VDDA_BO				(1 << 7)
+#define	POWER_STS_VDDD_BO				(1 << 6)
+#define	POWER_STS_VDD5V_GT_VDDIO			(1 << 5)
+#define	POWER_STS_VDD5V_DROOP				(1 << 4)
+#define	POWER_STS_AVALID0				(1 << 3)
+#define	POWER_STS_BVALID0				(1 << 2)
+#define	POWER_STS_VBUSVALID0				(1 << 1)
+#define	POWER_STS_SESSEND0				(1 << 0)
+
+#define	POWER_SPEED_STATUS_MASK				(0xff << 16)
+#define	POWER_SPEED_STATUS_OFFSET			16
+#define	POWER_SPEED_CTRL_MASK				0x3
+#define	POWER_SPEED_CTRL_OFFSET				0
+#define	POWER_SPEED_CTRL_SS_OFF				0x0
+#define	POWER_SPEED_CTRL_SS_ON				0x1
+#define	POWER_SPEED_CTRL_SS_ENABLE			0x3
+
+#define	POWER_BATTMONITOR_BATT_VAL_MASK			(0x3ff << 16)
+#define	POWER_BATTMONITOR_BATT_VAL_OFFSET		16
+#define	POWER_BATTMONITOR_EN_BATADJ			(1 << 10)
+#define	POWER_BATTMONITOR_PWDN_BATTBRNOUT		(1 << 9)
+#define	POWER_BATTMONITOR_BRWNOUT_PWD			(1 << 8)
+#define	POWER_BATTMONITOR_BRWNOUT_LVL_MASK		0x1f
+#define	POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET		0
+
+#define	POWER_RESET_UNLOCK_MASK				(0xffff << 16)
+#define	POWER_RESET_UNLOCK_OFFSET			16
+#define	POWER_RESET_UNLOCK_KEY				(0x3e77 << 16)
+#define	POWER_RESET_PWD_OFF				(1 << 1)
+#define	POWER_RESET_PWD					(1 << 0)
+
+#define	POWER_DEBUG_VBUSVALIDPIOLOCK			(1 << 3)
+#define	POWER_DEBUG_AVALIDPIOLOCK			(1 << 2)
+#define	POWER_DEBUG_BVALIDPIOLOCK			(1 << 1)
+#define	POWER_DEBUG_SESSENDPIOLOCK			(1 << 0)
+
+#define	POWER_SPECIAL_TEST_MASK				0xffffffff
+#define	POWER_SPECIAL_TEST_OFFSET			0
+
+#define	POWER_VERSION_MAJOR_MASK			(0xff << 24)
+#define	POWER_VERSION_MAJOR_OFFSET			24
+#define	POWER_VERSION_MINOR_MASK			(0xff << 16)
+#define	POWER_VERSION_MINOR_OFFSET			16
+#define	POWER_VERSION_STEP_MASK				0xffff
+#define	POWER_VERSION_STEP_OFFSET			0
+
+#endif	/* __MX23_REGS_POWER_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h
index cf52a28..9b30f56 100644
--- a/arch/arm/include/asm/arch-mxs/regs-ssp.h
+++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h
@@ -28,10 +28,32 @@
 #include <asm/arch/regs-common.h>
 
 #ifndef	__ASSEMBLY__
+#if defined(CONFIG_MX23)
 struct mxs_ssp_regs {
 	mxs_reg_32(hw_ssp_ctrl0)
 	mxs_reg_32(hw_ssp_cmd0)
 	mxs_reg_32(hw_ssp_cmd1)
+	mxs_reg_32(hw_ssp_compref)
+	mxs_reg_32(hw_ssp_compmask)
+	mxs_reg_32(hw_ssp_timing)
+	mxs_reg_32(hw_ssp_ctrl1)
+	mxs_reg_32(hw_ssp_data)
+	mxs_reg_32(hw_ssp_sdresp0)
+	mxs_reg_32(hw_ssp_sdresp1)
+	mxs_reg_32(hw_ssp_sdresp2)
+	mxs_reg_32(hw_ssp_sdresp3)
+	mxs_reg_32(hw_ssp_status)
+
+	uint32_t	reserved1[12];
+
+	mxs_reg_32(hw_ssp_debug)
+	mxs_reg_32(hw_ssp_version)
+};
+#elif defined(CONFIG_MX28)
+struct mxs_ssp_regs {
+	mxs_reg_32(hw_ssp_ctrl0)
+	mxs_reg_32(hw_ssp_cmd0)
+	mxs_reg_32(hw_ssp_cmd1)
 	mxs_reg_32(hw_ssp_xfer_size)
 	mxs_reg_32(hw_ssp_block_size)
 	mxs_reg_32(hw_ssp_compref)
@@ -52,6 +74,25 @@
 };
 #endif
 
+static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
+{
+	switch (port) {
+	case 0:
+		return (struct mxs_ssp_regs *)MXS_SSP0_BASE;
+	case 1:
+		return (struct mxs_ssp_regs *)MXS_SSP1_BASE;
+#ifdef CONFIG_MX28
+	case 2:
+		return (struct mxs_ssp_regs *)MXS_SSP2_BASE;
+	case 3:
+		return (struct mxs_ssp_regs *)MXS_SSP3_BASE;
+#endif
+	default:
+		return NULL;
+	}
+}
+#endif
+
 #define	SSP_CTRL0_SFTRST			(1 << 31)
 #define	SSP_CTRL0_CLKGATE			(1 << 30)
 #define	SSP_CTRL0_RUN				(1 << 29)
@@ -72,6 +113,11 @@
 #define	SSP_CTRL0_GET_RESP			(1 << 17)
 #define	SSP_CTRL0_ENABLE			(1 << 16)
 
+#ifdef CONFIG_MX23
+#define	SSP_CTRL0_XFER_COUNT_OFFSET		0
+#define	SSP_CTRL0_XFER_COUNT_MASK		0xffff
+#endif
+
 #define	SSP_CMD0_SOFT_TERMINATE			(1 << 26)
 #define	SSP_CMD0_DBL_DATA_RATE_EN		(1 << 25)
 #define	SSP_CMD0_PRIM_BOOT_OP_EN		(1 << 24)
@@ -79,6 +125,12 @@
 #define	SSP_CMD0_SLOW_CLKING_EN			(1 << 22)
 #define	SSP_CMD0_CONT_CLKING_EN			(1 << 21)
 #define	SSP_CMD0_APPEND_8CYC			(1 << 20)
+#if defined(CONFIG_MX23)
+#define	SSP_CMD0_BLOCK_SIZE_MASK		(0xf << 16)
+#define	SSP_CMD0_BLOCK_SIZE_OFFSET		16
+#define	SSP_CMD0_BLOCK_COUNT_MASK		(0xff << 8)
+#define	SSP_CMD0_BLOCK_COUNT_OFFSET		8
+#endif
 #define	SSP_CMD0_CMD_MASK			0xff
 #define	SSP_CMD0_CMD_OFFSET			0
 #define	SSP_CMD0_CMD_MMC_GO_IDLE_STATE		0x00
@@ -152,6 +204,7 @@
 #define	SSP_CMD1_CMD_ARG_MASK			0xffffffff
 #define	SSP_CMD1_CMD_ARG_OFFSET			0
 
+#if defined(CONFIG_MX28)
 #define	SSP_XFER_SIZE_XFER_COUNT_MASK		0xffffffff
 #define	SSP_XFER_SIZE_XFER_COUNT_OFFSET		0
 
@@ -159,6 +212,7 @@
 #define	SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET	4
 #define	SSP_BLOCK_SIZE_BLOCK_SIZE_MASK		0xf
 #define	SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET	0
+#endif
 
 #define	SSP_COMPREF_REFERENCE_MASK		0xffffffff
 #define	SSP_COMPREF_REFERENCE_OFFSET		0
diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h
index 9bddc12..5bafde5 100644
--- a/arch/arm/include/asm/arch-mxs/sys_proto.h
+++ b/arch/arm/include/asm/arch-mxs/sys_proto.h
@@ -31,10 +31,16 @@
 		       uint32_t mask,
 		       unsigned int timeout);
 
-int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int));
+int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
 
 #ifdef CONFIG_SPL_BUILD
+
+#if defined(CONFIG_MX23)
+#include <asm/arch/iomux-mx23.h>
+#elif defined(CONFIG_MX28)
 #include <asm/arch/iomux-mx28.h>
+#endif
+
 void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
 			const unsigned int iomux_size);
 #endif
@@ -46,6 +52,17 @@
 };
 
 static const struct mxs_pair mxs_boot_modes[] = {
+#if defined(CONFIG_MX23)
+	{ 0x00, 0x0f, "USB" },
+	{ 0x01, 0x1f, "I2C, master" },
+	{ 0x02, 0x1f, "SSP SPI #1, master, NOR" },
+	{ 0x03, 0x1f, "SSP SPI #2, master, NOR" },
+	{ 0x04, 0x1f, "NAND" },
+	{ 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
+	{ 0x09, 0x1f, "SSP SD/MMC #0" },
+	{ 0x0a, 0x1f, "SSP SD/MMC #1" },
+	{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
+#elif defined(CONFIG_MX28)
 	{ 0x00, 0x0f, "USB #0" },
 	{ 0x01, 0x1f, "I2C #0, master, 3V3" },
 	{ 0x11, 0x1f, "I2C #0, master, 1V8" },
@@ -62,6 +79,7 @@
 	{ 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
 	{ 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
 	{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
+#endif
 };
 
 struct mxs_spl_data {
diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h
index 70d94c5..73dfd39 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -23,67 +23,27 @@
 #include <asm/types.h>
 
 /* Stabilization delays, in usec */
-#define PLL_STABILIZATION_DELAY (300)
+#define PLL_STABILIZATION_DELAY	(300)
 #define IO_STABILIZATION_DELAY	(1000)
 
-#define NVBL_PLLP_KHZ	(216000)
-
 #define PLLX_ENABLED		(1 << 30)
 #define CCLK_BURST_POLICY	0x20008888
 #define SUPER_CCLK_DIVIDER	0x80000000
 
 /* Calculate clock fractional divider value from ref and target frequencies */
-#define CLK_DIVIDER(REF, FREQ)  ((((REF) * 2) / FREQ) - 2)
+#define CLK_DIVIDER(REF, FREQ)	((((REF) * 2) / FREQ) - 2)
 
 /* Calculate clock frequency value from reference and clock divider value */
-#define CLK_FREQUENCY(REF, REG)  (((REF) * 2) / (REG + 2))
+#define CLK_FREQUENCY(REF, REG)	(((REF) * 2) / (REG + 2))
 
 /* AVP/CPU ID */
 #define PG_UP_TAG_0_PID_CPU	0x55555555	/* CPU aka "a9" aka "mpcore" */
-#define PG_UP_TAG_0             0x0
+#define PG_UP_TAG_0		0x0
 
 #define CORESIGHT_UNLOCK	0xC5ACCE55;
 
-/* AP20-Specific Base Addresses */
-
-/* AP20 Base physical address of SDRAM. */
-#define AP20_BASE_PA_SDRAM      0x00000000
-/* AP20 Base physical address of internal SRAM. */
-#define AP20_BASE_PA_SRAM       0x40000000
-/* AP20 Size of internal SRAM (256KB). */
-#define AP20_BASE_PA_SRAM_SIZE  0x00040000
-/* AP20 Base physical address of flash. */
-#define AP20_BASE_PA_NOR_FLASH  0xD0000000
-/* AP20 Base physical address of boot information table. */
-#define AP20_BASE_PA_BOOT_INFO  AP20_BASE_PA_SRAM
-
-/*
- * Super-temporary stacks for EXTREMELY early startup. The values chosen for
- * these addresses must be valid on ALL SOCs because this value is used before
- * we are able to differentiate between the SOC types.
- *
- * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
- *       stack is placed below the AVP stack. Once the CPU stack has been moved,
- *       the AVP is free to use the IRAM the CPU stack previously occupied if
- *       it should need to do so.
- *
- * NOTE: In multi-processor CPU complex configurations, each processor will have
- *       its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
- *       limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
- *       stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
- *       CPU.
- */
-
-/* Common AVP early boot stack limit */
-#define AVP_EARLY_BOOT_STACK_LIMIT	\
-	(AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
-/* Common AVP early boot stack size */
-#define AVP_EARLY_BOOT_STACK_SIZE	0x1000
-/* Common CPU early boot stack limit */
-#define CPU_EARLY_BOOT_STACK_LIMIT	\
-	(AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
-/* Common CPU early boot stack size */
-#define CPU_EARLY_BOOT_STACK_SIZE	0x1000
+/* AP base physical address of internal SRAM */
+#define NV_PA_BASE_SRAM		0x40000000
 
 #define EXCEP_VECTOR_CPU_RESET_VECTOR	(NV_PA_EVP_BASE + 0x100)
 #define CSITE_CPU_DBG0_LAR		(NV_PA_CSITE_BASE + 0x10FB0)
diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h
index be6bf25..3db0d93 100644
--- a/arch/arm/include/asm/arch-tegra/board.h
+++ b/arch/arm/include/asm/arch-tegra/board.h
@@ -41,8 +41,9 @@
  * an empty stub function will be called.
  */
 
-void pin_mux_usb(void);      /* overrideable USB pinmux setup   */
-void pin_mux_spi(void);      /* overrideable SPI pinmux setup   */
-void pin_mux_nand(void);     /* overrideable NAND pinmux setup  */
+void pin_mux_usb(void);      /* overrideable USB pinmux setup     */
+void pin_mux_spi(void);      /* overrideable SPI pinmux setup     */
+void pin_mux_nand(void);     /* overrideable NAND pinmux setup    */
+void pin_mux_display(void);  /* overrideable DISPLAY pinmux setup */
 
 #endif
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index 7b548c2..c754ec7 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -21,8 +21,8 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _CLK_RST_H_
-#define _CLK_RST_H_
+#ifndef _TEGRA_CLK_RST_H_
+#define _TEGRA_CLK_RST_H_
 
 /* PLL registers - there are several PLLs in the clock controller */
 struct clk_pll {
@@ -37,6 +37,12 @@
 	uint pll_misc;		/* other misc things */
 };
 
+/* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */
+struct clk_set_clr {
+	uint set;
+	uint clr;
+};
+
 /*
  * Most PLLs use the clk_pll structure, but some have a simpler two-member
  * structure for which we use clk_pll_simple. The reason for this non-
@@ -45,8 +51,10 @@
 enum {
 	TEGRA_CLK_PLLS		= 6,	/* Number of normal PLLs */
 	TEGRA_CLK_SIMPLE_PLLS	= 3,	/* Number of simple PLLs */
-	TEGRA_CLK_REGS		= 3,	/* Number of clock enable registers */
-	TEGRA_CLK_SOURCES	= 64,	/* Number of peripheral clock sources */
+	TEGRA_CLK_REGS		= 3,	/* Number of clock enable regs L/H/U */
+	TEGRA_CLK_SOURCES	= 64,	/* Number of ppl clock sources L/H/U */
+	TEGRA_CLK_REGS_VW	= 2,	/* Number of clock enable regs V/W */
+	TEGRA_CLK_SOURCES_VW	= 32,	/* Number of ppl clock sources V/W*/
 };
 
 /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@@ -82,14 +90,80 @@
 	uint crc_reserved11;		/* _reserved_11,	0xFC */
 
 	uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0...	0x100-1fc */
-	uint crc_reserved20[80];	/*			0x200-33C */
-	uint crc_cpu_cmplx_set;		/* _CPU_CMPLX_SET_0,	0x340	  */
-	uint crc_cpu_cmplx_clr;		/* _CPU_CMPLX_CLR_0,	0x344     */
+
+	uint crc_reserved20[64];	/* _reserved_20,	0x200-2fc */
+
+	/* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
+	struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
+
+	uint crc_reserved30[2];		/* _reserved_30,	0x318, 0x31c */
+
+	/* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */
+	struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS];
+
+	uint crc_reserved31[2];		/* _reserved_31,	0x338, 0x33c */
+
+	uint crc_cpu_cmplx_set;		/* _RST_CPU_CMPLX_SET_0,    0x340 */
+	uint crc_cpu_cmplx_clr;		/* _RST_CPU_CMPLX_CLR_0,    0x344 */
+
+	/* Additional (T30) registers */
+	uint crc_clk_cpu_cmplx_set;	/* _CLK_CPU_CMPLX_SET_0,    0x348 */
+	uint crc_clk_cpu_cmplx_clr;	/* _CLK_CPU_CMPLX_SET_0,    0x34c */
+
+	uint crc_reserved32[2];		/* _reserved_32,      0x350,0x354 */
+
+	uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */
+	uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */
+	uint crc_cclkg_brst_pol;	/* _CCLKG_BURST_POLICY_0,   0x368 */
+	uint crc_super_cclkg_div;	/* _SUPER_CCLKG_DIVIDER_0,  0x36C */
+	uint crc_cclklp_brst_pol;	/* _CCLKLP_BURST_POLICY_0,  0x370 */
+	uint crc_super_cclkp_div;	/* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
+	uint crc_clk_cpug_cmplx;	/* _CLK_CPUG_CMPLX_0,       0x378 */
+	uint crc_clk_cpulp_cmplx;	/* _CLK_CPULP_CMPLX_0,      0x37C */
+	uint crc_cpu_softrst_ctrl;	/* _CPU_SOFTRST_CTRL_0,     0x380 */
+	uint crc_cpu_softrst_ctrl1;	/* _CPU_SOFTRST_CTR1L_0,    0x384 */
+	uint crc_cpu_softrst_ctrl2;	/* _CPU_SOFTRST_CTRL2_0,    0x388 */
+	uint crc_reserved33[9];		/* _reserved_33,        0x38c-3ac */
+	uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */
+	/* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
+	struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
+	/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
+	struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
+	/* Additional (T114) registers */
+	uint crc_rst_cpug_cmplx_set;	/* _RST_CPUG_CMPLX_SET_0,  0x450 */
+	uint crc_rst_cpug_cmplx_clr;	/* _RST_CPUG_CMPLX_CLR_0,  0x454 */
+	uint crc_rst_cpulp_cmplx_set;	/* _RST_CPULP_CMPLX_SET_0, 0x458 */
+	uint crc_rst_cpulp_cmplx_clr;	/* _RST_CPULP_CMPLX_CLR_0, 0x45C */
+	uint crc_clk_cpug_cmplx_set;	/* _CLK_CPUG_CMPLX_SET_0,  0x460 */
+	uint crc_clk_cpug_cmplx_clr;	/* _CLK_CPUG_CMPLX_CLR_0,  0x464 */
+	uint crc_clk_cpulp_cmplx_set;	/* _CLK_CPULP_CMPLX_SET_0, 0x468 */
+	uint crc_clk_cpulp_cmplx_clr;	/* _CLK_CPULP_CMPLX_CLR_0, 0x46C */
+	uint crc_cpu_cmplx_status;	/* _CPU_CMPLX_STATUS_0,    0x470 */
+	uint crc_reserved40[1];		/* _reserved_40,        0x474 */
+	uint crc_intstatus;		/* __INTSTATUS_0,       0x478 */
+	uint crc_intmask;		/* __INTMASK_0,         0x47C */
+	uint crc_utmip_pll_cfg0;	/* _UTMIP_PLL_CFG0_0,	0x480 */
+	uint crc_utmip_pll_cfg1;	/* _UTMIP_PLL_CFG1_0,	0x484 */
+	uint crc_utmip_pll_cfg2;	/* _UTMIP_PLL_CFG2_0,	0x488 */
+
+	uint crc_plle_aux;		/* _PLLE_AUX_0,		0x48C */
+	uint crc_sata_pll_cfg0;		/* _SATA_PLL_CFG0_0,	0x490 */
+	uint crc_sata_pll_cfg1;		/* _SATA_PLL_CFG1_0,	0x494 */
+	uint crc_pcie_pll_cfg0;		/* _PCIE_PLL_CFG0_0,	0x498 */
+
+	uint crc_prog_audio_dly_clk;	/* _PROG_AUDIO_DLY_CLK_0, 0x49C */
+	uint crc_audio_sync_clk_i2s0;	/* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */
+	uint crc_audio_sync_clk_i2s1;	/* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */
+	uint crc_audio_sync_clk_i2s2;	/* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */
+	uint crc_audio_sync_clk_i2s3;	/* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */
+	uint crc_audio_sync_clk_i2s4;	/* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
+	uint crc_audio_sync_clk_spdif;	/* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
 };
 
 /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
+#define CPU3_CLK_STP_SHIFT	11
+#define CPU2_CLK_STP_SHIFT	10
 #define CPU1_CLK_STP_SHIFT	9
-
 #define CPU0_CLK_STP_SHIFT	8
 #define CPU0_CLK_STP_MASK	(1U << CPU0_CLK_STP_SHIFT)
 
@@ -120,6 +194,12 @@
 #define PLL_OUT_RATIO_MASK	(0xffU << PLL_OUT_RATIO_SHIFT)
 
 /* CLK_RST_CONTROLLER_PLLx_MISC_0 */
+#define PLL_DCCON_SHIFT		20
+#define PLL_DCCON_MASK		(1U << PLL_DCCON_SHIFT)
+
+#define PLL_LOCK_ENABLE_SHIFT	18
+#define PLL_LOCK_ENABLE_MASK	(1U << PLL_LOCK_ENABLE_SHIFT)
+
 #define PLL_CPCON_SHIFT		8
 #define PLL_CPCON_MASK		(15U << PLL_CPCON_SHIFT)
 
@@ -129,9 +209,23 @@
 #define PLLU_VCO_FREQ_SHIFT	20
 #define PLLU_VCO_FREQ_MASK	(1U << PLLU_VCO_FREQ_SHIFT)
 
+#define PLLP_OUT1_OVR		(1 << 2)
+#define PLLP_OUT2_OVR		(1 << 18)
+#define PLLP_OUT3_OVR		(1 << 2)
+#define PLLP_OUT4_OVR		(1 << 18)
+#define PLLP_OUT1_RATIO		8
+#define PLLP_OUT2_RATIO		24
+#define PLLP_OUT3_RATIO		8
+#define PLLP_OUT4_RATIO		24
+
+enum {
+	IN_408_OUT_204_DIVISOR = 2,
+	IN_408_OUT_102_DIVISOR = 6,
+	IN_408_OUT_48_DIVISOR = 15,
+	IN_408_OUT_9_6_DIVISOR = 83,
+};
+
 /* CLK_RST_CONTROLLER_OSC_CTRL_0 */
-#define OSC_FREQ_SHIFT		30
-#define OSC_FREQ_MASK		(3U << OSC_FREQ_SHIFT)
 #define OSC_XOBP_SHIFT		1
 #define OSC_XOBP_MASK		(1U << OSC_XOBP_SHIFT)
 
@@ -151,4 +245,84 @@
 #define OUT_CLK_SOURCE4_SHIFT	28
 #define OUT_CLK_SOURCE4_MASK	(15U << OUT_CLK_SOURCE4_SHIFT)
 
+/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
+#define SCLK_SYS_STATE_SHIFT    28U
+#define SCLK_SYS_STATE_MASK     (15U << SCLK_SYS_STATE_SHIFT)
+enum {
+	SCLK_SYS_STATE_STDBY,
+	SCLK_SYS_STATE_IDLE,
+	SCLK_SYS_STATE_RUN,
+	SCLK_SYS_STATE_IRQ = 4U,
+	SCLK_SYS_STATE_FIQ = 8U,
+};
+#define SCLK_COP_FIQ_MASK       (1 << 27)
+#define SCLK_CPU_FIQ_MASK       (1 << 26)
+#define SCLK_COP_IRQ_MASK       (1 << 25)
+#define SCLK_CPU_IRQ_MASK       (1 << 24)
+
+#define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT		12
+#define SCLK_SWAKEUP_FIQ_SOURCE_MASK		\
+		(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT		8
+#define SCLK_SWAKEUP_IRQ_SOURCE_MASK		\
+		(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define SCLK_SWAKEUP_RUN_SOURCE_SHIFT		4
+#define SCLK_SWAKEUP_RUN_SOURCE_MASK		\
+		(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT		0
+
+#define SCLK_SWAKEUP_IDLE_SOURCE_MASK		\
+		(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+enum {
+	SCLK_SOURCE_CLKM,
+	SCLK_SOURCE_PLLC_OUT1,
+	SCLK_SOURCE_PLLP_OUT4,
+	SCLK_SOURCE_PLLP_OUT3,
+	SCLK_SOURCE_PLLP_OUT2,
+	SCLK_SOURCE_CLKD,
+	SCLK_SOURCE_CLKS,
+	SCLK_SOURCE_PLLM_OUT1,
+};
+#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1    (7 << 12)
+#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1    (7 << 8)
+#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1    (7 << 4)
+#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1   (7 << 0)
+
+/* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER */
+#define SUPER_SCLK_ENB_SHIFT		31U
+#define SUPER_SCLK_ENB_MASK		(1U << 31)
+#define SUPER_SCLK_DIVIDEND_SHIFT	8
+#define SUPER_SCLK_DIVIDEND_MASK	(0xff << SUPER_SCLK_DIVIDEND_SHIFT)
+#define SUPER_SCLK_DIVISOR_SHIFT	0
+#define SUPER_SCLK_DIVISOR_MASK		(0xff << SUPER_SCLK_DIVISOR_SHIFT)
+
+/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE */
+#define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
+#define CLK_SYS_RATE_HCLK_DISABLE_MASK  (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
+#define CLK_SYS_RATE_AHB_RATE_SHIFT     4
+#define CLK_SYS_RATE_AHB_RATE_MASK      (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
+#define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3
+#define CLK_SYS_RATE_PCLK_DISABLE_MASK  (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT)
+#define CLK_SYS_RATE_APB_RATE_SHIFT     0
+#define CLK_SYS_RATE_APB_RATE_MASK      (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
+
+/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR */
+#define CLR_CPURESET0   (1 << 0)
+#define CLR_CPURESET1   (1 << 1)
+#define CLR_CPURESET2   (1 << 2)
+#define CLR_CPURESET3   (1 << 3)
+#define CLR_DBGRESET0   (1 << 12)
+#define CLR_DBGRESET1   (1 << 13)
+#define CLR_DBGRESET2   (1 << 14)
+#define CLR_DBGRESET3   (1 << 15)
+#define CLR_CORERESET0  (1 << 16)
+#define CLR_CORERESET1  (1 << 17)
+#define CLR_CORERESET2  (1 << 18)
+#define CLR_CORERESET3  (1 << 19)
+#define CLR_CXRESET0    (1 << 20)
+#define CLR_CXRESET1    (1 << 21)
+#define CLR_CXRESET2    (1 << 22)
+#define CLR_CXRESET3    (1 << 23)
+#define CLR_NONCPURESET (1 << 29)
+
-#endif	/* CLK_RST_H */
+#endif	/* _TEGRA_CLK_RST_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index eac1dc2..c8677bd 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -21,8 +21,8 @@
 
 /* Tegra clock control functions */
 
-#ifndef _CLOCK_H
-#define _CLOCK_H
+#ifndef _TEGRA_CLOCK_H_
+#define _TEGRA_CLOCK_H_
 
 /* Set of oscillator frequencies supported in the internal API. */
 enum clock_osc_freq {
@@ -82,7 +82,7 @@
  * @returns 0 if ok, -1 on error (invalid clock id)
  */
 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
-		      u32 *divp, u32 *cpcon, u32 *lfcon);
+		u32 *divp, u32 *cpcon, u32 *lfcon);
 
 /*
  * Enable a clock
@@ -136,7 +136,7 @@
 /**
  * Put parts of the CPU complex into or out of reset.\
  *
- * @param cpu		cpu number (0 or 1 on Tegra2)
+ * @param cpu		cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
  * @param which		which parts of the complex to affect (OR of crc_reset_id)
  * @param reset		1 to assert reset, 0 to de-assert
  */
@@ -262,4 +262,59 @@
 /* Initialize the PLLs */
 void clock_early_init(void);
 
-#endif	/* _CLOCK_H_ */
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id);
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id     peripheral to start
+ * @param source        PLL id of required parent clock
+ * @param mux_bits      Set to number of bits in mux register: 2 or 4
+ * @param divider_bits  Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+		enum clock_id parent, int *mux_bits, int *divider_bits);
+
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id        Clock ID according to tegra30 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id);
+
+/**
+ * Set the output frequency you want for each PLL clock.
+ * PLL output frequencies are programmed by setting their N, M and P values.
+ * The governing equations are:
+ *     VCO = (Fi / m) * n, Fo = VCO / (2^p)
+ *     where Fo is the output frequency from the PLL.
+ * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
+ *     216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
+ * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
+ *
+ * @param n PLL feedback divider(DIVN)
+ * @param m PLL input divider(DIVN)
+ * @param p post divider(DIVP)
+ * @param cpcon base PLL charge pump(CPCON)
+ * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
+ *              be overriden), 1 if PLL is already correct
+ */
+int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
+
+/* return 1 if a peripheral ID is in range */
+#define clock_type_id_isvalid(id) ((id) >= 0 && \
+		(id) < CLOCK_TYPE_COUNT)
+
+/* return 1 if a periphc_internal_id is in range */
+#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
+		(id) < PERIPHC_COUNT)
+
+#endif  /* _TEGRA_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/funcmux.h b/arch/arm/include/asm/arch-tegra/funcmux.h
new file mode 100644
index 0000000..f101e5e
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/funcmux.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra high-level function multiplexing */
+
+#ifndef _TEGRA_FUNCMUX_H_
+#define _TEGRA_FUNCMUX_H_
+
+/**
+ * Select a config for a particular peripheral.
+ *
+ * Each peripheral can operate through a number of configurations,
+ * which are sets of pins that it uses to bring out its signals.
+ * The basic config is 0, and higher numbers indicate different
+ * pinmux settings to bring the peripheral out on other pins,
+ *
+ * This function also disables tristate for the function's pins,
+ * so that they operate in normal mode.
+ *
+ * @param id		Peripheral id
+ * @param config	Configuration to use (FUNCMUX_...), 0 for default
+ * @return 0 if ok, -1 on error (e.g. incorrect id or config)
+ */
+int funcmux_select(enum periph_id id, int config);
+
+#endif	/* _TEGRA_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
new file mode 100644
index 0000000..209abf1
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
@@ -0,0 +1,40 @@
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_GP_PADCTRL_H_
+#define _TEGRA_GP_PADCTRL_H_
+
+#define GP_HIDREV			0x804
+
+/* bit fields definitions for APB_MISC_GP_HIDREV register */
+#define HIDREV_CHIPID_SHIFT		8
+#define HIDREV_CHIPID_MASK		(0xff << HIDREV_CHIPID_SHIFT)
+#define HIDREV_MAJORPREV_SHIFT		4
+#define HIDREV_MAJORPREV_MASK		(0xf << HIDREV_MAJORPREV_SHIFT)
+
+/* CHIPID field returned from APB_MISC_GP_HIDREV register */
+#define CHIPID_TEGRA20			0x20
+#define CHIPID_TEGRA30			0x30
+#define CHIPID_TEGRA114			0x35
+
+#endif	/* _TEGRA_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h
index b1d47cd..1bcdcf8 100644
--- a/arch/arm/include/asm/arch-tegra/pmc.h
+++ b/arch/arm/include/asm/arch-tegra/pmc.h
@@ -128,5 +128,13 @@
 #define START_CP	(1 << 8)
 
 #define CPUPWRREQ_OE	(1 << 16)
+#define CPUPWRREQ_POL	(1 << 15)
+
+#define CRAILID		(0)
+#define CE0ID		(14)
+#define C0NCID		(15)
+#define CRAIL		(1 << CRAILID)
+#define CE0		(1 << CE0ID)
+#define C0NC		(1 << C0NCID)
 
 #endif	/* PMC_H */
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 6d2e62f..bf7229d 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -40,6 +40,12 @@
 #define NV_PA_APB_UARTE_BASE	(NV_PA_APB_MISC_BASE + 0x6400)
 #define NV_PA_NAND_BASE		(NV_PA_APB_MISC_BASE + 0x8000)
 #define NV_PA_SPI_BASE		(NV_PA_APB_MISC_BASE + 0xC380)
+#define NV_PA_SLINK1_BASE	(NV_PA_APB_MISC_BASE + 0xD400)
+#define NV_PA_SLINK2_BASE	(NV_PA_APB_MISC_BASE + 0xD600)
+#define NV_PA_SLINK3_BASE	(NV_PA_APB_MISC_BASE + 0xD800)
+#define NV_PA_SLINK4_BASE	(NV_PA_APB_MISC_BASE + 0xDA00)
+#define NV_PA_SLINK5_BASE	(NV_PA_APB_MISC_BASE + 0xDC00)
+#define NV_PA_SLINK6_BASE	(NV_PA_APB_MISC_BASE + 0xDE00)
 #define TEGRA_DVC_BASE		(NV_PA_APB_MISC_BASE + 0xD000)
 #define NV_PA_PMC_BASE		(NV_PA_APB_MISC_BASE + 0xE400)
 #define NV_PA_EMC_BASE		(NV_PA_APB_MISC_BASE + 0xF400)
@@ -72,14 +78,23 @@
 	SKU_ID_T25		= 0x18,
 	SKU_ID_AP25E		= 0x1b,
 	SKU_ID_T25E		= 0x1c,
+	SKU_ID_T30		= 0x81, /* Cardhu value */
+	SKU_ID_T114_ENG		= 0x00, /* Dalmore value, unfused */
 };
 
-/* These are the SOC categories that affect clocking */
+/*
+ * These are used to distinguish SOC types for setting up clocks. Mostly
+ * we can tell the clocking required by looking at the SOC sku_id, but
+ * for T30 it is a user option as to whether to run PLLP in fast or slow
+ * mode, so we have two options there.
+ */
 enum {
 	TEGRA_SOC_T20,
 	TEGRA_SOC_T25,
+	TEGRA_SOC_T30,
+	TEGRA_SOC_T114,
 
-	TEGRA_SOC_COUNT,
+	TEGRA_SOC_CNT,
 	TEGRA_SOC_UNKNOWN	= -1,
 };
 
diff --git a/arch/arm/include/asm/arch-tegra/tegra_slink.h b/arch/arm/include/asm/arch-tegra/tegra_slink.h
new file mode 100644
index 0000000..74804b5
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/tegra_slink.h
@@ -0,0 +1,84 @@
+/*
+ * NVIDIA Tegra SPI-SLINK controller
+ *
+ * Copyright 2010-2013 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_SLINK_H_
+#define _TEGRA_SLINK_H_
+
+#include <asm/types.h>
+
+struct slink_tegra {
+	u32 command;	/* SLINK_COMMAND_0 register  */
+	u32 command2;	/* SLINK_COMMAND2_0 reg */
+	u32 status;	/* SLINK_STATUS_0 register */
+	u32 reserved;	/* Reserved offset 0C */
+	u32 mas_data;	/* SLINK_MAS_DATA_0 reg */
+	u32 slav_data;	/* SLINK_SLAVE_DATA_0 reg */
+	u32 dma_ctl;	/* SLINK_DMA_CTL_0 register */
+	u32 status2;	/* SLINK_STATUS2_0 reg */
+	u32 rsvd[56];	/* 0x20 to 0xFF reserved */
+	u32 tx_fifo;	/* SLINK_TX_FIFO_0 reg off 100h */
+	u32 rsvd2[31];	/* 0x104 to 0x17F reserved */
+	u32 rx_fifo;	/* SLINK_RX_FIFO_0 reg off 180h */
+};
+
+/* COMMAND */
+#define SLINK_CMD_ENB			(1 << 31)
+#define SLINK_CMD_GO			(1 << 30)
+#define SLINK_CMD_M_S			(1 << 28)
+#define SLINK_CMD_CK_SDA		(1 << 21)
+#define SLINK_CMD_CS_POL		(1 << 13)
+#define SLINK_CMD_CS_VAL		(1 << 12)
+#define SLINK_CMD_CS_SOFT		(1 << 11)
+#define SLINK_CMD_BIT_LENGTH		(1 << 4)
+#define SLINK_CMD_BIT_LENGTH_MASK	0x0000001F
+/* COMMAND2 */
+#define SLINK_CMD2_TXEN			(1 << 30)
+#define SLINK_CMD2_RXEN			(1 << 31)
+#define SLINK_CMD2_SS_EN		(1 << 18)
+#define SLINK_CMD2_SS_EN_SHIFT		18
+#define SLINK_CMD2_SS_EN_MASK		0x000C0000
+#define SLINK_CMD2_CS_ACTIVE_BETWEEN	(1 << 17)
+/* STATUS */
+#define SLINK_STAT_BSY			(1 << 31)
+#define SLINK_STAT_RDY			(1 << 30)
+#define SLINK_STAT_ERR			(1 << 29)
+#define SLINK_STAT_RXF_FLUSH		(1 << 27)
+#define SLINK_STAT_TXF_FLUSH		(1 << 26)
+#define SLINK_STAT_RXF_OVF		(1 << 25)
+#define SLINK_STAT_TXF_UNR		(1 << 24)
+#define SLINK_STAT_RXF_EMPTY		(1 << 23)
+#define SLINK_STAT_RXF_FULL		(1 << 22)
+#define SLINK_STAT_TXF_EMPTY		(1 << 21)
+#define SLINK_STAT_TXF_FULL		(1 << 20)
+#define SLINK_STAT_TXF_OVF		(1 << 19)
+#define SLINK_STAT_RXF_UNR		(1 << 18)
+#define SLINK_STAT_CUR_BLKCNT		(1 << 15)
+/* STATUS2 */
+#define SLINK_STAT2_RXF_FULL_CNT	(1 << 16)
+#define SLINK_STAT2_TXF_FULL_CNT	(1 << 0)
+
+#define SPI_TIMEOUT		1000
+#define TEGRA_SPI_MAX_FREQ	52000000
+
+#endif	/* _TEGRA_SLINK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/include/asm/arch-tegra114/clock-tables.h
new file mode 100644
index 0000000..d8fa0e1
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/clock-tables.h
@@ -0,0 +1,402 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 clock PLL tables */
+
+#ifndef _TEGRA114_CLOCK_TABLES_H_
+#define _TEGRA114_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+	CLOCK_ID_FIRST,
+	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+	CLOCK_ID_MEMORY,
+	CLOCK_ID_PERIPH,
+	CLOCK_ID_AUDIO,
+	CLOCK_ID_USB,
+	CLOCK_ID_DISPLAY,
+
+	/* now the simple ones */
+	CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_EPCI,
+	CLOCK_ID_SFROM32KHZ,
+
+	/* These are the base clocks (inputs to the Tegra SOC) */
+	CLOCK_ID_32KHZ,
+	CLOCK_ID_OSC,
+
+	CLOCK_ID_COUNT,	/* number of PLLs */
+	CLOCK_ID_DISPLAY2,	/* placeholder */
+	CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+	PERIPH_ID_FIRST,
+
+	/* Low word: 31:0 (DEVICES_L) */
+	PERIPH_ID_CPU = PERIPH_ID_FIRST,
+	PERIPH_ID_COP,
+	PERIPH_ID_TRIGSYS,
+	PERIPH_ID_RESERVED3,
+	PERIPH_ID_RTC,
+	PERIPH_ID_TMR,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+
+	/* 8 */
+	PERIPH_ID_GPIO,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_SPDIF,
+	PERIPH_ID_I2S1,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_NDFLASH,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC4,
+
+	/* 16 */
+	PERIPH_ID_RESERVED16,
+	PERIPH_ID_PWM,
+	PERIPH_ID_I2S2,
+	PERIPH_ID_EPP,
+	PERIPH_ID_VI,
+	PERIPH_ID_2D,
+	PERIPH_ID_USBD,
+	PERIPH_ID_ISP,
+
+	/* 24 */
+	PERIPH_ID_3D,
+	PERIPH_ID_RESERVED24,
+	PERIPH_ID_DISP2,
+	PERIPH_ID_DISP1,
+	PERIPH_ID_HOST1X,
+	PERIPH_ID_VCP,
+	PERIPH_ID_I2S0,
+	PERIPH_ID_CACHE2,
+
+	/* Middle word: 63:32 (DEVICES_H) */
+	PERIPH_ID_MEM,
+	PERIPH_ID_AHBDMA,
+	PERIPH_ID_APBDMA,
+	PERIPH_ID_RESERVED35,
+	PERIPH_ID_KBC,
+	PERIPH_ID_STAT_MON,
+	PERIPH_ID_PMC,
+	PERIPH_ID_FUSE,
+
+	/* 40 */
+	PERIPH_ID_KFUSE,
+	PERIPH_ID_SBC1,
+	PERIPH_ID_SNOR,
+	PERIPH_ID_RESERVED43,
+	PERIPH_ID_SBC2,
+	PERIPH_ID_RESERVED45,
+	PERIPH_ID_SBC3,
+	PERIPH_ID_I2C5,
+
+	/* 48 */
+	PERIPH_ID_DSI,
+	PERIPH_ID_TVO,
+	PERIPH_ID_MIPI,
+	PERIPH_ID_HDMI,
+	PERIPH_ID_CSI,
+	PERIPH_ID_TVDAC,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_UART3,
+
+	/* 56 */
+	PERIPH_ID_RESERVED56,
+	PERIPH_ID_EMC,
+	PERIPH_ID_USB2,
+	PERIPH_ID_USB3,
+	PERIPH_ID_MPE,
+	PERIPH_ID_VDE,
+	PERIPH_ID_BSEA,
+	PERIPH_ID_BSEV,
+
+	/* Upper word 95:64 (DEVICES_U) */
+	PERIPH_ID_SPEEDO,
+	PERIPH_ID_UART4,
+	PERIPH_ID_UART5,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_SBC4,
+	PERIPH_ID_SDMMC3,
+	PERIPH_ID_PCIE,
+	PERIPH_ID_OWR,
+
+	/* 72 */
+	PERIPH_ID_AFI,
+	PERIPH_ID_CORESIGHT,
+	PERIPH_ID_PCIEXCLK,
+	PERIPH_ID_AVPUCQ,
+	PERIPH_ID_RESERVED76,
+	PERIPH_ID_RESERVED77,
+	PERIPH_ID_RESERVED78,
+	PERIPH_ID_DTV,
+
+	/* 80 */
+	PERIPH_ID_NANDSPEED,
+	PERIPH_ID_I2CSLOW,
+	PERIPH_ID_DSIB,
+	PERIPH_ID_RESERVED83,
+	PERIPH_ID_IRAMA,
+	PERIPH_ID_IRAMB,
+	PERIPH_ID_IRAMC,
+	PERIPH_ID_IRAMD,
+
+	/* 88 */
+	PERIPH_ID_CRAM2,
+	PERIPH_ID_RESERVED89,
+	PERIPH_ID_MDOUBLER,
+	PERIPH_ID_RESERVED91,
+	PERIPH_ID_SUSOUT,
+	PERIPH_ID_RESERVED93,
+	PERIPH_ID_RESERVED94,
+	PERIPH_ID_RESERVED95,
+
+	PERIPH_ID_VW_FIRST,
+	/* V word: 31:0 */
+	PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+	PERIPH_ID_CPULP,
+	PERIPH_ID_3D2,
+	PERIPH_ID_MSELECT,
+	PERIPH_ID_TSENSOR,
+	PERIPH_ID_I2S3,
+	PERIPH_ID_I2S4,
+	PERIPH_ID_I2C4,
+
+	/* 104 */
+	PERIPH_ID_SBC5,
+	PERIPH_ID_SBC6,
+	PERIPH_ID_AUDIO,
+	PERIPH_ID_APBIF,
+	PERIPH_ID_DAM0,
+	PERIPH_ID_DAM1,
+	PERIPH_ID_DAM2,
+	PERIPH_ID_HDA2CODEC2X,
+
+	/* 112 */
+	PERIPH_ID_ATOMICS,
+	PERIPH_ID_EX_RESERVED17,
+	PERIPH_ID_EX_RESERVED18,
+	PERIPH_ID_EX_RESERVED19,
+	PERIPH_ID_EX_RESERVED20,
+	PERIPH_ID_EX_RESERVED21,
+	PERIPH_ID_EX_RESERVED22,
+	PERIPH_ID_ACTMON,
+
+	/* 120 */
+	PERIPH_ID_EX_RESERVED24,
+	PERIPH_ID_EX_RESERVED25,
+	PERIPH_ID_EX_RESERVED26,
+	PERIPH_ID_EX_RESERVED27,
+	PERIPH_ID_SATA,
+	PERIPH_ID_HDA,
+	PERIPH_ID_EX_RESERVED30,
+	PERIPH_ID_EX_RESERVED31,
+
+	/* W word: 31:0 */
+	PERIPH_ID_HDA2HDMICODEC,
+	PERIPH_ID_RESERVED1_SATACOLD,
+	PERIPH_ID_RESERVED2_PCIERX0,
+	PERIPH_ID_RESERVED3_PCIERX1,
+	PERIPH_ID_RESERVED4_PCIERX2,
+	PERIPH_ID_RESERVED5_PCIERX3,
+	PERIPH_ID_RESERVED6_PCIERX4,
+	PERIPH_ID_RESERVED7_PCIERX5,
+
+	/* 136 */
+	PERIPH_ID_CEC,
+	PERIPH_ID_PCIE2_IOBIST,
+	PERIPH_ID_EMC_IOBIST,
+	PERIPH_ID_HDMI_IOBIST,
+	PERIPH_ID_SATA_IOBIST,
+	PERIPH_ID_MIPI_IOBIST,
+	PERIPH_ID_EMC1_IOBIST,
+	PERIPH_ID_XUSB,
+
+	/* 144 */
+	PERIPH_ID_CILAB,
+	PERIPH_ID_CILCD,
+	PERIPH_ID_CILE,
+	PERIPH_ID_DSIA_LP,
+	PERIPH_ID_DSIB_LP,
+	PERIPH_ID_RESERVED21_ENTROPY,
+	PERIPH_ID_RESERVED22_W,
+	PERIPH_ID_RESERVED23_W,
+
+	/* 152 */
+	PERIPH_ID_RESERVED24_W,
+	PERIPH_ID_AMX0,
+	PERIPH_ID_ADX0,
+	PERIPH_ID_DVFS,
+	PERIPH_ID_XUSB_SS,
+	PERIPH_ID_EMC_DLL,
+	PERIPH_ID_MC1,
+	PERIPH_ID_EMC1,
+
+	PERIPH_ID_COUNT,
+	PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+	PLL_OUT1,
+	PLL_OUT2,
+	PLL_OUT3,
+	PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+	/* 0x00 */
+	PERIPHC_I2S1,
+	PERIPHC_I2S2,
+	PERIPHC_SPDIF_OUT,
+	PERIPHC_SPDIF_IN,
+	PERIPHC_PWM,
+	PERIPHC_05h,
+	PERIPHC_SBC2,
+	PERIPHC_SBC3,
+
+	/* 0x08 */
+	PERIPHC_08h,
+	PERIPHC_I2C1,
+	PERIPHC_I2C5,
+	PERIPHC_0bh,
+	PERIPHC_0ch,
+	PERIPHC_SBC1,
+	PERIPHC_DISP1,
+	PERIPHC_DISP2,
+
+	/* 0x10 */
+	PERIPHC_CVE,
+	PERIPHC_11h,
+	PERIPHC_VI,
+	PERIPHC_13h,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC2,
+	PERIPHC_G3D,
+	PERIPHC_G2D,
+
+	/* 0x18 */
+	PERIPHC_NDFLASH,
+	PERIPHC_SDMMC4,
+	PERIPHC_VFIR,
+	PERIPHC_EPP,
+	PERIPHC_MPE,
+	PERIPHC_MIPI,
+	PERIPHC_UART1,
+	PERIPHC_UART2,
+
+	/* 0x20 */
+	PERIPHC_HOST1X,
+	PERIPHC_21h,
+	PERIPHC_TVO,
+	PERIPHC_HDMI,
+	PERIPHC_24h,
+	PERIPHC_TVDAC,
+	PERIPHC_I2C2,
+	PERIPHC_EMC,
+
+	/* 0x28 */
+	PERIPHC_UART3,
+	PERIPHC_29h,
+	PERIPHC_VI_SENSOR,
+	PERIPHC_2bh,
+	PERIPHC_2ch,
+	PERIPHC_SBC4,
+	PERIPHC_I2C3,
+	PERIPHC_SDMMC3,
+
+	/* 0x30 */
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_VDE,
+	PERIPHC_OWR,
+	PERIPHC_NOR,
+	PERIPHC_CSITE,
+	PERIPHC_I2S0,
+	PERIPHC_37h,
+
+	PERIPHC_VW_FIRST,
+	/* 0x38 */
+	PERIPHC_G3D2 = PERIPHC_VW_FIRST,
+	PERIPHC_MSELECT,
+	PERIPHC_TSENSOR,
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+
+	/* 0x40 */
+	PERIPHC_AUDIO,
+	PERIPHC_41h,
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+	PERIPHC_ACTMON,
+	PERIPHC_EXTPERIPH1,
+
+	/* 0x48 */
+	PERIPHC_EXTPERIPH2,
+	PERIPHC_EXTPERIPH3,
+	PERIPHC_NANDSPEED,
+	PERIPHC_I2CSLOW,
+	PERIPHC_SYS,
+	PERIPHC_SPEEDO,
+	PERIPHC_4eh,
+	PERIPHC_4fh,
+
+	/* 0x50 */
+	PERIPHC_50h,
+	PERIPHC_51h,
+	PERIPHC_52h,
+	PERIPHC_53h,
+	PERIPHC_SATAOOB,
+	PERIPHC_SATA,
+	PERIPHC_HDA,
+
+	PERIPHC_COUNT,
+
+	PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+	(id < PERIPH_ID_VW_FIRST) ? \
+		((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+		(id) < PERIPH_ID_COUNT)
+
+#endif	/* _TEGRA114_CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/clock.h b/arch/arm/include/asm/arch-tegra114/clock.h
new file mode 100644
index 0000000..abbefcd
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/clock.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 clock control functions */
+
+#ifndef _TEGRA114_CLOCK_H_
+#define _TEGRA114_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT          28
+#define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
+
+#endif	/* _TEGRA114_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/flow.h b/arch/arm/include/asm/arch-tegra114/flow.h
new file mode 100644
index 0000000..c7eb051
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/flow.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_FLOW_H_
+#define _TEGRA114_FLOW_H_
+
+struct flow_ctlr {
+	u32 halt_cpu_events;
+	u32 halt_cop_events;
+	u32 cpu_csr;
+	u32 cop_csr;
+	u32 xrq_events;
+	u32 halt_cpu1_events;
+	u32 cpu1_csr;
+	u32 halt_cpu2_events;
+	u32 cpu2_csr;
+	u32 halt_cpu3_events;
+	u32 cpu3_csr;
+	u32 cluster_control;
+};
+
+#endif	/* _TEGRA114_FLOW_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/funcmux.h b/arch/arm/include/asm/arch-tegra114/funcmux.h
new file mode 100644
index 0000000..7f48f25
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/funcmux.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 high-level function multiplexing */
+
+#ifndef _TEGRA114_FUNCMUX_H_
+#define _TEGRA114_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+	FUNCMUX_DEFAULT = 0,	/* default config */
+
+	/* UART configs */
+	FUNCMUX_UART4_GMI = 0,
+};
+#endif	/* _TEGRA114_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
new file mode 100644
index 0000000..c538bdd
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_GP_PADCTRL_H_
+#define _TEGRA114_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+	u32	modereg;	/* 0x00: APB_MISC_GP_MODEREG */
+	u32	hidrev;		/* 0x04: APB_MISC_GP_HIDREV */
+	u32	reserved0[22];	/* 0x08 - 0x5C: */
+	u32	emu_revid;	/* 0x60: APB_MISC_GP_EMU_REVID */
+	u32	xactor_scratch;	/* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+	u32	aocfg1;		/* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+	u32	aocfg2;		/* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
+	u32	atcfg1;		/* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+	u32	atcfg2;		/* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+	u32	atcfg3;		/* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+	u32	atcfg4;		/* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+	u32	atcfg5;		/* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+	u32	cdev1cfg;	/* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+	u32	cdev2cfg;	/* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+	u32	csuscfg;	/* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
+	u32	dap1cfg;	/* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+	u32	dap2cfg;	/* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+	u32	dap3cfg;	/* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+	u32	dap4cfg;	/* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+	u32	dbgcfg;		/* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+	u32	lcdcfg1;	/* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
+	u32	lcdcfg2;	/* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
+	u32	sdio2cfg;	/* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
+	u32	sdio3cfg;	/* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+	u32	spicfg;		/* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+	u32	uaacfg;		/* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+	u32	uabcfg;		/* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+	u32	uart2cfg;	/* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+	u32	uart3cfg;	/* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+	u32	vicfg1;		/* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
+	u32	vivttgen;	/* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
+	u32	reserved1[7];	/* 0xD0-0xE8: */
+	u32	sdio1cfg;	/* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+};
+
+#endif	/* _TEGRA114_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/gpio.h b/arch/arm/include/asm/arch-tegra114/gpio.h
new file mode 100644
index 0000000..21853b6
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/gpio.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_GPIO_H_
+#define _TEGRA114_GPIO_H_
+
+/*
+ * The Tegra114 GPIO controller has 246 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS	4	/* number of ports per bank */
+#define TEGRA_GPIO_BANKS	8	/* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+#include <asm/arch-tegra30/gpio.h>
+
+#endif	/* _TEGRA114_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/hardware.h b/arch/arm/include/asm/arch-tegra114/hardware.h
new file mode 100644
index 0000000..c21fbb6
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/hardware.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_HARDWARE_H_
+#define _TEGRA114_HARDWARE_H_
+
+/* include tegra specific hardware definitions */
+
+#endif /* _TEGRA114_HARDWARE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h
new file mode 100644
index 0000000..fd22930
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/pinmux.h
@@ -0,0 +1,618 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_PINMUX_H_
+#define _TEGRA114_PINMUX_H_
+
+/*
+ * Pin groups which we adjust. There are three basic attributes of each pin
+ * group which use this enum:
+ *
+ *	- function
+ *	- pullup / pulldown
+ *	- tristate or normal
+ */
+enum pmux_pingrp {
+	PINGRP_ULPI_DATA0 = 0,  /* offset 0x3000 */
+	PINGRP_ULPI_DATA1,
+	PINGRP_ULPI_DATA2,
+	PINGRP_ULPI_DATA3,
+	PINGRP_ULPI_DATA4,
+	PINGRP_ULPI_DATA5,
+	PINGRP_ULPI_DATA6,
+	PINGRP_ULPI_DATA7,
+	PINGRP_ULPI_CLK,
+	PINGRP_ULPI_DIR,
+	PINGRP_ULPI_NXT,
+	PINGRP_ULPI_STP,
+	PINGRP_DAP3_FS,
+	PINGRP_DAP3_DIN,
+	PINGRP_DAP3_DOUT,
+	PINGRP_DAP3_SCLK,
+	PINGRP_GPIO_PV0,
+	PINGRP_GPIO_PV1,
+	PINGRP_SDMMC1_CLK,
+	PINGRP_SDMMC1_CMD,
+	PINGRP_SDMMC1_DAT3,
+	PINGRP_SDMMC1_DAT2,
+	PINGRP_SDMMC1_DAT1,
+	PINGRP_SDMMC1_DAT0,
+	PINGRP_GPIO_PV2,
+	PINGRP_GPIO_PV3,
+	PINGRP_CLK2_OUT,
+	PINGRP_CLK2_REQ,
+	PINGRP_LCD_PWR1,
+	PINGRP_LCD_PWR2,
+	PINGRP_LCD_SDIN,
+	PINGRP_LCD_SDOUT,
+	PINGRP_LCD_WR_N,
+	PINGRP_LCD_CS0_N,
+	PINGRP_LCD_DC0,
+	PINGRP_LCD_SCK,
+	PINGRP_LCD_PWR0,
+	PINGRP_LCD_PCLK,
+	PINGRP_LCD_DE,
+	PINGRP_LCD_HSYNC,
+	PINGRP_LCD_VSYNC,
+	PINGRP_LCD_D0,
+	PINGRP_LCD_D1,
+	PINGRP_LCD_D2,
+	PINGRP_LCD_D3,
+	PINGRP_LCD_D4,
+	PINGRP_LCD_D5,
+	PINGRP_LCD_D6,
+	PINGRP_LCD_D7,
+	PINGRP_LCD_D8,
+	PINGRP_LCD_D9,
+	PINGRP_LCD_D10,
+	PINGRP_LCD_D11,
+	PINGRP_LCD_D12,
+	PINGRP_LCD_D13,
+	PINGRP_LCD_D14,
+	PINGRP_LCD_D15,
+	PINGRP_LCD_D16,
+	PINGRP_LCD_D17,
+	PINGRP_LCD_D18,
+	PINGRP_LCD_D19,
+	PINGRP_LCD_D20,
+	PINGRP_LCD_D21,
+	PINGRP_LCD_D22,
+	PINGRP_LCD_D23,
+	PINGRP_LCD_CS1_N,
+	PINGRP_LCD_M1,
+	PINGRP_LCD_DC1,
+	PINGRP_HDMI_INT,
+	PINGRP_DDC_SCL,
+	PINGRP_DDC_SDA,
+	PINGRP_CRT_HSYNC,
+	PINGRP_CRT_VSYNC,
+	PINGRP_VI_D0,
+	PINGRP_VI_D1,
+	PINGRP_VI_D2,
+	PINGRP_VI_D3,
+	PINGRP_VI_D4,
+	PINGRP_VI_D5,
+	PINGRP_VI_D6,
+	PINGRP_VI_D7,
+	PINGRP_VI_D8,
+	PINGRP_VI_D9,
+	PINGRP_VI_D10,
+	PINGRP_VI_D11,
+	PINGRP_VI_PCLK,
+	PINGRP_VI_MCLK,
+	PINGRP_VI_VSYNC,
+	PINGRP_VI_HSYNC,
+	PINGRP_UART2_RXD,
+	PINGRP_UART2_TXD,
+	PINGRP_UART2_RTS_N,
+	PINGRP_UART2_CTS_N,
+	PINGRP_UART3_TXD,
+	PINGRP_UART3_RXD,
+	PINGRP_UART3_CTS_N,
+	PINGRP_UART3_RTS_N,
+	PINGRP_GPIO_PU0,
+	PINGRP_GPIO_PU1,
+	PINGRP_GPIO_PU2,
+	PINGRP_GPIO_PU3,
+	PINGRP_GPIO_PU4,
+	PINGRP_GPIO_PU5,
+	PINGRP_GPIO_PU6,
+	PINGRP_GEN1_I2C_SDA,
+	PINGRP_GEN1_I2C_SCL,
+	PINGRP_DAP4_FS,
+	PINGRP_DAP4_DIN,
+	PINGRP_DAP4_DOUT,
+	PINGRP_DAP4_SCLK,
+	PINGRP_CLK3_OUT,
+	PINGRP_CLK3_REQ,
+	PINGRP_GMI_WP_N,
+	PINGRP_GMI_IORDY,
+	PINGRP_GMI_WAIT,
+	PINGRP_GMI_ADV_N,
+	PINGRP_GMI_CLK,
+	PINGRP_GMI_CS0_N,
+	PINGRP_GMI_CS1_N,
+	PINGRP_GMI_CS2_N,
+	PINGRP_GMI_CS3_N,
+	PINGRP_GMI_CS4_N,
+	PINGRP_GMI_CS6_N,
+	PINGRP_GMI_CS7_N,
+	PINGRP_GMI_AD0,
+	PINGRP_GMI_AD1,
+	PINGRP_GMI_AD2,
+	PINGRP_GMI_AD3,
+	PINGRP_GMI_AD4,
+	PINGRP_GMI_AD5,
+	PINGRP_GMI_AD6,
+	PINGRP_GMI_AD7,
+	PINGRP_GMI_AD8,
+	PINGRP_GMI_AD9,
+	PINGRP_GMI_AD10,
+	PINGRP_GMI_AD11,
+	PINGRP_GMI_AD12,
+	PINGRP_GMI_AD13,
+	PINGRP_GMI_AD14,
+	PINGRP_GMI_AD15,
+	PINGRP_GMI_A16,
+	PINGRP_GMI_A17,
+	PINGRP_GMI_A18,
+	PINGRP_GMI_A19,
+	PINGRP_GMI_WR_N,
+	PINGRP_GMI_OE_N,
+	PINGRP_GMI_DQS,
+	PINGRP_GMI_RST_N,
+	PINGRP_GEN2_I2C_SCL,
+	PINGRP_GEN2_I2C_SDA,
+	PINGRP_SDMMC4_CLK,
+	PINGRP_SDMMC4_CMD,
+	PINGRP_SDMMC4_DAT0,
+	PINGRP_SDMMC4_DAT1,
+	PINGRP_SDMMC4_DAT2,
+	PINGRP_SDMMC4_DAT3,
+	PINGRP_SDMMC4_DAT4,
+	PINGRP_SDMMC4_DAT5,
+	PINGRP_SDMMC4_DAT6,
+	PINGRP_SDMMC4_DAT7,
+	PINGRP_SDMMC4_RST_N,
+	PINGRP_CAM_MCLK,
+	PINGRP_GPIO_PCC1,
+	PINGRP_GPIO_PBB0,
+	PINGRP_CAM_I2C_SCL,
+	PINGRP_CAM_I2C_SDA,
+	PINGRP_GPIO_PBB3,
+	PINGRP_GPIO_PBB4,
+	PINGRP_GPIO_PBB5,
+	PINGRP_GPIO_PBB6,
+	PINGRP_GPIO_PBB7,
+	PINGRP_GPIO_PCC2,
+	PINGRP_JTAG_RTCK,
+	PINGRP_PWR_I2C_SCL,
+	PINGRP_PWR_I2C_SDA,
+	PINGRP_KB_ROW0,
+	PINGRP_KB_ROW1,
+	PINGRP_KB_ROW2,
+	PINGRP_KB_ROW3,
+	PINGRP_KB_ROW4,
+	PINGRP_KB_ROW5,
+	PINGRP_KB_ROW6,
+	PINGRP_KB_ROW7,
+	PINGRP_KB_ROW8,
+	PINGRP_KB_ROW9,
+	PINGRP_KB_ROW10,
+	PINGRP_KB_ROW11,
+	PINGRP_KB_ROW12,
+	PINGRP_KB_ROW13,
+	PINGRP_KB_ROW14,
+	PINGRP_KB_ROW15,
+	PINGRP_KB_COL0,
+	PINGRP_KB_COL1,
+	PINGRP_KB_COL2,
+	PINGRP_KB_COL3,
+	PINGRP_KB_COL4,
+	PINGRP_KB_COL5,
+	PINGRP_KB_COL6,
+	PINGRP_KB_COL7,
+	PINGRP_CLK_32K_OUT,
+	PINGRP_SYS_CLK_REQ,
+	PINGRP_CORE_PWR_REQ,
+	PINGRP_CPU_PWR_REQ,
+	PINGRP_PWR_INT_N,
+	PINGRP_CLK_32K_IN,
+	PINGRP_OWR,
+	PINGRP_DAP1_FS,
+	PINGRP_DAP1_DIN,
+	PINGRP_DAP1_DOUT,
+	PINGRP_DAP1_SCLK,
+	PINGRP_CLK1_REQ,
+	PINGRP_CLK1_OUT,
+	PINGRP_SPDIF_IN,
+	PINGRP_SPDIF_OUT,
+	PINGRP_DAP2_FS,
+	PINGRP_DAP2_DIN,
+	PINGRP_DAP2_DOUT,
+	PINGRP_DAP2_SCLK,
+	PINGRP_SPI2_MOSI,
+	PINGRP_SPI2_MISO,
+	PINGRP_SPI2_CS0_N,
+	PINGRP_SPI2_SCK,
+	PINGRP_SPI1_MOSI,
+	PINGRP_SPI1_SCK,
+	PINGRP_SPI1_CS0_N,
+	PINGRP_SPI1_MISO,
+	PINGRP_SPI2_CS1_N,
+	PINGRP_SPI2_CS2_N,
+	PINGRP_SDMMC3_CLK,
+	PINGRP_SDMMC3_CMD,
+	PINGRP_SDMMC3_DAT0,
+	PINGRP_SDMMC3_DAT1,
+	PINGRP_SDMMC3_DAT2,
+	PINGRP_SDMMC3_DAT3,
+	PINGRP_SDMMC3_DAT4,
+	PINGRP_SDMMC3_DAT5,
+	PINGRP_SDMMC3_DAT6,
+	PINGRP_SDMMC3_DAT7,
+	PINGRP_PEX_L0_PRSNT_N,
+	PINGRP_PEX_L0_RST_N,
+	PINGRP_PEX_L0_CLKREQ_N,
+	PINGRP_PEX_WAKE_N,
+	PINGRP_PEX_L1_PRSNT_N,
+	PINGRP_PEX_L1_RST_N,
+	PINGRP_PEX_L1_CLKREQ_N,
+	PINGRP_PEX_L2_PRSNT_N,
+	PINGRP_PEX_L2_RST_N,
+	PINGRP_PEX_L2_CLKREQ_N,
+	PINGRP_HDMI_CEC,	/* offset 0x33e0 */
+	PINGRP_SDMMC1_WP_N,
+	PINGRP_SDMMC3_CD_N,
+	PINGRP_SPI1_CS1_N,
+	PINGRP_SPI1_CS2_N,
+	PINGRP_USB_VBUS_EN0,    /* offset 0x33f4 */
+	PINGRP_USB_VBUS_EN1,
+	PINGRP_SDMMC3_CLK_LB_IN,
+	PINGRP_SDMMC3_CLK_LB_OUT,
+	PINGRP_NAND_GMI_CLK_LB,
+	PINGRP_RESET_OUT_N,
+	PINGRP_COUNT,
+};
+
+enum pdrive_pingrp {
+	PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
+	PDRIVE_PINGROUP_AO2,
+	PDRIVE_PINGROUP_AT1,
+	PDRIVE_PINGROUP_AT2,
+	PDRIVE_PINGROUP_AT3,
+	PDRIVE_PINGROUP_AT4,
+	PDRIVE_PINGROUP_AT5,
+	PDRIVE_PINGROUP_CDEV1,
+	PDRIVE_PINGROUP_CDEV2,
+	PDRIVE_PINGROUP_CSUS,
+	PDRIVE_PINGROUP_DAP1,
+	PDRIVE_PINGROUP_DAP2,
+	PDRIVE_PINGROUP_DAP3,
+	PDRIVE_PINGROUP_DAP4,
+	PDRIVE_PINGROUP_DBG,
+	PDRIVE_PINGROUP_LCD1,
+	PDRIVE_PINGROUP_LCD2,
+	PDRIVE_PINGROUP_SDIO2,
+	PDRIVE_PINGROUP_SDIO3,
+	PDRIVE_PINGROUP_SPI,
+	PDRIVE_PINGROUP_UAA,
+	PDRIVE_PINGROUP_UAB,
+	PDRIVE_PINGROUP_UART2,
+	PDRIVE_PINGROUP_UART3,
+	PDRIVE_PINGROUP_VI1 = 24,       /* offset 0x8c8 */
+	PDRIVE_PINGROUP_SDIO1 = 33,     /* offset 0x8ec */
+	PDRIVE_PINGROUP_CRT = 36,       /* offset 0x8f8 */
+	PDRIVE_PINGROUP_DDC,
+	PDRIVE_PINGROUP_GMA,
+	PDRIVE_PINGROUP_GMB,
+	PDRIVE_PINGROUP_GMC,
+	PDRIVE_PINGROUP_GMD,
+	PDRIVE_PINGROUP_GME,
+	PDRIVE_PINGROUP_GMF,
+	PDRIVE_PINGROUP_GMG,
+	PDRIVE_PINGROUP_GMH,
+	PDRIVE_PINGROUP_OWR,
+	PDRIVE_PINGROUP_UAD,
+	PDRIVE_PINGROUP_GPV,
+	PDRIVE_PINGROUP_DEV3 = 49,      /* offset 0x92c */
+	PDRIVE_PINGROUP_CEC = 52,       /* offset 0x938 */
+	PDRIVE_PINGROUP_AT6,
+	PDRIVE_PINGROUP_DAP5,
+	PDRIVE_PINGROUP_VBUS,
+	PDRIVE_PINGROUP_COUNT,
+};
+
+/*
+ * Functions which can be assigned to each of the pin groups. The values here
+ * bear no relation to the values programmed into pinmux registers and are
+ * purely a convenience. The translation is done through a table search.
+ */
+enum pmux_func {
+	PMUX_FUNC_AHB_CLK,
+	PMUX_FUNC_APB_CLK,
+	PMUX_FUNC_AUDIO_SYNC,
+	PMUX_FUNC_CRT,
+	PMUX_FUNC_DAP1,
+	PMUX_FUNC_DAP2,
+	PMUX_FUNC_DAP3,
+	PMUX_FUNC_DAP4,
+	PMUX_FUNC_DAP5,
+	PMUX_FUNC_DISPA,
+	PMUX_FUNC_DISPB,
+	PMUX_FUNC_EMC_TEST0_DLL,
+	PMUX_FUNC_EMC_TEST1_DLL,
+	PMUX_FUNC_GMI,
+	PMUX_FUNC_GMI_INT,
+	PMUX_FUNC_HDMI,
+	PMUX_FUNC_I2C1,
+	PMUX_FUNC_I2C2,
+	PMUX_FUNC_I2C3,
+	PMUX_FUNC_IDE,
+	PMUX_FUNC_KBC,
+	PMUX_FUNC_MIO,
+	PMUX_FUNC_MIPI_HS,
+	PMUX_FUNC_NAND,
+	PMUX_FUNC_OSC,
+	PMUX_FUNC_OWR,
+	PMUX_FUNC_PCIE,
+	PMUX_FUNC_PLLA_OUT,
+	PMUX_FUNC_PLLC_OUT1,
+	PMUX_FUNC_PLLM_OUT1,
+	PMUX_FUNC_PLLP_OUT2,
+	PMUX_FUNC_PLLP_OUT3,
+	PMUX_FUNC_PLLP_OUT4,
+	PMUX_FUNC_PWM,
+	PMUX_FUNC_PWR_INTR,
+	PMUX_FUNC_PWR_ON,
+	PMUX_FUNC_RTCK,
+	PMUX_FUNC_SDMMC1,
+	PMUX_FUNC_SDMMC2,
+	PMUX_FUNC_SDMMC3,
+	PMUX_FUNC_SDMMC4,
+	PMUX_FUNC_SFLASH,
+	PMUX_FUNC_SPDIF,
+	PMUX_FUNC_SPI1,
+	PMUX_FUNC_SPI2,
+	PMUX_FUNC_SPI2_ALT,
+	PMUX_FUNC_SPI3,
+	PMUX_FUNC_SPI4,
+	PMUX_FUNC_TRACE,
+	PMUX_FUNC_TWC,
+	PMUX_FUNC_UARTA,
+	PMUX_FUNC_UARTB,
+	PMUX_FUNC_UARTC,
+	PMUX_FUNC_UARTD,
+	PMUX_FUNC_UARTE,
+	PMUX_FUNC_ULPI,
+	PMUX_FUNC_VI,
+	PMUX_FUNC_VI_SENSOR_CLK,
+	PMUX_FUNC_XIO,
+	PMUX_FUNC_BLINK,
+	PMUX_FUNC_CEC,
+	PMUX_FUNC_CLK12,
+	PMUX_FUNC_DAP,
+	PMUX_FUNC_DAPSDMMC2,
+	PMUX_FUNC_DDR,
+	PMUX_FUNC_DEV3,
+	PMUX_FUNC_DTV,
+	PMUX_FUNC_VI_ALT1,
+	PMUX_FUNC_VI_ALT2,
+	PMUX_FUNC_VI_ALT3,
+	PMUX_FUNC_EMC_DLL,
+	PMUX_FUNC_EXTPERIPH1,
+	PMUX_FUNC_EXTPERIPH2,
+	PMUX_FUNC_EXTPERIPH3,
+	PMUX_FUNC_GMI_ALT,
+	PMUX_FUNC_HDA,
+	PMUX_FUNC_HSI,
+	PMUX_FUNC_I2C4,
+	PMUX_FUNC_I2C5,
+	PMUX_FUNC_I2CPWR,
+	PMUX_FUNC_I2S0,
+	PMUX_FUNC_I2S1,
+	PMUX_FUNC_I2S2,
+	PMUX_FUNC_I2S3,
+	PMUX_FUNC_I2S4,
+	PMUX_FUNC_NAND_ALT,
+	PMUX_FUNC_POPSDIO4,
+	PMUX_FUNC_POPSDMMC4,
+	PMUX_FUNC_PWM0,
+	PMUX_FUNC_PWM1,
+	PMUX_FUNC_PWM2,
+	PMUX_FUNC_PWM3,
+	PMUX_FUNC_SATA,
+	PMUX_FUNC_SPI5,
+	PMUX_FUNC_SPI6,
+	PMUX_FUNC_SYSCLK,
+	PMUX_FUNC_VGP1,
+	PMUX_FUNC_VGP2,
+	PMUX_FUNC_VGP3,
+	PMUX_FUNC_VGP4,
+	PMUX_FUNC_VGP5,
+	PMUX_FUNC_VGP6,
+
+	PMUX_FUNC_USB,
+	PMUX_FUNC_SOC,
+	PMUX_FUNC_CPU,
+	PMUX_FUNC_CLK,
+	PMUX_FUNC_PWRON,
+	PMUX_FUNC_PMI,
+	PMUX_FUNC_CLDVFS,
+	PMUX_FUNC_RESET_OUT_N,
+
+	PMUX_FUNC_SAFE,
+	PMUX_FUNC_MAX,
+
+	PMUX_FUNC_RSVD1 = 0x8000,
+	PMUX_FUNC_RSVD2 = 0x8001,
+	PMUX_FUNC_RSVD3 = 0x8002,
+	PMUX_FUNC_RSVD4 = 0x8003,
+};
+
+/* return 1 if a pmux_func is in range */
+#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
+	|| (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
+
+/* return 1 if a pingrp is in range */
+#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
+
+/* The pullup/pulldown state of a pin group */
+enum pmux_pull {
+	PMUX_PULL_NORMAL = 0,
+	PMUX_PULL_DOWN,
+	PMUX_PULL_UP,
+};
+/* return 1 if a pin_pupd_is in range */
+#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
+				((pupd) <= PMUX_PULL_UP))
+
+/* Defines whether a pin group is tristated or in normal operation */
+enum pmux_tristate {
+	PMUX_TRI_NORMAL = 0,
+	PMUX_TRI_TRISTATE = 1,
+};
+/* return 1 if a pin_tristate_is in range */
+#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
+				&& ((tristate) <= PMUX_TRI_TRISTATE))
+
+enum pmux_pin_io {
+	PMUX_PIN_OUTPUT = 0,
+	PMUX_PIN_INPUT = 1,
+};
+/* return 1 if a pin_io_is in range */
+#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
+				((io) <= PMUX_PIN_INPUT))
+
+enum pmux_pin_lock {
+	PMUX_PIN_LOCK_DEFAULT = 0,
+	PMUX_PIN_LOCK_DISABLE,
+	PMUX_PIN_LOCK_ENABLE,
+};
+/* return 1 if a pin_lock is in range */
+#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
+				((lock) <= PMUX_PIN_LOCK_ENABLE))
+
+enum pmux_pin_od {
+	PMUX_PIN_OD_DEFAULT = 0,
+	PMUX_PIN_OD_DISABLE,
+	PMUX_PIN_OD_ENABLE,
+};
+/* return 1 if a pin_od is in range */
+#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
+				((od) <= PMUX_PIN_OD_ENABLE))
+
+enum pmux_pin_ioreset {
+	PMUX_PIN_IO_RESET_DEFAULT = 0,
+	PMUX_PIN_IO_RESET_DISABLE,
+	PMUX_PIN_IO_RESET_ENABLE,
+};
+/* return 1 if a pin_ioreset_is in range */
+#define pmux_pin_ioreset_isvalid(ioreset) \
+				(((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
+				((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+
+/* Available power domains used by pin groups */
+enum pmux_vddio {
+	PMUX_VDDIO_BB = 0,
+	PMUX_VDDIO_LCD,
+	PMUX_VDDIO_VI,
+	PMUX_VDDIO_UART,
+	PMUX_VDDIO_DDR,
+	PMUX_VDDIO_NAND,
+	PMUX_VDDIO_SYS,
+	PMUX_VDDIO_AUDIO,
+	PMUX_VDDIO_SD,
+	PMUX_VDDIO_CAM,
+	PMUX_VDDIO_GMI,
+	PMUX_VDDIO_PEXCTL,
+	PMUX_VDDIO_SDMMC1,
+	PMUX_VDDIO_SDMMC3,
+	PMUX_VDDIO_SDMMC4,
+
+	PMUX_VDDIO_NONE
+};
+
+/* T114 pin drive group and pin mux registers */
+#define PDRIVE_PINGROUP_OFFSET  (0x868 >> 2)
+#define PMUX_OFFSET     ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
+			PDRIVE_PINGROUP_COUNT)
+struct pmux_tri_ctlr {
+	uint pmt_reserved0;		/* ABP_MISC_PP_ reserved offset 00 */
+	uint pmt_reserved1;		/* ABP_MISC_PP_ reserved offset 04 */
+	uint pmt_strap_opt_a;		/* _STRAPPING_OPT_A_0, offset 08   */
+	uint pmt_reserved2;		/* ABP_MISC_PP_ reserved offset 0C */
+	uint pmt_reserved3;		/* ABP_MISC_PP_ reserved offset 10 */
+	uint pmt_reserved4[4];		/* _TRI_STATE_REG_A/B/C/D in t20 */
+	uint pmt_cfg_ctl;		/* _CONFIG_CTL_0, offset 24        */
+
+	uint pmt_reserved[528];		/* ABP_MISC_PP_ reserved offs 28-864 */
+
+	uint pmt_drive[PDRIVE_PINGROUP_COUNT];	/* pin drive grps offs 868 */
+	uint pmt_reserved5[PMUX_OFFSET];
+	uint pmt_ctl[PINGRP_COUNT];	/* mux/pupd/tri regs, offset 0x3000 */
+};
+
+/*
+ * This defines the configuration for a pin, including the function assigned,
+ * pull up/down settings and tristate settings. Having set up one of these
+ * you can call pinmux_config_pingroup() to configure a pin in one step. Also
+ * available is pinmux_config_table() to configure a list of pins.
+ */
+struct pingroup_config {
+	enum pmux_pingrp pingroup;	/* pin group PINGRP_...             */
+	enum pmux_func func;		/* function to assign FUNC_...      */
+	enum pmux_pull pull;		/* pull up/down/normal PMUX_PULL_...*/
+	enum pmux_tristate tristate;	/* tristate or normal PMUX_TRI_...  */
+	enum pmux_pin_io io;		/* input or output PMUX_PIN_...  */
+	enum pmux_pin_lock lock;	/* lock enable/disable PMUX_PIN...  */
+	enum pmux_pin_od od;		/* open-drain or push-pull driver  */
+	enum pmux_pin_ioreset ioreset;	/* input/output reset PMUX_PIN...  */
+};
+
+/* Set a pin group to tristate */
+void pinmux_tristate_enable(enum pmux_pingrp pin);
+
+/* Set a pin group to normal (non tristate) */
+void pinmux_tristate_disable(enum pmux_pingrp pin);
+
+/* Set the pull up/down feature for a pin group */
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
+
+/* Set the mux function for a pin group */
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
+
+/* Set the complete configuration for a pin group */
+void pinmux_config_pingroup(struct pingroup_config *config);
+
+/* Set a pin group to tristate or normal */
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
+
+/* Set a pin group as input or output */
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
+
+/**
+ * Configure a list of pin groups
+ *
+ * @param config	List of config items
+ * @param len		Number of config items in list
+ */
+void pinmux_config_table(struct pingroup_config *config, int len);
+
+/* Set a group of pins from a table */
+void pinmux_init(void);
+
+#endif  /* _TEGRA114_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/pmu.h b/arch/arm/include/asm/arch-tegra114/pmu.h
new file mode 100644
index 0000000..c6e2381
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/pmu.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_PMU_H_
+#define _TEGRA114_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif	/* _TEGRA114_PMU_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/spl.h b/arch/arm/include/asm/arch-tegra114/spl.h
new file mode 100644
index 0000000..ebb16fe
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/spl.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_RAM         1
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h
new file mode 100644
index 0000000..a3d12d6
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/tegra.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_H_
+#define _TEGRA114_H_
+
+#define NV_PA_SDRAM_BASE	0x80000000	/* 0x80000000 for real T114 */
+
+#include <asm/arch-tegra/tegra.h>
+
+#define BCT_ODMDATA_OFFSET	1752	/* offset to ODMDATA word */
+
+#undef NVBOOTINFOTABLE_BCTSIZE
+#undef NVBOOTINFOTABLE_BCTPTR
+#define NVBOOTINFOTABLE_BCTSIZE        0x48    /* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR 0x4C    /* BCT pointer in BIT in IRAM */
+
+#define MAX_NUM_CPU            4
+
+#endif /* TEGRA114_H */
diff --git a/arch/arm/include/asm/arch-tegra20/clock-tables.h b/arch/arm/include/asm/arch-tegra20/clock-tables.h
index 53708e0..6ec5ccb 100644
--- a/arch/arm/include/asm/arch-tegra20/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra20/clock-tables.h
@@ -193,4 +193,8 @@
 #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
 		(id) < CLOCK_ID_FIRST_SIMPLE)
 
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+		(id) < PERIPH_ID_COUNT)
+
 #endif	/* _CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/clock.h b/arch/arm/include/asm/arch-tegra20/clock.h
index f592b95..491c02c 100644
--- a/arch/arm/include/asm/arch-tegra20/clock.h
+++ b/arch/arm/include/asm/arch-tegra20/clock.h
@@ -26,4 +26,8 @@
 
 #include <asm/arch-tegra/clock.h>
 
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT          30
+#define OSC_FREQ_MASK           (3U << OSC_FREQ_SHIFT)
+
 #endif	/* _TEGRA20_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-tegra20/funcmux.h b/arch/arm/include/asm/arch-tegra20/funcmux.h
index c986b93..7f15bce 100644
--- a/arch/arm/include/asm/arch-tegra20/funcmux.h
+++ b/arch/arm/include/asm/arch-tegra20/funcmux.h
@@ -21,8 +21,10 @@
 
 /* Tegra20 high-level function multiplexing */
 
-#ifndef __FUNCMUX_H
-#define __FUNCMUX_H
+#ifndef _TEGRA20_FUNCMUX_H_
+#define _TEGRA20_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
 
 /* Configs supported by the func mux */
 enum {
@@ -33,7 +35,7 @@
 	FUNCMUX_UART1_UAA_UAB,
 	FUNCMUX_UART1_GPU,
 	FUNCMUX_UART1_SDIO1,
-	FUNCMUX_UART2_IRDA = 0,
+	FUNCMUX_UART2_UAD = 0,
 	FUNCMUX_UART4_GMC = 0,
 
 	/* I2C configs */
@@ -62,22 +64,4 @@
 	FUNCMUX_NDFLASH_ATC = 0,
 	FUNCMUX_NDFLASH_KBC_8_BIT,
 };
-
-/**
- * Select a config for a particular peripheral.
- *
- * Each peripheral can operate through a number of configurations,
- * which are sets of pins that it uses to bring out its signals.
- * The basic config is 0, and higher numbers indicate different
- * pinmux settings to bring the peripheral out on other pins,
- *
- * This function also disables tristate for the function's pins,
- * so that they operate in normal mode.
- *
- * @param id		Peripheral id
- * @param config	Configuration to use (FUNCMUX_...), 0 for default
- * @return 0 if ok, -1 on error (e.g. incorrect id or config)
- */
-int funcmux_select(enum periph_id id, int config);
-
-#endif
+#endif	/* _TEGRA20_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/gp_padctrl.h b/arch/arm/include/asm/arch-tegra20/gp_padctrl.h
index 865af5b..eaaf903 100644
--- a/arch/arm/include/asm/arch-tegra20/gp_padctrl.h
+++ b/arch/arm/include/asm/arch-tegra20/gp_padctrl.h
@@ -21,8 +21,10 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _GP_PADCTRL_H_
-#define _GP_PADCTRL_H_
+#ifndef _TEGRA20_GP_PADCTRL_H_
+#define _TEGRA20_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
 
 /* APB_MISC_GP and padctrl registers */
 struct apb_misc_gp_ctlr {
@@ -61,13 +63,4 @@
 	u32	memcomp;	/* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */
 };
 
-/* bit fields definitions for APB_MISC_GP_HIDREV register */
-#define HIDREV_CHIPID_SHIFT		8
-#define HIDREV_CHIPID_MASK		(0xff << HIDREV_CHIPID_SHIFT)
-#define HIDREV_MAJORPREV_SHIFT		4
-#define HIDREV_MAJORPREV_MASK		(0xf << HIDREV_MAJORPREV_SHIFT)
-
-/* CHIPID field returned from APB_MISC_GP_HIDREV register */
-#define CHIPID_TEGRA20				0x20
-
-#endif
+#endif	/* _TEGRA20_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
index 797e158..a9b4eda 100644
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -204,7 +204,6 @@
 	PMUX_FUNC_I2C2,
 	PMUX_FUNC_I2C3,
 	PMUX_FUNC_IDE,
-	PMUX_FUNC_IRDA,
 	PMUX_FUNC_KBC,
 	PMUX_FUNC_MIO,
 	PMUX_FUNC_MIPI_HS,
diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h
index ca98733..e1de044 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra.h
@@ -33,4 +33,6 @@
 
 #define BCT_ODMDATA_OFFSET	4068	/* 12 bytes from end of BCT */
 
+#define MAX_NUM_CPU		2
+
 #endif	/* TEGRA20_H */
diff --git a/arch/arm/include/asm/arch-tegra30/clock-tables.h b/arch/arm/include/asm/arch-tegra30/clock-tables.h
new file mode 100644
index 0000000..cb619f1
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/clock-tables.h
@@ -0,0 +1,382 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 clock PLL tables */
+
+#ifndef _TEGRA30_CLOCK_TABLES_H_
+#define _TEGRA30_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+	CLOCK_ID_FIRST,
+	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+	CLOCK_ID_MEMORY,
+	CLOCK_ID_PERIPH,
+	CLOCK_ID_AUDIO,
+	CLOCK_ID_USB,
+	CLOCK_ID_DISPLAY,
+
+	/* now the simple ones */
+	CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_EPCI,
+	CLOCK_ID_SFROM32KHZ,
+
+	/* These are the base clocks (inputs to the Tegra SOC) */
+	CLOCK_ID_32KHZ,
+	CLOCK_ID_OSC,
+
+	CLOCK_ID_COUNT,	/* number of PLLs */
+	CLOCK_ID_DISPLAY2,	/* Tegra3, placeholder */
+	CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+	PERIPH_ID_FIRST,
+
+	/* Low word: 31:0 */
+	PERIPH_ID_CPU = PERIPH_ID_FIRST,
+	PERIPH_ID_COP,
+	PERIPH_ID_TRIGSYS,
+	PERIPH_ID_RESERVED3,
+	PERIPH_ID_RESERVED4,
+	PERIPH_ID_TMR,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+
+	/* 8 */
+	PERIPH_ID_GPIO,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_SPDIF,
+	PERIPH_ID_I2S1,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_NDFLASH,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC4,
+
+	/* 16 */
+	PERIPH_ID_RESERVED16,
+	PERIPH_ID_PWM,
+	PERIPH_ID_I2S2,
+	PERIPH_ID_EPP,
+	PERIPH_ID_VI,
+	PERIPH_ID_2D,
+	PERIPH_ID_USBD,
+	PERIPH_ID_ISP,
+
+	/* 24 */
+	PERIPH_ID_3D,
+	PERIPH_ID_RESERVED24,
+	PERIPH_ID_DISP2,
+	PERIPH_ID_DISP1,
+	PERIPH_ID_HOST1X,
+	PERIPH_ID_VCP,
+	PERIPH_ID_I2S0,
+	PERIPH_ID_CACHE2,
+
+	/* Middle word: 63:32 */
+	PERIPH_ID_MEM,
+	PERIPH_ID_AHBDMA,
+	PERIPH_ID_APBDMA,
+	PERIPH_ID_RESERVED35,
+	PERIPH_ID_KBC,
+	PERIPH_ID_STAT_MON,
+	PERIPH_ID_PMC,
+	PERIPH_ID_FUSE,
+
+	/* 40 */
+	PERIPH_ID_KFUSE,
+	PERIPH_ID_SBC1,
+	PERIPH_ID_SNOR,
+	PERIPH_ID_RESERVED43,
+	PERIPH_ID_SBC2,
+	PERIPH_ID_RESERVED45,
+	PERIPH_ID_SBC3,
+	PERIPH_ID_DVC_I2C,
+
+	/* 48 */
+	PERIPH_ID_DSI,
+	PERIPH_ID_TVO,
+	PERIPH_ID_MIPI,
+	PERIPH_ID_HDMI,
+	PERIPH_ID_CSI,
+	PERIPH_ID_TVDAC,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_UART3,
+
+	/* 56 */
+	PERIPH_ID_RESERVED56,
+	PERIPH_ID_EMC,
+	PERIPH_ID_USB2,
+	PERIPH_ID_USB3,
+	PERIPH_ID_MPE,
+	PERIPH_ID_VDE,
+	PERIPH_ID_BSEA,
+	PERIPH_ID_BSEV,
+
+	/* Upper word 95:64 */
+	PERIPH_ID_SPEEDO,
+	PERIPH_ID_UART4,
+	PERIPH_ID_UART5,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_SBC4,
+	PERIPH_ID_SDMMC3,
+	PERIPH_ID_PCIE,
+	PERIPH_ID_OWR,
+
+	/* 72 */
+	PERIPH_ID_AFI,
+	PERIPH_ID_CORESIGHT,
+	PERIPH_ID_PCIEXCLK,
+	PERIPH_ID_AVPUCQ,
+	PERIPH_ID_RESERVED76,
+	PERIPH_ID_RESERVED77,
+	PERIPH_ID_RESERVED78,
+	PERIPH_ID_DTV,
+
+	/* 80 */
+	PERIPH_ID_NANDSPEED,
+	PERIPH_ID_I2CSLOW,
+	PERIPH_ID_DSIB,
+	PERIPH_ID_RESERVED83,
+	PERIPH_ID_IRAMA,
+	PERIPH_ID_IRAMB,
+	PERIPH_ID_IRAMC,
+	PERIPH_ID_IRAMD,
+
+	/* 88 */
+	PERIPH_ID_CRAM2,
+	PERIPH_ID_RESERVED89,
+	PERIPH_ID_MDOUBLER,
+	PERIPH_ID_RESERVED91,
+	PERIPH_ID_SUSOUT,
+	PERIPH_ID_RESERVED93,
+	PERIPH_ID_RESERVED94,
+	PERIPH_ID_RESERVED95,
+
+	PERIPH_ID_VW_FIRST,
+	/* V word: 31:0 */
+	PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+	PERIPH_ID_CPULP,
+	PERIPH_ID_3D2,
+	PERIPH_ID_MSELECT,
+	PERIPH_ID_TSENSOR,
+	PERIPH_ID_I2S3,
+	PERIPH_ID_I2S4,
+	PERIPH_ID_I2C4,
+
+	/* 08 */
+	PERIPH_ID_SBC5,
+	PERIPH_ID_SBC6,
+	PERIPH_ID_AUDIO,
+	PERIPH_ID_APBIF,
+	PERIPH_ID_DAM0,
+	PERIPH_ID_DAM1,
+	PERIPH_ID_DAM2,
+	PERIPH_ID_HDA2CODEC2X,
+
+	/* 16 */
+	PERIPH_ID_ATOMICS,
+	PERIPH_ID_EX_RESERVED17,
+	PERIPH_ID_EX_RESERVED18,
+	PERIPH_ID_EX_RESERVED19,
+	PERIPH_ID_EX_RESERVED20,
+	PERIPH_ID_EX_RESERVED21,
+	PERIPH_ID_EX_RESERVED22,
+	PERIPH_ID_ACTMON,
+
+	/* 24 */
+	PERIPH_ID_EX_RESERVED24,
+	PERIPH_ID_EX_RESERVED25,
+	PERIPH_ID_EX_RESERVED26,
+	PERIPH_ID_EX_RESERVED27,
+	PERIPH_ID_SATA,
+	PERIPH_ID_HDA,
+	PERIPH_ID_EX_RESERVED30,
+	PERIPH_ID_EX_RESERVED31,
+
+	/* W word: 31:0 */
+	PERIPH_ID_HDA2HDMICODEC,
+	PERIPH_ID_SATACOLD,
+	PERIPH_ID_RESERVED0_PCIERX0,
+	PERIPH_ID_RESERVED1_PCIERX1,
+	PERIPH_ID_RESERVED2_PCIERX2,
+	PERIPH_ID_RESERVED3_PCIERX3,
+	PERIPH_ID_RESERVED4_PCIERX4,
+	PERIPH_ID_RESERVED5_PCIERX5,
+
+	/* 40 */
+	PERIPH_ID_CEC,
+	PERIPH_ID_RESERVED6_PCIE2,
+	PERIPH_ID_RESERVED7_EMC,
+	PERIPH_ID_RESERVED8_HDMI,
+	PERIPH_ID_RESERVED9_SATA,
+	PERIPH_ID_RESERVED10_MIPI,
+	PERIPH_ID_EX_RESERVED46,
+	PERIPH_ID_EX_RESERVED47,
+
+	PERIPH_ID_COUNT,
+	PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+	PLL_OUT1,
+	PLL_OUT2,
+	PLL_OUT3,
+	PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+	/* 0x00 */
+	PERIPHC_I2S1,
+	PERIPHC_I2S2,
+	PERIPHC_SPDIF_OUT,
+	PERIPHC_SPDIF_IN,
+	PERIPHC_PWM,
+	PERIPHC_05h,
+	PERIPHC_SBC2,
+	PERIPHC_SBC3,
+
+	/* 0x08 */
+	PERIPHC_08h,
+	PERIPHC_I2C1,
+	PERIPHC_DVC_I2C,
+	PERIPHC_0bh,
+	PERIPHC_0ch,
+	PERIPHC_SBC1,
+	PERIPHC_DISP1,
+	PERIPHC_DISP2,
+
+	/* 0x10 */
+	PERIPHC_CVE,
+	PERIPHC_11h,
+	PERIPHC_VI,
+	PERIPHC_13h,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC2,
+	PERIPHC_G3D,
+	PERIPHC_G2D,
+
+	/* 0x18 */
+	PERIPHC_NDFLASH,
+	PERIPHC_SDMMC4,
+	PERIPHC_VFIR,
+	PERIPHC_EPP,
+	PERIPHC_MPE,
+	PERIPHC_MIPI,
+	PERIPHC_UART1,
+	PERIPHC_UART2,
+
+	/* 0x20 */
+	PERIPHC_HOST1X,
+	PERIPHC_21h,
+	PERIPHC_TVO,
+	PERIPHC_HDMI,
+	PERIPHC_24h,
+	PERIPHC_TVDAC,
+	PERIPHC_I2C2,
+	PERIPHC_EMC,
+
+	/* 0x28 */
+	PERIPHC_UART3,
+	PERIPHC_29h,
+	PERIPHC_VI_SENSOR,
+	PERIPHC_2bh,
+	PERIPHC_2ch,
+	PERIPHC_SBC4,
+	PERIPHC_I2C3,
+	PERIPHC_SDMMC3,
+
+	/* 0x30 */
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_VDE,
+	PERIPHC_OWR,
+	PERIPHC_NOR,
+	PERIPHC_CSITE,
+	PERIPHC_I2S0,
+	PERIPHC_37h,
+
+	PERIPHC_VW_FIRST,
+	/* 0x38 */
+	PERIPHC_G3D2 = PERIPHC_VW_FIRST,
+	PERIPHC_MSELECT,
+	PERIPHC_TSENSOR,
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+
+	/* 0x40 */
+	PERIPHC_AUDIO,
+	PERIPHC_41h,
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+	PERIPHC_ACTMON,
+	PERIPHC_EXTPERIPH1,
+
+	/* 0x48 */
+	PERIPHC_EXTPERIPH2,
+	PERIPHC_EXTPERIPH3,
+	PERIPHC_NANDSPEED,
+	PERIPHC_I2CSLOW,
+	PERIPHC_SYS,
+	PERIPHC_SPEEDO,
+	PERIPHC_4eh,
+	PERIPHC_4fh,
+
+	/* 0x50 */
+	PERIPHC_50h,
+	PERIPHC_51h,
+	PERIPHC_52h,
+	PERIPHC_53h,
+	PERIPHC_SATAOOB,
+	PERIPHC_SATA,
+	PERIPHC_HDA,
+
+	PERIPHC_COUNT,
+
+	PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+	(id < PERIPH_ID_VW_FIRST) ? \
+		((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+		(id) < PERIPH_ID_COUNT)
+
+#endif	/* _TEGRA30_CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/clock.h b/arch/arm/include/asm/arch-tegra30/clock.h
new file mode 100644
index 0000000..2f24a75
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/clock.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 clock control functions */
+
+#ifndef _TEGRA30_CLOCK_H_
+#define _TEGRA30_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT          28
+#define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
+
+#endif	/* _TEGRA30_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/flow.h b/arch/arm/include/asm/arch-tegra30/flow.h
new file mode 100644
index 0000000..f5966a8
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/flow.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_FLOW_H_
+#define _TEGRA30_FLOW_H_
+
+struct flow_ctlr {
+	u32 halt_cpu_events;
+	u32 halt_cop_events;
+	u32 cpu_csr;
+	u32 cop_csr;
+	u32 xrq_events;
+	u32 halt_cpu1_events;
+	u32 cpu1_csr;
+	u32 halt_cpu2_events;
+	u32 cpu2_csr;
+	u32 halt_cpu3_events;
+	u32 cpu3_csr;
+	u32 cluster_control;
+};
+
+#endif	/* _TEGRA30_FLOW_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/funcmux.h b/arch/arm/include/asm/arch-tegra30/funcmux.h
new file mode 100644
index 0000000..24b2bca
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/funcmux.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 high-level function multiplexing */
+
+#ifndef _TEGRA30_FUNCMUX_H_
+#define _TEGRA30_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+	FUNCMUX_DEFAULT = 0,	/* default config */
+
+	/* UART configs */
+	FUNCMUX_UART1_ULPI = 0,
+};
+#endif	/* _TEGRA30_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
new file mode 100644
index 0000000..9b383d0
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_GP_PADCTRL_H_
+#define _TEGRA30_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+	u32	modereg;	/* 0x00: APB_MISC_GP_MODEREG */
+	u32	hidrev;		/* 0x04: APB_MISC_GP_HIDREV */
+	u32	reserved0[22];	/* 0x08 - 0x5C: */
+	u32	emu_revid;	/* 0x60: APB_MISC_GP_EMU_REVID */
+	u32	xactor_scratch;	/* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+	u32	aocfg1;		/* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+	u32	aocfg2;		/* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
+	u32	atcfg1;		/* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+	u32	atcfg2;		/* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+	u32	atcfg3;		/* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+	u32	atcfg4;		/* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+	u32	atcfg5;		/* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+	u32	cdev1cfg;	/* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+	u32	cdev2cfg;	/* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+	u32	csuscfg;	/* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
+	u32	dap1cfg;	/* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+	u32	dap2cfg;	/* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+	u32	dap3cfg;	/* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+	u32	dap4cfg;	/* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+	u32	dbgcfg;		/* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+	u32	lcdcfg1;	/* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
+	u32	lcdcfg2;	/* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
+	u32	sdio2cfg;	/* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
+	u32	sdio3cfg;	/* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+	u32	spicfg;		/* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+	u32	uaacfg;		/* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+	u32	uabcfg;		/* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+	u32	uart2cfg;	/* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+	u32	uart3cfg;	/* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+	u32	vicfg1;		/* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
+	u32	vivttgen;	/* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
+	u32	reserved1[7];	/* 0xD0-0xE8: */
+	u32	sdio1cfg;	/* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+};
+
+#endif	/* _TEGRA30_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/gpio.h b/arch/arm/include/asm/arch-tegra30/gpio.h
new file mode 100644
index 0000000..f1c89f5
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/gpio.h
@@ -0,0 +1,304 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_GPIO_H_
+#define _TEGRA30_GPIO_H_
+
+/*
+ * The Tegra 3x GPIO controller has 246 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS	4	/* number of ports per bank */
+#define TEGRA_GPIO_BANKS	8	/* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+	uint gpio_config[TEGRA_GPIO_PORTS];
+	uint gpio_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_out[TEGRA_GPIO_PORTS];
+	uint gpio_in[TEGRA_GPIO_PORTS];
+	uint gpio_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_int_clear[TEGRA_GPIO_PORTS];
+	uint gpio_masked_config[TEGRA_GPIO_PORTS];
+	uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_masked_out[TEGRA_GPIO_PORTS];
+	uint gpio_masked_in[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+enum gpio_pin {
+	GPIO_PA0 = 0,	/* pin 0 */
+	GPIO_PA1,
+	GPIO_PA2,
+	GPIO_PA3,
+	GPIO_PA4,
+	GPIO_PA5,
+	GPIO_PA6,
+	GPIO_PA7,
+	GPIO_PB0,	/* pin 8 */
+	GPIO_PB1,
+	GPIO_PB2,
+	GPIO_PB3,
+	GPIO_PB4,
+	GPIO_PB5,
+	GPIO_PB6,
+	GPIO_PB7,
+	GPIO_PC0,	/* pin 16 */
+	GPIO_PC1,
+	GPIO_PC2,
+	GPIO_PC3,
+	GPIO_PC4,
+	GPIO_PC5,
+	GPIO_PC6,
+	GPIO_PC7,
+	GPIO_PD0,	/* pin 24 */
+	GPIO_PD1,
+	GPIO_PD2,
+	GPIO_PD3,
+	GPIO_PD4,
+	GPIO_PD5,
+	GPIO_PD6,
+	GPIO_PD7,
+	GPIO_PE0,	/* pin 32 */
+	GPIO_PE1,
+	GPIO_PE2,
+	GPIO_PE3,
+	GPIO_PE4,
+	GPIO_PE5,
+	GPIO_PE6,
+	GPIO_PE7,
+	GPIO_PF0,	/* pin 40 */
+	GPIO_PF1,
+	GPIO_PF2,
+	GPIO_PF3,
+	GPIO_PF4,
+	GPIO_PF5,
+	GPIO_PF6,
+	GPIO_PF7,
+	GPIO_PG0,	/* pin 48 */
+	GPIO_PG1,
+	GPIO_PG2,
+	GPIO_PG3,
+	GPIO_PG4,
+	GPIO_PG5,
+	GPIO_PG6,
+	GPIO_PG7,
+	GPIO_PH0,	/* pin 56 */
+	GPIO_PH1,
+	GPIO_PH2,
+	GPIO_PH3,
+	GPIO_PH4,
+	GPIO_PH5,
+	GPIO_PH6,
+	GPIO_PH7,
+	GPIO_PI0,	/* pin 64 */
+	GPIO_PI1,
+	GPIO_PI2,
+	GPIO_PI3,
+	GPIO_PI4,
+	GPIO_PI5,
+	GPIO_PI6,
+	GPIO_PI7,
+	GPIO_PJ0,	/* pin 72 */
+	GPIO_PJ1,
+	GPIO_PJ2,
+	GPIO_PJ3,
+	GPIO_PJ4,
+	GPIO_PJ5,
+	GPIO_PJ6,
+	GPIO_PJ7,
+	GPIO_PK0,	/* pin 80 */
+	GPIO_PK1,
+	GPIO_PK2,
+	GPIO_PK3,
+	GPIO_PK4,
+	GPIO_PK5,
+	GPIO_PK6,
+	GPIO_PK7,
+	GPIO_PL0,	/* pin 88 */
+	GPIO_PL1,
+	GPIO_PL2,
+	GPIO_PL3,
+	GPIO_PL4,
+	GPIO_PL5,
+	GPIO_PL6,
+	GPIO_PL7,
+	GPIO_PM0,	/* pin 96 */
+	GPIO_PM1,
+	GPIO_PM2,
+	GPIO_PM3,
+	GPIO_PM4,
+	GPIO_PM5,
+	GPIO_PM6,
+	GPIO_PM7,
+	GPIO_PN0,	/* pin 104 */
+	GPIO_PN1,
+	GPIO_PN2,
+	GPIO_PN3,
+	GPIO_PN4,
+	GPIO_PN5,
+	GPIO_PN6,
+	GPIO_PN7,
+	GPIO_PO0,	/* pin 112 */
+	GPIO_PO1,
+	GPIO_PO2,
+	GPIO_PO3,
+	GPIO_PO4,
+	GPIO_PO5,
+	GPIO_PO6,
+	GPIO_PO7,
+	GPIO_PP0,	/* pin 120 */
+	GPIO_PP1,
+	GPIO_PP2,
+	GPIO_PP3,
+	GPIO_PP4,
+	GPIO_PP5,
+	GPIO_PP6,
+	GPIO_PP7,
+	GPIO_PQ0,	/* pin 128 */
+	GPIO_PQ1,
+	GPIO_PQ2,
+	GPIO_PQ3,
+	GPIO_PQ4,
+	GPIO_PQ5,
+	GPIO_PQ6,
+	GPIO_PQ7,
+	GPIO_PR0,	/* pin 136 */
+	GPIO_PR1,
+	GPIO_PR2,
+	GPIO_PR3,
+	GPIO_PR4,
+	GPIO_PR5,
+	GPIO_PR6,
+	GPIO_PR7,
+	GPIO_PS0,	/* pin 144 */
+	GPIO_PS1,
+	GPIO_PS2,
+	GPIO_PS3,
+	GPIO_PS4,
+	GPIO_PS5,
+	GPIO_PS6,
+	GPIO_PS7,
+	GPIO_PT0,	/* pin 152 */
+	GPIO_PT1,
+	GPIO_PT2,
+	GPIO_PT3,
+	GPIO_PT4,
+	GPIO_PT5,
+	GPIO_PT6,
+	GPIO_PT7,
+	GPIO_PU0,	/* pin 160 */
+	GPIO_PU1,
+	GPIO_PU2,
+	GPIO_PU3,
+	GPIO_PU4,
+	GPIO_PU5,
+	GPIO_PU6,
+	GPIO_PU7,
+	GPIO_PV0,	/* pin 168 */
+	GPIO_PV1,
+	GPIO_PV2,
+	GPIO_PV3,
+	GPIO_PV4,
+	GPIO_PV5,
+	GPIO_PV6,
+	GPIO_PV7,
+	GPIO_PW0,	/* pin 176 */
+	GPIO_PW1,
+	GPIO_PW2,
+	GPIO_PW3,
+	GPIO_PW4,
+	GPIO_PW5,
+	GPIO_PW6,
+	GPIO_PW7,
+	GPIO_PX0,	/* pin 184 */
+	GPIO_PX1,
+	GPIO_PX2,
+	GPIO_PX3,
+	GPIO_PX4,
+	GPIO_PX5,
+	GPIO_PX6,
+	GPIO_PX7,
+	GPIO_PY0,	/* pin 192 */
+	GPIO_PY1,
+	GPIO_PY2,
+	GPIO_PY3,
+	GPIO_PY4,
+	GPIO_PY5,
+	GPIO_PY6,
+	GPIO_PY7,
+	GPIO_PZ0,	/* pin 200 */
+	GPIO_PZ1,
+	GPIO_PZ2,
+	GPIO_PZ3,
+	GPIO_PZ4,
+	GPIO_PZ5,
+	GPIO_PZ6,
+	GPIO_PZ7,
+	GPIO_PAA0,	/* pin 208 */
+	GPIO_PAA1,
+	GPIO_PAA2,
+	GPIO_PAA3,
+	GPIO_PAA4,
+	GPIO_PAA5,
+	GPIO_PAA6,
+	GPIO_PAA7,
+	GPIO_PBB0,	/* pin 216 */
+	GPIO_PBB1,
+	GPIO_PBB2,
+	GPIO_PBB3,
+	GPIO_PBB4,
+	GPIO_PBB5,
+	GPIO_PBB6,
+	GPIO_PBB7,
+	GPIO_PCC0,	/* pin 224 */
+	GPIO_PCC1,
+	GPIO_PCC2,
+	GPIO_PCC3,
+	GPIO_PCC4,
+	GPIO_PCC5,
+	GPIO_PCC6,
+	GPIO_PCC7,
+	GPIO_PDD0,	/* pin 232 */
+	GPIO_PDD1,
+	GPIO_PDD2,
+	GPIO_PDD3,
+	GPIO_PDD4,
+	GPIO_PDD5,
+	GPIO_PDD6,
+	GPIO_PDD7,
+	GPIO_PEE0,	/* pin 240 */
+	GPIO_PEE1,
+	GPIO_PEE2,
+	GPIO_PEE3,
+	GPIO_PEE4,
+	GPIO_PEE5,
+	GPIO_PEE6,
+	GPIO_PEE7,	/* pin 247 */
+};
+
+#endif	/* _TEGRA30_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/hardware.h b/arch/arm/include/asm/arch-tegra30/hardware.h
new file mode 100644
index 0000000..b1a5aa9
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/hardware.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_HARDWARE_H_
+#define _TEGRA30_HARDWARE_H_
+
+/* include tegra specific hardware definitions */
+
+#endif /* _TEGRA30-HARDWARE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h
new file mode 100644
index 0000000..341951b
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/pinmux.h
@@ -0,0 +1,603 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_PINMUX_H_
+#define _TEGRA30_PINMUX_H_
+
+/*
+ * Pin groups which we adjust. There are three basic attributes of each pin
+ * group which use this enum:
+ *
+ *	- function
+ *	- pullup / pulldown
+ *	- tristate or normal
+ */
+enum pmux_pingrp {
+	PINGRP_ULPI_DATA0 = 0,  /* offset 0x3000 */
+	PINGRP_ULPI_DATA1,
+	PINGRP_ULPI_DATA2,
+	PINGRP_ULPI_DATA3,
+	PINGRP_ULPI_DATA4,
+	PINGRP_ULPI_DATA5,
+	PINGRP_ULPI_DATA6,
+	PINGRP_ULPI_DATA7,
+	PINGRP_ULPI_CLK,
+	PINGRP_ULPI_DIR,
+	PINGRP_ULPI_NXT,
+	PINGRP_ULPI_STP,
+	PINGRP_DAP3_FS,
+	PINGRP_DAP3_DIN,
+	PINGRP_DAP3_DOUT,
+	PINGRP_DAP3_SCLK,
+	PINGRP_GPIO_PV0,
+	PINGRP_GPIO_PV1,
+	PINGRP_SDMMC1_CLK,
+	PINGRP_SDMMC1_CMD,
+	PINGRP_SDMMC1_DAT3,
+	PINGRP_SDMMC1_DAT2,
+	PINGRP_SDMMC1_DAT1,
+	PINGRP_SDMMC1_DAT0,
+	PINGRP_GPIO_PV2,
+	PINGRP_GPIO_PV3,
+	PINGRP_CLK2_OUT,
+	PINGRP_CLK2_REQ,
+	PINGRP_LCD_PWR1,
+	PINGRP_LCD_PWR2,
+	PINGRP_LCD_SDIN,
+	PINGRP_LCD_SDOUT,
+	PINGRP_LCD_WR_N,
+	PINGRP_LCD_CS0_N,
+	PINGRP_LCD_DC0,
+	PINGRP_LCD_SCK,
+	PINGRP_LCD_PWR0,
+	PINGRP_LCD_PCLK,
+	PINGRP_LCD_DE,
+	PINGRP_LCD_HSYNC,
+	PINGRP_LCD_VSYNC,
+	PINGRP_LCD_D0,
+	PINGRP_LCD_D1,
+	PINGRP_LCD_D2,
+	PINGRP_LCD_D3,
+	PINGRP_LCD_D4,
+	PINGRP_LCD_D5,
+	PINGRP_LCD_D6,
+	PINGRP_LCD_D7,
+	PINGRP_LCD_D8,
+	PINGRP_LCD_D9,
+	PINGRP_LCD_D10,
+	PINGRP_LCD_D11,
+	PINGRP_LCD_D12,
+	PINGRP_LCD_D13,
+	PINGRP_LCD_D14,
+	PINGRP_LCD_D15,
+	PINGRP_LCD_D16,
+	PINGRP_LCD_D17,
+	PINGRP_LCD_D18,
+	PINGRP_LCD_D19,
+	PINGRP_LCD_D20,
+	PINGRP_LCD_D21,
+	PINGRP_LCD_D22,
+	PINGRP_LCD_D23,
+	PINGRP_LCD_CS1_N,
+	PINGRP_LCD_M1,
+	PINGRP_LCD_DC1,
+	PINGRP_HDMI_INT,
+	PINGRP_DDC_SCL,
+	PINGRP_DDC_SDA,
+	PINGRP_CRT_HSYNC,
+	PINGRP_CRT_VSYNC,
+	PINGRP_VI_D0,
+	PINGRP_VI_D1,
+	PINGRP_VI_D2,
+	PINGRP_VI_D3,
+	PINGRP_VI_D4,
+	PINGRP_VI_D5,
+	PINGRP_VI_D6,
+	PINGRP_VI_D7,
+	PINGRP_VI_D8,
+	PINGRP_VI_D9,
+	PINGRP_VI_D10,
+	PINGRP_VI_D11,
+	PINGRP_VI_PCLK,
+	PINGRP_VI_MCLK,
+	PINGRP_VI_VSYNC,
+	PINGRP_VI_HSYNC,
+	PINGRP_UART2_RXD,
+	PINGRP_UART2_TXD,
+	PINGRP_UART2_RTS_N,
+	PINGRP_UART2_CTS_N,
+	PINGRP_UART3_TXD,
+	PINGRP_UART3_RXD,
+	PINGRP_UART3_CTS_N,
+	PINGRP_UART3_RTS_N,
+	PINGRP_GPIO_PU0,
+	PINGRP_GPIO_PU1,
+	PINGRP_GPIO_PU2,
+	PINGRP_GPIO_PU3,
+	PINGRP_GPIO_PU4,
+	PINGRP_GPIO_PU5,
+	PINGRP_GPIO_PU6,
+	PINGRP_GEN1_I2C_SDA,
+	PINGRP_GEN1_I2C_SCL,
+	PINGRP_DAP4_FS,
+	PINGRP_DAP4_DIN,
+	PINGRP_DAP4_DOUT,
+	PINGRP_DAP4_SCLK,
+	PINGRP_CLK3_OUT,
+	PINGRP_CLK3_REQ,
+	PINGRP_GMI_WP_N,
+	PINGRP_GMI_IORDY,
+	PINGRP_GMI_WAIT,
+	PINGRP_GMI_ADV_N,
+	PINGRP_GMI_CLK,
+	PINGRP_GMI_CS0_N,
+	PINGRP_GMI_CS1_N,
+	PINGRP_GMI_CS2_N,
+	PINGRP_GMI_CS3_N,
+	PINGRP_GMI_CS4_N,
+	PINGRP_GMI_CS6_N,
+	PINGRP_GMI_CS7_N,
+	PINGRP_GMI_AD0,
+	PINGRP_GMI_AD1,
+	PINGRP_GMI_AD2,
+	PINGRP_GMI_AD3,
+	PINGRP_GMI_AD4,
+	PINGRP_GMI_AD5,
+	PINGRP_GMI_AD6,
+	PINGRP_GMI_AD7,
+	PINGRP_GMI_AD8,
+	PINGRP_GMI_AD9,
+	PINGRP_GMI_AD10,
+	PINGRP_GMI_AD11,
+	PINGRP_GMI_AD12,
+	PINGRP_GMI_AD13,
+	PINGRP_GMI_AD14,
+	PINGRP_GMI_AD15,
+	PINGRP_GMI_A16,
+	PINGRP_GMI_A17,
+	PINGRP_GMI_A18,
+	PINGRP_GMI_A19,
+	PINGRP_GMI_WR_N,
+	PINGRP_GMI_OE_N,
+	PINGRP_GMI_DQS,
+	PINGRP_GMI_RST_N,
+	PINGRP_GEN2_I2C_SCL,
+	PINGRP_GEN2_I2C_SDA,
+	PINGRP_SDMMC4_CLK,
+	PINGRP_SDMMC4_CMD,
+	PINGRP_SDMMC4_DAT0,
+	PINGRP_SDMMC4_DAT1,
+	PINGRP_SDMMC4_DAT2,
+	PINGRP_SDMMC4_DAT3,
+	PINGRP_SDMMC4_DAT4,
+	PINGRP_SDMMC4_DAT5,
+	PINGRP_SDMMC4_DAT6,
+	PINGRP_SDMMC4_DAT7,
+	PINGRP_SDMMC4_RST_N,
+	PINGRP_CAM_MCLK,
+	PINGRP_GPIO_PCC1,
+	PINGRP_GPIO_PBB0,
+	PINGRP_CAM_I2C_SCL,
+	PINGRP_CAM_I2C_SDA,
+	PINGRP_GPIO_PBB3,
+	PINGRP_GPIO_PBB4,
+	PINGRP_GPIO_PBB5,
+	PINGRP_GPIO_PBB6,
+	PINGRP_GPIO_PBB7,
+	PINGRP_GPIO_PCC2,
+	PINGRP_JTAG_RTCK,
+	PINGRP_PWR_I2C_SCL,
+	PINGRP_PWR_I2C_SDA,
+	PINGRP_KB_ROW0,
+	PINGRP_KB_ROW1,
+	PINGRP_KB_ROW2,
+	PINGRP_KB_ROW3,
+	PINGRP_KB_ROW4,
+	PINGRP_KB_ROW5,
+	PINGRP_KB_ROW6,
+	PINGRP_KB_ROW7,
+	PINGRP_KB_ROW8,
+	PINGRP_KB_ROW9,
+	PINGRP_KB_ROW10,
+	PINGRP_KB_ROW11,
+	PINGRP_KB_ROW12,
+	PINGRP_KB_ROW13,
+	PINGRP_KB_ROW14,
+	PINGRP_KB_ROW15,
+	PINGRP_KB_COL0,
+	PINGRP_KB_COL1,
+	PINGRP_KB_COL2,
+	PINGRP_KB_COL3,
+	PINGRP_KB_COL4,
+	PINGRP_KB_COL5,
+	PINGRP_KB_COL6,
+	PINGRP_KB_COL7,
+	PINGRP_CLK_32K_OUT,
+	PINGRP_SYS_CLK_REQ,
+	PINGRP_CORE_PWR_REQ,
+	PINGRP_CPU_PWR_REQ,
+	PINGRP_PWR_INT_N,
+	PINGRP_CLK_32K_IN,
+	PINGRP_OWR,
+	PINGRP_DAP1_FS,
+	PINGRP_DAP1_DIN,
+	PINGRP_DAP1_DOUT,
+	PINGRP_DAP1_SCLK,
+	PINGRP_CLK1_REQ,
+	PINGRP_CLK1_OUT,
+	PINGRP_SPDIF_IN,
+	PINGRP_SPDIF_OUT,
+	PINGRP_DAP2_FS,
+	PINGRP_DAP2_DIN,
+	PINGRP_DAP2_DOUT,
+	PINGRP_DAP2_SCLK,
+	PINGRP_SPI2_MOSI,
+	PINGRP_SPI2_MISO,
+	PINGRP_SPI2_CS0_N,
+	PINGRP_SPI2_SCK,
+	PINGRP_SPI1_MOSI,
+	PINGRP_SPI1_SCK,
+	PINGRP_SPI1_CS0_N,
+	PINGRP_SPI1_MISO,
+	PINGRP_SPI2_CS1_N,
+	PINGRP_SPI2_CS2_N,
+	PINGRP_SDMMC3_CLK,
+	PINGRP_SDMMC3_CMD,
+	PINGRP_SDMMC3_DAT0,
+	PINGRP_SDMMC3_DAT1,
+	PINGRP_SDMMC3_DAT2,
+	PINGRP_SDMMC3_DAT3,
+	PINGRP_SDMMC3_DAT4,
+	PINGRP_SDMMC3_DAT5,
+	PINGRP_SDMMC3_DAT6,
+	PINGRP_SDMMC3_DAT7,
+	PINGRP_PEX_L0_PRSNT_N,
+	PINGRP_PEX_L0_RST_N,
+	PINGRP_PEX_L0_CLKREQ_N,
+	PINGRP_PEX_WAKE_N,
+	PINGRP_PEX_L1_PRSNT_N,
+	PINGRP_PEX_L1_RST_N,
+	PINGRP_PEX_L1_CLKREQ_N,
+	PINGRP_PEX_L2_PRSNT_N,
+	PINGRP_PEX_L2_RST_N,
+	PINGRP_PEX_L2_CLKREQ_N,
+	PINGRP_HDMI_CEC,	/* offset 0x33e0 */
+	PINGRP_COUNT,
+};
+
+enum pdrive_pingrp {
+	PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
+	PDRIVE_PINGROUP_AO2,
+	PDRIVE_PINGROUP_AT1,
+	PDRIVE_PINGROUP_AT2,
+	PDRIVE_PINGROUP_AT3,
+	PDRIVE_PINGROUP_AT4,
+	PDRIVE_PINGROUP_AT5,
+	PDRIVE_PINGROUP_CDEV1,
+	PDRIVE_PINGROUP_CDEV2,
+	PDRIVE_PINGROUP_CSUS,
+	PDRIVE_PINGROUP_DAP1,
+	PDRIVE_PINGROUP_DAP2,
+	PDRIVE_PINGROUP_DAP3,
+	PDRIVE_PINGROUP_DAP4,
+	PDRIVE_PINGROUP_DBG,
+	PDRIVE_PINGROUP_LCD1,
+	PDRIVE_PINGROUP_LCD2,
+	PDRIVE_PINGROUP_SDIO2,
+	PDRIVE_PINGROUP_SDIO3,
+	PDRIVE_PINGROUP_SPI,
+	PDRIVE_PINGROUP_UAA,
+	PDRIVE_PINGROUP_UAB,
+	PDRIVE_PINGROUP_UART2,
+	PDRIVE_PINGROUP_UART3,
+	PDRIVE_PINGROUP_VI1 = 24,	/* offset 0x8c8 */
+	PDRIVE_PINGROUP_SDIO1 = 33,	/* offset 0x8ec */
+	PDRIVE_PINGROUP_CRT = 36,	/* offset 0x8f8 */
+	PDRIVE_PINGROUP_DDC,
+	PDRIVE_PINGROUP_GMA,
+	PDRIVE_PINGROUP_GMB,
+	PDRIVE_PINGROUP_GMC,
+	PDRIVE_PINGROUP_GMD,
+	PDRIVE_PINGROUP_GME,
+	PDRIVE_PINGROUP_GMF,
+	PDRIVE_PINGROUP_GMG,
+	PDRIVE_PINGROUP_GMH,
+	PDRIVE_PINGROUP_OWR,
+	PDRIVE_PINGROUP_UAD,
+	PDRIVE_PINGROUP_GPV,
+	PDRIVE_PINGROUP_DEV3 = 49,	/* offset 0x92c */
+	PDRIVE_PINGROUP_CEC = 52,	/* offset 0x938 */
+	PDRIVE_PINGROUP_COUNT,
+};
+
+/*
+ * Functions which can be assigned to each of the pin groups. The values here
+ * bear no relation to the values programmed into pinmux registers and are
+ * purely a convenience. The translation is done through a table search.
+ */
+enum pmux_func {
+	PMUX_FUNC_AHB_CLK,
+	PMUX_FUNC_APB_CLK,
+	PMUX_FUNC_AUDIO_SYNC,
+	PMUX_FUNC_CRT,
+	PMUX_FUNC_DAP1,
+	PMUX_FUNC_DAP2,
+	PMUX_FUNC_DAP3,
+	PMUX_FUNC_DAP4,
+	PMUX_FUNC_DAP5,
+	PMUX_FUNC_DISPA,
+	PMUX_FUNC_DISPB,
+	PMUX_FUNC_EMC_TEST0_DLL,
+	PMUX_FUNC_EMC_TEST1_DLL,
+	PMUX_FUNC_GMI,
+	PMUX_FUNC_GMI_INT,
+	PMUX_FUNC_HDMI,
+	PMUX_FUNC_I2C1,
+	PMUX_FUNC_I2C2,
+	PMUX_FUNC_I2C3,
+	PMUX_FUNC_IDE,
+	PMUX_FUNC_KBC,
+	PMUX_FUNC_MIO,
+	PMUX_FUNC_MIPI_HS,
+	PMUX_FUNC_NAND,
+	PMUX_FUNC_OSC,
+	PMUX_FUNC_OWR,
+	PMUX_FUNC_PCIE,
+	PMUX_FUNC_PLLA_OUT,
+	PMUX_FUNC_PLLC_OUT1,
+	PMUX_FUNC_PLLM_OUT1,
+	PMUX_FUNC_PLLP_OUT2,
+	PMUX_FUNC_PLLP_OUT3,
+	PMUX_FUNC_PLLP_OUT4,
+	PMUX_FUNC_PWM,
+	PMUX_FUNC_PWR_INTR,
+	PMUX_FUNC_PWR_ON,
+	PMUX_FUNC_RTCK,
+	PMUX_FUNC_SDMMC1,
+	PMUX_FUNC_SDMMC2,
+	PMUX_FUNC_SDMMC3,
+	PMUX_FUNC_SDMMC4,
+	PMUX_FUNC_SFLASH,
+	PMUX_FUNC_SPDIF,
+	PMUX_FUNC_SPI1,
+	PMUX_FUNC_SPI2,
+	PMUX_FUNC_SPI2_ALT,
+	PMUX_FUNC_SPI3,
+	PMUX_FUNC_SPI4,
+	PMUX_FUNC_TRACE,
+	PMUX_FUNC_TWC,
+	PMUX_FUNC_UARTA,
+	PMUX_FUNC_UARTB,
+	PMUX_FUNC_UARTC,
+	PMUX_FUNC_UARTD,
+	PMUX_FUNC_UARTE,
+	PMUX_FUNC_ULPI,
+	PMUX_FUNC_VI,
+	PMUX_FUNC_VI_SENSOR_CLK,
+	PMUX_FUNC_XIO,
+	PMUX_FUNC_BLINK,
+	PMUX_FUNC_CEC,
+	PMUX_FUNC_CLK12,
+	PMUX_FUNC_DAP,
+	PMUX_FUNC_DAPSDMMC2,
+	PMUX_FUNC_DDR,
+	PMUX_FUNC_DEV3,
+	PMUX_FUNC_DTV,
+	PMUX_FUNC_VI_ALT1,
+	PMUX_FUNC_VI_ALT2,
+	PMUX_FUNC_VI_ALT3,
+	PMUX_FUNC_EMC_DLL,
+	PMUX_FUNC_EXTPERIPH1,
+	PMUX_FUNC_EXTPERIPH2,
+	PMUX_FUNC_EXTPERIPH3,
+	PMUX_FUNC_GMI_ALT,
+	PMUX_FUNC_HDA,
+	PMUX_FUNC_HSI,
+	PMUX_FUNC_I2C4,
+	PMUX_FUNC_I2C5,
+	PMUX_FUNC_I2CPWR,
+	PMUX_FUNC_I2S0,
+	PMUX_FUNC_I2S1,
+	PMUX_FUNC_I2S2,
+	PMUX_FUNC_I2S3,
+	PMUX_FUNC_I2S4,
+	PMUX_FUNC_NAND_ALT,
+	PMUX_FUNC_POPSDIO4,
+	PMUX_FUNC_POPSDMMC4,
+	PMUX_FUNC_PWM0,
+	PMUX_FUNC_PWM1,
+	PMUX_FUNC_PWM2,
+	PMUX_FUNC_PWM3,
+	PMUX_FUNC_SATA,
+	PMUX_FUNC_SPI5,
+	PMUX_FUNC_SPI6,
+	PMUX_FUNC_SYSCLK,
+	PMUX_FUNC_VGP1,
+	PMUX_FUNC_VGP2,
+	PMUX_FUNC_VGP3,
+	PMUX_FUNC_VGP4,
+	PMUX_FUNC_VGP5,
+	PMUX_FUNC_VGP6,
+	PMUX_FUNC_CLK_12M_OUT,
+	PMUX_FUNC_HDCP,
+	PMUX_FUNC_TEST,
+	PMUX_FUNC_CORE_PWR_REQ,
+	PMUX_FUNC_CPU_PWR_REQ,
+	PMUX_FUNC_PWR_INT_N,
+	PMUX_FUNC_CLK_32K_IN,
+	PMUX_FUNC_SAFE,
+
+	PMUX_FUNC_MAX,
+
+	PMUX_FUNC_RSVD1 = 0x8000,
+	PMUX_FUNC_RSVD2 = 0x8001,
+	PMUX_FUNC_RSVD3 = 0x8002,
+	PMUX_FUNC_RSVD4 = 0x8003,
+};
+
+/* return 1 if a pmux_func is in range */
+#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
+	|| (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
+
+/* return 1 if a pingrp is in range */
+#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
+
+/* The pullup/pulldown state of a pin group */
+enum pmux_pull {
+	PMUX_PULL_NORMAL = 0,
+	PMUX_PULL_DOWN,
+	PMUX_PULL_UP,
+};
+/* return 1 if a pin_pupd_is in range */
+#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
+				((pupd) <= PMUX_PULL_UP))
+
+/* Defines whether a pin group is tristated or in normal operation */
+enum pmux_tristate {
+	PMUX_TRI_NORMAL = 0,
+	PMUX_TRI_TRISTATE = 1,
+};
+/* return 1 if a pin_tristate_is in range */
+#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
+				&& ((tristate) <= PMUX_TRI_TRISTATE))
+
+enum pmux_pin_io {
+	PMUX_PIN_OUTPUT = 0,
+	PMUX_PIN_INPUT = 1,
+};
+/* return 1 if a pin_io_is in range */
+#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
+				((io) <= PMUX_PIN_INPUT))
+
+enum pmux_pin_lock {
+	PMUX_PIN_LOCK_DEFAULT = 0,
+	PMUX_PIN_LOCK_DISABLE,
+	PMUX_PIN_LOCK_ENABLE,
+};
+/* return 1 if a pin_lock is in range */
+#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
+				((lock) <= PMUX_PIN_LOCK_ENABLE))
+
+enum pmux_pin_od {
+	PMUX_PIN_OD_DEFAULT = 0,
+	PMUX_PIN_OD_DISABLE,
+	PMUX_PIN_OD_ENABLE,
+};
+/* return 1 if a pin_od is in range */
+#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
+				((od) <= PMUX_PIN_OD_ENABLE))
+
+enum pmux_pin_ioreset {
+	PMUX_PIN_IO_RESET_DEFAULT = 0,
+	PMUX_PIN_IO_RESET_DISABLE,
+	PMUX_PIN_IO_RESET_ENABLE,
+};
+/* return 1 if a pin_ioreset_is in range */
+#define pmux_pin_ioreset_isvalid(ioreset) \
+				(((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
+				((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+
+/* Available power domains used by pin groups */
+enum pmux_vddio {
+	PMUX_VDDIO_BB = 0,
+	PMUX_VDDIO_LCD,
+	PMUX_VDDIO_VI,
+	PMUX_VDDIO_UART,
+	PMUX_VDDIO_DDR,
+	PMUX_VDDIO_NAND,
+	PMUX_VDDIO_SYS,
+	PMUX_VDDIO_AUDIO,
+	PMUX_VDDIO_SD,
+	PMUX_VDDIO_CAM,
+	PMUX_VDDIO_GMI,
+	PMUX_VDDIO_PEXCTL,
+	PMUX_VDDIO_SDMMC1,
+	PMUX_VDDIO_SDMMC3,
+	PMUX_VDDIO_SDMMC4,
+
+	PMUX_VDDIO_NONE
+};
+
+/* t30 pin drive group and pin mux registers */
+#define PDRIVE_PINGROUP_OFFSET	(0x868 >> 2)
+#define PMUX_OFFSET	((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
+				PDRIVE_PINGROUP_COUNT)
+struct pmux_tri_ctlr {
+	uint pmt_reserved0;		/* ABP_MISC_PP_ reserved offset 00 */
+	uint pmt_reserved1;		/* ABP_MISC_PP_ reserved offset 04 */
+	uint pmt_strap_opt_a;		/* _STRAPPING_OPT_A_0, offset 08   */
+	uint pmt_reserved2;		/* ABP_MISC_PP_ reserved offset 0C */
+	uint pmt_reserved3;		/* ABP_MISC_PP_ reserved offset 10 */
+	uint pmt_reserved4[4];		/* _TRI_STATE_REG_A/B/C/D in t20 */
+	uint pmt_cfg_ctl;		/* _CONFIG_CTL_0, offset 24        */
+
+	uint pmt_reserved[528];		/* ABP_MISC_PP_ reserved offs 28-864 */
+
+	uint pmt_drive[PDRIVE_PINGROUP_COUNT];	/* pin drive grps offs 868 */
+	uint pmt_reserved5[PMUX_OFFSET];
+	uint pmt_ctl[PINGRP_COUNT];	/* mux/pupd/tri regs, offset 0x3000 */
+};
+
+/*
+ * This defines the configuration for a pin, including the function assigned,
+ * pull up/down settings and tristate settings. Having set up one of these
+ * you can call pinmux_config_pingroup() to configure a pin in one step. Also
+ * available is pinmux_config_table() to configure a list of pins.
+ */
+struct pingroup_config {
+	enum pmux_pingrp pingroup;	/* pin group PINGRP_...             */
+	enum pmux_func func;		/* function to assign FUNC_...      */
+	enum pmux_pull pull;		/* pull up/down/normal PMUX_PULL_...*/
+	enum pmux_tristate tristate;	/* tristate or normal PMUX_TRI_...  */
+	enum pmux_pin_io io;		/* input or output PMUX_PIN_...  */
+	enum pmux_pin_lock lock;	/* lock enable/disable PMUX_PIN...  */
+	enum pmux_pin_od od;		/* open-drain or push-pull driver  */
+	enum pmux_pin_ioreset ioreset;	/* input/output reset PMUX_PIN...  */
+};
+
+/* Set a pin group to tristate */
+void pinmux_tristate_enable(enum pmux_pingrp pin);
+
+/* Set a pin group to normal (non tristate) */
+void pinmux_tristate_disable(enum pmux_pingrp pin);
+
+/* Set the pull up/down feature for a pin group */
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
+
+/* Set the mux function for a pin group */
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
+
+/* Set the complete configuration for a pin group */
+void pinmux_config_pingroup(struct pingroup_config *config);
+
+/* Set a pin group to tristate or normal */
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
+
+/* Set a pin group as input or output */
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
+
+/**
+ * Configure a list of pin groups
+ *
+ * @param config	List of config items
+ * @param len		Number of config items in list
+ */
+void pinmux_config_table(struct pingroup_config *config, int len);
+
+/* Set a group of pins from a table */
+void pinmux_init(void);
+
+#endif	/* _TEGRA30_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/pmu.h b/arch/arm/include/asm/arch-tegra30/pmu.h
new file mode 100644
index 0000000..52bea29
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/pmu.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_PMU_H_
+#define _TEGRA30_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif	/* _TEGRA30_PMU_H_ */
diff --git a/board/eNET/eNET_start.S b/arch/arm/include/asm/arch-tegra30/spl.h
similarity index 70%
rename from board/eNET/eNET_start.S
rename to arch/arm/include/asm/arch-tegra30/spl.h
index 0dec7ea..5e453c5 100644
--- a/board/eNET/eNET_start.S
+++ b/arch/arm/include/asm/arch-tegra30/spl.h
@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
+ * (C) Copyright 2012
+ * NVIDIA Corporation <www.nvidia.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -20,11 +20,9 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
 
-#include "hardware.h"
+#define BOOT_DEVICE_RAM         1
 
-/* board early intialization */
-.globl early_board_init
-early_board_init:
-	/* No 32-bit board specific initialisation */
-	jmp	early_board_init_ret
+#endif
diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h
new file mode 100644
index 0000000..decf564
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/tegra.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_H_
+#define _TEGRA30_H_
+
+#define NV_PA_SDRAM_BASE	0x80000000	/* 0x80000000 for real T30 */
+
+#include <asm/arch-tegra/tegra.h>
+
+#define BCT_ODMDATA_OFFSET	6116	/* 12 bytes from end of BCT */
+
+#define MAX_NUM_CPU		4
+
+#endif	/* TEGRA30_H */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 78ca8e0..1918492 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -61,6 +61,12 @@
 
 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 
+#ifdef __ARM_ARCH_7A__
+#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
+#else
+#define wfi()
+#endif
+
 static inline unsigned int get_cr(void)
 {
 	unsigned int val;
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 1bd2730..f3b30c5 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -30,7 +30,6 @@
 #include <image.h>
 #include <u-boot/zlib.h>
 #include <asm/byteorder.h>
-#include <fdt.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <asm/bootm.h>
diff --git a/arch/mips/config.mk b/arch/mips/config.mk
index de9140b..aaa94e8 100644
--- a/arch/mips/config.mk
+++ b/arch/mips/config.mk
@@ -65,4 +65,5 @@
 PLATFORM_CPPFLAGS		+= -msoft-float
 PLATFORM_LDFLAGS		+= -G 0 -static -n -nostdlib $(ENDIANNESS)
 PLATFORM_RELFLAGS		+= -ffunction-sections -fdata-sections
-LDFLAGS_FINAL			+= --gc-sections
+LDFLAGS_FINAL			+= --gc-sections -pie
+OBJCFLAGS			+= --remove-section=.dynsym
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 51ce914..76abbaa 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -47,27 +47,16 @@
 	.set	pop
 	.endm
 
-	.macro	setup_c0_status_reset
-#ifdef CONFIG_64BIT
-	setup_c0_status ST0_KX 0
-#else
-	setup_c0_status 0 0
-#endif
-	.endm
-
-#define RVECENT(f,n) \
-   b f; nop
-#define XVECENT(f,bev) \
-   b f     ;           \
-   li k0,bev
-
 	.set noreorder
 
 	.globl _start
 	.text
 _start:
-	RVECENT(reset,0)			# U-boot entry point
-	RVECENT(reset,1)			# software reboot
+	/* U-boot entry point */
+	b	reset
+	 nop
+
+	.org 0x10
 #ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
 	/*
 	 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
@@ -77,141 +66,39 @@
 	 * device with correct parameters. This config option is board-specific.
 	 */
 	.word CONFIG_SYS_XWAY_EBU_BOOTCFG
-	.word 0x00000000
-#else
-	RVECENT(romReserved,2)
+	.word 0x0
 #endif
-	RVECENT(romReserved,3)
-	RVECENT(romReserved,4)
-	RVECENT(romReserved,5)
-	RVECENT(romReserved,6)
-	RVECENT(romReserved,7)
-	RVECENT(romReserved,8)
-	RVECENT(romReserved,9)
-	RVECENT(romReserved,10)
-	RVECENT(romReserved,11)
-	RVECENT(romReserved,12)
-	RVECENT(romReserved,13)
-	RVECENT(romReserved,14)
-	RVECENT(romReserved,15)
-	RVECENT(romReserved,16)
-	RVECENT(romReserved,17)
-	RVECENT(romReserved,18)
-	RVECENT(romReserved,19)
-	RVECENT(romReserved,20)
-	RVECENT(romReserved,21)
-	RVECENT(romReserved,22)
-	RVECENT(romReserved,23)
-	RVECENT(romReserved,24)
-	RVECENT(romReserved,25)
-	RVECENT(romReserved,26)
-	RVECENT(romReserved,27)
-	RVECENT(romReserved,28)
-	RVECENT(romReserved,29)
-	RVECENT(romReserved,30)
-	RVECENT(romReserved,31)
-	RVECENT(romReserved,32)
-	RVECENT(romReserved,33)
-	RVECENT(romReserved,34)
-	RVECENT(romReserved,35)
-	RVECENT(romReserved,36)
-	RVECENT(romReserved,37)
-	RVECENT(romReserved,38)
-	RVECENT(romReserved,39)
-	RVECENT(romReserved,40)
-	RVECENT(romReserved,41)
-	RVECENT(romReserved,42)
-	RVECENT(romReserved,43)
-	RVECENT(romReserved,44)
-	RVECENT(romReserved,45)
-	RVECENT(romReserved,46)
-	RVECENT(romReserved,47)
-	RVECENT(romReserved,48)
-	RVECENT(romReserved,49)
-	RVECENT(romReserved,50)
-	RVECENT(romReserved,51)
-	RVECENT(romReserved,52)
-	RVECENT(romReserved,53)
-	RVECENT(romReserved,54)
-	RVECENT(romReserved,55)
-	RVECENT(romReserved,56)
-	RVECENT(romReserved,57)
-	RVECENT(romReserved,58)
-	RVECENT(romReserved,59)
-	RVECENT(romReserved,60)
-	RVECENT(romReserved,61)
-	RVECENT(romReserved,62)
-	RVECENT(romReserved,63)
-	XVECENT(romExcHandle,0x200)	# bfc00200: R4000 tlbmiss vector
-	RVECENT(romReserved,65)
-	RVECENT(romReserved,66)
-	RVECENT(romReserved,67)
-	RVECENT(romReserved,68)
-	RVECENT(romReserved,69)
-	RVECENT(romReserved,70)
-	RVECENT(romReserved,71)
-	RVECENT(romReserved,72)
-	RVECENT(romReserved,73)
-	RVECENT(romReserved,74)
-	RVECENT(romReserved,75)
-	RVECENT(romReserved,76)
-	RVECENT(romReserved,77)
-	RVECENT(romReserved,78)
-	RVECENT(romReserved,79)
-	XVECENT(romExcHandle,0x280)	# bfc00280: R4000 xtlbmiss vector
-	RVECENT(romReserved,81)
-	RVECENT(romReserved,82)
-	RVECENT(romReserved,83)
-	RVECENT(romReserved,84)
-	RVECENT(romReserved,85)
-	RVECENT(romReserved,86)
-	RVECENT(romReserved,87)
-	RVECENT(romReserved,88)
-	RVECENT(romReserved,89)
-	RVECENT(romReserved,90)
-	RVECENT(romReserved,91)
-	RVECENT(romReserved,92)
-	RVECENT(romReserved,93)
-	RVECENT(romReserved,94)
-	RVECENT(romReserved,95)
-	XVECENT(romExcHandle,0x300)	# bfc00300: R4000 cache vector
-	RVECENT(romReserved,97)
-	RVECENT(romReserved,98)
-	RVECENT(romReserved,99)
-	RVECENT(romReserved,100)
-	RVECENT(romReserved,101)
-	RVECENT(romReserved,102)
-	RVECENT(romReserved,103)
-	RVECENT(romReserved,104)
-	RVECENT(romReserved,105)
-	RVECENT(romReserved,106)
-	RVECENT(romReserved,107)
-	RVECENT(romReserved,108)
-	RVECENT(romReserved,109)
-	RVECENT(romReserved,110)
-	RVECENT(romReserved,111)
-	XVECENT(romExcHandle,0x380)	# bfc00380: R4000 general vector
-	RVECENT(romReserved,113)
-	RVECENT(romReserved,114)
-	RVECENT(romReserved,115)
-	RVECENT(romReserved,116)
-	RVECENT(romReserved,116)
-	RVECENT(romReserved,118)
-	RVECENT(romReserved,119)
-	RVECENT(romReserved,120)
-	RVECENT(romReserved,121)
-	RVECENT(romReserved,122)
-	RVECENT(romReserved,123)
-	RVECENT(romReserved,124)
-	RVECENT(romReserved,125)
-	RVECENT(romReserved,126)
-	RVECENT(romReserved,127)
 
-	/*
-	 * We hope there are no more reserved vectors!
-	 * 128 * 8 == 1024 == 0x400
-	 * so this is address R_VEC+0x400 == 0xbfc00400
-	 */
+	.org 0x200
+	/* TLB refill, 32 bit task */
+1:	b	1b
+	 nop
+
+	.org 0x280
+	/* XTLB refill, 64 bit task */
+1:	b	1b
+	 nop
+
+	.org 0x300
+	/* Cache error exception */
+1:	b	1b
+	 nop
+
+	.org 0x380
+	/* General exception */
+1:	b	1b
+	 nop
+
+	.org 0x400
+	/* Catch interrupt exceptions */
+1:	b	1b
+	 nop
+
+	.org 0x480
+	/* EJTAG debug exception */
+1:	b	1b
+	 nop
+
 	.align 4
 reset:
 
@@ -222,7 +109,7 @@
 	/* WP(Watch Pending), SW0/1 should be cleared */
 	mtc0	zero, CP0_CAUSE
 
-	setup_c0_status_reset
+	setup_c0_status 0 0
 
 	/* Init Timer */
 	mtc0	zero, CP0_COUNT
@@ -286,7 +173,7 @@
 	sub	s1, s2, t0		# s1 <-- relocation offset
 
 	la	t3, in_ram
-	lw	t2, -12(t3)		# t2 <-- uboot_end_data
+	lw	t2, -12(t3)		# t2 <-- __image_copy_end
 	move	t1, a2
 
 	add	gp, s1			# adjust gp
@@ -314,9 +201,10 @@
 	jr	t0
 	 nop
 
+	.word	__rel_dyn_end
+	.word	__rel_dyn_start
+	.word	__image_copy_end
 	.word	_GLOBAL_OFFSET_TABLE_
-	.word	uboot_end_data
-	.word	uboot_end
 	.word	num_got_entries
 
 in_ram:
@@ -327,7 +215,7 @@
 	 * generated by GNU ld. Skip these reserved entries from relocation.
 	 */
 	lw	t3, -4(t0)		# t3 <-- num_got_entries
-	lw	t4, -16(t0)		# t4 <-- _GLOBAL_OFFSET_TABLE_
+	lw	t4, -8(t0)		# t4 <-- _GLOBAL_OFFSET_TABLE_
 	add	t4, s1			# t4 now holds relocated _G_O_T_
 	addi	t4, t4, 8		# skipping first two entries
 	li	t2, 2
@@ -341,17 +229,45 @@
 	blt	t2, t3, 1b
 	 addi	t4, 4
 
-	/* Clear BSS */
-	lw	t1, -12(t0)		# t1 <-- uboot_end_data
-	lw	t2, -8(t0)		# t2 <-- uboot_end
-	add	t1, s1			# adjust pointers
-	add	t2, s1
+	/* Update dynamic relocations */
+	lw	t1, -16(t0)		# t1 <-- __rel_dyn_start
+	lw	t2, -20(t0)		# t2 <-- __rel_dyn_end
 
-	sub	t1, 4
+	b	2f			# skip first reserved entry
+	 addi	t1, 8
+
 1:
-	addi	t1, 4
-	bltl	t1, t2, 1b
-	 sw	zero, 0(t1)
+	lw	t3, -4(t1)		# t3 <-- relocation info
+
+	sub	t3, 3
+	bnez	t3, 2f			# skip non R_MIPS_REL32 entries
+	 nop
+
+	lw	t3, -8(t1)		# t3 <-- location to fix up in FLASH
+
+	lw	t4, 0(t3)		# t4 <-- original pointer
+	add	t4, s1			# t4 <-- adjusted pointer
+
+	add	t3, s1			# t3 <-- location to fix up in RAM
+	sw	t4, 0(t3)
+
+2:
+	blt	t1, t2, 1b
+	 addi	t1, 8			# each rel.dyn entry is 8 bytes
+
+	/*
+	 * Clear BSS
+	 *
+	 * GOT is now relocated. Thus __bss_start and __bss_end can be
+	 * accessed directly via $gp.
+	 */
+	la	t1, __bss_start		# t1 <-- __bss_start
+	la	t2, __bss_end		# t2 <-- __bss_end
+
+1:
+	sw	zero, 0(t1)
+	blt	t1, t2, 1b
+	 addi	t1, 4
 
 	move	a0, s0			# a0 <-- gd
 	la	t9, board_init_r
@@ -359,12 +275,3 @@
 	 move	a1, s2
 
 	.end	relocate_code
-
-	/* Exception handlers */
-romReserved:
-	b	romReserved
-	 nop
-
-romExcHandle:
-	b	romExcHandle
-	 nop
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
index 1522594..dc7ce07 100644
--- a/arch/mips/cpu/mips64/start.S
+++ b/arch/mips/cpu/mips64/start.S
@@ -31,6 +31,14 @@
 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
 #endif
 
+#ifdef CONFIG_SYS_LITTLE_ENDIAN
+#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
+	(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
+#else
+#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
+	((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
+#endif
+
 	/*
 	 * For the moment disable interrupts, mark the kernel mode and
 	 * set ST0_KX so that the CPU does not spit fire when using
@@ -52,40 +60,40 @@
 	.globl _start
 	.text
 _start:
-	.org 0x000
+	/* U-boot entry point */
 	b	reset
 	 nop
-	.org 0x080
-	b	romReserved
-	 nop
-	.org 0x100
-	b	romReserved
-	 nop
-	.org 0x180
-	b	romReserved
-	 nop
+
 	.org 0x200
-	b	romReserved
+	/* TLB refill, 32 bit task */
+1:	b	1b
 	 nop
+
 	.org 0x280
-	b	romReserved
+	/* XTLB refill, 64 bit task */
+1:	b	1b
 	 nop
+
 	.org 0x300
-	b	romReserved
+	/* Cache error exception */
+1:	b	1b
 	 nop
+
 	.org 0x380
-	b	romReserved
+	/* General exception */
+1:	b	1b
+	 nop
+
+	.org 0x400
+	/* Catch interrupt exceptions */
+1:	b	1b
 	 nop
+
 	.org 0x480
-	b	romReserved
+	/* EJTAG debug exception */
+1:	b	1b
 	 nop
 
-	/*
-	 * We hope there are no more reserved vectors!
-	 * 128 * 8 == 1024 == 0x400
-	 * so this is address R_VEC+0x400 == 0xbfc00400
-	 */
-	.org 0x500
 	.align 4
 reset:
 
@@ -165,7 +173,7 @@
 	dsub	s1, s2, t0		# s1 <-- relocation offset
 
 	dla	t3, in_ram
-	ld	t2, -24(t3)		# t2 <-- uboot_end_data
+	ld	t2, -24(t3)		# t2 <-- __image_copy_end
 	move	t1, a2
 
 	dadd	gp, s1			# adjust gp
@@ -193,9 +201,10 @@
 	jr	t0
 	 nop
 
+	.dword	__rel_dyn_end
+	.dword	__rel_dyn_start
+	.dword	__image_copy_end
 	.dword	_GLOBAL_OFFSET_TABLE_
-	.dword	uboot_end_data
-	.dword	uboot_end
 	.dword	num_got_entries
 
 in_ram:
@@ -206,7 +215,7 @@
 	 * generated by GNU ld. Skip these reserved entries from relocation.
 	 */
 	ld	t3, -8(t0)		# t3 <-- num_got_entries
-	ld	t8, -32(t0)		# t8 <-- _GLOBAL_OFFSET_TABLE_
+	ld	t8, -16(t0)		# t8 <-- _GLOBAL_OFFSET_TABLE_
 	dadd	t8, s1			# t8 now holds relocated _G_O_T_
 	daddi	t8, t8, 16		# skipping first two entries
 	dli	t2, 2
@@ -220,17 +229,45 @@
 	blt	t2, t3, 1b
 	 daddi	t8, 8
 
+	/* Update dynamic relocations */
+	ld	t1, -32(t0)		# t1 <-- __rel_dyn_start
+	ld	t2, -40(t0)		# t2 <-- __rel_dyn_end
+
-	/* Clear BSS */
-	ld	t1, -24(t0)		# t1 <-- uboot_end_data
-	ld	t2, -16(t0)		# t2 <-- uboot_end
-	dadd	t1, s1			# adjust pointers
-	dadd	t2, s1
+	b	2f			# skip first reserved entry
+	 daddi	t1, 16
 
-	dsub	t1, 8
 1:
-	daddi	t1, 8
-	bltl	t1, t2, 1b
-	 sd	zero, 0(t1)
+	lw	t8, -4(t1)		# t8 <-- relocation info
+
+	dli	t3, MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
+	bne	t8, t3, 2f		# skip non R_MIPS_REL32 entries
+	 nop
+
+	ld	t3, -16(t1)		# t3 <-- location to fix up in FLASH
+
+	ld	t8, 0(t3)		# t8 <-- original pointer
+	dadd	t8, s1			# t8 <-- adjusted pointer
+
+	dadd	t3, s1			# t3 <-- location to fix up in RAM
+	sd	t8, 0(t3)
+
+2:
+	blt	t1, t2, 1b
+	 daddi	t1, 16			# each rel.dyn entry is 16 bytes
+
+	/*
+	 * Clear BSS
+	 *
+	 * GOT is now relocated. Thus __bss_start and __bss_end can be
+	 * accessed directly via $gp.
+	 */
+	dla	t1, __bss_start		# t1 <-- __bss_start
+	dla	t2, __bss_end		# t2 <-- __bss_end
+
+1:
+	sd	zero, 0(t1)
+	blt	t1, t2, 1b
+	 daddi	t1, 8
 
 	move	a0, s0			# a0 <-- gd
 	dla	t9, board_init_r
@@ -238,8 +275,3 @@
 	 move	a1, s2
 
 	.end	relocate_code
-
-	/* Exception handlers */
-romReserved:
-	b	romReserved
-	 nop
diff --git a/arch/mips/cpu/u-boot.lds b/arch/mips/cpu/u-boot.lds
index 37c9d23..10513ab 100644
--- a/arch/mips/cpu/u-boot.lds
+++ b/arch/mips/cpu/u-boot.lds
@@ -52,11 +52,11 @@
 	_gp = ALIGN(16) + 0x7ff0;
 
 	.got : {
-		__got_start = .;
 		*(.got)
-		__got_end = .;
 	}
 
+	num_got_entries = SIZEOF(.got) >> PTR_COUNT_SHIFT;
+
 	. = ALIGN(4);
 	.sdata : {
 		*(.sdata*)
@@ -67,18 +67,55 @@
 		#include <u-boot.lst>
 	}
 
-	uboot_end_data = .;
+	. = ALIGN(4);
+	__image_copy_end = .;
 
-	num_got_entries = (__got_end - __got_start) >> PTR_COUNT_SHIFT;
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel.dyn)
+		__rel_dyn_end = .;
+	}
 
-	. = ALIGN(4);
-	.sbss : {
-		*(.sbss*)
+	.deadcode : {
+		/*
+		 * Workaround for a binutils feature (or bug?).
+		 *
+		 * The GNU ld from binutils puts the dynamic relocation
+		 * entries into the .rel.dyn section. Sometimes it
+		 * allocates more dynamic relocation entries than it needs
+		 * and the unused slots are set to R_MIPS_NONE entries.
+		 *
+		 * However the size of the .rel.dyn section in the ELF
+		 * section header does not cover the unused entries, so
+		 * objcopy removes those during stripping.
+		 *
+		 * Create a small section here to avoid that.
+		 */
+		LONG(0xffffffff);
 	}
 
-	.bss : {
-		*(.bss*)
+	.dynsym : {
+		*(.dynsym)
+	}
+
+	.bss __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.sbss.*)
+		*(.bss.*)
+		*(COMMON)
 		. = ALIGN(4);
+		__bss_end = .;
+	}
+
+	/DISCARD/ : {
+		*(.dynbss)
+		*(.dynstr)
+		*(.dynamic)
+		*(.interp)
+		*(.hash)
+		*(.gnu.*)
+		*(.plt)
+		*(.got.plt)
+		*(.rel.plt)
 	}
-	uboot_end = .;
 }
diff --git a/arch/mips/cpu/xburst/jz4740.c b/arch/mips/cpu/xburst/jz4740.c
index c0b9817..b2d8f4d 100644
--- a/arch/mips/cpu/xburst/jz4740.c
+++ b/arch/mips/cpu/xburst/jz4740.c
@@ -201,10 +201,10 @@
 	pllout = __cpm_get_pllout();
 
 	gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
-	gd->sys_clk = pllout / div[__cpm_get_hdiv()];
-	gd->per_clk = pllout / div[__cpm_get_pdiv()];
+	gd->arch.sys_clk = pllout / div[__cpm_get_hdiv()];
+	gd->arch.per_clk = pllout / div[__cpm_get_pdiv()];
 	gd->mem_clk = pllout / div[__cpm_get_mdiv()];
-	gd->dev_clk = CONFIG_SYS_EXTAL;
+	gd->arch.dev_clk = CONFIG_SYS_EXTAL;
 }
 
 void rtc_init(void)
diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S
index 50b7fb1..d2c064b0 100644
--- a/arch/mips/cpu/xburst/start.S
+++ b/arch/mips/cpu/xburst/start.S
@@ -67,7 +67,7 @@
 	sub	t6, a2, t0		# t6 <-- relocation offset
 
 	la	t3, in_ram
-	lw	t2, -12(t3)		# t2 <-- uboot_end_data
+	lw	t2, -12(t3)		# t2 <-- __image_copy_end
 	move	t1, a2
 
 	add	gp, t6			# adjust gp
@@ -116,9 +116,10 @@
 	jr	t0
 	 nop
 
+	.word	__rel_dyn_end
+	.word	__rel_dyn_start
+	.word	__image_copy_end
 	.word	_GLOBAL_OFFSET_TABLE_
-	.word	uboot_end_data
-	.word	uboot_end
 	.word	num_got_entries
 
 in_ram:
@@ -129,7 +130,7 @@
 	 * generated by GNU ld. Skip these reserved entries from relocation.
 	 */
 	lw	t3, -4(t0)		# t3 <-- num_got_entries
-	lw	t4, -16(t0)		# t4 <-- _GLOBAL_OFFSET_TABLE_
+	lw	t4, -8(t0)		# t4 <-- _GLOBAL_OFFSET_TABLE_
 	add	t4, t6			# t4 now holds relocated _G_O_T_
 	addi	t4, t4, 8		# skipping first two entries
 	li	t2, 2
@@ -143,16 +144,45 @@
 	blt	t2, t3, 1b
 	 addi	t4, 4
 
-	/* Clear BSS */
-	lw	t1, -12(t0)		# t1 <-- uboot_end_data
-	lw	t2, -8(t0)		# t2 <-- uboot_end
-	add	t1, t6			# adjust pointers
-	add	t2, t6
+	/* Update dynamic relocations */
+	lw	t1, -16(t0)		# t1 <-- __rel_dyn_start
+	lw	t2, -20(t0)		# t2 <-- __rel_dyn_end
 
-	sub	t1, 4
-1:	addi	t1, 4
-	bltl	t1, t2, 1b
-	 sw	zero, 0(t1)
+	b	2f			# skip first reserved entry
+	 addi	t1, 8
+
+1:
+	lw	t3, -4(t1)		# t3 <-- relocation info
+
+	sub	t3, 3
+	bnez	t3, 2f			# skip non R_MIPS_REL32 entries
+	 nop
+
+	lw	t3, -8(t1)		# t3 <-- location to fix up in FLASH
+
+	lw	t4, 0(t3)		# t4 <-- original pointer
+	add	t4, t6			# t4 <-- adjusted pointer
+
+	add	t3, t6			# t3 <-- location to fix up in RAM
+	sw	t4, 0(t3)
+
+2:
+	blt	t1, t2, 1b
+	 addi	t1, 8			# each rel.dyn entry is 8 bytes
+
+	/*
+	 * Clear BSS
+	 *
+	 * GOT is now relocated. Thus __bss_start and __bss_end can be
+	 * accessed directly via $gp.
+	 */
+	la	t1, __bss_start		# t1 <-- __bss_start
+	la	t2, __bss_end		# t2 <-- __bss_end
+
+1:
+	sw	zero, 0(t1)
+	blt	t1, t2, 1b
+	 addi	t1, 4
 
 	move	a0, a1			# a0 <-- gd
 	la	t9, board_init_r
diff --git a/arch/mips/include/asm/config.h b/arch/mips/include/asm/config.h
index 02fbfb3..049c44e 100644
--- a/arch/mips/include/asm/config.h
+++ b/arch/mips/include/asm/config.h
@@ -21,6 +21,4 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
-#define CONFIG_NEEDS_MANUAL_RELOC
-
 #endif
diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
index b39737f..f912428 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -32,6 +32,9 @@
 	/* There are other clocks in the jz4740 */
 	unsigned long per_clk;	/* Peripheral bus clock */
 	unsigned long dev_clk;	/* Device clock */
+	unsigned long sys_clk;
+	unsigned long tbl;
+	unsigned long lastinc;
 #endif
 };
 
diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h
index 6f26dfa..a483166 100644
--- a/arch/mips/include/asm/u-boot-mips.h
+++ b/arch/mips/include/asm/u-boot-mips.h
@@ -5,7 +5,22 @@
  * Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, wd@denx.de
  */
 
-extern ulong uboot_end_data;
-extern ulong uboot_end;
+static inline unsigned long bss_start(void)
+{
+	extern ulong __bss_start;
+	return (unsigned long) &__bss_start;
+}
+
+static inline unsigned long bss_end(void)
+{
+	extern ulong __bss_end;
+	return (unsigned long) &__bss_end;
+}
+
+static inline unsigned long image_copy_end(void)
+{
+	extern ulong __image_copy_end;
+	return (unsigned long) &__image_copy_end;
+}
 
 extern int incaip_set_cpuclk(void);
diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
index d79e183..f19f198 100644
--- a/arch/mips/lib/board.c
+++ b/arch/mips/lib/board.c
@@ -143,7 +143,7 @@
 	gd_t gd_data, *id;
 	bd_t *bd;
 	init_fnc_t **init_fnc_ptr;
-	ulong addr, addr_sp, len = (ulong)&uboot_end - CONFIG_SYS_MONITOR_BASE;
+	ulong addr, addr_sp, len;
 	ulong *s;
 
 	/* Pointer is writable since we allocated a register for it.
@@ -176,6 +176,7 @@
 	/* Reserve memory for U-Boot code, data & bss
 	 * round down to next 16 kB limit
 	 */
+	len = bss_end() - CONFIG_SYS_MONITOR_BASE;
 	addr -= len;
 	addr &= ~(16 * 1024 - 1);
 
@@ -249,9 +250,6 @@
 #ifndef CONFIG_SYS_NO_FLASH
 	ulong size;
 #endif
-#ifndef CONFIG_ENV_IS_NOWHERE
-	extern char *env_name_spec;
-#endif
 	bd_t *bd;
 
 	gd = id;
@@ -261,29 +259,15 @@
 
 	gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE;
 
-	monitor_flash_len = (ulong)&uboot_end_data - dest_addr;
+	monitor_flash_len = image_copy_end() - dest_addr;
 
 	serial_initialize();
 
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
-	/*
-	 * We have to relocate the command table manually
-	 */
-	fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
-			ll_entry_count(cmd_tbl_t, cmd));
-#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
-
-	/* there are some other pointer constants we must deal with */
-#ifndef CONFIG_ENV_IS_NOWHERE
-	env_name_spec += gd->reloc_off;
-#endif
-
 	bd = gd->bd;
 
 	/* The Malloc area is immediately below the monitor copy in DRAM */
 	mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
 			TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN);
-	malloc_bin_reloc();
 
 #ifndef CONFIG_SYS_NO_FLASH
 	/* configure available FLASH banks */
diff --git a/arch/nios2/cpu/fdt.c b/arch/nios2/cpu/fdt.c
index b1ed9e1..f238665 100644
--- a/arch/nios2/cpu/fdt.c
+++ b/arch/nios2/cpu/fdt.c
@@ -30,7 +30,6 @@
 
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 #include <libfdt.h>
-#include <libfdt_env.h>
 #include <fdt_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/powerpc/cpu/mpc5xxx/cpu.c b/arch/powerpc/cpu/mpc5xxx/cpu.c
index 0c1eebd..dc021e3 100644
--- a/arch/powerpc/cpu/mpc5xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc5xxx/cpu.c
@@ -36,7 +36,6 @@
 
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
-#include <libfdt_env.h>
 #include <fdt_support.h>
 #endif
 
diff --git a/arch/powerpc/cpu/mpc8260/cpu.c b/arch/powerpc/cpu/mpc8260/cpu.c
index 220c1e2..f8bc5a9 100644
--- a/arch/powerpc/cpu/mpc8260/cpu.c
+++ b/arch/powerpc/cpu/mpc8260/cpu.c
@@ -50,7 +50,6 @@
 
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
-#include <libfdt_env.h>
 #include <fdt_support.h>
 #endif
 
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index d381cf9..24eb978 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -811,7 +811,7 @@
 #ifdef CONFIG_SYS_LBC_ADDR
 	off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
 	if (off > 0) {
-		const u32 *reg = fdt_getprop(fdt, off, "reg", NULL);
+		const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
 		if (reg) {
 			uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
 
diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c
index b3fcfe5..b6b733d 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu.c
@@ -45,7 +45,6 @@
 
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
-#include <libfdt_env.h>
 #include <fdt_support.h>
 #endif
 
diff --git a/arch/powerpc/cpu/ppc4xx/fdt.c b/arch/powerpc/cpu/ppc4xx/fdt.c
index 37f5817..3cdd531 100644
--- a/arch/powerpc/cpu/ppc4xx/fdt.c
+++ b/arch/powerpc/cpu/ppc4xx/fdt.c
@@ -29,7 +29,6 @@
 
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 #include <libfdt.h>
-#include <libfdt_env.h>
 #include <fdt_support.h>
 #include <asm/4xx_pcie.h>
 
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 7088293..0119a7b 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -36,10 +36,8 @@
 #include <asm/mp.h>
 
 #if defined(CONFIG_OF_LIBFDT)
-#include <fdt.h>
 #include <libfdt.h>
 #include <fdt_support.h>
-
 #endif
 
 #ifdef CONFIG_SYS_INIT_RAM_LOCK
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 57324b6..7b520f8 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -29,12 +29,12 @@
 LIB	= $(obj)lib$(CPU).o
 
 START-y	= start.o
-RESET_OBJS-$(CONFIG_X86_NO_RESET_VECTOR) += resetvec.o start16.o
+START-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
 COBJS	= interrupts.o cpu.o timer.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START-y) $(RESET_OBJS-))
+START	:= $(addprefix $(obj),$(START-y))
 
 all:	$(obj).depend $(START) $(LIB)
 
diff --git a/arch/x86/cpu/sc520/Makefile b/arch/x86/cpu/sc520/Makefile
deleted file mode 100644
index f462264..0000000
--- a/arch/x86/cpu/sc520/Makefile
+++ /dev/null
@@ -1,58 +0,0 @@
-#
-# (C) Copyright 2008
-# Graeme Russ, graeme.russ@gmail.com.
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2002
-# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)lib$(SOC).o
-
-COBJS-$(CONFIG_SYS_SC520) += sc520.o
-COBJS-$(CONFIG_PCI) += sc520_pci.o
-COBJS-$(CONFIG_SYS_SC520_RESET) += sc520_reset.o
-COBJS-$(CONFIG_SYS_SC520) += sc520_sdram.o
-COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o
-COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o
-
-SOBJS-$(CONFIG_SYS_SC520) += sc520_car.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-all: $(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
\ No newline at end of file
diff --git a/arch/x86/cpu/sc520/asm-offsets.c b/arch/x86/cpu/sc520/asm-offsets.c
deleted file mode 100644
index 794f00c..0000000
--- a/arch/x86/cpu/sc520/asm-offsets.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
- *
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- * We use the technique used in the OSF Mach kernel code:
- * generate asm statements containing #defines,
- * compile this file to assembler, and then extract the
- * #defines from the assembly-language output.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <common.h>
-#include <asm/arch/sc520.h>
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
-	DEFINE(GENERATED_GD_RELOC_OFF, offsetof(gd_t, reloc_off));
-
-	DEFINE(GENERATED_SC520_PAR0, offsetof(struct sc520_mmcr, par[0]));
-	DEFINE(GENERATED_SC520_PAR1, offsetof(struct sc520_mmcr, par[1]));
-	DEFINE(GENERATED_SC520_PAR2, offsetof(struct sc520_mmcr, par[2]));
-	DEFINE(GENERATED_SC520_PAR3, offsetof(struct sc520_mmcr, par[3]));
-	DEFINE(GENERATED_SC520_PAR4, offsetof(struct sc520_mmcr, par[4]));
-	DEFINE(GENERATED_SC520_PAR5, offsetof(struct sc520_mmcr, par[5]));
-	DEFINE(GENERATED_SC520_PAR6, offsetof(struct sc520_mmcr, par[6]));
-	DEFINE(GENERATED_SC520_PAR7, offsetof(struct sc520_mmcr, par[7]));
-	DEFINE(GENERATED_SC520_PAR8, offsetof(struct sc520_mmcr, par[8]));
-	DEFINE(GENERATED_SC520_PAR9, offsetof(struct sc520_mmcr, par[9]));
-	DEFINE(GENERATED_SC520_PAR10, offsetof(struct sc520_mmcr, par[10]));
-	DEFINE(GENERATED_SC520_PAR11, offsetof(struct sc520_mmcr, par[11]));
-	DEFINE(GENERATED_SC520_PAR12, offsetof(struct sc520_mmcr, par[12]));
-	DEFINE(GENERATED_SC520_PAR13, offsetof(struct sc520_mmcr, par[13]));
-	DEFINE(GENERATED_SC520_PAR14, offsetof(struct sc520_mmcr, par[14]));
-	DEFINE(GENERATED_SC520_PAR15, offsetof(struct sc520_mmcr, par[15]));
-
-	return 0;
-}
diff --git a/arch/x86/cpu/sc520/sc520.c b/arch/x86/cpu/sc520/sc520.c
deleted file mode 100644
index 3fe85e7..0000000
--- a/arch/x86/cpu/sc520/sc520.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2008-2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor-flags.h>
-#include <asm/arch/sc520.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;
-
-int cpu_init_f(void)
-{
-	if (CONFIG_SYS_SC520_HIGH_SPEED) {
-		/* set it to 133 MHz and write back */
-		writeb(0x02, &sc520_mmcr->cpuctl);
-		gd->cpu_clk = 133000000;
-	} else {
-		/* set it to 100 MHz and write back */
-		writeb(0x01, &sc520_mmcr->cpuctl);
-		gd->cpu_clk = 100000000;
-	}
-
-	/* wait at least one millisecond */
-	asm("movl	$0x2000, %%ecx\n"
-	    "0:		pushl %%ecx\n"
-	    "popl	%%ecx\n"
-	    "loop 0b\n" : : : "ecx");
-
-	return x86_cpu_init_f();
-}
-
-int cpu_init_r(void)
-{
-	/* Disable the PAR used for CAR */
-	writel(0x0000000, &sc520_mmcr->par[2]);
-
-	/* turn on the SDRAM write buffer */
-	writeb(0x11, &sc520_mmcr->dbctl);
-
-	return x86_cpu_init_r();
-}
diff --git a/arch/x86/cpu/sc520/sc520_car.S b/arch/x86/cpu/sc520/sc520_car.S
deleted file mode 100644
index c04cc1f..0000000
--- a/arch/x86/cpu/sc520/sc520_car.S
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * (C) Copyright 2010-2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/processor-flags.h>
-#include <asm/arch/sc520.h>
-#include <generated/asm-offsets.h>
-
-.section .text
-
-.globl car_init
-car_init:
-	/*
-	 * How to enable Cache-As-RAM for the AMD Elan SC520:
-	 *  1. Turn off the CPU Cache (may not be strictly required)
-	 *  2. Set code execution PAR (usually the BOOTCS region) to be
-	 *     non-cachable
-	 *  3. Create a Cachable PAR Region for an area of memory which is
-	 *       a) NOT where the code is being executed
-	 *       b) NOT SDRAM (Controller not initialised yet)
-	 *       c) WILL response to read requests
-	 *     The easiest way to do this is to create a second BOOTCS
-	 *     PAR mappnig with an address != the PAR in step 2
-	 *  4. Issue a wbinvd to invalidate the CPU cache
-	 *  5. Turn on the CPU Cache
-	 *  6. Read 16kB from the cached PAR region setup in step 3
-	 *  7. Turn off the CPU Cache (but DO NOT issue a wbinvd)
-	 *
-	 * The following code uses PAR2 as the cached PAR (PAR0 and PAR1
-	 * are avoided as these are the only two PARs which can be used
-	 * as PCI BUS Memory regions which the board might require)
-	 *
-	 * The configuration of PAR2 must be set in the board configuration
-	 * file as CONFIG_SYS_SC520_CAR_PAR
-	 */
-
-	/* Configure Cache-As-RAM PAR */
-	movl	$CONFIG_SYS_SC520_CAR_PAR, %eax
-	movl	$(SC520_MMCR_BASE + GENERATED_SC520_PAR2), %edi
-	movl	%eax, (%edi)
-
-	/* Trash the cache then turn it on */
-	wbinvd
-	movl	%cr0, %eax
-	andl	$~(X86_CR0_NW | X86_CR0_CD), %eax
-	movl	%eax, %cr0
-
-	/*
-	 * The cache is now enabled and empty. Map a region of memory to
-	 * it by reading that region.
-	 */
-	movl	$CONFIG_SYS_CAR_ADDR, %esi
-	movl	$CONFIG_SYS_CAR_SIZE, %ecx
-	shrl	$2, %ecx			/* we are reading longs */
-	cld
-	rep	lodsl
-
-	/* Turn off the cache, but don't trash it */
-	movl	%cr0, %eax
-	orl	$(X86_CR0_NW | X86_CR0_CD), %eax
-	movl	%eax, %cr0
-
-	/* Clear the CAR region */
-	xorl	%eax, %eax
-	movl	$CONFIG_SYS_CAR_ADDR, %edi
-	movl	$CONFIG_SYS_CAR_SIZE, %ecx
-	shrl	$2, %ecx			/* we are writing longs */
-	rep	stosl
-
-	/*
-	 * Done - We should now have CONFIG_SYS_CAR_SIZE bytes of
-	 * Cache-As-RAM
-	 */
-	jmp	car_init_ret
diff --git a/arch/x86/cpu/sc520/sc520_pci.c b/arch/x86/cpu/sc520/sc520_pci.c
deleted file mode 100644
index 52d07c1..0000000
--- a/arch/x86/cpu/sc520/sc520_pci.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * (C) Copyright 2008-2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-#include <asm/arch/pci.h>
-#include <asm/arch/sc520.h>
-
-static struct {
-	u8 priority;
-	u16 level_reg;
-	u8 level_bit;
-} sc520_irq[] = {
-	{ SC520_IRQ0,  0, 0x01 },
-	{ SC520_IRQ1,  0, 0x02 },
-	{ SC520_IRQ2,  1, 0x02 },
-	{ SC520_IRQ3,  0, 0x08 },
-	{ SC520_IRQ4,  0, 0x10 },
-	{ SC520_IRQ5,  0, 0x20 },
-	{ SC520_IRQ6,  0, 0x40 },
-	{ SC520_IRQ7,  0, 0x80 },
-
-	{ SC520_IRQ8,  1, 0x01 },
-	{ SC520_IRQ9,  1, 0x02 },
-	{ SC520_IRQ10, 1, 0x04 },
-	{ SC520_IRQ11, 1, 0x08 },
-	{ SC520_IRQ12, 1, 0x10 },
-	{ SC520_IRQ13, 1, 0x20 },
-	{ SC520_IRQ14, 1, 0x40 },
-	{ SC520_IRQ15, 1, 0x80 }
-};
-
-/* The interrupt used for PCI INTA-INTD  */
-int sc520_pci_ints[15] = {
-	-1, -1, -1, -1, -1, -1, -1, -1,
-		-1, -1, -1, -1, -1, -1, -1
-};
-
-/* utility function to configure a pci interrupt */
-int pci_sc520_set_irq(int pci_pin, int irq)
-{
-	int i;
-	u8 tmpb;
-	u16 tmpw;
-
-	debug("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
-
-	if (irq < 0 || irq > 15)
-		return -1; /* illegal irq */
-
-	if (pci_pin < 0 || pci_pin > 15)
-		return -1; /* illegal pci int pin */
-
-	/* first disable any non-pci interrupt source that use
-	 * this level */
-
-	/* PCI interrupt mapping (A through D)*/
-	for (i = 0; i <= 3 ; i++) {
-		tmpb = readb(&sc520_mmcr->pci_int_map[i]);
-
-		if (tmpb == sc520_irq[irq].priority)
-			writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]);
-	}
-
-	/* GP IRQ interrupt mapping */
-	for (i = 0; i <= 10 ; i++) {
-		tmpb = readb(&sc520_mmcr->gp_int_map[i]);
-
-		if (tmpb == sc520_irq[irq].priority)
-			writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]);
-	}
-
-	/* Set the trigger to level */
-	tmpb = readb(&sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
-	tmpb |= sc520_irq[irq].level_bit;
-	writeb(tmpb, &sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
-
-
-	if (pci_pin < 4) {
-		/* PCI INTA-INTD */
-		/* route the interrupt */
-		writeb(sc520_irq[irq].priority,
-				&sc520_mmcr->pci_int_map[pci_pin]);
-	} else {
-		/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
-		writeb(sc520_irq[irq].priority,
-				&sc520_mmcr->gp_int_map[pci_pin - 4]);
-
-		/* also set the polarity in this case */
-		tmpw = readw(&sc520_mmcr->intpinpol);
-		tmpw |= (1 << (pci_pin-4));
-		writew(tmpw, &sc520_mmcr->intpinpol);
-	}
-
-	/* register the pin */
-	sc520_pci_ints[pci_pin] = irq;
-
-
-	return 0; /* OK */
-}
-
-void pci_sc520_init(struct pci_controller *hose)
-{
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-	hose->region_count = pci_set_regions(hose);
-
-	pci_setup_type1(hose);
-
-	pci_register_hose(hose);
-
-	hose->last_busno = pci_hose_scan(hose);
-
-	/* enable target memory acceses on host brige */
-	pci_write_config_word(0, PCI_COMMAND,
-			      PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-}
diff --git a/arch/x86/cpu/sc520/sc520_sdram.c b/arch/x86/cpu/sc520/sc520_sdram.c
deleted file mode 100644
index 9dc1334..0000000
--- a/arch/x86/cpu/sc520/sc520_sdram.c
+++ /dev/null
@@ -1,479 +0,0 @@
-/*
- * (C) Copyright 2010,2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor-flags.h>
-#include <asm/arch/sc520.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct sc520_sdram_info {
-	u8 banks;
-	u8 columns;
-	u8 rows;
-	u8 size;
-};
-
-static void sc520_sizemem(void);
-static void sc520_set_dram_timing(void);
-static void sc520_set_dram_refresh_rate(void);
-static void sc520_enable_dram_refresh(void);
-static void sc520_enable_sdram(void);
-
-int dram_init_f(void)
-{
-	sc520_sizemem();
-	sc520_set_dram_timing();
-	sc520_set_dram_refresh_rate();
-	sc520_enable_dram_refresh();
-	sc520_enable_sdram();
-
-	return 0;
-}
-
-static inline void sc520_dummy_write(void)
-{
-	writew(0x0000, CACHELINESZ);
-}
-static inline void sc520_issue_sdram_op_mode_select(u8 command)
-{
-	writeb(command, &sc520_mmcr->drcctl);
-	sc520_dummy_write();
-}
-
-static inline int check_long(u32 test_long)
-{
-	u8 i;
-	u8 tmp_byte = (u8)(test_long & 0x000000ff);
-
-	for (i = 1; i < 4; i++) {
-		if ((u8)((test_long >> (i * 8)) & 0x000000ff) != tmp_byte)
-				return -1;
-	}
-
-	return 0;
-}
-
-static inline int write_and_test(u32 data, u32 address)
-{
-	writel(data, address);
-	if (readl(address) == data)
-		return 0; /* Good */
-	else
-		return -1; /* Bad */
-}
-
-static void sc520_enable_sdram(void)
-{
-	u32 par_config;
-
-	/* Enable Writes, Caching and Code Execution to SDRAM */
-	par_config = readl(&sc520_mmcr->par[3]);
-	par_config &= ~(SC520_PAR_EXEC_DIS |
-			SC520_PAR_CACHE_DIS |
-			SC520_PAR_WRITE_DIS);
-	writel(par_config, &sc520_mmcr->par[3]);
-
-	par_config = readl(&sc520_mmcr->par[4]);
-	par_config &= ~(SC520_PAR_EXEC_DIS |
-			SC520_PAR_CACHE_DIS |
-			SC520_PAR_WRITE_DIS);
-	writel(par_config, &sc520_mmcr->par[4]);
-}
-
-static void sc520_set_dram_timing(void)
-{
-	u8 drctmctl = 0x00;
-
-#if defined CONFIG_SYS_SDRAM_DRCTMCTL
-	/* just have your hardware designer _GIVE_ you what you need here! */
-	drctmctl = CONFIG_SYS_SDRAM_DRCTMCTL;
-#else
-	switch (CONFIG_SYS_SDRAM_RAS_CAS_DELAY) {
-	case 2:
-		break;
-	case 3:
-		drctmctl |= 0x01;
-		break;
-	case 4:
-	default:
-		drctmctl |= 0x02;
-		break;
-	}
-
-	switch (CONFIG_SYS_SDRAM_PRECHARGE_DELAY) {
-	case 2:
-		break;
-	case 3:
-		drctmctl |= 0x04;
-		break;
-	case 4:
-	default:
-		drctmctl |= 0x08;
-		break;
-
-	case 6:
-		drctmctl |= 0x0c;
-		break;
-	}
-
-	switch (CONFIG_SYS_SDRAM_CAS_LATENCY) {
-	case 2:
-		break;
-	case 3:
-	default:
-		drctmctl |= 0x10;
-		break;
-	}
-#endif
-	writeb(drctmctl, &sc520_mmcr->drctmctl);
-
-	/* Issue load mode register command */
-	sc520_issue_sdram_op_mode_select(0x03);
-}
-
-static void sc520_set_dram_refresh_rate(void)
-{
-	u8 drctl;
-
-	drctl = readb(&sc520_mmcr->drcctl);
-	drctl &= 0xcf;
-
-	switch (CONFIG_SYS_SDRAM_REFRESH_RATE) {
-	case 78:
-		break;
-	case 156:
-	default:
-		drctl |= 0x10;
-		break;
-	case 312:
-		drctl |= 0x20;
-		break;
-	case 624:
-		drctl |= 0x30;
-		break;
-	}
-
-	writeb(drctl, &sc520_mmcr->drcctl);
-}
-
-static void sc520_enable_dram_refresh(void)
-{
-	u8 drctl;
-
-	drctl = readb(&sc520_mmcr->drcctl);
-	drctl &= 0x30; /* keep refresh rate */
-	drctl |= 0x08; /* enable refresh, normal mode */
-
-	writeb(drctl, &sc520_mmcr->drcctl);
-}
-
-static void sc520_get_bank_info(int bank, struct sc520_sdram_info *bank_info)
-{
-	u32 col_data;
-	u32 row_data;
-
-	u32 drcbendadr;
-	u16 drccfg;
-
-	u8 banks = 0x00;
-	u8 columns = 0x00;
-	u8 rows = 0x00;
-
-	bank_info->banks = 0x00;
-	bank_info->columns = 0x00;
-	bank_info->rows = 0x00;
-	bank_info->size = 0x00;
-
-	if ((bank < 0) || (bank > 3)) {
-		printf("Bad Bank ID\n");
-		return;
-	}
-
-	/* Save configuration */
-	drcbendadr = readl(&sc520_mmcr->drcbendadr);
-	drccfg = readw(&sc520_mmcr->drccfg);
-
-	/* Setup SDRAM Bank to largest possible size */
-	writew(0x000b << (bank * 4), &sc520_mmcr->drccfg);
-
-	/* Set ending address for this bank */
-	writel(0x000000ff << (bank * 8), &sc520_mmcr->drcbendadr);
-
-	/* write col 11 wrap adr */
-	if (write_and_test(COL11_DATA, COL11_ADR) != 0)
-		goto restore_and_exit;
-
-	/* write col 10 wrap adr */
-	if (write_and_test(COL10_DATA, COL10_ADR) != 0)
-		goto restore_and_exit;
-
-	/* write col 9 wrap adr */
-	if (write_and_test(COL09_DATA, COL09_ADR) != 0)
-		goto restore_and_exit;
-
-	/* write col 8 wrap adr */
-	if (write_and_test(COL08_DATA, COL08_ADR) != 0)
-		goto restore_and_exit;
-
-	col_data = readl(COL11_ADR);
-
-	/* All four bytes in the read long must be the same */
-	if (check_long(col_data) < 0)
-		goto restore_and_exit;
-
-	if ((col_data >= COL08_DATA) && (col_data <= COL11_DATA))
-		columns = (u8)(col_data & 0x000000ff);
-	else
-		goto restore_and_exit;
-
-	/* write row 14 wrap adr */
-	if (write_and_test(ROW14_DATA, ROW14_ADR) != 0)
-		goto restore_and_exit;
-
-	/* write row 13 wrap adr */
-	if (write_and_test(ROW13_DATA, ROW13_ADR) != 0)
-		goto restore_and_exit;
-
-	/* write row 12 wrap adr */
-	if (write_and_test(ROW12_DATA, ROW12_ADR) != 0)
-		goto restore_and_exit;
-
-	/* write row 11 wrap adr */
-	if (write_and_test(ROW11_DATA, ROW11_ADR) != 0)
-		goto restore_and_exit;
-
-	if (write_and_test(ROW10_DATA, ROW10_ADR) != 0)
-		goto restore_and_exit;
-
-	/*
-	 * read data @ row 12 wrap adr to determine number of banks,
-	 * and read data @ row 14 wrap adr to determine number of rows.
-	 * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
-	 * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
-	 * if data @ row 12 wrap == 11 or 12, we have 4 banks,
-	 */
-	row_data = readl(ROW12_ADR);
-
-	/* All four bytes in the read long must be the same */
-	if (check_long(row_data) != 0)
-		goto restore_and_exit;
-
-	switch (row_data) {
-	case ROW10_DATA:
-		banks = 2;
-		break;
-
-	case ROW11_DATA:
-	case ROW12_DATA:
-		banks = 4;
-		break;
-
-	default:
-		goto restore_and_exit;
-	}
-
-	row_data = readl(ROW14_ADR);
-
-	/* All four bytes in the read long must be the same */
-	if (check_long(row_data) != 0)
-		goto restore_and_exit;
-
-	switch (row_data) {
-	case ROW11_DATA:
-	case ROW12_DATA:
-	case ROW13_DATA:
-	case ROW14_DATA:
-		rows = (u8)(row_data & 0x000000ff);
-		break;
-
-	default:
-		goto restore_and_exit;
-	}
-
-	bank_info->banks = banks;
-	bank_info->columns = columns;
-	bank_info->rows = rows;
-
-	if ((bank_info->banks != 0) &&
-	    (bank_info->columns != 0) &&
-	    (bank_info->rows != 0)) {
-		bank_info->size = bank_info->rows;
-		bank_info->size >>= (11 - bank_info->columns);
-		bank_info->size++;
-	}
-
-restore_and_exit:
-	/* Restore configuration */
-	writel(drcbendadr, &sc520_mmcr->drcbendadr);
-	writew(drccfg, &sc520_mmcr->drccfg);
-}
-
-static void sc520_setup_sizemem(void)
-{
-	u8 i;
-
-	/* Disable write buffer */
-	writeb(0x00, &sc520_mmcr->dbctl);
-
-	/* Disable ECC */
-	writeb(0x00, &sc520_mmcr->eccctl);
-
-	/* Set slowest SDRAM timing */
-	writeb(0x1e, &sc520_mmcr->drctmctl);
-
-	/* Issue a NOP to all SDRAM banks */
-	sc520_issue_sdram_op_mode_select(0x01);
-
-	/* Delay for 100 microseconds */
-	udelay(100);
-
-	/* Issue 'All Banks Precharge' command */
-	sc520_issue_sdram_op_mode_select(0x02);
-
-	/* Issue 2 'Auto Refresh Enable' command */
-	sc520_issue_sdram_op_mode_select(0x04);
-	sc520_dummy_write();
-
-	/* Issue 'Load Mode Register' command */
-	sc520_issue_sdram_op_mode_select(0x03);
-
-	/* Issue 8 more 'Auto Refresh Enable' commands */
-	sc520_issue_sdram_op_mode_select(0x04);
-	for (i = 0; i < 7; i++)
-		sc520_dummy_write();
-
-	/* Set control register to 'Normal Mode' */
-	writeb(0x00, &sc520_mmcr->drcctl);
-}
-
-static void sc520_sizemem(void)
-{
-	struct sc520_sdram_info sdram_info[4];
-	u8 bank_config = 0x00;
-	u8 end_addr = 0x00;
-	u16 drccfg = 0x0000;
-	u32 drcbendadr = 0x00000000;
-	u8 i;
-
-	/* Use PARs to disable caching of maximum allowable 256MB SDRAM */
-	writel(SC520_SDRAM1_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[3]);
-	writel(SC520_SDRAM2_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[4]);
-
-	sc520_setup_sizemem();
-
-	gd->ram_size = 0;
-
-	/* Size each SDRAM bank */
-	for (i = 0; i <= 3; i++) {
-		sc520_get_bank_info(i, &sdram_info[i]);
-
-		if (sdram_info[i].banks != 0) {
-			/* Update Configuration register */
-			bank_config = sdram_info[i].columns - 8;
-
-			if (sdram_info[i].banks == 4)
-				bank_config |= 0x08;
-
-			drccfg |= bank_config << (i * 4);
-
-			/* Update End Address register */
-			end_addr += sdram_info[i].size;
-			drcbendadr |= (end_addr | 0x80) << (i * 8);
-
-			gd->ram_size += sdram_info[i].size << 22;
-		}
-
-		/* Issue 'All Banks Precharge' command */
-		sc520_issue_sdram_op_mode_select(0x02);
-
-		/* Set control register to 'Normal Mode' */
-		writeb(0x00, &sc520_mmcr->drcctl);
-	}
-
-	writel(drcbendadr, &sc520_mmcr->drcbendadr);
-	writew(drccfg, &sc520_mmcr->drccfg);
-
-	/* Clear PARs preventing caching of SDRAM */
-	writel(0x00000000, &sc520_mmcr->par[3]);
-	writel(0x00000000, &sc520_mmcr->par[4]);
-}
-
-int dram_init(void)
-{
-	ulong dram_ctrl;
-	ulong dram_present = 0x00000000;
-
-	/*
-	 * We read-back the configuration of the dram
-	 * controller that the assembly code wrote
-	 */
-	dram_ctrl = readl(&sc520_mmcr->drcbendadr);
-
-	gd->bd->bi_dram[0].start = 0;
-	if (dram_ctrl & 0x80) {
-		/* bank 0 enabled */
-		gd->bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
-		dram_present = gd->bd->bi_dram[1].start;
-		gd->bd->bi_dram[0].size = gd->bd->bi_dram[1].start;
-	} else {
-		gd->bd->bi_dram[0].size = 0;
-		gd->bd->bi_dram[1].start = gd->bd->bi_dram[0].start;
-	}
-
-	if (dram_ctrl & 0x8000) {
-		/* bank 1 enabled */
-		gd->bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
-		dram_present = gd->bd->bi_dram[2].start;
-		gd->bd->bi_dram[1].size = gd->bd->bi_dram[2].start -
-				gd->bd->bi_dram[1].start;
-	} else {
-		gd->bd->bi_dram[1].size = 0;
-		gd->bd->bi_dram[2].start = gd->bd->bi_dram[1].start;
-	}
-
-	if (dram_ctrl & 0x800000) {
-		/* bank 2 enabled */
-		gd->bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
-		dram_present = gd->bd->bi_dram[3].start;
-		gd->bd->bi_dram[2].size = gd->bd->bi_dram[3].start -
-				gd->bd->bi_dram[2].start;
-	} else {
-		gd->bd->bi_dram[2].size = 0;
-		gd->bd->bi_dram[3].start = gd->bd->bi_dram[2].start;
-	}
-
-	if (dram_ctrl & 0x80000000) {
-		/* bank 3 enabled */
-		dram_present  = (dram_ctrl & 0x7f000000) >> 2;
-		gd->bd->bi_dram[3].size = dram_present -
-				gd->bd->bi_dram[3].start;
-	} else {
-		gd->bd->bi_dram[3].size = 0;
-	}
-
-	gd->ram_size = dram_present;
-
-	return 0;
-}
diff --git a/arch/x86/cpu/sc520/sc520_ssi.c b/arch/x86/cpu/sc520/sc520_ssi.c
deleted file mode 100644
index cc601e5..0000000
--- a/arch/x86/cpu/sc520/sc520_ssi.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/ssi.h>
-#include <asm/arch/sc520.h>
-
-int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
-{
-	u8 temp = 0;
-
-	if (freq >= 8192)
-		temp |= CTL_CLK_SEL_4;
-	else if (freq >= 4096)
-		temp |= CTL_CLK_SEL_8;
-	else if (freq >= 2048)
-		temp |= CTL_CLK_SEL_16;
-	else if (freq >= 1024)
-		temp |= CTL_CLK_SEL_32;
-	else if (freq >= 512)
-		temp |= CTL_CLK_SEL_64;
-	else if (freq >= 256)
-		temp |= CTL_CLK_SEL_128;
-	else if (freq >= 128)
-		temp |= CTL_CLK_SEL_256;
-	else
-		temp |= CTL_CLK_SEL_512;
-
-	if (!lsb_first)
-		temp |= MSBF_ENB;
-
-	if (inv_clock)
-		temp |= CLK_INV_ENB;
-
-	if (inv_phase)
-		temp |= PHS_INV_ENB;
-
-	writeb(temp, &sc520_mmcr->ssictl);
-
-	return 0;
-}
-
-u8 ssi_txrx_byte(u8 data)
-{
-	writeb(data, &sc520_mmcr->ssixmit);
-	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
-		;
-	writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd);
-	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
-		;
-
-	return readb(&sc520_mmcr->ssircv);
-}
-
-void ssi_tx_byte(u8 data)
-{
-	writeb(data, &sc520_mmcr->ssixmit);
-	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
-		;
-	writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd);
-}
-
-u8 ssi_rx_byte(void)
-{
-	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
-		;
-	writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd);
-	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
-		;
-
-	return readb(&sc520_mmcr->ssircv);
-}
diff --git a/arch/x86/cpu/sc520/sc520_timer.c b/arch/x86/cpu/sc520/sc520_timer.c
deleted file mode 100644
index 41f121f..0000000
--- a/arch/x86/cpu/sc520/sc520_timer.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * (C) Copyright 2008-2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/interrupt.h>
-#include <asm/arch/sc520.h>
-
-void sc520_timer_isr(void)
-{
-	/* Ack the GP Timer Interrupt */
-	writeb(0x02, &sc520_mmcr->gptmrsta);
-}
-
-int timer_init(void)
-{
-	/* Register the SC520 specific timer interrupt handler */
-	register_timer_isr(sc520_timer_isr);
-
-	/* Install interrupt handler for GP Timer 1 */
-	irq_install_handler (0, timer_isr, NULL);
-
-	/* Map GP Timer 1 to Master PIC IR0  */
-	writeb(0x01, &sc520_mmcr->gp_tmr_int_map[1]);
-
-	/* Disable GP Timers 1 & 2 - Allow configuration writes */
-	writew(0x4000, &sc520_mmcr->gptmr1ctl);
-	writew(0x4000, &sc520_mmcr->gptmr2ctl);
-
-	/* Reset GP Timers 1 & 2 */
-	writew(0x0000, &sc520_mmcr->gptmr1cnt);
-	writew(0x0000, &sc520_mmcr->gptmr2cnt);
-
-	/* Setup GP Timer 2 as a 100kHz (10us) prescaler */
-	writew(83, &sc520_mmcr->gptmr2maxcmpa);
-	writew(0xc001, &sc520_mmcr->gptmr2ctl);
-
-	/* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */
-	writew(100, &sc520_mmcr->gptmr1maxcmpa);
-	writew(0xe009, &sc520_mmcr->gptmr1ctl);
-
-	unmask_irq(0);
-
-	/* Clear the GP Timer 1 status register to get the show rolling*/
-	writeb(0x02, &sc520_mmcr->gptmrsta);
-
-	return 0;
-}
-
-/* Allow boards to override udelay implementation */
-void __udelay(unsigned long usec)
-	__attribute__((weak, alias("sc520_udelay")));
-
-void sc520_udelay(unsigned long usec)
-{
-	int m = 0;
-	long u;
-
-	readw(&sc520_mmcr->swtmrmilli);
-	readw(&sc520_mmcr->swtmrmicro);
-
-	do {
-		m += readw(&sc520_mmcr->swtmrmilli);
-		u = readw(&sc520_mmcr->swtmrmicro) + (m * 1000);
-	} while (u < usec);
-}
diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds
index 0c6f0e3..2313cd7 100644
--- a/arch/x86/cpu/u-boot.lds
+++ b/arch/x86/cpu/u-boot.lds
@@ -86,7 +86,7 @@
 	__bios_start = LOADADDR(.bios);
 	__bios_size = SIZEOF(.bios);
 
-#ifndef CONFIG_X86_NO_RESET_VECTOR
+#ifdef CONFIG_X86_RESET_VECTOR
 
 	/*
 	 * The following expressions place the 16-bit Real-Mode code and
diff --git a/arch/x86/include/asm/arch-coreboot/sysinfo.h b/arch/x86/include/asm/arch-coreboot/sysinfo.h
index 77ae304..78d3a9d 100644
--- a/arch/x86/include/asm/arch-coreboot/sysinfo.h
+++ b/arch/x86/include/asm/arch-coreboot/sysinfo.h
@@ -32,7 +32,7 @@
 
 #include <common.h>
 #include <compiler.h>
-#include <fdt.h>
+#include <libfdt.h>
 #include <asm/arch/tables.h>
 
 /* Allow a maximum of 16 memory range definitions. */
diff --git a/arch/x86/include/asm/arch-sc520/pci.h b/arch/x86/include/asm/arch-sc520/pci.h
deleted file mode 100644
index 12ba656..0000000
--- a/arch/x86/include/asm/arch-sc520/pci.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ASM_IC_SC520_PCI_H_
-#define _ASM_IC_SC520_PCI_H_ 1
-
-/* bus mapping constants (used for PCI core initialization) */																																																 /* bus mapping constants */
-#define SC520_REG_ADDR		0x00000cf8
-#define SC520_REG_DATA		0x00000cfc
-
-#define SC520_ISA_MEM_PHYS	0x00000000
-#define SC520_ISA_MEM_BUS	0x00000000
-#define SC520_ISA_MEM_SIZE	0x01000000
-
-#define SC520_ISA_IO_PHYS	0x00000000
-#define SC520_ISA_IO_BUS	0x00000000
-#define SC520_ISA_IO_SIZE	0x00001000
-
-/* PCI I/O space from 0x1000 to 0xdfff
- * (make 0xe000-0xfdff available for stuff like PCCard boot) */
-#define SC520_PCI_IO_PHYS	0x00001000
-#define SC520_PCI_IO_BUS	0x00001000
-#define SC520_PCI_IO_SIZE	0x0000d000
-
-/* system memory from 0x00000000 to 0x0fffffff */
-#define	SC520_PCI_MEMORY_PHYS	0x00000000
-#define	SC520_PCI_MEMORY_BUS	0x00000000
-#define SC520_PCI_MEMORY_SIZE	0x10000000
-
-/* PCI bus memory from 0x10000000 to 0x26ffffff
- * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */
-#define SC520_PCI_MEM_PHYS	0x10000000
-#define SC520_PCI_MEM_BUS	0x10000000
-#define SC520_PCI_MEM_SIZE	0x17000000
-
-/* pin number used for PCI interrupt mappings */
-#define SC520_PCI_INTA 0
-#define SC520_PCI_INTB 1
-#define SC520_PCI_INTC 2
-#define SC520_PCI_INTD 3
-#define SC520_PCI_GPIRQ0 4
-#define SC520_PCI_GPIRQ1 5
-#define SC520_PCI_GPIRQ2 6
-#define SC520_PCI_GPIRQ3 7
-#define SC520_PCI_GPIRQ4 8
-#define SC520_PCI_GPIRQ5 9
-#define SC520_PCI_GPIRQ6 10
-#define SC520_PCI_GPIRQ7 11
-#define SC520_PCI_GPIRQ8 12
-#define SC520_PCI_GPIRQ9 13
-#define SC520_PCI_GPIRQ10 14
-
-extern int sc520_pci_ints[];
-
-void pci_sc520_init(struct pci_controller *hose);
-int pci_set_regions(struct pci_controller *hose);
-int pci_sc520_set_irq(int pci_pin, int irq);
-
-#endif
diff --git a/arch/x86/include/asm/arch-sc520/sc520.h b/arch/x86/include/asm/arch-sc520/sc520.h
deleted file mode 100644
index 9dc29d3..0000000
--- a/arch/x86/include/asm/arch-sc520/sc520.h
+++ /dev/null
@@ -1,372 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ASM_IC_SC520_H_
-#define _ASM_IC_SC520_H_ 1
-
-#ifndef __ASSEMBLY__
-
-void init_sc520(void);
-unsigned long init_sc520_dram(void);
-void sc520_udelay(unsigned long usec);
-
-/* Memory mapped configuration registers */
-typedef struct sc520_mmcr {
-	u16 revid;	/* ElanSC520 microcontroller revision id */
-	u8  cpuctl;	/* am5x86 CPU control  */
-
-	u8  pad_0x003[0x0d];
-
-	u8  drcctl;		/* SDRAM control */
-	u8  pad_0x011[0x01];
-	u8  drctmctl;		/* SDRAM timing control */
-	u8  pad_0x013[0x01];
-	u16 drccfg;		/* SDRAM bank configuration*/
-	u8  pad_0x016[0x02];
-	u32 drcbendadr;		/* SDRAM bank 0-3 ending address*/
-	u8  pad_0x01c[0x04];
-	u8  eccctl;		/* ECC control */
-	u8  eccsta;		/* ECC status */
-	u8  eccckbpos;		/* ECC check bit position */
-	u8  ecccktest;		/* ECC Check Code Test */
-	u32 eccsbadd;		/* ECC single-bit error address */
-	u32 eccmbadd;		/* ECC multi-bit error address */
-
-	u8  pad_0x02c[0x14];
-
-	u8  dbctl;		/* SDRAM buffer control */
-
-	u8  pad_0x041[0x0f];
-
-	u16 bootcsctl;		/* /BOOTCS control */
-	u8  pad_0x052[0x02];
-	u16 romcs1ctl;		/* /ROMCS1 control */
-	u16 romcs2ctl;		/* /ROMCS2 control */
-
-	u8  pad_0x058[0x08];
-
-	u16 hbctl;		/* host bridge control */
-	u16 hbtgtirqctl;	/* host bridge target interrupt control */
-	u16 hbtgtirqsta;	/* host bridge target interrupt status */
-	u16 hbmstirqctl;	/* host bridge target interrupt control */
-	u16 hbmstirqsta;	/* host bridge master interrupt status */
-	u8  pad_0x06a[0x02];
-	u32 mstintadd;		/* host bridge master interrupt address */
-
-	u8  sysarbctl;		/* system arbiter control */
-	u8  pciarbsta;		/* PCI bus arbiter status */
-	u16 sysarbmenb;		/* system arbiter master enable */
-	u32 arbprictl;		/* arbiter priority control */
-
-	u8  pad_0x078[0x08];
-
-	u8  adddecctl;		/* address decode control */
-	u8  pad_0x081[0x01];
-	u16 wpvsta;		/* write-protect violation status */
-	u8  pad_0x084[0x04];
-	u32 par[16];		/* programmable address regions */
-
-	u8  pad_0x0c8[0x0b38];
-
-	u8  gpecho;		/* GP echo mode */
-	u8  gpcsdw;		/* GP chip select data width */
-	u16 gpcsqual;		/* GP chip select qualification */
-	u8  pad_0xc04[0x4];
-	u8  gpcsrt;		/* GP chip select recovery time */
-	u8  gpcspw;		/* GP chip select pulse width */
-	u8  gpcsoff;		/* GP chip select offset */
-	u8  gprdw;		/* GP read pulse width */
-	u8  gprdoff;		/* GP read offset */
-	u8  gpwrw;		/* GP write pulse width */
-	u8  gpwroff;		/* GP write offset */
-	u8  gpalew;		/* GP ale pulse width */
-	u8  gpaleoff;		/* GP ale offset */
-
-	u8  pad_0xc11[0x0f];
-
-	u16 piopfs15_0;		/* PIO15-PIO0 pin function select */
-	u16 piopfs31_16;	/* PIO31-PIO16 pin function select */
-	u8  cspfs;		/* chip select pin function select */
-	u8  pad_0xc25[0x01];
-	u8  clksel;		/* clock select */
-	u8  pad_0xc27[0x01];
-	u16 dsctl;		/* drive strength control */
-	u16 piodir15_0;		/* PIO15-PIO0 direction */
-	u16 piodir31_16;	/* PIO31-PIO16 direction */
-	u8  pad_0xc2e[0x02];
-	u16 piodata15_0	;	/* PIO15-PIO0 data */
-	u16 piodata31_16;	/* PIO31-PIO16 data */
-	u16 pioset15_0;		/* PIO15-PIO0 set */
-	u16 pioset31_16;	/* PIO31-PIO16 set */
-	u16 pioclr15_0;		/* PIO15-PIO0 clear */
-	u16 pioclr31_16;	/* PIO31-PIO16 clear */
-
-	u8  pad_0xc3c[0x24];
-
-	u16 swtmrmilli;		/* software timer millisecond count */
-	u16 swtmrmicro;		/* software timer microsecond count */
-	u8  swtmrcfg;		/* software timer configuration */
-
-	u8  pad_0xc65[0x0b];
-
-	u8  gptmrsta;		/* GP timers status register */
-	u8  pad_0xc71;
-	u16 gptmr0ctl;		/* GP timer 0 mode/control */
-	u16 gptmr0cnt;		/* GP timer 0 count */
-	u16 gptmr0maxcmpa;	/* GP timer 0 maxcount compare A */
-	u16 gptmr0maxcmpb;	/* GP timer 0 maxcount compare B */
-	u16 gptmr1ctl;		/* GP timer 1 mode/control */
-	u16 gptmr1cnt;		/* GP timer 1 count */
-	u16 gptmr1maxcmpa;	/* GP timer 1 maxcount compare A */
-	u16 gptmr1maxcmpb;	/* GP timer 1 maxcount compare B*/
-	u16 gptmr2ctl;		/* GP timer 2 mode/control */
-	u16 gptmr2cnt;		/* GP timer 2 count */
-	u8  pad_0xc86[0x08];
-	u16 gptmr2maxcmpa;	/* GP timer 2 maxcount compare A */
-
-	u8  pad_0xc90[0x20];
-
-	u16 wdtmrctl;		/* watchdog timer control */
-	u16 wdtmrcntl;		/* watchdog timer count low */
-	u16 wdtmrcnth;		/* watchdog timer count high */
-
-	u8  pad_0xcb6[0x0a];
-
-	u8  uart1ctl;		/* UART 1 general control */
-	u8  uart1sta;		/* UART 1 general status */
-	u8  uart1fcrshad;	/* UART 1 FIFO control shadow */
-	u8  pad_0xcc3[0x01];
-	u8  uart2ctl;		/* UART 2 general control */
-	u8  uart2sta;		/* UART 2 general status */
-	u8  uart2fcrshad;	/* UART 2 FIFO control shadow */
-
-	u8  pad_0xcc7[0x09];
-
-	u8  ssictl;		/* SSI control */
-	u8  ssixmit;		/* SSI transmit */
-	u8  ssicmd;		/* SSI command */
-	u8  ssista;		/* SSI status */
-	u8  ssircv;		/* SSI receive */
-
-	u8  pad_0xcd5[0x2b];
-
-	u8  picicr;		/* interrupt control */
-	u8  pad_0xd01[0x01];
-	u8  pic_mode[3];	/* PIC interrupt mode */
-	u8  pad_0xd05[0x03];
-	u16 swint16_1;		/* software interrupt 16-1 control */
-	u8  swint22_17;		/* software interrupt 22-17/NMI control */
-	u8  pad_0xd0b[0x05];
-	u16 intpinpol;		/* interrupt pin polarity */
-	u8  pad_0xd12[0x02];
-	u16 pcihostmap;		/* PCI host bridge interrupt mapping */
-	u8  pad_0xd16[0x02];
-	u16 eccmap;		/* ECC interrupt mapping */
-	u8  gp_tmr_int_map[3];	/* GP timer interrupt mapping */
-	u8  pad_0xd1d[0x03];
-	u8  pit_int_map[3];	/* PIT interrupt mapping */
-	u8  pad_0xd23[0x05];
-	u8  uart_int_map[2];	/* UART interrupt mapping */
-	u8  pad_0xd2a[0x06];
-	u8  pci_int_map[4];	/* PCI interrupt mapping (A through D)*/
-	u8  pad_0xd34[0x0c];
-	u8  dmabcintmap;	/* DMA buffer chaining interrupt mapping */
-	u8  ssimap;		/* SSI interrupt mapping register */
-	u8  wdtmap;		/* watchdog timer interrupt mapping */
-	u8  rtcmap;		/* RTC interrupt mapping register */
-	u8  wpvmap;		/* write-protect interrupt mapping */
-	u8  icemap;		/* AMDebug JTAG Rx/Tx interrupt mapping */
-	u8  ferrmap;		/* floating point error interrupt mapping */
-	u8  pad_0xd47[0x09];
-	u8  gp_int_map[11];	/* GP IRQ interrupt mapping */
-
-	u8  pad_0xd5b[0x15];
-
-	u8  sysinfo;		/* system board information */
-	u8  pad_0xd71[0x01];
-	u8  rescfg;		/* reset configuration */
-	u8  pad_0xd73[0x01];
-	u8  ressta;		/* reset status */
-
-	u8  pad_0xd75[0x0b];
-
-	u8  gpdmactl;		/* GP-DMA Control */
-	u8  gpdmammio;		/* GP-DMA memory-mapped I/O */
-	u16 gpdmaextchmapa;	/* GP-DMA resource channel map a */
-	u16 gpdmaextchmapb;	/* GP-DMA resource channel map b */
-	u8  gp_dma_ext_pg_0;	/* GP-DMA channel extended page 0 */
-	u8  gp_dma_ext_pg_1;	/* GP-DMA channel extended page 0 */
-	u8  gp_dma_ext_pg_2;	/* GP-DMA channel extended page 0 */
-	u8  gp_dma_ext_pg_3;	/* GP-DMA channel extended page 0 */
-	u8  gp_dma_ext_pg_5;	/* GP-DMA channel extended page 0 */
-	u8  gp_dma_ext_pg_6;	/* GP-DMA channel extended page 0 */
-	u8  gp_dma_ext_pg_7;	/* GP-DMA channel extended page 0 */
-	u8  pad_0xd8d[0x03];
-	u8  gpdmaexttc3;	/* GP-DMA channel 3 extender transfer count */
-	u8  gpdmaexttc5;	/* GP-DMA channel 5 extender transfer count */
-	u8  gpdmaexttc6;	/* GP-DMA channel 6 extender transfer count */
-	u8  gpdmaexttc7;	/* GP-DMA channel 7 extender transfer count */
-	u8  pad_0xd94[0x4];
-	u8  gpdmabcctl;		/* buffer chaining control */
-	u8  gpdmabcsta;		/* buffer chaining status */
-	u8  gpdmabsintenb;	/* buffer chaining interrupt enable */
-	u8  gpdmabcval;		/* buffer chaining valid */
-	u8  pad_0xd9c[0x04];
-	u16 gpdmanxtaddl3;	/* GP-DMA channel 3 next address low */
-	u16 gpdmanxtaddh3;	/* GP-DMA channel 3 next address high */
-	u16 gpdmanxtaddl5;	/* GP-DMA channel 5 next address low */
-	u16 gpdmanxtaddh5;	/* GP-DMA channel 5 next address high */
-	u16 gpdmanxtaddl6;	/* GP-DMA channel 6 next address low */
-	u16 gpdmanxtaddh6;	/* GP-DMA channel 6 next address high */
-	u16 gpdmanxtaddl7;	/* GP-DMA channel 7 next address low */
-	u16 gpdmanxtaddh7;	/* GP-DMA channel 7 next address high */
-	u16 gpdmanxttcl3;	/* GP-DMA channel 3 next transfer count low */
-	u16 gpdmanxttch3;	/* GP-DMA channel 3 next transfer count high */
-	u16 gpdmanxttcl5;	/* GP-DMA channel 5 next transfer count low */
-	u16 gpdmanxttch5;	/* GP-DMA channel 5 next transfer count high */
-	u16 gpdmanxttcl6;	/* GP-DMA channel 6 next transfer count low */
-	u16 gpdmanxttch6;	/* GP-DMA channel 6 next transfer count high */
-	u16 gpdmanxttcl7;	/* GP-DMA channel 7 next transfer count low */
-	u16 gpdmanxttch7;	/* GP-DMA channel 7 next transfer count high */
-
-	u8  pad_0xdc0[0x0240];
-} sc520_mmcr_t;
-
-extern sc520_mmcr_t *sc520_mmcr;
-
-#endif
-
-/* Memory Mapped Control Registers (MMCR) Base Address */
-#define SC520_MMCR_BASE		0xfffef000
-
-/*
- * PARs for maximum allowable 256MB of SDRAM @ 0x00000000
- * Two PARs are required due to maximum PAR size of 128MB
- * These are used in the SDRAM sizing code to disable caching
- *
- * 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000
- * 111 0 0 0 1 11111111111 00100000000000 }- 0xe3ffc800
- * \ / | | | | \----+----/ \-----+------/
- *  |  | | | |      |            +---------- Start at 0x00000000
- *  |  | | | |      |                                 0x08000000
- *  |  | | | |      +----------------------- 128MB Region Size
- *  |  | | | |                               ((2047 + 1) * 64kB)
- *  |  | | | +------------------------------ 64kB Page Size
- *  |  | | +-------------------------------- Writes Enabled
- *  |  | +---------------------------------- Caching Enabled
- *  |  +------------------------------------ Execution Enabled
- *  +--------------------------------------- SDRAM
- */
-#define SC520_SDRAM1_PAR	0xe3ffc000
-#define SC520_SDRAM2_PAR	0xe3ffc800
-
-#define SC520_PAR_WRITE_DIS	0x04000000
-#define SC520_PAR_CACHE_DIS	0x08000000
-#define SC520_PAR_EXEC_DIS	0x10000000
-
-/*
- * Programmable Address Regions to cover 256MB SDRAM (Maximum supported)
- * required for DRAM sizing code
- */
-
-/* MMCR Register bits (not all of them :) ) */
-
-/* SSI Stuff */
-#define CTL_CLK_SEL_4		0x00	/* Nominal Bit Rate = 8 MHz    */
-#define CTL_CLK_SEL_8		0x10	/* Nominal Bit Rate = 4 MHz    */
-#define CTL_CLK_SEL_16		0x20	/* Nominal Bit Rate = 2 MHz    */
-#define CTL_CLK_SEL_32		0x30	/* Nominal Bit Rate = 1 MHz    */
-#define CTL_CLK_SEL_64		0x40	/* Nominal Bit Rate = 512 KHz  */
-#define CTL_CLK_SEL_128		0x50	/* Nominal Bit Rate = 256 KHz  */
-#define CTL_CLK_SEL_256		0x60	/* Nominal Bit Rate = 128 KHz  */
-#define CTL_CLK_SEL_512		0x70	/* Nominal Bit Rate = 64 KHz   */
-
-#define TC_INT_ENB		0x08	/* Transaction Complete Interrupt Enable */
-#define PHS_INV_ENB		0x04	/* SSI Inverted Phase Mode Enable */
-#define CLK_INV_ENB		0x02	/* SSI Inverted Clock Mode Enable */
-#define MSBF_ENB		0x01	/* SSI Most Significant Bit First Mode Enable */
-
-#define SSICMD_CMD_SEL_XMITRCV	0x03	/* Simultaneous Transmit / Receive Transaction */
-#define SSICMD_CMD_SEL_RCV	0x02	/* Receive Transaction */
-#define SSICMD_CMD_SEL_XMIT	0x01	/* Transmit Transaction */
-#define SSISTA_BSY		0x02	/* SSI Busy */
-#define SSISTA_TC_INT		0x01	/* SSI Transaction Complete Interrupt */
-
-/* BITS for SC520_ADDDECCTL: */
-#define WPV_INT_ENB		0x80	/* Write-Protect Violation Interrupt Enable */
-#define IO_HOLE_DEST_PCI	0x10	/* I/O Hole Access Destination */
-#define RTC_DIS			0x04	/* RTC Disable */
-#define UART2_DIS		0x02	/* UART2 Disable */
-#define UART1_DIS		0x01	/* UART1 Disable */
-
-/*
- * Defines used for SDRAM Sizing (number of columns and rows)
- * Refer to section 10.6.4 - SDRAM Sizing Algorithm in the
- * Elan SC520 Microcontroller User's Manual (Order #22004B)
- */
-#define CACHELINESZ		0x00000010
-
-#define COL11_ADR		0x0e001e00
-#define COL10_ADR		0x0e000e00
-#define COL09_ADR		0x0e000600
-#define COL08_ADR		0x0e000200
-#define COL11_DATA		0x0b0b0b0b
-#define COL10_DATA		0x0a0a0a0a
-#define COL09_DATA		0x09090909
-#define COL08_DATA		0x08080808
-
-#define ROW14_ADR		0x0f000000
-#define ROW13_ADR		0x07000000
-#define ROW12_ADR		0x03000000
-#define ROW11_ADR		0x01000000
-#define ROW10_ADR		0x00000000
-#define ROW14_DATA		0x3f3f3f3f
-#define ROW13_DATA		0x1f1f1f1f
-#define ROW12_DATA		0x0f0f0f0f
-#define ROW11_DATA		0x07070707
-#define ROW10_DATA		0xaaaaaaaa
-
-/* 0x28000000 - 0x3fffffff is used by the flash banks */
-
-/* 0x40000000 - 0xffffffff is not adressable by the SC520 */
-
-/* priority numbers used for interrupt channel mappings */
-#define SC520_IRQ_DISABLED 0
-#define SC520_IRQ0  1
-#define SC520_IRQ1  2
-#define SC520_IRQ2  4  /* same as IRQ9 */
-#define SC520_IRQ3  11
-#define SC520_IRQ4  12
-#define SC520_IRQ5  13
-#define SC520_IRQ6  21
-#define SC520_IRQ7  22
-#define SC520_IRQ8  3
-#define SC520_IRQ9  4
-#define SC520_IRQ10 5
-#define SC520_IRQ11 6
-#define SC520_IRQ12 7
-#define SC520_IRQ13 8
-#define SC520_IRQ14 9
-#define SC520_IRQ15 10
-
-#endif
diff --git a/arch/x86/include/asm/arch-sc520/ssi.h b/arch/x86/include/asm/arch-sc520/ssi.h
deleted file mode 100644
index bd48eab..0000000
--- a/arch/x86/include/asm/arch-sc520/ssi.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * (C) Copyright 2008
- * Graeme Russ <graeme.russ@gmail.com>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ASM_IC_SSI_H_
-#define _ASM_IC_SSI_H_ 1
-
-int ssi_set_interface(int, int, int, int);
-void ssi_chip_select(int);
-u8 ssi_txrx_byte(u8);
-void ssi_tx_byte(u8);
-u8 ssi_rx_byte(void);
-
-
-#endif
diff --git a/arch/x86/include/asm/realmode.h b/arch/x86/include/asm/realmode.h
deleted file mode 100644
index 0f12a89..0000000
--- a/arch/x86/include/asm/realmode.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_REALMODE_H_
-#define __ASM_REALMODE_H_
-#include <asm/ptrace.h>
-
-extern ulong __realmode_start;
-extern ulong __realmode_size;
-extern char realmode_enter;
-
-int bios_setup(void);
-int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out);
-int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out);
-
-#endif
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 0a52cc8..9b24dc5f 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -25,16 +25,6 @@
 
 LIB	= $(obj)lib$(ARCH).o
 
-ifeq ($(CONFIG_X86_NO_REAL_MODE),)
-SOBJS-$(CONFIG_SYS_PC_BIOS)	+= bios.o
-SOBJS-$(CONFIG_SYS_PCI_BIOS)	+= bios_pci.o
-COBJS-y	+= realmode.o
-SOBJS-y	+= realmode_switch.o
-
-COBJS-$(CONFIG_SYS_PC_BIOS)	+= bios_setup.o
-COBJS-$(CONFIG_VIDEO_VGA)	+= video_bios.o
-endif
-
 COBJS-y	+= board.o
 COBJS-y	+= bootm.o
 COBJS-y	+= cmd_boot.o
diff --git a/arch/x86/lib/bios.S b/arch/x86/lib/bios.S
deleted file mode 100644
index 239aaa9..0000000
--- a/arch/x86/lib/bios.S
+++ /dev/null
@@ -1,569 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Based on msbios.c from rolo 1.6:
- *----------------------------------------------------------------------
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions GmbH
- * Klein-Winternheim, Germany
- *----------------------------------------------------------------------
- */
-
-#include "bios.h"
-
-/*
- * During it's initialization phase, before switching to protected
- * mode, the Linux Kernel makes a few BIOS calls. This won't work
- * if the board does not have a BIOS.
- *
- * This is a very minimalisic BIOS that supplies just enough
- * functionality to keep the Linux Kernel happy. It is NOT
- * a general purpose replacement for a real BIOS !!
- */
-
-.section .bios, "ax"
-.code16
-.org 0
-	/* a call to f000:0 should warmboot */
-	jmp	realmode_reset
-
-.globl rm_int00
-.hidden rm_int00
-.type rm_int00, @function
-rm_int00:
-	pushw	$0
-	jmp	any_interrupt16
-.globl rm_int01
-.hidden rm_int01
-.type rm_int01, @function
-rm_int01:
-	pushw	$1
-	jmp	any_interrupt16
-.globl rm_int02
-.hidden rm_int02
-.type rm_int02, @function
-rm_int02:
-	pushw	$2
-	jmp	any_interrupt16
-.globl rm_int03
-.hidden rm_int03
-.type rm_int03, @function
-rm_int03:
-	pushw	$3
-	jmp	any_interrupt16
-.globl rm_int04
-.hidden rm_int04
-.type rm_int04, @function
-rm_int04:
-	pushw	$4
-	jmp	any_interrupt16
-.globl rm_int05
-.hidden rm_int05
-.type rm_int05, @function
-rm_int05:
-	pushw	$5
-	jmp	any_interrupt16
-.globl rm_int06
-.hidden rm_int06
-.type rm_int06, @function
-rm_int06:
-	pushw	$6
-	jmp	any_interrupt16
-.globl rm_int07
-.hidden rm_int07
-.type rm_int07, @function
-rm_int07:
-	pushw	$7
-	jmp	any_interrupt16
-.globl rm_int08
-.hidden rm_int08
-.type rm_int08, @function
-rm_int08:
-	pushw	$8
-	jmp	any_interrupt16
-.globl rm_int09
-.hidden rm_int09
-.type rm_int09, @function
-rm_int09:
-	pushw	$9
-	jmp	any_interrupt16
-.globl rm_int0a
-.hidden rm_int0a
-.type rm_int0a, @function
-rm_int0a:
-	pushw	$10
-	jmp	any_interrupt16
-.globl rm_int0b
-.hidden rm_int0b
-.type rm_int0b, @function
-rm_int0b:
-	pushw	$11
-	jmp	any_interrupt16
-.globl rm_int0c
-.hidden rm_int0c
-.type rm_int0c, @function
-rm_int0c:
-	pushw	$12
-	jmp	any_interrupt16
-.globl rm_int0d
-.hidden rm_int0d
-.type rm_int0d, @function
-rm_int0d:
-	pushw	$13
-	jmp	any_interrupt16
-.globl rm_int0e
-.hidden rm_int0e
-.type rm_int0e, @function
-rm_int0e:
-	pushw	$14
-	jmp	any_interrupt16
-.globl rm_int0f
-.hidden rm_int0f
-.type rm_int0f, @function
-rm_int0f:
-	pushw	$15
-	jmp	any_interrupt16
-.globl rm_int10
-.hidden rm_int10
-.type rm_int10, @function
-rm_int10:
-	pushw	$16
-	jmp	any_interrupt16
-.globl rm_int11
-.hidden rm_int11
-.type rm_int11, @function
-rm_int11:
-	pushw	$17
-	jmp	any_interrupt16
-.globl rm_int12
-.hidden rm_int12
-.type rm_int12, @function
-rm_int12:
-	pushw	$18
-	jmp	any_interrupt16
-.globl rm_int13
-.hidden rm_int13
-.type rm_int13, @function
-rm_int13:
-	pushw	$19
-	jmp	any_interrupt16
-.globl rm_int14
-.hidden rm_int14
-.type rm_int14, @function
-rm_int14:
-	pushw	$20
-	jmp	any_interrupt16
-.globl rm_int15
-.hidden rm_int15
-.type rm_int15, @function
-rm_int15:
-	pushw	$21
-	jmp	any_interrupt16
-.globl rm_int16
-.hidden rm_int16
-.type rm_int16, @function
-rm_int16:
-	pushw	$22
-	jmp	any_interrupt16
-.globl rm_int17
-.hidden rm_int17
-.type rm_int17, @function
-rm_int17:
-	pushw	$23
-	jmp	any_interrupt16
-.globl rm_int18
-.hidden rm_int18
-.type rm_int18, @function
-rm_int18:
-	pushw	$24
-	jmp	any_interrupt16
-.globl rm_int19
-.hidden rm_int19
-.type rm_int19, @function
-rm_int19:
-	pushw	$25
-	jmp	any_interrupt16
-.globl rm_int1a
-.hidden rm_int1a
-.type rm_int1a, @function
-rm_int1a:
-	pushw	$26
-	jmp	any_interrupt16
-.globl rm_int1b
-.hidden rm_int1b
-.type rm_int1b, @function
-rm_int1b:
-	pushw	$27
-	jmp	any_interrupt16
-.globl rm_int1c
-.hidden rm_int1c
-.type rm_int1c, @function
-rm_int1c:
-	pushw	$28
-	jmp	any_interrupt16
-.globl rm_int1d
-.hidden rm_int1d
-.type rm_int1d, @function
-rm_int1d:
-	pushw	$29
-	jmp	any_interrupt16
-.globl rm_int1e
-.hidden rm_int1e
-.type rm_int1e, @function
-rm_int1e:
-	pushw	$30
-	jmp	any_interrupt16
-.globl rm_int1f
-.hidden rm_int1f
-.type rm_int1f, @function
-rm_int1f:
-	pushw	$31
-	jmp	any_interrupt16
-.globl rm_def_int
-.hidden rm_def_int
-.type rm_def_int, @function
-rm_def_int:
-	iret
-
-	/*
-	 * All interrupt jumptable entries jump to here after pushing the
-	 * interrupt vector number onto the stack.
-	 */
-any_interrupt16:
-	MAKE_BIOS_STACK
-
-gs	movw	OFFS_VECTOR(%bp), %ax
-	cmpw	$0x10, %ax
-	je	Lint_10h
-	cmpw	$0x11, %ax
-	je	Lint_11h
-	cmpw	$0x12, %ax
-	je	Lint_12h
-	cmpw	$0x13, %ax
-	je	Lint_13h
-	cmpw	$0x15, %ax
-	je	Lint_15h
-	cmpw	$0x16, %ax
-	je	Lint_16h
-	cmpw	$0x1a, %ax
-	je	Lint_1ah
-	movw	$0xffff, %ax
-	jmp	Lout
-Lint_10h:
-	/* VGA BIOS services */
-	call	bios_10h
-	jmp	Lout
-Lint_11h:
-	call	bios_11h
-	jmp	Lout
-Lint_12h:
-	call	bios_12h
-	jmp	Lout
-Lint_13h:
-	/* BIOS disk services */
-	call	bios_13h
-	jmp	Lout
-Lint_15h:
-	/* Misc. BIOS services */
-	call	bios_15h
-	jmp	Lout
-Lint_16h:
-	/* keyboard services */
-	call	bios_16h
-	jmp	Lout
-Lint_1ah:
-	/* PCI bios */
-	call	bios_1ah
-	jmp	Lout
-Lout:
-	cmpw	$0, %ax
-	je	Lhandeled
-
-	/*
-	 * Insert code for unhandeled INTs here.
-	 *
-	 * ROLO prints a message to the console we could do that but then
-	 * we're in 16bit mode so we'll have to get back into 32bit mode
-	 * to use the console I/O routines (if we do this we should make
-	 * int 0x10 and int 0x16 work as well)
-	 */
-Lhandeled:
-	RESTORE_CALLERS_STACK
-
-	/* dump vector number */
-	addw	$2,%sp
-
-	/* return from interrupt */
-	iret
-
-/*
- ************************************************************
- * BIOS	interrupt 10h -- VGA services
- ************************************************************
- */
-bios_10h:
-gs	movw	OFFS_AX(%bp), %ax
-	shrw	$8, %ax
-	cmpw	$0x3, %ax
-	je	Lcur_pos
-	cmpw	$0xf, %ax
-	je	Lvid_state
-	cmpw	$0x12, %ax
-	je	Lvid_cfg
-	movw	$0xffff, %ax
-	ret
-Lcur_pos:
-	/* Read Cursor Position and Size */
-gs	movw	$0, OFFS_CX(%bp)
-gs	movw	$0, OFFS_DX(%bp)
-	xorw	%ax, %ax
-	ret
-Lvid_state:
-	/* Get Video State - 80 columns, 80x25, 16 colors */
-gs	movw	$(80 << 8|0x03), OFFS_AX(%bp)
-gs	movw	$0, OFFS_BX(%bp)
-	xorw	%ax, %ax
-	ret
-Lvid_cfg:
-	/* Video Subsystem Configuration (EGA/VGA) - indicate CGA/MDA/HGA */
-gs	movw	$0x10, OFFS_BX(%bp)
-	xorw	%ax, %ax
-	ret
-
-/*
- ************************************************************
- * BIOS interrupt 11h -- Equipment determination
- ************************************************************
- */
-
-bios_11h:
-cs	movw	bios_equipment, %ax
-gs	movw	%ax, OFFS_AX(%bp)
-	xorw	%ax, %ax
-	ret
-
-/*
- ************************************************************
- * BIOS	interrupt 12h -- Get Memory Size
- ************************************************************
- */
-bios_12h:
-cs	movw	ram_in_64kb_chunks, %ax
-	cmpw	$0xa, %ax
-	ja	b12_more_than_640k
-	shlw	$6, %ax
-	jmp	b12_return
-b12_more_than_640k:
-	movw	$0x280, %ax
-b12_return:
-	/* return number of kilobytes in ax */
-gs	movw	%ax, OFFS_AX(%bp)
-
-gs	movw	OFFS_FLAGS(%bp), %ax
-
-	/* clear carry -- function succeeded */
-	andw	$0xfffe, %ax
-gs	movw	%ax, OFFS_FLAGS(%bp)
-
-	xorw	%ax, %ax
-	ret
-
-/*
- ************************************************************
- * BIOS interrupt 13h -- Disk services
- ************************************************************
- */
-bios_13h:
-gs	movw	OFFS_AX(%bp), %ax
-	shrw	$8, %ax
-	cmpw	$0x15, %ax
-	je	Lfunc_15h
-	movw	$0xffff, %ax
-	ret
-Lfunc_15h:
-gs	movw	OFFS_AX(%bp), %ax
-
-	/* return AH=0->drive not present */
-	andw	$0x00ff, %ax
-gs	movw	%ax, OFFS_AX(%bp)
-	xorw	%ax, %ax
-	ret
-
-/*
- ***********************************************************
- * BIOS interrupt 15h -- Miscellaneous services
- ***********************************************************
- */
-bios_15h:
-gs	movw	OFFS_AX(%bp), %ax
-	shrw	$8, %ax
-	cmpw	$0xc0, %ax
-	je	Lfunc_c0h
-	cmpw	$0xe8, %ax
-	je	Lfunc_e8h
-	cmpw	$0x88, %ax
-	je	Lfunc_88h
-	movw	$0xffff, %ax
-	ret
-
-Lfunc_c0h:
-	/* Return System Configuration Parameters (PS2 only) */
-gs	movw	OFFS_FLAGS(%bp), %ax
-
-	/* return carry -- function not supported */
-	orw	$1, %ax
-gs	movw	%ax, OFFS_FLAGS(%bp)
-	xorw	%ax, %ax
-	ret
-
-Lfunc_e8h:
-gs	movw	OFFS_AX(%bp), %ax
-	andw	$0xff, %ax
-	cmpw	$1, %ax
-	je	Lfunc_e801h
-gs	movw	OFFS_FLAGS(%bp), %ax
-
-	/* return carry -- function not supported */
-	orw	$1, %ax
-gs	movw	%ax, OFFS_FLAGS(%bp)
-	xorw	%ax, %ax
-	ret
-
-Lfunc_e801h:
-	/* Get memory size for >64M Configurations */
-cs	movw	ram_in_64kb_chunks, %ax
-	cmpw	$0x100, %ax
-	ja	e801_more_than_16mb
-
-	/* multiply by 64 */
-	shlw	$6, %ax
-
-	/* 1st meg does not count */
-	subw	$0x400, %ax
-
-	/* return memory size between 1M and 16M in 1kb chunks in AX and CX */
-gs	movw	%ax, OFFS_AX(%bp)
-gs	movw	%ax, OFFS_CX(%bp)
-
-	/* set BX and DX to 0*/
-gs	movw	$0, OFFS_BX(%bp)
-gs	movw	$0, OFFS_DX(%bp)
-gs	movw	OFFS_FLAGS(%bp), %ax
-
-	/* clear carry -- function succeeded */
-	andw	$0xfffe, %ax
-gs	movw	%ax, OFFS_FLAGS(%bp)
-	xorw	%ax, %ax
-	ret
-
-e801_more_than_16mb:
-	/* subtract 16MB */
-	subw	$0x100, %ax
-
-	/* return 0x3c00 (16MB-1MB) in AX and CX */
-gs	movw	$0x3c00, OFFS_AX(%bp)
-gs	movw	$0x3c00, OFFS_CX(%bp)
-
-	/* set BX and DX to number of 64kb chunks above 16MB */
-gs	movw	%ax, OFFS_BX(%bp)
-gs	movw	%ax, OFFS_DX(%bp)
-
-gs	movw	OFFS_FLAGS(%bp), %ax
-
-	/* clear carry -- function succeeded */
-	andw	$0xfffe, %ax
-gs	movw	%ax, OFFS_FLAGS(%bp)
-	xorw	%ax, %ax
-	ret
-
-Lfunc_88h:
-cs	movw	ram_in_64kb_chunks, %ax
-	cmpw	$0x100, %ax
-	jna	b88_not_more_than16
-	movw	$0x100, %ax
-b88_not_more_than16:
-	shlw	$6, %ax
-
-	/* 1st meg does not count */
-	subw	$0x400, %ax
-
-	/* return number of kilobytes between 16MB and 16MB in ax */
-gs	movw	%ax, OFFS_AX(%bp)
-
-gs	movw	OFFS_FLAGS(%bp), %ax
-
-	/* clear carry -- function succeeded */
-	andw	$0xfffe, %ax
-gs	movw	%ax, OFFS_FLAGS(%bp)
-
-	xorw	%ax, %ax
-	ret
-
-/*
- ************************************************************
- * BIOS interrupt 16h -- keyboard services
- ************************************************************
- */
-bios_16h:
-gs	movw	OFFS_AX(%bp), %ax
-	shrw	$8, %ax
-	cmpw	$0x03, %ax
-	je	Lfunc_03h
-	movw	$0xffff, %ax
-	ret
-Lfunc_03h:
-	/* do nothing -- function not supported */
-	xorw	%ax, %ax
-	ret
-
-/*
- ************************************************************
- * BIOS interrupt 1ah -- PCI bios
- ************************************************************
- */
-bios_1ah:
-gs	movw	OFFS_AX(%bp), %ax
-	cmpb	$0xb1, %ah
-	je	Lfunc_b1h
-	movw	$0xffff, %ax
-	ret
-Lfunc_b1h:
-	call	realmode_pci_bios
-
-	/* do nothing -- function not supported */
-	xorw	%ax, %ax
-	ret
-
-
-.globl ram_in_64kb_chunks
-.hidden ram_in_64kb_chunks
-.type ram_in_64kb_chunks, @function
-ram_in_64kb_chunks:
-	.word	0
-
-.globl bios_equipment
-.hidden bios_equipment
-.type bios_equipment, @function
-bios_equipment:
-	.word	0
diff --git a/arch/x86/lib/bios.h b/arch/x86/lib/bios.h
index a220983..96509b0 100644
--- a/arch/x86/lib/bios.h
+++ b/arch/x86/lib/bios.h
@@ -145,9 +145,6 @@
 extern void *rm_int1f;
 extern void *rm_def_int;
 
-extern void *realmode_reset;
-extern void *realmode_pci_bios_call_entry;
-
 #define RELOC_16_LONG(seg, off) (*(u32 *)(seg << 4 | (u32)&off))
 #define RELOC_16_WORD(seg, off) (*(u16 *)(seg << 4 | (u32)&off))
 #define RELOC_16_BYTE(seg, off) (*(u8 *)(seg << 4 | (u32)&off))
diff --git a/arch/x86/lib/bios_pci.S b/arch/x86/lib/bios_pci.S
deleted file mode 100644
index 47c478b..0000000
--- a/arch/x86/lib/bios_pci.S
+++ /dev/null
@@ -1,447 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * x86 realmode assembly implementation of a PCI BIOS
- * for platforms that use one PCI hose and configuration
- * access type 1. (The common case for low-end PC's)
- */
-
-#include "bios.h"
-
-#define PCI_BIOS_DEBUG
-
-.section .bios, "ax"
-.code16
-.globl realmode_pci_bios_call_entry
-.hidden realmode_pci_bios_call_entry
-.type realmode_pci_bios_call_entry, @function
-realmode_pci_bios_call_entry:
-	MAKE_BIOS_STACK
-	call realmode_pci_bios
-	RESTORE_CALLERS_STACK
-	ret
-
-
-.globl realmode_pci_bios
-realmode_pci_bios:
-gs	movw	OFFS_AX(%bp), %ax
-	cmpb	$1, %al
-	je	pci_bios_present
-	cmpb	$2, %al
-	je	pci_bios_find_device
-	cmpb	$3, %al
-	je	pci_bios_find_class
-	cmpb	$6, %al
-	je	pci_bios_generate_special_cycle
-	cmpb	$8, %al
-	je	pci_bios_read_cfg_byte
-	cmpb	$9, %al
-	je	pci_bios_read_cfg_word
-	cmpb	$10, %al
-	je	pci_bios_read_cfg_dword
-	cmpb	$11, %al
-	je	pci_bios_write_cfg_byte
-	cmpb	$12, %al
-	je	pci_bios_write_cfg_word
-	cmpb	$13, %al
-	je	pci_bios_write_cfg_dword
-	cmpb	$14, %al
-	je	pci_bios_get_irq_routing
-	cmpb	$15, %al
-	je	pci_bios_set_irq
-	jmp	unknown_function
-
-/*****************************************************************************/
-
-pci_bios_present:
-#ifdef PCI_BIOS_DEBUG
-cs	incl	num_pci_bios_present
-#endif
-	movl	$0x20494350, %eax
-gs	movl	%eax, OFFS_EDX(%bp)
-
-	/* We support cfg type 1 version 2.10 */
-	movb	$0x01, %al
-gs	movb	%al, OFFS_AL(%bp)
-	movw	$0x0210, %ax
-gs	movw	%ax, OFFS_BX(%bp)
-
-	/* last bus number */
-cs	movb	pci_last_bus, %al
-gs	movb	%al, OFFS_CL(%bp)
-	jmp	clear_carry
-
-/*****************************************************************************/
-
-/* device 0-31, function 0-7 */
-pci_bios_find_device:
-#ifdef PCI_BIOS_DEBUG
-cs	incl	num_pci_bios_find_device
-#endif
-gs	movw	OFFS_CX(%bp), %di
-	shll	$16, %edi
-gs	movw	OFFS_DX(%bp), %di
-	/* edi now holds device in upper 16 bits and vendor in lower 16 bits */
-
-gs	movw	OFFS_SI(%bp), %si
-
-	/* start at bus 0 dev 0 function 0 */
-	xorw	%bx, %bx
-pfd_loop:
-	/* dword 0 is vendor/device */
-	xorw	%ax, %ax
-	call	__pci_bios_select_register
-	movw	$0xcfc, %dx
-	inl	%dx, %eax
-
-	/* our device ? */
-	cmpl	%edi, %eax
-	je	pfd_found_one
-pfd_next_dev:
-	/* check for multi function devices */
-	movw	%bx, %ax
-	andw	$3, %ax
-	jnz	pfd_function_not_zero
-	movw	$0x000c, %ax
-	call	__pci_bios_select_register
-	movw	$0xcfe, %dx
-	inb	%dx, %al
-	andb	$0x80, %al
-	jz	pfd_not_multi_function
-pfd_function_not_zero:
-	/* next function, overflows in to device number, then bus number */
-	incw	%bx
-	jmp	pfd_check_bus
-
-pfd_not_multi_function:
-	/* remove function bits */
-	andw	$0xfff8, %bx
-
-	/* next device, overflows in to bus number */
-	addw	$0x0008, %bx
-pfd_check_bus:
-cs	movb	pci_last_bus, %ah
-	cmpb	%ah, %bh
-	ja	pfd_not_found
-	jmp	pfd_loop
-pfd_found_one:
-	decw	%si
-	js	pfd_done
-	jmp	pfd_next_dev
-
-pfd_done:
-gs	movw	%bx, OFFS_BX(%bp)
-	jmp	clear_carry
-
-pfd_not_found:
-	/* device not found */
-	movb	$0x86, %ah
-	jmp	set_carry
-
-/*****************************************************************************/
-
-pci_bios_find_class:
-#ifdef PCI_BIOS_DEBUG
-cs	incl	num_pci_bios_find_class
-#endif
-gs	movl	OFFS_ECX(%bp), %edi
-
-	/* edi now holds class-code in lower 24 bits */
-	andl	$0x00ffffff, %edi
-gs	movw	OFFS_SI(%bp), %si
-
-	/* start at bus 0 dev 0 function 0 */
-	xorw	%bx, %bx
-pfc_loop:
-	/* dword 8 is class-code high 24bits */
-	movw	$8, %ax
-	call	__pci_bios_select_register
-	movw	$0xcfc, %dx
-	inl	%dx, %eax
-	shrl	$8, %eax
-	andl	$0x00ffffff, %eax
-
-	/* our device ? */
-	cmpl	%edi, %eax
-	je	pfc_found_one
-pfc_next_dev:
-	/* check for multi function devices */
-	andw	$3, %bx
-	jnz	pfc_function_not_zero
-	movw	$0x000c, %ax
-	call	__pci_bios_select_register
-	movw	$0xcfe, %dx
-	inb	%dx, %al
-	andb	$0x80, %al
-	jz	pfc_not_multi_function
-pfc_function_not_zero:
-	/* next function, overflows in to device number, then bus number */
-	incw	%bx
-	jmp	pfc_check_bus
-
-pfc_not_multi_function:
-	/* remove function bits */
-	andw	$0xfff8, %bx
-
-	/* next device, overflows in to bus number */
-	addw	$0x0008, %bx
-pfc_check_bus:
-cs	movb	pci_last_bus, %ah
-	cmpb	%ah, %bh
-	ja	pfc_not_found
-	jmp	pfc_loop
-pfc_found_one:
-	decw	%si
-	js	pfc_done
-	jmp	pfc_next_dev
-
-pfc_done:
-gs	movw	%bx, OFFS_BX(%bp)
-	jmp	clear_carry
-
-pfc_not_found:
-	/* device not found */
-	movb	$0x86, %ah
-	jmp	set_carry
-
-/*****************************************************************************/
-
-pci_bios_generate_special_cycle:
-#ifdef PCI_BIOS_DEBUG
-cs	incl	num_pci_bios_generate_special_cycle
-#endif
-	/* function not supported */
-	movb	$0x81, %ah
-	jmp	set_carry
-
-/*****************************************************************************/
-
-pci_bios_read_cfg_byte:
-#ifdef PCI_BIOS_DEBUG
-cs	incl	num_pci_bios_read_cfg_byte
-#endif
-	call	pci_bios_select_register
-gs	movw	OFFS_DI(%bp), %dx
-	andw	$3, %dx
-	addw	$0xcfc, %dx
-	inb	%dx, %al
-gs	movb	%al, OFFS_CL(%bp)
-	jmp	clear_carry
-
-/*****************************************************************************/
-
-pci_bios_read_cfg_word:
-#ifdef PCI_BIOS_DEBUG
-cs	incl	num_pci_bios_read_cfg_word
-#endif
-	call	pci_bios_select_register
-gs	movw	OFFS_DI(%bp), %dx
-	andw	$2, %dx
-	addw	$0xcfc, %dx
-	inw	%dx, %ax
-gs	movw	%ax, OFFS_CX(%bp)
-	jmp	clear_carry
-
-
-/*****************************************************************************/
-
-pci_bios_read_cfg_dword:
-#ifdef PCI_BIOS_DEBUG
-cs	incl	num_pci_bios_read_cfg_dword
-#endif
-	call	pci_bios_select_register
-	movw	$0xcfc, %dx
-	inl	%dx, %eax
-gs	movl	%eax, OFFS_ECX(%bp)
-	jmp	clear_carry
-
-/*****************************************************************************/
-
-pci_bios_write_cfg_byte:
-#ifdef PCI_BIOS_DEBUG
-cs	incl	num_pci_bios_write_cfg_byte
-#endif
-	call	pci_bios_select_register
-gs	movw	OFFS_DI(%bp), %dx
-gs	movb	OFFS_CL(%bp), %al
-	andw	$3, %dx
-	addw	$0xcfc, %dx
-	outb	%al, %dx
-	jmp	clear_carry
-
-/*****************************************************************************/
-
-pci_bios_write_cfg_word:
-#ifdef PCI_BIOS_DEBUG
-cs	incl	num_pci_bios_write_cfg_word
-#endif
-	call	pci_bios_select_register
-gs	movw	OFFS_DI(%bp), %dx
-gs	movw	OFFS_CX(%bp), %ax
-	andw	$2, %dx
-	addw	$0xcfc, %dx
-	outw	%ax, %dx
-	jmp	clear_carry
-
-/*****************************************************************************/
-
-pci_bios_write_cfg_dword:
-#ifdef PCI_BIOS_DEBUG
-cs	incl	num_pci_bios_write_cfg_dword
-#endif
-	call	pci_bios_select_register
-gs	movl	OFFS_ECX(%bp), %eax
-	movw	$0xcfc, %dx
-	outl	%eax, %dx
-	jmp	clear_carry
-
-/*****************************************************************************/
-
-pci_bios_get_irq_routing:
-#ifdef PCI_BIOS_DEBUG
-cs	incl	num_pci_bios_get_irq_routing
-#endif
-	/* function not supported */
-	movb	$0x81, %ah
-	jmp	set_carry
-
-/*****************************************************************************/
-
-pci_bios_set_irq:
-#ifdef PCI_BIOS_DEBUG
-cs	incl	num_pci_bios_set_irq
-#endif
-	/* function not supported */
-	movb	$0x81, %ah
-	jmp	set_carry
-
-/*****************************************************************************/
-
-unknown_function:
-#ifdef PCI_BIOS_DEBUG
-cs	incl	num_pci_bios_unknown_function
-#endif
-	/* function not supported */
-	movb	$0x81, %ah
-	jmp	set_carry
-
-/*****************************************************************************/
-
-pci_bios_select_register:
-gs	movw	OFFS_BX(%bp), %bx
-gs	movw	OFFS_DI(%bp), %ax
-/* destroys eax, dx */
-__pci_bios_select_register:
-	/* BX holds device id, AX holds register index */
-	pushl	%ebx
-	andl	$0xfc, %eax
-	andl	$0xffff, %ebx
-	shll	$8, %ebx
-	orl	%ebx, %eax
-	orl	$0x80000000, %eax
-	movw	$0xcf8, %dx
-	outl	%eax, %dx
-	popl	%ebx
-	ret
-
-
-clear_carry:
-gs	movw	OFFS_FLAGS(%bp), %ax
-
-	/* clear carry -- function succeeded */
-	andw	$0xfffe, %ax
-gs	movw	%ax, OFFS_FLAGS(%bp)
-	xorw	%ax, %ax
-gs	movb	%ah, OFFS_AH(%bp)
-	ret
-
-set_carry:
-gs	movb	%ah, OFFS_AH(%bp)
-gs	movw	OFFS_FLAGS(%bp), %ax
-
-	/* return carry -- function not supported */
-	orw	$1, %ax
-gs	movw	%ax, OFFS_FLAGS(%bp)
-	movw	$-1, %ax
-	ret
-
-/*****************************************************************************/
-
-.globl pci_last_bus
-pci_last_bus:
-	.byte	0
-
-#ifdef PCI_BIOS_DEBUG
-.globl num_pci_bios_present
-num_pci_bios_present:
-	.long	0
-
-.globl num_pci_bios_find_device
-num_pci_bios_find_device:
-	.long	0
-
-.globl num_pci_bios_find_class
-num_pci_bios_find_class:
-	.long	0
-
-.globl num_pci_bios_generate_special_cycle
-num_pci_bios_generate_special_cycle:
-	.long 0
-
-.globl num_pci_bios_read_cfg_byte
-num_pci_bios_read_cfg_byte:
-	.long	0
-
-.globl num_pci_bios_read_cfg_word
-num_pci_bios_read_cfg_word:
-	.long	0
-
-.globl num_pci_bios_read_cfg_dword
-num_pci_bios_read_cfg_dword:
-	.long	0
-
-.globl num_pci_bios_write_cfg_byte
-num_pci_bios_write_cfg_byte:
-	.long	0
-
-.globl num_pci_bios_write_cfg_word
-num_pci_bios_write_cfg_word:
-	.long	0
-
-.globl num_pci_bios_write_cfg_dword
-num_pci_bios_write_cfg_dword:
-	.long	0
-
-.globl num_pci_bios_get_irq_routing
-num_pci_bios_get_irq_routing:
-	.long	0
-
-.globl num_pci_bios_set_irq
-num_pci_bios_set_irq:
-	.long	0
-
-.globl num_pci_bios_unknown_function
-num_pci_bios_unknown_function:
-	.long	0
-#endif
diff --git a/arch/x86/lib/bios_setup.c b/arch/x86/lib/bios_setup.c
deleted file mode 100644
index 265f7d6..0000000
--- a/arch/x86/lib/bios_setup.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Partly based on msbios.c from rolo 1.6:
- *----------------------------------------------------------------------
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions GmbH
- * Klein-Winternheim, Germany
- *----------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/realmode.h>
-#include <asm/io.h>
-#include "bios.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define NUMVECTS	256
-
-static int set_jmp_vector(int entry_point, void *target)
-{
-	if (entry_point & ~0xffff)
-		return -1;
-
-	if (((u32)target - 0xf0000) & ~0xffff)
-		return -1;
-
-	printf("set_jmp_vector: 0xf000:%04x -> %p\n",
-			entry_point, target);
-
-	/* jmp opcode */
-	writeb(0xea, 0xf0000 + entry_point);
-
-	/* offset */
-	writew(((u32)target-0xf0000), 0xf0000 + entry_point + 1);
-
-	/* segment */
-	writew(0xf000, 0xf0000 + entry_point + 3);
-
-	return 0;
-}
-
-/* Install an interrupt vector */
-static void setvector(int vector, u16 segment, void *handler)
-{
-	u16 *ptr = (u16 *)(vector * 4);
-	ptr[0] = ((u32)handler - (segment << 4)) & 0xffff;
-	ptr[1] = segment;
-
-#if 0
-	printf("setvector: int%02x -> %04x:%04x\n",
-			vector, ptr[1], ptr[0]);
-#endif
-}
-
-int bios_setup(void)
-{
-	/* The BIOS section is not relocated and still in the ROM. */
-	ulong bios_start = (ulong)&__bios_start;
-	ulong bios_size = (ulong)&__bios_size;
-
-	static int done;
-	int vector;
-#ifdef CONFIG_PCI
-	struct pci_controller *pri_hose;
-#endif
-	if (done)
-		return 0;
-
-	done = 1;
-
-	if (bios_size > 65536) {
-		printf("BIOS too large (%ld bytes, max is 65536)\n",
-				bios_size);
-		return -1;
-	}
-
-	memcpy(BIOS_BASE, (void *)bios_start, bios_size);
-
-	/* clear bda */
-	memset(BIOS_DATA, 0, BIOS_DATA_SIZE);
-
-	/* enter some values to the bda */
-	writew(0x3f8, BIOS_DATA);   /* com1 addr */
-	writew(0x2f8, BIOS_DATA+2); /* com2 addr */
-	writew(0x3e8, BIOS_DATA+4); /* com3 addr */
-	writew(0x2e8, BIOS_DATA+6); /* com4 addr */
-	writew(0x278, BIOS_DATA+8); /* lpt1 addr */
-	/*
-	 * The kernel wants to read the base memory size
-	 * from 40:13. Put a zero there to avoid an error message
-	 */
-	writew(0, BIOS_DATA+0x13);  /* base memory size */
-
-
-	/* setup realmode interrupt vectors */
-	for (vector = 0; vector < NUMVECTS; vector++)
-		setvector(vector, BIOS_CS, &rm_def_int);
-
-	setvector(0x00, BIOS_CS, &rm_int00);
-	setvector(0x01, BIOS_CS, &rm_int01);
-	setvector(0x02, BIOS_CS, &rm_int02);
-	setvector(0x03, BIOS_CS, &rm_int03);
-	setvector(0x04, BIOS_CS, &rm_int04);
-	setvector(0x05, BIOS_CS, &rm_int05);
-	setvector(0x06, BIOS_CS, &rm_int06);
-	setvector(0x07, BIOS_CS, &rm_int07);
-	setvector(0x08, BIOS_CS, &rm_int08);
-	setvector(0x09, BIOS_CS, &rm_int09);
-	setvector(0x0a, BIOS_CS, &rm_int0a);
-	setvector(0x0b, BIOS_CS, &rm_int0b);
-	setvector(0x0c, BIOS_CS, &rm_int0c);
-	setvector(0x0d, BIOS_CS, &rm_int0d);
-	setvector(0x0e, BIOS_CS, &rm_int0e);
-	setvector(0x0f, BIOS_CS, &rm_int0f);
-	setvector(0x10, BIOS_CS, &rm_int10);
-	setvector(0x11, BIOS_CS, &rm_int11);
-	setvector(0x12, BIOS_CS, &rm_int12);
-	setvector(0x13, BIOS_CS, &rm_int13);
-	setvector(0x14, BIOS_CS, &rm_int14);
-	setvector(0x15, BIOS_CS, &rm_int15);
-	setvector(0x16, BIOS_CS, &rm_int16);
-	setvector(0x17, BIOS_CS, &rm_int17);
-	setvector(0x18, BIOS_CS, &rm_int18);
-	setvector(0x19, BIOS_CS, &rm_int19);
-	setvector(0x1a, BIOS_CS, &rm_int1a);
-	setvector(0x1b, BIOS_CS, &rm_int1b);
-	setvector(0x1c, BIOS_CS, &rm_int1c);
-	setvector(0x1d, BIOS_CS, &rm_int1d);
-	setvector(0x1e, BIOS_CS, &rm_int1e);
-	setvector(0x1f, BIOS_CS, &rm_int1f);
-
-	set_jmp_vector(0xfff0, &realmode_reset);
-	set_jmp_vector(0xfe6e, &realmode_pci_bios_call_entry);
-
-	/* fill in data area */
-	RELOC_16_WORD(0xf000, ram_in_64kb_chunks) = gd->ram_size >> 16;
-	RELOC_16_WORD(0xf000, bios_equipment) = 0; /* FixMe */
-
-	/* If we assume only one PCI hose, this PCI hose
-	 * will own PCI bus #0, and the last PCI bus of
-	 * that PCI hose will be the last PCI bus in the
-	 * system.
-	 * (This, ofcause break on multi hose systems,
-	 *  but our PCI BIOS only support one hose anyway)
-	 */
-#ifdef CONFIG_PCI
-	pri_hose = pci_bus_to_hose(0);
-	if (NULL != pri_hose) {
-		/* fill in last pci bus number for use by the realmode
-		 * PCI BIOS */
-		RELOC_16_BYTE(0xf000, pci_last_bus) = pri_hose->last_busno;
-	}
-#endif
-	return 0;
-}
diff --git a/arch/x86/lib/realmode.c b/arch/x86/lib/realmode.c
deleted file mode 100644
index 75511b2..0000000
--- a/arch/x86/lib/realmode.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/ptrace.h>
-#include <asm/realmode.h>
-
-#define REALMODE_MAILBOX ((char *)0xe00)
-
-int realmode_setup(void)
-{
-	/* The realmode section is not relocated and still in the ROM. */
-	ulong realmode_start = (ulong)&__realmode_start;
-	ulong realmode_size = (ulong)&__realmode_size;
-
-	/* copy the realmode switch code */
-	if (realmode_size > (REALMODE_MAILBOX - (char *)REALMODE_BASE)) {
-		printf("realmode switch too large (%ld bytes, max is %d)\n",
-		       realmode_size,
-		       (int)(REALMODE_MAILBOX - (char *)REALMODE_BASE));
-		return -1;
-	}
-
-	memcpy((char *)REALMODE_BASE, (void *)realmode_start, realmode_size);
-	asm("wbinvd\n");
-
-	return 0;
-}
-
-int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out)
-{
-
-	/* setup out thin bios emulation */
-	if (bios_setup())
-		return -1;
-
-	if (realmode_setup())
-		return -1;
-
-	in->eip = off;
-	in->xcs = seg;
-	if ((in->esp & 0xffff) < 4)
-		printf("Warning: entering realmode with sp < 4 will fail\n");
-
-	memcpy(REALMODE_MAILBOX, in, sizeof(struct pt_regs));
-	asm("wbinvd\n");
-
-	__asm__ volatile (
-		 "lcall $0x20,%0\n" : : "i" (&realmode_enter));
-
-	asm("wbinvd\n");
-	memcpy(out, REALMODE_MAILBOX, sizeof(struct pt_regs));
-
-	return out->eax;
-}
-
-/*
- * This code is supposed to access a realmode interrupt
- * it does currently not work for me
- */
-int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out)
-{
-	/* place two instructions at 0x700 */
-	writeb(0xcd, 0x700);  /* int $lvl */
-	writeb(lvl, 0x701);
-	writeb(0xcb, 0x702);  /* lret */
-	asm("wbinvd\n");
-
-	enter_realmode(0x00, 0x700, in, out);
-
-	return out->eflags & 0x00000001;
-}
diff --git a/arch/x86/lib/realmode_switch.S b/arch/x86/lib/realmode_switch.S
deleted file mode 100644
index c4c4c43..0000000
--- a/arch/x86/lib/realmode_switch.S
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* 32bit -> 16bit -> 32bit mode switch code */
-
-/*
- * Stack frame at 0xe00
- *	e00 ebx;
- *	e04 ecx;
- *	e08 edx;
- *	e0c esi;
- *	e10 edi;
- *	e14 ebp;
- *	e18 eax;
- *	e1c ds;
- *	e20 es;
- *	e24 fs;
- *	e28 gs;
- *	e2c orig_eax;
- *	e30 eip;
- *	e34 cs;
- *	e38 eflags;
- *	e3c esp;
- *	e40 ss;
- */
-
-#define a32		.byte 0x67;	/* address size prefix 32 */
-#define o32		.byte 0x66;	/* operand size prefix 32 */
-
-.section .realmode, "ax"
-.code16
-
-	/* 16bit protected mode code here */
-.globl realmode_enter
-realmode_enter:
-o32	pusha
-o32	pushf
-	cli
-	sidt	saved_idt
-	sgdt	saved_gdt
-	movl	%esp, %eax
-	movl	%eax, saved_protected_mode_esp
-
-	movl	$0x10, %eax
-	movl	%eax, %esp
-	movw	$0x28, %ax
-	movw	%ax, %ds
-	movw	%ax, %es
-	movw	%ax, %fs
-	movw	%ax, %gs
-
-	lidt	realmode_idt_ptr
-	/* Go back into real mode by clearing PE to 0 */
-	movl	%cr0, %eax
-	andl	$0x7ffffffe, %eax
-	movl	%eax, %cr0
-
-	/* switch to real mode */
-	ljmp	$0x0,$do_realmode
-
-do_realmode:
-	/* realmode code from here */
-	movw	%cs,%ax
-	movw	%ax,%ds
-	movw	%ax,%es
-	movw	%ax,%fs
-	movw	%ax,%gs
-
-	/* create a temporary stack */
-	movw	$0xc0, %ax
-	movw	%ax, %ss
-	movw	$0x200, %ax
-	movw	%ax, %sp
-
-	popl	%ebx
-	popl	%ecx
-	popl	%edx
-	popl	%esi
-	popl	%edi
-	popl	%ebp
-	popl	%eax
-	movl	%eax, temp_eax
-	popl	%eax
-	movw	%ax, %ds
-	popl	%eax
-	movw	%ax, %es
-	popl	%eax
-	movw	%ax, %fs
-	popl	%eax
-	movw	%ax, %gs
-	popl	%eax				/* orig_eax */
-	popl	%eax
-cs	movw	%ax, temp_ip
-	popl	%eax
-cs	movw	%ax, temp_cs
-o32	popf
-	popl	%eax
-	popw	%ss
-	movl	%eax, %esp
-cs	movl	temp_eax, %eax
-
-	/* self-modifying code, better flush the cache */
-	wbinvd
-
-	.byte	0x9a				/* lcall */
-temp_ip:
-	.word	0				/* new ip */
-temp_cs:
-	.word	0				/* new cs */
-
-realmode_ret:
-	/* save eax, esp and ss */
-cs	movl	%eax, saved_eax
-	movl	%esp, %eax
-cs	movl	%eax, saved_esp
-	movw	%ss, %ax
-cs	movw	%ax, saved_ss
-
-	/*
-	 * restore the stack, note that we set sp to 0x244;
-	 * pt_regs is 0x44 bytes long and we push the structure
-	 * backwards on to the stack, bottom first
-	 */
-	movw	$0xc0, %ax
-	movw	%ax, %ss
-	movw	$0x244, %ax
-	movw	%ax, %sp
-
-	xorl	%eax,%eax
-cs	movw	saved_ss, %ax
-	pushl	%eax
-cs	movl	saved_esp, %eax
-	pushl	%eax
-o32	pushf
-	xorl	%eax,%eax
-cs	movw	temp_cs, %ax
-	pushl	%eax
-cs	movw	temp_ip, %ax
-	pushl	%eax
-	pushl	$0
-	movw	%gs, %ax
-	pushl	%eax
-	movw	%fs, %ax
-	pushl	%eax
-	movw	%es, %ax
-	pushl	%eax
-	movw	%ds, %ax
-	pushl	%eax
-	movl	saved_eax, %eax
-	pushl	%eax
-	pushl	%ebp
-	pushl	%edi
-	pushl	%esi
-	pushl	%edx
-	pushl	%ecx
-	pushl	%ebx
-
-o32 cs	lidt	saved_idt
-o32 cs	lgdt	saved_gdt
-
-	/* Go back into protected mode reset PE to 1 */
-	movl	%cr0, %eax
-	orl	$1,%eax
-	movl	%eax, %cr0
-
-	/* flush prefetch queue */
-	jmp	next_line
-next_line:
-	movw	$return_ptr, %ax
-	movw	%ax,%bp
-o32 cs	ljmp	*(%bp)
-
-.code32
-protected_mode:
-	/* Reload segment registers */
-	movl	$0x18, %eax
-	movw	%ax, %fs
-	movw	%ax, %ds
-	movw	%ax, %gs
-	movw	%ax, %es
-	movw	%ax, %ss
-	movl	saved_protected_mode_esp, %eax
-	movl	%eax, %esp
-	popf
-	popa
-	ret
-
-temp_eax:
-	.long	0
-
-saved_ss:
-	.word	0
-saved_esp:
-	.long	0
-saved_eax:
-	.long	0
-
-realmode_idt_ptr:
-	.word	0x400
-	.word	0x0, 0x0
-
-saved_gdt:
-	.word	0, 0, 0, 0
-saved_idt:
-	.word	0, 0, 0, 0
-
-saved_protected_mode_esp:
-	.long	0
-
-return_ptr:
-	.long	protected_mode
-	.word	0x10
diff --git a/arch/x86/lib/video.c b/arch/x86/lib/video.c
index 20e2416..81824f3 100644
--- a/arch/x86/lib/video.c
+++ b/arch/x86/lib/video.c
@@ -26,7 +26,6 @@
 #include <stdio_dev.h>
 #include <i8042.h>
 #include <asm/ptrace.h>
-#include <asm/realmode.h>
 #include <asm/io.h>
 #include <asm/pci.h>
 
@@ -222,10 +221,5 @@
 
 int drv_video_init(void)
 {
-#ifndef CONFIG_X86_NO_REAL_MODE
-	if (video_bios_init())
-		return 1;
-#endif
-
 	return video_init();
 }
diff --git a/arch/x86/lib/video_bios.c b/arch/x86/lib/video_bios.c
deleted file mode 100644
index 1e06759..0000000
--- a/arch/x86/lib/video_bios.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-#include <malloc.h>
-#include <asm/ptrace.h>
-#include <asm/realmode.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-#include "bios.h"
-
-#undef PCI_BIOS_DEBUG
-#undef VGA_BIOS_DEBUG
-
-#ifdef	VGA_BIOS_DEBUG
-#define	PRINTF(fmt, args...)	printf(fmt, ##args)
-#else
-#define PRINTF(fmt, args...)
-#endif
-
-#define PCI_CLASS_VIDEO			3
-#define PCI_CLASS_VIDEO_STD		0
-#define PCI_CLASS_VIDEO_PROG_IF_VGA	0
-
-DEFINE_PCI_DEVICE_TABLE(supported) = {
-	{PCI_VIDEO_VENDOR_ID, PCI_VIDEO_DEVICE_ID},
-	{}
-};
-
-static u32 probe_pci_video(void)
-{
-	struct pci_controller *hose;
-	pci_dev_t devbusfn = pci_find_devices(supported, 0);
-
-	if ((devbusfn != -1)) {
-		u32 old;
-		u32 addr;
-
-		/* PCI video device detected */
-		printf("Found PCI VGA device at %02x.%02x.%x\n",
-		       PCI_BUS(devbusfn),
-		       PCI_DEV(devbusfn),
-		       PCI_FUNC(devbusfn));
-
-		/* Enable I/O decoding as well, PCI viudeo boards
-		 * support I/O accesses, but they provide no
-		 * bar register for this since the ports are fixed.
-		 */
-		pci_write_config_word(devbusfn,
-				      PCI_COMMAND,
-				      PCI_COMMAND_MEMORY |
-				      PCI_COMMAND_IO |
-				      PCI_COMMAND_MASTER);
-
-		/* Test the ROM decoder, do the device support a rom? */
-		pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &old);
-		pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS,
-				       (u32)PCI_ROM_ADDRESS_MASK);
-		pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &addr);
-		pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, old);
-
-		if (!addr) {
-			printf("PCI VGA have no ROM?\n");
-			return 0;
-		}
-
-		/* device have a rom */
-		if (pci_shadow_rom(devbusfn, (void *)0xc0000)) {
-			printf("Shadowing of PCI VGA BIOS failed\n");
-			return 0;
-		}
-
-		/* Now enable lagacy VGA port access */
-		hose = pci_bus_to_hose(PCI_BUS(devbusfn));
-		if (pci_enable_legacy_video_ports(hose)) {
-			printf("PCI VGA enable failed\n");
-			return 0;
-		}
-
-
-		/* return the pci device info, that we'll need later */
-		return PCI_BUS(devbusfn) << 8 |
-			PCI_DEV(devbusfn) << 3 | (PCI_FUNC(devbusfn) & 7);
-	}
-
-	return 0;
-}
-
-static int probe_isa_video(void)
-{
-	u32 ptr;
-	char *buf;
-
-	ptr = isa_map_rom(0xc0000, 0x8000);
-
-	if (!ptr)
-		return -1;
-
-	buf = malloc(0x8000);
-	if (!buf) {
-		isa_unmap_rom(ptr);
-		return -1;
-	}
-
-	if (readw(ptr) != 0xaa55) {
-		free(buf);
-		isa_unmap_rom(ptr);
-		return -1;
-	}
-
-	/* shadow the rom */
-	memcpy(buf, (void *)ptr, 0x8000);
-	isa_unmap_rom(ptr);
-	memcpy((void *)0xc0000, buf, 0x8000);
-
-	free(buf);
-
-	return 0;
-}
-
-int video_bios_init(void)
-{
-	struct pt_regs regs;
-	int size;
-	int i;
-	u8 sum;
-
-	/* clear the video bios area in case we warmbooted */
-	memset((void *)0xc0000, 0, 0x8000);
-	memset(&regs, 0, sizeof(struct pt_regs));
-
-	if (probe_isa_video())
-		/* No ISA board found, try the PCI bus */
-		regs.eax = probe_pci_video();
-
-	/* Did we succeed in mapping any video bios */
-	if (readw(0xc0000) == 0xaa55) {
-		PRINTF("Found video bios signature\n");
-		size = readb(0xc0002) * 512;
-		PRINTF("size %d\n", size);
-		sum = 0;
-
-		for (i = 0; i < size; i++)
-			sum += readb(0xc0000 + i);
-
-		PRINTF("Checksum is %sOK\n", sum ? "NOT " : "");
-
-		if (sum)
-			return 1;
-
-		/*
-		 * Some video bioses (ATI Mach64) seem to think that
-		 * the original int 10 handler is always at
-		 * 0xf000:0xf065 , place an iret instruction there
-		 */
-		writeb(0xcf, 0xff065);
-
-		regs.esp = 0x8000;
-		regs.xss = 0x2000;
-		enter_realmode(0xc000, 3, &regs, &regs);
-
-		PRINTF("INT 0x10 vector after:  %04x:%04x\n",
-		       readw(0x42), readw(0x40));
-		PRINTF("BIOS returned %scarry\n",
-		       regs.eflags & 0x00000001 ? "" : "NOT ");
-#ifdef PCI_BIOS_DEBUG
-		print_bios_bios_stat();
-#endif
-		return regs.eflags & 0x00000001;
-
-	}
-
-	return 1;
-
-}
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 46af391..4e9e1f7 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -33,7 +33,6 @@
 #include <asm/io.h>
 #include <asm/ptrace.h>
 #include <asm/zimage.h>
-#include <asm/realmode.h>
 #include <asm/byteorder.h>
 #include <asm/bootparam.h>
 #ifdef CONFIG_SYS_COREBOOT
@@ -175,16 +174,9 @@
 	else
 		*load_address = (void *)ZIMAGE_LOAD_ADDR;
 
-#if (defined CONFIG_ZBOOT_32 || defined CONFIG_X86_NO_REAL_MODE)
 	printf("Building boot_params at 0x%8.8lx\n", (ulong)setup_base);
 	memset(setup_base, 0, sizeof(*setup_base));
 	setup_base->hdr = params->hdr;
-#else
-	/* load setup */
-	printf("Moving Real-Mode Code to 0x%8.8lx (%d bytes)\n",
-	       (ulong)setup_base, setup_size);
-	memmove(setup_base, image, setup_size);
-#endif
 
 	if (bootproto >= 0x0204)
 		kernel_size = hdr->syssize * 16;
@@ -241,10 +233,8 @@
 	struct setup_header *hdr = &setup_base->hdr;
 	int bootproto = get_boot_protocol(hdr);
 
-#if (defined CONFIG_ZBOOT_32 || defined CONFIG_X86_NO_REAL_MODE)
 	setup_base->e820_entries = install_e820_map(
 		ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map);
-#endif
 
 	if (bootproto == 0x0100) {
 		setup_base->screen_info.cl_magic = COMMAND_LINE_MAGIC;
@@ -300,7 +290,6 @@
 #ifdef CONFIG_SYS_COREBOOT
 	timestamp_add_now(TS_U_BOOT_START_KERNEL);
 #endif
-#if defined CONFIG_ZBOOT_32
 	/*
 	 * Set %ebx, %ebp, and %edi to 0, %esi to point to the boot_params
 	 * structure, and then jump to the kernel. We assume that %cs is
@@ -317,18 +306,6 @@
 	   "b"(0), "D"(0)
 	:  "%ebp"
 	);
-#else
-	struct pt_regs regs;
-
-	memset(&regs, 0, sizeof(struct pt_regs));
-	regs.xds = (u32)setup_base >> 4;
-	regs.xes = regs.xds;
-	regs.xss = regs.xds;
-	regs.esp = 0x9000;
-	regs.eflags = 0;
-	enter_realmode(((u32)setup_base + SETUP_START_OFFSET) >> 4, 0,
-		       &regs, &regs);
-#endif
 }
 
 void setup_pcat_compatibility(void)
diff --git a/board/avionic-design/dts/tegra20-medcom-wide.dts b/board/avionic-design/dts/tegra20-medcom-wide.dts
index f916122..e46afbe 100644
--- a/board/avionic-design/dts/tegra20-medcom-wide.dts
+++ b/board/avionic-design/dts/tegra20-medcom-wide.dts
@@ -14,18 +14,17 @@
 		reg = <0x00000000 0x20000000>;
 	};
 
-	clocks {
-		clk_32k: clk_32k {
-			clock-frequency = <32000>;
-		};
+	host1x {
+		status = "okay";
 
-		osc {
-			clock-frequency = <12000000>;
-		};
-	};
+		dc@54200000 {
+			status = "okay";
 
-	clock@60006000 {
-		clocks = <&clk_32k &osc>;
+			rgb {
+				nvidia,panel = <&lcd_panel>;
+				status = "okay";
+			};
+		};
 	};
 
 	serial@70006300 {
@@ -55,4 +54,23 @@
 	usb@c5004000 {
 		status = "disabled";
 	};
+
+	lcd_panel: panel {
+		clock = <61715000>;
+		xres = <1366>;
+		yres = <768>;
+		left-margin = <2>;
+		right-margin = <47>;
+		hsync-len = <136>;
+		lower-margin = <21>;
+		upper-margin = <11>;
+		vsync-len = <4>;
+
+		nvidia,bits-per-pixel = <16>;
+		nvidia,pwm = <&pwm 0 500000>;
+		nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
+		nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
+		nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
+		nvidia,panel-timings = <0 0 0 0>;
+	};
 };
diff --git a/board/avionic-design/dts/tegra20-plutux.dts b/board/avionic-design/dts/tegra20-plutux.dts
index 78c394f..3e6cce0 100644
--- a/board/avionic-design/dts/tegra20-plutux.dts
+++ b/board/avionic-design/dts/tegra20-plutux.dts
@@ -14,20 +14,6 @@
 		reg = <0x00000000 0x20000000>;
 	};
 
-	clocks {
-		clk_32k: clk_32k {
-			clock-frequency = <32000>;
-		};
-
-		osc {
-			clock-frequency = <12000000>;
-		};
-	};
-
-	clock@60006000 {
-		clocks = <&clk_32k &osc>;
-	};
-
 	serial@70006300 {
 		clock-frequency = <216000000>;
 	};
diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts
index 50ea3b5..bf3ff1d 100644
--- a/board/avionic-design/dts/tegra20-tec.dts
+++ b/board/avionic-design/dts/tegra20-tec.dts
@@ -14,24 +14,34 @@
 		reg = <0x00000000 0x20000000>;
 	};
 
-	clocks {
-		clk_32k: clk_32k {
-			clock-frequency = <32000>;
-		};
+	host1x {
+		status = "okay";
 
-		osc {
-			clock-frequency = <12000000>;
-		};
-	};
+		dc@54200000 {
+			status = "okay";
 
-	clock@60006000 {
-		clocks = <&clk_32k &osc>;
+			rgb {
+				nvidia,panel = <&lcd_panel>;
+				status = "okay";
+			};
+		};
 	};
 
 	serial@70006300 {
 		clock-frequency = <216000000>;
 	};
 
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
+		nvidia,width = <8>;
+		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+
+		nand@0 {
+			reg = <0>;
+			compatible = "hynix,hy27uf4g2b", "nand-flash";
+		};
+	};
+
 	i2c@7000c000 {
 		status = "disabled";
 	};
@@ -56,14 +66,22 @@
 		status = "disabled";
 	};
 
-	nand-controller@70008000 {
-		nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
-		nvidia,width = <8>;
-		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+	lcd_panel: panel {
+		clock = <33260000>;
+		xres = <800>;
+		yres = <480>;
+		left-margin = <120>;
+		right-margin = <120>;
+		hsync-len = <16>;
+		lower-margin = <15>;
+		upper-margin = <15>;
+		vsync-len = <15>;
 
-		nand@0 {
-			reg = <0>;
-			compatible = "hynix,hy27uf4g2b", "nand-flash";
-		};
+		nvidia,bits-per-pixel = <16>;
+		nvidia,pwm = <&pwm 0 500000>;
+		nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
+		nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
+		nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
+		nvidia,panel-timings = <0 0 0 0>;
 	};
 };
diff --git a/board/bluegiga/apx4devkit/apx4devkit.c b/board/bluegiga/apx4devkit/apx4devkit.c
index ae48ab5..5927693 100644
--- a/board/bluegiga/apx4devkit/apx4devkit.c
+++ b/board/bluegiga/apx4devkit/apx4devkit.c
@@ -43,12 +43,12 @@
 int board_early_init_f(void)
 {
 	/* IO0 clock at 480MHz */
-	mx28_set_ioclk(MXC_IOCLK0, 480000);
+	mxs_set_ioclk(MXC_IOCLK0, 480000);
 	/* IO1 clock at 480MHz */
-	mx28_set_ioclk(MXC_IOCLK1, 480000);
+	mxs_set_ioclk(MXC_IOCLK1, 480000);
 
 	/* SSP0 clock at 96MHz */
-	mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
+	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
 
 	return 0;
 }
@@ -69,7 +69,7 @@
 #ifdef CONFIG_CMD_MMC
 int board_mmc_init(bd_t *bis)
 {
-	return mxsmmc_initialize(bis, 0, NULL);
+	return mxsmmc_initialize(bis, 0, NULL, NULL);
 }
 #endif
 
diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c
index b25887b..c0ea1c6 100644
--- a/board/cm5200/cm5200.c
+++ b/board/cm5200/cm5200.c
@@ -44,7 +44,6 @@
 
 #ifdef CONFIG_OF_LIBFDT
 #include <libfdt.h>
-#include <libfdt_env.h>
 #include <fdt_support.h>
 #endif /* CONFIG_OF_LIBFDT */
 
diff --git a/board/compal/dts/tegra20-paz00.dts b/board/compal/dts/tegra20-paz00.dts
index 9e3e169..31b064d 100644
--- a/board/compal/dts/tegra20-paz00.dts
+++ b/board/compal/dts/tegra20-paz00.dts
@@ -14,17 +14,15 @@
 		reg = <0x00000000 0x20000000>;
 	};
 
-	clocks {
-		clk_32k: clk_32k {
-			clock-frequency = <32000>;
+	host1x {
+		status = "okay";
+		dc@54200000 {
+			status = "okay";
+			rgb {
+				status = "okay";
+				nvidia,panel = <&lcd_panel>;
+			};
 		};
-		osc {
-			clock-frequency = <12000000>;
-		};
-	};
-
-	clock@60006000 {
-		clocks = <&clk_32k &osc>;
 	};
 
 	serial@70006000 {
@@ -54,4 +52,25 @@
 	usb@c5004000 {
 		status = "disabled";
 	};
+
+	lcd_panel: panel {
+		/* PAZ00 has 1024x600 */
+		clock = <54030000>;
+		xres = <1024>;
+		yres = <600>;
+		right-margin = <160>;
+		left-margin = <24>;
+		hsync-len = <136>;
+		upper-margin = <3>;
+		lower-margin = <61>;
+		vsync-len = <6>;
+		hsync-active-high;
+		nvidia,bits-per-pixel = <16>;
+		nvidia,pwm = <&pwm 0 0>;
+		nvidia,backlight-enable-gpios = <&gpio 164 0>;	/* PU4 */
+		nvidia,lvds-shutdown-gpios = <&gpio 102 0>;	/* PM6 */
+		nvidia,backlight-vdd-gpios = <&gpio 176 0>;	/* PW0 */
+		nvidia,panel-vdd-gpios = <&gpio 4 0>;		/* PA4 */
+		nvidia,panel-timings = <400 4 203 17 15>;
+	};
 };
diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c
index 6492d41..1447f47 100644
--- a/board/compal/paz00/paz00.c
+++ b/board/compal/paz00/paz00.c
@@ -71,3 +71,14 @@
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_LCD
+/* this is a weak define that we are overriding */
+void pin_mux_display(void)
+{
+	debug("init display pinmux\n");
+
+	/* EN_VDD_PANEL GPIO A4 */
+	pinmux_tristate_disable(PINGRP_DAP2);
+}
+#endif
diff --git a/board/compulab/dts/tegra20-trimslice.dts b/board/compulab/dts/tegra20-trimslice.dts
index 4450674..7aeed67 100644
--- a/board/compulab/dts/tegra20-trimslice.dts
+++ b/board/compulab/dts/tegra20-trimslice.dts
@@ -15,19 +15,6 @@
 		reg = <0x00000000 0x40000000>;
 	};
 
-	clocks {
-		clk_32k: clk_32k {
-			clock-frequency = <32000>;
-		};
-		osc {
-			clock-frequency = <12000000>;
-		};
-	};
-
-	clock@60006000 {
-		clocks = <&clk_32k &osc>;
-	};
-
 	serial@70006000 {
 		clock-frequency = <216000000>;
 	};
@@ -36,6 +23,11 @@
 		status = "disabled";
 	};
 
+	spi@7000c380 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
 	i2c@7000c400 {
 		status = "disabled";
 	};
diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c
index 9d6db65..d93efaf 100644
--- a/board/denx/m28evk/m28evk.c
+++ b/board/denx/m28evk/m28evk.c
@@ -43,14 +43,14 @@
 int board_early_init_f(void)
 {
 	/* IO0 clock at 480MHz */
-	mx28_set_ioclk(MXC_IOCLK0, 480000);
+	mxs_set_ioclk(MXC_IOCLK0, 480000);
 	/* IO1 clock at 480MHz */
-	mx28_set_ioclk(MXC_IOCLK1, 480000);
+	mxs_set_ioclk(MXC_IOCLK1, 480000);
 
 	/* SSP0 clock at 96MHz */
-	mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
+	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
 	/* SSP2 clock at 160MHz */
-	mx28_set_sspclk(MXC_SSPCLK2, 160000, 0);
+	mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
 
 #ifdef	CONFIG_CMD_USB
 	mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
@@ -93,7 +93,7 @@
 	/* Turn on the power to the card. */
 	gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
 
-	return mxsmmc_initialize(bis, 0, m28_mmc_wp);
+	return mxsmmc_initialize(bis, 0, m28_mmc_wp, NULL);
 }
 #endif
 
diff --git a/board/eNET/Makefile b/board/eNET/Makefile
deleted file mode 100644
index ad1c5b1..0000000
--- a/board/eNET/Makefile
+++ /dev/null
@@ -1,52 +0,0 @@
-#
-# (C) Copyright 2008
-# Graeme Russ, graeme.russ@gmail.com.
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2002
-# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= eNET.o
-COBJS-$(CONFIG_PCI) += eNET_pci.o
-SOBJS-y	+= eNET_start16.o
-SOBJS-y	+= eNET_start.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
deleted file mode 100644
index 2f26470..0000000
--- a/board/eNET/eNET.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc520.h>
-#include <net.h>
-#include <netdev.h>
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-#endif
-
-#include "hardware.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
-
-static void enet_timer_isr(void);
-static void enet_toggle_run_led(void);
-static void enet_setup_pars(void);
-
-/*
- * Miscellaneous platform dependent initializations
- */
-int board_early_init_f(void)
-{
-	u16 pio_out_cfg = 0x0000;
-
-	/* Configure General Purpose Bus timing */
-	writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
-	writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
-	writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
-	writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
-	writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
-	writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
-	writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
-
-	/* Configure Programmable Input/Output Pins */
-	writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
-	writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
-	writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
-	writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
-	writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
-	writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
-
-	/*
-	 * Turn off top board
-	 * Set StrataFlash chips to 16-bit width
-	 * Set StrataFlash chips to normal (non reset/power down) mode
-	 */
-	pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
-	pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
-	pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
-	pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
-	writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
-
-	/* Turn off auxiliary power output */
-	writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
-
-	/* Clear FPGA program mode */
-	writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
-
-	enet_setup_pars();
-
-	/* Disable Watchdog */
-	writew(0x3333, &sc520_mmcr->wdtmrctl);
-	writew(0xcccc, &sc520_mmcr->wdtmrctl);
-	writew(0x0000, &sc520_mmcr->wdtmrctl);
-
-	/* Chip Select Configuration */
-	writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
-	writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
-	writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
-
-	writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
-	writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
-	writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
-
-	writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
-	writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
-
-	/* enable posted-writes */
-	writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
-
-	return 0;
-}
-
-static void enet_setup_pars(void)
-{
-	/*
-	 * PARs 11 and 12 are 2MB SRAM @ 0x19000000
-	 *
-	 * These are setup now because older version of U-Boot have them
-	 * mapped to a different PAR which gets clobbered which prevents
-	 * using SRAM for warm-booting a new image
-	 */
-	writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]);
-	writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]);
-
-	/* PARs 0 and 1 are Compact Flash slots (4kB each) */
-	writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]);
-	writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]);
-
-	/* PAR 2 is used for Cache-As-RAM */
-
-	/*
-	 * PARs 5 through 8 are additional NS16550 UARTS
-	 * 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8
-	 */
-	writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]);
-	writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]);
-	writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]);
-	writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]);
-
-	/* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */
-	writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]);
-	writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]);
-
-	/* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */
-	writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]);
-
-	/*
-	 * PAR 14 is Low Level I/O (LEDs, Hex Switches etc)
-	 * Already configured in board_init16 (eNET_start16.S)
-	 *
-	 * PAR 15 is Boot ROM
-	 * Already configured in board_init16 (eNET_start16.S)
-	 */
-}
-
-
-int board_early_init_r(void)
-{
-	/* CPU Speed to 100MHz */
-	gd->cpu_clk = 100000000;
-
-	/* Crystal is 33.000MHz */
-	gd->bus_clk = 33000000;
-
-	return 0;
-}
-
-void show_boot_progress(int val)
-{
-	uchar led_mask;
-
-	led_mask = 0x00;
-
-	if (val < 0)
-		led_mask |= LED_ERR_BITMASK;
-
-	led_mask |= (uchar)(val & 0x001f);
-	outb(led_mask, LED_LATCH_ADDRESS);
-}
-
-
-int last_stage_init(void)
-{
-	outb(0x00, LED_LATCH_ADDRESS);
-
-	register_timer_isr(enet_timer_isr);
-
-	printf("Serck Controls eNET\n");
-
-	return 0;
-}
-
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
-	if (banknum == 0) {	/* non-CFI boot flash */
-		info->portwidth = FLASH_CFI_8BIT;
-		info->chipwidth = FLASH_CFI_BY8;
-		info->interface = FLASH_CFI_X8;
-		return 1;
-	} else {
-		return 0;
-	}
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}
-
-void setup_pcat_compatibility()
-{
-	/* disable global interrupt mode */
-	writeb(0x40, &sc520_mmcr->picicr);
-
-	/* set all irqs to edge */
-	writeb(0x00, &sc520_mmcr->pic_mode[0]);
-	writeb(0x00, &sc520_mmcr->pic_mode[1]);
-	writeb(0x00, &sc520_mmcr->pic_mode[2]);
-
-	/*
-	 *  active low polarity on PIC interrupt pins,
-	 *  active high polarity on all other irq pins
-	 */
-	writew(0x0000, &sc520_mmcr->intpinpol);
-
-	/*
-	 * PIT 0 -> IRQ0
-	 * RTC -> IRQ8
-	 * FP error -> IRQ13
-	 * UART1 -> IRQ4
-	 * UART2 -> IRQ3
-	 */
-	writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
-	writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
-	writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
-	writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
-	writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
-
-	/* Disable all other interrupt sources */
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
-}
-
-void enet_timer_isr(void)
-{
-	static long enet_ticks;
-
-	enet_ticks++;
-
-	/* Toggle Watchdog every 100ms */
-	if ((enet_ticks % 100) == 0)
-		hw_watchdog_reset();
-
-	/* Toggle Run LED every 500ms */
-	if ((enet_ticks % 500) == 0)
-		enet_toggle_run_led();
-}
-
-void hw_watchdog_reset(void)
-{
-	/* Watchdog Reset must be atomic */
-	long flag = disable_interrupts();
-
-	if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
-		sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
-	else
-		sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
-
-	if (flag)
-		enable_interrupts();
-}
-
-void enet_toggle_run_led(void)
-{
-	unsigned char leds_state = inb(LED_LATCH_ADDRESS);
-	if (leds_state & LED_RUN_BITMASK)
-		outb(leds_state & ~LED_RUN_BITMASK, LED_LATCH_ADDRESS);
-	else
-		outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
-}
diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c
deleted file mode 100644
index 5af4ef7..0000000
--- a/board/eNET/eNET_pci.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * (C) Copyright 2008,2009
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/pci.h>
-#include <asm/arch/pci.h>
-
-static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
-	/* a configurable lists of IRQs to steal when we need one */
-	static int irq_list[] = {
-		CONFIG_SYS_FIRST_PCI_IRQ,
-		CONFIG_SYS_SECOND_PCI_IRQ,
-		CONFIG_SYS_THIRD_PCI_IRQ,
-		CONFIG_SYS_FORTH_PCI_IRQ
-	};
-	static int next_irq_index;
-
-	uchar tmp_pin;
-	int pin;
-
-	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
-	pin = tmp_pin;
-
-	pin -= 1; /* PCI config space use 1-based numbering */
-	if (pin == -1)
-		return; /* device use no irq */
-
-	/* map device number +  pin to a pin on the sc520 */
-	switch (PCI_DEV(dev)) {
-	case 12:	/* First Ethernet Chip */
-		pin += SC520_PCI_INTA;
-		break;
-
-	case 13:	/* Second Ethernet Chip */
-		pin += SC520_PCI_INTB;
-		break;
-
-	default:
-		return;
-	}
-
-	pin &= 3; /* wrap around */
-
-	if (sc520_pci_ints[pin] == -1) {
-		/* re-route one interrupt for us */
-		if (next_irq_index > 3)
-			return;
-
-		if (pci_sc520_set_irq(pin, irq_list[next_irq_index]))
-			return;
-
-		next_irq_index++;
-	}
-
-	if (-1 != sc520_pci_ints[pin])
-		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
-					   sc520_pci_ints[pin]);
-
-	printf("fixup_irq: device %d pin %c irq %d\n",
-	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
-}
-
-static struct pci_controller enet_hose = {
-	fixup_irq: pci_enet_fixup_irq,
-};
-
-void pci_init_board(void)
-{
-	pci_sc520_init(&enet_hose);
-}
-
-int pci_set_regions(struct pci_controller *hose)
-{
-	/* System memory space */
-	pci_set_region(hose->regions + 0,
-		       SC520_PCI_MEMORY_BUS,
-		       SC520_PCI_MEMORY_PHYS,
-		       SC520_PCI_MEMORY_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
-	/* ISA/PCI memory space */
-	pci_set_region(hose->regions + 1,
-		       SC520_ISA_MEM_BUS,
-		       SC520_ISA_MEM_PHYS,
-		       SC520_ISA_MEM_SIZE,
-		       PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region(hose->regions + 2,
-		       SC520_PCI_IO_BUS,
-		       SC520_PCI_IO_PHYS,
-		       SC520_PCI_IO_SIZE,
-		       PCI_REGION_IO);
-
-	/* ISA/PCI I/O space */
-	pci_set_region(hose->regions + 3,
-		       SC520_ISA_IO_BUS,
-		       SC520_ISA_IO_PHYS,
-		       SC520_ISA_IO_SIZE,
-		       PCI_REGION_IO);
-
-	return 4;
-}
diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S
deleted file mode 100644
index 5e3f44c6..0000000
--- a/board/eNET/eNET_start16.S
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * 16bit initialization code.
- * This code have to map the area of the boot flash
- * that is used by U-boot to its final destination.
- */
-
-#include "config.h"
-#include "hardware.h"
-#include <asm/arch/sc520.h>
-#include <generated/asm-offsets.h>
-
-.text
-.section .start16, "ax"
-.code16
-.globl board_init16
-board_init16:
-	/* Alias MMCR to 0xdf000 */
-	movw	$0xfffc, %dx
-	movl	$0x800df0cb, %eax
-	outl	%eax, %dx
-
-	/* Set ds to point to MMCR alias */
-	movw	$0xdf00, %ax
-	movw	%ax, %ds
-
-	/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
-	movl    $GENERATED_SC520_PAR14, %edi
-	movl	$CONFIG_SYS_SC520_BOOTCS_PAR, %eax
-	movl	%eax, (%di)
-
-	/* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
-	movl    $GENERATED_SC520_PAR15, %edi
-	movl	$CONFIG_SYS_SC520_LLIO_PAR, %eax
-	movl	%eax, (%di)
-
-	/* Disabe MMCR alias */
-	movw	$0xfffc, %dx
-	movl	$0x000000cb, %eax
-	outl	%eax, %dx
-
-	jmp	board_init16_ret
-
-.section .bios, "ax"
-.code16
-.globl realmode_reset
-.hidden realmode_reset
-.type realmode_reset, @function
-realmode_reset:
-	/* Alias MMCR to 0xdf000 */
-	movw	$0xfffc, %dx
-	movl	$0x800df0cb, %eax
-	outl	%eax, %dx
-
-	/* Set ds to point to MMCR alias */
-	movw	$0xdf00, %ax
-	movw	%ax, %ds
-
-	/* issue software reset thorugh MMCR */
-	movl    $0xd72, %edi
-	movb	$0x01, %al
-	movb	%al, (%di)
-
-1:	hlt
-	jmp	1
diff --git a/board/eNET/hardware.h b/board/eNET/hardware.h
deleted file mode 100644
index dec2cd8..0000000
--- a/board/eNET/hardware.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef HARDWARE_H_
-#define HARDWARE_H_
-
-#define LED_LATCH_ADDRESS	0x1002
-#define LED_RUN_BITMASK		0x01
-#define LED_1_BITMASK		0x02
-#define LED_2_BITMASK		0x04
-#define LED_RX_BITMASK		0x08
-#define LED_TX_BITMASK		0x10
-#define LED_ERR_BITMASK		0x20
-#define WATCHDOG_PIO_BIT	0x8000
-
-#endif /* HARDWARE_H_ */
diff --git a/board/esg/ima3-mx53/imximage.cfg b/board/esg/ima3-mx53/imximage.cfg
index fa6b42d..fce7492 100644
--- a/board/esg/ima3-mx53/imximage.cfg
+++ b/board/esg/ima3-mx53/imximage.cfg
@@ -1,50 +1,52 @@
-#
-# (C) Copyright 2012
-# Stefano Babic DENX Software Engineering sbabic@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
+/*
+ * (C) Copyright 2012
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
 
-# image version
-
+/* image version */
 IMAGE_VERSION 2
 
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
 BOOT_FROM	nor
 
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type           Address        Value
-#
-# where:
-#	Addr-type register length (1,2 or 4 bytes)
-#	Address	  absolute address of the register
-#	value	  value to be stored in the register
-
-# IOMUX for RAM only
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+/* IOMUX for RAM only */
 DATA 4 0x53fa8554 0x300020
 DATA 4 0x53fa8560 0x300020
 DATA 4 0x53fa8594 0x300020
@@ -72,37 +74,47 @@
 DATA 4 0x53fa86f4 0x0
 DATA 4 0x53fa8714 0x0
 DATA 4 0x53fa8724 0x4000000
-#
-# DDR RAM
+
+/* DDR RAM */
 DATA 4 0x63fd9088 0x40404040
 DATA 4 0x63fd9090 0x40404040
 DATA 4 0x63fd907C 0x01420143
 DATA 4 0x63fd9080 0x01450146
 DATA 4 0x63fd9018 0x00111740
 DATA 4 0x63fd9000 0x84190000
-# esdcfgX
+
+/* esdcfgX */
 DATA 4 0x63fd900C 0x9f5152e3
 DATA 4 0x63fd9010 0xb68e8a63
 DATA 4 0x63fd9014 0x01ff00db
-# Read/Write command delay
+
+/* Read/Write command delay */
 DATA 4 0x63fd902c 0x000026d2
-# Out of reset delays
+
+/* Out of reset delays */
 DATA 4 0x63fd9030 0x00ff0e21
-# ESDCTL ODT timing control
+
+/* ESDCTL ODT timing control */
 DATA 4 0x63fd9008 0x12273030
-# ESDCTL power down control
+
+/* ESDCTL power down control */
 DATA 4 0x63fd9004 0x0002002d
-# Set registers in DDR memory chips
+
+/* Set registers in DDR memory chips */
 DATA 4 0x63fd901c 0x00008032
 DATA 4 0x63fd901c 0x00008033
 DATA 4 0x63fd901c 0x00028031
 DATA 4 0x63fd901c 0x052080b0
 DATA 4 0x63fd901c 0x04008040
-# ESDCTL refresh control
+
+/* ESDCTL refresh control */
 DATA 4 0x63fd9020 0x00005800
-# PHY ZQ HW control
+
+/* PHY ZQ HW control */
 DATA 4 0x63fd9040 0x05380003
-# PHY ODT control
+
+/* PHY ODT control */
 DATA 4 0x63fd9058 0x00022222
-# start DDR3
+
+/* start DDR3 */
 DATA 4 0x63fd901c 0x00000000
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 62498ab..c86cd40 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -1,47 +1,51 @@
-# Copyright (C) 2011 Freescale Semiconductor, Inc.
-# Jason Liu <r64343@freescale.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
 
-# image version
-
+/* image version */
 IMAGE_VERSION 2
 
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
 BOOT_FROM      sd
 
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type           Address        Value
-#
-# where:
-#      Addr-type register length (1,2 or 4 bytes)
-#      Address   absolute address of the register
-#      value     value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
 DATA 4 0x020e05a8 0x00000030
 DATA 4 0x020e05b0 0x00000030
 DATA 4 0x020e0524 0x00000030
@@ -154,7 +158,7 @@
 DATA 4 0x021b001c 0x00000000
 DATA 4 0x021b0404 0x00011006
 
-# set the default clock gate to save power
+/* set the default clock gate to save power */
 DATA 4 0x020c4068 0x00C03F3F
 DATA 4 0x020c406c 0x0030FC03
 DATA 4 0x020c4070 0x0FFFC000
@@ -163,8 +167,8 @@
 DATA 4 0x020c407c 0x0F0000C3
 DATA 4 0x020c4080 0x000003FF
 
-# enable AXI cache for VDOA/VPU/IPU
+/* enable AXI cache for VDOA/VPU/IPU */
 DATA 4 0x020e0010 0xF00000CF
-# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 DATA 4 0x020e0018 0x007F007F
 DATA 4 0x020e001c 0x007F007F
diff --git a/board/isee/igep0030/Makefile b/board/freescale/mx23evk/Makefile
similarity index 92%
copy from board/isee/igep0030/Makefile
copy to board/freescale/mx23evk/Makefile
index cbc03d4..7518d7b 100644
--- a/board/isee/igep0030/Makefile
+++ b/board/freescale/mx23evk/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -25,7 +25,11 @@
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= igep0030.o
+ifndef	CONFIG_SPL_BUILD
+COBJS	:= mx23evk.o
+else
+COBJS	:= spl_boot.o
+endif
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/mx23evk/mx23evk.c b/board/freescale/mx23evk/mx23evk.c
new file mode 100644
index 0000000..41ba303
--- /dev/null
+++ b/board/freescale/mx23evk/mx23evk.c
@@ -0,0 +1,83 @@
+/*
+ * Freescale MX23EVK board
+ *
+ * (C) Copyright 2013 O.S. Systems Software LTDA.
+ *
+ * Author: Otavio Salvador <otavio@ossystems.com.br>
+ *
+ * Based on m28evk.c:
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+	/* IO0 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK0, 480000);
+
+	/* SSP0 clock at 96MHz */
+	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	return mxs_dram_init();
+}
+
+int board_init(void)
+{
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+#ifdef	CONFIG_CMD_MMC
+static int mx23evk_mmc_wp(int id)
+{
+	if (id != 0) {
+		printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
+		return 1;
+	}
+
+	return gpio_get_value(MX23_PAD_PWM4__GPIO_1_30);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	/* Configure WP as input */
+	gpio_direction_input(MX23_PAD_PWM4__GPIO_1_30);
+
+	/* Configure MMC0 Power Enable */
+	gpio_direction_output(MX23_PAD_PWM3__GPIO_1_29, 0);
+
+	return mxsmmc_initialize(bis, 0, mx23evk_mmc_wp, NULL);
+}
+#endif
diff --git a/board/freescale/mx23evk/spl_boot.c b/board/freescale/mx23evk/spl_boot.c
new file mode 100644
index 0000000..6007433
--- /dev/null
+++ b/board/freescale/mx23evk/spl_boot.c
@@ -0,0 +1,104 @@
+/*
+ * Freescale MX23EVK Boot setup
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define	MUX_CONFIG_SSP1	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_16MA | MXS_PAD_PULLUP)
+
+const iomux_cfg_t iomux_setup[] = {
+	/* DUART */
+	MX23_PAD_PWM0__DUART_RX,
+	MX23_PAD_PWM1__DUART_TX,
+
+	/* EMI */
+	MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
+
+	MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+
+	MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+
+	/* MMC 0 */
+	MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP1,
+	MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP1,
+	MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP1,
+	MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP1,
+	MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP1,
+	MX23_PAD_SSP1_DETECT__SSP1_DETECT | MUX_CONFIG_SSP1,
+		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+	MX23_PAD_SSP1_SCK__SSP1_SCK |
+		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+	/* Write Protect Pin */
+	MX23_PAD_PWM4__GPIO_1_30 |
+		(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+	/* Slot Power Enable */
+	MX23_PAD_PWM3__GPIO_1_29 |
+		(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+};
+
+void board_init_ll(void)
+{
+	mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/board/freescale/mx25pdk/imximage.cfg b/board/freescale/mx25pdk/imximage.cfg
index f7af7ff..c42a283 100644
--- a/board/freescale/mx25pdk/imximage.cfg
+++ b/board/freescale/mx25pdk/imximage.cfg
@@ -1,46 +1,49 @@
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
 
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
 BOOT_FROM	sd
 
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type           Address        Value
-#
-# where:
-#	Addr-type register length (1,2 or 4 bytes)
-#	Address	  absolute address of the register
-#	value	  value to be stored in the register
-
-# EIM config-CS5 init -- CPLD
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+/* EIM config-CS5 init -- CPLD */
 DATA 4 0xB8002050 0x0000D843
 DATA 4 0xB8002054 0x22252521
 DATA 4 0xB8002058 0x22220A00
 
-# DDR2 init
+/* DDR2 init */
 DATA 4 0xB8001004 0x0076E83A
 DATA 4 0xB8001010 0x00000204
 DATA 4 0xB8001000 0x92210000
@@ -67,7 +70,7 @@
 
 DATA 4 0x53F80008 0x20034000
 
-# Enable the clocks
+/* Enable the clocks */
 DATA 4 0x53f8000c 0x1fffffff
 DATA 4 0x53f80010 0xffffffff
 DATA 4 0x53f80014 0xfdfff
diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c
index 6e719ff..de7231b 100644
--- a/board/freescale/mx28evk/mx28evk.c
+++ b/board/freescale/mx28evk/mx28evk.c
@@ -43,14 +43,14 @@
 int board_early_init_f(void)
 {
 	/* IO0 clock at 480MHz */
-	mx28_set_ioclk(MXC_IOCLK0, 480000);
+	mxs_set_ioclk(MXC_IOCLK0, 480000);
 	/* IO1 clock at 480MHz */
-	mx28_set_ioclk(MXC_IOCLK1, 480000);
+	mxs_set_ioclk(MXC_IOCLK1, 480000);
 
 	/* SSP0 clock at 96MHz */
-	mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
+	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
 	/* SSP2 clock at 160MHz */
-	mx28_set_sspclk(MXC_SSPCLK2, 160000, 0);
+	mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
 
 #ifdef	CONFIG_CMD_USB
 	mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
@@ -94,7 +94,7 @@
 	/* Configure MMC0 Power Enable */
 	gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
 
-	return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp);
+	return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp, NULL);
 }
 #endif
 
diff --git a/board/freescale/mx51evk/imximage.cfg b/board/freescale/mx51evk/imximage.cfg
index a875e8f..3e141ee 100644
--- a/board/freescale/mx51evk/imximage.cfg
+++ b/board/freescale/mx51evk/imximage.cfg
@@ -1,46 +1,50 @@
-#
-# (C Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
+/*
+ * (C Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
 
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
 BOOT_FROM	spi
 
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type           Address        Value
-#
-# where:
-#	Addr-type register length (1,2 or 4 bytes)
-#	Address	  absolute address of the register
-#	value	  value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
 
-# Setting IOMUXC
+/* Setting IOMUXC */
 DATA 4 0x73FA88a0 0x200
 DATA 4 0x73FA850c 0x20c5
 DATA 4 0x73FA8510 0x20c5
@@ -65,22 +69,24 @@
 DATA 4 0x73FA88ac 0x6
 DATA 4 0x73FA88b8 0x6
 
-# Setting DDR for micron
-# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
-# CAS=3 BL=4
-# ESDCTL_ESDCTL0
+/*
+ * Setting DDR for micron
+ * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+ * CAS=3 BL=4
+ */
+/* ESDCTL_ESDCTL0 */
 DATA 4 0x83FD9000 0x82a20000
-# ESDCTL_ESDCTL1
+/* ESDCTL_ESDCTL1 */
 DATA 4 0x83FD9008 0x82a20000
-# ESDCTL_ESDMISC
+/* ESDCTL_ESDMISC */
 DATA 4 0x83FD9010 0x000ad0d0
-# ESDCTL_ESDCFG0
+/* ESDCTL_ESDCFG0 */
 DATA 4 0x83FD9004 0x333574aa
-# ESDCTL_ESDCFG1
+/* ESDCTL_ESDCFG1 */
 DATA 4 0x83FD900C 0x333574aa
 
-# Init DRAM on CS0
-# ESDCTL_ESDSCR
+/* Init DRAM on CS0 */
+/* ESDCTL_ESDSCR */
 DATA 4 0x83FD9014 0x04008008
 DATA 4 0x83FD9014 0x0000801a
 DATA 4 0x83FD9014 0x0000801b
@@ -94,7 +100,7 @@
 DATA 4 0x83FD9014 0x00408019
 DATA 4 0x83FD9014 0x00008000
 
-# Init DRAM on CS1
+/* Init DRAM on CS1 */
 DATA 4 0x83FD9014 0x0400800c
 DATA 4 0x83FD9014 0x0000801e
 DATA 4 0x83FD9014 0x0000801f
@@ -108,12 +114,12 @@
 DATA 4 0x83FD9014 0x0040801d
 DATA 4 0x83FD9014 0x00008004
 
-# Write to CTL0
+/* Write to CTL0 */
 DATA 4 0x83FD9000 0xb2a20000
-# Write to CTL1
+/* Write to CTL1 */
 DATA 4 0x83FD9008 0xb2a20000
-# ESDMISC
+/* ESDMISC */
 DATA 4 0x83FD9010 0x000ad6d0
-#ESDCTL_ESDCDLYGD
+/* ESDCTL_ESDCDLYGD */
 DATA 4 0x83FD9034 0x90000000
 DATA 4 0x83FD9014 0x00000000
diff --git a/board/freescale/mx53ard/imximage_dd3.cfg b/board/freescale/mx53ard/imximage_dd3.cfg
index 614d29e..4633e4d 100644
--- a/board/freescale/mx53ard/imximage_dd3.cfg
+++ b/board/freescale/mx53ard/imximage_dd3.cfg
@@ -1,48 +1,51 @@
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
 
-# image version
-
+/* image version */
 IMAGE_VERSION 2
 
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
 BOOT_FROM	sd
 
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type           Address        Value
-#
-# where:
-#	Addr-type register length (1,2 or 4 bytes)
-#	Address	  absolute address of the register
-#	value	  value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
 DATA 4 0x53fa8554 0x00300000
 DATA 4 0x53fa8558 0x00300040
 DATA 4 0x53fa8560 0x00300000
diff --git a/board/freescale/mx53evk/imximage.cfg b/board/freescale/mx53evk/imximage.cfg
index 915fb2c..1cd61d5 100644
--- a/board/freescale/mx53evk/imximage.cfg
+++ b/board/freescale/mx53evk/imximage.cfg
@@ -1,50 +1,52 @@
-#
-# (C Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
+/*
+ * (C Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
 
-# image version
-
+/* image version */
 IMAGE_VERSION 2
 
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
 BOOT_FROM	sd
 
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type           Address        Value
-#
-# where:
-#	Addr-type register length (1,2 or 4 bytes)
-#	Address	  absolute address of the register
-#	value	  value to be stored in the register
-
-# Setting IOMUXC
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+/* Setting IOMUXC */
 DATA 4 0x53fa8554 0x00200000
 DATA 4 0x53fa8560 0x00200000
 DATA 4 0x53fa8594 0x00200000
diff --git a/board/freescale/mx53loco/imximage.cfg b/board/freescale/mx53loco/imximage.cfg
index 2ce5f8d..e6b90c1 100644
--- a/board/freescale/mx53loco/imximage.cfg
+++ b/board/freescale/mx53loco/imximage.cfg
@@ -1,48 +1,51 @@
-# Copyright (C) 2011 Freescale Semiconductor, Inc.
-# Jason Liu <r64343@freescale.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
 
-# image version
-
+/* image version */
 IMAGE_VERSION 2
 
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
 BOOT_FROM	sd
 
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type           Address        Value
-#
-# where:
-#	Addr-type register length (1,2 or 4 bytes)
-#	Address	  absolute address of the register
-#	value	  value to be stored in the register
-
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
 DATA 4 0x53fa8554 0x00300000
 DATA 4 0x53fa8558 0x00300040
 DATA 4 0x53fa8560 0x00300000
diff --git a/board/freescale/mx53smd/imximage.cfg b/board/freescale/mx53smd/imximage.cfg
index 614d29e..4633e4d 100644
--- a/board/freescale/mx53smd/imximage.cfg
+++ b/board/freescale/mx53smd/imximage.cfg
@@ -1,48 +1,51 @@
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
 
-# image version
-
+/* image version */
 IMAGE_VERSION 2
 
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
 BOOT_FROM	sd
 
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type           Address        Value
-#
-# where:
-#	Addr-type register length (1,2 or 4 bytes)
-#	Address	  absolute address of the register
-#	value	  value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
 DATA 4 0x53fa8554 0x00300000
 DATA 4 0x53fa8558 0x00300040
 DATA 4 0x53fa8560 0x00300000
diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg
index bf941a3..4ed211e 100644
--- a/board/freescale/mx6qarm2/imximage.cfg
+++ b/board/freescale/mx6qarm2/imximage.cfg
@@ -1,47 +1,51 @@
-# Copyright (C) 2011 Freescale Semiconductor, Inc.
-# Jason Liu <r64343@freescale.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
 
-# image version
-
+/* image version */
 IMAGE_VERSION 2
 
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
 BOOT_FROM	sd
 
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type           Address        Value
-#
-# where:
-#	Addr-type register length (1,2 or 4 bytes)
-#	Address	  absolute address of the register
-#	value	  value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
 DATA 4 0x020e05a8 0x00000030
 DATA 4 0x020e05b0 0x00000030
 DATA 4 0x020e0524 0x00000030
@@ -166,8 +170,8 @@
 DATA 4 0x020c407c 0x0F0000C3
 DATA 4 0x020c4080 0x000003FF
 
-# enable AXI cache for VDOA/VPU/IPU
+/* enable AXI cache for VDOA/VPU/IPU */
 DATA 4 0x020e0010 0xF00000CF
-# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 DATA 4 0x020e0018 0x007F007F
 DATA 4 0x020e001c 0x007F007F
diff --git a/board/freescale/mx6qsabreauto/imximage.cfg b/board/freescale/mx6qsabreauto/imximage.cfg
index d909aa8..bbff813 100644
--- a/board/freescale/mx6qsabreauto/imximage.cfg
+++ b/board/freescale/mx6qsabreauto/imximage.cfg
@@ -1,46 +1,50 @@
-# Copyright (C) 2012 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
 
 IMAGE_VERSION 2
 
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
 BOOT_FROM	sd
 
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type           Address        Value
-#
-# where:
-#	Addr-type register length (1,2 or 4 bytes)
-#	Address	  absolute address of the register
-#	value	  value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
 DATA 4 0x020e05a8 0x00000028
 DATA 4 0x020e05b0 0x00000028
 DATA 4 0x020e0524 0x00000028
@@ -126,7 +130,7 @@
 DATA 4 0x021b0818 0x00000007
 DATA 4 0x021b4818 0x00000007
 
-# Calibration values based on ARD and 528MHz
+/* Calibration values based on ARD and 528MHz */
 DATA 4 0x021b083c 0x434B0358
 DATA 4 0x021b0840 0x033D033C
 DATA 4 0x021b483c 0x03520362
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index af6f917..f010d0c 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -33,6 +33,7 @@
 #include <asm/imx-common/boot_mode.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
+#include <malloc.h>
 #include <micrel.h>
 #include <miiphy.h>
 #include <netdev.h>
@@ -338,14 +339,31 @@
 
 int board_eth_init(bd_t *bis)
 {
+	uint32_t base = IMX_FEC_BASE;
+	struct mii_dev *bus = NULL;
+	struct phy_device *phydev = NULL;
 	int ret;
 
 	setup_iomux_enet();
 
-	ret = cpu_eth_init(bis);
-	if (ret)
+#ifdef CONFIG_FEC_MXC
+	bus = fec_get_miibus(base, -1);
+	if (!bus)
+		return 0;
+	/* scan phy 4,5,6,7 */
+	phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
+	if (!phydev) {
+		free(bus);
+		return 0;
+	}
+	printf("using phy at %d\n", phydev->addr);
+	ret  = fec_probe(bis, -1, base, bus, phydev);
+	if (ret) {
 		printf("FEC MXC: %s:failed\n", __func__);
-
+		free(phydev);
+		free(bus);
+	}
+#endif
 	return 0;
 }
 
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg
index 38fa760..21ff6d6 100644
--- a/board/genesi/mx51_efikamx/imximage_mx.cfg
+++ b/board/genesi/mx51_efikamx/imximage_mx.cfg
@@ -1,52 +1,58 @@
-#
-# Copyright (C) 2009 Pegatron Corporation
-# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
-# Copyright (C) 2009-2012 Genesi USA, Inc.
-#
-# BASED ON: imx51evk
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
+/*
+ * Copyright (C) 2009 Pegatron Corporation
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2009-2012 Genesi USA, Inc.
+ *
+ * BASED ON: imx51evk
+ *
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
 
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
 BOOT_FROM	spi
 
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type           Address        Value
-#
-# where:
-#	Addr-type register length (1,2 or 4 bytes)
-#	Address	  absolute address of the register
-#	value	  value to be stored in the register
-
-# Essential GPIO settings to be done as early as possible
-# PCBIDn pad settings are all the defaults except #2 which needs HVE off
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+/*
+ * Essential GPIO settings to be done as early as possible
+ * PCBIDn pad settings are all the defaults except #2 which needs HVE off
+ */
 DATA 4 0x73fa8134 0x3			# PCBID0 ALT3 GPIO 3_16
 DATA 4 0x73fa8130 0x3			# PCBID1 ALT3 GPIO 3_17
 DATA 4 0x73fa8128 0x3			# PCBID2 ALT3 GPIO 3_11
@@ -55,7 +61,7 @@
 DATA 4 0x73fa81c4 0x3			# LED1 ALT3 GPIO 3_14
 DATA 4 0x73fa81c8 0x3			# LED2 ALT3 GPIO 3_15
 
-# DDR bus IOMUX PAD settings
+/* DDR bus IOMUX PAD settings */
 DATA 4 0x73fa850c 0x20c5		# SDODT1
 DATA 4 0x73fa8510 0x20c5		# SDODT0
 DATA 4 0x73fa84ac 0xc5			# SDWE
@@ -72,22 +78,24 @@
 DATA 4 0x73fa84dc 0xc5			# DRAM_DQM2
 DATA 4 0x73fa84e0 0xc5			# DRAM_DQM3
 
-# Setting DDR for micron
-# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
-# CAS=3 BL=4
-# ESDCTL_ESDCTL0
+/*
+ * Setting DDR for micron
+ * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+ * CAS=3 BL=4
+ */
+/* ESDCTL_ESDCTL0 */
 DATA 4 0x83fd9000 0x82a20000
-# ESDCTL_ESDCTL1
+/* ESDCTL_ESDCTL1 */
 DATA 4 0x83fd9008 0x82a20000
-# ESDCTL_ESDMISC
+/* ESDCTL_ESDMISC */
 DATA 4 0x83fd9010 0xcaaaf6d0
-# ESDCTL_ESDCFG0
+/* ESDCTL_ESDCFG0 */
 DATA 4 0x83fd9004 0x3f3574aa
-# ESDCTL_ESDCFG1
+/* ESDCTL_ESDCFG1 */
 DATA 4 0x83fd900c 0x3f3574aa
 
-# Init DRAM on CS0
-# ESDCTL_ESDSCR
+/* Init DRAM on CS0 */
+/* ESDCTL_ESDSCR */
 DATA 4 0x83fd9014 0x04008008
 DATA 4 0x83fd9014 0x0000801a
 DATA 4 0x83fd9014 0x0000801b
@@ -101,7 +109,7 @@
 DATA 4 0x83fd9014 0x00408019
 DATA 4 0x83fd9014 0x00008000
 
-# Init DRAM on CS1
+/* Init DRAM on CS1 */
 DATA 4 0x83fd9014 0x0400800c
 DATA 4 0x83fd9014 0x0000801e
 DATA 4 0x83fd9014 0x0000801f
@@ -115,12 +123,12 @@
 DATA 4 0x83fd9014 0x0040801d
 DATA 4 0x83fd9014 0x00008004
 
-# Write to CTL0
+/* Write to CTL0 */
 DATA 4 0x83fd9000 0xb2a20000
-# Write to CTL1
+/* Write to CTL1 */
 DATA 4 0x83fd9008 0xb2a20000
-# ESDMISC
+/* ESDMISC */
 DATA 4 0x83fd9010 0x000ad6d0
-#ESDCTL_ESDCDLYGD
+/* ESDCTL_ESDCDLYGD */
 DATA 4 0x83fd9034 0x90000000
 DATA 4 0x83fd9014 0x00000000
diff --git a/board/genesi/mx51_efikamx/imximage_sb.cfg b/board/genesi/mx51_efikamx/imximage_sb.cfg
index 26d259f..7ddd0b1 100644
--- a/board/genesi/mx51_efikamx/imximage_sb.cfg
+++ b/board/genesi/mx51_efikamx/imximage_sb.cfg
@@ -1,51 +1,55 @@
-#
-# Copyright (C) 2009 Pegatron Corporation
-# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
-# Copyright (C) 2009-2012 Genesi USA, Inc.
-#
-# BASED ON: imx51evk
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
+/*
+ * Copyright (C) 2009 Pegatron Corporation
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2009-2012 Genesi USA, Inc.
+ *
+ * BASED ON: imx51evk
+ *
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
 
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
 BOOT_FROM	spi
 
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type           Address        Value
-#
-# where:
-#	Addr-type register length (1,2 or 4 bytes)
-#	Address	  absolute address of the register
-#	value	  value to be stored in the register
-
-# DDR bus IOMUX PAD settings
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+*/
+/* DDR bus IOMUX PAD settings */
 DATA 4 0x73fa88a0 0x200		# GRP_INMODE1
 DATA 4 0x73fa850c 0x20c5	# SDODT1
 DATA 4 0x73fa8510 0x20c5	# SDODT0
@@ -62,22 +66,24 @@
 DATA 4 0x73fa84cc 0xe5		# DRAM_CS0
 DATA 4 0x73fa84d0 0xe4		# DRAM_CS1
 
-# Setting DDR for micron
-# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
-# CAS=3 BL=4
-# ESDCTL_ESDCTL0
+/*
+ * Setting DDR for micron
+ * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+ * CAS=3 BL=4
+ */
+/* ESDCTL_ESDCTL0 */
 DATA 4 0x83fd9000 0x82a20000
-# ESDCTL_ESDCTL1
+/* ESDCTL_ESDCTL1 */
 DATA 4 0x83fd9008 0x82a20000
-# ESDCTL_ESDMISC
+/* ESDCTL_ESDMISC */
 DATA 4 0x83fd9010 0xcaaaf6d0
-# ESDCTL_ESDCFG0
+/* ESDCTL_ESDCFG0 */
 DATA 4 0x83fd9004 0x333574aa
-# ESDCTL_ESDCFG1
+/* ESDCTL_ESDCFG1 */
 DATA 4 0x83fd900c 0x333574aa
 
-# Init DRAM on CS0
-# ESDCTL_ESDSCR
+/* Init DRAM on CS0 */
+/* ESDCTL_ESDSCR */
 DATA 4 0x83fd9014 0x04008008
 DATA 4 0x83fd9014 0x0000801a
 DATA 4 0x83fd9014 0x0000801b
@@ -91,7 +97,7 @@
 DATA 4 0x83fd9014 0x00408019
 DATA 4 0x83fd9014 0x00008000
 
-# Init DRAM on CS1
+/* Init DRAM on CS1 */
 DATA 4 0x83fd9014 0x0400800c
 DATA 4 0x83fd9014 0x0000801e
 DATA 4 0x83fd9014 0x0000801f
@@ -105,12 +111,12 @@
 DATA 4 0x83fd9014 0x0042801d
 DATA 4 0x83fd9014 0x00008004
 
-# Write to CTL0
+/* Write to CTL0 */
 DATA 4 0x83fd9000 0xb2a20000
-# Write to CTL1
+/* Write to CTL1 */
 DATA 4 0x83fd9008 0xb2a20000
-# ESDMISC
+/* ESDMISC */
 DATA 4 0x83fd9010 0xcaaaf6d0
-#ESDCTL_ESDCDLYGD
+/* ESDCTL_ESDCDLYGD */
 DATA 4 0x83fd9034 0x90000000
 DATA 4 0x83fd9014 0x00000000
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index f41bf05..09cd45d 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -88,5 +88,6 @@
 void reset_cpu(ulong addr)
 {
 	writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
-	asm("	wfi");
+
+	wfi();
 }
diff --git a/board/isee/igep0020/Makefile b/board/isee/igep0020/Makefile
deleted file mode 100644
index 00463e1..0000000
--- a/board/isee/igep0020/Makefile
+++ /dev/null
@@ -1,43 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= igep0020.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/isee/igep0020/igep0020.h b/board/isee/igep0020/igep0020.h
deleted file mode 100644
index 3335ecc..0000000
--- a/board/isee/igep0020/igep0020.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * (C) Copyright 2010
- * ISEE 2007 SL, <www.iseebcn.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _IGEP0020_H_
-#define _IGEP0020_H_
-
-const omap3_sysinfo sysinfo = {
-	DDR_STACKED,
-	"IGEP v2 board",
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
-	"ONENAND",
-#else
-	"NAND",
-#endif
-};
-
-static void setup_net_chip(void);
-
-/*
- * IEN  - Input Enable
- * IDIS - Input Disable
- * PTD  - Pull type Down
- * PTU  - Pull type Up
- * DIS  - Pull type selection is inactive
- * EN   - Pull type selection is active
- * M0   - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_DEFAULT()\
-	MUX_VAL(CP(SDRC_D0),        (IEN  | PTD | DIS | M0)) /* SDRC_D0 */\
-	MUX_VAL(CP(SDRC_D1),        (IEN  | PTD | DIS | M0)) /* SDRC_D1 */\
-	MUX_VAL(CP(SDRC_D2),        (IEN  | PTD | DIS | M0)) /* SDRC_D2 */\
-	MUX_VAL(CP(SDRC_D3),        (IEN  | PTD | DIS | M0)) /* SDRC_D3 */\
-	MUX_VAL(CP(SDRC_D4),        (IEN  | PTD | DIS | M0)) /* SDRC_D4 */\
-	MUX_VAL(CP(SDRC_D5),        (IEN  | PTD | DIS | M0)) /* SDRC_D5 */\
-	MUX_VAL(CP(SDRC_D6),        (IEN  | PTD | DIS | M0)) /* SDRC_D6 */\
-	MUX_VAL(CP(SDRC_D7),        (IEN  | PTD | DIS | M0)) /* SDRC_D7 */\
-	MUX_VAL(CP(SDRC_D8),        (IEN  | PTD | DIS | M0)) /* SDRC_D8 */\
-	MUX_VAL(CP(SDRC_D9),        (IEN  | PTD | DIS | M0)) /* SDRC_D9 */\
-	MUX_VAL(CP(SDRC_D10),       (IEN  | PTD | DIS | M0)) /* SDRC_D10 */\
-	MUX_VAL(CP(SDRC_D11),       (IEN  | PTD | DIS | M0)) /* SDRC_D11 */\
-	MUX_VAL(CP(SDRC_D12),       (IEN  | PTD | DIS | M0)) /* SDRC_D12 */\
-	MUX_VAL(CP(SDRC_D13),       (IEN  | PTD | DIS | M0)) /* SDRC_D13 */\
-	MUX_VAL(CP(SDRC_D14),       (IEN  | PTD | DIS | M0)) /* SDRC_D14 */\
-	MUX_VAL(CP(SDRC_D15),       (IEN  | PTD | DIS | M0)) /* SDRC_D15 */\
-	MUX_VAL(CP(SDRC_D16),       (IEN  | PTD | DIS | M0)) /* SDRC_D16 */\
-	MUX_VAL(CP(SDRC_D17),       (IEN  | PTD | DIS | M0)) /* SDRC_D17 */\
-	MUX_VAL(CP(SDRC_D18),       (IEN  | PTD | DIS | M0)) /* SDRC_D18 */\
-	MUX_VAL(CP(SDRC_D19),       (IEN  | PTD | DIS | M0)) /* SDRC_D19 */\
-	MUX_VAL(CP(SDRC_D20),       (IEN  | PTD | DIS | M0)) /* SDRC_D20 */\
-	MUX_VAL(CP(SDRC_D21),       (IEN  | PTD | DIS | M0)) /* SDRC_D21 */\
-	MUX_VAL(CP(SDRC_D22),       (IEN  | PTD | DIS | M0)) /* SDRC_D22 */\
-	MUX_VAL(CP(SDRC_D23),       (IEN  | PTD | DIS | M0)) /* SDRC_D23 */\
-	MUX_VAL(CP(SDRC_D24),       (IEN  | PTD | DIS | M0)) /* SDRC_D24 */\
-	MUX_VAL(CP(SDRC_D25),       (IEN  | PTD | DIS | M0)) /* SDRC_D25 */\
-	MUX_VAL(CP(SDRC_D26),       (IEN  | PTD | DIS | M0)) /* SDRC_D26 */\
-	MUX_VAL(CP(SDRC_D27),       (IEN  | PTD | DIS | M0)) /* SDRC_D27 */\
-	MUX_VAL(CP(SDRC_D28),       (IEN  | PTD | DIS | M0)) /* SDRC_D28 */\
-	MUX_VAL(CP(SDRC_D29),       (IEN  | PTD | DIS | M0)) /* SDRC_D29 */\
-	MUX_VAL(CP(SDRC_D30),       (IEN  | PTD | DIS | M0)) /* SDRC_D30 */\
-	MUX_VAL(CP(SDRC_D31),       (IEN  | PTD | DIS | M0)) /* SDRC_D31 */\
-	MUX_VAL(CP(SDRC_CLK),       (IEN  | PTD | DIS | M0)) /* SDRC_CLK */\
-	MUX_VAL(CP(SDRC_DQS0),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS0 */\
-	MUX_VAL(CP(SDRC_DQS1),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS1 */\
-	MUX_VAL(CP(SDRC_DQS2),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS2 */\
-	MUX_VAL(CP(SDRC_DQS3),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS3 */\
-	MUX_VAL(CP(GPMC_A1),        (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
-	MUX_VAL(CP(GPMC_A2),        (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
-	MUX_VAL(CP(GPMC_A3),        (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
-	MUX_VAL(CP(GPMC_A4),        (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
-	MUX_VAL(CP(GPMC_A5),        (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
-	MUX_VAL(CP(GPMC_A6),        (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
-	MUX_VAL(CP(GPMC_A7),        (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
-	MUX_VAL(CP(GPMC_A8),        (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
-	MUX_VAL(CP(GPMC_A9),        (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
-	MUX_VAL(CP(GPMC_A10),       (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
-	MUX_VAL(CP(GPMC_D0),        (IEN  | PTD | DIS | M0)) /* GPMC_D0 */\
-	MUX_VAL(CP(GPMC_D1),        (IEN  | PTD | DIS | M0)) /* GPMC_D1 */\
-	MUX_VAL(CP(GPMC_D2),        (IEN  | PTD | DIS | M0)) /* GPMC_D2 */\
-	MUX_VAL(CP(GPMC_D3),        (IEN  | PTD | DIS | M0)) /* GPMC_D3 */\
-	MUX_VAL(CP(GPMC_D4),        (IEN  | PTD | DIS | M0)) /* GPMC_D4 */\
-	MUX_VAL(CP(GPMC_D5),        (IEN  | PTD | DIS | M0)) /* GPMC_D5 */\
-	MUX_VAL(CP(GPMC_D6),        (IEN  | PTD | DIS | M0)) /* GPMC_D6 */\
-	MUX_VAL(CP(GPMC_D7),        (IEN  | PTD | DIS | M0)) /* GPMC_D7 */\
-	MUX_VAL(CP(GPMC_D8),        (IEN  | PTD | DIS | M0)) /* GPMC_D8 */\
-	MUX_VAL(CP(GPMC_D9),        (IEN  | PTD | DIS | M0)) /* GPMC_D9 */\
-	MUX_VAL(CP(GPMC_D10),       (IEN  | PTD | DIS | M0)) /* GPMC_D10 */\
-	MUX_VAL(CP(GPMC_D11),       (IEN  | PTD | DIS | M0)) /* GPMC_D11 */\
-	MUX_VAL(CP(GPMC_D12),       (IEN  | PTD | DIS | M0)) /* GPMC_D12 */\
-	MUX_VAL(CP(GPMC_D13),       (IEN  | PTD | DIS | M0)) /* GPMC_D13 */\
-	MUX_VAL(CP(GPMC_D14),       (IEN  | PTD | DIS | M0)) /* GPMC_D14 */\
-	MUX_VAL(CP(GPMC_D15),       (IEN  | PTD | DIS | M0)) /* GPMC_D15 */\
-	MUX_VAL(CP(GPMC_NCS0),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS0 */\
-	MUX_VAL(CP(GPMC_NCS1),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS1 */\
-	MUX_VAL(CP(GPMC_NCS2),      (IDIS | PTU | EN  | M0)) /* GPIO_nCS2 */\
-	MUX_VAL(CP(GPMC_NCS3),      (IDIS | PTU | EN  | M0)) /* GPIO_nCS3 */\
-	MUX_VAL(CP(GPMC_NCS4),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS4 */\
-	MUX_VAL(CP(GPMC_NCS5),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS5 */\
-	MUX_VAL(CP(GPMC_NCS6),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS6 */\
-	MUX_VAL(CP(GPMC_NCS7),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS7 */\
-	MUX_VAL(CP(GPMC_CLK),       (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
-	MUX_VAL(CP(GPMC_NADV_ALE),  (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
-	MUX_VAL(CP(GPMC_NOE),       (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
-	MUX_VAL(CP(GPMC_NWE),       (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
-	MUX_VAL(CP(GPMC_NBE0_CLE),  (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
-	MUX_VAL(CP(GPMC_NBE1),      (IEN  | PTD | DIS | M0)) /* GPMC_nBE1 */\
-	MUX_VAL(CP(GPMC_NWP),       (IEN  | PTD | DIS | M0)) /* GPMC_nWP */\
-	MUX_VAL(CP(GPMC_WAIT0),     (IEN  | PTU | EN  | M0)) /* GPMC_WAIT0 */\
-	MUX_VAL(CP(GPMC_WAIT2),     (IEN  | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
-	MUX_VAL(CP(MMC1_CLK),       (IDIS | PTU | EN  | M0)) /* MMC1_CLK */\
-	MUX_VAL(CP(MMC1_CMD),       (IEN  | PTU | EN  | M0)) /* MMC1_CMD */\
-	MUX_VAL(CP(MMC1_DAT0),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT0 */\
-	MUX_VAL(CP(MMC1_DAT1),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT1 */\
-	MUX_VAL(CP(MMC1_DAT2),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT2 */\
-	MUX_VAL(CP(MMC1_DAT3),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT3 */\
-	MUX_VAL(CP(UART3_TX_IRTX),  (IDIS | PTD | DIS | M0)) /* UART3_TX */\
-	MUX_VAL(CP(UART3_RX_IRRX),  (IEN  | PTD | DIS | M0)) /* UART3_RX */\
-	MUX_VAL(CP(I2C1_SCL),       (IEN  | PTU | EN  | M0)) /* I2C1_SCL */\
-	MUX_VAL(CP(I2C1_SDA),       (IEN  | PTU | EN  | M0)) /* I2C1_SDA */\
-	MUX_VAL(CP(I2C4_SCL),       (IEN  | PTU | EN  | M0)) /* I2C4_SCL */\
-	MUX_VAL(CP(I2C4_SDA),       (IEN  | PTU | EN  | M0)) /* I2C4_SDA */\
-	MUX_VAL(CP(SYS_32K),        (IEN  | PTD | DIS | M0)) /* SYS_32K */\
-	MUX_VAL(CP(SYS_BOOT0),      (IEN  | PTD | DIS | M4)) /* GPIO_2 */\
-	MUX_VAL(CP(SYS_BOOT1),      (IEN  | PTD | DIS | M4)) /* GPIO_3 */\
-	MUX_VAL(CP(SYS_BOOT2),      (IEN  | PTD | DIS | M4)) /* GPIO_4 */\
-	MUX_VAL(CP(SYS_BOOT3),      (IEN  | PTD | DIS | M4)) /* GPIO_5 */\
-	MUX_VAL(CP(SYS_BOOT4),      (IEN  | PTD | DIS | M4)) /* GPIO_6 */\
-	MUX_VAL(CP(SYS_BOOT5),      (IEN  | PTD | DIS | M4)) /* GPIO_7 */\
-	MUX_VAL(CP(SYS_BOOT6),      (IEN  | PTD | DIS | M4)) /* GPIO_8 */\
-	MUX_VAL(CP(SDRC_CKE0),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE0 */\
-	MUX_VAL(CP(SDRC_CKE1),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE1 */
-#endif
diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c
deleted file mode 100644
index a41e752..0000000
--- a/board/isee/igep0030/igep0030.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * (C) Copyright 2010
- * ISEE 2007 SL, <www.iseebcn.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
-#include "igep0030.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
-	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-	return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * Routine: omap_rev_string
- * Description: For SPL builds output board rev
- */
-void omap_rev_string(void)
-{
-}
-
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on both banks.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
-	timings->mr = MICRON_V_MR_165;
-#ifdef CONFIG_BOOT_NAND
-	timings->mcfg = MICRON_V_MCFG_200(256 << 20);
-	timings->ctrla = MICRON_V_ACTIMA_200;
-	timings->ctrlb = MICRON_V_ACTIMB_200;
-	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
-#else
-	if (get_cpu_family() == CPU_OMAP34XX) {
-		timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
-		timings->ctrla = NUMONYX_V_ACTIMA_165;
-		timings->ctrlb = NUMONYX_V_ACTIMB_165;
-		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
-
-	} else {
-		timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
-		timings->ctrla = NUMONYX_V_ACTIMA_200;
-		timings->ctrlb = NUMONYX_V_ACTIMB_200;
-		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
-	}
-#endif
-}
-#endif
-
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
-{
-	omap_mmc_init(0, 0, 0);
-	return 0;
-}
-#endif
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
-	twl4030_power_init();
-
-	dieid_num_r();
-
-	return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *		hardware. Many pins need to be moved from protect to primary
- *		mode.
- */
-void set_muxconf_regs(void)
-{
-	MUX_DEFAULT();
-}
diff --git a/board/isee/igep0030/Makefile b/board/isee/igep00x0/Makefile
similarity index 98%
rename from board/isee/igep0030/Makefile
rename to board/isee/igep00x0/Makefile
index cbc03d4..f595954 100644
--- a/board/isee/igep0030/Makefile
+++ b/board/isee/igep00x0/Makefile
@@ -25,7 +25,7 @@
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= igep0030.o
+COBJS	:= igep00x0.o
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep00x0/igep00x0.c
similarity index 85%
rename from board/isee/igep0020/igep0020.c
rename to board/isee/igep00x0/igep00x0.c
index a0f2aa3..49fcf34 100644
--- a/board/isee/igep0020/igep0020.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -21,29 +21,31 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
-#include <netdev.h>
 #include <twl4030.h>
-#include <asm/io.h>
+#include <netdev.h>
 #include <asm/gpio.h>
+#include <asm/arch/omap_gpmc.h>
+#include <asm/io.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/omap_gpmc.h>
 #include <asm/mach-types.h>
-#include "igep0020.h"
+#include "igep00x0.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_CMD_NET)
 /* GPMC definitions for LAN9221 chips */
 static const u32 gpmc_lan_config[] = {
-    NET_LAN9221_GPMC_CONFIG1,
-    NET_LAN9221_GPMC_CONFIG2,
-    NET_LAN9221_GPMC_CONFIG3,
-    NET_LAN9221_GPMC_CONFIG4,
-    NET_LAN9221_GPMC_CONFIG5,
-    NET_LAN9221_GPMC_CONFIG6,
+	NET_LAN9221_GPMC_CONFIG1,
+	NET_LAN9221_GPMC_CONFIG2,
+	NET_LAN9221_GPMC_CONFIG3,
+	NET_LAN9221_GPMC_CONFIG4,
+	NET_LAN9221_GPMC_CONFIG5,
+	NET_LAN9221_GPMC_CONFIG6,
 };
+#endif
 
 /*
  * Routine: board_init
@@ -58,6 +60,19 @@
 	return 0;
 }
 
+#if defined(CONFIG_SHOW_BOOT_PROGRESS) && !defined(CONFIG_SPL_BUILD)
+void show_boot_progress(int val)
+{
+	if (val < 0) {
+		/* something went wrong */
+		return;
+	}
+
+	if (!gpio_request(IGEP00X0_GPIO_LED, ""))
+		gpio_direction_output(IGEP00X0_GPIO_LED, 1);
+}
+#endif
+
 #ifdef CONFIG_SPL_BUILD
 /*
  * Routine: omap_rev_string
@@ -97,12 +112,12 @@
 }
 #endif
 
+#if defined(CONFIG_CMD_NET)
 /*
  * Routine: setup_net_chip
  * Description: Setting up the configuration GPMC registers specific to the
  *		Ethernet hardware.
  */
-#if defined(CONFIG_CMD_NET)
 static void setup_net_chip(void)
 {
 	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
@@ -128,6 +143,8 @@
 		gpio_set_value(64, 1);
 	}
 }
+#else
+static inline void setup_net_chip(void) {}
 #endif
 
 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
@@ -146,9 +163,7 @@
 {
 	twl4030_power_init();
 
-#if defined(CONFIG_CMD_NET)
 	setup_net_chip();
-#endif
 
 	dieid_num_r();
 
@@ -164,8 +179,17 @@
 void set_muxconf_regs(void)
 {
 	MUX_DEFAULT();
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
+	MUX_IGEP0020();
+#endif
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
+	MUX_IGEP0030();
+#endif
 }
 
+#if defined(CONFIG_CMD_NET)
 int board_eth_init(bd_t *bis)
 {
 	int rc = 0;
@@ -174,3 +198,4 @@
 #endif
 	return rc;
 }
+#endif
diff --git a/board/isee/igep0030/igep0030.h b/board/isee/igep00x0/igep00x0.h
similarity index 93%
rename from board/isee/igep0030/igep0030.h
rename to board/isee/igep00x0/igep00x0.h
index a93339d..ea1e9ac 100644
--- a/board/isee/igep0030/igep0030.h
+++ b/board/isee/igep00x0/igep00x0.h
@@ -20,12 +20,25 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
-#ifndef _IGEP0030_H_
-#define _IGEP0030_H_
+#ifndef _IGEP00X0_H_
+#define _IGEP00X0_H_
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
+#define IGEP00X0_GPIO_LED 27
+#endif
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
+#define IGEP00X0_GPIO_LED 16
+#endif
 
 const omap3_sysinfo sysinfo = {
 	DDR_STACKED,
-	"OMAP3 IGEP module",
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
+	"OMAP3 IGEP v2 board",
+#endif
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
+	"OMAP3 IGEP COM Module",
+#endif
 #if defined(CONFIG_ENV_IS_IN_ONENAND)
 	"ONENAND",
 #else
@@ -33,6 +46,8 @@
 #endif
 };
 
+static void setup_net_chip(void);
+
 /*
  * IEN  - Input Enable
  * IDIS - Input Disable
@@ -43,7 +58,6 @@
  * M0   - Mode 0
  * The commented string gives the final mux configuration for that pin
  */
-
 #define MUX_DEFAULT()\
 	MUX_VAL(CP(SDRC_D0),        (IEN  | PTD | DIS | M0)) /* SDRC_D0 */\
 	MUX_VAL(CP(SDRC_D1),        (IEN  | PTD | DIS | M0)) /* SDRC_D1 */\
@@ -117,10 +131,10 @@
 	MUX_VAL(CP(GPMC_NCS6),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS6 */\
 	MUX_VAL(CP(GPMC_NCS7),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS7 */\
 	MUX_VAL(CP(GPMC_CLK),       (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
-	MUX_VAL(CP(GPMC_NADV_ALE),  (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE*/\
+	MUX_VAL(CP(GPMC_NADV_ALE),  (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
 	MUX_VAL(CP(GPMC_NOE),       (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
 	MUX_VAL(CP(GPMC_NWE),       (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
-	MUX_VAL(CP(GPMC_NBE0_CLE),  (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE*/\
+	MUX_VAL(CP(GPMC_NBE0_CLE),  (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
 	MUX_VAL(CP(GPMC_NBE1),      (IEN  | PTD | DIS | M0)) /* GPMC_nBE1 */\
 	MUX_VAL(CP(GPMC_NWP),       (IEN  | PTD | DIS | M0)) /* GPMC_nWP */\
 	MUX_VAL(CP(GPMC_WAIT0),     (IEN  | PTU | EN  | M0)) /* GPMC_WAIT0 */\
@@ -130,8 +144,6 @@
 	MUX_VAL(CP(MMC1_DAT1),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT1 */\
 	MUX_VAL(CP(MMC1_DAT2),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT2 */\
 	MUX_VAL(CP(MMC1_DAT3),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT3 */\
-	MUX_VAL(CP(UART1_TX),       (IDIS | PTD | DIS | M0)) /* UART1_TX */\
-	MUX_VAL(CP(UART1_RX),       (IEN  | PTD | DIS | M0)) /* UART1_RX */\
 	MUX_VAL(CP(UART3_TX_IRTX),  (IDIS | PTD | DIS | M0)) /* UART3_TX */\
 	MUX_VAL(CP(UART3_RX_IRRX),  (IEN  | PTD | DIS | M0)) /* UART3_RX */\
 	MUX_VAL(CP(I2C1_SCL),       (IEN  | PTU | EN  | M0)) /* I2C1_SCL */\
@@ -149,3 +161,10 @@
 	MUX_VAL(CP(SDRC_CKE0),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE0 */\
 	MUX_VAL(CP(SDRC_CKE1),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE1 */
 #endif
+
+#define MUX_IGEP0020() \
+	MUX_VAL(CP(GPMC_WAIT2),     (IEN  | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
+
+#define MUX_IGEP0030() \
+	MUX_VAL(CP(UART1_TX),       (IDIS | PTD | DIS | M0)) /* UART1_TX */\
+	MUX_VAL(CP(UART1_RX),       (IEN  | PTD | DIS | M0)) /* UART1_RX */
diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c
index 54f25e0..0d895c2 100644
--- a/board/kmc/kzm9g/kzm9g.c
+++ b/board/kmc/kzm9g/kzm9g.c
@@ -84,7 +84,7 @@
 	writel(0x0017040a, &sbsc->sdwcr01);
 	writel(0x31020707, &sbsc->sdwcr10);
 	writel(0x0017040a, &sbsc->sdwcr11);
-	writel(0x05555555, &sbsc->sddrvcr0);
+	writel(0x055557ff, &sbsc->sddrvcr0); /* Enlarge drivability of LPDQS0-3, LPCLK */
 	writel(0x30000000, &sbsc->sdwcr2);
 
 	writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr);
@@ -112,7 +112,7 @@
 		writel(0x0, SDMRA1A);
 		writel(0x00000402, &sbsc->sdmracr0);
 		writel(0x0, SDMRA1A);
-		writel(0x00000403, &sbsc->sdmracr0);
+		writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */
 		writel(0x0, SDMRA1A);
 		writel(0x0, SDMRA2A);
 	} else {
@@ -120,7 +120,7 @@
 		writel(0x0, SDMRA1B);
 		writel(0x00000402, &sbsc->sdmracr0);
 		writel(0x0, SDMRA1B);
-		writel(0x00000403, &sbsc->sdmracr0);
+		writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */
 		writel(0x0, SDMRA1B);
 		writel(0x0, SDMRA2B);
 	}
@@ -195,7 +195,7 @@
 
 	/* FRQCR Init */
 	writel(0x0012453C, &cpg->frqcra);
-	writel(0x80331350, &cpg->frqcrb);
+	writel(0x80431350, &cpg->frqcrb);    /* ETM TRCLK  78MHz */
 	cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
 	writel(0x00000B0B, &cpg->frqcrd);
 	cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
@@ -301,8 +301,19 @@
 	return 0;
 }
 
+void adjust_core_voltage(void)
+{
+	u8 data;
+
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	data = 0x35;
+	i2c_set_bus_num(0);
+	i2c_write(0x40, 3, 1, &data, 1);
+}
+
 int board_init(void)
 {
+	adjust_core_voltage();
 	sh73a0_pinmux_init();
 
     /* SCIFA 4 */
diff --git a/board/nvidia/cardhu/Makefile b/board/nvidia/cardhu/Makefile
new file mode 100644
index 0000000..913f1ce
--- /dev/null
+++ b/board/nvidia/cardhu/Makefile
@@ -0,0 +1,44 @@
+#
+#  (C) Copyright 2010-2012
+#  NVIDIA Corporation <www.nvidia.com>
+#
+#
+#  See file CREDITS for list of people who contributed to this
+#  project.
+#
+#  This program is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU General Public License as
+#  published by the Free Software Foundation; either version 2 of
+#  the License, or (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program; if not, write to the Free Software
+#  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+#  MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/x86/cpu/sc520/sc520_reset.c b/board/nvidia/cardhu/cardhu.c
similarity index 66%
rename from arch/x86/cpu/sc520/sc520_reset.c
rename to board/nvidia/cardhu/cardhu.c
index 137af97..df4cb6b 100644
--- a/arch/x86/cpu/sc520/sc520_reset.c
+++ b/board/nvidia/cardhu/cardhu.c
@@ -1,9 +1,6 @@
 /*
- * (C) Copyright 2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -25,16 +22,18 @@
  */
 
 #include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc520.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-cardhu.h"
 
-DECLARE_GLOBAL_DATA_PTR;
-
-void reset_cpu(ulong addr)
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
 {
-	printf("Resetting using SC520 MMCR\n");
-	/* Write a '1' to the SYS_RST of the RESCFG MMCR */
-	writeb(0x01, &sc520_mmcr->rescfg);
+	pinmux_config_table(tegra3_pinmux_common,
+		ARRAY_SIZE(tegra3_pinmux_common));
 
-	/* NOTREACHED */
+	pinmux_config_table(unused_pins_lowpower,
+		ARRAY_SIZE(unused_pins_lowpower));
 }
diff --git a/board/nvidia/cardhu/cardhu.c.mmc b/board/nvidia/cardhu/cardhu.c.mmc
new file mode 100644
index 0000000..9e83b6f
--- /dev/null
+++ b/board/nvidia/cardhu/cardhu.c.mmc
@@ -0,0 +1,151 @@
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-cardhu.h"
+
+#include <asm/arch/clock.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/pmu.h>
+#include <asm/arch/sdmmc.h>
+#include <asm/arch-tegra/mmc.h>
+#include <asm/arch-tegra/tegra_mmc.h>
+#include <mmc.h>
+#include <i2c.h>
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_config_table(tegra3_pinmux_common,
+		ARRAY_SIZE(tegra3_pinmux_common));
+
+	pinmux_config_table(unused_pins_lowpower,
+		ARRAY_SIZE(unused_pins_lowpower));
+}
+
+#if defined(CONFIG_MMC)
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+static void pin_mux_mmc(void)
+{
+}
+
+/* Do I2C/PMU writes to bring up SD card bus power */
+static void board_sdmmc_voltage_init(void)
+{
+        uchar reg, data_buffer[1];
+        int i;
+
+        i2c_set_bus_num(0);             /* PMU is on bus 0 */
+
+        data_buffer[0] = 0x65;
+        reg = 0x32;
+
+        for (i = 0; i < MAX_I2C_RETRY; ++i) {
+                if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
+                        udelay(100);
+        }
+
+        data_buffer[0] = 0x09;
+        reg = 0x67;
+
+        for (i = 0; i < MAX_I2C_RETRY; ++i) {
+                if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
+                        udelay(100);
+        }
+}
+
+static void pad_init_mmc(struct tegra_mmc *reg)
+{
+        struct apb_misc_gp_ctlr *const gpc =
+                (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
+        struct sdmmc_ctlr *const sdmmc = (struct sdmmc_ctlr *)reg;
+        u32 val, offset = (unsigned int)reg;
+        u32 padcfg, padmask;
+
+        debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)sdmmc);
+
+        /* Set the pad drive strength for SDMMC1 or 3 only */
+        if (offset != TEGRA_SDMMC1_BASE && offset != TEGRA_SDMMC3_BASE) {
+                debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
+                        __func__);
+                return;
+        }
+
+        /* Set pads as per T30 TRM, section 24.6.1.2 */
+        padcfg = (GP_SDIOCFG_DRVUP_SLWF | GP_SDIOCFG_DRVDN_SLWR | \
+                GP_SDIOCFG_DRVUP | GP_SDIOCFG_DRVDN);
+        padmask = 0x00000FFF;
+        if (offset == TEGRA_SDMMC1_BASE) {
+                val = readl(&gpc->sdio1cfg);
+                val &= padmask;
+                val |= padcfg;
+                writel(val, &gpc->sdio1cfg);
+        } else {                                /* SDMMC3 */
+                val = readl(&gpc->sdio3cfg);
+                val &= padmask;
+                val |= padcfg;
+                writel(val, &gpc->sdio3cfg);
+        }
+
+        val = readl(&sdmmc->sdmmc_sdmemcomp_pad_ctrl);
+        val &= 0xFFFFFFF0;
+        val |= MEMCOMP_PADCTRL_VREF;
+        writel(val, &sdmmc->sdmmc_sdmemcomp_pad_ctrl);
+
+        val = readl(&sdmmc->sdmmc_auto_cal_config);
+        val &= 0xFFFF0000;
+        val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
+        writel(val, &sdmmc->sdmmc_auto_cal_config);
+}
+
+/* this is a weak define that we are overriding */
+int board_mmc_init(bd_t *bd)
+{
+	debug("board_mmc_init called\n");
+
+	/* Turn on SD-card bus power */
+	board_sdmmc_voltage_init();
+
+	/* Set up the SDMMC pads as per the TRM */
+	pad_init_mmc((struct tegra_mmc *)TEGRA_SDMMC1_BASE);
+
+	/* Enable muxes, etc. for SDMMC controllers */
+	pin_mux_mmc();
+
+	/* init dev 0 (SDMMC4), ("HSMMC") with 8-bit bus */
+	tegra_mmc_init(0, 8, -1, -1);
+
+	/* init dev 1 (SDMMC0), ("SDIO") with 8-bit bus */
+	tegra_mmc_init(1, 8, -1, -1);
+
+	return 0;
+}
+#endif	/* MMC */
diff --git a/board/nvidia/cardhu/pinmux-config-cardhu.h b/board/nvidia/cardhu/pinmux-config-cardhu.h
new file mode 100644
index 0000000..8428bba
--- /dev/null
+++ b/board/nvidia/cardhu/pinmux-config-cardhu.h
@@ -0,0 +1,329 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _PINMUX_CONFIG_CARDHU_H_
+#define _PINMUX_CONFIG_CARDHU_H_
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io)	\
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_##_ioreset	\
+	}
+
+static struct pingroup_config tegra3_pinmux_common[] = {
+	/* SDMMC1 pinmux */
+	DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
+
+	/* SDMMC3 pinmux */
+	DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT6, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT7, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* SDMMC4 pinmux */
+	LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* I2C1 pinmux */
+	I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C2 pinmux */
+	I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C3 pinmux */
+	I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C4 pinmux */
+	I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* Power I2C pinmux */
+	I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA3, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PV2, OWR, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+	LV_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D2, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_MCLK, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_CS2_N, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
+	DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
+	DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
+	DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
+
+	/* KBC keys */
+	DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW11, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(SPI2_CS1_N, SPI2, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
+
+	/* GPIOs */
+	/* SDMMC1 CD gpio */
+	DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT),
+	/* SDMMC1 WP gpio */
+	LV_PINMUX(VI_D11, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* Touch panel GPIO */
+	/* Touch IRQ */
+	DEFAULT_PINMUX(GMI_AD12, NAND, UP, NORMAL, INPUT),
+
+	/* Touch RESET */
+	DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, OUTPUT),
+
+	/* Power rails GPIO */
+	DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT),
+
+	LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D8, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D9, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_PCLK, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_HSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+};
+
+static struct pingroup_config unused_pins_lowpower[] = {
+	DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
+};
+
+#endif /* _PINMUX_CONFIG_CARDHU_H_ */
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 76ec687..d1d8a29 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -26,22 +26,30 @@
 #include <linux/compiler.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
+#ifdef CONFIG_LCD
 #include <asm/arch/display.h>
-#include <asm/arch/emc.h>
+#endif
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/pmu.h>
+#ifdef CONFIG_PWM_TEGRA
 #include <asm/arch/pwm.h>
+#endif
 #include <asm/arch/tegra.h>
-#include <asm/arch/usb.h>
 #include <asm/arch-tegra/board.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/pmc.h>
 #include <asm/arch-tegra/sys_proto.h>
 #include <asm/arch-tegra/uart.h>
 #include <asm/arch-tegra/warmboot.h>
-#include <spi.h>
+#ifdef CONFIG_TEGRA_CLOCK_SCALING
+#include <asm/arch/emc.h>
+#endif
+#ifdef CONFIG_USB_EHCI_TEGRA
+#include <asm/arch/usb.h>
+#endif
 #include <i2c.h>
+#include <spi.h>
 #include "emc.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -87,6 +95,12 @@
 
 void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand")));
 
+void __pin_mux_display(void)
+{
+}
+
+void pin_mux_display(void) __attribute__((weak, alias("__pin_mux_display")));
+
 /*
  * Routine: power_det_init
  * Description: turn off power detects
@@ -117,15 +131,17 @@
 #ifdef CONFIG_SPI_UART_SWITCH
 	gpio_config_uart();
 #endif
-#ifdef CONFIG_TEGRA_SPI
+#if defined(CONFIG_TEGRA_SPI) || defined(CONFIG_TEGRA_SLINK)
 	pin_mux_spi();
 	spi_init();
 #endif
+
 #ifdef CONFIG_PWM_TEGRA
 	if (pwm_init(gd->fdt_blob))
 		debug("%s: Failed to init pwm\n", __func__);
 #endif
 #ifdef CONFIG_LCD
+	pin_mux_display();
 	tegra_lcd_check_next_stage(gd->fdt_blob, 0);
 #endif
 	/* boot param addr */
@@ -181,6 +197,9 @@
 
 int board_early_init_f(void)
 {
+#if !defined(CONFIG_TEGRA20)
+	pinmux_init();
+#endif
 	board_init_uart_f();
 
 	/* Initialize periph GPIOs */
diff --git a/board/nvidia/dalmore/Makefile b/board/nvidia/dalmore/Makefile
new file mode 100644
index 0000000..699b9f6
--- /dev/null
+++ b/board/nvidia/dalmore/Makefile
@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c
new file mode 100644
index 0000000..aca3c7d
--- /dev/null
+++ b/board/nvidia/dalmore/dalmore.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-dalmore.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_config_table(tegra114_pinmux_common,
+		ARRAY_SIZE(tegra114_pinmux_common));
+
+	pinmux_config_table(unused_pins_lowpower,
+		ARRAY_SIZE(unused_pins_lowpower));
+}
diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h
new file mode 100644
index 0000000..3dd47da
--- /dev/null
+++ b/board/nvidia/dalmore/pinmux-config-dalmore.h
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _PINMUX_CONFIG_DALMORE_H_
+#define _PINMUX_CONFIG_DALMORE_H_
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io)   \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_##_ioreset  \
+	}
+
+static struct pingroup_config tegra114_pinmux_common[] = {
+	/* SDMMC1 pinmux */
+	DEFAULT_PINMUX(SDMMC1_CLK,      SDMMC1,	  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD,      SDMMC1,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3,     SDMMC1,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2,     SDMMC1,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1,     SDMMC1,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0,     SDMMC1,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_WP_N,     SDMMC1,	  UP,     NORMAL,   INPUT),
+
+	/* SDMMC3 pinmux */
+	DEFAULT_PINMUX(SDMMC3_CLK,      SDMMC3,	  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3,  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, NORMAL, NORMAL,   OUTPUT),
+
+	DEFAULT_PINMUX(SDMMC3_CMD,      SDMMC3,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0,     SDMMC3,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1,     SDMMC3,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2,     SDMMC3,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3,     SDMMC3,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CD_N,     SDMMC3,   UP,     NORMAL,   INPUT),
+
+	/* SDMMC4 pinmux */
+	LV_PINMUX(SDMMC4_CLK,  SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_CMD,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_RST_N,	RSVD1, DOWN,   NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* I2C1 pinmux */
+	I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL,	NORMAL,	INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL,	NORMAL,	INPUT, DISABLE, ENABLE),
+
+	/* I2C2 pinmux */
+	I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL,	NORMAL,	INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL,	NORMAL,	INPUT, DISABLE, ENABLE),
+
+	/* I2C3 pinmux */
+	I2C_PINMUX(CAM_I2C_SCL,	I2C3, NORMAL,	NORMAL,	INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(CAM_I2C_SDA,	I2C3, NORMAL,	NORMAL,	INPUT, DISABLE, ENABLE),
+
+	/* I2C4 pinmux */
+	I2C_PINMUX(DDC_SCL,	I2C4, NORMAL,	NORMAL,	INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(DDC_SDA,	I2C4, NORMAL,	NORMAL,	INPUT, DISABLE, ENABLE),
+
+	/* Power I2C pinmux */
+	I2C_PINMUX(PWR_I2C_SCL,	I2CPWR,	NORMAL,	NORMAL,	INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	DEFAULT_PINMUX(ULPI_DATA0,      UARTA,    NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(ULPI_DATA1,      UARTA,    UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA2,      UARTA,    NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA3,      UARTA,    NORMAL, NORMAL,   INPUT),
+
+	DEFAULT_PINMUX(ULPI_DATA4,      UARTA,    NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5,      UARTA,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6,      UARTA,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7,      UARTA,	  NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(ULPI_CLK,	UARTD,    NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(ULPI_DIR,	UARTD,    NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(ULPI_NXT,	UARTD,    NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(ULPI_STP,	UARTD,    NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(DAP3_FS,	        I2S2,     NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(DAP3_DIN,	I2S2,     NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(DAP3_DOUT,       I2S2,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(DAP3_SCLK,       I2S2,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(CLK2_OUT,	EXTPERIPH2, NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(CLK2_REQ,	DAP,      NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(UART2_RXD,       UARTB,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(UART2_TXD,       UARTB,	  NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(UART2_RTS_N,     UARTB,	  NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(UART2_CTS_N,     UARTB,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(UART3_TXD,       UARTC,	  NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(UART3_RXD,       UARTC,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(UART3_CTS_N,     UARTC,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N,     UARTC,	  NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU0,	RSVD1,    NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PU1,	RSVD1,    NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU2,	RSVD1,    NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PU3,	RSVD1,    NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PU4,	PWM1,     NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU5,	PWM2,     NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU6,	RSVD1,    NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(DAP4_FS,         I2S3,     NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(DAP4_DIN,	I2S3,     NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(DAP4_DOUT,       I2S3,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(DAP4_SCLK,       I2S3,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(CLK3_OUT,	EXTPERIPH3, NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(CLK3_REQ,	DEV3,     NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GMI_WP_N,	GMI,      NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GMI_CS2_N,       RSVD1,	  UP,     NORMAL,     INPUT),
+	DEFAULT_PINMUX(GMI_AD8,	        PWM0,     NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(GMI_AD10,	NAND,     NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(GMI_A16,	        UARTD,    NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(GMI_A17,	        UARTD,    NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GMI_A18,	        UARTD,    NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GMI_A19,	        UARTD,    NORMAL, NORMAL,     OUTPUT),
+	DEFAULT_PINMUX(CAM_MCLK,	VI_ALT2,  UP,     NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PCC1,       RSVD1,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PBB0,       RSVD1,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PBB3,       VGP3,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PBB5,       VGP5,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PBB6,       VGP6,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PBB7,       I2S4,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(GPIO_PCC2,       I2S4,	  NORMAL, NORMAL,     INPUT),
+	DEFAULT_PINMUX(JTAG_RTCK,       RTCK,	  NORMAL, NORMAL,     OUTPUT),
+
+	/*  KBC keys */
+	DEFAULT_PINMUX(KB_ROW0,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW1,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW2,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW3,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW4,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW5,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW6,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW7,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW8,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW9,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW10,   KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL0,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL1,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL2,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL3,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL4,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL5,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL6,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL7,    KBC,    UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PV0,   RSVD1,  UP,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PV1,   RSVD1,  UP,    NORMAL,    INPUT),
+
+	DEFAULT_PINMUX(CLK_32K_OUT,     BLINK,	  NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(SYS_CLK_REQ,     SYSCLK,	  NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(OWR,	        OWR,	  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP1_FS,	        I2S0,     NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP1_DIN,	I2S0,     NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP1_DOUT,       I2S0,	  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP1_SCLK,       I2S0,	  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(CLK1_REQ,	DAP,      NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(CLK1_OUT,	EXTPERIPH1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPDIF_IN,	SPDIF,    NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(SPDIF_OUT,       SPDIF,	  NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(DAP2_FS,	        I2S1,     NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP2_DIN,	I2S1,     NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP2_DOUT,       I2S1,     NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP2_SCLK,       I2S1,	  NORMAL, NORMAL,   INPUT),
+
+	DEFAULT_PINMUX(SPI1_MOSI,       SPI1,     NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(SPI1_SCK,	SPI1,     NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(SPI1_CS0_N,      SPI1,	  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(SPI1_CS1_N,      SPI1,	  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(SPI1_CS2_N,      SPI1,	  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(SPI1_MISO,       SPI1,	  NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(HDMI_CEC,	CEC,      NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(HDMI_INT,        RSVD1,    NORMAL, TRISTATE, INPUT),
+
+	/* GPIOs */
+	/* SDMMC1 CD gpio */
+	DEFAULT_PINMUX(GMI_IORDY,       RSVD1,	  UP,     NORMAL,   INPUT),
+
+	/* Touch RESET */
+	DEFAULT_PINMUX(GMI_AD14,	NAND,     NORMAL, NORMAL,   OUTPUT),
+
+	/* Power rails GPIO */
+	DEFAULT_PINMUX(SPI2_SCK,	GMI,      NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(GPIO_PBB4,       VGP4,     NORMAL, NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_ROW8,	        KBC,      UP,     NORMAL,   INPUT),
+};
+
+static struct pingroup_config unused_pins_lowpower[] = {
+	DEFAULT_PINMUX(GMI_CS0_N,       NAND,	  UP,     TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS3_N,       NAND,	  UP,     TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS4_N,       NAND,	  UP,     TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS7_N,       NAND,	  UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(GMI_AD0,	        NAND,     NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_AD1,	        NAND,     NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_AD2,	        NAND,     NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_AD3,	        NAND,     NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_AD4,	        NAND,     NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_AD5,	        NAND,     NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_AD6,	        NAND,     NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_AD7,	        NAND,     NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_AD9,	        PWM1,     NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD11,	NAND,     NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD13,	NAND,     UP,	  NORMAL,   INPUT),
+	DEFAULT_PINMUX(GMI_WR_N,	NAND,     NORMAL, TRISTATE, OUTPUT),
+};
+
+#endif /* _PINMUX_CONFIG_DALMORE_H_ */
diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts
new file mode 100644
index 0000000..7315577
--- /dev/null
+++ b/board/nvidia/dts/tegra114-dalmore.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+/include/ ARCH_CPU_DTS
+
+/ {
+	model = "NVIDIA Dalmore";
+	compatible = "nvidia,dalmore", "nvidia,tegra114";
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+};
diff --git a/board/nvidia/dts/tegra20-harmony.dts b/board/nvidia/dts/tegra20-harmony.dts
index 5645a8d..aeda3a1 100644
--- a/board/nvidia/dts/tegra20-harmony.dts
+++ b/board/nvidia/dts/tegra20-harmony.dts
@@ -15,23 +15,20 @@
 		reg = <0x00000000 0x40000000>;
 	};
 
-	clocks {
-		clk_32k: clk_32k {
-			clock-frequency = <32000>;
-		};
-		osc {
-			clock-frequency = <12000000>;
-		};
-	};
-
-	clock@60006000 {
-		clocks = <&clk_32k &osc>;
-	};
-
 	serial@70006300 {
 		clock-frequency = < 216000000 >;
 	};
 
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 23 0>;		/* PC7 */
+		nvidia,width = <8>;
+		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+		nand@0 {
+			reg = <0>;
+			compatible = "hynix,hy27uf4g2b", "nand-flash";
+		};
+	};
+
 	i2c@7000c000 {
 		status = "disabled";
 	};
@@ -55,14 +52,4 @@
 	usb@c5004000 {
 		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
 	};
-
-	nand-controller@70008000 {
-		nvidia,wp-gpios = <&gpio 23 0>;		/* PC7 */
-		nvidia,width = <8>;
-		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
-		nand@0 {
-			reg = <0>;
-			compatible = "hynix,hy27uf4g2b", "nand-flash";
-		};
-	};
 };
diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts
index dd98ca4..527a296 100644
--- a/board/nvidia/dts/tegra20-seaboard.dts
+++ b/board/nvidia/dts/tegra20-seaboard.dts
@@ -27,6 +27,17 @@
 		reg = < 0x00000000 0x40000000 >;
 	};
 
+	host1x {
+		status = "okay";
+		dc@54200000 {
+			status = "okay";
+			rgb {
+				status = "okay";
+				nvidia,panel = <&lcd_panel>;
+			};
+		};
+	};
+
 	/* This is not used in U-Boot, but is expected to be in kernel .dts */
 	i2c@7000d000 {
 		clock-frequency = <100000>;
@@ -45,37 +56,18 @@
 		};
 	};
 
-	clocks {
-		osc {
-			clock-frequency = <12000000>;
-		};
-	};
-
-	clock@60006000 {
-		clocks = <&clk_32k &osc>;
-	};
-
 	serial@70006300 {
 		clock-frequency = < 216000000 >;
 	};
 
-	sdhci@c8000400 {
-		cd-gpios = <&gpio 69 0>; /* gpio PI5 */
-		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-		power-gpios = <&gpio 70 0>; /* gpio PI6 */
-	};
-
-	sdhci@c8000600 {
-		support-8bit;
-	};
-
-	usb@c5000000 {
-		nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
-		dr_mode = "otg";
-	};
-
-	usb@c5004000 {
-		status = "disabled";
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 59 0>;		/* PH3 */
+		nvidia,width = <8>;
+		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+		nand@0 {
+			reg = <0>;
+			compatible = "hynix,hy27uf4g2b", "nand-flash";
+		};
 	};
 
 	i2c@7000c000 {
@@ -90,6 +82,33 @@
 		clock-frequency = <100000>;
 	};
 
+	kbc@7000e200 {
+		linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c
+			0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006
+			0x03010005 0x03020013 0x03030012 0x03040021 0x03050020
+			0x0306002d 0x04000008 0x04010007 0x04020014 0x04030023
+			0x04040022 0x0405002f 0x0406002e 0x04070039 0x0500000a
+			0x05010009 0x05020016 0x05030015 0x05040024 0x05050031
+			0x05060030 0x0507002b 0x0600000c 0x0601000b 0x06020018
+			0x06030017 0x06040026 0x06050025 0x06060033 0x06070032
+			0x0701000d 0x0702001b 0x0703001c 0x0707008b 0x08040036
+			0x0805002a 0x09050061 0x0907001d 0x0b00001a 0x0b010019
+			0x0b020028 0x0b030027 0x0b040035 0x0b050034 0x0c000044
+			0x0c010043 0x0c02000e 0x0c030004 0x0c040003 0x0c050067
+			0x0c0600d2 0x0c070077 0x0d00006e 0x0d01006f 0x0d030068
+			0x0d04006d 0x0d05006a 0x0d06006c 0x0d070069 0x0e000057
+			0x0e010058 0x0e020042 0x0e030010 0x0e04003e 0x0e05003d
+			0x0e060002 0x0e070041 0x0f000001 0x0f010029 0x0f02003f
+			0x0f03000f 0x0f04003b 0x0f05003c 0x0f06003a 0x0f070040
+			0x14000047 0x15000049 0x15010048 0x1502004b 0x1504004f
+			0x16010062 0x1602004d 0x1603004c 0x16040051 0x16050050
+			0x16070052 0x1b010037 0x1b03004a 0x1b04004e 0x1b050053
+			0x1c050073 0x1d030066 0x1d04006b 0x1d0500e0 0x1d060072
+			0x1d0700e1 0x1e000045 0x1e010046 0x1e020071
+			0x1f04008a>;
+		linux,fn-keymap = <0x05040002>;
+	};
+
 	emc@7000f400 {
 		emc-table@190000 {
 			reg = < 190000 >;
@@ -127,54 +146,25 @@
 		};
 	};
 
-	kbc@7000e200 {
-		linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c
-			0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006
-			0x03010005 0x03020013 0x03030012 0x03040021 0x03050020
-			0x0306002d 0x04000008 0x04010007 0x04020014 0x04030023
-			0x04040022 0x0405002f 0x0406002e 0x04070039 0x0500000a
-			0x05010009 0x05020016 0x05030015 0x05040024 0x05050031
-			0x05060030 0x0507002b 0x0600000c 0x0601000b 0x06020018
-			0x06030017 0x06040026 0x06050025 0x06060033 0x06070032
-			0x0701000d 0x0702001b 0x0703001c 0x0707008b 0x08040036
-			0x0805002a 0x09050061 0x0907001d 0x0b00001a 0x0b010019
-			0x0b020028 0x0b030027 0x0b040035 0x0b050034 0x0c000044
-			0x0c010043 0x0c02000e 0x0c030004 0x0c040003 0x0c050067
-			0x0c0600d2 0x0c070077 0x0d00006e 0x0d01006f 0x0d030068
-			0x0d04006d 0x0d05006a 0x0d06006c 0x0d070069 0x0e000057
-			0x0e010058 0x0e020042 0x0e030010 0x0e04003e 0x0e05003d
-			0x0e060002 0x0e070041 0x0f000001 0x0f010029 0x0f02003f
-			0x0f03000f 0x0f04003b 0x0f05003c 0x0f06003a 0x0f070040
-			0x14000047 0x15000049 0x15010048 0x1502004b 0x1504004f
-			0x16010062 0x1602004d 0x1603004c 0x16040051 0x16050050
-			0x16070052 0x1b010037 0x1b03004a 0x1b04004e 0x1b050053
-			0x1c050073 0x1d030066 0x1d04006b 0x1d0500e0 0x1d060072
-			0x1d0700e1 0x1e000045 0x1e010046 0x1e020071
-			0x1f04008a>;
-		linux,fn-keymap = <0x05040002>;
+	usb@c5000000 {
+		nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+		dr_mode = "otg";
 	};
 
-	nand-controller@70008000 {
-		nvidia,wp-gpios = <&gpio 59 0>;		/* PH3 */
-		nvidia,width = <8>;
-		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
-		nand@0 {
-			reg = <0>;
-			compatible = "hynix,hy27uf4g2b", "nand-flash";
-		};
+	usb@c5004000 {
+		status = "disabled";
 	};
 
-	host1x {
-		status = "okay";
-		dc@54200000 {
-			status = "okay";
-			rgb {
-				status = "okay";
-				nvidia,panel = <&lcd_panel>;
-			};
-		};
+	sdhci@c8000400 {
+		cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+		power-gpios = <&gpio 70 0>; /* gpio PI6 */
 	};
 
+	sdhci@c8000600 {
+		support-8bit;
+	};
+
 	lcd_panel: panel {
 		/* Seaboard has 1366x768 */
 		clock = <70600000>;
@@ -195,5 +185,4 @@
 		nvidia,panel-vdd-gpios = <&gpio 22 0>;		/* PC6 */
 		nvidia,panel-timings = <400 4 203 17 15>;
 	};
-
 };
diff --git a/board/nvidia/dts/tegra20-ventana.dts b/board/nvidia/dts/tegra20-ventana.dts
index 38b7b13..3e5e39d 100644
--- a/board/nvidia/dts/tegra20-ventana.dts
+++ b/board/nvidia/dts/tegra20-ventana.dts
@@ -14,19 +14,6 @@
 		reg = <0x00000000 0x40000000>;
 	};
 
-	clocks {
-		clk_32k: clk_32k {
-			clock-frequency = <32000>;
-		};
-		osc {
-			clock-frequency = <12000000>;
-		};
-	};
-
-	clock@60006000 {
-		clocks = <&clk_32k &osc>;
-	};
-
 	serial@70006300 {
 		clock-frequency = < 216000000 >;
 	};
diff --git a/board/nvidia/dts/tegra20-whistler.dts b/board/nvidia/dts/tegra20-whistler.dts
index f830cf3..4579557 100644
--- a/board/nvidia/dts/tegra20-whistler.dts
+++ b/board/nvidia/dts/tegra20-whistler.dts
@@ -16,16 +16,6 @@
 		reg = < 0x00000000 0x20000000 >;
 	};
 
-	clocks {
-		osc {
-			clock-frequency = <12000000>;
-		};
-	};
-
-	clock@60006000 {
-		clocks = <&clk_32k &osc>;
-	};
-
 	serial@70006000 {
 		clock-frequency = < 216000000 >;
 	};
diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts
new file mode 100644
index 0000000..f9f80c5
--- /dev/null
+++ b/board/nvidia/dts/tegra30-cardhu.dts
@@ -0,0 +1,47 @@
+/dts-v1/;
+
+/memreserve/ 0x1c000000 0x04000000;
+/include/ ARCH_CPU_DTS
+
+/ {
+	model = "NVIDIA Cardhu";
+	compatible = "nvidia,cardhu", "nvidia,tegra30";
+
+	aliases {
+		i2c0 = "/i2c@7000d000";
+		i2c1 = "/i2c@7000c000";
+		i2c2 = "/i2c@7000c400";
+		i2c3 = "/i2c@7000c500";
+		i2c4 = "/i2c@7000c700";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+
+	i2c@7000c000 {
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c400 {
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c500 {
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c700 {
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000d000 {
+		clock-frequency = <100000>;
+	};
+
+	spi@7000da00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+};
diff --git a/board/isee/igep0030/Makefile b/board/olimex/mx23_olinuxino/Makefile
similarity index 91%
copy from board/isee/igep0030/Makefile
copy to board/olimex/mx23_olinuxino/Makefile
index cbc03d4..ff41cff 100644
--- a/board/isee/igep0030/Makefile
+++ b/board/olimex/mx23_olinuxino/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -25,7 +25,11 @@
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= igep0030.o
+ifndef	CONFIG_SPL_BUILD
+COBJS	:= mx23_olinuxino.o
+else
+COBJS	:= spl_boot.o
+endif
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c
new file mode 100644
index 0000000..6a6053b
--- /dev/null
+++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c
@@ -0,0 +1,71 @@
+/*
+ * Olimex MX23 Olinuxino board
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+	/* IO0 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK0, 480000);
+
+	/* SSP0 clock at 96MHz */
+	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	return mxs_dram_init();
+}
+
+#ifdef	CONFIG_CMD_MMC
+static int mx23_olx_mmc_cd(int id)
+{
+	return 1;	/* Card always present */
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	return mxsmmc_initialize(bis, 0, NULL, mx23_olx_mmc_cd);
+}
+#endif
+
+int board_init(void)
+{
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
diff --git a/board/olimex/mx23_olinuxino/spl_boot.c b/board/olimex/mx23_olinuxino/spl_boot.c
new file mode 100644
index 0000000..7def8bc
--- /dev/null
+++ b/board/olimex/mx23_olinuxino/spl_boot.c
@@ -0,0 +1,99 @@
+/*
+ * Olimex MX23 Olinuxino Boot setup
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_16MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_SSP	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+
+const iomux_cfg_t iomux_setup[] = {
+	/* DUART */
+	MX23_PAD_PWM0__DUART_RX,
+	MX23_PAD_PWM1__DUART_TX,
+
+	/* EMI */
+	MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
+
+	MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+
+	MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+
+	/* MMC 0 */
+	MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP,
+	MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP,
+	MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP,
+	MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP,
+	MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP,
+	MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP,
+};
+
+void board_init_ll(void)
+{
+	mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/board/phytec/pcm051/Makefile b/board/phytec/pcm051/Makefile
new file mode 100644
index 0000000..67a87a1
--- /dev/null
+++ b/board/phytec/pcm051/Makefile
@@ -0,0 +1,46 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS	:= mux.o
+endif
+
+COBJS	+= board.o
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
new file mode 100644
index 0000000..55bc018
--- /dev/null
+++ b/board/phytec/pcm051/board.c
@@ -0,0 +1,266 @@
+/*
+ * board.c
+ *
+ * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
+ *
+ * Copyright (C) 2013 Lemonage Software GmbH
+ * Author Lars Poeschel <poeschel@lemonage.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+#ifdef CONFIG_SPL_BUILD
+static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+#endif
+
+/* MII mode defines */
+#define MII_MODE_ENABLE		0x0
+#define RGMII_MODE_ENABLE	0xA
+#define RMII_RGMII2_MODE_ENABLE	0x49
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* UART defines */
+#ifdef CONFIG_SPL_BUILD
+#define UART_RESET		(0x1 << 1)
+#define UART_CLK_RUNNING_MASK	0x1
+#define UART_SMART_IDLE_EN	(0x1 << 0x3)
+
+/* DDR RAM defines */
+#define DDR_CLK_MHZ		303 /* DDR_DPLL_MULT value */
+
+static void rtc32k_enable(void)
+{
+	struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
+
+	/*
+	 * Unlock the RTC's registers.  For more details please see the
+	 * RTC_SS section of the TRM.  In order to unlock we need to
+	 * write these specific values (keys) in this order.
+	 */
+	writel(0x83e70b13, &rtc->kick0r);
+	writel(0x95a4f1e0, &rtc->kick1r);
+
+	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
+	writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41J256M8HX15E_RD_DQS,
+	.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
+	.datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
+	.datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41J256M8HX15E_RATIO,
+	.cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
+	.cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41J256M8HX15E_RATIO,
+	.cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
+	.cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41J256M8HX15E_RATIO,
+	.cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
+	.cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
+	.ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
+	.sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
+	.sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
+	.sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
+	.zq_config = MT41J256M8HX15E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY,
+};
+#endif
+
+/*
+ * early system init of muxing and clocks.
+ */
+void s_init(void)
+{
+	/*
+	 * WDT1 is already running when the bootloader gets control
+	 * Disable it to avoid "random" resets
+	 */
+	writel(0xAAAA, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+	writel(0x5555, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+
+#ifdef CONFIG_SPL_BUILD
+	/* Setup the PLLs and the clocks for the peripherals */
+	pll_init();
+
+	/* Enable RTC32K clock */
+	rtc32k_enable();
+
+	/* UART softreset */
+	u32 regval;
+
+	enable_uart0_pin_mux();
+
+	regval = readl(&uart_base->uartsyscfg);
+	regval |= UART_RESET;
+	writel(regval, &uart_base->uartsyscfg);
+	while ((readl(&uart_base->uartsyssts) &	UART_CLK_RUNNING_MASK)
+		!= UART_CLK_RUNNING_MASK)
+		;
+
+	/* Disable smart idle */
+	regval = readl(&uart_base->uartsyscfg);
+	regval |= UART_SMART_IDLE_EN;
+	writel(regval, &uart_base->uartsyscfg);
+
+	gd = &gdata;
+
+	preloader_console_init();
+
+	/* Initalize the board header */
+	enable_i2c0_pin_mux();
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	enable_board_pin_mux();
+
+	config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
+			&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
+#endif
+}
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_id		= 0,
+		.phy_if		= PHY_INTERFACE_MODE_RGMII,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_id		= 1,
+		.phy_if		= PHY_INTERFACE_MODE_RGMII,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= AM335X_CPSW_MDIO_BASE,
+	.cpsw_base		= AM335X_CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+#endif
+
+#if defined(CONFIG_DRIVER_TI_CPSW) || \
+	(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
+int board_eth_init(bd_t *bis)
+{
+	int rv, n = 0;
+#ifdef CONFIG_DRIVER_TI_CPSW
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+		printf("<ethaddr> not set. Reading from E-fuse\n");
+		/* try reading mac address from efuse */
+		mac_lo = readl(&cdev->macid0l);
+		mac_hi = readl(&cdev->macid0h);
+		mac_addr[0] = mac_hi & 0xFF;
+		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+		mac_addr[4] = mac_lo & 0xFF;
+		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+		else
+			goto try_usbether;
+	}
+
+	writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+try_usbether:
+#endif
+
+#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
+	rv = usb_eth_initialize(bis);
+	if (rv < 0)
+		printf("Error %d registering USB_ETHER\n", rv);
+	else
+		n += rv;
+#endif
+	return n;
+}
+#endif
diff --git a/board/phytec/pcm051/board.h b/board/phytec/pcm051/board.h
new file mode 100644
index 0000000..c2630d7
--- /dev/null
+++ b/board/phytec/pcm051/board.h
@@ -0,0 +1,33 @@
+/*
+ * board.h
+ *
+ * Phytec phyCORE-AM335x (pcm051) boards information header
+ *
+ * Copyright (C) 2013, Lemonage Software GmbH
+ * Author Lars Poeschel <poeschel@lemonage.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+void enable_cbmux_pin_mux(void);
+#endif
diff --git a/board/phytec/pcm051/mux.c b/board/phytec/pcm051/mux.c
new file mode 100644
index 0000000..4d3a1d5
--- /dev/null
+++ b/board/phytec/pcm051/mux.c
@@ -0,0 +1,128 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Lemonage Software GmbH
+ * Author Lars Poeschel <poeschel@lemonage.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},		/* MMC0_WP */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
+	{-1},
+};
+#endif
+
+#ifdef CONFIG_I2C
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+	{-1},
+};
+#endif
+
+#ifdef CONFIG_SPI
+static struct module_pin_mux spi0_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_SCLK */
+	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN)},			/* SPI0_D0 */
+	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_D1 */
+	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN)},			/* SPI0_CS0 */
+	{-1},
+};
+#endif
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},     /* RMII1_CRS */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},   /* RMII1_RXERR */
+	{OFFSET(mii1_txen), MODE(1)},               /* RMII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},               /* RMII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},               /* RMII1_TXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},    /* RMII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},    /* RMII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},    /* MDIO_CLK */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
+	{-1},
+};
+
+static struct module_pin_mux cbmux_pin_mux[] = {
+	{OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */
+	{OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN},	/* JP4 */
+	{-1},
+};
+
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+#endif
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux()
+{
+	configure_module_pin_mux(rmii1_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(cbmux_pin_mux);
+#ifdef CONFIG_NAND
+	configure_module_pin_mux(nand_pin_mux);
+#endif
+#ifdef CONFIG_SPI
+	configure_module_pin_mux(spi0_pin_mux);
+#endif
+}
diff --git a/board/schulercontrol/sc_sps_1/sc_sps_1.c b/board/schulercontrol/sc_sps_1/sc_sps_1.c
index fda191a..8138237 100644
--- a/board/schulercontrol/sc_sps_1/sc_sps_1.c
+++ b/board/schulercontrol/sc_sps_1/sc_sps_1.c
@@ -43,14 +43,14 @@
 int board_early_init_f(void)
 {
 	/* IO0 clock at 480MHz */
-	mx28_set_ioclk(MXC_IOCLK0, 480000);
+	mxs_set_ioclk(MXC_IOCLK0, 480000);
 	/* IO1 clock at 480MHz */
-	mx28_set_ioclk(MXC_IOCLK1, 480000);
+	mxs_set_ioclk(MXC_IOCLK1, 480000);
 
 	/* SSP0 clock at 96MHz */
-	mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
+	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
 	/* SSP2 clock at 96MHz */
-	mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
+	mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
 
 #ifdef	CONFIG_CMD_USB
 	mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT);
@@ -78,7 +78,7 @@
 #ifdef	CONFIG_CMD_MMC
 int board_mmc_init(bd_t *bis)
 {
-	return mxsmmc_initialize(bis, 0, NULL);
+	return mxsmmc_initialize(bis, 0, NULL, NULL);
 }
 #endif
 
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index ed4229e..48e6896 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -73,6 +73,17 @@
 	return !strncmp(header.config, "SKU#02", 6);
 }
 
+static int board_is_gp_evm(void)
+{
+	return !strncmp("A33515BB", header.name, 8);
+}
+
+int board_is_evm_15_or_later(void)
+{
+	return (!strncmp("A33515BB", header.name, 8) &&
+		strncmp("1.5", header.version, 3) <= 0);
+}
+
 /*
  * Read header information from EEPROM into global structure.
  */
@@ -197,6 +208,14 @@
 	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
+static const struct ddr_data ddr3_evm_data = {
+	.datardsratio0 = MT41J512M8RH125_RD_DQS,
+	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
+	.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
+	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
+	.datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
 static const struct cmd_control ddr3_cmd_ctrl_data = {
 	.cmd0csratio = MT41J128MJT125_RATIO,
 	.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
@@ -211,6 +230,20 @@
 	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 };
 
+static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
+	.cmd0csratio = MT41J512M8RH125_RATIO,
+	.cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
+	.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41J512M8RH125_RATIO,
+	.cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
+	.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41J512M8RH125_RATIO,
+	.cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
+	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+};
+
 static struct emif_regs ddr3_emif_reg_data = {
 	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
 	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
@@ -220,6 +253,16 @@
 	.zq_config = MT41J128MJT125_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
 };
+
+static struct emif_regs ddr3_evm_emif_reg_data = {
+	.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
+	.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
+	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
+	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
+	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
+	.zq_config = MT41J512M8RH125_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY,
+};
 #endif
 
 /*
@@ -301,6 +344,9 @@
 	if (board_is_evm_sk() || board_is_bone_lt())
 		config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
 			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
+	else if (board_is_evm_15_or_later())
+		config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
+			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data);
 	else
 		config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
 			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
@@ -393,7 +439,7 @@
 	uint32_t mac_hi, mac_lo;
 
 	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
-		debug("<ethaddr> not set. Reading from E-fuse\n");
+		printf("<ethaddr> not set. Reading from E-fuse\n");
 		/* try reading mac address from efuse */
 		mac_lo = readl(&cdev->macid0l);
 		mac_hi = readl(&cdev->macid0h);
@@ -425,6 +471,28 @@
 		printf("Error %d registering CPSW switch\n", rv);
 	else
 		n += rv;
+
+	/*
+	 *
+	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
+	 * operating points.  So we must set the TX clock delay feature
+	 * in the AR8051 PHY.  Since we only support a single ethernet
+	 * device in U-Boot, we only do this for the first instance.
+	 */
+#define AR8051_PHY_DEBUG_ADDR_REG	0x1d
+#define AR8051_PHY_DEBUG_DATA_REG	0x1e
+#define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
+#define AR8051_RGMII_TX_CLK_DLY		0x100
+
+	if (board_is_evm_sk() || board_is_gp_evm()) {
+		const char *devname;
+		devname = miiphy_get_current_dev();
+
+		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
+				AR8051_DEBUG_RGMII_CLK_DLY_REG);
+		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
+				AR8051_RGMII_TX_CLK_DLY);
+	}
 #endif
 try_usbether:
 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
diff --git a/board/ttcontrol/vision2/imximage_hynix.cfg b/board/ttcontrol/vision2/imximage_hynix.cfg
index ed531db..c1de94f 100644
--- a/board/ttcontrol/vision2/imximage_hynix.cfg
+++ b/board/ttcontrol/vision2/imximage_hynix.cfg
@@ -1,209 +1,228 @@
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic@denx.de.
-#
-# (C) Copyright 2010
-# Klaus Steinhammer TTECH Control Gmbh kst@tttech.com
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * (C) Copyright 2010
+ * Klaus Steinhammer TTECH Control Gmbh kst@tttech.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
 
-# Boot Device : one of
-# spi, nand, onenand, sd
-
+/*
+ * Boot Device : one of
+ * spi, nand, onenand, sd
+ */
 BOOT_FROM	spi
 
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type           Address        Value
-#
-# where:
-#	Addr-type register length (1,2 or 4 bytes)
-#	Address	  absolute address of the register
-#	value	  value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
 
-#######################
-### Disable WDOG ###
-#######################
+/*
+ * #######################
+ * ### Disable WDOG ###
+ * #######################
+ */
 DATA 2 0x73f98000 0x30
 
-#######################
-### SET DDR Clk     ###
-#######################
-
-# CCM: CBMCR - ddr_clk_sel: axi_b (133MHz)
+/*
+ * #######################
+ * ### SET DDR Clk     ###
+ * #######################
+ */
+/* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */
 DATA 4 0x73FD4018 0x000024C0
 
-# DOUBLE SPI CLK (13MHz->26 MHz Clock)
+/* DOUBLE SPI CLK (13MHz->26 MHz Clock) */
 DATA 4 0x73FD4038 0x2010241
 
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST */
 DATA 4 0x73fa8600 0x00000107
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST */
 DATA 4 0x73fa8604 0x00000107
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
 DATA 4 0x73fa8608 0x00000187
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
 DATA 4 0x73fa860c 0x00000187
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST */
 DATA 4 0x73fa8614 0x00000107
-#IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2)
+/* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) */
 DATA 4 0x73fa86a8 0x00000187
 
-#######################
-### Settings IOMUXC ###
-#######################
-
-# DDR IOMUX configuration
-# Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
-# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
+/*
+ * #######################
+ * ### Settings IOMUXC ###
+ * #######################
+ */
+/*
+ * DDR IOMUX configuration
+ * Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
+ * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
+ */
 DATA 4 0x73fa84b8 0x000000e7
-# PVTC MAX (at GPC, PGR reg)
-#DATA 4 0x73FD8004 0x1fc00000
+/* PVTC MAX (at GPC, PGR reg) */
+/* DATA 4 0x73FD8004 0x1fc00000 */
 
-#DQM0 DS high slew rate slow
+/* DQM0 DS high slew rate slow */
 DATA 4 0x73fa84d4 0x000000e4
-#DQM1 DS high slew rate slow
+/* DQM1 DS high slew rate slow */
 DATA 4 0x73fa84d8 0x000000e4
-#DQM2 DS high slew rate slow
+/* DQM2 DS high slew rate slow */
 DATA 4 0x73fa84dc 0x000000e4
-#DQM3 DS high slew rate slow
+/* DQM3 DS high slew rate slow */
 DATA 4 0x73fa84e0 0x000000e4
 
-#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */
 DATA 4 0x73fa84bc 0x000000c4
-#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */
 DATA 4 0x73fa84c0 0x000000c4
-#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */
 DATA 4 0x73fa84c4 0x000000c4
-#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */
 DATA 4 0x73fa84c8 0x000000c4
 
-#DRAM_DATA B0
+/* DRAM_DATA B0 */
 DATA 4 0x73fa88a4 0x00000004
-#DRAM_DATA B1
+/* DRAM_DATA B1 */
 DATA 4 0x73fa88ac 0x00000004
-#DRAM_DATA B2
+/* DRAM_DATA B2 */
 DATA 4 0x73fa88b8 0x00000004
-#DRAM_DATA B3
+/* DRAM_DATA B3 */
 DATA 4 0x73fa882c 0x00000004
 
-#DRAM_DATA B0 slew rate
+/* DRAM_DATA B0 slew rate */
 DATA 4 0x73fa8878 0x00000000
-#DRAM_DATA B1 slew rate
+/* DRAM_DATA B1 slew rate */
 DATA 4 0x73fa8880 0x00000000
-#DRAM_DATA B2 slew rate
+/* DRAM_DATA B2 slew rate */
 DATA 4 0x73fa888c 0x00000000
-#DRAM_DATA B3 slew rate
+/* DRAM_DATA B3 slew rate */
 DATA 4 0x73fa889c 0x00000000
 
-#######################
-### Configure SDRAM ###
-#######################
+/*
+ * #######################
+ * ### Configure SDRAM ###
+ * #######################
+ */
 
-# Configure CS0
-#######################
+/* Configure CS0 */
+/* ####################### */
 
-# ESDCTL0: Enable controller
+/* ESDCTL0: Enable controller */
 DATA 4 0x83fd9000 0x83220000
 
-# Init DRAM on CS0
-# ESDSCR: Precharge command
+/* Init DRAM on CS0 /
+/* ESDSCR: Precharge command */
 DATA 4 0x83fd9014 0x04008008
-# ESDSCR: Refresh command
+/* ESDSCR: Refresh command */
 DATA 4 0x83fd9014 0x00008010
-# ESDSCR: Refresh command
+/* ESDSCR: Refresh command */
 DATA 4 0x83fd9014 0x00008010
-# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
 DATA 4 0x83fd9014 0x00338018
-# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
+/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
 DATA 4 0x83fd9014 0x0020801a
-# ESDSCR
+/* ESDSCR */
 DATA 4 0x83fd9014 0x00008000
 
-# ESDSCR: EMR with full Drive strength
-#DATA 4 0x83fd9014 0x0000801a
+/* ESDSCR: EMR with full Drive strength */
+/* DATA 4 0x83fd9014 0x0000801a */
 
-# ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8
+/* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */
 DATA 4 0x83fd9000 0xC3220000
 
-# ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
-#          tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
-#DATA 4 0x83fd9004 0xC33574AA
-
-#micron mDDR
-# ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
-# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
-#DATA 4 0x83FD9004 0x101564a8
-
-#hynix mDDR
-# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
-# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+/*
+ * ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ *          tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+ * DATA 4 0x83fd9004 0xC33574AA
+ */
+/*
+ * micron mDDR
+ * ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ * DATA 4 0x83FD9004 0x101564a8
+ */
+/*
+ * hynix mDDR
+ * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ */
 DATA 4 0x83FD9004 0x704564a8
 
-# ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2
+/* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */
 DATA 4 0x83fd9010 0x000a1700
 
-# Configure CS1
-#######################
+/* Configure CS1 */
+/* ####################### */
 
-# ESDCTL1: Enable controller
+/* ESDCTL1: Enable controller */
 DATA 4 0x83fd9008 0x83220000
 
-# Init DRAM on CS1
-# ESDSCR: Precharge command
+/* Init DRAM on CS1 */
+/* ESDSCR: Precharge command */
 DATA 4 0x83fd9014 0x0400800c
-# ESDSCR: Refresh command
+/* ESDSCR: Refresh command */
 DATA 4 0x83fd9014 0x00008014
-# ESDSCR: Refresh command
+/* ESDSCR: Refresh command */
 DATA 4 0x83fd9014 0x00008014
-# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
 DATA 4 0x83fd9014 0x0033801c
-# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
+/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
 DATA 4 0x83fd9014 0x0020801e
-# ESDSCR
+/* ESDSCR */
 DATA 4 0x83fd9014 0x00008004
 
-# ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8
+/* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */
 DATA 4 0x83fd9008 0xC3220000
-
-# ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
-#          tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
-#DATA 4 0x83fd900c 0xC33574AA
-
-#micron mDDR
-# ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
-# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
-#DATA 4 0x83FD900C 0x101564a8
-
-#hynix mDDR
-# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
-# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+/*
+ * ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ *          tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+ * DATA 4 0x83fd900c 0xC33574AA
+ */
+/*
+ * micron mDDR
+ * ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ * DATA 4 0x83FD900C 0x101564a8
+ */
+/*
+ * hynix mDDR
+ * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ */
 DATA 4 0x83FD900C 0x704564a8
 
-# ESDSCR (mDRAM configuration finished)
+/* ESDSCR (mDRAM configuration finished) */
 DATA 4 0x83FD9014 0x00000004
 
-# ESDSCR - clear "configuration request" bit
+/* ESDSCR - clear "configuration request" bit */
 DATA 4 0x83fd9014 0x00000000
diff --git a/board/woodburn/imximage.cfg b/board/woodburn/imximage.cfg
index b4cc8ec..ba42a5e 100644
--- a/board/woodburn/imximage.cfg
+++ b/board/woodburn/imximage.cfg
@@ -1,4 +1,4 @@
 BOOT_FROM      sd
 
-# DDR2 init
+/* DDR2 init */
 DATA 4 0xB8001010 0x00000304
diff --git a/board/woodburn/woodburn.c b/board/woodburn/woodburn.c
index d74f360..5b044a9 100644
--- a/board/woodburn/woodburn.c
+++ b/board/woodburn/woodburn.c
@@ -241,9 +241,10 @@
 	mxc_iomux_set_input(MUX_IN_GPIO1_IN_7, 0x1);
 	gpio_direction_input(GPIO_MMC_CD);
 
+	/* MMC Write Protection on GPIO1_8 */
 	mxc_request_iomux(MX35_PIN_FST, MUX_CONFIG_ALT5);
 	mxc_iomux_set_input(MUX_IN_GPIO1_IN_8, 0x1);
-	gpio_direction_output(GPIO_MMC_WP, 0);
+	gpio_direction_input(GPIO_MMC_WP);
 
 	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 
diff --git a/boards.cfg b/boards.cfg
index 98f7a14..b1319aa 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -191,7 +191,9 @@
 zmx25                        arm         arm926ejs   zmx25               syteco         mx25
 imx27lite                    arm         arm926ejs   imx27lite           logicpd        mx27
 magnesium                    arm         arm926ejs   imx27lite           logicpd        mx27
+mx23_olinuxino               arm         arm926ejs   mx23_olinuxino      olimex         mxs		mx23_olinuxino
 apx4devkit                   arm         arm926ejs   apx4devkit          bluegiga       mxs		apx4devkit
+mx23evk                      arm         arm926ejs   mx23evk             freescale      mxs		mx23evk
 m28evk                       arm         arm926ejs   m28evk              denx           mxs		m28evk
 mx28evk                      arm         arm926ejs   mx28evk             freescale      mxs		mx28evk
 sc_sps_1                     arm         arm926ejs   sc_sps_1            schulercontrol mxs
@@ -236,6 +238,7 @@
 am335x_evm_uart3             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL4,CONS_INDEX=4
 am335x_evm_uart4             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL5,CONS_INDEX=5
 am335x_evm_uart5             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL6,CONS_INDEX=6
+pcm051                       arm         armv7       pcm051              phytec         am33xx      pcm051
 highbank                     arm         armv7       highbank            -              highbank
 mx51_efikamx                 arm         armv7       mx51_efikamx        genesi         mx5		mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
 mx51_efikasb                 arm         armv7       mx51_efikamx        genesi         mx5		mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
@@ -255,10 +258,10 @@
 omap3_overo                  arm         armv7       overo               -              omap3
 omap3_pandora                arm         armv7       pandora             -              omap3
 dig297                       arm         armv7       dig297              comelit        omap3
-igep0020                     arm         armv7       igep0020            isee           omap3		igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND
-igep0020_nand                arm         armv7       igep0020            isee           omap3		igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND
-igep0030                     arm         armv7       igep0030            isee           omap3		igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND
-igep0030_nand                arm         armv7       igep0030            isee           omap3		igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND
+igep0020                     arm         armv7       igep00x0            isee           omap3		igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND
+igep0020_nand                arm         armv7       igep00x0            isee           omap3		igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND
+igep0030                     arm         armv7       igep00x0            isee           omap3		igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND
+igep0030_nand                arm         armv7       igep00x0            isee           omap3		igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND
 am3517_evm                   arm         armv7       am3517evm           logicpd        omap3
 mt_ventoux                   arm         armv7       mt_ventoux          teejet         omap3
 omap3_zoom1                  arm         armv7       zoom1               logicpd        omap3
@@ -290,6 +293,8 @@
 seaboard                     arm         armv7:arm720t seaboard          nvidia         tegra20
 ventana                      arm         armv7:arm720t ventana           nvidia         tegra20
 whistler                     arm         armv7:arm720t whistler          nvidia         tegra20
+cardhu                       arm         armv7:arm720t cardhu            nvidia         tegra30
+dalmore                      arm         armv7:arm720t dalmore           nvidia         tegra114
 colibri_t20_iris             arm         armv7:arm720t colibri_t20_iris  toradex        tegra20
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
 snowball                     arm         armv7       snowball               st-ericsson    u8500
@@ -1118,7 +1123,5 @@
 grsim                        sparc       leon3       -                   gaisler
 gr_xc3s_1500                 sparc       leon3       -                   gaisler
 coreboot-x86                 x86         x86        coreboot            chromebook-x86 coreboot    coreboot:SYS_TEXT_BASE=0x01110000
-eNET                         x86         x86        eNET                -              sc520       eNET:SYS_TEXT_BASE=0x38040000
-eNET_SRAM                    x86         x86        eNET                -              sc520       eNET:SYS_TEXT_BASE=0x19000000
 # Target                     ARCH        CPU         Board name          Vendor	        SoC         Options
 ########################################################################################################################
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 7ae5d5b..f0338ba 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -47,7 +47,6 @@
 #endif
 
 #if defined(CONFIG_OF_LIBFDT)
-#include <fdt.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 #endif
diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c
index 9e2de34..6eec947 100644
--- a/common/cmd_fdt.c
+++ b/common/cmd_fdt.c
@@ -29,7 +29,6 @@
 #include <linux/ctype.h>
 #include <linux/types.h>
 #include <asm/global_data.h>
-#include <fdt.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 6b9fa05..812acb4 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -28,7 +28,6 @@
 #include <linux/ctype.h>
 #include <linux/types.h>
 #include <asm/global_data.h>
-#include <fdt.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <exports.h>
@@ -52,7 +51,7 @@
 u32 fdt_getprop_u32_default(const void *fdt, const char *path,
 				const char *prop, const u32 dflt)
 {
-	const u32 *val;
+	const fdt32_t *val;
 	int off;
 
 	off = fdt_path_offset(fdt, path);
@@ -86,7 +85,7 @@
 	if (nodeoff < 0)
 		return nodeoff;
 
-	if ((!create) && (fdt_get_property(fdt, nodeoff, prop, 0) == NULL))
+	if ((!create) && (fdt_get_property(fdt, nodeoff, prop, NULL) == NULL))
 		return 0; /* create flag not set; so exit quietly */
 
 	return fdt_setprop(fdt, nodeoff, prop, val, len);
@@ -150,7 +149,7 @@
 {
 	int   nodeoffset;
 	int   err, j, total;
-	u32   tmp;
+	fdt32_t  tmp;
 	const char *path;
 	uint64_t addr, size;
 
@@ -189,7 +188,7 @@
 
 	path = fdt_getprop(fdt, nodeoffset, "linux,initrd-start", NULL);
 	if ((path == NULL) || force) {
-		tmp = __cpu_to_be32(initrd_start);
+		tmp = cpu_to_fdt32(initrd_start);
 		err = fdt_setprop(fdt, nodeoffset,
 			"linux,initrd-start", &tmp, sizeof(tmp));
 		if (err < 0) {
@@ -198,7 +197,7 @@
 				fdt_strerror(err));
 			return err;
 		}
-		tmp = __cpu_to_be32(initrd_end);
+		tmp = cpu_to_fdt32(initrd_end);
 		err = fdt_setprop(fdt, nodeoffset,
 			"linux,initrd-end", &tmp, sizeof(tmp));
 		if (err < 0) {
@@ -301,8 +300,8 @@
 void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop,
 			  u32 val, int create)
 {
-	val = cpu_to_fdt32(val);
-	do_fixup_by_path(fdt, path, prop, &val, sizeof(val), create);
+	fdt32_t tmp = cpu_to_fdt32(val);
+	do_fixup_by_path(fdt, path, prop, &tmp, sizeof(tmp), create);
 }
 
 void do_fixup_by_prop(void *fdt,
@@ -320,7 +319,7 @@
 #endif
 	off = fdt_node_offset_by_prop_value(fdt, -1, pname, pval, plen);
 	while (off != -FDT_ERR_NOTFOUND) {
-		if (create || (fdt_get_property(fdt, off, prop, 0) != NULL))
+		if (create || (fdt_get_property(fdt, off, prop, NULL) != NULL))
 			fdt_setprop(fdt, off, prop, val, len);
 		off = fdt_node_offset_by_prop_value(fdt, off, pname, pval, plen);
 	}
@@ -330,8 +329,8 @@
 			  const char *pname, const void *pval, int plen,
 			  const char *prop, u32 val, int create)
 {
-	val = cpu_to_fdt32(val);
-	do_fixup_by_prop(fdt, pname, pval, plen, prop, &val, 4, create);
+	fdt32_t tmp = cpu_to_fdt32(val);
+	do_fixup_by_prop(fdt, pname, pval, plen, prop, &tmp, 4, create);
 }
 
 void do_fixup_by_compat(void *fdt, const char *compat,
@@ -347,7 +346,7 @@
 #endif
 	off = fdt_node_offset_by_compatible(fdt, -1, compat);
 	while (off != -FDT_ERR_NOTFOUND) {
-		if (create || (fdt_get_property(fdt, off, prop, 0) != NULL))
+		if (create || (fdt_get_property(fdt, off, prop, NULL) != NULL))
 			fdt_setprop(fdt, off, prop, val, len);
 		off = fdt_node_offset_by_compatible(fdt, off, compat);
 	}
@@ -356,8 +355,8 @@
 void do_fixup_by_compat_u32(void *fdt, const char *compat,
 			    const char *prop, u32 val, int create)
 {
-	val = cpu_to_fdt32(val);
-	do_fixup_by_compat(fdt, compat, prop, &val, 4, create);
+	fdt32_t tmp = cpu_to_fdt32(val);
+	do_fixup_by_compat(fdt, compat, prop, &tmp, 4, create);
 }
 
 /*
@@ -367,7 +366,7 @@
  */
 static int get_cells_len(void *blob, char *nr_cells_name)
 {
-	const u32 *cell;
+	const fdt32_t *cell;
 
 	cell = fdt_getprop(blob, 0, nr_cells_name, NULL);
 	if (cell && fdt32_to_cpu(*cell) == 2)
@@ -388,13 +387,21 @@
 	}
 }
 
+#define MEMORY_BANKS_MAX 4
 int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks)
 {
 	int err, nodeoffset;
 	int addr_cell_len, size_cell_len, len;
-	u8 tmp[banks * 16]; /* Up to 64-bit address + 64-bit size */
+	u8 tmp[MEMORY_BANKS_MAX * 16]; /* Up to 64-bit address + 64-bit size */
 	int bank;
 
+	if (banks > MEMORY_BANKS_MAX) {
+		printf("%s: num banks %d exceeds hardcoded limit %d."
+		       " Recompile with higher MEMORY_BANKS_MAX?\n",
+		       __FUNCTION__, banks, MEMORY_BANKS_MAX);
+		return -1;
+	}
+
 	err = fdt_check_header(blob);
 	if (err < 0) {
 		printf("%s: %s\n", __FUNCTION__, fdt_strerror(err));
@@ -903,11 +910,11 @@
 }
 
 /* Helper to read a big number; size is in cells (not bytes) */
-static inline u64 of_read_number(const __be32 *cell, int size)
+static inline u64 of_read_number(const fdt32_t *cell, int size)
 {
 	u64 r = 0;
 	while (size--)
-		r = (r << 32) | be32_to_cpu(*(cell++));
+		r = (r << 32) | fdt32_to_cpu(*(cell++));
 	return r;
 }
 
@@ -921,7 +928,7 @@
 
 /* Debug utility */
 #ifdef DEBUG
-static void of_dump_addr(const char *s, const u32 *addr, int na)
+static void of_dump_addr(const char *s, const fdt32_t *addr, int na)
 {
 	printf("%s", s);
 	while(na--)
@@ -929,7 +936,7 @@
 	printf("\n");
 }
 #else
-static void of_dump_addr(const char *s, const u32 *addr, int na) { }
+static void of_dump_addr(const char *s, const fdt32_t *addr, int na) { }
 #endif
 
 /* Callbacks for bus specific translators */
@@ -938,21 +945,21 @@
 	const char	*addresses;
 	void		(*count_cells)(void *blob, int parentoffset,
 				int *addrc, int *sizec);
-	u64		(*map)(u32 *addr, const u32 *range,
+	u64		(*map)(fdt32_t *addr, const fdt32_t *range,
 				int na, int ns, int pna);
-	int		(*translate)(u32 *addr, u64 offset, int na);
+	int		(*translate)(fdt32_t *addr, u64 offset, int na);
 };
 
 /* Default translator (generic bus) */
 static void of_bus_default_count_cells(void *blob, int parentoffset,
 					int *addrc, int *sizec)
 {
-	const u32 *prop;
+	const fdt32_t *prop;
 
 	if (addrc) {
 		prop = fdt_getprop(blob, parentoffset, "#address-cells", NULL);
 		if (prop)
-			*addrc = be32_to_cpup((u32 *)prop);
+			*addrc = be32_to_cpup(prop);
 		else
 			*addrc = 2;
 	}
@@ -960,13 +967,13 @@
 	if (sizec) {
 		prop = fdt_getprop(blob, parentoffset, "#size-cells", NULL);
 		if (prop)
-			*sizec = be32_to_cpup((u32 *)prop);
+			*sizec = be32_to_cpup(prop);
 		else
 			*sizec = 1;
 	}
 }
 
-static u64 of_bus_default_map(u32 *addr, const u32 *range,
+static u64 of_bus_default_map(fdt32_t *addr, const fdt32_t *range,
 		int na, int ns, int pna)
 {
 	u64 cp, s, da;
@@ -983,14 +990,14 @@
 	return da - cp;
 }
 
-static int of_bus_default_translate(u32 *addr, u64 offset, int na)
+static int of_bus_default_translate(fdt32_t *addr, u64 offset, int na)
 {
 	u64 a = of_read_number(addr, na);
 	memset(addr, 0, na * 4);
 	a += offset;
 	if (na > 1)
-		addr[na - 2] = a >> 32;
-	addr[na - 1] = a & 0xffffffffu;
+		addr[na - 2] = cpu_to_fdt32(a >> 32);
+	addr[na - 1] = cpu_to_fdt32(a & 0xffffffffu);
 
 	return 0;
 }
@@ -1008,10 +1015,10 @@
 };
 
 static int of_translate_one(void * blob, int parent, struct of_bus *bus,
-			    struct of_bus *pbus, u32 *addr,
+			    struct of_bus *pbus, fdt32_t *addr,
 			    int na, int ns, int pna, const char *rprop)
 {
-	const u32 *ranges;
+	const fdt32_t *ranges;
 	int rlen;
 	int rone;
 	u64 offset = OF_BAD_ADDR;
@@ -1028,7 +1035,7 @@
 	 * to translate addresses that aren't supposed to be translated in
 	 * the first place. --BenH.
 	 */
-	ranges = (u32 *)fdt_getprop(blob, parent, rprop, &rlen);
+	ranges = fdt_getprop(blob, parent, rprop, &rlen);
 	if (ranges == NULL || rlen == 0) {
 		offset = of_read_number(addr, na);
 		memset(addr, 0, pna * 4);
@@ -1070,12 +1077,12 @@
  * that can be mapped to a cpu physical address). This is not really specified
  * that way, but this is traditionally the way IBM at least do things
  */
-u64 __of_translate_address(void *blob, int node_offset, const u32 *in_addr,
-			   const char *rprop)
+static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in_addr,
+				  const char *rprop)
 {
 	int parent;
 	struct of_bus *bus, *pbus;
-	u32 addr[OF_MAX_ADDR_CELLS];
+	fdt32_t addr[OF_MAX_ADDR_CELLS];
 	int na, ns, pna, pns;
 	u64 result = OF_BAD_ADDR;
 
@@ -1143,7 +1150,7 @@
 	return result;
 }
 
-u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr)
+u64 fdt_translate_address(void *blob, int node_offset, const fdt32_t *in_addr)
 {
 	return __of_translate_address(blob, node_offset, in_addr, "ranges");
 }
@@ -1162,7 +1169,7 @@
 {
 	int len, off = fdt_node_offset_by_compatible(blob, -1, compat);
 	while (off != -FDT_ERR_NOTFOUND) {
-		u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
+		const fdt32_t *reg = fdt_getprop(blob, off, "reg", &len);
 		if (reg) {
 			if (compat_off == fdt_translate_address(blob, off, reg))
 				return off;
@@ -1356,7 +1363,7 @@
 int fdt_verify_alias_address(void *fdt, int anode, const char *alias, u64 addr)
 {
 	const char *path;
-	const u32 *reg;
+	const fdt32_t *reg;
 	int node, len;
 	u64 dt_addr;
 
@@ -1398,11 +1405,11 @@
 {
 	int size;
 	u32 naddr;
-	const u32 *prop;
+	const fdt32_t *prop;
 
 	prop = fdt_getprop(fdt, node, "#address-cells", &size);
 	if (prop && size == 4)
-		naddr = *prop;
+		naddr = be32_to_cpup(prop);
 	else
 		naddr = 2;
 
diff --git a/common/image.c b/common/image.c
index 95498e6..ae1a9d3 100644
--- a/common/image.c
+++ b/common/image.c
@@ -47,7 +47,6 @@
 #include <image.h>
 
 #if defined(CONFIG_FIT) || defined(CONFIG_OF_LIBFDT)
-#include <fdt.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 #endif
diff --git a/doc/README.fec_mxc b/doc/README.fec_mxc
new file mode 100644
index 0000000..72a1d59
--- /dev/null
+++ b/doc/README.fec_mxc
@@ -0,0 +1,27 @@
+U-boot config options used in fec_mxc.c
+
+CONFIG_FEC_MXC
+	Selects fec_mxc.c to be compiled into u-boot.
+
+CONFIG_MII
+	Must be defined if CONFIG_FEC_MXC is defined.
+
+CONFIG_FEC_XCV_TYPE
+	Defaults to MII100 for 100 Base-tx.
+	RGMII selects 1000 Base-tx reduced pin count interface.
+	RMII selects 100 Base-tx reduced pin count interface.
+
+CONFIG_FEC_MXC_SWAP_PACKET
+	Forced on iff MX28.
+	Swaps the bytes order of all words(4 byte units) in the packet.
+	This should not be specified by a board file. It is cpu specific.
+
+CONFIG_PHYLIB
+	fec_mxc supports PHYLIB and should be used for new boards.
+
+CONFIG_FEC_MXC_NO_ANEG
+	Relevant only if PHYLIB not used. Skips auto-negotiation restart.
+
+CONFIG_FEC_MXC_PHYADDR
+	Optional, selects the exact phy address that should be connected
+	and function fecmxc_initialize will try to initialize it.
diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index 37a941c..0c1cd83 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -223,13 +223,19 @@
 	struct mxs_apbh_regs *apbh_regs =
 		(struct mxs_apbh_regs *)MXS_APBH_BASE;
 	int ret;
+#if defined(CONFIG_MX23)
+	uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
+	uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
+#elif defined(CONFIG_MX28)
+	uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
+	uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
+#endif
 
 	ret = mxs_dma_validate_chan(channel);
 	if (ret)
 		return ret;
 
-	writel(1 << (channel + APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET),
-		&apbh_regs->hw_apbh_channel_ctrl_set);
+	writel(1 << (channel + offset), setreg);
 
 	return 0;
 }
diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index 024df59..a72f66c 100644
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -47,16 +47,31 @@
 struct mxsmmc_priv {
 	int			id;
 	struct mxs_ssp_regs	*regs;
-	uint32_t		clkseq_bypass;
-	uint32_t		*clkctrl_ssp;
 	uint32_t		buswidth;
 	int			(*mmc_is_wp)(int);
+	int			(*mmc_cd)(int);
 	struct mxs_dma_desc	*desc;
 };
 
+#if defined(CONFIG_MX23)
+static const unsigned int mxsmmc_id_offset = 1;
+#elif defined(CONFIG_MX28)
+static const unsigned int mxsmmc_id_offset = 0;
+#endif
+
 #define	MXSMMC_MAX_TIMEOUT	10000
 #define MXSMMC_SMALL_TRANSFER	512
 
+static int mxsmmc_cd(struct mxsmmc_priv *priv)
+{
+	struct mxs_ssp_regs *ssp_regs = priv->regs;
+
+	if (priv->mmc_cd)
+		return priv->mmc_cd(priv->id);
+
+	return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
+}
+
 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
 {
 	struct mxs_ssp_regs *ssp_regs = priv->regs;
@@ -122,7 +137,7 @@
 	priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
 				(data_count << MXS_DMA_DESC_BYTES_OFFSET);
 
-	dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
+	dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id + mxsmmc_id_offset;
 	mxs_dma_desc_append(dmach, priv->desc);
 	if (mxs_dma_go(dmach)) {
 		bounce_buffer_stop(&bbstate);
@@ -168,7 +183,7 @@
 	}
 
 	/* See if card is present */
-	if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) {
+	if (!mxsmmc_cd(priv)) {
 		printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
 		return NO_CARD_ERR;
 	}
@@ -213,14 +228,25 @@
 		}
 
 		ctrl0 |= SSP_CTRL0_DATA_XFER;
+
+		reg = data->blocksize * data->blocks;
+#if defined(CONFIG_MX23)
+		ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
+
+		clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
+			SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
+			((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
+			((ffs(data->blocksize) - 1) <<
+				SSP_CMD0_BLOCK_SIZE_OFFSET));
+#elif defined(CONFIG_MX28)
+		writel(reg, &ssp_regs->hw_ssp_xfer_size);
+
 		reg = ((data->blocks - 1) <<
 			SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
 			((ffs(data->blocksize) - 1) <<
 			SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
 		writel(reg, &ssp_regs->hw_ssp_block_size);
-
-		reg = data->blocksize * data->blocks;
-		writel(reg, &ssp_regs->hw_ssp_xfer_size);
+#endif
 	}
 
 	/* Kick off the command */
@@ -306,7 +332,7 @@
 
 	/* Set the clock speed */
 	if (mmc->clock)
-		mx28_set_ssp_busclock(priv->id, mmc->clock / 1000);
+		mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
 
 	switch (mmc->bus_width) {
 	case 1:
@@ -336,14 +362,20 @@
 	/* Reset SSP */
 	mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
 
-	/* 8 bits word length in MMC mode */
-	clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
-		SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK |
-		SSP_CTRL1_DMA_ENABLE,
-		SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS);
+	/* Reconfigure the SSP block for MMC operation */
+	writel(SSP_CTRL1_SSP_MODE_SD_MMC |
+		SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
+		SSP_CTRL1_DMA_ENABLE |
+		SSP_CTRL1_POLARITY |
+		SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
+		SSP_CTRL1_DATA_CRC_IRQ_EN |
+		SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
+		SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
+		SSP_CTRL1_RESP_ERR_IRQ_EN,
+		&ssp_regs->hw_ssp_ctrl1_set);
 
 	/* Set initial bit clock 400 KHz */
-	mx28_set_ssp_busclock(priv->id, 400);
+	mxs_set_ssp_busclock(priv->id, 400);
 
 	/* Send initial 74 clock cycles (185 us @ 400 KHz)*/
 	writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
@@ -353,13 +385,21 @@
 	return 0;
 }
 
-int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
+int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
 {
-	struct mxs_clkctrl_regs *clkctrl_regs =
-		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	struct mmc *mmc = NULL;
 	struct mxsmmc_priv *priv = NULL;
 	int ret;
+#if defined(CONFIG_MX23)
+	const unsigned int mxsmmc_max_id = 2;
+	const unsigned int mxsmmc_clk_id = 0;
+#elif defined(CONFIG_MX28)
+	const unsigned int mxsmmc_max_id = 4;
+	const unsigned int mxsmmc_clk_id = id;
+#endif
+
+	if (id >= mxsmmc_max_id)
+		return -ENODEV;
 
 	mmc = malloc(sizeof(struct mmc));
 	if (!mmc)
@@ -378,34 +418,14 @@
 		return -ENOMEM;
 	}
 
-	ret = mxs_dma_init_channel(id);
+	ret = mxs_dma_init_channel(id + mxsmmc_id_offset);
 	if (ret)
 		return ret;
 
 	priv->mmc_is_wp = wp;
+	priv->mmc_cd = cd;
 	priv->id = id;
-	switch (id) {
-	case 0:
-		priv->regs = (struct mxs_ssp_regs *)MXS_SSP0_BASE;
-		priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0;
-		priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0;
-		break;
-	case 1:
-		priv->regs = (struct mxs_ssp_regs *)MXS_SSP1_BASE;
-		priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1;
-		priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1;
-		break;
-	case 2:
-		priv->regs = (struct mxs_ssp_regs *)MXS_SSP2_BASE;
-		priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2;
-		priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2;
-		break;
-	case 3:
-		priv->regs = (struct mxs_ssp_regs *)MXS_SSP3_BASE;
-		priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3;
-		priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3;
-		break;
-	}
+	priv->regs = mxs_ssp_regs_by_bus(id);
 
 	sprintf(mmc->name, "MXS MMC");
 	mmc->send_cmd = mxsmmc_send_cmd;
@@ -426,7 +446,7 @@
 	 * CLOCK_RATE could be any integer from 0 to 255.
 	 */
 	mmc->f_min = 400000;
-	mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2;
+	mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
 	mmc->b_max = 0x20;
 
 	mmc_register(mmc);
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index 32b76e0..9288672 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -97,7 +97,7 @@
 		.name = "S25FL129P_64K",
 	},
 	{
-		.idcode1 = 0x2019,
+		.idcode1 = 0x0219,
 		.idcode2 = 0x4d01,
 		.pages_per_sector = 256,
 		.nr_sectors = 512,
diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c
index 9ec938a..8a19344 100644
--- a/drivers/mtd/spi/stmicro.c
+++ b/drivers/mtd/spi/stmicro.c
@@ -93,12 +93,30 @@
 		.name = "M25P128",
 	},
 	{
+		.id = 0xba16,
+		.pages_per_sector = 256,
+		.nr_sectors = 64,
+		.name = "N25Q32",
+	},
+	{
+		.id = 0xbb16,
+		.pages_per_sector = 256,
+		.nr_sectors = 64,
+		.name = "N25Q32A",
+	},
+	{
 		.id = 0xba17,
 		.pages_per_sector = 256,
 		.nr_sectors = 128,
 		.name = "N25Q064",
 	},
 	{
+		.id = 0xbb17,
+		.pages_per_sector = 256,
+		.nr_sectors = 128,
+		.name = "N25Q64A",
+	},
+	{
 		.id = 0xba18,
 		.pages_per_sector = 256,
 		.nr_sectors = 256,
@@ -116,6 +134,12 @@
 		.nr_sectors = 512,
 		.name = "N25Q256",
 	},
+	{
+		.id = 0xbb19,
+		.pages_per_sector = 256,
+		.nr_sectors = 512,
+		.name = "N25Q256A",
+	},
 };
 
 struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode)
diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c
index f6aab3d..4418302 100644
--- a/drivers/mtd/spi/winbond.c
+++ b/drivers/mtd/spi/winbond.c
@@ -67,6 +67,11 @@
 		.nr_blocks		= 128,
 		.name			= "W25Q80",
 	},
+	{
+		.id			= 0x6017,
+		.nr_blocks		= 128,
+		.name			= "W25Q64DW",
+	},
 };
 
 struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 3e232c7..4dbcdca 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -135,15 +135,15 @@
 	return val;
 }
 
-static void fec_mii_setspeed(struct fec_priv *fec)
+static void fec_mii_setspeed(struct ethernet_regs *eth)
 {
 	/*
 	 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
 	 * and do not drop the Preamble.
 	 */
 	writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
-			&fec->eth->mii_speed);
-	debug("%s: mii_speed %08x\n", __func__, readl(&fec->eth->mii_speed));
+			&eth->mii_speed);
+	debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));
 }
 
 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
@@ -392,21 +392,6 @@
 	return 0;
 }
 
-static void fec_eth_phy_config(struct eth_device *dev)
-{
-#ifdef CONFIG_PHYLIB
-	struct fec_priv *fec = (struct fec_priv *)dev->priv;
-	struct phy_device *phydev;
-
-	phydev = phy_connect(fec->bus, fec->phy_id, dev,
-			PHY_INTERFACE_MODE_RGMII);
-	if (phydev) {
-		fec->phydev = phydev;
-		phy_config(phydev);
-	}
-#endif
-}
-
 /*
  * Do initial configuration of the FEC registers
  */
@@ -511,9 +496,7 @@
 #endif
 
 #ifdef CONFIG_PHYLIB
-	if (!fec->phydev)
-		fec_eth_phy_config(edev);
-	if (fec->phydev) {
+	{
 		/* Start up the PHY */
 		int ret = phy_startup(fec->phydev);
 
@@ -523,8 +506,6 @@
 			return ret;
 		}
 		speed = fec->phydev->speed;
-	} else {
-		speed = _100BASET;
 	}
 #else
 	miiphy_wait_aneg(edev);
@@ -611,7 +592,7 @@
 	fec_reg_setup(fec);
 
 	if (fec->xcv_type != SEVENWIRE)
-		fec_mii_setspeed(fec);
+		fec_mii_setspeed(fec->bus->priv);
 
 	/*
 	 * Set Opcode/Pause Duration Register
@@ -915,11 +896,21 @@
 	return len;
 }
 
-static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
+static void fec_set_dev_name(char *dest, int dev_id)
+{
+	sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
+}
+
+#ifdef CONFIG_PHYLIB
+int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
+		struct mii_dev *bus, struct phy_device *phydev)
+#else
+static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
+		struct mii_dev *bus, int phy_id)
+#endif
 {
 	struct eth_device *edev;
 	struct fec_priv *fec;
-	struct mii_dev *bus;
 	unsigned char ethaddr[6];
 	uint32_t start;
 	int ret = 0;
@@ -966,53 +957,25 @@
 	}
 
 	fec_reg_setup(fec);
-	fec_mii_setspeed(fec);
-
-	if (dev_id == -1) {
-		sprintf(edev->name, "FEC");
-		fec->dev_id = 0;
-	} else {
-		sprintf(edev->name, "FEC%i", dev_id);
-		fec->dev_id = dev_id;
-	}
-	fec->phy_id = phy_id;
-
-	bus = mdio_alloc();
-	if (!bus) {
-		printf("mdio_alloc failed\n");
-		ret = -ENOMEM;
-		goto err3;
-	}
-	bus->read = fec_phy_read;
-	bus->write = fec_phy_write;
-	sprintf(bus->name, edev->name);
-#ifdef CONFIG_MX28
-	/*
-	 * The i.MX28 has two ethernet interfaces, but they are not equal.
-	 * Only the first one can access the MDIO bus.
-	 */
-	bus->priv = (struct ethernet_regs *)MXS_ENET0_BASE;
+	fec_set_dev_name(edev->name, dev_id);
+	fec->dev_id = (dev_id == -1) ? 0 : dev_id;
+	fec->bus = bus;
+	fec_mii_setspeed(bus->priv);
+#ifdef CONFIG_PHYLIB
+	fec->phydev = phydev;
+	phy_connect_dev(phydev, edev);
+	/* Configure phy */
+	phy_config(phydev);
 #else
-	bus->priv = fec->eth;
+	fec->phy_id = phy_id;
 #endif
-	ret = mdio_register(bus);
-	if (ret) {
-		printf("mdio_register failed\n");
-		free(bus);
-		ret = -ENOMEM;
-		goto err3;
-	}
-	fec->bus = bus;
 	eth_register(edev);
 
 	if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
 		debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
 		memcpy(edev->enetaddr, ethaddr, 6);
 	}
-	/* Configure phy */
-	fec_eth_phy_config(edev);
 	return ret;
-
 err3:
 	free(fec);
 err2:
@@ -1021,27 +984,80 @@
 	return ret;
 }
 
-#ifndef CONFIG_FEC_MXC_MULTI
-int fecmxc_initialize(bd_t *bd)
+struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
 {
-	int lout = 1;
+	struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
+	struct mii_dev *bus;
+	int ret;
 
-	debug("eth_init: fec_probe(bd)\n");
-	lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+	bus = mdio_alloc();
+	if (!bus) {
+		printf("mdio_alloc failed\n");
+		return NULL;
+	}
+	bus->read = fec_phy_read;
+	bus->write = fec_phy_write;
+	bus->priv = eth;
+	fec_set_dev_name(bus->name, dev_id);
 
-	return lout;
+	ret = mdio_register(bus);
+	if (ret) {
+		printf("mdio_register failed\n");
+		free(bus);
+		return NULL;
+	}
+	fec_mii_setspeed(eth);
+	return bus;
 }
-#endif
 
 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
 {
-	int lout = 1;
+	uint32_t base_mii;
+	struct mii_dev *bus = NULL;
+#ifdef CONFIG_PHYLIB
+	struct phy_device *phydev = NULL;
+#endif
+	int ret;
 
+#ifdef CONFIG_MX28
+	/*
+	 * The i.MX28 has two ethernet interfaces, but they are not equal.
+	 * Only the first one can access the MDIO bus.
+	 */
+	base_mii = MXS_ENET0_BASE;
+#else
+	base_mii = addr;
+#endif
 	debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
-	lout = fec_probe(bd, dev_id, phy_id, addr);
+	bus = fec_get_miibus(base_mii, dev_id);
+	if (!bus)
+		return -ENOMEM;
+#ifdef CONFIG_PHYLIB
+	phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
+	if (!phydev) {
+		free(bus);
+		return -ENOMEM;
+	}
+	ret = fec_probe(bd, dev_id, addr, bus, phydev);
+#else
+	ret = fec_probe(bd, dev_id, addr, bus, phy_id);
+#endif
+	if (ret) {
+#ifdef CONFIG_PHYLIB
+		free(phydev);
+#endif
+		free(bus);
+	}
+	return ret;
+}
 
-	return lout;
+#ifdef CONFIG_FEC_MXC_PHYADDR
+int fecmxc_initialize(bd_t *bd)
+{
+	return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
+			IMX_FEC_BASE);
 }
+#endif
 
 #ifndef CONFIG_PHYLIB
 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 203285a..b8f0da3 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -271,11 +271,11 @@
 	bd_t *bd;
 	uint8_t *tdb_ptr;
 	int dev_id;
-	int phy_id;
 	struct mii_dev *bus;
 #ifdef CONFIG_PHYLIB
 	struct phy_device *phydev;
 #else
+	int phy_id;
 	int (*mii_postcall)(int);
 #endif
 };
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 1ffa791..d0ed766 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -31,6 +31,7 @@
 #include <miiphy.h>
 #include <phy.h>
 #include <errno.h>
+#include <linux/err.h>
 
 /* Generic PHY support and helper functions */
 
@@ -574,6 +575,61 @@
 	return 0;
 }
 
+static struct phy_device *create_phy_by_mask(struct mii_dev *bus,
+		unsigned phy_mask, int devad, phy_interface_t interface)
+{
+	u32 phy_id = 0xffffffff;
+	while (phy_mask) {
+		int addr = ffs(phy_mask) - 1;
+		int r = get_phy_id(bus, addr, devad, &phy_id);
+		if (r < 0)
+			return ERR_PTR(r);
+		/* If the PHY ID is mostly f's, we didn't find anything */
+		if ((phy_id & 0x1fffffff) != 0x1fffffff)
+			return phy_device_create(bus, addr, phy_id, interface);
+		phy_mask &= ~(1 << addr);
+	}
+	return NULL;
+}
+
+static struct phy_device *search_for_existing_phy(struct mii_dev *bus,
+		unsigned phy_mask, phy_interface_t interface)
+{
+	/* If we have one, return the existing device, with new interface */
+	while (phy_mask) {
+		int addr = ffs(phy_mask) - 1;
+		if (bus->phymap[addr]) {
+			bus->phymap[addr]->interface = interface;
+			return bus->phymap[addr];
+		}
+		phy_mask &= ~(1 << addr);
+	}
+	return NULL;
+}
+
+static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus,
+		unsigned phy_mask, phy_interface_t interface)
+{
+	int i;
+	struct phy_device *phydev;
+
+	phydev = search_for_existing_phy(bus, phy_mask, interface);
+	if (phydev)
+		return phydev;
+	/* Try Standard (ie Clause 22) access */
+	/* Otherwise we have to try Clause 45 */
+	for (i = 0; i < 5; i++) {
+		phydev = create_phy_by_mask(bus, phy_mask,
+				i ? i : MDIO_DEVAD_NONE, interface);
+		if (IS_ERR(phydev))
+			return NULL;
+		if (phydev)
+			return phydev;
+	}
+	printf("Phy not found\n");
+	return phy_device_create(bus, ffs(phy_mask) - 1, 0xffffffff, interface);
+}
+
 /**
  * get_phy_device - reads the specified PHY device and returns its @phy_device struct
  * @bus: the target MII bus
@@ -585,38 +641,7 @@
 static struct phy_device *get_phy_device(struct mii_dev *bus, int addr,
 					 phy_interface_t interface)
 {
-	u32 phy_id = 0x1fffffff;
-	int i;
-	int r;
-
-	/* If we have one, return the existing device, with new interface */
-	if (bus->phymap[addr]) {
-		bus->phymap[addr]->interface = interface;
-
-		return bus->phymap[addr];
-	}
-
-	/* Try Standard (ie Clause 22) access */
-	r = get_phy_id(bus, addr, MDIO_DEVAD_NONE, &phy_id);
-	if (r)
-		return NULL;
-
-	/* If the PHY ID is mostly f's, we didn't find anything */
-	if ((phy_id & 0x1fffffff) != 0x1fffffff)
-		return phy_device_create(bus, addr, phy_id, interface);
-
-	/* Otherwise we have to try Clause 45 */
-	for (i = 1; i < 5; i++) {
-		r = get_phy_id(bus, addr, i, &phy_id);
-		if (r)
-			return NULL;
-
-		/* If the phy_id is mostly Fs, there is no device there */
-		if ((phy_id & 0x1fffffff) != 0x1fffffff)
-			break;
-	}
-
-	return phy_device_create(bus, addr, phy_id, interface);
+	return get_phy_device_by_mask(bus, 1 << addr, interface);
 }
 
 int phy_reset(struct phy_device *phydev)
@@ -689,38 +714,41 @@
 	return phy_reset(phydev);
 }
 
-struct phy_device *phy_connect(struct mii_dev *bus, int addr,
-				struct eth_device *dev,
-				phy_interface_t interface)
+struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
+		phy_interface_t interface)
 {
-	struct phy_device *phydev;
-
 	/* Reset the bus */
 	if (bus->reset)
 		bus->reset(bus);
 
 	/* Wait 15ms to make sure the PHY has come out of hard reset */
 	udelay(15000);
-
-	phydev = get_phy_device(bus, addr, interface);
-
-	if (!phydev) {
-		printf("Could not get PHY for %s:%d\n", bus->name, addr);
-
-		return NULL;
-	}
+	return get_phy_device_by_mask(bus, phy_mask, interface);
+}
 
+void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev)
+{
 	/* Soft Reset the PHY */
 	phy_reset(phydev);
-
-	if (phydev->dev)
+	if (phydev->dev) {
 		printf("%s:%d is connected to %s.  Reconnecting to %s\n",
-			bus->name, addr, phydev->dev->name, dev->name);
-
+				phydev->bus->name, phydev->addr,
+				phydev->dev->name, dev->name);
+	}
 	phydev->dev = dev;
-
 	debug("%s connected to %s\n", dev->name, phydev->drv->name);
+}
+
+struct phy_device *phy_connect(struct mii_dev *bus, int addr,
+		struct eth_device *dev, phy_interface_t interface)
+{
+	struct phy_device *phydev;
 
+	phydev = phy_find_by_mask(bus, 1 << addr, interface);
+	if (phydev)
+		phy_connect_dev(phydev, dev);
+	else
+		printf("Could not get PHY for %s: addr %d\n", bus->name, addr);
 	return phydev;
 }
 
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 824d357..83abcbd 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@
 COBJS-$(CONFIG_SH_SPI) += sh_spi.o
 COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
 COBJS-$(CONFIG_TEGRA_SPI) += tegra_spi.o
+COBJS-$(CONFIG_TEGRA_SLINK) += tegra_slink.o
 COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 
 COBJS	:= $(COBJS-y)
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 42e4c99..bb865b7 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -80,7 +80,6 @@
 				  unsigned int max_hz, unsigned int mode)
 {
 	struct mxs_spi_slave *mxs_slave;
-	uint32_t addr;
 	struct mxs_ssp_regs *ssp_regs;
 	int reg;
 
@@ -96,13 +95,11 @@
 	if (mxs_dma_init_channel(bus))
 		goto err_init;
 
-	addr = MXS_SSP0_BASE + (bus * MXS_SPI_PORT_OFFSET);
-
 	mxs_slave->slave.bus = bus;
 	mxs_slave->slave.cs = cs;
 	mxs_slave->max_khz = max_hz / 1000;
 	mxs_slave->mode = mode;
-	mxs_slave->regs = (struct mxs_ssp_regs *)addr;
+	mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
 	ssp_regs = mxs_slave->regs;
 
 	reg = readl(&ssp_regs->hw_ssp_ctrl0);
@@ -140,7 +137,7 @@
 
 	writel(0, &ssp_regs->hw_ssp_cmd0);
 
-	mx28_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
+	mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
 
 	return 0;
 }
diff --git a/drivers/spi/tegra_slink.c b/drivers/spi/tegra_slink.c
new file mode 100644
index 0000000..2c41fab
--- /dev/null
+++ b/drivers/spi/tegra_slink.c
@@ -0,0 +1,343 @@
+/*
+ * NVIDIA Tegra SPI-SLINK controller
+ *
+ * Copyright (c) 2010-2013 NVIDIA Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/tegra_slink.h>
+#include <spi.h>
+#include <fdtdec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct tegra_spi_ctrl {
+	struct slink_tegra *regs;
+	unsigned int freq;
+	unsigned int mode;
+	int periph_id;
+	int valid;
+};
+
+struct tegra_spi_slave {
+	struct spi_slave slave;
+	struct tegra_spi_ctrl *ctrl;
+};
+
+static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA_SLINK_CTRLS];
+
+static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
+{
+	return container_of(slave, struct tegra_spi_slave, slave);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	if (bus >= CONFIG_TEGRA_SLINK_CTRLS || cs > 3 || !spi_ctrls[bus].valid)
+		return 0;
+	else
+		return 1;
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+		unsigned int max_hz, unsigned int mode)
+{
+	struct tegra_spi_slave *spi;
+
+	debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__,
+		bus, cs, max_hz, mode);
+
+	if (!spi_cs_is_valid(bus, cs)) {
+		printf("SPI error: unsupported bus %d / chip select %d\n",
+		       bus, cs);
+		return NULL;
+	}
+
+	if (max_hz > TEGRA_SPI_MAX_FREQ) {
+		printf("SPI error: unsupported frequency %d Hz. Max frequency"
+			" is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
+		return NULL;
+	}
+
+	spi = malloc(sizeof(struct tegra_spi_slave));
+	if (!spi) {
+		printf("SPI error: malloc of SPI structure failed\n");
+		return NULL;
+	}
+	spi->slave.bus = bus;
+	spi->slave.cs = cs;
+	spi->ctrl = &spi_ctrls[bus];
+	if (!spi->ctrl) {
+		printf("SPI error: could not find controller for bus %d\n",
+		       bus);
+		return NULL;
+	}
+
+	if (max_hz < spi->ctrl->freq) {
+		debug("%s: limiting frequency from %u to %u\n", __func__,
+		      spi->ctrl->freq, max_hz);
+		spi->ctrl->freq = max_hz;
+	}
+	spi->ctrl->mode = mode;
+
+	return &spi->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+
+	free(spi);
+}
+
+void spi_init(void)
+{
+	struct tegra_spi_ctrl *ctrl;
+	int i;
+#ifdef CONFIG_OF_CONTROL
+	int node = 0;
+	int count;
+	int node_list[CONFIG_TEGRA_SLINK_CTRLS];
+
+	count = fdtdec_find_aliases_for_id(gd->fdt_blob, "spi",
+					   COMPAT_NVIDIA_TEGRA20_SLINK,
+					   node_list,
+					   CONFIG_TEGRA_SLINK_CTRLS);
+	for (i = 0; i < count; i++) {
+		ctrl = &spi_ctrls[i];
+		node = node_list[i];
+
+		ctrl->regs = (struct slink_tegra *)fdtdec_get_addr(gd->fdt_blob,
+								   node, "reg");
+		if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
+			debug("%s: no slink register found\n", __func__);
+			continue;
+		}
+		ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
+					    "spi-max-frequency", 0);
+		if (!ctrl->freq) {
+			debug("%s: no slink max frequency found\n", __func__);
+			continue;
+		}
+
+		ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
+		if (ctrl->periph_id == PERIPH_ID_NONE) {
+			debug("%s: could not decode periph id\n", __func__);
+			continue;
+		}
+		ctrl->valid = 1;
+
+		debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
+		      __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
+	}
+#else
+	for (i = 0; i < CONFIG_TEGRA_SLINK_CTRLS; i++) {
+		ctrl = &spi_ctrls[i];
+		u32 base_regs[] = {
+			NV_PA_SLINK1_BASE,
+			NV_PA_SLINK2_BASE,
+			NV_PA_SLINK3_BASE,
+			NV_PA_SLINK4_BASE,
+			NV_PA_SLINK5_BASE,
+			NV_PA_SLINK6_BASE,
+		};
+		int periph_ids[] = {
+			PERIPH_ID_SBC1,
+			PERIPH_ID_SBC2,
+			PERIPH_ID_SBC3,
+			PERIPH_ID_SBC4,
+			PERIPH_ID_SBC5,
+			PERIPH_ID_SBC6,
+		};
+		ctrl->regs = (struct slink_tegra *)base_regs[i];
+		ctrl->freq = TEGRA_SPI_MAX_FREQ;
+		ctrl->periph_id = periph_ids[i];
+		ctrl->valid = 1;
+
+		debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
+		      __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
+	}
+#endif
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+	struct slink_tegra *regs = spi->ctrl->regs;
+	u32 reg;
+
+	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
+	clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
+			       spi->ctrl->freq);
+
+	/* Clear stale status here */
+	reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \
+		SLINK_STAT_RXF_UNR | SLINK_STAT_TXF_OVF;
+	writel(reg, &regs->status);
+	debug("%s: STATUS = %08x\n", __func__, readl(&regs->status));
+
+	/* Set master mode and sw controlled CS */
+	reg = readl(&regs->command);
+	reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT;
+	writel(reg, &regs->command);
+	debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command));
+
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+	struct slink_tegra *regs = spi->ctrl->regs;
+
+	/* CS is negated on Tegra, so drive a 1 to get a 0 */
+	setbits_le32(&regs->command, SLINK_CMD_CS_VAL);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+	struct slink_tegra *regs = spi->ctrl->regs;
+
+	/* CS is negated on Tegra, so drive a 0 to get a 1 */
+	clrbits_le32(&regs->command, SLINK_CMD_CS_VAL);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+		const void *data_out, void *data_in, unsigned long flags)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+	struct slink_tegra *regs = spi->ctrl->regs;
+	u32 reg, tmpdout, tmpdin = 0;
+	const u8 *dout = data_out;
+	u8 *din = data_in;
+	int num_bytes;
+	int ret;
+
+	debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
+	      __func__, slave->bus, slave->cs, dout, din, bitlen);
+	if (bitlen % 8)
+		return -1;
+	num_bytes = bitlen / 8;
+
+	ret = 0;
+
+	reg = readl(&regs->status);
+	writel(reg, &regs->status);	/* Clear all SPI events via R/W */
+	debug("%s entry: STATUS = %08x\n", __func__, reg);
+
+	reg = readl(&regs->status2);
+	writel(reg, &regs->status2);	/* Clear all STATUS2 events via R/W */
+	debug("%s entry: STATUS2 = %08x\n", __func__, reg);
+
+	debug("%s entry: COMMAND = %08x\n", __func__, readl(&regs->command));
+
+	clrsetbits_le32(&regs->command2, SLINK_CMD2_SS_EN_MASK,
+			SLINK_CMD2_TXEN | SLINK_CMD2_RXEN |
+			(slave->cs << SLINK_CMD2_SS_EN_SHIFT));
+	debug("%s entry: COMMAND2 = %08x\n", __func__, readl(&regs->command2));
+
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(slave);
+
+	/* handle data in 32-bit chunks */
+	while (num_bytes > 0) {
+		int bytes;
+		int is_read = 0;
+		int tm, i;
+
+		tmpdout = 0;
+		bytes = (num_bytes > 4) ?  4 : num_bytes;
+
+		if (dout != NULL) {
+			for (i = 0; i < bytes; ++i)
+				tmpdout = (tmpdout << 8) | dout[i];
+			dout += bytes;
+		}
+
+		num_bytes -= bytes;
+
+		clrsetbits_le32(&regs->command, SLINK_CMD_BIT_LENGTH_MASK,
+				bytes * 8 - 1);
+		writel(tmpdout, &regs->tx_fifo);
+		setbits_le32(&regs->command, SLINK_CMD_GO);
+
+		/*
+		 * Wait for SPI transmit FIFO to empty, or to time out.
+		 * The RX FIFO status will be read and cleared last
+		 */
+		for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
+			u32 status;
+
+			status = readl(&regs->status);
+
+			/* We can exit when we've had both RX and TX activity */
+			if (is_read && (status & SLINK_STAT_TXF_EMPTY))
+				break;
+
+			if ((status & (SLINK_STAT_BSY | SLINK_STAT_RDY)) !=
+					SLINK_STAT_RDY)
+				tm++;
+
+			else if (!(status & SLINK_STAT_RXF_EMPTY)) {
+				tmpdin = readl(&regs->rx_fifo);
+				is_read = 1;
+
+				/* swap bytes read in */
+				if (din != NULL) {
+					for (i = bytes - 1; i >= 0; --i) {
+						din[i] = tmpdin & 0xff;
+						tmpdin >>= 8;
+					}
+					din += bytes;
+				}
+			}
+		}
+
+		if (tm >= SPI_TIMEOUT)
+			ret = tm;
+
+		/* clear ACK RDY, etc. bits */
+		writel(readl(&regs->status), &regs->status);
+	}
+
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(slave);
+
+	debug("%s: transfer ended. Value=%08x, status = %08x\n",
+	      __func__, tmpdin, readl(&regs->status));
+
+	if (ret) {
+		printf("%s: timeout during SPI transfer, tm %d\n",
+		       __func__, ret);
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/drivers/spi/tegra_spi.c b/drivers/spi/tegra_spi.c
index 9bb34e2..ce19095 100644
--- a/drivers/spi/tegra_spi.c
+++ b/drivers/spi/tegra_spi.c
@@ -32,6 +32,9 @@
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/tegra_spi.h>
 #include <spi.h>
+#include <fdtdec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_SPI_CORRUPTS_UART)
  #define corrupt_delay()	udelay(CONFIG_SPI_CORRUPTS_UART_DLY);
@@ -44,6 +47,7 @@
 	struct spi_tegra *regs;
 	unsigned int freq;
 	unsigned int mode;
+	int periph_id;
 };
 
 static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
@@ -84,8 +88,45 @@
 	}
 	spi->slave.bus = bus;
 	spi->slave.cs = cs;
-	spi->freq = max_hz;
+#ifdef CONFIG_OF_CONTROL
+	int node = fdtdec_next_compatible(gd->fdt_blob, 0,
+					  COMPAT_NVIDIA_TEGRA20_SFLASH);
+	if (node < 0) {
+		debug("%s: cannot locate sflash node\n", __func__);
+		return NULL;
+	}
+	if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) {
+		debug("%s: sflash is disabled\n", __func__);
+		return NULL;
+	}
+	spi->regs = (struct spi_tegra *)fdtdec_get_addr(gd->fdt_blob,
+							node, "reg");
+	if ((fdt_addr_t)spi->regs == FDT_ADDR_T_NONE) {
+		debug("%s: no sflash register found\n", __func__);
+		return NULL;
+	}
+	spi->freq = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency", 0);
+	if (!spi->freq) {
+		debug("%s: no sflash max frequency found\n", __func__);
+		return NULL;
+	}
+	spi->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
+	if (spi->periph_id == PERIPH_ID_NONE) {
+		debug("%s: could not decode periph id\n", __func__);
+		return NULL;
+	}
+#else
 	spi->regs = (struct spi_tegra *)NV_PA_SPI_BASE;
+	spi->freq = TEGRA_SPI_MAX_FREQ;
+	spi->periph_id = PERIPH_ID_SPI1;
+#endif
+	if (max_hz < spi->freq) {
+		debug("%s: limiting frequency from %u to %u\n", __func__,
+		      spi->freq, max_hz);
+		spi->freq = max_hz;
+	}
+	debug("%s: controller initialized at %p, freq = %u, periph_id = %d\n",
+	      __func__, spi->regs, spi->freq, spi->periph_id);
 	spi->mode = mode;
 
 	return &spi->slave;
@@ -110,7 +151,7 @@
 	u32 reg;
 
 	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
-	clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, spi->freq);
+	clock_start_periph_pll(spi->periph_id, CLOCK_ID_PERIPH, spi->freq);
 
 	/* Clear stale status here */
 	reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c
index 750a283..afcb008 100644
--- a/drivers/video/tegra.c
+++ b/drivers/video/tegra.c
@@ -145,8 +145,8 @@
 
 void lcd_ctrl_init(void *lcdbase)
 {
-	int line_length, size;
 	int type = DCACHE_OFF;
+	int size;
 
 	assert(disp_config);
 
@@ -160,7 +160,7 @@
 			&& disp_config->height <= LCD_MAX_HEIGHT
 			&& disp_config->log2_bpp <= LCD_MAX_LOG2_BPP)
 		update_panel_size(disp_config);
-	size = lcd_get_size(&line_length);
+	size = lcd_get_size(&lcd_line_length);
 
 	/* Set up the LCD caching as requested */
 	if (config.cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
diff --git a/dts/Makefile b/dts/Makefile
index 785104e..922c78c 100644
--- a/dts/Makefile
+++ b/dts/Makefile
@@ -36,7 +36,7 @@
 Please define CONFIG_ARCH_DEVICE_TREE))
 
 # We preprocess the device tree file provide a useful define
-DTS_CPPFLAGS := -ansi \
+DTS_CPPFLAGS := -x assembler-with-cpp \
 		-DARCH_CPU_DTS=\"$(SRCTREE)/arch/$(ARCH)/dts/$(CONFIG_ARCH_DEVICE_TREE).dtsi\" \
 		-DBOARD_DTS=\"$(SRCTREE)/board/$(VENDOR)/$(BOARD)/dts/$(DEVICE_TREE).dts\"
 
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 72459d8..33ee2c4 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -52,6 +52,7 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x80200000\0" \
 	"fdtaddr=0x80F80000\0" \
+	"fdt_high=0xffffffff\0" \
 	"rdaddr=0x81000000\0" \
 	"bootfile=/boot/uImage\0" \
 	"fdtfile=\0" \
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
new file mode 100644
index 0000000..1616b39
--- /dev/null
+++ b/include/configs/cardhu.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/sizes.h>
+
+#include "tegra30-common.h"
+
+/* Enable fdt support for Cardhu. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra30-cardhu
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT		"Tegra30 (Cardhu) # "
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Cardhu"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_CARDHU
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_TEGRA_I2C
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS		TEGRA_I2C_NUM_CONTROLLERS
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_I2C
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/* SPI */
+#define CONFIG_TEGRA_SLINK
+#define CONFIG_TEGRA_SLINK_CTRLS       6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED        24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index d8aabd4..c7f36ff 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -37,7 +37,6 @@
 #define CONFIG_SYS_COREBOOT
 #define CONFIG_SHOW_BOOT_PROGRESS
 #define CONFIG_LAST_STAGE_INIT
-#define CONFIG_X86_NO_RESET_VECTOR
 #define CONFIG_SYS_VSNPRINTF
 #define CONFIG_INTEL_CORE_ARCH	/* Sandy bridge and ivy bridge chipsets. */
 #define CONFIG_ZBOOT_32
diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
new file mode 100644
index 0000000..ce32c80
--- /dev/null
+++ b/include/configs/dalmore.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/sizes.h>
+
+#include "tegra114-common.h"
+
+/* Must be off for Dalmore to boot !?!? FIXME */
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Enable fdt support for Dalmore. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra114-dalmore
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT		"Tegra114 (Dalmore) # "
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Dalmore"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_DALMORE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ENV_IS_NOWHERE
+
+#define MACH_TYPE_DALMORE	4304	/* not yet in mach-types.h */
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
deleted file mode 100644
index 28cf95b..0000000
--- a/include/configs/eNET.h
+++ /dev/null
@@ -1,619 +0,0 @@
-/*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/ibmpc.h>
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SYS_SC520
-#define CONFIG_SYS_SC520_SSI
-#define CONFIG_SHOW_BOOT_PROGRESS
-#define CONFIG_LAST_STAGE_INIT
-
-/*-----------------------------------------------------------------------
- * Watchdog Configuration
- * NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
- * bottom (processor) board MUST be removed!
- */
-#undef CONFIG_WATCHDOG
-#define CONFIG_HW_WATCHDOG
-
-/*-----------------------------------------------------------------------
- * Real Time Clock Configuration
- */
-#define CONFIG_RTC_MC146818
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS		0
-
-/*-----------------------------------------------------------------------
- * Serial Configuration
- */
-#define CONFIG_CONS_INDEX			1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE		1
-#define CONFIG_SYS_NS16550_CLK			1843200
-#define CONFIG_BAUDRATE				9600
-#define CONFIG_SYS_BAUDRATE_TABLE		{300, 600, 1200, 2400, 4800, \
-						 9600, 19200, 38400, 115200}
-#define CONFIG_SYS_NS16550_COM1			UART0_BASE
-#define CONFIG_SYS_NS16550_COM2			UART1_BASE
-#define CONFIG_SYS_NS16550_COM3			(0x1000 + UART0_BASE)
-#define CONFIG_SYS_NS16550_COM4			(0x1000 + UART1_BASE)
-#define CONFIG_SYS_NS16550_PORT_MAPPED
-
-/*-----------------------------------------------------------------------
- * Video Configuration
- */
-#undef CONFIG_VIDEO
-#undef CONFIG_CFB_CONSOLE
-
-/*-----------------------------------------------------------------------
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_IMLS
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ITEST
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_SETGETDCR
-#define CONFIG_CMD_SOURCE
-#define CONFIG_CMD_XIMG
-#define CONFIG_CMD_ZBOOT
-
-#define CONFIG_BOOTDELAY			15
-#define CONFIG_BOOTARGS				"root=/dev/mtdblock0 console=ttyS0,9600"
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE			115200
-#define CONFIG_KGDB_SER_INDEX			2
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP
-#define	CONFIG_SYS_PROMPT			"boot > "
-#define	CONFIG_SYS_CBSIZE			256
-#define	CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + \
-						 sizeof(CONFIG_SYS_PROMPT) + \
-						 16)
-#define	CONFIG_SYS_MAXARGS			16
-#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START		0x00100000
-#define CONFIG_SYS_MEMTEST_END			0x01000000
-#define	CONFIG_SYS_LOAD_ADDR			0x100000
-#define	CONFIG_SYS_HZ				1000
-
-/*-----------------------------------------------------------------------
- * SDRAM Configuration
- */
-#define CONFIG_SYS_SDRAM_DRCTMCTL		0x18
-#define CONFIG_SYS_SDRAM_REFRESH_RATE		156
-#define CONFIG_NR_DRAM_BANKS			4
-
-/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
-#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
-#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
-#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
-#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
-
-/*-----------------------------------------------------------------------
- * CPU Features
- */
-#define CONFIG_SYS_SC520_HIGH_SPEED		0
-#define CONFIG_SYS_SC520_RESET
-#define CONFIG_SYS_SC520_TIMER
-#undef  CONFIG_SYS_GENERIC_TIMER
-#define CONFIG_SYS_PCAT_INTERRUPTS
-#define CONFIG_SYS_NUM_IRQS			16
-#define CONFIG_SYS_PC_BIOS
-#define CONFIG_SYS_PCI_BIOS
-#define CONFIG_SYS_X86_REALMODE
-#define CONFIG_SYS_X86_ISR_TIMER
-
-/*-----------------------------------------------------------------------
- * Memory organization:
- * 32kB Stack
- * 16kB Cache-As-RAM @ 0x19200000
- * 256kB Monitor
- * (128kB + Environment Sector Size) malloc pool
- */
-#define CONFIG_SYS_STACK_SIZE			(32 * 1024)
-#define CONFIG_SYS_CAR_ADDR			0x19200000
-#define CONFIG_SYS_CAR_SIZE			(16 * 1024)
-#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN			(256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SECT_SIZE + \
-						 128*1024)
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/*-----------------------------------------------------------------------
- * FLASH configuration
- * 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000)
- * 16MB StrataFlash #1 @ 0x10000000
- * 16MB StrataFlash #2 @ 0x11000000
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_MAX_FLASH_BANKS		3
-#define CONFIG_SYS_FLASH_BASE			0x38000000
-#define CONFIG_SYS_FLASH_BASE_1			0x10000000
-#define CONFIG_SYS_FLASH_BASE_2			0x11000000
-#define CONFIG_SYS_FLASH_BANKS_LIST		{CONFIG_SYS_FLASH_BASE,   \
-						 CONFIG_SYS_FLASH_BASE_1, \
-						 CONFIG_SYS_FLASH_BASE_2}
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_MAX_FLASH_SECT		128
-#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_8BIT
-#define CONFIG_SYS_FLASH_LEGACY_512Kx8
-#define CONFIG_SYS_FLASH_ERASE_TOUT		2000	/* ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT		2000	/* ms */
-
-/*-----------------------------------------------------------------------
- * Environment configuration
- * - Boot flash is 512kB with 64kB sectors
- * - StrataFlash is 32MB with 128kB sectors
- * - Redundant embedded environment is 25% of the Boot flash
- * - Redundant StrataFlash environment is <1% of the StrataFlash
- * - Environment is therefore located in StrataFlash
- * - Primary copy is located in first sector of first flash
- * - Redundant copy is located in second sector of first flash
- * - Stack is only 32kB, so environment size is limited to 4kB
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE			0x20000
-#define CONFIG_ENV_SIZE				0x01000
-#define CONFIG_ENV_ADDR				CONFIG_SYS_FLASH_BASE_1
-#define CONFIG_ENV_ADDR_REDUND			(CONFIG_SYS_FLASH_BASE_1 + \
-						 CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND			CONFIG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * PCI configuration
- */
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_SYS_FIRST_PCI_IRQ		10
-#define CONFIG_SYS_SECOND_PCI_IRQ		9
-#define CONFIG_SYS_THIRD_PCI_IRQ		11
-#define CONFIG_SYS_FORTH_PCI_IRQ		15
-
-/*-----------------------------------------------------------------------
- * Network device (TRL8100B) support
- */
-#define CONFIG_RTL8139
-
-/*-----------------------------------------------------------------------
- * BOOTCS Control (for AM29LV040B-120JC)
- *
- * 000 0 00 0 000 11 0 011 }- 0x0033
- * \ / | \| | \ / \| | \ /
- *  |  |  | |  |   | |  |
- *  |  |  | |  |   | |  +---- 3 Wait States (First Access)
- *  |  |  | |  |   | +------- Reserved
- *  |  |  | |  |   +--------- 3 Wait States (Subsequent Access)
- *  |  |  | |  +------------- Reserved
- *  |  |  | +---------------- Non-Paged Mode
- *  |  |  +------------------ 8 Bit Wide
- *  |  +--------------------- GP Bus
- *  +------------------------ Reserved
- */
-#define CONFIG_SYS_SC520_BOOTCS_CTRL		0x0033
-
-/*-----------------------------------------------------------------------
- * ROMCS Control (for E28F128J3A-150 StrataFlash)
- *
- * 000 0 01 1 000 01 0 101 }- 0x0615
- * \ / | \| | \ / \| | \ /
- *  |  |  | |  |   | |  |
- *  |  |  | |  |   | |  +---- 5 Wait States (First Access)
- *  |  |  | |  |   | +------- Reserved
- *  |  |  | |  |   +--------- 1 Wait State (Subsequent Access)
- *  |  |  | |  +------------- Reserved
- *  |  |  | +---------------- Paged Mode
- *  |  |  +------------------ 16 Bit Wide
- *  |  +--------------------- GP Bus
- *  +------------------------ Reserved
- */
-#define CONFIG_SYS_SC520_ROMCS1_CTRL		0x0615
-#define CONFIG_SYS_SC520_ROMCS2_CTRL		0x0615
-
-/*-----------------------------------------------------------------------
- * SC520 General Purpose Bus configuration
- *
- * Chip Select Offset		1 Clock Cycle
- * Chip Select Pulse Width	8 Clock Cycles
- * Chip Select Read Offset	2 Clock Cycles
- * Chip Select Read Width	6 Clock Cycles
- * Chip Select Write Offset	2 Clock Cycles
- * Chip Select Write Width	6 Clock Cycles
- * Chip Select Recovery Time	2 Clock Cycles
- *
- * Timing Diagram (from SC520 Register Set Manual - Order #22005B)
- *
- *   |<-------------General Purpose Bus Cycle---------------->|
- *   |                                                        |
- * ----------------------\__________________/------------------
- *   |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
- *
- * ------------------------\_______________/-------------------
- *   |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
- *
- * --------------------------\_______________/-----------------
- *   |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
- *
- * ________/-----------\_______________________________________
- *   |<--->|<--------->|
- *      ^         ^
- * (GPALEOFF + 1) |
- *                |
- *         (GPALEW + 1)
- */
-#define CONFIG_SYS_SC520_GPCSOFF		0x00
-#define CONFIG_SYS_SC520_GPCSPW			0x07
-#define CONFIG_SYS_SC520_GPRDOFF		0x01
-#define CONFIG_SYS_SC520_GPRDW			0x05
-#define CONFIG_SYS_SC520_GPWROFF		0x01
-#define CONFIG_SYS_SC520_GPWRW			0x05
-#define CONFIG_SYS_SC520_GPCSRT			0x01
-
-/*-----------------------------------------------------------------------
- * SC520 Programmable I/O configuration
- *
- * Pin	  Mode		Dir.	Description
- * ----------------------------------------------------------------------
- * PIO0   PIO		Output	Unused
- * PIO1   GPBHE#	Output	GP Bus Byte High Enable (active low)
- * PIO2   PIO		Output	Auxiliary power output enable
- * PIO3   GPAEN		Output	GP Bus Address Enable
- * PIO4   PIO		Output	Top Board Enable (active low)
- * PIO5   PIO		Output	StrataFlash 16 bit mode (low = 8 bit mode)
- * PIO6   PIO		Input	Data output of Power Supply ADC
- * PIO7   PIO		Output	Clock input to Power Supply ADC
- * PIO8   PIO		Output  Chip Select input of Power Supply ADC
- * PIO9   PIO		Output	StrataFlash 1 Reset / Power Down (active low)
- * PIO10  PIO		Output	StrataFlash 2 Reset / Power Down (active low)
- * PIO11  PIO		Input	StrataFlash 1 Status
- * PIO12  PIO		Input	StrataFlash 2 Status
- * PIO13  GPIRQ10#	Input	Can Bus / I2C IRQ (active low)
- * PIO14  PIO		Input	Low Input Voltage Warning (active low)
- * PIO15  PIO		Output	Watchdog (must toggle at least every 1.6s)
- * PIO16  PIO		Input	Power Fail
- * PIO17  GPIRQ6	Input	Compact Flash 1 IRQ (active low)
- * PIO18  GPIRQ5	Input	Compact Flash 2 IRQ (active low)
- * PIO19  GPIRQ4#	Input	Dual-Port RAM IRQ (active low)
- * PIO20  GPIRQ3	Input	UART D IRQ
- * PIO21  GPIRQ2	Input	UART C IRQ
- * PIO22  GPIRQ1	Input	UART B IRQ
- * PIO23  GPIRQ0	Input	UART A IRQ
- * PIO24  GPDBUFOE#	Output	GP Bus Data Bus Buffer Output Enable
- * PIO25  PIO		Input	Battery OK Indication
- * PIO26  GPMEMCS16#	Input	GP Bus Memory Chip-Select 16-bit access
- * PIO27  GPCS0#	Output	SRAM 1 Chip Select
- * PIO28  PIO		Input	Top Board UART CTS
- * PIO29  PIO		Output	FPGA Program Mode (active low)
- * PIO30  PIO		Input	FPGA Initialised (active low)
- * PIO31  PIO		Input	FPGA Done (active low)
- */
-#define CONFIG_SYS_SC520_PIOPFS15_0		0x200a
-#define CONFIG_SYS_SC520_PIOPFS31_16		0x0dfe
-#define CONFIG_SYS_SC520_PIODIR15_0		0x87bf
-#define CONFIG_SYS_SC520_PIODIR31_16		0x2900
-
-/*-----------------------------------------------------------------------
- * PIO Pin defines
- */
-#define CONFIG_SYS_ENET_AUX_PWR			0x0004
-#define CONFIG_SYS_ENET_TOP_BRD_PWR		0x0010
-#define CONFIG_SYS_ENET_SF_WIDTH		0x0020
-#define CONFIG_SYS_ENET_PWR_ADC_DATA		0x0040
-#define CONFIG_SYS_ENET_PWR_ADC_CLK		0x0080
-#define CONFIG_SYS_ENET_PWR_ADC_CS		0x0100
-#define CONFIG_SYS_ENET_SF1_MODE		0x0200
-#define CONFIG_SYS_ENET_SF2_MODE		0x0400
-#define CONFIG_SYS_ENET_SF1_STATUS		0x0800
-#define CONFIG_SYS_ENET_SF2_STATUS		0x1000
-#define CONFIG_SYS_ENET_PWR_STATUS		0x4000
-#define CONFIG_SYS_ENET_WATCHDOG		0x8000
-
-#define CONFIG_SYS_ENET_PWR_FAIL		0x0001
-#define CONFIG_SYS_ENET_BAT_OK			0x0200
-#define CONFIG_SYS_ENET_TOP_BRD_CTS		0x1000
-#define CONFIG_SYS_ENET_FPGA_PROG		0x2000
-#define CONFIG_SYS_ENET_FPGA_INIT		0x4000
-#define CONFIG_SYS_ENET_FPGA_DONE		0x8000
-
-/*-----------------------------------------------------------------------
- * Chip Select Pin Function Select
- *
- * 1 1 1 1 1 0 0 0 }- 0xf8
- * | | | | | | | |
- * | | | | | | | +--- Reserved
- * | | | | | | +----- GPCS1_SEL = ROMCS1#
- * | | | | | +------- GPCS2_SEL = ROMCS2#
- * | | | | +--------- GPCS3_SEL = GPCS3
- * | | | +----------- GPCS4_SEL = GPCS4
- * | | +------------- GPCS5_SEL = GPCS5
- * | +--------------- GPCS6_SEL = GPCS6
- * +----------------- GPCS7_SEL = GPCS7
- */
-#define CONFIG_SYS_SC520_CSPFS			0xf8
-
-/*-----------------------------------------------------------------------
- * Clock Select (CLKTIMER[CLKTEST] pin)
- *
- * 0 111 00 1 0 }- 0x72
- * | \ / \| | |
- * |  |   | | +--- Pin Disabled
- * |  |   | +----- Pin is an output
- * |  |   +------- Reserved
- * |  +----------- Disabled (pin stays Low)
- * +-------------- Reserved
- */
-#define CONFIG_SYS_SC520_CLKSEL			0x72
-
-/*-----------------------------------------------------------------------
- * Address Decode Control
- *
- * 0 00 0 0 0 0 0 }- 0x00
- * | \| | | | | |
- * |  | | | | | +--- Integrated UART 1 is enabled
- * |  | | | | +----- Integrated UART 2 is enabled
- * |  | | | +------- Integrated RTC is enabled
- * |  | | +--------- Reserved
- * |  | +----------- I/O Hole accesses are forwarded to the external GP bus
- * |  +------------- Reserved
- * +---------------- Write-protect violations do not generate an IRQ
- */
-#define CONFIG_SYS_SC520_ADDDECCTL		0x00
-
-/*-----------------------------------------------------------------------
- * UART Control
- *
- * 00000 1 1 1 }- 0x07
- * \___/ | | |
- *   |   | | +--- Transmit TC interrupt enable
- *   |   | +----- Receive TC interrupt enable
- *   |   +------- 1.8432 MHz
- *   +----------- Reserved
- */
-#define CONFIG_SYS_SC520_UART1CTL		0x07
-#define CONFIG_SYS_SC520_UART2CTL		0x07
-
-/*-----------------------------------------------------------------------
- * System Arbiter Control
- *
- * 00000 1 1 0 }- 0x06
- * \___/ | | |
- *   |   | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
- *   |   | +----- The system arbiter operates in concurrent mode
- *   |   +------- Park the PCI bus on the last master that acquired the bus
- *   +----------- Reserved
- */
-#define CONFIG_SYS_SC520_SYSARBCTL		0x06
-
-/*-----------------------------------------------------------------------
- * System Arbiter Master Enable
- *
- * 00000000000 0 0 0 1 1 }- 0x06
- * \_________/ | | | | |
- *      |      | | | | +--- PCI master REQ0 enabled (Ethernet 1)
- *      |      | | | +----- PCI master REQ1 enabled (Ethernet 2)
- *      |      | | +------- PCI master REQ2 disabled
- *      |      | +--------- PCI master REQ3 disabled
- *      |      +----------- PCI master REQ4 disabled
- *      +------------------ Reserved
- */
-#define CONFIG_SYS_SC520_SYSARBMENB		0x0003
-
-/*-----------------------------------------------------------------------
- * System Arbiter Master Enable
- *
- * 0 0000 0 00 0000 1 000 }- 0x06
- * | \__/ | \| \__/ | \_/
- * |   |  |  |   |  |  +---- Reserved
- * |   |  |  |   |  +------- Enable CPU-to-PCI bus write posting
- * |   |  |  |   +---------- Reserved
- * |   |  |  +-------------- PCI bus reads to SDRAM are not automatically
- * |   |  |                  retried
- * |   |  +----------------- Target read FIFOs are not snooped during write
- * |   |                     transactions
- * |   +-------------------- Reserved
- * +------------------------ Deassert the PCI bus reset signal
- */
-#define CONFIG_SYS_SC520_HBCTL			0x08
-
-/*-----------------------------------------------------------------------
- * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
- * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
- * \ / | | | | \----+----/ \-----+------/
- *  |  | | | |      |            +---------- Start at 0x38000000
- *  |  | | | |      +----------------------- 512kB Region Size
- *  |  | | | |                               ((7 + 1) * 64kB)
- *  |  | | | +------------------------------ 64kB Page Size
- *  |  | | +-------------------------------- Writes Enabled (So it can be
- *  |  | |                                   reprogrammed!)
- *  |  | +---------------------------------- Caching Disabled
- *  |  +------------------------------------ Execution Enabled
- *  +--------------------------------------- BOOTCS
- */
-#define CONFIG_SYS_SC520_BOOTCS_PAR		0x8a01f800
-
-/*-----------------------------------------------------------------------
- * Cache-As-RAM (Targets Boot Flash)
- *
- * 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200
- * \ / | | | | \--+--/ \-------+--------/
- *  |  | | | |    |            +------------ Start at 0x19200000
- *  |  | | | |    +------------------------- 64k Region Size
- *  |  | | | |                               ((15 + 1) * 4kB)
- *  |  | | | +------------------------------ 4kB Page Size
- *  |  | | +-------------------------------- Writes Enabled
- *  |  | +---------------------------------- Caching Enabled
- *  |  +------------------------------------ Execution Prevented
- *  +--------------------------------------- BOOTCS
- */
-#define CONFIG_SYS_SC520_CAR_PAR		0x903d9200
-
-/*-----------------------------------------------------------------------
- * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6
- *
- * 001 110 0 000100000 0001000000000000 }- 0x38201000
- * \ / \ / | \---+---/ \------+-------/
- *  |   |  |     |            +----------- Start at 0x00001000
- *  |   |  |     +------------------------ 33 Bytes (0x20 + 1)
- *  |   |  +------------------------------ Ignored
- *  |   +--------------------------------- GPCS6
- *  +------------------------------------- GP Bus I/O
- */
-#define CONFIG_SYS_SC520_LLIO_PAR		0x38201000
-
-/*-----------------------------------------------------------------------
- * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
- * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
- *
- * 010 101 0 0000000 100000000000000000 }- 0x54020000
- * 010 111 0 0000000 100000000000000001 }- 0x5c020001
- * \ / \ / | \--+--/ \-------+--------/
- *  |   |  |    |            +------------ Start at 0x200000000
- *  |   |  |    |                                   0x200010000
- *  |   |  |    +------------------------- 4kB Region Size
- *  |   |  |                               ((0 + 1) * 4kB)
- *  |   |  +------------------------------ 4k Page Size
- *  |   +--------------------------------- GPCS5
- *  |                                      GPCS7
- *  +------------------------------------- GP Bus Memory
- */
-#define CONFIG_SYS_SC520_CF1_PAR		0x54020000
-#define CONFIG_SYS_SC520_CF2_PAR		0x5c020001
-
-/*-----------------------------------------------------------------------
- * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
- * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
- * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
- * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
- *
- * 001 000 0 000000111 0001001111111000 }- 0x200713f8
- * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
- * 001 011 0 000000111 0001001011111000 }- 0x300711f8
- * 001 011 0 000000111 0001001011111000 }- 0x340710f8
- * \ / \ / | \---+---/ \------+-------/
- *  |   |  |     |            +----------- Start at 0x013f8
- *  |   |  |     |                                  0x012f8
- *  |   |  |     |                                  0x011f8
- *  |   |  |     |                                  0x010f8
- *  |   |  |     +------------------------ 33 Bytes (32 + 1)
- *  |   |  +------------------------------ Ignored
- *  |   +--------------------------------- GPCS6
- *  +------------------------------------- GP Bus I/O
- */
-#define CONFIG_SYS_SC520_UARTA_PAR		0x200713f8
-#define CONFIG_SYS_SC520_UARTB_PAR		0x2c0712f8
-#define CONFIG_SYS_SC520_UARTC_PAR		0x300711f8
-#define CONFIG_SYS_SC520_UARTD_PAR		0x340710f8
-
-/*-----------------------------------------------------------------------
- * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
- * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
- *
- * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
- * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
- * \ / | | | | \----+----/ \-----+------/
- *  |  | | | |      |            +---------- Start at 0x10000000
- *  |  | | | |      |                                 0x11000000
- *  |  | | | |      +----------------------- 16MB Region Size
- *  |  | | | |                               ((255 + 1) * 64kB)
- *  |  | | | +------------------------------ 64kB Page Size
- *  |  | | +-------------------------------- Writes Enabled
- *  |  | +---------------------------------- Caching Disabled
- *  |  +------------------------------------ Execution Enabled
- *  +--------------------------------------- ROMCS1
- *                                           ROMCS2
- */
-#define CONFIG_SYS_SC520_SF1_PAR		0xaa3fd000
-#define CONFIG_SYS_SC520_SF2_PAR		0xca3fd100
-
-/*-----------------------------------------------------------------------
- * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
- * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
- *
- * 010 000 1 00000001111 01100100000000 }- 0x4203d900
- * 010 011 1 00000001111 01100100010000 }- 0x4e03d910
- * \ / \ / | \----+----/ \-----+------/
- *  |   |  |      |            +---------- Start at 0x19000000
- *  |   |  |      |                                 0x19100000
- *  |   |  |      +----------------------- 1MB Region Size
- *  |   |  |                               ((15 + 1) * 64kB)
- *  |   |  +------------------------------ 64kB Page Size
- *  |   +--------------------------------- GPCS0
- *  |                                      GPCS3
- *  +------------------------------------- GP Bus Memory
- */
-#define CONFIG_SYS_SC520_SRAM1_PAR		0x4203d900
-#define CONFIG_SYS_SC520_SRAM2_PAR		0x4e03d910
-
-/*-----------------------------------------------------------------------
- * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
- *
- * 010 100 0 00000000 11000000100000000 }- 0x50018100
- * \ / \ / | \---+--/ \-------+-------/
- *  |   |  |     |            +----------- Start at 0x18100000
- *  |   |  |     +------------------------ 4kB Region Size
- *  |   |  |                               ((0 + 1) * 4kB)
- *  |   |  +------------------------------ 4kB Page Size
- *  |   +--------------------------------- GPCS4
- *  +------------------------------------- GP Bus Memory
- */
-#define CONFIG_SYS_SC520_DPRAM_PAR		0x50018100
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h
index e59f41e..0e7f924 100644
--- a/include/configs/igep00x0.h
+++ b/include/configs/igep00x0.h
@@ -85,6 +85,9 @@
 #define CONFIG_OMAP_HSMMC		1
 #define CONFIG_DOS_PARTITION		1
 
+/* define to enable boot progress via leds */
+#define CONFIG_SHOW_BOOT_PROGRESS
+
 /* USB */
 #define CONFIG_MUSB_UDC			1
 #define CONFIG_USB_OMAP3		1
@@ -115,7 +118,9 @@
 #ifdef CONFIG_BOOT_NAND
 #define CONFIG_CMD_NAND
 #endif
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
 #define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#endif
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_NFS		/* NFS support			*/
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index 6887171..1b51fe2 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -191,7 +191,6 @@
 #ifdef	CONFIG_CMD_NET
 #define	CONFIG_ETHPRIME			"FEC0"
 #define	CONFIG_FEC_MXC
-#define	CONFIG_FEC_MXC_MULTI
 #define	CONFIG_MII
 #define	CONFIG_FEC_XCV_TYPE		RMII
 #endif
@@ -274,7 +273,7 @@
 #define	CONFIG_SETUP_MEMORY_TAGS
 #define	CONFIG_BOOTDELAY	3
 #define	CONFIG_BOOTFILE		"uImage"
-#define	CONFIG_BOOTARGS		"console=ttyAM0,115200n8 "
+#define	CONFIG_BOOTARGS		"console=ttyAMA0,115200n8 "
 #define	CONFIG_BOOTCOMMAND	"run bootcmd_net"
 #define	CONFIG_LOADADDR		0x42000000
 #define	CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h
index e852e31..bae4ba0 100644
--- a/include/configs/medcom-wide.h
+++ b/include/configs/medcom-wide.h
@@ -42,6 +42,7 @@
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
 
 #define CONFIG_ENV_IS_NOWHERE
 
@@ -77,6 +78,13 @@
 	"ext2load mmc 0 0x17000000 /boot/uImage;"	\
 	"bootm"
 
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+
 #include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h
new file mode 100644
index 0000000..7983c5d
--- /dev/null
+++ b/include/configs/mx23_olinuxino.h
@@ -0,0 +1,210 @@
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __MX23_OLINUXINO_CONFIG_H__
+#define __MX23_OLINUXINO_CONFIG_H__
+
+/*
+ * SoC configurations
+ */
+#define	CONFIG_MX23				/* i.MX23 SoC */
+#define	CONFIG_MXS_GPIO				/* GPIO control */
+#define	CONFIG_SYS_HZ		1000		/* Ticks per second */
+
+#define	CONFIG_MACH_TYPE	4105
+
+#include <asm/arch/regs-base.h>
+
+#define	CONFIG_SYS_NO_FLASH
+#define	CONFIG_BOARD_EARLY_INIT_F
+#define	CONFIG_ARCH_MISC_INIT
+
+/*
+ * SPL
+ */
+#define	CONFIG_SPL
+#define	CONFIG_SPL_NO_CPU_SUPPORT_CODE
+#define	CONFIG_SPL_START_S_PATH		"arch/arm/cpu/arm926ejs/mxs"
+#define	CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
+#define	CONFIG_SPL_LIBCOMMON_SUPPORT
+#define	CONFIG_SPL_LIBGENERIC_SUPPORT
+#define	CONFIG_SPL_GPIO_SUPPORT
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define	CONFIG_DISPLAY_CPUINFO
+#define	CONFIG_DOS_PARTITION
+
+#define	CONFIG_CMD_CACHE
+#define	CONFIG_CMD_EXT2
+#define	CONFIG_CMD_FAT
+#define	CONFIG_CMD_GPIO
+#define	CONFIG_CMD_MMC
+
+/*
+ * Memory configurations
+ */
+#define	CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define	PHYS_SDRAM_1			0x40000000	/* Base address */
+#define	PHYS_SDRAM_1_SIZE		0x08000000	/* Max 128 MB RAM */
+#define	CONFIG_SYS_MALLOC_LEN		0x00400000	/* 4 MB for malloc */
+#define	CONFIG_SYS_GBL_DATA_SIZE	128		/* Initial data */
+#define	CONFIG_SYS_MEMTEST_START	0x40000000	/* Memtest start adr */
+#define	CONFIG_SYS_MEMTEST_END		0x40400000	/* 4 MB RAM test */
+#define	CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+/* Point initial SP in SRAM so SPL can use it too. */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x00000000
+#define CONFIG_SYS_INIT_RAM_SIZE	(128 * 1024)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+/*
+ * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
+ * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
+ * binary. In case there was more of this mess, 0x100 bytes are skipped.
+ */
+#define	CONFIG_SYS_TEXT_BASE		0x40000100
+
+/*
+ * U-Boot general configurations
+ */
+#define	CONFIG_SYS_LONGHELP
+#define	CONFIG_SYS_PROMPT	"=> "
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
+#define	CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+						/* Print buffer size */
+#define	CONFIG_SYS_MAXARGS	32		/* Max number of command args */
+#define	CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+#define	CONFIG_VERSION_VARIABLE			/* U-BOOT version */
+#define	CONFIG_AUTO_COMPLETE			/* Command auto complete */
+#define	CONFIG_CMDLINE_EDITING			/* Command history etc */
+#define	CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Serial Driver
+ */
+#define	CONFIG_PL011_SERIAL
+#define	CONFIG_PL011_CLOCK		24000000
+#define	CONFIG_PL01x_PORTS		{ (void *)MXS_UARTDBG_BASE }
+#define	CONFIG_CONS_INDEX		0
+#define	CONFIG_BAUDRATE			115200	/* Default baud rate */
+
+/*
+ * MMC Driver
+ */
+#ifdef	CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXS_MMC
+#endif
+
+/*
+ * APBH DMA
+ */
+#define CONFIG_APBH_DMA
+
+/*
+ * Boot Linux
+ */
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+#define	CONFIG_BOOTDELAY	3
+#define	CONFIG_BOOTFILE		"uImage"
+#define	CONFIG_LOADADDR		0x42000000
+#define	CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+#define	CONFIG_OF_LIBFDT
+
+/*
+ * Environment
+ */
+#define	CONFIG_ENV_IS_IN_MMC
+#define	CONFIG_ENV_OVERWRITE
+#ifdef	CONFIG_ENV_IS_IN_MMC
+#define	CONFIG_ENV_OFFSET	(256 * 1024)
+#define	CONFIG_ENV_SIZE	(16 * 1024)
+#define	CONFIG_SYS_MMC_ENV_DEV 0
+#endif
+
+/*
+ * Extra Environments
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"update_sd_firmware_filename=u-boot.sd\0" \
+	"update_sd_firmware="		/* Update the SD firmware partition */ \
+		"if mmc rescan ; then "	\
+		"if tftp ${update_sd_firmware_filename} ; then " \
+		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
+		"setexpr fw_sz ${fw_sz} + 1 ; "	\
+		"mmc write ${loadaddr} 0x800 ${fw_sz} ; " \
+		"fi ; "	\
+		"fi\0" \
+	"script=boot.scr\0"	\
+	"uimage=uImage\0" \
+	"console=ttyAMA0\0" \
+	"fdt_file=imx23-olinuxino.dtb\0" \
+	"fdt_addr=0x41000000\0" \
+	"boot_fdt=try\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rw rootwait\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript="  \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; "	\
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else " \
+				"echo ERR: Fail to boot from MMC; " \
+			"fi; " \
+		"fi; " \
+	"else exit; fi"
+
+#endif /* __MX23_OLINUXINO_CONFIG_H__ */
diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h
new file mode 100644
index 0000000..c44a8b8
--- /dev/null
+++ b/include/configs/mx23evk.h
@@ -0,0 +1,202 @@
+/*
+ * Freescale i.MX23 EVK board config
+ *
+ * Copyright (C) 2013 Otavio Salvador <otavio@ossystems.com.br>
+ * on behalf of O.S. Systems Software LTDA.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+#ifndef __MX23EVK_CONFIG_H__
+#define __MX23EVK_CONFIG_H__
+
+/* SoC configurations */
+#define CONFIG_MX23				/* i.MX23 SoC */
+
+#include <asm/arch/regs-base.h>
+
+#define CONFIG_MXS_GPIO			/* GPIO control */
+#define CONFIG_SYS_HZ		1000		/* Ticks per second */
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX23EVK
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_MISC_INIT
+
+/* SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
+#define CONFIG_SPL_START_S_PATH	"arch/arm/cpu/arm926ejs/mxs"
+#define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+
+/* U-Boot Commands */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_BOOTZ
+
+/* Memory configurations */
+#define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x08000000	/* Max 128 MB RAM */
+#define CONFIG_STACKSIZE		(128 * 1024)	/* 128 KB stack */
+#define CONFIG_SYS_MALLOC_LEN		0x00400000	/* 4 MB for malloc */
+#define CONFIG_SYS_MEMTEST_START	0x40000000	/* Memtest start adr */
+#define CONFIG_SYS_MEMTEST_END		0x40400000	/* 4 MB RAM test */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+/* Point initial SP in SRAM so SPL can use it too. */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x00000000
+#define CONFIG_SYS_INIT_RAM_SIZE	(128 * 1024)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/*
+ * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
+ * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
+ * binary. In case there was more of this mess, 0x100 bytes are skipped.
+ */
+#define CONFIG_SYS_TEXT_BASE	0x40000100
+
+#define CONFIG_ENV_OVERWRITE
+
+/* U-Boot general configurations */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT	"=> "
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+						/* Print buffer size */
+#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE	/* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE		/* Command auto complete */
+#define CONFIG_CMDLINE_EDITING		/* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/* Serial Driver */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK		24000000
+#define CONFIG_PL01x_PORTS		{ (void *)MXS_UARTDBG_BASE }
+#define CONFIG_CONS_INDEX		0
+#define CONFIG_BAUDRATE			115200	/* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* DMA */
+#define CONFIG_APBH_DMA
+
+/* MMC Driver */
+#ifdef	CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_MXS_MMC
+#endif
+
+/* Boot Linux */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY	1
+#define CONFIG_BOOTFILE	"uImage"
+#define CONFIG_LOADADDR	0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+#define CONFIG_OF_LIBFDT
+
+/* Environment */
+#define CONFIG_ENV_IS_IN_MMC
+#ifdef CONFIG_ENV_IS_IN_MMC
+ #define CONFIG_ENV_OFFSET	(256 * 1024)
+ #define CONFIG_ENV_SIZE	(16 * 1024)
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+#endif
+
+/* Extra Environments */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"update_sd_firmware_filename=u-boot.sd\0" \
+	"update_sd_firmware="		/* Update the SD firmware partition */ \
+		"if mmc rescan ; then "	\
+		"if tftp ${update_sd_firmware_filename} ; then " \
+		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
+		"setexpr fw_sz ${fw_sz} + 1 ; "	\
+		"mmc write ${loadaddr} 0x800 ${fw_sz} ; " \
+		"fi ; "	\
+		"fi\0" \
+	"script=boot.scr\0"	\
+	"uimage=uImage\0" \
+	"console=ttyAMA0\0" \
+	"fdt_file=imx23-evk.dtb\0" \
+	"fdt_addr=0x41000000\0" \
+	"boot_fdt=try\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rw rootwait\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript="  \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; "	\
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else " \
+				"echo ERR: Fail to boot from MMC; " \
+			"fi; " \
+		"fi; " \
+	"else exit; fi"
+
+#endif /* __MX23EVK_CONFIG_H__ */
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index dd0ef21..71447d9 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -163,7 +163,6 @@
 #define CONFIG_NET_MULTI
 #define CONFIG_ETHPRIME	"FEC0"
 #define CONFIG_FEC_MXC
-#define CONFIG_FEC_MXC_MULTI
 #define CONFIG_MII
 #define CONFIG_FEC_XCV_TYPE	RMII
 #define CONFIG_MX28_FEC_MAC_IN_OCOTP
diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h
index cda4512..d76357c 100644
--- a/include/configs/mx6qsabre_common.h
+++ b/include/configs/mx6qsabre_common.h
@@ -91,7 +91,7 @@
 	"fdt_high=0xffffffff\0"	  \
 	"initrd_high=0xffffffff\0" \
 	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
-	"mmcpart=1\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
 		"root=${mmcroot}\0" \
diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h
index f4a082a..1583c11 100644
--- a/include/configs/mx6qsabreauto.h
+++ b/include/configs/mx6qsabreauto.h
@@ -19,11 +19,23 @@
 #define CONFIG_MMCROOT			"/dev/mmcblk0p2"
 #define PHYS_SDRAM_SIZE		(2u * 1024 * 1024 * 1024)
 
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
 #include "mx6qsabre_common.h"
 
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #if defined(CONFIG_ENV_IS_IN_MMC)
 #define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		1	/* Boot partition 1 */
 #endif
 
 #endif                         /* __MX6QSABREAUTO_CONFIG_H */
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index ca4e724..180cb24 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -157,6 +157,9 @@
 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
 		"source ${loadaddr}\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
 	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 	"mmcboot=echo Booting from mmc${mmcdev} ...; " \
 		"run mmcargs; " \
@@ -164,12 +167,20 @@
 
 #define CONFIG_BOOTCOMMAND \
 	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmcdev};" \
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \
-			"if run loaduimage; then " \
-				"run mmcboot; " \
-			"fi; " \
+			"if run loadbootenv; then " \
+				"run importbootenv; " \
+			"fi;" \
+			"if test -n ${uenvcmd}; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+		"fi;" \
+		"if run loaduimage; then " \
+			"run mmcboot; " \
 		"fi; " \
 	"fi"
 
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index 38c79cf..2edb4aa 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -36,6 +36,7 @@
 #define CONFIG_MACH_TYPE		MACH_TYPE_PAZ00
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -71,6 +72,14 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPP				LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES	10
+
 #include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
new file mode 100644
index 0000000..aa90ba9
--- /dev/null
+++ b/include/configs/pcm051.h
@@ -0,0 +1,301 @@
+/*
+ * pcm051.h
+ *
+ * Phytec phyCORE-AM335x (pcm051) boards information header
+ *
+ * Copyright (C) 2013 Lemonage Software GmbH
+ * Author Lars Poeschel <poeschel@lemonage.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_PCM051_H
+#define __CONFIG_PCM051_H
+
+#define CONFIG_AM33XX
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+
+#define CONFIG_DMA_COHERENT
+#define CONFIG_DMA_COHERENT_SIZE	(1 << 20)
+
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"U-Boot# "
+#define CONFIG_SYS_NO_FLASH
+#define MACH_TYPE_PCM051		4144	/* Until the next sync */
+#define CONFIG_MACH_TYPE		MACH_TYPE_PCM051
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_VERSION_VARIABLE
+
+/* set to negative value for no autoboot */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80007fc0\0" \
+	"fdtaddr=0x80000000\0" \
+	"rdaddr=0x81000000\0" \
+	"bootfile=uImage\0" \
+	"fdtfile=pcm051.dtb\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 ro\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
+	"ramrootfstype=ext2\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${ramroot} " \
+		"rootfstype=${ramrootfstype}\0" \
+	"loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+	"loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+	"loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"ramboot=echo Booting from ramdisk ...; " \
+		"run ramargs; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmcdev};" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run loaduimage; then " \
+			"run mmcboot;" \
+		"fi;" \
+	"fi;" \
+
+/* Clock Defines */
+#define V_OSCK				25000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_CMD_ECHO
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS		16
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*
+ * memtest works on 8 MB in DRAM after skipping 32MB from
+ * start addr of ram disk
+ */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_DRAM_1 + (64 * 1024 * 1024))
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START \
+					+ (8 * 1024 * 1024))
+
+#define CONFIG_SYS_LOAD_ADDR		0x80007fc0 /* Default load address */
+#define CONFIG_SYS_HZ			1000 /* 1ms clock */
+
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_SPI
+#define CONFIG_OMAP3_SPI
+#define CONFIG_MTD_DEVICE
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED		24000000
+
+ /* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1		/*  1 bank of DRAM */
+#define PHYS_DRAM_1			0x80000000	/* DRAM Bank #1 */
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 19)	/* 512MiB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
+						GENERATED_GBL_DATA_SIZE)
+ /* Platform/Board specific defs */
+#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_CONS_INDEX		1
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		(48000000)
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+
+/* I2C Configuration */
+#define CONFIG_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_DRIVER_OMAP24XX_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+#define CONFIG_OMAP_GPIO
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 110, 300, 600, 1200, 2400, \
+4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x402F0400
+#define CONFIG_SPL_MAX_SIZE		(101 * 1024)
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING	"pcm051 U-Boot SPL"
+#define CONFIG_SPL_ETH_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS		0
+#define CONFIG_SPL_SPI_CS		0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
+#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x40000
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80800000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+/* Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/*
+ * USB configuration
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_GADGET
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif
+
+#ifdef CONFIG_MUSB_GADGET
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#endif /* CONFIG_MUSB_GADGET */
+
+/* Unsupported features */
+#undef CONFIG_USE_IRQ
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT         10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR			0
+#define CONFIG_PHY_SMSC
+
+#endif	/* ! __CONFIG_PCM051_H */
diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h
index f807a61..decf8d9 100644
--- a/include/configs/sc_sps_1.h
+++ b/include/configs/sc_sps_1.h
@@ -158,7 +158,6 @@
 #ifdef CONFIG_CMD_NET
 #define CONFIG_ETHPRIME			"FEC0"
 #define CONFIG_FEC_MXC
-#define CONFIG_FEC_MXC_MULTI
 #define CONFIG_MII
 #define CONFIG_FEC_XCV_TYPE		RMII
 #define CONFIG_PHYLIB
diff --git a/include/configs/tec.h b/include/configs/tec.h
index 200cf66..caeb9cd 100644
--- a/include/configs/tec.h
+++ b/include/configs/tec.h
@@ -36,13 +36,13 @@
 /* High-level configuration options */
 #define V_PROMPT			"Tegra20 (TEC) # "
 #define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Tamonten Evaluation Carrier"
-#define CONFIG_SYS_BOARD_ODMDATA	0x2b0d8011
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTD	/* UARTD: debug UART */
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -85,6 +85,13 @@
 	"ext2load mmc 0 0x17000000 /boot/uImage;"	\
 	"bootm"
 
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+
 #include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index ee40cc2..f2a70b1 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -119,33 +119,6 @@
 
 #endif
 
-/*
- * Memory layout for where various images get loaded by boot scripts:
- *
- * scriptaddr can be pretty much anywhere that doesn't conflict with something
- *   else. Put it above BOOTMAPSZ to eliminate conflicts.
- *
- * kernel_addr_r must be within the first 128M of RAM in order for the
- *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
- *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
- *   should not overlap that area, or the kernel will have to copy itself
- *   somewhere else before decompression. Similarly, the address of any other
- *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
- *   this up to 16M allows for a sizable kernel to be decompressed below the
- *   compressed load address.
- *
- * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
- *   the compressed kernel to be up to 16M too.
- *
- * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
- *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
- */
-#define MEM_LAYOUT_ENV_SETTINGS \
-	"scriptaddr=0x10000000\0" \
-	"kernel_addr_r=0x01000000\0" \
-	"fdt_addr_r=0x02000000\0" \
-	"ramdisk_addr_r=0x02100000\0" \
-
 #ifdef CONFIG_TEGRA_KEYBOARD
 #define STDIN_KBD_KBC ",tegra-kbc"
 #else
@@ -160,10 +133,17 @@
 #define STDIN_KBD_USB ""
 #endif
 
+#ifdef CONFIG_VIDEO_TEGRA
+#define STDOUT_LCD ",lcd"
+#else
+#define STDOUT_LCD ""
+#endif
+
 #define TEGRA_DEVICE_SETTINGS \
 	"stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB "\0" \
-	"stdout=serial,lcd\0" \
-	"stderr=serial,lcd\0" \
+	"stdout=serial" STDOUT_LCD "\0" \
+	"stderr=serial" STDOUT_LCD "\0" \
+	""
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	TEGRA_DEVICE_SETTINGS \
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
new file mode 100644
index 0000000..4a656bb
--- /dev/null
+++ b/include/configs/tegra-common.h
@@ -0,0 +1,160 @@
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __TEGRA_COMMON_H
+#define __TEGRA_COMMON_H
+#include <asm/sizes.h>
+#include <linux/stringify.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA9		/* This is an ARM V7 CPU core */
+#define CONFIG_TEGRA			/* which is a Tegra generic machine */
+#define CONFIG_SYS_L2CACHE_OFF		/* No L2 cache */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+#include <asm/arch/tegra.h>		/* get chip and board defs */
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_OF_LIBFDT		/* enable passing of devicetree */
+
+/* Environment */
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_SIZE			0x2000	/* Total Size Environment */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* 4MB  */
+
+/*
+ * PllX Configuration
+ */
+#define CONFIG_SYS_CPU_OSC_FREQUENCY	1000000	/* Set CPU clock to 1GHz */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX	1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+
+/* include default commands */
+#include <config_cmd_default.h>
+
+/* remove unused commands */
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA		/* FPGA configuration support */
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NFS		/* NFS support */
+#undef CONFIG_CMD_NET		/* network support */
+
+/* turn on command-line edit/hist/auto */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_COMMAND_HISTORY
+#define CONFIG_AUTO_COMPLETE
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_BOOTDELAY	2		/* -1 to disable auto boot */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		V_PROMPT
+/*
+ * Increasing the size of the IO buffer as default nfsargs size is more
+ *  than 256 and so it is not possible to edit it
+ */
+#define CONFIG_SYS_CBSIZE		(256 * 2) /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START	(NV_PA_SDRC_CS0 + 0x600000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x100000)
+
+#define CONFIG_SYS_HZ			1000
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		NV_PA_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512M */
+
+#define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* 256M */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_STACKBASE
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+						CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_TEGRA_GPIO
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_ENTERRCM
+#define CONFIG_CMD_BOOTZ
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_MAX_SIZE		(CONFIG_SYS_TEXT_BASE - \
+						CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00010000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+
+#endif /* _TEGRA_COMMON_H_ */
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
new file mode 100644
index 0000000..0033530
--- /dev/null
+++ b/include/configs/tegra114-common.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_COMMON_H_
+#define _TEGRA114_COMMON_H_
+#include "tegra-common.h"
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_TEGRA114			/* in a NVidia Tegra114 core */
+
+/* Environment information, boards can override if required */
+#define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x80A00800	/* default */
+#define CONFIG_STACKBASE	0x82800000	/* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_SYS_TEXT_BASE	0x8010E000
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ *   the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x90000000\0" \
+	"kernel_addr_r=0x81000000\0" \
+	"fdt_addr_r=0x82000000\0" \
+	"ramdisk_addr_r=0x82100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE		0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80090000
+#define CONFIG_SPL_STACK		0x800ffffc
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/tegra114/u-boot-spl.lds"
+
+#endif /* _TEGRA114_COMMON_H_ */
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index fe07f72..33e5f52 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -21,81 +21,82 @@
  * MA 02111-1307 USA
  */
 
-#ifndef __TEGRA20_COMMON_H
-#define __TEGRA20_COMMON_H
-#include <asm/sizes.h>
-#include <linux/stringify.h>
+#ifndef _TEGRA20_COMMON_H_
+#define _TEGRA20_COMMON_H_
+#include "tegra-common.h"
 
 /*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		216000000	/* 216MHz (pllp_out0) */
+
+/*
  * High Level Configuration Options
  */
-#define CONFIG_ARMCORTEXA9		/* This is an ARM V7 CPU core */
-#define CONFIG_TEGRA20			/* in a NVidia Tegra20 core */
-#define CONFIG_TEGRA			/* which is a Tegra generic machine */
-#define CONFIG_SYS_L2CACHE_OFF		/* No L2 cache */
+#define CONFIG_TEGRA20				/* in a NVidia Tegra20 core */
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
+/* Environment information, boards can override if required */
+#define CONFIG_LOADADDR		0x00408000	/* def. location for kernel */
 
-#include <asm/arch/tegra.h>		/* get chip and board defs */
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x00A00800	/* default */
+#define CONFIG_STACKBASE	0x02800000	/* 40MB */
 
-/* Align LCD to 1MB boundary */
-#define CONFIG_LCD_ALIGNMENT	MMU_SECTION_SIZE
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_SYS_TEXT_BASE	0x0010E000
 
 /*
- * Display CPU and Board information
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ *   the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x10000000\0" \
+	"kernel_addr_r=0x01000000\0" \
+	"fdt_addr_r=0x02000000\0" \
+	"ramdisk_addr_r=0x02100000\0"
 
-#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
-#define CONFIG_OF_LIBFDT		/* enable passing of devicetree */
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE		0x00108000
+#define CONFIG_SYS_SPL_MALLOC_START	0x00090000
+#define CONFIG_SPL_STACK		0x000ffffc
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/tegra20/u-boot-spl.lds"
+
+/* Align LCD to 1MB boundary */
+#define CONFIG_LCD_ALIGNMENT	MMU_SECTION_SIZE
 
 #ifdef CONFIG_TEGRA_LP0
 #define TEGRA_LP0_ADDR			0x1C406000
 #define TEGRA_LP0_SIZE			0x2000
 #define TEGRA_LP0_VEC \
-	"lp0_vec=" __stringify(TEGRA_LP0_SIZE)	\
+	"lp0_vec=" __stringify(TEGRA_LP0_SIZE)  \
 	"@" __stringify(TEGRA_LP0_ADDR) " "
 #else
 #define TEGRA_LP0_VEC
 #endif
 
-/* Environment */
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_ENV_SIZE			0x2000	/* Total Size Environment */
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* 4MB  */
-
-/*
- * PllX Configuration
- */
-#define CONFIG_SYS_CPU_OSC_FREQUENCY	1000000	/* Set CPU clock to 1GHz */
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK			216000000	/* 216MHz (pllp_out0) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
-
 /*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX	1
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
-					115200}
-
-/*
  * This parameter affects a TXFILLTUNING field that controls how much data is
  * sent to the latency fifo before it is sent to the wire. Without this
  * parameter, the default (2) causes occasional Data Buffer Errors in OUT
@@ -107,105 +108,13 @@
 /* Total I2C ports on Tegra20 */
 #define TEGRA_I2C_NUM_CONTROLLERS	4
 
-/* include default commands */
-#include <config_cmd_default.h>
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_CMD_PART
 
-/* remove unused commands */
-#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA		/* FPGA configuration support */
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_NFS		/* NFS support */
-#undef CONFIG_CMD_NET		/* network support */
-
-/* turn on command-line edit/hist/auto */
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_COMMAND_HISTORY
-#define CONFIG_AUTO_COMPLETE
-
-#define CONFIG_SYS_NO_FLASH
-
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-#define CONFIG_LOADADDR		0x408000	/* def. location for kernel */
-#define CONFIG_BOOTDELAY	2		/* -1 to disable auto boot */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT		V_PROMPT
-/*
- * Increasing the size of the IO buffer as default nfsargs size is more
- *  than 256 and so it is not possible to edit it
- */
-#define CONFIG_SYS_CBSIZE		(256 * 2) /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
-
-#define CONFIG_SYS_MEMTEST_START	(NV_PA_SDRC_CS0 + 0x600000)
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x100000)
-
-#define CONFIG_SYS_LOAD_ADDR		(0xA00800)	/* default */
-#define CONFIG_SYS_HZ			1000
-
-#define CONFIG_STACKBASE	0x2800000	/* 40MB */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1
-#define PHYS_SDRAM_1		NV_PA_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512M */
-
-#define CONFIG_SYS_TEXT_BASE	0x0010c000
-#define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
-
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* 256M */
-
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_STACKBASE
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-						CONFIG_SYS_INIT_RAM_SIZE - \
-						GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_TEGRA_GPIO
-#define CONFIG_CMD_GPIO
-#define CONFIG_CMD_ENTERRCM
-#define CONFIG_CMD_BOOTZ
-
-/* Defines for SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_RAM_DEVICE
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_TEXT_BASE		0x00108000
-#define CONFIG_SPL_MAX_SIZE		(CONFIG_SYS_TEXT_BASE - \
-						CONFIG_SPL_TEXT_BASE)
-#define CONFIG_SYS_SPL_MALLOC_START	0x00090000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00010000
-#define CONFIG_SPL_STACK		0x000ffffc
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/tegra20/u-boot-spl.lds"
-
 #define CONFIG_SYS_NAND_SELF_INIT
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 
 /* Misc utility code */
 #define CONFIG_BOUNCE_BUFFER
 
-#endif /* __TEGRA20_COMMON_H */
+#endif /* _TEGRA20_COMMON_H_ */
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
new file mode 100644
index 0000000..04517e1
--- /dev/null
+++ b/include/configs/tegra30-common.h
@@ -0,0 +1,89 @@
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA30_COMMON_H_
+#define _TEGRA30_COMMON_H_
+#include "tegra-common.h"
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_TEGRA30			/* in a NVidia Tegra30 core */
+
+/* Environment information, boards can override if required */
+#define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x80A00800	/* default */
+#define CONFIG_STACKBASE	0x82800000	/* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_SYS_TEXT_BASE	0x8010E000
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ *   the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x90000000\0" \
+	"kernel_addr_r=0x81000000\0" \
+	"fdt_addr_r=0x82000000\0" \
+	"ramdisk_addr_r=0x82100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE		0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80090000
+#define CONFIG_SPL_STACK		0x800ffffc
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/tegra30/u-boot-spl.lds"
+
+/* Total I2C ports on Tegra30 */
+#define TEGRA_I2C_NUM_CONTROLLERS	5
+
+#endif /* _TEGRA30_COMMON_H_ */
diff --git a/include/fdt.h b/include/fdt.h
index c51212e..f9612ed 100644
--- a/include/fdt.h
+++ b/include/fdt.h
@@ -4,45 +4,45 @@
 #ifndef __ASSEMBLY__
 
 struct fdt_header {
-	uint32_t magic;			 /* magic word FDT_MAGIC */
-	uint32_t totalsize;		 /* total size of DT block */
-	uint32_t off_dt_struct;		 /* offset to structure */
-	uint32_t off_dt_strings;	 /* offset to strings */
-	uint32_t off_mem_rsvmap;	 /* offset to memory reserve map */
-	uint32_t version;		 /* format version */
-	uint32_t last_comp_version;	 /* last compatible version */
+	fdt32_t magic;			 /* magic word FDT_MAGIC */
+	fdt32_t totalsize;		 /* total size of DT block */
+	fdt32_t off_dt_struct;		 /* offset to structure */
+	fdt32_t off_dt_strings;		 /* offset to strings */
+	fdt32_t off_mem_rsvmap;		 /* offset to memory reserve map */
+	fdt32_t version;		 /* format version */
+	fdt32_t last_comp_version;	 /* last compatible version */
 
 	/* version 2 fields below */
-	uint32_t boot_cpuid_phys;	 /* Which physical CPU id we're
+	fdt32_t boot_cpuid_phys;	 /* Which physical CPU id we're
 					    booting on */
 	/* version 3 fields below */
-	uint32_t size_dt_strings;	 /* size of the strings block */
+	fdt32_t size_dt_strings;	 /* size of the strings block */
 
 	/* version 17 fields below */
-	uint32_t size_dt_struct;	 /* size of the structure block */
+	fdt32_t size_dt_struct;		 /* size of the structure block */
 };
 
 struct fdt_reserve_entry {
-	uint64_t address;
-	uint64_t size;
+	fdt64_t address;
+	fdt64_t size;
 };
 
 struct fdt_node_header {
-	uint32_t tag;
+	fdt32_t tag;
 	char name[0];
 };
 
 struct fdt_property {
-	uint32_t tag;
-	uint32_t len;
-	uint32_t nameoff;
+	fdt32_t tag;
+	fdt32_t len;
+	fdt32_t nameoff;
 	char data[0];
 };
 
 #endif /* !__ASSEMBLY */
 
 #define FDT_MAGIC	0xd00dfeed	/* 4: version, 4: total size */
-#define FDT_TAGSIZE	sizeof(uint32_t)
+#define FDT_TAGSIZE	sizeof(fdt32_t)
 
 #define FDT_BEGIN_NODE	0x1		/* Start node: full name */
 #define FDT_END_NODE	0x2		/* End node */
@@ -51,11 +51,11 @@
 #define FDT_NOP		0x4		/* nop */
 #define FDT_END		0x9
 
-#define FDT_V1_SIZE	(7*sizeof(uint32_t))
-#define FDT_V2_SIZE	(FDT_V1_SIZE + sizeof(uint32_t))
-#define FDT_V3_SIZE	(FDT_V2_SIZE + sizeof(uint32_t))
+#define FDT_V1_SIZE	(7*sizeof(fdt32_t))
+#define FDT_V2_SIZE	(FDT_V1_SIZE + sizeof(fdt32_t))
+#define FDT_V3_SIZE	(FDT_V2_SIZE + sizeof(fdt32_t))
 #define FDT_V16_SIZE	FDT_V3_SIZE
-#define FDT_V17_SIZE	(FDT_V16_SIZE + sizeof(uint32_t))
+#define FDT_V17_SIZE	(FDT_V16_SIZE + sizeof(fdt32_t))
 
 /* adding a ramdisk needs 0x44 bytes in version 2008.10 */
 #define FDT_RAMDISK_OVERHEAD	0x80
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 4b9f84a..2cccc35 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -26,7 +26,7 @@
 
 #ifdef CONFIG_OF_LIBFDT
 
-#include <fdt.h>
+#include <libfdt.h>
 
 u32 fdt_getprop_u32_default(const void *fdt, const char *path,
 				const char *prop, const u32 dflt);
@@ -92,7 +92,7 @@
 
 void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size);
 void fdt_del_node_and_alias(void *blob, const char *alias);
-u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr);
+u64 fdt_translate_address(void *blob, int node_offset, const __be32 *in_addr);
 int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
 					phys_addr_t compat_off);
 int fdt_alloc_phandle(void *blob);
diff --git a/include/fdtdec.h b/include/fdtdec.h
index f77d195..77f244f 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -70,6 +70,8 @@
 	COMPAT_NVIDIA_TEGRA20_NAND,	/* Tegra2 NAND controller */
 	COMPAT_NVIDIA_TEGRA20_PWM,	/* Tegra 2 PWM controller */
 	COMPAT_NVIDIA_TEGRA20_DC,	/* Tegra 2 Display controller */
+	COMPAT_NVIDIA_TEGRA20_SFLASH,	/* Tegra 2 SPI flash controller */
+	COMPAT_NVIDIA_TEGRA20_SLINK,	/* Tegra 2 SPI SLINK controller */
 	COMPAT_SMSC_LAN9215,		/* SMSC 10/100 Ethernet LAN9215 */
 	COMPAT_SAMSUNG_EXYNOS5_SROMC,	/* Exynos5 SROMC */
 	COMPAT_SAMSUNG_S3C2440_I2C,	/* Exynos I2C Controller */
diff --git a/include/image.h b/include/image.h
index f5adc50..8e285f9 100644
--- a/include/image.h
+++ b/include/image.h
@@ -52,7 +52,6 @@
 #endif /* USE_HOSTCC */
 
 #if defined(CONFIG_FIT)
-#include <fdt.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 #define CONFIG_MD5		/* FIT images need MD5 support */
diff --git a/include/libfdt.h b/include/libfdt.h
index c93ae28..fc7f75b 100644
--- a/include/libfdt.h
+++ b/include/libfdt.h
@@ -882,8 +882,8 @@
 static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset,
 					  const char *name, uint32_t val)
 {
-	val = cpu_to_fdt32(val);
-	return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val));
+	fdt32_t tmp = cpu_to_fdt32(val);
+	return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp));
 }
 
 /**
@@ -917,8 +917,8 @@
 static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset,
 					  const char *name, uint64_t val)
 {
-	val = cpu_to_fdt64(val);
-	return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val));
+	fdt64_t tmp = cpu_to_fdt64(val);
+	return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp));
 }
 
 /**
@@ -993,13 +993,13 @@
 int fdt_property(void *fdt, const char *name, const void *val, int len);
 static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val)
 {
-	val = cpu_to_fdt32(val);
-	return fdt_property(fdt, name, &val, sizeof(val));
+	fdt32_t tmp = cpu_to_fdt32(val);
+	return fdt_property(fdt, name, &tmp, sizeof(tmp));
 }
 static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val)
 {
-	val = cpu_to_fdt64(val);
-	return fdt_property(fdt, name, &val, sizeof(val));
+	fdt64_t tmp = cpu_to_fdt64(val);
+	return fdt_property(fdt, name, &tmp, sizeof(tmp));
 }
 static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val)
 {
@@ -1154,8 +1154,8 @@
 static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name,
 				  uint32_t val)
 {
-	val = cpu_to_fdt32(val);
-	return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val));
+	fdt32_t tmp = cpu_to_fdt32(val);
+	return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
 }
 
 /**
@@ -1189,8 +1189,8 @@
 static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name,
 				  uint64_t val)
 {
-	val = cpu_to_fdt64(val);
-	return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val));
+	fdt64_t tmp = cpu_to_fdt64(val);
+	return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
 }
 
 /**
@@ -1296,8 +1296,8 @@
 static inline int fdt_appendprop_u32(void *fdt, int nodeoffset,
 				     const char *name, uint32_t val)
 {
-	val = cpu_to_fdt32(val);
-	return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val));
+	fdt32_t tmp = cpu_to_fdt32(val);
+	return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
 }
 
 /**
@@ -1331,8 +1331,8 @@
 static inline int fdt_appendprop_u64(void *fdt, int nodeoffset,
 				     const char *name, uint64_t val)
 {
-	val = cpu_to_fdt64(val);
-	return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val));
+	fdt64_t tmp = cpu_to_fdt64(val);
+	return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
 }
 
 /**
diff --git a/include/libfdt_env.h b/include/libfdt_env.h
index bf63583..3e3defc 100644
--- a/include/libfdt_env.h
+++ b/include/libfdt_env.h
@@ -22,9 +22,14 @@
 #define _LIBFDT_ENV_H
 
 #include "compiler.h"
+#include "linux/types.h"
 
 extern struct fdt_header *working_fdt;  /* Pointer to the working fdt */
 
+typedef __be16 fdt16_t;
+typedef __be32 fdt32_t;
+typedef __be64 fdt64_t;
+
 #define fdt32_to_cpu(x)		be32_to_cpu(x)
 #define cpu_to_fdt32(x)		cpu_to_be32(x)
 #define fdt64_to_cpu(x)		be64_to_cpu(x)
diff --git a/include/netdev.h b/include/netdev.h
index 7f158d4..fd3e243 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -215,9 +215,16 @@
 int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
 #endif /* CONFIG_MV88E61XX_SWITCH */
 
+struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id);
+#ifdef CONFIG_PHYLIB
+struct phy_device;
+int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
+		struct mii_dev *bus, struct phy_device *phydev);
+#else
 /*
  * Allow FEC to fine-tune MII configuration on boards which require this.
  */
 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int));
+#endif
 
 #endif /* _NETDEV_H_ */
diff --git a/include/phy.h b/include/phy.h
index 3c30f11..58ca273 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -199,6 +199,9 @@
 
 int phy_init(void);
 int phy_reset(struct phy_device *phydev);
+struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
+		phy_interface_t interface);
+void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
 struct phy_device *phy_connect(struct mii_dev *bus, int addr,
 				struct eth_device *dev,
 				phy_interface_t interface);
diff --git a/include/serial.h b/include/serial.h
index 14f863e..f6bb2b9 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -32,7 +32,7 @@
 	defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
 	defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
 	defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
-	defined(CONFIG_TEGRA20) || defined(CONFIG_SYS_COREBOOT) || \
+	defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \
 	defined(CONFIG_MICROBLAZE)
 extern struct serial_device serial0_device;
 extern struct serial_device serial1_device;
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 16921e1..3ae348d 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -45,6 +45,8 @@
 	COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
 	COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
 	COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
+	COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"),
+	COMPAT(NVIDIA_TEGRA20_SLINK, "nvidia,tegra20-slink"),
 	COMPAT(SMSC_LAN9215, "smsc,lan9215"),
 	COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),
 	COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"),
diff --git a/lib/libfdt/fdt.c b/lib/libfdt/fdt.c
index 4157b21..387e354 100644
--- a/lib/libfdt/fdt.c
+++ b/lib/libfdt/fdt.c
@@ -96,7 +96,7 @@
 
 uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset)
 {
-	const uint32_t *tagp, *lenp;
+	const fdt32_t *tagp, *lenp;
 	uint32_t tag;
 	int offset = startoffset;
 	const char *p;
diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c
index 1933010..1a461c3 100644
--- a/lib/libfdt/fdt_ro.c
+++ b/lib/libfdt/fdt_ro.c
@@ -326,7 +326,7 @@
 
 uint32_t fdt_get_phandle(const void *fdt, int nodeoffset)
 {
-	const uint32_t *php;
+	const fdt32_t *php;
 	int len;
 
 	/* FIXME: This is a bit sub-optimal, since we potentially scan
diff --git a/lib/libfdt/fdt_rw.c b/lib/libfdt/fdt_rw.c
index 5ed23d6..aba6094 100644
--- a/lib/libfdt/fdt_rw.c
+++ b/lib/libfdt/fdt_rw.c
@@ -343,7 +343,7 @@
 	int nodelen;
 	int err;
 	uint32_t tag;
-	uint32_t *endtag;
+	fdt32_t *endtag;
 
 	FDT_RW_CHECK_HEADER(fdt);
 
@@ -370,7 +370,7 @@
 	nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE);
 	memset(nh->name, 0, FDT_TAGALIGN(namelen+1));
 	memcpy(nh->name, name, namelen);
-	endtag = (uint32_t *)((char *)nh + nodelen - FDT_TAGSIZE);
+	endtag = (fdt32_t *)((char *)nh + nodelen - FDT_TAGSIZE);
 	*endtag = cpu_to_fdt32(FDT_END_NODE);
 
 	return offset;
diff --git a/lib/libfdt/fdt_sw.c b/lib/libfdt/fdt_sw.c
index 55ebebf..f422754 100644
--- a/lib/libfdt/fdt_sw.c
+++ b/lib/libfdt/fdt_sw.c
@@ -153,7 +153,7 @@
 
 int fdt_end_node(void *fdt)
 {
-	uint32_t *en;
+	fdt32_t *en;
 
 	FDT_SW_CHECK_HEADER(fdt);
 
@@ -213,7 +213,7 @@
 int fdt_finish(void *fdt)
 {
 	char *p = (char *)fdt;
-	uint32_t *end;
+	fdt32_t *end;
 	int oldstroffset, newstroffset;
 	uint32_t tag;
 	int offset, nextoffset;
diff --git a/lib/libfdt/fdt_wip.c b/lib/libfdt/fdt_wip.c
index e373677..63e67b7 100644
--- a/lib/libfdt/fdt_wip.c
+++ b/lib/libfdt/fdt_wip.c
@@ -78,7 +78,7 @@
 
 static void _fdt_nop_region(void *start, int len)
 {
-	uint32_t *p;
+	fdt32_t *p;
 
 	for (p = start; (char *)p < ((char *)start + len); p++)
 		*p = cpu_to_fdt32(FDT_NOP);
diff --git a/spl/Makefile b/spl/Makefile
index 6dbb105..101d478 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -86,7 +86,7 @@
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
-ifeq ($(SOC),tegra20)
+ifneq ($(CONFIG_TEGRA),)
 LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
 LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
 LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
@@ -141,11 +141,8 @@
 	$(OBJTREE)/tools/mkimage -T omapimage -n byteswap \
 		-a $(CONFIG_SPL_TEXT_BASE) -d $< $@
 
-ifneq ($(CONFIG_IMX_CONFIG),)
-$(OBJTREE)/SPL:	$(obj)u-boot-spl.bin
-	$(OBJTREE)/tools/mkimage -n  $(SRCTREE)/$(CONFIG_IMX_CONFIG) -T imximage \
-		-e $(CONFIG_SPL_TEXT_BASE) -d $< $@
-endif
+$(OBJTREE)/SPL : $(obj)u-boot-spl.bin depend
+		$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $@
 
 ALL-y	+= $(obj)u-boot-spl.bin
 
diff --git a/tools/Makefile b/tools/Makefile
index 686840a..c5952fc 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -69,6 +69,7 @@
 BIN_FILES-y += mkenvimage$(SFX)
 BIN_FILES-y += mkimage$(SFX)
 BIN_FILES-$(CONFIG_SMDK5250) += mksmdk5250spl$(SFX)
+BIN_FILES-$(CONFIG_MX23) += mxsboot$(SFX)
 BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
 BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
 BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
@@ -98,6 +99,7 @@
 NOPED_OBJ_FILES-y += mkenvimage.o
 NOPED_OBJ_FILES-y += mkimage.o
 OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o
+OBJ_FILES-$(CONFIG_MX23) += mxsboot.o
 OBJ_FILES-$(CONFIG_MX28) += mxsboot.o
 OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
 NOPED_OBJ_FILES-y += os_support.o
diff --git a/tools/fdt_host.h b/tools/fdt_host.h
index 085013e..b08bf86 100644
--- a/tools/fdt_host.h
+++ b/tools/fdt_host.h
@@ -21,7 +21,6 @@
 #define __FDT_HOST_H__
 
 /* Make sure to include u-boot version of libfdt include files */
-#include "../include/fdt.h"
 #include "../include/libfdt.h"
 #include "../include/fdt_support.h"
 
diff --git a/tools/imls/imls.c b/tools/imls/imls.c
index b21c505..a982a13 100644
--- a/tools/imls/imls.c
+++ b/tools/imls/imls.c
@@ -38,7 +38,6 @@
 #endif
 
 #include <sha1.h>
-#include <fdt.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <image.h>
diff --git a/tools/imximage.c b/tools/imximage.c
index a93d7eb..fa308c9 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -551,7 +551,7 @@
  * imximage parameters
  */
 static struct image_type_params imximage_params = {
-	.name		= "Freescale i.MX 5x Boot Image support",
+	.name		= "Freescale i.MX Boot Image support",
 	.header_size	= sizeof(struct imx_header),
 	.hdr		= (void *)&imximage_header,
 	.check_image_type = imximage_check_image_types,
diff --git a/tools/patman/README b/tools/patman/README
index dc3957c..1832ebd 100644
--- a/tools/patman/README
+++ b/tools/patman/README
@@ -43,6 +43,9 @@
 
 in one of your commits, the series will be sent there.
 
+In Linux this will also call get_maintainer.pl on each of your
+patches automatically.
+
 
 How to use this tool
 ====================
@@ -65,8 +68,12 @@
 How to configure it
 ===================
 
+For most cases of using patman for U-Boot developement patman will
+locate and use the file 'doc/git-mailrc' in your U-Boot directory.
+This contains most of the aliases you will need.
+
-For most cases patman will locate and use the file 'doc/git-mailrc' in
-your U-Boot directory. This contains most of the aliases you will need.
+For Linux the 'scripts/get_maintainer.pl' handles figuring out where
+to send patches pretty well.
 
 During the first run patman creates a config file for you by taking the default
 user name and email address from the global .gitconfig file.
@@ -90,6 +97,35 @@
 The checkpatch.pl in the U-Boot tools/ subdirectory will be located and
 used. Failing that you can put it into your path or ~/bin/checkpatch.pl
 
+
+If you want to change the defaults for patman's command-line arguments,
+you can add a [settings] section to your .patman file.  This can be used
+for any command line option by referring to the "dest" for the option in
+patman.py.  For reference, the useful ones (at the moment) shown below
+(all with the non-default setting):
+
+>>>
+
+[settings]
+ignore_errors: True
+process_tags: False
+verbose: True
+
+<<<
+
+
+If you want to adjust settings (or aliases) that affect just a single
+project you can add a section that looks like [project_settings] or
+[project_alias].  If you want to use tags for your linux work, you could
+do:
+
+>>>
+
+[linux_settings]
+process_tags: True
+
+<<<
+
 
 How to run it
 =============
@@ -226,6 +262,9 @@
 will create a patch which is copied to x86, arm, sandbox, mikef, ag and
 afleming.
 
+If you have a cover letter it will get sent to the union of the CC lists of
+all of the other patches.
+
 
 Example Work Flow
 =================
diff --git a/tools/patman/checkpatch.py b/tools/patman/checkpatch.py
index d831087..d3a0477 100644
--- a/tools/patman/checkpatch.py
+++ b/tools/patman/checkpatch.py
@@ -23,13 +23,16 @@
 import gitutil
 import os
 import re
+import sys
 import terminal
 
 def FindCheckPatch():
+    top_level = gitutil.GetTopLevel()
     try_list = [
         os.getcwd(),
         os.path.join(os.getcwd(), '..', '..'),
-        os.path.join(gitutil.GetTopLevel(), 'tools'),
+        os.path.join(top_level, 'tools'),
+        os.path.join(top_level, 'scripts'),
         '%s/bin' % os.getenv('HOME'),
         ]
     # Look in current dir
@@ -45,8 +48,10 @@
         if os.path.isfile(fname):
             return fname
         path = os.path.dirname(path)
-    print 'Could not find checkpatch.pl'
-    return None
+
+    print >> sys.stderr, ('Cannot find checkpatch.pl - please put it in your ' +
+                '~/bin directory or use --no-check')
+    sys.exit(1)
 
 def CheckPatch(fname, verbose=False):
     """Run checkpatch.pl on a file.
@@ -65,9 +70,6 @@
     error_count, warning_count, lines = 0, 0, 0
     problems = []
     chk = FindCheckPatch()
-    if not chk:
-        raise OSError, ('Cannot find checkpatch.pl - please put it in your ' +
-                '~/bin directory')
     item = {}
     stdout = command.Output(chk, '--no-tree', fname)
     #pipe = subprocess.Popen(cmd, stdout=subprocess.PIPE)
diff --git a/tools/patman/get_maintainer.py b/tools/patman/get_maintainer.py
new file mode 100644
index 0000000..cb11373
--- /dev/null
+++ b/tools/patman/get_maintainer.py
@@ -0,0 +1,63 @@
+# Copyright (c) 2012 The Chromium OS Authors.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+import command
+import gitutil
+import os
+
+def FindGetMaintainer():
+    """Look for the get_maintainer.pl script.
+
+    Returns:
+        If the script is found we'll return a path to it; else None.
+    """
+    try_list = [
+        os.path.join(gitutil.GetTopLevel(), 'scripts'),
+        ]
+    # Look in the list
+    for path in try_list:
+        fname = os.path.join(path, 'get_maintainer.pl')
+        if os.path.isfile(fname):
+            return fname
+
+    return None
+
+def GetMaintainer(fname, verbose=False):
+    """Run get_maintainer.pl on a file if we find it.
+
+    We look for get_maintainer.pl in the 'scripts' directory at the top of
+    git.  If we find it we'll run it.  If we don't find get_maintainer.pl
+    then we fail silently.
+
+    Args:
+        fname: Path to the patch file to run get_maintainer.pl on.
+
+    Returns:
+        A list of email addresses to CC to.
+    """
+    get_maintainer = FindGetMaintainer()
+    if not get_maintainer:
+        if verbose:
+            print "WARNING: Couldn't find get_maintainer.pl"
+        return []
+
+    stdout = command.Output(get_maintainer, '--norolestats', fname)
+    return stdout.splitlines()
diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py
index 72d37a0..ca3ba4a 100644
--- a/tools/patman/gitutil.py
+++ b/tools/patman/gitutil.py
@@ -217,6 +217,10 @@
     Returns:
         Git command that was/would be run
 
+    # For the duration of this doctest pretend that we ran patman with ./patman
+    >>> _old_argv0 = sys.argv[0]
+    >>> sys.argv[0] = './patman'
+
     >>> alias = {}
     >>> alias['fred'] = ['f.bloggs@napier.co.nz']
     >>> alias['john'] = ['j.bloggs@napier.co.nz']
@@ -244,6 +248,9 @@
     'git send-email --annotate --to "f.bloggs@napier.co.nz" --cc \
 "f.bloggs@napier.co.nz" --cc "j.bloggs@napier.co.nz" --cc \
 "m.poppins@cloud.net" --cc-cmd "./patman --cc-cmd cc-fname" cover p1 p2'
+
+    # Restore argv[0] since we clobbered it.
+    >>> sys.argv[0] = _old_argv0
     """
     to = BuildEmailList(series.get('to'), '--to', alias)
     if not to:
@@ -340,8 +347,8 @@
 
     This test makes sure that we are running tests in the right subdir
 
-    >>> os.path.realpath(os.getcwd()) == \
-            os.path.join(GetTopLevel(), 'tools', 'scripts', 'patman')
+    >>> os.path.realpath(os.path.dirname(__file__)) == \
+            os.path.join(GetTopLevel(), 'tools', 'patman')
     True
     """
     return command.OutputOneLine('git', 'rev-parse', '--show-toplevel')
@@ -377,8 +384,6 @@
 
 def Setup():
     """Set up git utils, by reading the alias files."""
-    settings.Setup('')
-
     # Check for a git alias file also
     alias_fname = GetAliasFile()
     if alias_fname:
diff --git a/tools/patman/patman.py b/tools/patman/patman.py
index cfe06d0..e049081 100755
--- a/tools/patman/patman.py
+++ b/tools/patman/patman.py
@@ -34,6 +34,8 @@
 import command
 import gitutil
 import patchstream
+import project
+import settings
 import terminal
 import test
 
@@ -48,6 +50,9 @@
        help='Send patches email even if patch errors are found')
 parser.add_option('-n', '--dry-run', action='store_true', dest='dry_run',
        default=False, help="Do a try run (create but don't email patches)")
+parser.add_option('-p', '--project', default=project.DetectProject(),
+                  help="Project name; affects default option values and "
+                  "aliases [default: %default]")
 parser.add_option('-s', '--start', dest='start', type='int',
        default=0, help='Commit to start creating patches from (0 = HEAD)')
 parser.add_option('-t', '--test', action='store_true', dest='test',
@@ -56,6 +61,9 @@
        default=False, help='Verbose output of errors and warnings')
 parser.add_option('--cc-cmd', dest='cc_cmd', type='string', action='store',
        default=None, help='Output cc list for patch file (used by git)')
+parser.add_option('--no-check', action='store_false', dest='check_patch',
+                  default=True,
+                  help="Don't check for patch compliance")
 parser.add_option('--no-tags', action='store_false', dest='process_tags',
                   default=True, help="Don't process subject tags as aliaes")
 
@@ -64,6 +72,11 @@
 Create patches from commits in a branch, check them and email them as
 specified by tags you place in the commits. Use -n to """
 
+
+# Parse options twice: first to get the project and second to handle
+# defaults properly (which depends on project).
+(options, args) = parser.parse_args()
+settings.Setup(parser, options.project, '')
 (options, args) = parser.parse_args()
 
 # Run our meagre tests
@@ -75,8 +88,9 @@
     result = unittest.TestResult()
     suite.run(result)
 
-    suite = doctest.DocTestSuite('gitutil')
-    suite.run(result)
+    for module in ['gitutil', 'settings']:
+        suite = doctest.DocTestSuite(module)
+        suite.run(result)
 
     # TODO: Surely we can just 'print' result?
     print result
@@ -135,19 +149,24 @@
     series.DoChecks()
 
     # Check the patches, and run them through 'git am' just to be sure
-    ok = checkpatch.CheckPatches(options.verbose, args)
+    if options.check_patch:
+        ok = checkpatch.CheckPatches(options.verbose, args)
+    else:
+        ok = True
     if not gitutil.ApplyPatches(options.verbose, args,
             options.count + options.start):
         ok = False
 
+    cc_file = series.MakeCcFile(options.process_tags, cover_fname)
+
     # Email the patches out (giving the user time to check / cancel)
     cmd = ''
     if ok or options.ignore_errors:
-        cc_file = series.MakeCcFile(options.process_tags)
         cmd = gitutil.EmailPatches(series, cover_fname, args,
                 options.dry_run, cc_file)
-        os.remove(cc_file)
 
     # For a dry run, just show our actions as a sanity check
     if options.dry_run:
         series.ShowActions(args, cmd, options.process_tags)
+
+    os.remove(cc_file)
diff --git a/tools/patman/project.py b/tools/patman/project.py
new file mode 100644
index 0000000..4f7b2b3
--- /dev/null
+++ b/tools/patman/project.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2012 The Chromium OS Authors.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+import os.path
+
+import gitutil
+
+def DetectProject():
+    """Autodetect the name of the current project.
+
+    This looks for signature files/directories that are unlikely to exist except
+    in the given project.
+
+    Returns:
+        The name of the project, like "linux" or "u-boot".  Returns "unknown"
+        if we can't detect the project.
+    """
+    top_level = gitutil.GetTopLevel()
+
+    if os.path.exists(os.path.join(top_level, "include", "u-boot")):
+        return "u-boot"
+    elif os.path.exists(os.path.join(top_level, "kernel")):
+        return "linux"
+
+    return "unknown"
diff --git a/tools/patman/series.py b/tools/patman/series.py
index d2971f4..6c5c570 100644
--- a/tools/patman/series.py
+++ b/tools/patman/series.py
@@ -19,8 +19,10 @@
 # MA 02111-1307 USA
 #
 
+import itertools
 import os
 
+import get_maintainer
 import gitutil
 import terminal
 
@@ -46,6 +48,11 @@
         self.notes = []
         self.changes = {}
 
+        # Written in MakeCcFile()
+        #  key: name of patch file
+        #  value: list of email addresses
+        self._generated_cc = {}
+
     # These make us more like a dictionary
     def __setattr__(self, name, value):
         self[name] = value
@@ -109,10 +116,7 @@
         for upto in range(len(args)):
             commit = self.commits[upto]
             print col.Color(col.GREEN, '   %s' % args[upto])
-            cc_list = []
-            if process_tags:
-                cc_list += gitutil.BuildEmailList(commit.tags)
-            cc_list += gitutil.BuildEmailList(commit.cc_list)
+            cc_list = list(self._generated_cc[commit.patch])
 
             # Skip items in To list
             if 'to' in self:
@@ -136,6 +140,9 @@
         print 'Prefix:\t ', self.get('prefix')
         if self.cover:
             print 'Cover: %d lines' % len(self.cover)
+            all_ccs = itertools.chain(*self._generated_cc.values())
+            for email in set(all_ccs):
+                    print '      Cc: ',email
         if cmd:
             print 'Git command: %s' % cmd
 
@@ -199,23 +206,33 @@
             str = 'Change log exists, but no version is set'
             print col.Color(col.RED, str)
 
-    def MakeCcFile(self, process_tags):
+    def MakeCcFile(self, process_tags, cover_fname):
         """Make a cc file for us to use for per-commit Cc automation
 
+        Also stores in self._generated_cc to make ShowActions() faster.
+
         Args:
             process_tags: Process tags as if they were aliases
+            cover_fname: If non-None the name of the cover letter.
         Return:
             Filename of temp file created
         """
         # Look for commit tags (of the form 'xxx:' at the start of the subject)
         fname = '/tmp/patman.%d' % os.getpid()
         fd = open(fname, 'w')
+        all_ccs = []
         for commit in self.commits:
             list = []
             if process_tags:
                 list += gitutil.BuildEmailList(commit.tags)
             list += gitutil.BuildEmailList(commit.cc_list)
+            list += get_maintainer.GetMaintainer(commit.patch)
+            all_ccs += list
             print >>fd, commit.patch, ', '.join(list)
+            self._generated_cc[commit.patch] = list
+
+        if cover_fname:
+            print >>fd, cover_fname, ', '.join(set(all_ccs))
 
         fd.close()
         return fname
diff --git a/tools/patman/settings.py b/tools/patman/settings.py
index 4dda17b..084d1b8 100644
--- a/tools/patman/settings.py
+++ b/tools/patman/settings.py
@@ -26,6 +26,140 @@
 import command
 import gitutil
 
+"""Default settings per-project.
+
+These are used by _ProjectConfigParser.  Settings names should match
+the "dest" of the option parser from patman.py.
+"""
+_default_settings = {
+    "u-boot": {},
+    "linux": {
+        "process_tags": "False",
+    }
+}
+
+class _ProjectConfigParser(ConfigParser.SafeConfigParser):
+    """ConfigParser that handles projects.
+
+    There are two main goals of this class:
+    - Load project-specific default settings.
+    - Merge general default settings/aliases with project-specific ones.
+
+    # Sample config used for tests below...
+    >>> import StringIO
+    >>> sample_config = '''
+    ... [alias]
+    ... me: Peter P. <likesspiders@example.com>
+    ... enemies: Evil <evil@example.com>
+    ...
+    ... [sm_alias]
+    ... enemies: Green G. <ugly@example.com>
+    ...
+    ... [sm2_alias]
+    ... enemies: Doc O. <pus@example.com>
+    ...
+    ... [settings]
+    ... am_hero: True
+    ... '''
+
+    # Check to make sure that bogus project gets general alias.
+    >>> config = _ProjectConfigParser("zzz")
+    >>> config.readfp(StringIO.StringIO(sample_config))
+    >>> config.get("alias", "enemies")
+    'Evil <evil@example.com>'
+
+    # Check to make sure that alias gets overridden by project.
+    >>> config = _ProjectConfigParser("sm")
+    >>> config.readfp(StringIO.StringIO(sample_config))
+    >>> config.get("alias", "enemies")
+    'Green G. <ugly@example.com>'
+
+    # Check to make sure that settings get merged with project.
+    >>> config = _ProjectConfigParser("linux")
+    >>> config.readfp(StringIO.StringIO(sample_config))
+    >>> sorted(config.items("settings"))
+    [('am_hero', 'True'), ('process_tags', 'False')]
+
+    # Check to make sure that settings works with unknown project.
+    >>> config = _ProjectConfigParser("unknown")
+    >>> config.readfp(StringIO.StringIO(sample_config))
+    >>> sorted(config.items("settings"))
+    [('am_hero', 'True')]
+    """
+    def __init__(self, project_name):
+        """Construct _ProjectConfigParser.
+
+        In addition to standard SafeConfigParser initialization, this also loads
+        project defaults.
+
+        Args:
+            project_name: The name of the project.
+        """
+        self._project_name = project_name
+        ConfigParser.SafeConfigParser.__init__(self)
+
+        # Update the project settings in the config based on
+        # the _default_settings global.
+        project_settings = "%s_settings" % project_name
+        if not self.has_section(project_settings):
+            self.add_section(project_settings)
+        project_defaults = _default_settings.get(project_name, {})
+        for setting_name, setting_value in project_defaults.iteritems():
+            self.set(project_settings, setting_name, setting_value)
+
+    def get(self, section, option, *args, **kwargs):
+        """Extend SafeConfigParser to try project_section before section.
+
+        Args:
+            See SafeConfigParser.
+        Returns:
+            See SafeConfigParser.
+        """
+        try:
+            return ConfigParser.SafeConfigParser.get(
+                self, "%s_%s" % (self._project_name, section), option,
+                *args, **kwargs
+            )
+        except (ConfigParser.NoSectionError, ConfigParser.NoOptionError):
+            return ConfigParser.SafeConfigParser.get(
+                self, section, option, *args, **kwargs
+            )
+
+    def items(self, section, *args, **kwargs):
+        """Extend SafeConfigParser to add project_section to section.
+
+        Args:
+            See SafeConfigParser.
+        Returns:
+            See SafeConfigParser.
+        """
+        project_items = []
+        has_project_section = False
+        top_items = []
+
+        # Get items from the project section
+        try:
+            project_items = ConfigParser.SafeConfigParser.items(
+                self, "%s_%s" % (self._project_name, section), *args, **kwargs
+            )
+            has_project_section = True
+        except ConfigParser.NoSectionError:
+            pass
+
+        # Get top-level items
+        try:
+            top_items = ConfigParser.SafeConfigParser.items(
+                self, section, *args, **kwargs
+            )
+        except ConfigParser.NoSectionError:
+            # If neither section exists raise the error on...
+            if not has_project_section:
+                raise
+
+        item_dict = dict(top_items)
+        item_dict.update(project_items)
+        return item_dict.items()
+
 def ReadGitAliases(fname):
     """Read a git alias file. This is in the form used by git:
 
@@ -88,13 +222,45 @@
     print >>f, "[alias]\nme: %s <%s>" % (name, email)
     f.close();
 
+def _UpdateDefaults(parser, config):
+    """Update the given OptionParser defaults based on config.
+
-def Setup(config_fname=''):
+    We'll walk through all of the settings from the parser
+    For each setting we'll look for a default in the option parser.
+    If it's found we'll update the option parser default.
+
+    The idea here is that the .patman file should be able to update
+    defaults but that command line flags should still have the final
+    say.
+
+    Args:
+        parser: An instance of an OptionParser whose defaults will be
+            updated.
+        config: An instance of _ProjectConfigParser that we will query
+            for settings.
+    """
+    defaults = parser.get_default_values()
+    for name, val in config.items('settings'):
+        if hasattr(defaults, name):
+            default_val = getattr(defaults, name)
+            if isinstance(default_val, bool):
+                val = config.getboolean('settings', name)
+            elif isinstance(default_val, int):
+                val = config.getint('settings', name)
+            parser.set_default(name, val)
+        else:
+            print "WARNING: Unknown setting %s" % name
+
+def Setup(parser, project_name, config_fname=''):
     """Set up the settings module by reading config files.
 
     Args:
+        parser:         The parser to update
+        project_name:   Name of project that we're working on; we'll look
+            for sections named "project_section" as well.
         config_fname:   Config filename to read ('' for default)
     """
-    settings = ConfigParser.SafeConfigParser()
+    config = _ProjectConfigParser(project_name)
     if config_fname == '':
         config_fname = '%s/.patman' % os.getenv('HOME')
 
@@ -102,11 +268,17 @@
         print "No config file found ~/.patman\nCreating one...\n"
         CreatePatmanConfigFile(config_fname)
 
-    settings.read(config_fname)
+    config.read(config_fname)
 
-    for name, value in settings.items('alias'):
+    for name, value in config.items('alias'):
         alias[name] = value.split(',')
 
+    _UpdateDefaults(parser, config)
 
 # These are the aliases we understand, indexed by alias. Each member is a list.
 alias = {}
+
+if __name__ == "__main__":
+    import doctest
+
+    doctest.testmod()
diff --git a/tools/patman/test.py b/tools/patman/test.py
index cf42480..f801ced 100644
--- a/tools/patman/test.py
+++ b/tools/patman/test.py
@@ -119,8 +119,8 @@
 --- a/README
 +++ b/README
 @@ -2026,6 +2026,17 @@ The following options need to be configured:
-		example, some LED's) on your board. At the moment,
-		the following checkpoints are implemented:
+ 		example, some LED's) on your board. At the moment,
+ 		the following checkpoints are implemented:
 
 +- Time boot progress
 +		CONFIG_BOOTSTAGE
@@ -134,7 +134,7 @@
 +		You can add calls to bootstage_mark() to set time markers.
 +
  - Standalone program support:
-		CONFIG_STANDALONE_LOAD_ADDR
+ 		CONFIG_STANDALONE_LOAD_ADDR
 
 diff --git a/common/bootstage.c b/common/bootstage.c
 new file mode 100644