ppc4xx: Big cleanup of PPC4xx defines
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:
- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines
Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index e9861ab..2287904 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -64,7 +64,7 @@
static int pci_async_enabled(void)
{
#if defined(CONFIG_405GP)
- return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
+ return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN);
#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
@@ -72,7 +72,7 @@
defined(CONFIG_460EX) || defined(CONFIG_460GT)
unsigned long val;
- mfsdr(sdr_sdstp1, val);
+ mfsdr(SDR0_SDSTP1, val);
return (val & SDR0_SDSTP1_PAME_MASK);
#endif
}
@@ -84,21 +84,21 @@
static int pci_arbiter_enabled(void)
{
#if defined(CONFIG_405GP)
- return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
+ return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
#endif
#if defined(CONFIG_405EP)
- return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
+ return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN);
#endif
#if defined(CONFIG_440GP)
- return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
+ return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK);
#endif
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
unsigned long val;
- mfsdr(sdr_xcr, val);
+ mfsdr(SDR0_XCR, val);
return (val & 0x80000000);
#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
@@ -106,7 +106,7 @@
defined(CONFIG_460EX) || defined(CONFIG_460GT)
unsigned long val;
- mfsdr(sdr_pci0, val);
+ mfsdr(SDR0_PCI0, val);
return (val & 0x80000000);
#endif
}
@@ -118,11 +118,11 @@
static int i2c_bootrom_enabled(void)
{
#if defined(CONFIG_405EP)
- return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
+ return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP);
#else
unsigned long val;
- mfsdr(sdr_sdcs, val);
+ mfsdr(SDR0_SDCS0, val);
return (val & SDR0_SDCS_SDD);
#endif
}
@@ -256,7 +256,7 @@
{
unsigned long val;
- mfsdr(SDR_PINSTP, val);
+ mfsdr(SDR0_PINSTP, val);
return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
}
#endif /* SDR0_PINSTP_SHIFT */
@@ -265,13 +265,13 @@
#if defined(CONFIG_440)
static int do_chip_reset (unsigned long sys0, unsigned long sys1)
{
- /* Changes to cpc0_sys0 and cpc0_sys1 require chip
+ /* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
* reset.
*/
- mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
- mtdcr (cpc0_sys0, sys0);
- mtdcr (cpc0_sys1, sys1);
- mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
+ mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */
+ mtdcr (CPC0_SYS0, sys0);
+ mtdcr (CPC0_SYS1, sys1);
+ mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */
mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */
return 1;
@@ -410,13 +410,13 @@
case PVR_440GP_RB:
puts("GP Rev. B");
/* See errata 1.12: CHIP_4 */
- if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
- (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
+ if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
+ (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
puts ( "\n\t CPC0_SYSx DCRs corrupted. "
"Resetting chip ...\n");
udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
- do_chip_reset ( mfdcr(cpc0_strp0),
- mfdcr(cpc0_strp1) );
+ do_chip_reset ( mfdcr(CPC0_STRP0),
+ mfdcr(CPC0_STRP1) );
}
break;