diff --git a/board/ronetix/pm9261/led.c b/board/ronetix/pm9261/led.c
index 396c3e7..ff21ce6 100644
--- a/board/ronetix/pm9261/led.c
+++ b/board/ronetix/pm9261/led.c
@@ -26,19 +26,21 @@
 #include <common.h>
 #include <asm/arch/at91sam9261.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
 #include <asm/arch/io.h>
 
 void coloured_LED_init(void)
 {
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
 	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
+	writel(1 << AT91SAM9261_ID_PIOC, &pmc->pcer);
 
-	at91_set_gpio_output(CONFIG_RED_LED, 1);
-	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
-	at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+	at91_set_pio_output(CONFIG_RED_LED, 1);
+	at91_set_pio_output(CONFIG_GREEN_LED, 1);
+	at91_set_pio_output(CONFIG_YELLOW_LED, 1);
 
-	at91_set_gpio_value(CONFIG_RED_LED, 0);
-	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
-	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+	at91_set_pio_value(CONFIG_RED_LED, 0);
+	at91_set_pio_value(CONFIG_GREEN_LED, 1);
+	at91_set_pio_value(CONFIG_YELLOW_LED, 1);
 }
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index 8662339..53d8c48 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c
@@ -27,13 +27,14 @@
 #include <common.h>
 #include <asm/sizes.h>
 #include <asm/arch/at91sam9261.h>
-#include <asm/arch/at91sam9261_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
 #include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
 #include <asm/arch/io.h>
 #include <asm/arch/hardware.h>
 #include <lcd.h>
@@ -55,39 +56,48 @@
 static void pm9261_nand_hw_init(void)
 {
 	unsigned long csa;
+	at91_smc_t 	*smc 	= (at91_smc_t *) AT91_SMC_BASE;
+	at91_matrix_t 	*matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
 
 	/* Enable CS3 */
-	csa = at91_sys_read(AT91_MATRIX_EBICSA);
-	at91_sys_write(AT91_MATRIX_EBICSA,
-		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+	csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa);
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
-	at91_sys_write(AT91_SMC_SETUP(3),
-		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC_PULSE(3),
-		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
-		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
-	at91_sys_write(AT91_SMC_CYCLE(3),
-		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
-	at91_sys_write(AT91_SMC_MODE(3),
-		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		       AT91_SMC_EXNWMODE_DISABLE |
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
 #ifdef CONFIG_SYS_NAND_DBW_16
-		       AT91_SMC_DBW_16 |
+		AT91_SMC_MODE_DBW_16 |
 #else /* CONFIG_SYS_NAND_DBW_8 */
-		       AT91_SMC_DBW_8 |
+		AT91_SMC_MODE_DBW_8 |
 #endif
-		       AT91_SMC_TDF_(2));
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
+
+	writel(1 << AT91SAM9261_ID_PIOA |
+		1 << AT91SAM9261_ID_PIOC,
+		&pmc->pcer);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(AT91_PIN_PA16, 1);
+	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(AT91_PIN_PC14, 1);
+	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 
-	at91_set_A_periph(AT91_PIN_PC0, 0);	/* NANDOE */
-	at91_set_A_periph(AT91_PIN_PC1, 0);	/* NANDWE */
+	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* NANDOE */
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* NANDWE */
 }
 #endif
 
@@ -95,23 +105,30 @@
 #ifdef CONFIG_DRIVER_DM9000
 static void pm9261_dm9000_hw_init(void)
 {
+	at91_smc_t 	*smc 	= (at91_smc_t *) AT91_SMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
 	/* Configure SMC CS2 for DM9000 */
-	at91_sys_write(AT91_SMC_SETUP(2),
-		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC_PULSE(2),
-		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
-		       AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
-	at91_sys_write(AT91_SMC_CYCLE(2),
-		       AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
-	at91_sys_write(AT91_SMC_MODE(2),
-		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		       AT91_SMC_EXNWMODE_DISABLE |
-		       AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
-		       AT91_SMC_TDF_(1));
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[2].setup);
+
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
+		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
+		&smc->cs[2].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
+		&smc->cs[2].cycle);
+
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+		AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+		AT91_SMC_MODE_TDF_CYCLE(1),
+		&smc->cs[2].mode);
 
 	/* Configure Interrupt pin as input, no pull-up */
-	at91_set_gpio_input(AT91_PIN_PA24, 0);
+	writel(1 << AT91SAM9261_ID_PIOA, &pmc->pcer);
+	at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
 }
 #endif
 
@@ -135,40 +152,42 @@
 
 void lcd_enable(void)
 {
-	at91_set_gpio_value(AT91_PIN_PA22, 0);  /* power up */
+	at91_set_pio_value(AT91_PIO_PORTA, 22, 0);  /* power up */
 }
 
 void lcd_disable(void)
 {
-	at91_set_gpio_value(AT91_PIN_PA22, 1);  /* power down */
+	at91_set_pio_value(AT91_PIO_PORTA, 22, 1);  /* power down */
 }
 
 static void pm9261_lcd_hw_init(void)
 {
-	at91_set_A_periph(AT91_PIN_PB1, 0);	/* LCDHSYNC */
-	at91_set_A_periph(AT91_PIN_PB2, 0);	/* LCDDOTCK */
-	at91_set_A_periph(AT91_PIN_PB3, 0);	/* LCDDEN */
-	at91_set_A_periph(AT91_PIN_PB4, 0);	/* LCDCC */
-	at91_set_A_periph(AT91_PIN_PB7, 0);	/* LCDD2 */
-	at91_set_A_periph(AT91_PIN_PB8, 0);	/* LCDD3 */
-	at91_set_A_periph(AT91_PIN_PB9, 0);	/* LCDD4 */
-	at91_set_A_periph(AT91_PIN_PB10, 0);	/* LCDD5 */
-	at91_set_A_periph(AT91_PIN_PB11, 0);	/* LCDD6 */
-	at91_set_A_periph(AT91_PIN_PB12, 0);	/* LCDD7 */
-	at91_set_A_periph(AT91_PIN_PB15, 0);	/* LCDD10 */
-	at91_set_A_periph(AT91_PIN_PB16, 0);	/* LCDD11 */
-	at91_set_A_periph(AT91_PIN_PB17, 0);	/* LCDD12 */
-	at91_set_A_periph(AT91_PIN_PB18, 0);	/* LCDD13 */
-	at91_set_A_periph(AT91_PIN_PB19, 0);	/* LCDD14 */
-	at91_set_A_periph(AT91_PIN_PB20, 0);	/* LCDD15 */
-	at91_set_B_periph(AT91_PIN_PB23, 0);	/* LCDD18 */
-	at91_set_B_periph(AT91_PIN_PB24, 0);	/* LCDD19 */
-	at91_set_B_periph(AT91_PIN_PB25, 0);	/* LCDD20 */
-	at91_set_B_periph(AT91_PIN_PB26, 0);	/* LCDD21 */
-	at91_set_B_periph(AT91_PIN_PB27, 0);	/* LCDD22 */
-	at91_set_B_periph(AT91_PIN_PB28, 0);	/* LCDD23 */
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
 
-	at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
+	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTB, 3, 0);	/* LCDDEN */
+	at91_set_a_periph(AT91_PIO_PORTB, 4, 0);	/* LCDCC */
+	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTB, 10, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTB, 11, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* LCDD7 */
+	at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* LCDD12 */
+	at91_set_a_periph(AT91_PIO_PORTB, 18, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTB, 19, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTB, 20, 0);	/* LCDD15 */
+	at91_set_b_periph(AT91_PIO_PORTB, 23, 0);	/* LCDD18 */
+	at91_set_b_periph(AT91_PIO_PORTB, 24, 0);	/* LCDD19 */
+	at91_set_b_periph(AT91_PIO_PORTB, 25, 0);	/* LCDD20 */
+	at91_set_b_periph(AT91_PIO_PORTB, 26, 0);	/* LCDD21 */
+	at91_set_b_periph(AT91_PIO_PORTB, 27, 0);	/* LCDD22 */
+	at91_set_b_periph(AT91_PIO_PORTB, 28, 0);	/* LCDD23 */
+
+	writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */
 
 	gd->fb_base = AT91SAM9261_SRAM_BASE;
 }
@@ -222,11 +241,14 @@
 
 int board_init(void)
 {
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
 	/* Enable Ctrlc */
 	console_init_f();
 
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA);
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
+	writel(1 << AT91SAM9261_ID_PIOA |
+		1 << AT91SAM9261_ID_PIOC,
+		&pmc->pcer);
 
 	/* arch number of PM9261-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_PM9261;