// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
 */

/ {
	chosen {
		u-boot,spl-boot-order = &sdmmc;
	};

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		mmc0 = &sdmmc;
		serial1 = &uart1;
		serial2 = &uart2;
		spi0 = &sfc;
	};
};

/* U-Boot clk driver for px30 cannot set GPU_CLK */
&cru {
	u-boot,dm-pre-reloc;
	assigned-clocks = <&cru PLL_NPLL>,
		<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
		<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
		<&cru PCLK_BUS_PRE>, <&cru PLL_CPLL>;

	assigned-clock-rates = <1188000000>,
		<200000000>, <200000000>,
		<150000000>, <150000000>,
		<100000000>, <17000000>;
};

&dmc {
	u-boot,dm-pre-reloc;
};

&gpio0 {
	u-boot,dm-pre-reloc;
};

&gpio1 {
	u-boot,dm-pre-reloc;
};

&gpio2 {
	u-boot,dm-pre-reloc;
};

&gpio3 {
	u-boot,dm-pre-reloc;
};

&grf {
	u-boot,dm-pre-reloc;
};

&pmucru {
	u-boot,dm-pre-reloc;
};

&pmugrf {
	u-boot,dm-pre-reloc;
};

&saradc {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&sdmmc {
	u-boot,dm-pre-reloc;

	/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
	u-boot,spl-fifo-mode;
};

&sfc {
	u-boot,dm-pre-reloc;
};

&{/sfc@ff3a0000/flash@0} {
	u-boot,dm-pre-reloc;
};

&uart1 {
	clock-frequency = <24000000>;
	u-boot,dm-pre-reloc;
};

&uart2 {
	clock-frequency = <24000000>;
	u-boot,dm-pre-reloc;
};

&xin24m {
	u-boot,dm-pre-reloc;
};