ARM: socfpga: Reorder Arria10 SPL
The Arria10 SPL is a complete mess of calls to functions which are
called in the wrong context and it is surprise it works at all. This
patch tries to clean that mess up by shuffling the function calls
around and moving the calls into the correct context. Due to the
delicate nature of the reordering, this is done in one huge patch.
The following changes happen in this patch:
- Security policy init and NIC301 happens first in board_init_f()
- The clock init happens very early in board_init_f() in SPL only
- arch_early_init_r() only registers the FPGA, just like on Gen5
- arch_early_init_r() is never called from any _f() function
- Dedicated FPGA pins are inited in board_init_f() as on Gen5
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index 284e076..f347ae8 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -28,17 +28,14 @@
#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
+static struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
#if defined(CONFIG_SPL_BUILD)
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
(void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
-#endif
-
-static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-#if defined(CONFIG_SPL_BUILD)
/*
+ * This function initializes security policies to be consistent across
+ * all logic units in the Arria 10.
@@ -46,7 +43,7 @@
+ * The idea is to set all security policies to be normal, nonsecure
+ * for all units.
+ */
-static void initialize_security_policies(void)
+void socfpga_init_security_policies(void)
{
/* Put OCRAM in non-secure */
writel(0x003f0000, &noc_fw_ocram_base->region0);
@@ -66,24 +63,20 @@
writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set);
}
-int arch_early_init_r(void)
+void socfpga_sdram_remap_zero(void)
{
- initialize_security_policies();
-
/* Configure the L2 controller to make SDRAM start at 0 */
writel(0x1, &pl310->pl310_addr_filter_start);
-
- /* assert reset to all except L4WD0 and L4TIMER0 */
- socfpga_per_reset_all();
-
- return 0;
}
-#else
+#endif
+
int arch_early_init_r(void)
{
+ /* Add device descriptor to FPGA device table */
+ socfpga_fpga_add();
+
return 0;
}
-#endif
/*
* Print CPU information